change log for rtems (2011-11-08)
rtems-vc at rtems.org
rtems-vc at rtems.org
Tue Nov 8 11:10:31 UTC 2011
*sh*:
2011-11-08 Sebastian Huber <sebastian.huber at embedded-brains.de>
* make/custom/mpc5566evb_spe.cfg, make/custom/mpc5674fevb_spe.cfg,
startup/linkcmds.mpc5566evb_spe, startup/linkcmds.mpc5674fevb_spe,
startup/reset.c: New files.
* Makefile.am, preinstall.am: Reflect changes above.
* startup/early-init.c: Added missing section attribute.
* configure.ac, network/smsc9218i.c: New BSP options
SMSC9218I_EDMA_RX_CHANNEL and SMSC9218I_EDMA_TX_CHANNEL. Enable reset
at cleanup.
M 1.72 c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog
M 1.29 c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am
M 1.20 c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac
A 1.1 c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/mpc5566evb_spe.cfg
A 1.1 c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/mpc5674fevb_spe.cfg
M 1.10 c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c
M 1.13 c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am
M 1.2 c/src/lib/libbsp/powerpc/mpc55xxevb/startup/early-init.c
A 1.1 c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.mpc5566evb_spe
A 1.1 c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.mpc5674fevb_spe
A 1.1 c/src/lib/libbsp/powerpc/mpc55xxevb/startup/reset.c
diff -u rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog:1.71 rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog:1.72
--- rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog:1.71 Wed Aug 31 11:03:09 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog Tue Nov 8 04:13:31 2011
@@ -1,3 +1,14 @@
+2011-11-08 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * make/custom/mpc5566evb_spe.cfg, make/custom/mpc5674fevb_spe.cfg,
+ startup/linkcmds.mpc5566evb_spe, startup/linkcmds.mpc5674fevb_spe,
+ startup/reset.c: New files.
+ * Makefile.am, preinstall.am: Reflect changes above.
+ * startup/early-init.c: Added missing section attribute.
+ * configure.ac, network/smsc9218i.c: New BSP options
+ SMSC9218I_EDMA_RX_CHANNEL and SMSC9218I_EDMA_TX_CHANNEL. Enable reset
+ at cleanup.
+
2011-08-31 Sebastian Huber <sebastian.huber at embedded-brains.de>
* startup/bspgetworkarea.c, startup/linkcmds.base: Removed files.
diff -u rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am:1.28 rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am:1.29
--- rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am:1.28 Wed Aug 31 11:03:09 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am Tue Nov 8 04:13:31 2011
@@ -27,7 +27,9 @@
dist_project_lib_DATA += ../shared/startup/linkcmds.base
dist_project_lib_DATA += startup/linkcmds.gwlcfm
dist_project_lib_DATA += startup/linkcmds.mpc5566evb
+dist_project_lib_DATA += startup/linkcmds.mpc5566evb_spe
dist_project_lib_DATA += startup/linkcmds.mpc5674fevb
+dist_project_lib_DATA += startup/linkcmds.mpc5674fevb_spe
dist_project_lib_DATA += startup/linkcmds.phycore_mpc5554
noinst_LIBRARIES += libbsp.a
@@ -70,6 +72,7 @@
libbsp_a_SOURCES += startup/mmu-config.c
libbsp_a_SOURCES += startup/siu-pcr-config.c
libbsp_a_SOURCES += startup/early-init.c
+libbsp_a_SOURCES += startup/reset.c
# clock
libbsp_a_SOURCES += clock/clock-config.c
diff -u rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac:1.19 rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac:1.20
--- rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac:1.19 Wed Aug 31 11:03:09 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac Tue Nov 8 04:13:31 2011
@@ -24,17 +24,23 @@
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([gwlcfm],[])
-RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5566evb],[1])
-RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5674fevb],[1])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5566evb*],[1])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5674fevb*],[1])
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([gwlcfm],[])
-RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([mpc5566evb],[1])
-RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([mpc5674fevb],[1])
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([mpc5566evb*],[1])
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([mpc5674fevb*],[1])
RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
+RTEMS_BSPOPTS_SET([BSP_INTERRUPT_HANDLER_TABLE_SIZE],[mpc5674fevb*],[255])
+RTEMS_BSPOPTS_SET([BSP_INTERRUPT_HANDLER_TABLE_SIZE],[mpc5566evb*],[127])
+RTEMS_BSPOPTS_SET([BSP_INTERRUPT_HANDLER_TABLE_SIZE],[*],[63])
+RTEMS_BSPOPTS_HELP([BSP_INTERRUPT_HANDLER_TABLE_SIZE],
+[defines the maximum number of interrupt handlers])
+
RTEMS_BSPOPTS_SET([MPC55XX_ESCI_CONSOLE_MINOR],[*],[0])
RTEMS_BSPOPTS_HELP([MPC55XX_ESCI_CONSOLE_MINOR],
[determines which eSCI device will be registered as /dev/console])
@@ -44,26 +50,26 @@
[define to zero or one to disable or enable interrupts for the eSCI devices])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[gwlcfm],[40000000])
-RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[mpc5674fevb],[40000000])
+RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[mpc5674fevb*],[40000000])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[*] ,[8000000])
RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_REF_CLOCK],
[Must be defined to be the external reference clock (in Hz)
for clock generation])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[gwlcfm],[66000000])
-RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[mpc5674fevb],[264000000])
+RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[mpc5674fevb*],[264000000])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[*] ,[128000000])
RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_CLK_OUT],
[Must be defined to be the PLL output clock (in Hz) for clock generation])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[gwlcfm],[10])
-RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[mpc5674fevb],[5])
+RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[mpc5674fevb*],[5])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[*] ,[1])
RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_PREDIV],
[Must be defined to be the PLL predivider factor for clock generation])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[gwlcfm],[99])
-RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[mpc5674fevb],[66])
+RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[mpc5674fevb*],[66])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[*] ,[12])
RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_MFD],
[Must be defined to be the PLL multiplication factor for clock generation])
@@ -81,13 +87,21 @@
RTEMS_BSPOPTS_HELP([SMC91111_ENADDR_IS_SETUP],
[If defined the SMC91111 chip has the ethernet address loaded at reset.])
-RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_EMIOS_CHANNEL],[*],[(MPC55XX_EMIOS_CHANNEL_NUMBER-1)])
+RTEMS_BSPOPTS_SET([SMSC9218I_EDMA_RX_CHANNEL],[*],[49])
+RTEMS_BSPOPTS_HELP([SMSC9218I_EDMA_RX_CHANNEL],
+[receive eDMA channel for SMSC9218I network interface])
+
+RTEMS_BSPOPTS_SET([SMSC9218I_EDMA_TX_CHANNEL],[*],[48])
+RTEMS_BSPOPTS_HELP([SMSC9218I_EDMA_TX_CHANNEL],
+[transmit eDMA channel for SMSC9218I network interface])
+
+RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_EMIOS_CHANNEL],[mpc5674fevb*],[31])
+RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_EMIOS_CHANNEL],[*],[23])
RTEMS_BSPOPTS_HELP([MPC55XX_CLOCK_EMIOS_CHANNEL],
-[Define to the eMIOS channel to use for the BSP clock.
- The default is the last channel.])
+[selects the eMIOS channel for the RTEMS system tick (the default is the last channel)])
-RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5674fevb],[5674])
-RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5566evb],[5566])
+RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5674fevb*],[5674])
+RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5566evb*],[5566])
RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[gwlcfm] ,[5516])
RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[*] ,[5554])
RTEMS_BSPOPTS_HELP([MPC55XX_CHIP_TYPE],
@@ -97,10 +111,10 @@
RTEMS_BSPOPTS_HELP([MPC55XX_BOOTFLAGS],
[if defined, builds in bootflags above the RCHW for setup in a debugger to avoid startup MMU setup])
-RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5674FEVB],[mpc5674fevb],[1])
+RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5674FEVB],[mpc5674fevb*],[1])
RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_MPC5674FEVB],[if defined, use custom settings for MPC5674FEVB board])
-RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5566EVB],[mpc5566evb],[1])
+RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5566EVB],[mpc5566evb*],[1])
RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_MPC5566EVB],[if defined, use custom settings for MPC5566EVB board])
RTEMS_BSPOPTS_SET([MPC55XX_BOARD_GWLCFM],[gwlcfm],[1])
@@ -114,14 +128,10 @@
RTEMS_BSPOPTS_SET([RTEMS_BSP_I2C_EEPROM_DEVICE_PATH],[gwlcfm],['"/dev/i2c1.eeprom"'])
RTEMS_BSPOPTS_HELP([RTEMS_BSP_I2C_EEPROM_DEVICE_PATH],[EEPROM device file path])
-RTEMS_BSPOPTS_SET([BOARD_PHYCORE_MPC5554],[phycore_mpc5554],[1])
-RTEMS_BSPOPTS_HELP([BOARD_PHYCORE_MPC5554],
-[If defined, use custom settings for the Phytec PhyCORE MPC5554 SOM])
-
AC_CONFIG_FILES([Makefile
include/bspopts.h])
-RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
+RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
RTEMS_BSP_LINKCMDS
RTEMS_PPC_EXCEPTIONS
diff -u /dev/null rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/mpc5566evb_spe.cfg:1.1
--- /dev/null Tue Nov 8 05:10:27 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/mpc5566evb_spe.cfg Tue Nov 8 04:13:31 2011
@@ -0,0 +1,3 @@
+CPU_CFLAGS_FLOAT ?= -mspe
+
+include $(RTEMS_ROOT)/make/custom/mpc55xx.inc
diff -u /dev/null rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/mpc5674fevb_spe.cfg:1.1
--- /dev/null Tue Nov 8 05:10:27 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/mpc5674fevb_spe.cfg Tue Nov 8 04:13:31 2011
@@ -0,0 +1,3 @@
+CPU_CFLAGS_FLOAT ?= -mspe
+
+include $(RTEMS_ROOT)/make/custom/mpc55xx.inc
diff -u rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c:1.9 rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c:1.10
--- rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c:1.9 Wed Aug 31 11:03:09 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c Tue Nov 8 04:13:31 2011
@@ -99,14 +99,10 @@
#define SMSC9218I_IRQ_CFG_GLOBAL_DISABLE SMSC9218I_IRQ_CFG_IRQ_TYPE
-#define SMSC9218I_EDMA_RX_CHANNEL 49
-
#define SMSC9218I_EDMA_RX_TCD_CDF 0x10004
#define SMSC9218I_EDMA_RX_TCD_BMF 0x10003
-#define SMSC9218I_EDMA_TX_CHANNEL 48
-
#define SMSC9218I_TCD_BMF_LINK 0x10011
#define SMSC9218I_TCD_BMF_LAST 0x10003
diff -u rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am:1.12 rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am:1.13
--- rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am:1.12 Wed Aug 31 11:03:09 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am Tue Nov 8 04:13:31 2011
@@ -65,10 +65,18 @@
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc5566evb
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc5566evb
+$(PROJECT_LIB)/linkcmds.mpc5566evb_spe: startup/linkcmds.mpc5566evb_spe $(PROJECT_LIB)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc5566evb_spe
+PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc5566evb_spe
+
$(PROJECT_LIB)/linkcmds.mpc5674fevb: startup/linkcmds.mpc5674fevb $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc5674fevb
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc5674fevb
+$(PROJECT_LIB)/linkcmds.mpc5674fevb_spe: startup/linkcmds.mpc5674fevb_spe $(PROJECT_LIB)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc5674fevb_spe
+PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc5674fevb_spe
+
$(PROJECT_LIB)/linkcmds.phycore_mpc5554: startup/linkcmds.phycore_mpc5554 $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.phycore_mpc5554
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.phycore_mpc5554
diff -u rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/early-init.c:1.1 rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/early-init.c:1.2
--- rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/early-init.c:1.1 Wed Aug 31 11:03:09 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/early-init.c Tue Nov 8 04:13:31 2011
@@ -35,7 +35,7 @@
extern uint32_t mpc55xx_bootflag_0 [];
#endif
-static void mpc55xx_siu_init(void)
+static void BSP_START_TEXT_SECTION mpc55xx_siu_init(void)
{
size_t i = 0;
diff -u /dev/null rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.mpc5566evb_spe:1.1
--- /dev/null Tue Nov 8 05:10:28 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.mpc5566evb_spe Tue Nov 8 04:13:31 2011
@@ -0,0 +1 @@
+INCLUDE linkcmds.mpc5566evb
diff -u /dev/null rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.mpc5674fevb_spe:1.1
--- /dev/null Tue Nov 8 05:10:28 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.mpc5674fevb_spe Tue Nov 8 04:13:32 2011
@@ -0,0 +1 @@
+INCLUDE linkcmds.mpc5674fevb
diff -u /dev/null rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/reset.c:1.1
--- /dev/null Tue Nov 8 05:10:28 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/reset.c Tue Nov 8 04:13:32 2011
@@ -0,0 +1,36 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief BSP reset.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
+ */
+
+#include <stdbool.h>
+
+#include <bsp/bootcard.h>
+
+#include <mpc55xx/regs.h>
+
+void bsp_reset(void)
+{
+ while (true) {
+ SIU.SRCR.R = 0x1;
+ }
+}
*sh*:
2011-11-08 Sebastian Huber <sebastian.huber at embedded-brains.de>
* shared/startup/bsp-start-copy-sections.c,
shared/startup/bsp-start-memcpy.S: New files.
* shared/include/start.h: Declare bsp_start_copy_sections().
* shared/start/start.S, shared/include/linker-symbols.h: Moved
content. Support for ARMv7-M.
M 1.94 c/src/lib/libbsp/arm/ChangeLog
M 1.8 c/src/lib/libbsp/arm/shared/include/linker-symbols.h
M 1.6 c/src/lib/libbsp/arm/shared/include/start.h
M 1.13 c/src/lib/libbsp/arm/shared/start/start.S
A 1.1 c/src/lib/libbsp/arm/shared/startup/bsp-start-copy-sections.c
A 1.1 c/src/lib/libbsp/arm/shared/startup/bsp-start-memcpy.S
diff -u rtems/c/src/lib/libbsp/arm/ChangeLog:1.93 rtems/c/src/lib/libbsp/arm/ChangeLog:1.94
--- rtems/c/src/lib/libbsp/arm/ChangeLog:1.93 Sat Sep 24 08:25:45 2011
+++ rtems/c/src/lib/libbsp/arm/ChangeLog Tue Nov 8 04:18:19 2011
@@ -1,3 +1,11 @@
+2011-11-08 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * shared/startup/bsp-start-copy-sections.c,
+ shared/startup/bsp-start-memcpy.S: New files.
+ * shared/include/start.h: Declare bsp_start_copy_sections().
+ * shared/start/start.S, shared/include/linker-symbols.h: Moved
+ content. Support for ARMv7-M.
+
2011-09-24 Sebastian Huber <sebastian.huber at embedded-brains.de>
* acinclude.m4: Added lm3s69xx BSP.
diff -u rtems/c/src/lib/libbsp/arm/shared/include/linker-symbols.h:1.7 rtems/c/src/lib/libbsp/arm/shared/include/linker-symbols.h:1.8
--- rtems/c/src/lib/libbsp/arm/shared/include/linker-symbols.h:1.7 Fri Dec 3 03:23:52 2010
+++ rtems/c/src/lib/libbsp/arm/shared/include/linker-symbols.h Tue Nov 8 04:18:19 2011
@@ -116,6 +116,10 @@
LINKER_SYMBOL(bsp_vector_table_end)
LINKER_SYMBOL(bsp_vector_table_size)
+LINKER_SYMBOL(bsp_start_vector_table_begin)
+LINKER_SYMBOL(bsp_start_vector_table_end)
+LINKER_SYMBOL(bsp_start_vector_table_size)
+
#define BSP_FAST_TEXT_SECTION __attribute__((section(".bsp_fast_text")))
#define BSP_FAST_DATA_SECTION __attribute__((section(".bsp_fast_data")))
diff -u rtems/c/src/lib/libbsp/arm/shared/include/start.h:1.5 rtems/c/src/lib/libbsp/arm/shared/include/start.h:1.6
--- rtems/c/src/lib/libbsp/arm/shared/include/start.h:1.5 Fri Dec 3 03:23:52 2010
+++ rtems/c/src/lib/libbsp/arm/shared/include/start.h Tue Nov 8 04:18:19 2011
@@ -7,12 +7,13 @@
*/
/*
- * Copyright (c) 2008, 2009
- * embedded brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * <rtems at embedded-brains.de>
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -77,6 +78,11 @@
*/
void bsp_start_memcpy_arm(int *dest, const int *src, size_t n);
+/**
+ * @brief Copies all standard sections from the load to the runtime area.
+ */
+void bsp_start_copy_sections(void);
+
/** @} */
#ifdef __cplusplus
diff -u rtems/c/src/lib/libbsp/arm/shared/start/start.S:1.12 rtems/c/src/lib/libbsp/arm/shared/start/start.S:1.13
--- rtems/c/src/lib/libbsp/arm/shared/start/start.S:1.12 Mon Mar 28 03:49:58 2011
+++ rtems/c/src/lib/libbsp/arm/shared/start/start.S Tue Nov 8 04:18:19 2011
@@ -5,15 +5,17 @@
*/
/*
- * Copyright (c) 2008
- * Embedded Brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * rtems at embedded-brains.de
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
- * The license and distribution terms for this file may be found in the file
- * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
*/
#include <rtems/asm.h>
@@ -21,30 +23,34 @@
#include <rtems/score/cpu.h>
#include <bspopts.h>
+#include <bsp/irq.h>
#include <bsp/linker-symbols.h>
-/* External symbols */
-
-.extern bsp_reset
-.extern boot_card
-.extern bsp_start_hook_0
-.extern bsp_start_hook_1
+ /* External symbols */
+ .extern bsp_reset
+ .extern boot_card
+ .extern bsp_start_hook_0
+ .extern bsp_start_hook_1
+
+ /* Global symbols */
+ .globl _start
+ .globl bsp_start_vector_table_begin
+ .globl bsp_start_vector_table_end
+ .globl bsp_start_vector_table_size
+ .globl bsp_vector_table_size
-/* Global symbols */
+ .section ".bsp_start_text", "ax"
-.globl _start
-.globl bsp_start_memcpy
+#if defined(ARM_MULTILIB_ARCH_V4)
-.section ".bsp_start_text", "ax"
-
-.arm
+ .arm
/*
* This is the exception vector table and the pointers to the default
* exceptions handlers.
*/
-vector_block:
+bsp_start_vector_table_begin:
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
@@ -94,6 +100,8 @@
.word reset
+bsp_start_vector_table_end:
+
/* Start entry */
_start:
@@ -169,7 +177,7 @@
*/
ldr r0, =bsp_vector_table_begin
- adr r1, vector_block
+ adr r1, bsp_start_vector_table_begin
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
ldmia r1!, {r2-r9}
@@ -198,64 +206,58 @@
SWITCH_FROM_ARM_TO_THUMB r0
b twiddle
-DEFINE_FUNCTION_ARM(bsp_start_memcpy)
+#elif defined(ARM_MULTILIB_ARCH_V7M)
- /* Return if dest == src */
- cmp r0, r1
-#ifdef __thumb__
- bxeq lr
-#else
- moveq pc, lr
-#endif
+ .syntax unified
- /* Return if length is zero */
- mov r3, #0
- cmp r3, r2
-#ifdef __thumb__
- bxeq lr
-#else
- moveq pc, lr
-#endif
+ .extern bsp_stack_main_end
- /* Save non-volatile registers */
- push {r4-r8, lr}
+ .thumb
- /* Copy worker routine to stack */
- adr ip, bsp_start_memcpy_begin
- ldm ip, {r3-r8}
- push {r3-r8}
-
- /* Execute worker routine */
- mov r3, #0
- mov ip, sp
- mov lr, pc
-#ifdef __thumb__
- bx ip
-#else
- mov pc, ip
-#endif
+bsp_start_vector_table_begin:
+
+ .word bsp_stack_main_end
+ .word _start /* Reset */
+ .word bsp_reset /* NMI */
+ .word bsp_reset /* Hard Fault */
+ .word bsp_reset /* MPU Fault */
+ .word bsp_reset /* Bus Fault */
+ .word bsp_reset /* Usage Fault */
+ .word bsp_reset /* Reserved */
+ .word bsp_reset /* Reserved */
+ .word bsp_reset /* Reserved */
+ .word bsp_reset /* Reserved */
+ .word bsp_reset /* SVC */
+ .word bsp_reset /* Debug Monitor */
+ .word bsp_reset /* Reserved */
+ .word bsp_reset /* PendSV */
+ .word bsp_reset /* SysTick */
+ .rept BSP_INTERRUPT_VECTOR_MAX + 1
+ .word bsp_reset /* IRQ */
+ .endr
- /* Restore stack and non-volatile registers */
- add sp, sp, #24
- pop {r4-r8, lr}
+bsp_start_vector_table_end:
- /* Return */
-#ifdef __thumb__
- bx lr
-#else
- mov pc, lr
-#endif
+ .thumb_func
-bsp_start_memcpy_begin:
+_start:
- /* Worker routine */
- ldr ip, [r1, r3]
- str ip, [r0, r3]
- add r3, r3, #4
- cmp r3, r2
- bcc bsp_start_memcpy_begin
-#ifdef __thumb__
- bx lr
-#else
- mov pc, lr
-#endif
+ ldr sp, =bsp_stack_main_end
+ ldr lr, =bsp_start_hook_0_done + 1
+ b bsp_start_hook_0
+
+bsp_start_hook_0_done:
+
+ bl bsp_start_hook_1
+ movs r0, #0
+ bl boot_card
+
+twiddle:
+
+ bl bsp_reset
+ b twiddle
+
+#endif /* defined(ARM_MULTILIB_ARCH_V7M) */
+
+ .set bsp_start_vector_table_size, bsp_start_vector_table_end - bsp_start_vector_table_begin
+ .set bsp_vector_table_size, bsp_start_vector_table_size
diff -u /dev/null rtems/c/src/lib/libbsp/arm/shared/startup/bsp-start-copy-sections.c:1.1
--- /dev/null Tue Nov 8 05:10:28 2011
+++ rtems/c/src/lib/libbsp/arm/shared/startup/bsp-start-copy-sections.c Tue Nov 8 04:18:19 2011
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp/start.h>
+#include <bsp/linker-symbols.h>
+
+static void BSP_START_TEXT_SECTION bsp_start_clear_bss(void)
+{
+ const int *end = (const int *) bsp_section_bss_end;
+ int *out = (int *) bsp_section_bss_begin;
+
+ /* Clear BSS */
+ while (out != end) {
+ *out = 0;
+ ++out;
+ }
+}
+
+void BSP_START_TEXT_SECTION bsp_start_copy_sections(void)
+{
+ /* Copy .text section */
+ bsp_start_memcpy(
+ (int *) bsp_section_text_begin,
+ (const int *) bsp_section_text_load_begin,
+ (size_t) bsp_section_text_size
+ );
+
+ /* Copy .rodata section */
+ bsp_start_memcpy(
+ (int *) bsp_section_rodata_begin,
+ (const int *) bsp_section_rodata_load_begin,
+ (size_t) bsp_section_rodata_size
+ );
+
+ /* Copy .data section */
+ bsp_start_memcpy(
+ (int *) bsp_section_data_begin,
+ (const int *) bsp_section_data_load_begin,
+ (size_t) bsp_section_data_size
+ );
+
+ /* Copy .fast_text section */
+ bsp_start_memcpy(
+ (int *) bsp_section_fast_text_begin,
+ (const int *) bsp_section_fast_text_load_begin,
+ (size_t) bsp_section_fast_text_size
+ );
+
+ /* Copy .fast_data section */
+ bsp_start_memcpy(
+ (int *) bsp_section_fast_data_begin,
+ (const int *) bsp_section_fast_data_load_begin,
+ (size_t) bsp_section_fast_data_size
+ );
+
+ bsp_start_clear_bss();
+}
diff -u /dev/null rtems/c/src/lib/libbsp/arm/shared/startup/bsp-start-memcpy.S:1.1
--- /dev/null Tue Nov 8 05:10:28 2011
+++ rtems/c/src/lib/libbsp/arm/shared/startup/bsp-start-memcpy.S Tue Nov 8 04:18:19 2011
@@ -0,0 +1,147 @@
+/**
+ * @file
+ *
+ * @brief bsp_start_memcpy() implementation.
+ */
+
+/*
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <rtems/asm.h>
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+
+ .section ".bsp_start_text", "ax"
+
+#if defined(ARM_MULTILIB_ARCH_V4)
+
+DEFINE_FUNCTION_ARM(bsp_start_memcpy)
+
+ /* Return if dest == src */
+ cmp r0, r1
+#ifdef __thumb__
+ bxeq lr
+#else
+ moveq pc, lr
+#endif
+
+ /* Return if length is zero */
+ mov r3, #0
+ cmp r3, r2
+#ifdef __thumb__
+ bxeq lr
+#else
+ moveq pc, lr
+#endif
+
+ /* Save non-volatile registers */
+ push {r4-r8, lr}
+
+ /* Copy worker routine to stack */
+ adr ip, worker_begin
+ ldm ip, {r3-r8}
+ push {r3-r8}
+
+ /* Execute worker routine */
+ mov r3, #0
+ mov ip, sp
+ mov lr, pc
+#ifdef __thumb__
+ bx ip
+#else
+ mov pc, ip
+#endif
+
+ /* Restore stack and non-volatile registers */
+ add sp, sp, #24
+ pop {r4-r8, lr}
+
+ /* Return */
+#ifdef __thumb__
+ bx lr
+#else
+ mov pc, lr
+#endif
+
+worker_begin:
+
+ /* Worker routine */
+ ldr ip, [r1, r3]
+ str ip, [r0, r3]
+ add r3, r3, #4
+ cmp r3, r2
+ bcc worker_begin
+#ifdef __thumb__
+ bx lr
+#else
+ mov pc, lr
+#endif
+
+#elif defined(ARM_MULTILIB_ARCH_V7M)
+
+ .syntax unified
+
+ .align 2
+ .globl bsp_start_memcpy
+ .thumb
+ .thumb_func
+ .type bsp_start_memcpy, %function
+
+bsp_start_memcpy:
+
+ /* Return if dest == src */
+ cmp r0, r1
+ beq return
+
+ /* Return if length is zero */
+ movs r3, #0
+ cmp r3, r2
+ beq return
+
+ /* Save non-volatile registers */
+ push {r4-r7, lr}
+
+ /* Copy worker routine to stack */
+ adr r3, worker_begin
+ ldm r3, {r4-r7}
+ push {r4-r7}
+
+ /* Execute worker routine */
+ add r3, sp, #1
+ adds r2, r2, #3
+ bic r2, r2, #3
+ adds r2, r2, r1
+ blx r3
+
+ /* Restore stack and non-volatile registers */
+ add sp, sp, #16
+ pop {r4-r7, lr}
+
+return:
+
+ /* Return */
+ bx lr
+
+ .align 2
+
+worker_begin:
+
+ /* Worker routine */
+ ldr r3, [r1], #4
+ cmp r2, r1
+ str r3, [r0], #4
+ bne worker_begin
+ bx lr
+
+#endif /* defined(ARM_MULTILIB_ARCH_V7M) */
*sh*:
2011-11-08 Sebastian Huber <sebastian.huber at embedded-brains.de>
* include/lpc17xx.h: New file.
* Makefile.am, preinstall.am: Reflect change above. Update due to API
changes.
* configure.ac, console/console-config.c, include/bsp.h, include/io.h,
include/irq.h, include/lcd.h, include/lpc-clock-config.h,
include/lpc24xx.h, include/start-config.h, irq/irq-dispatch.c,
irq/irq.c, misc/bspidle.c, misc/io.c, misc/lcd.c, misc/restart.c,
misc/system-clocks.c, ssp/ssp.c, startup/bspreset.c,
startup/bspstart.c, startup/bspstarthooks.c,
startup/start-config-emc-dynamic.c, startup/start-config-emc-static.c,
startup/start-config-pinsel.c: Basic support for LPC17XX. New memory
configurations for W9825G2JB75I, IS42S32800B, and SST39VF3201.
M 1.76 c/src/lib/libbsp/arm/lpc24xx/ChangeLog
M 1.39 c/src/lib/libbsp/arm/lpc24xx/Makefile.am
M 1.19 c/src/lib/libbsp/arm/lpc24xx/configure.ac
M 1.9 c/src/lib/libbsp/arm/lpc24xx/console/console-config.c
M 1.11 c/src/lib/libbsp/arm/lpc24xx/include/bsp.h
M 1.6 c/src/lib/libbsp/arm/lpc24xx/include/io.h
M 1.6 c/src/lib/libbsp/arm/lpc24xx/include/irq.h
M 1.3 c/src/lib/libbsp/arm/lpc24xx/include/lcd.h
M 1.2 c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h
A 1.1 c/src/lib/libbsp/arm/lpc24xx/include/lpc17xx.h
M 1.16 c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
M 1.2 c/src/lib/libbsp/arm/lpc24xx/include/start-config.h
M 1.2 c/src/lib/libbsp/arm/lpc24xx/irq/irq-dispatch.c
M 1.8 c/src/lib/libbsp/arm/lpc24xx/irq/irq.c
M 1.4 c/src/lib/libbsp/arm/lpc24xx/misc/bspidle.c
M 1.10 c/src/lib/libbsp/arm/lpc24xx/misc/io.c
M 1.3 c/src/lib/libbsp/arm/lpc24xx/misc/lcd.c
M 1.2 c/src/lib/libbsp/arm/lpc24xx/misc/restart.c
M 1.13 c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c
M 1.24 c/src/lib/libbsp/arm/lpc24xx/preinstall.am
M 1.8 c/src/lib/libbsp/arm/lpc24xx/ssp/ssp.c
M 1.4 c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c
M 1.11 c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c
M 1.11 c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c
M 1.2 c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c
M 1.2 c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-static.c
M 1.2 c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/ChangeLog:1.75 rtems/c/src/lib/libbsp/arm/lpc24xx/ChangeLog:1.76
--- rtems/c/src/lib/libbsp/arm/lpc24xx/ChangeLog:1.75 Mon Nov 7 02:33:14 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/ChangeLog Tue Nov 8 04:39:45 2011
@@ -1,3 +1,18 @@
+2011-11-08 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * include/lpc17xx.h: New file.
+ * Makefile.am, preinstall.am: Reflect change above. Update due to API
+ changes.
+ * configure.ac, console/console-config.c, include/bsp.h, include/io.h,
+ include/irq.h, include/lcd.h, include/lpc-clock-config.h,
+ include/lpc24xx.h, include/start-config.h, irq/irq-dispatch.c,
+ irq/irq.c, misc/bspidle.c, misc/io.c, misc/lcd.c, misc/restart.c,
+ misc/system-clocks.c, ssp/ssp.c, startup/bspreset.c,
+ startup/bspstart.c, startup/bspstarthooks.c,
+ startup/start-config-emc-dynamic.c, startup/start-config-emc-static.c,
+ startup/start-config-pinsel.c: Basic support for LPC17XX. New memory
+ configurations for W9825G2JB75I, IS42S32800B, and SST39VF3201.
+
2011-11-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
* console/console-config.c: Avoid explicit type.
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/Makefile.am:1.38 rtems/c/src/lib/libbsp/arm/lpc24xx/Makefile.am:1.39
--- rtems/c/src/lib/libbsp/arm/lpc24xx/Makefile.am:1.38 Tue Oct 18 13:25:35 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/Makefile.am Tue Nov 8 04:39:45 2011
@@ -44,6 +44,7 @@
include_bsp_HEADERS += include/io.h
include_bsp_HEADERS += include/irq.h
include_bsp_HEADERS += include/lcd.h
+include_bsp_HEADERS += include/lpc17xx.h
include_bsp_HEADERS += include/lpc24xx.h
include_bsp_HEADERS += include/lpc-clock-config.h
include_bsp_HEADERS += include/lpc-ethernet-config.h
@@ -93,12 +94,13 @@
../../shared/gnatinstallhandler.c \
../../shared/sbrk.c \
../../shared/src/stackalloc.c \
- ../../shared/src/uart-output-char.c \
- ../shared/abort/simple_abort.c
+ ../../shared/src/uart-output-char.c
# Startup
-libbsp_a_SOURCES += startup/bspstart.c \
- startup/bspreset.c
+libbsp_a_SOURCES += ../shared/startup/bsp-start-copy-sections.c
+libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S
+libbsp_a_SOURCES += startup/bspreset.c
+libbsp_a_SOURCES += startup/bspstart.c
# IRQ
libbsp_a_SOURCES += ../../shared/src/irq-generic.c \
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/configure.ac:1.18 rtems/c/src/lib/libbsp/arm/lpc24xx/configure.ac:1.19
--- rtems/c/src/lib/libbsp/arm/lpc24xx/configure.ac:1.18 Mon Oct 17 05:39:59 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/configure.ac Tue Nov 8 04:39:46 2011
@@ -32,11 +32,22 @@
RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_RTC],[*],[32768U])
RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_RTC],[RTC oscillator frequency in Hz])
+RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc17*],[120000000U])
+#RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc17*],[96000000U])
+#RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc17*],[48000000U])
RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc23*],[58982400U])
RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc24xx_plx800*],[51612800U])
RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[*],[72000000U])
RTEMS_BSPOPTS_HELP([LPC24XX_CCLK],[CPU clock in Hz])
+RTEMS_BSPOPTS_SET([LPC24XX_PCLKDIV],[lpc17*],[2U])
+RTEMS_BSPOPTS_SET([LPC24XX_PCLKDIV],[*],[1U])
+RTEMS_BSPOPTS_HELP([LPC24XX_PCLKDIV],[peripheral clock divider for default PCLK (PCLK = CCLK / PCLKDIV)])
+
+RTEMS_BSPOPTS_SET([LPC24XX_EMCCLKDIV],[lpc17*],[2U])
+RTEMS_BSPOPTS_SET([LPC24XX_EMCCLKDIV],[*],[1U])
+RTEMS_BSPOPTS_HELP([LPC24XX_EMCCLKDIV],[peripheral clock divider for default EMCCLK (EMCCLK = CCLK / EMCCLKDIV)])
+
RTEMS_BSPOPTS_SET([LPC24XX_UART_BAUD],[*],[115200U])
RTEMS_BSPOPTS_HELP([LPC24XX_UART_BAUD],[baud for UARTs])
@@ -44,15 +55,20 @@
RTEMS_BSPOPTS_SET([LPC24XX_ETHERNET_RMII],[*],[])
RTEMS_BSPOPTS_HELP([LPC24XX_ETHERNET_RMII],[enable RMII for Ethernet])
-RTEMS_BSPOPTS_SET([LPC24XX_EMC_MICRON],[lpc24xx_plx800_rom_*],[1])
-RTEMS_BSPOPTS_SET([LPC24XX_EMC_MICRON],[lpc24xx_ncs_rom_*],[1])
-RTEMS_BSPOPTS_HELP([LPC24XX_EMC_MICRON],[enable Micron configuration for EMC])
+RTEMS_BSPOPTS_SET([LPC24XX_EMC_MT48LC4M16A2],[lpc24xx_ncs_rom_*],[1])
+RTEMS_BSPOPTS_HELP([LPC24XX_EMC_MT48LC4M16A2],[enable Micron MT48LC4M16A2 configuration for EMC])
+
+RTEMS_BSPOPTS_SET([LPC24XX_EMC_W9825G2JB75I],[lpc24xx_plx800_rom_*],[1])
+RTEMS_BSPOPTS_HELP([LPC24XX_EMC_W9825G2JB75I],[enable Winbond W9825G2JB75I configuration for EMC])
+
+RTEMS_BSPOPTS_SET([LPC24XX_EMC_IS42S32800B],[lpc17xx_ea_rom_*],[1])
+RTEMS_BSPOPTS_HELP([LPC24XX_EMC_IS42S32800B],[enable ISSI IS42S32800B configuration for EMC])
-RTEMS_BSPOPTS_SET([LPC24XX_EMC_NUMONYX],[lpc24xx_ncs_rom_*],[1])
-RTEMS_BSPOPTS_HELP([LPC24XX_EMC_NUMONYX],[enable Numonyx configuration for EMC])
+RTEMS_BSPOPTS_SET([LPC24XX_EMC_NUMONYX_M29W160E],[lpc24xx_ncs_rom_*],[1])
+RTEMS_BSPOPTS_HELP([LPC24XX_EMC_NUMONYX_M29W160E],[enable Numonyx M29W160E configuration for EMC])
-RTEMS_BSPOPTS_SET([LPC24XX_EMC_W9825G2JB],[lpc24xx_plx800_rom_*],[1])
-RTEMS_BSPOPTS_HELP([LPC24XX_EMC_W9825G2JB],[enable Winbond W9825G2JB configuration for EMC])
+RTEMS_BSPOPTS_SET([LPC24XX_EMC_SST39VF3201],[lpc24xx_plx800_rom_*],[1])
+RTEMS_BSPOPTS_HELP([LPC24XX_EMC_SST39VF3201],[enable SST39VF3201 configuration for EMC])
RTEMS_BSPOPTS_SET([LPC24XX_EMC_TEST],[*],[])
RTEMS_BSPOPTS_HELP([LPC24XX_EMC_TEST],[enable tests for EMC])
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c:1.8 rtems/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c:1.9
--- rtems/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c:1.8 Mon Nov 7 02:33:14 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c Tue Nov 8 04:39:46 2011
@@ -50,7 +50,7 @@
LPC24XX_PIN_TERMINAL
};
- lpc24xx_module_enable(LPC24XX_MODULE_UART_1, LPC24XX_MODULE_CCLK);
+ lpc24xx_module_enable(LPC24XX_MODULE_UART_1, LPC24XX_MODULE_PCLK_DEFAULT);
lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION);
return true;
@@ -66,7 +66,7 @@
LPC24XX_PIN_TERMINAL
};
- lpc24xx_module_enable(LPC24XX_MODULE_UART_2, LPC24XX_MODULE_CCLK);
+ lpc24xx_module_enable(LPC24XX_MODULE_UART_2, LPC24XX_MODULE_PCLK_DEFAULT);
lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION);
return true;
@@ -82,7 +82,7 @@
LPC24XX_PIN_TERMINAL
};
- lpc24xx_module_enable(LPC24XX_MODULE_UART_3, LPC24XX_MODULE_CCLK);
+ lpc24xx_module_enable(LPC24XX_MODULE_UART_3, LPC24XX_MODULE_PCLK_DEFAULT);
lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION);
return true;
@@ -107,7 +107,7 @@
.setRegister = lpc24xx_uart_set_register,
.getData = NULL,
.setData = NULL,
- .ulClock = LPC24XX_CCLK,
+ .ulClock = LPC24XX_PCLK,
.ulIntVector = LPC24XX_IRQ_UART_0
},
#endif
@@ -128,7 +128,7 @@
.setRegister = lpc24xx_uart_set_register,
.getData = NULL,
.setData = NULL,
- .ulClock = LPC24XX_CCLK,
+ .ulClock = LPC24XX_PCLK,
.ulIntVector = LPC24XX_IRQ_UART_1
},
#endif
@@ -149,7 +149,7 @@
.setRegister = lpc24xx_uart_set_register,
.getData = NULL,
.setData = NULL,
- .ulClock = LPC24XX_CCLK,
+ .ulClock = LPC24XX_PCLK,
.ulIntVector = LPC24XX_IRQ_UART_2
},
#endif
@@ -170,7 +170,7 @@
.setRegister = lpc24xx_uart_set_register,
.getData = NULL,
.setData = NULL,
- .ulClock = LPC24XX_CCLK,
+ .ulClock = LPC24XX_PCLK,
.ulIntVector = LPC24XX_IRQ_UART_3
},
#endif
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h:1.10 rtems/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h:1.11
--- rtems/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h:1.10 Mon Feb 21 06:56:34 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h Tue Nov 8 04:39:46 2011
@@ -7,15 +7,19 @@
*/
/*
- * Copyright (c) 2008
- * Embedded Brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * rtems at embedded-brains.de
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
- * The license and distribution terms for this file may be found in the file
- * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
*/
#ifndef LIBBSP_ARM_LPC24XX_BSP_H
@@ -33,6 +37,10 @@
#define BSP_FEATURE_IRQ_EXTENSION
+#define LPC24XX_PCLK (LPC24XX_CCLK / LPC24XX_PCLKDIV)
+
+#define LPC24XX_EMCCLK (LPC24XX_CCLK / LPC24XX_EMCCLKDIV)
+
#ifndef ASM
struct rtems_bsdnet_ifconfig;
@@ -87,7 +95,11 @@
*/
void *bsp_idle_thread(uintptr_t ignored);
-#define BSP_CONSOLE_UART_BASE 0xe000c000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define BSP_CONSOLE_UART_BASE 0xe000c000
+#else
+ #define BSP_CONSOLE_UART_BASE 0x4000c000
+#endif
void bsp_restart(void *addr);
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/include/io.h:1.5 rtems/c/src/lib/libbsp/arm/lpc24xx/include/io.h:1.6
--- rtems/c/src/lib/libbsp/arm/lpc24xx/include/io.h:1.5 Thu May 19 07:30:00 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/include/io.h Tue Nov 8 04:39:46 2011
@@ -47,14 +47,18 @@
#define LPC24XX_IO_INDEX_BY_PORT(port, bit) (((port) << 5U) + (bit))
-#define LPC24XX_IO_PORT(index) (index >> 5U)
+#define LPC24XX_IO_PORT(index) ((index) >> 5U)
-#define LPC24XX_IO_PORT_BIT(index) (index & 0x1fU)
+#define LPC24XX_IO_PORT_BIT(index) ((index) & 0x1fU)
typedef enum {
- LPC24XX_MODULE_ACF = 0,
- LPC24XX_MODULE_ADC,
- LPC24XX_MODULE_BAT_RAM,
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_ACF,
+ #endif
+ LPC24XX_MODULE_ADC,
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_BAT_RAM,
+ #endif
LPC24XX_MODULE_CAN_0,
LPC24XX_MODULE_CAN_1,
LPC24XX_MODULE_DAC,
@@ -72,7 +76,9 @@
LPC24XX_MODULE_PWM_0,
LPC24XX_MODULE_PWM_1,
LPC24XX_MODULE_RTC,
- LPC24XX_MODULE_SPI,
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_SPI,
+ #endif
LPC24XX_MODULE_SSP_0,
LPC24XX_MODULE_SSP_1,
LPC24XX_MODULE_SYSCON,
@@ -84,16 +90,16 @@
LPC24XX_MODULE_UART_1,
LPC24XX_MODULE_UART_2,
LPC24XX_MODULE_UART_3,
- LPC24XX_MODULE_USB,
- LPC24XX_MODULE_WDT
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_WDT,
+ #endif
+ LPC24XX_MODULE_USB
} lpc24xx_module;
-#define LPC24XX_MODULE_FIRST LPC24XX_MODULE_ACF
-
-#define LPC24XX_MODULE_COUNT (LPC24XX_MODULE_WDT + 1)
+#define LPC24XX_MODULE_COUNT (LPC24XX_MODULE_USB + 1)
typedef enum {
- LPC24XX_MODULE_PCLK_DEFAULT = 0x0U,
+ LPC24XX_MODULE_PCLK_DEFAULT = 0x4U,
LPC24XX_MODULE_CCLK = 0x1U,
LPC24XX_MODULE_CCLK_2 = 0x2U,
LPC24XX_MODULE_CCLK_4 = 0x0U,
@@ -105,16 +111,13 @@
typedef enum {
LPC24XX_GPIO_DEFAULT = 0x0U,
- LPC24XX_GPIO_RESISTOR_DEFAULT = 0x0U,
+ LPC24XX_GPIO_RESISTOR_PULL_UP = 0x0U,
LPC24XX_GPIO_RESISTOR_NONE = 0x1U,
- LPC24XX_GPIO_RESISTOR_PULL_UP = 0x2U,
- LPC24XX_GPIO_RESISTOR_PULL_DOWN = 0x3U,
+ LPC24XX_GPIO_RESISTOR_PULL_DOWN = 0x2U,
LPC24XX_GPIO_INPUT = 0x0U,
- LPC24XX_GPIO_OUTPUT = 0x8U
+ LPC24XX_GPIO_OUTPUT = 0x8000U
} lpc24xx_gpio_settings;
-#define LPC24XX_GPIO_RESISTOR_MASK 0x3U
-
rtems_status_code lpc24xx_module_enable(
lpc24xx_module module,
lpc24xx_module_clock clock
@@ -174,7 +177,7 @@
/**
* @brief Sets the pin function.
*/
- LPC24XX_PIN_SET_FUNCTION = 0,
+ LPC24XX_PIN_SET_FUNCTION,
/**
* @brief Checks if all pins are configured with the specified function.
@@ -195,23 +198,37 @@
typedef union {
struct {
uint16_t port : 3;
- uint16_t index_begin : 5;
- uint16_t index_last : 5;
+ uint16_t port_bit : 5;
uint16_t function : 3;
+ uint16_t type : 4;
+ uint16_t range : 1;
} fields;
uint16_t value;
} lpc24xx_pin_range;
-#define LPC24XX_PIN_FUNCTION_00 0x0
-#define LPC24XX_PIN_FUNCTION_01 0x1
-#define LPC24XX_PIN_FUNCTION_10 0x2
-#define LPC24XX_PIN_FUNCTION_11 0x3
-
-#define LPC24XX_PIN(p, i, f) { { p, i, i, f } }
+typedef enum {
+ LPC24XX_PIN_FUNCTION_00,
+ LPC24XX_PIN_FUNCTION_01,
+ LPC24XX_PIN_FUNCTION_10,
+ LPC24XX_PIN_FUNCTION_11
+} lpc24xx_pin_function;
-#define LPC24XX_PIN_RANGE(p, i, j, f) { { p, i, j, f } }
+typedef enum {
+ LPC17XX_PIN_TYPE_DEFAULT,
+ LPC17XX_PIN_TYPE_ADC,
+ LPC17XX_PIN_TYPE_DAC,
+ LPC17XX_PIN_TYPE_I2C,
+ LPC17XX_PIN_TYPE_I2C_FAST_PLUS
+} lpc17xx_pin_type;
+
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define LPC24XX_PIN(p, i, f0, f1) { { p, i, f0, 0, 0 } }
+ #define LPC24XX_PIN_WITH_TYPE(p, i, f0, f1, t) { { p, i, f0, t, 0 } }
+ #define LPC24XX_PIN_RANGE(p, i, j, f0, f1) \
+ { { p, i, f0, 0, 0 } }, { { p, j, f0, 0, 1 } }
+#endif
-#define LPC24XX_PIN_TERMINAL { { 0x3, 0x1f, 0x1f, 0x3 } }
+#define LPC24XX_PIN_TERMINAL { { 0x7, 0x1f, 0x7, 0xf, 0x1 } }
/**
* @brief Performs the @a action with the @a pins
@@ -256,21 +273,49 @@
*/
#define LPC24XX_PIN_ADC_CHANNEL_0 \
- LPC24XX_PIN(0, 23, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 23, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_1 \
- LPC24XX_PIN(0, 24, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 24, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_2 \
- LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 25, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_3 \
- LPC24XX_PIN(0, 26, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 26, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_4 \
- LPC24XX_PIN(1, 30, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(1, 30, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_5 \
- LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(1, 31, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_6 \
- LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(0, 12, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_7 \
- LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(0, 13, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC)
+
+/** @} */
+
+/**
+ * @name CAN 0 Pins
+ *
+ * @{
+ */
+
+#define LPC24XX_PIN_CAN_0_RD \
+ LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_CAN_0_TD \
+ LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_01, 1)
+
+/** @} */
+
+/**
+ * @name CAN 1 Pins
+ *
+ * @{
+ */
+
+#define LPC24XX_PIN_CAN_1_RD \
+ LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_10, 2)
+
+#define LPC24XX_PIN_CAN_1_TD \
+ LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_10, 2)
/** @} */
@@ -281,7 +326,7 @@
*/
#define LPC24XX_PIN_DAC \
- LPC24XX_PIN(0, 26, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN_WITH_TYPE(0, 26, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_DAC)
/** @} */
@@ -292,16 +337,146 @@
*/
#define LPC24XX_PIN_ETHERNET_MII \
- LPC24XX_PIN_RANGE(1, 0, 17, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_RANGE(1, 0, 17, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_ETHERNET_RMII_0 \
- LPC24XX_PIN_RANGE(1, 0, 1, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_RANGE(1, 0, 1, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_ETHERNET_RMII_1 \
- LPC24XX_PIN(1, 4, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 4, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_ETHERNET_RMII_2 \
- LPC24XX_PIN_RANGE(1, 8, 10, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_RANGE(1, 8, 10, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_ETHERNET_RMII_3 \
- LPC24XX_PIN_RANGE(1, 14, 17, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_RANGE(1, 14, 17, LPC24XX_PIN_FUNCTION_01, 1)
+
+/** @} */
+
+/**
+ * @name External Interrupt Pins
+ *
+ * @{
+ */
+
+#define LPC24XX_PIN_EINT_0 \
+ LPC24XX_PIN(2, 10, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EINT_1 \
+ LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EINT_2 \
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EINT_3 \
+ LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 1)
+
+/** @} */
+
+/**
+ * @name External Memory Controller (EMC) Pins
+ *
+ * @{
+ */
+
+#define LPC24XX_PIN_EMC_CS_0 \
+ LPC24XX_PIN(4, 30, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CS_1 \
+ LPC24XX_PIN(4, 31, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CS_2 \
+ LPC24XX_PIN(2, 14, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CS_3 \
+ LPC24XX_PIN(2, 15, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_DYCS_0 \
+ LPC24XX_PIN(2, 20, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DYCS_1 \
+ LPC24XX_PIN(2, 21, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DYCS_2 \
+ LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DYCS_3 \
+ LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_OE \
+ LPC24XX_PIN(4, 24, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_WE \
+ LPC24XX_PIN(4, 25, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CAS \
+ LPC24XX_PIN(2, 16, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_RAS \
+ LPC24XX_PIN(2, 17, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_CLK_0 \
+ LPC24XX_PIN(2, 18, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CLK_1 \
+ LPC24XX_PIN(2, 19, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_CKE_0 \
+ LPC24XX_PIN(2, 24, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CKE_1 \
+ LPC24XX_PIN(2, 25, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CKE_2 \
+ LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CKE_3 \
+ LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_DQM_0 \
+ LPC24XX_PIN(2, 28, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DQM_1 \
+ LPC24XX_PIN(2, 29, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DQM_2 \
+ LPC24XX_PIN(2, 30, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DQM_3 \
+ LPC24XX_PIN(2, 31, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_BLS0 \
+ LPC24XX_PIN(4, 26, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_BLS1 \
+ LPC24XX_PIN(4, 27, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_BLS2 \
+ LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_BLS3 \
+ LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_D_0_15 \
+ LPC24XX_PIN_RANGE(3, 0, 15, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_D_15_31 \
+ LPC24XX_PIN_RANGE(3, 15, 31, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_D_0_31 \
+ LPC24XX_PIN_RANGE(3, 0, 31, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_A_0_12 \
+ LPC24XX_PIN_RANGE(4, 0, 12, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_13 \
+ LPC24XX_PIN_RANGE(4, 0, 13, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_14 \
+ LPC24XX_PIN_RANGE(4, 0, 14, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_15 \
+ LPC24XX_PIN_RANGE(4, 0, 15, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_16 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN(4, 16, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_17 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 17, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_18 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 18, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_19 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 19, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_20 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 20, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_21 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 21, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_22 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 22, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_23 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 23, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_24 \
+ LPC24XX_PIN_EMC_A_0_23, \
+ LPC24XX_PIN(5, 24, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_25 \
+ LPC24XX_PIN_EMC_A_0_23, \
+ LPC24XX_PIN_RANGE(5, 24, 25, LPC24XX_PIN_FUNCTION_01, 1)
/** @} */
@@ -312,9 +487,9 @@
*/
#define LPC24XX_PIN_I2C_0_SDA \
- LPC24XX_PIN(0, 27, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 27, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_0_SCL \
- LPC24XX_PIN(0, 28, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 28, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_I2C)
/** @} */
@@ -325,18 +500,18 @@
*/
#define LPC24XX_PIN_I2C_1_SDA_P0_0 \
- LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(0, 0, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_1_SDA_P0_19 \
- LPC24XX_PIN(0, 19, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(0, 19, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_1_SDA_P2_14 \
- LPC24XX_PIN(2, 14, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(2, 14, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C)
-#define LPC24XX_PIN_I2C_1_SCL_P0_20 \
- LPC24XX_PIN(0, 20, LPC24XX_PIN_FUNCTION_11)
#define LPC24XX_PIN_I2C_1_SCL_P0_1 \
- LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(0, 1, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C)
+#define LPC24XX_PIN_I2C_1_SCL_P0_20 \
+ LPC24XX_PIN_WITH_TYPE(0, 20, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_1_SCL_P2_15 \
- LPC24XX_PIN(2, 15, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(2, 15, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C)
/** @} */
@@ -347,18 +522,18 @@
*/
#define LPC24XX_PIN_I2C_2_SDA_P0_10 \
- LPC24XX_PIN(0, 10, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN_WITH_TYPE(0, 10, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_2_SDA_P2_30 \
- LPC24XX_PIN(2, 30, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(2, 30, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_2_SDA_P4_20 \
- LPC24XX_PIN(4, 20, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN_WITH_TYPE(4, 20, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C)
-#define LPC24XX_PIN_I2C_2_SCL_P2_31 \
- LPC24XX_PIN(2, 31, LPC24XX_PIN_FUNCTION_11)
#define LPC24XX_PIN_I2C_2_SCL_P0_11 \
- LPC24XX_PIN(0, 11, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN_WITH_TYPE(0, 11, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C)
+#define LPC24XX_PIN_I2C_2_SCL_P2_31 \
+ LPC24XX_PIN_WITH_TYPE(2, 31, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_2_SCL_P4_21 \
- LPC24XX_PIN(4, 21, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN_WITH_TYPE(4, 21, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C)
/** @} */
@@ -369,34 +544,34 @@
*/
#define LPC24XX_PIN_I2S_RX_CLK_P0_4 \
- LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_RX_CLK_P0_23 \
- LPC24XX_PIN(0, 23, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 23, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_I2S_RX_WS_P0_5 \
- LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_RX_WS_P0_24 \
- LPC24XX_PIN(0, 24, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 24, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_I2S_RX_SDA_P0_6 \
- LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_RX_SDA_P0_25 \
- LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_I2S_TX_CLK_P0_7 \
- LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_TX_CLK_P2_11 \
- LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_I2S_TX_WS_P0_8 \
- LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_TX_WS_P2_12 \
- LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_I2S_TX_SDA_P0_9 \
- LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_TX_SDA_P2_13 \
- LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_11, 3)
/** @} */
@@ -407,68 +582,114 @@
*/
#define LPC24XX_PIN_LCD_PWR \
- LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_LE \
- LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_DCLK \
- LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_FP \
- LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_ENAB_M \
- LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_LP \
- LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_CLKIN \
- LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01, 7)
-#define LPC24XX_PIN_LCD_VD_P0_4 \
- LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P0_5 \
- LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P0_6 \
- LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P0_7 \
- LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P0_8 \
- LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P0_9 \
- LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_20 \
- LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_21 \
- LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_22 \
- LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_23 \
- LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_24 \
- LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_25 \
- LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_26 \
- LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_27 \
- LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_28 \
- LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_29 \
- LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P2_6 \
- LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_LCD_VD_P2_7 \
- LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_LCD_VD_P2_8 \
- LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_LCD_VD_P2_9 \
- LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_LCD_VD_P2_12 \
- LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P2_13 \
- LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P4_28 \
- LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10)
-#define LPC24XX_PIN_LCD_VD_P4_29 \
- LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10)
+#define LPC24XX_PIN_LCD_VD_0_P0_4 \
+ LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_0_P2_6 \
+ LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11, 6)
+#define LPC24XX_PIN_LCD_VD_1_P0_5 \
+ LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_1_P2_7 \
+ LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11, 6)
+#define LPC24XX_PIN_LCD_VD_2_P2_8 \
+ LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11, 6)
+#define LPC24XX_PIN_LCD_VD_2_P4_28 \
+ LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 7)
+#define LPC24XX_PIN_LCD_VD_3_P2_9 \
+ LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11, 6)
+#define LPC24XX_PIN_LCD_VD_3_P2_12 \
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 5)
+#define LPC24XX_PIN_LCD_VD_3_P4_29 \
+ LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 7)
+#define LPC24XX_PIN_LCD_VD_4_P2_6 \
+ LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11, 7)
+#define LPC24XX_PIN_LCD_VD_4_P2_12 \
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 4)
+#define LPC24XX_PIN_LCD_VD_5_P2_7 \
+ LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11, 7)
+#define LPC24XX_PIN_LCD_VD_5_P2_13 \
+ LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 5)
+#define LPC24XX_PIN_LCD_VD_6_P1_20 \
+ LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_6_P2_8 \
+ LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11, 7)
+#define LPC24XX_PIN_LCD_VD_6_P4_28 \
+ LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 5)
+#define LPC24XX_PIN_LCD_VD_7_P1_21 \
+ LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_7_P2_9 \
+ LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11, 7)
+#define LPC24XX_PIN_LCD_VD_7_P4_29 \
+ LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 5)
+#define LPC24XX_PIN_LCD_VD_8_P0_6 \
+ LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_8_P1_22 \
+ LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_8_P2_12 \
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_9_P0_7 \
+ LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_9_P1_23 \
+ LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_9_P2_13 \
+ LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_10_P1_20 \
+ LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_10_P1_24 \
+ LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_10_P4_28 \
+ LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 6)
+#define LPC24XX_PIN_LCD_VD_11_P1_21 \
+ LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_11_P1_25 \
+ LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_11_P4_29 \
+ LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 6)
+#define LPC24XX_PIN_LCD_VD_12_P1_22 \
+ LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_12_P1_26 \
+ LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_13_P1_23 \
+ LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_13_P1_27 \
+ LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_14_P1_24 \
+ LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_14_P1_28 \
+ LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_15_P1_25 \
+ LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_15_P1_29 \
+ LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_16_P0_8 \
+ LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_17_P0_9 \
+ LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_18_P2_12 \
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_19_P2_13 \
+ LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_20_P1_26 \
+ LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_21_P1_27 \
+ LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_22_P1_28 \
+ LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_23_P1_29 \
+ LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 7)
/** @} */
@@ -479,39 +700,39 @@
*/
#define LPC24XX_PIN_PWM_0_CHANNEL_1_P1_2 \
- LPC24XX_PIN(1, 2, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 2, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_1_P3_16 \
- LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CHANNEL_2_P1_3 \
- LPC24XX_PIN(1, 3, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 3, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_2_P3_17 \
- LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CHANNEL_3_P1_5 \
- LPC24XX_PIN(1, 5, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 5, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_3_P3_18 \
- LPC24XX_PIN(3, 18, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 18, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CHANNEL_4_P1_6 \
- LPC24XX_PIN(1, 6, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 6, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_4_P3_19 \
- LPC24XX_PIN(3, 19, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 19, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CHANNEL_5_P1_7 \
- LPC24XX_PIN(1, 7, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 7, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_5_P3_20 \
- LPC24XX_PIN(3, 20, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 20, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CHANNEL_6_P1_11 \
- LPC24XX_PIN(1, 11, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 11, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_6_P3_21 \
- LPC24XX_PIN(3, 21, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 21, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CAPTURE_0_P1_12 \
- LPC24XX_PIN(1, 12, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 12, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CAPTURE_0_P3_22 \
- LPC24XX_PIN(3, 22, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 22, LPC24XX_PIN_FUNCTION_10, 2)
/** @} */
@@ -522,73 +743,56 @@
*/
#define LPC24XX_PIN_PWM_1_CHANNEL_1_P1_18 \
- LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_1_P2_0 \
- LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_1_P3_24 \
- LPC24XX_PIN(3, 24, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 24, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_2_P1_20 \
- LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_2_P2_1 \
- LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_2_P3_25 \
- LPC24XX_PIN(3, 25, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 25, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_3_P1_21 \
- LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_3_P2_2 \
- LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_3_P3_26 \
- LPC24XX_PIN(3, 26, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 26, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_4_P1_23 \
- LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_4_P2_3 \
- LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_4_P3_27 \
- LPC24XX_PIN(3, 27, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 27, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_5_P1_24 \
- LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_5_P2_4 \
- LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_5_P3_28 \
- LPC24XX_PIN(3, 28, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 28, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_6_P1_26 \
- LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_6_P2_5 \
- LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_6_P3_29 \
- LPC24XX_PIN(3, 29, LPC24XX_PIN_FUNCTIO9_11)
+ LPC24XX_PIN(3, 29, LPC24XX_PIN_FUNCTIO9_11, 2)
#define LPC24XX_PIN_PWM_1_CAPTURE_0_P1_28 \
- LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CAPTURE_0_P2_7 \
- LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CAPTURE_0_P3_23 \
- LPC24XX_PIN(3, 23, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 23, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CAPTURE_1_P1_29 \
- LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_10)
-
-/** @} */
-
-/**
- * @name SPI Pins
- *
- * @{
- */
-
-#define LPC24XX_PIN_SPI_SCK \
- LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_SPI_SSEL \
- LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_SPI_MISO \
- LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_SPI_MOSI \
- LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_10, 2)
/** @} */
@@ -599,32 +803,32 @@
*/
#define LPC24XX_PIN_SSP_0_SCK_P0_15 \
- LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_0_SCK_P1_20 \
- LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_11, 5)
#define LPC24XX_PIN_SSP_0_SCK_P2_22 \
- LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_SSP_0_SSEL_P0_16 \
- LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_0_SSEL_P1_21 \
- LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_SSP_0_SSEL_P2_23 \
- LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_SSP_0_MISO_P0_17 \
- LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_0_MISO_P1_23 \
- LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_11, 5)
#define LPC24XX_PIN_SSP_0_MISO_P2_26 \
- LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_SSP_0_MOSI_P0_18 \
- LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_0_MOSI_P1_24 \
- LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_11, 5)
#define LPC24XX_PIN_SSP_0_MOSI_P2_27 \
- LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_11, 2)
/** @} */
@@ -635,32 +839,32 @@
*/
#define LPC24XX_PIN_SSP_1_SCK_P0_6 \
- LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_SCK_P0_12 \
- LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_SCK_P4_20 \
- LPC24XX_PIN(4, 20, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 20, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_SSP_1_SSEL_P0_7 \
- LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_SSEL_P0_13 \
- LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_SSP_1_SSEL_P4_21 \
- LPC24XX_PIN(4, 21, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 21, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_SSP_1_MISO_P0_8 \
- LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_MISO_P0_14 \
- LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_MISO_P4_22 \
- LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_SSP_1_MOSI_P0_9 \
- LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_MOSI_P1_31 \
- LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_MOSI_P4_23 \
- LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_11, 3)
/** @} */
@@ -671,10 +875,10 @@
*/
#define LPC24XX_PIN_UART_0_TXD \
- LPC24XX_PIN(0, 2, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 2, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_UART_0_RXD \
- LPC24XX_PIN(0, 3, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 3, LPC24XX_PIN_FUNCTION_01, 1)
/** @} */
@@ -685,18 +889,18 @@
*/
#define LPC24XX_PIN_UART_1_TXD_P0_15 \
- LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_UART_1_TXD_P2_0 \
- LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_1_TXD_P3_16 \
- LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_UART_1_RXD_P0_16 \
- LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_UART_1_RXD_P2_1 \
- LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_1_RXD_P3_17 \
- LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_11, 3)
/** @} */
@@ -707,18 +911,18 @@
*/
#define LPC24XX_PIN_UART_2_TXD_P0_10 \
- LPC24XX_PIN(0, 10, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 10, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_UART_2_TXD_P2_8 \
- LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_2_TXD_P4_22 \
- LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_2_RXD_P0_11 \
- LPC24XX_PIN(0, 11, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 11, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_UART_2_RXD_P2_9 \
- LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_2_RXD_P4_23 \
- LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_10, 2)
/** @} */
@@ -729,18 +933,18 @@
*/
#define LPC24XX_PIN_UART_3_TXD_P0_0 \
- LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_3_TXD_P0_25 \
- LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_UART_3_TXD_P4_28 \
- LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_UART_3_RXD_P0_1 \
- LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_3_RXD_P0_25 \
- LPC24XX_PIN(0, 26, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(0, 26, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_UART_3_RXD_P4_29 \
- LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_11, 2)
/** @} */
@@ -751,43 +955,43 @@
*/
#define LPC24XX_PIN_USB_D_PLUS_1\
- LPC24XX_PIN(0, 29, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 29, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_D_MINUS_1\
- LPC24XX_PIN(0, 30, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 30, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_UP_LED_1\
- LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_TX_E_1\
- LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_PPWR_1\
- LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_USB_TX_DP_1\
- LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_TX_DM_1\
- LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_RCV_1\
- LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_PWRD_1\
- LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_USB_RX_DP_1\
- LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_RX_DM_1\
- LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_LS_1\
- LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_HSTEN_1\
- LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_USB_SSPND_1\
- LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_INT_1\
- LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_OVRCR_1\
- LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_USB_SCL_1\
- LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_SDA_1\
- LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_CONNECT_1\
- LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_01, 1)
/** @} */
@@ -798,19 +1002,19 @@
*/
#define LPC24XX_PIN_USB_PPWR_2\
- LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_UP_LED_2\
- LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_HSTEN_2\
- LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_CONNECT_2\
- LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01, 3)
#define LPC24XX_PIN_USB_D_PLUS_2\
- LPC24XX_PIN(0, 31, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 31, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_PWRD_2\
- LPC24XX_PIN(1, 30, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 30, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_OVRCR_2\
- LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_01, 1)
/** @} */
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/include/irq.h:1.5 rtems/c/src/lib/libbsp/arm/lpc24xx/include/irq.h:1.6
--- rtems/c/src/lib/libbsp/arm/lpc24xx/include/irq.h:1.5 Tue Dec 15 09:20:46 2009
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/include/irq.h Tue Nov 8 04:39:46 2011
@@ -7,25 +7,27 @@
*/
/*
- * Copyright (c) 2008
- * Embedded Brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * rtems at embedded-brains.de
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
- * The license and distribution terms for this file may be found in the file
- * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
*/
#ifndef LIBBSP_ARM_LPC24XX_IRQ_H
#define LIBBSP_ARM_LPC24XX_IRQ_H
#ifndef ASM
-
-#include <rtems.h>
-#include <rtems/irq.h>
-#include <rtems/irq-extension.h>
+ #include <rtems.h>
+ #include <rtems/irq.h>
+ #include <rtems/irq-extension.h>
+#endif
/**
* @addtogroup bsp_interrupt
@@ -33,61 +35,63 @@
* @{
*/
-#define LPC24XX_IRQ_WDT 0
-#define LPC24XX_IRQ_SOFTWARE 1
-#define LPC24XX_IRQ_ARM_CORE_0 2
-#define LPC24XX_IRQ_ARM_CORE_1 3
-#define LPC24XX_IRQ_TIMER_0 4
-#define LPC24XX_IRQ_TIMER_1 5
-#define LPC24XX_IRQ_UART_0 6
-#define LPC24XX_IRQ_UART_1 7
-#define LPC24XX_IRQ_PWM 8
-#define LPC24XX_IRQ_I2C_0 9
-#define LPC24XX_IRQ_SPI_SSP_0 10
-#define LPC24XX_IRQ_SSP_1 11
-#define LPC24XX_IRQ_PLL 12
-#define LPC24XX_IRQ_RTC 13
-#define LPC24XX_IRQ_EINT_0 14
-#define LPC24XX_IRQ_EINT_1 15
-#define LPC24XX_IRQ_EINT_2 16
-#define LPC24XX_IRQ_EINT_3 17
-#define LPC24XX_IRQ_ADC_0 18
-#define LPC24XX_IRQ_I2C_1 19
-#define LPC24XX_IRQ_BOD 20
-#define LPC24XX_IRQ_ETHERNET 21
-#define LPC24XX_IRQ_USB 22
-#define LPC24XX_IRQ_CAN 23
-#define LPC24XX_IRQ_SD_MMC 24
-#define LPC24XX_IRQ_DMA 25
-#define LPC24XX_IRQ_TIMER_2 26
-#define LPC24XX_IRQ_TIMER_3 27
-#define LPC24XX_IRQ_UART_2 28
-#define LPC24XX_IRQ_UART_3 29
-#define LPC24XX_IRQ_I2C_2 30
-#define LPC24XX_IRQ_I2S 31
-
-#define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0U
-#define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15U
-#define LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1U)
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define LPC24XX_IRQ_WDT 0
+ #define LPC24XX_IRQ_SOFTWARE 1
+ #define LPC24XX_IRQ_ARM_CORE_0 2
+ #define LPC24XX_IRQ_ARM_CORE_1 3
+ #define LPC24XX_IRQ_TIMER_0 4
+ #define LPC24XX_IRQ_TIMER_1 5
+ #define LPC24XX_IRQ_UART_0 6
+ #define LPC24XX_IRQ_UART_1 7
+ #define LPC24XX_IRQ_PWM 8
+ #define LPC24XX_IRQ_I2C_0 9
+ #define LPC24XX_IRQ_SPI_SSP_0 10
+ #define LPC24XX_IRQ_SSP_1 11
+ #define LPC24XX_IRQ_PLL 12
+ #define LPC24XX_IRQ_RTC 13
+ #define LPC24XX_IRQ_EINT_0 14
+ #define LPC24XX_IRQ_EINT_1 15
+ #define LPC24XX_IRQ_EINT_2 16
+ #define LPC24XX_IRQ_EINT_3 17
+ #define LPC24XX_IRQ_ADC_0 18
+ #define LPC24XX_IRQ_I2C_1 19
+ #define LPC24XX_IRQ_BOD 20
+ #define LPC24XX_IRQ_ETHERNET 21
+ #define LPC24XX_IRQ_USB 22
+ #define LPC24XX_IRQ_CAN 23
+ #define LPC24XX_IRQ_SD_MMC 24
+ #define LPC24XX_IRQ_DMA 25
+ #define LPC24XX_IRQ_TIMER_2 26
+ #define LPC24XX_IRQ_TIMER_3 27
+ #define LPC24XX_IRQ_UART_2 28
+ #define LPC24XX_IRQ_UART_3 29
+ #define LPC24XX_IRQ_I2C_2 30
+ #define LPC24XX_IRQ_I2S 31
+
+ #define BSP_INTERRUPT_VECTOR_MAX 31
+#endif
+
+#define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15
+#endif
+#define LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1)
#define LPC24XX_IRQ_PRIORITY_HIGHEST LPC24XX_IRQ_PRIORITY_VALUE_MIN
#define LPC24XX_IRQ_PRIORITY_LOWEST LPC24XX_IRQ_PRIORITY_VALUE_MAX
-/**
- * @brief Minimum vector number.
- */
-#define BSP_INTERRUPT_VECTOR_MIN LPC24XX_IRQ_WDT
-
-/**
- * @brief Maximum vector number.
- */
-#define BSP_INTERRUPT_VECTOR_MAX LPC24XX_IRQ_I2S
+#ifndef ASM
void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority);
unsigned lpc24xx_irq_get_priority(rtems_vector_number vector);
-/** @} */
+void bsp_interrupt_dispatch(void);
#endif /* ASM */
+/** @} */
+
#endif /* LIBBSP_ARM_LPC24XX_IRQ_H */
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/include/lcd.h:1.2 rtems/c/src/lib/libbsp/arm/lpc24xx/include/lcd.h:1.3
--- rtems/c/src/lib/libbsp/arm/lpc24xx/include/lcd.h:1.2 Thu May 19 07:30:00 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/include/lcd.h Tue Nov 8 04:39:46 2011
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2010 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
@@ -42,15 +42,17 @@
*/
typedef enum {
- LCD_MODE_STN_4_BIT = 0,
- LCD_MODE_STN_8_BIT,
- LCD_MODE_STN_DUAL_PANEL_4_BIT,
- LCD_MODE_STN_DUAL_PANEL_8_BIT,
- LCD_MODE_TFT_12_BIT_4_4_4,
- LCD_MODE_TFT_16_BIT_5_6_5,
- LCD_MODE_TFT_16_BIT_1_5_5_5,
- LCD_MODE_TFT_24_BIT,
- LCD_MODE_DISABLED
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LCD_MODE_STN_4_BIT = 0,
+ LCD_MODE_STN_8_BIT,
+ LCD_MODE_STN_DUAL_PANEL_4_BIT,
+ LCD_MODE_STN_DUAL_PANEL_8_BIT,
+ LCD_MODE_TFT_12_BIT_4_4_4,
+ LCD_MODE_TFT_16_BIT_5_6_5,
+ LCD_MODE_TFT_16_BIT_1_5_5_5,
+ LCD_MODE_TFT_24_BIT,
+ LCD_MODE_DISABLED
+ #endif
} lpc24xx_lcd_mode;
/**
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h:1.1 rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h:1.2
--- rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h:1.1 Wed Dec 16 02:10:29 2009
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h Tue Nov 8 04:39:46 2011
@@ -35,10 +35,10 @@
#define LPC_CLOCK_TIMER_BASE TMR0_BASE_ADDR
-#define LPC_CLOCK_REFERENCE LPC24XX_CCLK
+#define LPC_CLOCK_REFERENCE LPC24XX_PCLK
#define LPC_CLOCK_MODULE_ENABLE() \
- lpc24xx_module_enable(LPC24XX_MODULE_TIMER_0, LPC24XX_MODULE_CCLK)
+ lpc24xx_module_enable(LPC24XX_MODULE_TIMER_0, LPC24XX_MODULE_PCLK_DEFAULT)
#ifdef __cplusplus
}
diff -u /dev/null rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc17xx.h:1.1
--- /dev/null Tue Nov 8 05:10:29 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc17xx.h Tue Nov 8 04:39:46 2011
@@ -0,0 +1,187 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx_regs
+ *
+ * @brief Register definitions.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
+ */
+
+#ifndef LPC17XX_REGS_H
+#define LPC17XX_REGS_H
+
+#include <bsp/utility.h>
+
+#define LPC17XX_BASE 0x00
+
+typedef struct {
+#define LPC17XX_PLL_CON_PLLE BSP_BIT32(0)
+#define LPC17XX_PLL_SEL_MSEL(val) BSP_FLD32(val, 0, 4)
+#define LPC17XX_PLL_SEL_MSEL_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define LPC17XX_PLL_SEL_MSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+#define LPC17XX_PLL_SEL_PSEL(val) BSP_FLD32(val, 5, 6)
+#define LPC17XX_PLL_SEL_PSEL_GET(reg) BSP_FLD32GET(reg, 5, 6)
+#define LPC17XX_PLL_SEL_PSEL_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6)
+#define LPC17XX_PLL_STAT_PLLE BSP_BIT32(8)
+#define LPC17XX_PLL_STAT_PLOCK BSP_BIT32(10)
+ uint32_t con;
+ uint32_t cfg;
+ uint32_t stat;
+ uint32_t feed;
+} lpc17xx_pll;
+
+typedef struct {
+ uint32_t flashcfg;
+#define LPC17XX_SCB_FLASHCFG_FLASHTIM(val) BSP_FLD32(val, 12, 15)
+#define LPC17XX_SCB_FLASHCFG_FLASHTIM_GET(reg) BSP_FLD32GET(reg, 12, 15)
+#define LPC17XX_SCB_FLASHCFG_FLASHTIM_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
+ uint32_t reserved_04 [15];
+ uint32_t memmap;
+#define LPC17XX_SCB_MEMMAP_MAP BSP_BIT32(0)
+ uint32_t reserved_44 [15];
+ lpc17xx_pll pll_0;
+ uint32_t reserved_90 [4];
+ lpc17xx_pll pll_1;
+ uint32_t reserved_b0 [4];
+ uint32_t pcon;
+#define LPC17XX_SCB_PCON_PM0 BSP_BIT32(0)
+#define LPC17XX_SCB_PCON_PM1 BSP_BIT32(1)
+#define LPC17XX_SCB_PCON_BODRPM BSP_BIT32(2)
+#define LPC17XX_SCB_PCON_BOGD BSP_BIT32(3)
+#define LPC17XX_SCB_PCON_BORD BSP_BIT32(4)
+#define LPC17XX_SCB_PCON_SMFLAG BSP_BIT32(8)
+#define LPC17XX_SCB_PCON_DSFLAG BSP_BIT32(9)
+#define LPC17XX_SCB_PCON_PDFLAG BSP_BIT32(10)
+#define LPC17XX_SCB_PCON_DPDFLAG BSP_BIT32(11)
+ uint32_t pconp;
+#define LPC17XX_SCB_PCONP_LCD BSP_BIT32(0)
+#define LPC17XX_SCB_PCONP_TIMER_0 BSP_BIT32(1)
+#define LPC17XX_SCB_PCONP_TIMER_1 BSP_BIT32(2)
+#define LPC17XX_SCB_PCONP_UART_0 BSP_BIT32(3)
+#define LPC17XX_SCB_PCONP_UART_1 BSP_BIT32(4)
+#define LPC17XX_SCB_PCONP_PWM_0 BSP_BIT32(5)
+#define LPC17XX_SCB_PCONP_PWM_1 BSP_BIT32(6)
+#define LPC17XX_SCB_PCONP_I2C_0 BSP_BIT32(7)
+#define LPC17XX_SCB_PCONP_UART_4 BSP_BIT32(8)
+#define LPC17XX_SCB_PCONP_RTC BSP_BIT32(9)
+#define LPC17XX_SCB_PCONP_SSP_1 BSP_BIT32(10)
+#define LPC17XX_SCB_PCONP_EMC BSP_BIT32(11)
+#define LPC17XX_SCB_PCONP_ADC BSP_BIT32(12)
+#define LPC17XX_SCB_PCONP_CAN_0 BSP_BIT32(13)
+#define LPC17XX_SCB_PCONP_CAN_1 BSP_BIT32(14)
+#define LPC17XX_SCB_PCONP_GPIO BSP_BIT32(15)
+#define LPC17XX_SCB_PCONP_QEI BSP_BIT32(17)
+#define LPC17XX_SCB_PCONP_I2C_1 BSP_BIT32(18)
+#define LPC17XX_SCB_PCONP_SSP_2 BSP_BIT32(19)
+#define LPC17XX_SCB_PCONP_SSP_0 BSP_BIT32(20)
+#define LPC17XX_SCB_PCONP_TIMER_2 BSP_BIT32(21)
+#define LPC17XX_SCB_PCONP_TIMER_3 BSP_BIT32(22)
+#define LPC17XX_SCB_PCONP_UART_2 BSP_BIT32(23)
+#define LPC17XX_SCB_PCONP_UART_3 BSP_BIT32(24)
+#define LPC17XX_SCB_PCONP_I2C_2 BSP_BIT32(25)
+#define LPC17XX_SCB_PCONP_I2S BSP_BIT32(26)
+#define LPC17XX_SCB_PCONP_SDC BSP_BIT32(27)
+#define LPC17XX_SCB_PCONP_GPDMA BSP_BIT32(28)
+#define LPC17XX_SCB_PCONP_ENET BSP_BIT32(29)
+#define LPC17XX_SCB_PCONP_USB BSP_BIT32(30)
+#define LPC17XX_SCB_PCONP_MCPWM BSP_BIT32(31)
+ uint32_t reserved_c8 [14];
+ uint32_t emcclksel;
+#define LPC17XX_SCB_EMCCLKSEL_EMCDIV BSP_BIT32(0)
+ uint32_t cclksel;
+#define LPC17XX_SCB_CCLKSEL_CCLKDIV(val) BSP_FLD32(val, 0, 4)
+#define LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define LPC17XX_SCB_CCLKSEL_CCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+#define LPC17XX_SCB_CCLKSEL_CCLKSEL BSP_BIT32(8)
+ uint32_t usbclksel;
+#define LPC17XX_SCB_USBCLKSEL_USBDIV(val) BSP_FLD32(val, 0, 4)
+#define LPC17XX_SCB_USBCLKSEL_USBDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define LPC17XX_SCB_USBCLKSEL_USBDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+#define LPC17XX_SCB_USBCLKSEL_USBSEL(val) BSP_FLD32(val, 8, 9)
+#define LPC17XX_SCB_USBCLKSEL_USBSEL_GET(reg) BSP_FLD32GET(reg, 8, 9)
+#define LPC17XX_SCB_USBCLKSEL_USBSEL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
+ uint32_t clksrcsel;
+#define LPC17XX_SCB_CLKSRCSEL_CLKSRC BSP_BIT32(0)
+ uint32_t reserved_110 [12];
+ uint32_t extint;
+ uint32_t reserved_144;
+ uint32_t extmode;
+ uint32_t extpolar;
+ uint32_t reserved_150 [12];
+ uint32_t rsid;
+ uint32_t reserved_184 [7];
+ uint32_t scs;
+#define LPC17XX_SCB_SCS_EMC_SHIFT_CTL BSP_BIT32(0)
+#define LPC17XX_SCB_SCS_EMC_RESET_DIS BSP_BIT32(1)
+#define LPC17XX_SCB_SCS_EMC_BURST_CTL BSP_BIT32(2)
+#define LPC17XX_SCB_SCS_MCIPWR BSP_BIT32(3)
+#define LPC17XX_SCB_SCS_OSC_RANGE_SEL BSP_BIT32(4)
+#define LPC17XX_SCB_SCS_OSC_ENABLE BSP_BIT32(5)
+#define LPC17XX_SCB_SCS_OSC_STATUS BSP_BIT32(6)
+ uint32_t reserved_1a4;
+ uint32_t pclksel;
+#define LPC17XX_SCB_PCLKSEL_PCLKDIV(val) BSP_FLD32(val, 0, 4)
+#define LPC17XX_SCB_PCLKSEL_PCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define LPC17XX_SCB_PCLKSEL_PCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+ uint32_t reserved_1ac;
+ uint32_t pboost;
+#define LPC17XX_SCB_PBOOST_BOOST BSP_BIT32(0)
+ uint32_t reserved_1b4 [5];
+ uint32_t clkoutcfg;
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL(val) BSP_FLD32(val, 3, 0)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_GET(reg) BSP_FLD32GET(reg, 3, 0)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 0)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV(val) BSP_FLD32(val, 7, 4)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_GET(reg) BSP_FLD32GET(reg, 7, 4)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_SET(reg, val) BSP_FLD32SET(reg, val, 7, 4)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32(8)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32(9)
+ uint32_t rstcon0;
+ uint32_t rstcon1;
+ uint32_t reserved_1d4 [2];
+ uint32_t emcdlyctl;
+#define LPC17XX_SCB_EMCDLYCTL_CMDDLY(val) BSP_FLD32(val, 0, 4)
+#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY(val) BSP_FLD32(val, 8, 12)
+#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_GET(reg) BSP_FLD32GET(reg, 8, 12)
+#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 12)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY(val) BSP_FLD32(val, 16, 20)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_GET(reg) BSP_FLD32GET(reg, 16, 20)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY(val) BSP_FLD32(val, 24, 28)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_GET(reg) BSP_FLD32GET(reg, 24, 28)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28)
+ uint32_t emccal;
+#define LPC17XX_SCB_EMCCAL_CALVALUE(val) BSP_FLD32(val, 0, 7)
+#define LPC17XX_SCB_EMCCAL_CALVALUE_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define LPC17XX_SCB_EMCCAL_CALVALUE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+#define LPC17XX_SCB_EMCCAL_START BSP_BIT32(14)
+#define LPC17XX_SCB_EMCCAL_DONE BSP_BIT32(15)
+} lpc17xx_scb;
+
+#define LPC17XX_SCB (*(volatile lpc17xx_scb *) (LPC17XX_BASE + 0x400fc000))
+
+typedef struct {
+ uint32_t reserved_00 [268693504];
+ lpc17xx_scb scb;
+} lpc17xx;
+
+#define LPC17XX (*(volatile lpc17xx *) (LPC17XX_BASE))
+
+#endif /* LPC17XX_REGS_H */
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h:1.15 rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h:1.16
--- rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h:1.15 Thu Jul 21 10:32:08 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h Tue Nov 8 04:39:46 2011
@@ -7,24 +7,32 @@
*/
/*
- * Copyright (c) 2008
- * Embedded Brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * rtems at embedded-brains.de
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
- * The license and distribution terms for this file may be found in the file
- * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
*/
#ifndef LIBBSP_ARM_LPC24XX_LPC24XX_H
#define LIBBSP_ARM_LPC24XX_LPC24XX_H
-#include <stdint.h>
+#include <rtems/score/cpu.h>
#include <bsp/utility.h>
#include <bsp/lpc-i2s.h>
+#ifdef ARM_MULTILIB_ARCH_V7M
+ #include <bsp/lpc17xx.h>
+#endif
+
/**
* @defgroup lpc24xx_regs Register Definitions
*
@@ -35,6 +43,8 @@
* @{
*/
+#ifdef ARM_MULTILIB_ARCH_V4
+
/* Vectored Interrupt Controller (VIC) */
#define VIC_BASE_ADDR 0xFFFFF000
#define VICIRQStatus (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x000))
@@ -118,9 +128,17 @@
#define VICVectAddr (*(volatile uint32_t *) (VIC_BASE_ADDR + 0xF00))
+#endif /* ARM_MULTILIB_ARCH_V4 */
/* Pin Connect Block */
-#define PINSEL_BASE_ADDR 0xE002C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define PINSEL_BASE_ADDR 0xE002C000
+#else
+ #define PINSEL_BASE_ADDR 0x4002C000
+#endif
+
+#ifdef ARM_MULTILIB_ARCH_V4
+
#define PINSEL0 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x00))
#define PINSEL1 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x04))
#define PINSEL2 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x08))
@@ -145,8 +163,14 @@
#define PINMODE8 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x60))
#define PINMODE9 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x64))
+#endif /* ARM_MULTILIB_ARCH_V4 */
+
/* General Purpose Input/Output (GPIO) */
-#define GPIO_BASE_ADDR 0xE0028000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define GPIO_BASE_ADDR 0xE0028000
+#else
+ #define GPIO_BASE_ADDR 0x40028000
+#endif
#define IOPIN0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x00))
#define IOSET0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x04))
#define IODIR0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x08))
@@ -171,11 +195,19 @@
#define IO_INT_STAT (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x80))
+#ifdef ARM_MULTILIB_ARCH_V4
+
#define PARTCFG_BASE_ADDR 0x3FFF8000
#define PARTCFG (*(volatile uint32_t *) (PARTCFG_BASE_ADDR + 0x00))
+#endif /* ARM_MULTILIB_ARCH_V4 */
+
/* Fast I/O setup */
-#define FIO_BASE_ADDR 0x3FFFC000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define FIO_BASE_ADDR 0x3FFFC000
+#else
+ #define FIO_BASE_ADDR 0x20098000
+#endif
#define FIO0DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x00))
#define FIO0MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x10))
#define FIO0PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x14))
@@ -206,6 +238,16 @@
#define FIO4SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x98))
#define FIO4CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x9C))
+#ifdef ARM_MULTILIB_ARCH_V7M
+
+#define FIO5DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xa0))
+#define FIO5MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb0))
+#define FIO5PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb4))
+#define FIO5SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb8))
+#define FIO5CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xbC))
+
+#endif /* ARM_MULTILIB_ARCH_V7M */
+
/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
#define FIO0DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x00))
#define FIO1DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x20))
@@ -387,6 +429,7 @@
#define FIO3CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7E))
#define FIO4CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9E))
+#ifdef ARM_MULTILIB_ARCH_V4
/* System Control Block(SCB) modules include Memory Accelerator Module,
Phase Locked Loop, VPB divider, Power Control, External Interrupt,
@@ -435,9 +478,14 @@
/* System Controls and Status */
#define SCS (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A0))
+#endif /* ARM_MULTILIB_ARCH_V4 */
/* External Memory Controller (EMC) */
-#define EMC_BASE_ADDR 0xFFE08000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define EMC_BASE_ADDR 0xFFE08000
+#else
+ #define EMC_BASE_ADDR 0x2009c000
+#endif
#define EMC_CTRL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x000))
#define EMC_STAT (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x004))
#define EMC_CONFIG (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x008))
@@ -508,7 +556,11 @@
/* Timer 0 */
-#define TMR0_BASE_ADDR 0xE0004000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define TMR0_BASE_ADDR 0xE0004000
+#else
+ #define TMR0_BASE_ADDR 0x40004000
+#endif
#define T0IR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x00))
#define T0TCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x04))
#define T0TC (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x08))
@@ -528,7 +580,11 @@
#define T0CTCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x70))
/* Timer 1 */
-#define TMR1_BASE_ADDR 0xE0008000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define TMR1_BASE_ADDR 0xE0008000
+#else
+ #define TMR1_BASE_ADDR 0x40008000
+#endif
#define T1IR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x00))
#define T1TCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x04))
#define T1TC (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x08))
@@ -548,7 +604,11 @@
#define T1CTCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x70))
/* Timer 2 */
-#define TMR2_BASE_ADDR 0xE0070000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define TMR2_BASE_ADDR 0xE0070000
+#else
+ #define TMR2_BASE_ADDR 0x40090000
+#endif
#define T2IR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x00))
#define T2TCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x04))
#define T2TC (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x08))
@@ -568,7 +628,11 @@
#define T2CTCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x70))
/* Timer 3 */
-#define TMR3_BASE_ADDR 0xE0074000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define TMR3_BASE_ADDR 0xE0074000
+#else
+ #define TMR3_BASE_ADDR 0x40094000
+#endif
#define T3IR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x00))
#define T3TCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x04))
#define T3TC (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x08))
@@ -589,7 +653,11 @@
/* Pulse Width Modulator (PWM) */
-#define PWM0_BASE_ADDR 0xE0014000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define PWM0_BASE_ADDR 0xE0014000
+#else
+ #define PWM0_BASE_ADDR 0x40014000
+#endif
#define PWM0IR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x00))
#define PWM0TCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x04))
#define PWM0TC (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x08))
@@ -613,7 +681,11 @@
#define PWM0LER (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x50))
#define PWM0CTCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x70))
-#define PWM1_BASE_ADDR 0xE0018000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define PWM1_BASE_ADDR 0xE0018000
+#else
+ #define PWM1_BASE_ADDR 0x40018000
+#endif
#define PWM1IR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x00))
#define PWM1TCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x04))
#define PWM1TC (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x08))
@@ -639,7 +711,11 @@
/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
-#define UART0_BASE_ADDR 0xE000C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define UART0_BASE_ADDR 0xE000C000
+#else
+ #define UART0_BASE_ADDR 0x4000C000
+#endif
#define U0RBR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
#define U0THR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
#define U0DLL (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
@@ -656,7 +732,11 @@
#define U0TER (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x30))
/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
-#define UART1_BASE_ADDR 0xE0010000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define UART1_BASE_ADDR 0xE0010000
+#else
+ #define UART1_BASE_ADDR 0x40010000
+#endif
#define U1RBR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
#define U1THR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
#define U1DLL (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
@@ -674,7 +754,11 @@
#define U1TER (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x30))
/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
-#define UART2_BASE_ADDR 0xE0078000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define UART2_BASE_ADDR 0xE0078000
+#else
+ #define UART2_BASE_ADDR 0x40098000
+#endif
#define U2RBR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
#define U2THR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
#define U2DLL (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
@@ -691,7 +775,11 @@
#define U2TER (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x30))
/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
-#define UART3_BASE_ADDR 0xE007C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define UART3_BASE_ADDR 0xE007C000
+#else
+ #define UART3_BASE_ADDR 0x4009C000
+#endif
#define U3RBR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
#define U3THR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
#define U3DLL (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
@@ -708,7 +796,11 @@
#define U3TER (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x30))
/* I2C Interface 0 */
-#define I2C0_BASE_ADDR 0xE001C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define I2C0_BASE_ADDR 0xE001C000
+#else
+ #define I2C0_BASE_ADDR 0x4001C000
+#endif
#define I20CONSET (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x00))
#define I20STAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x04))
#define I20DAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x08))
@@ -718,7 +810,11 @@
#define I20CONCLR (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x18))
/* I2C Interface 1 */
-#define I2C1_BASE_ADDR 0xE005C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define I2C1_BASE_ADDR 0xE005C000
+#else
+ #define I2C1_BASE_ADDR 0x4005C000
+#endif
#define I21CONSET (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x00))
#define I21STAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x04))
#define I21DAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x08))
@@ -728,7 +824,11 @@
#define I21CONCLR (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x18))
/* I2C Interface 2 */
-#define I2C2_BASE_ADDR 0xE0080000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define I2C2_BASE_ADDR 0xE0080000
+#else
+ #define I2C2_BASE_ADDR 0x400a0000
+#endif
#define I22CONSET (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x00))
#define I22STAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x04))
#define I22DAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x08))
@@ -746,7 +846,11 @@
#define S0SPINT (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x1C))
/* SSP0 Controller */
-#define SSP0_BASE_ADDR 0xE0068000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define SSP0_BASE_ADDR 0xE0068000
+#else
+ #define SSP0_BASE_ADDR 0x40088000
+#endif
#define SSP0CR0 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x00))
#define SSP0CR1 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x04))
#define SSP0DR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x08))
@@ -759,7 +863,11 @@
#define SSP0DMACR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x24))
/* SSP1 Controller */
-#define SSP1_BASE_ADDR 0xE0030000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define SSP1_BASE_ADDR 0xE0030000
+#else
+ #define SSP1_BASE_ADDR 0x40030000
+#endif
#define SSP1CR0 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x00))
#define SSP1CR1 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x04))
#define SSP1DR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x08))
@@ -771,9 +879,29 @@
#define SSP1ICR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x20))
#define SSP1DMACR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x24))
+#ifdef ARM_MULTILIB_ARCH_V7M
+
+/* SSP2 Controller */
+#define SSP2_BASE_ADDR 0x400ac000
+#define SSP2CR0 (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x00))
+#define SSP2CR1 (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x04))
+#define SSP2DR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x08))
+#define SSP2SR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x0C))
+#define SSP2CPSR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x10))
+#define SSP2IMSC (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x14))
+#define SSP2RIS (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x18))
+#define SSP2MIS (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x1C))
+#define SSP2ICR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x20))
+#define SSP2DMACR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x24))
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
/* Real Time Clock */
-#define RTC_BASE_ADDR 0xE0024000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define RTC_BASE_ADDR 0xE0024000
+#else
+ #define RTC_BASE_ADDR 0x40024000
+#endif
#define RTC_ILR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x00))
#define RTC_CTC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x04))
#define RTC_CCR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x08))
@@ -804,7 +932,11 @@
/* A/D Converter 0 (AD0) */
-#define AD0_BASE_ADDR 0xE0034000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define AD0_BASE_ADDR 0xE0034000
+#else
+ #define AD0_BASE_ADDR 0x40034000
+#endif
#define AD0CR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x00))
#define AD0GDR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x04))
#define AD0INTEN (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x0C))
@@ -821,12 +953,20 @@
/* D/A Converter */
-#define DAC_BASE_ADDR 0xE006C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define DAC_BASE_ADDR 0xE006C000
+#else
+ #define DAC_BASE_ADDR 0x4008C000
+#endif
#define DACR (*(volatile uint32_t *) (DAC_BASE_ADDR + 0x00))
/* Watchdog */
-#define WDG_BASE_ADDR 0xE0000000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define WDG_BASE_ADDR 0xE0000000
+#else
+ #define WDG_BASE_ADDR 0x40000000
+#endif
#define WDMOD (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x00))
#define WDTC (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x04))
#define WDFEED (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x08))
@@ -834,7 +974,11 @@
#define WDCLKSEL (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x10))
/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
-#define CAN_ACCEPT_BASE_ADDR 0xE003C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define CAN_ACCEPT_BASE_ADDR 0xE003C000
+#else
+ #define CAN_ACCEPT_BASE_ADDR 0x4003C000
+#endif
#define CAN_AFMR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x00))
#define CAN_SFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x04))
#define CAN_SFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x08))
@@ -844,12 +988,20 @@
#define CAN_LUT_ERR_ADR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x18))
#define CAN_LUT_ERR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x1C))
-#define CAN_CENTRAL_BASE_ADDR 0xE0040000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define CAN_CENTRAL_BASE_ADDR 0xE0040000
+#else
+ #define CAN_CENTRAL_BASE_ADDR 0x40040000
+#endif
#define CAN_TX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x00))
#define CAN_RX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x04))
#define CAN_MSR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x08))
-#define CAN1_BASE_ADDR 0xE0044000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define CAN1_BASE_ADDR 0xE0044000
+#else
+ #define CAN1_BASE_ADDR 0x40044000
+#endif
#define CAN1MOD (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x00))
#define CAN1CMR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x04))
#define CAN1GSR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x08))
@@ -876,7 +1028,11 @@
#define CAN1TDA3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x58))
#define CAN1TDB3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x5C))
-#define CAN2_BASE_ADDR 0xE0048000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define CAN2_BASE_ADDR 0xE0048000
+#else
+ #define CAN2_BASE_ADDR 0x40048000
+#endif
#define CAN2MOD (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x00))
#define CAN2CMR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x04))
#define CAN2GSR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x08))
@@ -905,7 +1061,11 @@
/* MultiMedia Card Interface(MCI) Controller */
-#define MCI_BASE_ADDR 0xE008C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define MCI_BASE_ADDR 0xE008C000
+#else
+ #define MCI_BASE_ADDR 0x400c0000
+#endif
#define MCI_POWER (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x00))
#define MCI_CLOCK (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x04))
#define MCI_ARGUMENT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x08))
@@ -928,7 +1088,11 @@
/* I2S Interface Controller (I2S) */
-#define I2S_BASE_ADDR 0xE0088000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define I2S_BASE_ADDR 0xE0088000
+#else
+ #define I2S_BASE_ADDR 0x400a8000
+#endif
#define I2S_DAO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x00))
#define I2S_DAI (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x04))
#define I2S_TX_FIFO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x08))
@@ -942,7 +1106,11 @@
/* General-purpose DMA Controller */
-#define DMA_BASE_ADDR 0xFFE04000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define DMA_BASE_ADDR 0xFFE04000
+#else
+ #define DMA_BASE_ADDR 0x20080000
+#endif
#define GPDMA_INT_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x000))
#define GPDMA_INT_TCSTAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x004))
#define GPDMA_INT_TCCLR (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x008))
@@ -974,10 +1142,14 @@
#define GPDMA_CH1_CTRL (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x12C))
#define GPDMA_CH1_CFG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x130))
-
/* USB Controller */
-#define USB_INT_BASE_ADDR 0xE01FC1C0
-#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define USB_INT_BASE_ADDR 0xE01FC1C0
+ #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
+#else
+ #define USB_INT_BASE_ADDR 0x400fc1c0
+ #define USB_BASE_ADDR 0x2008c200
+#endif
#define USB_INT_STAT (*(volatile uint32_t *) (USB_INT_BASE_ADDR + 0x00))
@@ -1031,9 +1203,12 @@
#define SYS_ERR_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xBC))
#define SYS_ERR_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xC0))
-
/* USB Host Controller */
-#define USBHC_BASE_ADDR 0xFFE0C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define USBHC_BASE_ADDR 0xFFE0C000
+#else
+ #define USBHC_BASE_ADDR 0x2008c000
+#endif
#define HC_REVISION (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x00))
#define HC_CONTROL (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x04))
#define HC_CMD_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x08))
@@ -1059,7 +1234,11 @@
#define HC_RH_PORT_STAT2 (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x58))
/* USB OTG Controller */
-#define USBOTG_BASE_ADDR 0xFFE0C100
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define USBOTG_BASE_ADDR 0xFFE0C100
+#else
+ #define USBOTG_BASE_ADDR 0x2008c100
+#endif
#define OTG_INT_STAT (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x00))
#define OTG_INT_EN (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x04))
#define OTG_INT_SET (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x08))
@@ -1067,7 +1246,11 @@
#define OTG_STAT_CTRL (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x10))
#define OTG_TIMER (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x14))
-#define USBOTG_I2C_BASE_ADDR 0xFFE0C300
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define USBOTG_I2C_BASE_ADDR 0xFFE0C300
+#else
+ #define USBOTG_I2C_BASE_ADDR 0x2008c300
+#endif
#define OTG_I2C_RX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
#define OTG_I2C_TX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
#define OTG_I2C_STS (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x04))
@@ -1075,13 +1258,20 @@
#define OTG_I2C_CLKHI (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x0C))
#define OTG_I2C_CLKLO (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x10))
-#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
+#else
+ #define USBOTG_CLK_BASE_ADDR 0x2008cff0
+#endif
#define OTG_CLK_CTRL (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x04))
#define OTG_CLK_STAT (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x08))
-
/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
-#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
+#else
+ #define MAC_BASE_ADDR 0x20084000
+#endif
#define MAC_MAC1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
#define MAC_MAC2 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
#define MAC_IPGT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
@@ -1138,7 +1328,11 @@
/* LCD Controller */
-#define LCD_BASE_ADDR 0xFFE10000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define LCD_BASE_ADDR 0xFFE10000
+#else
+ #define LCD_BASE_ADDR 0x20088000
+#endif
#define LCD_CFG (*(volatile uint32_t *) 0xE01FC1B8)
#define LCD_TIMH (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x000))
#define LCD_TIMV (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x004))
@@ -1937,6 +2131,28 @@
/* IO */
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0)
+ #define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0)
+#else
+ #define IOCON_FUNC(val) BSP_FLD32(val, 0, 2)
+ #define IOCON_FUNC_GET(reg) BSP_FLD32GET(reg, 0, 2)
+ #define IOCON_FUNC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
+ #define IOCON_MODE(val) BSP_FLD32(val, 3, 4)
+ #define IOCON_MODE_GET(reg) BSP_FLD32GET(reg, 3, 4)
+ #define IOCON_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 3, 4)
+ #define IOCON_HYS BSP_BIT32(5)
+ #define IOCON_INV BSP_BIT32(6)
+ #define IOCON_ADMODE BSP_BIT32(7)
+ #define IOCON_FILTER BSP_BIT32(8)
+ #define IOCON_HS BSP_BIT32(8)
+ #define IOCON_SLEW BSP_BIT32(9)
+ #define IOCON_HIDRIVE BSP_BIT32(9)
+ #define IOCON_OD BSP_BIT32(10)
+ #define IOCON_DACEN BSP_BIT32(16)
+ #define LPC17XX_IOCON ((volatile uint32_t *) PINSEL_BASE_ADDR)
+#endif
+
typedef struct {
uint32_t dir;
uint32_t reserved [3];
@@ -1946,18 +2162,18 @@
uint32_t clr;
} lpc24xx_fio;
-#define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0)
-
-#define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0)
-
#define LPC24XX_FIO ((volatile lpc24xx_fio *) FIO_BASE_ADDR)
+#ifdef ARM_MULTILIB_ARCH_V4
+
/* PCONP */
#define PCONP_GPDMA (1U << 29)
#define PCONP_ETHERNET (1U << 30)
#define PCONP_USB (1U << 31)
+#endif /* ARM_MULTILIB_ARCH_V4 */
+
/* I2S */
static volatile lpc_i2s *const lpc24xx_i2s = (lpc_i2s *) I2S_BASE_ADDR;
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/include/start-config.h:1.1 rtems/c/src/lib/libbsp/arm/lpc24xx/include/start-config.h:1.2
--- rtems/c/src/lib/libbsp/arm/lpc24xx/include/start-config.h:1.1 Mon Oct 17 05:39:59 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/include/start-config.h Tue Nov 8 04:39:46 2011
@@ -26,6 +26,7 @@
#define LIBBSP_ARM_LPC24XX_START_CONFIG_H
#include <bsp.h>
+#include <bsp/io.h>
#include <bsp/start.h>
#include <bsp/lpc-emc.h>
@@ -47,6 +48,7 @@
uint32_t txsr;
uint32_t trrd;
uint32_t tmrd;
+ uint32_t emcdlyctl;
} lpc24xx_emc_dynamic_config;
typedef struct {
@@ -70,25 +72,22 @@
} config;
} lpc24xx_emc_static_chip_config;
-extern const BSP_START_DATA_SECTION uint32_t
- lpc24xx_start_config_pinsel_5_9 [];
+extern BSP_START_DATA_SECTION const lpc24xx_pin_range
+ lpc24xx_start_config_pinsel [];
-extern const BSP_START_DATA_SECTION size_t
- lpc24xx_start_config_pinsel_5_9_size;
-
-extern const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_config
+extern BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
lpc24xx_start_config_emc_dynamic [];
-extern const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_chip_config
+extern BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
lpc24xx_start_config_emc_dynamic_chip [];
-extern const BSP_START_DATA_SECTION size_t
+extern BSP_START_DATA_SECTION const size_t
lpc24xx_start_config_emc_dynamic_chip_count;
-extern const BSP_START_DATA_SECTION lpc24xx_emc_static_chip_config
+extern BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
lpc24xx_start_config_emc_static_chip [];
-extern const BSP_START_DATA_SECTION size_t
+extern BSP_START_DATA_SECTION const size_t
lpc24xx_start_config_emc_static_chip_count;
#ifdef __cplusplus
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/irq/irq-dispatch.c:1.1 rtems/c/src/lib/libbsp/arm/lpc24xx/irq/irq-dispatch.c:1.2
--- rtems/c/src/lib/libbsp/arm/lpc24xx/irq/irq-dispatch.c:1.1 Mon Aug 8 07:36:15 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/irq/irq-dispatch.c Tue Nov 8 04:39:46 2011
@@ -20,24 +20,29 @@
* http://www.rtems.com/license/LICENSE.
*/
+#include <rtems/score/armv7m.h>
+
#include <bsp.h>
+#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#include <bsp/lpc24xx.h>
void bsp_interrupt_dispatch(void)
{
- /* Read current vector number */
- rtems_vector_number vector = VICVectAddr;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ /* Read current vector number */
+ rtems_vector_number vector = VICVectAddr;
- /* Enable interrupts in program status register */
- uint32_t psr = arm_status_irq_enable();
+ /* Enable interrupts in program status register */
+ uint32_t psr = arm_status_irq_enable();
- /* Dispatch interrupt handlers */
- bsp_interrupt_handler_dispatch(vector);
+ /* Dispatch interrupt handlers */
+ bsp_interrupt_handler_dispatch(vector);
- /* Restore program status register */
- arm_status_restore(psr);
+ /* Restore program status register */
+ arm_status_restore(psr);
- /* Acknowledge interrupt */
- VICVectAddr = 0;
+ /* Acknowledge interrupt */
+ VICVectAddr = 0;
+ #endif
}
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/irq/irq.c:1.7 rtems/c/src/lib/libbsp/arm/lpc24xx/irq/irq.c:1.8
--- rtems/c/src/lib/libbsp/arm/lpc24xx/irq/irq.c:1.7 Mon Aug 8 07:36:15 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/irq/irq.c Tue Nov 8 04:39:46 2011
@@ -20,10 +20,13 @@
* http://www.rtems.com/license/LICENSE.
*/
+#include <rtems/score/armv7m.h>
+
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#include <bsp/lpc24xx.h>
+#include <bsp/linker-symbols.h>
static inline bool lpc24xx_irq_is_valid(rtems_vector_number vector)
{
@@ -37,14 +40,18 @@
priority = LPC24XX_IRQ_PRIORITY_VALUE_MAX;
}
- VICVectPriorityBase [vector] = priority;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ VICVectPriorityBase [vector] = priority;
+ #endif
}
}
unsigned lpc24xx_irq_get_priority(rtems_vector_number vector)
{
if (lpc24xx_irq_is_valid(vector)) {
- return VICVectPriorityBase [vector];
+ #ifdef ARM_MULTILIB_ARCH_V4
+ return VICVectPriorityBase [vector];
+ #endif
} else {
return LPC24XX_IRQ_PRIORITY_VALUE_MIN - 1U;
}
@@ -52,51 +59,61 @@
rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
{
- VICIntEnable = 1U << vector;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ VICIntEnable = 1U << vector;
+ #endif
return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
{
- VICIntEnClear = 1U << vector;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ VICIntEnClear = 1U << vector;
+ #endif
return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_facility_initialize(void)
{
- volatile uint32_t *addr = VICVectAddrBase;
- volatile uint32_t *prio = VICVectPriorityBase;
- rtems_vector_number i = 0;
-
- /* Disable all interrupts */
- VICIntEnClear = 0xffffffff;
-
- /* Clear all software interrupts */
- VICSoftIntClear = 0xffffffff;
-
- /* Use IRQ category */
- VICIntSelect = 0;
-
- for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
- /* Use the vector address register to store the vector number */
- addr [i] = i;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ volatile uint32_t *addr = VICVectAddrBase;
+ volatile uint32_t *prio = VICVectPriorityBase;
+ rtems_vector_number i = 0;
+
+ /* Disable all interrupts */
+ VICIntEnClear = 0xffffffff;
+
+ /* Clear all software interrupts */
+ VICSoftIntClear = 0xffffffff;
+
+ /* Use IRQ category */
+ VICIntSelect = 0;
+
+ for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
+ /* Use the vector address register to store the vector number */
+ addr [i] = i;
- /* Give vector lowest priority */
- prio [i] = 15;
- }
+ /* Give vector lowest priority */
+ prio [i] = 15;
+ }
- /* Reset priority mask register */
- VICSWPrioMask = 0xffff;
+ /* Reset priority mask register */
+ VICSWPrioMask = 0xffff;
- /* Acknowledge interrupts for all priorities */
- for (i = LPC24XX_IRQ_PRIORITY_VALUE_MIN; i <= LPC24XX_IRQ_PRIORITY_VALUE_MAX; ++i) {
- VICVectAddr = 0;
- }
+ /* Acknowledge interrupts for all priorities */
+ for (
+ i = LPC24XX_IRQ_PRIORITY_VALUE_MIN;
+ i <= LPC24XX_IRQ_PRIORITY_VALUE_MAX;
+ ++i
+ ) {
+ VICVectAddr = 0;
+ }
- /* Install the IRQ exception handler */
- _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
+ /* Install the IRQ exception handler */
+ _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
+ #endif
return RTEMS_SUCCESSFUL;
}
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/misc/bspidle.c:1.3 rtems/c/src/lib/libbsp/arm/lpc24xx/misc/bspidle.c:1.4
--- rtems/c/src/lib/libbsp/arm/lpc24xx/misc/bspidle.c:1.3 Fri Sep 18 03:05:40 2009
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/misc/bspidle.c Tue Nov 8 04:39:46 2011
@@ -1,20 +1,19 @@
/**
* @file
*
- * @author Sebastian Huber <sebastian.huber at embedded-brains.de>
- *
* @ingroup lpc24xx
*
* @brief Idle task.
*/
/*
- * Copyright (c) 2008
- * Embedded Brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * rtems at embedded-brains.de
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -27,12 +26,14 @@
void *bsp_idle_thread(uintptr_t ignored)
{
while (true) {
- /*
- * Set power mode to idle. Causes the processor clock to be stopped, while
- * on-chip peripherals remain active. Any enabled interrupt from a
- * peripheral or an external interrupt source will cause the processor to
- * resume execution.
- */
- PCON = 0x1;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ /*
+ * Set power mode to idle. Causes the processor clock to be stopped,
+ * while on-chip peripherals remain active. Any enabled interrupt from a
+ * peripheral or an external interrupt source will cause the processor to
+ * resume execution.
+ */
+ PCON = 0x1;
+ #endif
}
}
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/misc/io.c:1.9 rtems/c/src/lib/libbsp/arm/lpc24xx/misc/io.c:1.10
--- rtems/c/src/lib/libbsp/arm/lpc24xx/misc/io.c:1.9 Thu May 19 07:30:00 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/misc/io.c Tue Nov 8 04:39:46 2011
@@ -20,57 +20,62 @@
* http://www.rtems.com/license/LICENSE.
*/
+#include <bsp.h>
#include <bsp/io.h>
+#include <bsp/start.h>
#include <bsp/system-clocks.h>
-#define LPC24XX_PIN_SELECT(pin) (pin >> 4U)
+#define LPC24XX_PIN_SELECT(index) ((index) >> 4U)
-#define LPC24XX_PIN_SELECT_SHIFT(pin) ((pin & 0xfU) << 1U)
+#define LPC24XX_PIN_SELECT_SHIFT(index) (((index) & 0xfU) << 1U)
#define LPC24XX_PIN_SELECT_MASK 0x3U
rtems_status_code lpc24xx_gpio_config(
- unsigned pin,
+ unsigned index,
lpc24xx_gpio_settings settings
)
{
- if (pin <= LPC24XX_IO_INDEX_MAX) {
+ if (index <= LPC24XX_IO_INDEX_MAX) {
rtems_interrupt_level level;
- unsigned port = LPC24XX_IO_PORT(pin);
- unsigned bit = LPC24XX_IO_PORT_BIT(pin);
- unsigned select = LPC24XX_PIN_SELECT(pin);
- unsigned shift = LPC24XX_PIN_SELECT_SHIFT(pin);
- unsigned resistor = settings & LPC24XX_GPIO_RESISTOR_MASK;
- unsigned output = (settings & LPC24XX_GPIO_OUTPUT) != 0 ? 1U : 0U;
-
- /* Get resistor flags */
- switch (resistor) {
- case LPC24XX_GPIO_RESISTOR_PULL_UP:
- case LPC24XX_GPIO_RESISTOR_DEFAULT:
- resistor = 0x0U;
- break;
- case LPC24XX_GPIO_RESISTOR_NONE:
- resistor = 0x2U;
- break;
- case LPC24XX_GPIO_RESISTOR_PULL_DOWN:
- resistor = 0x3U;
- break;
- default:
- return RTEMS_INVALID_NUMBER;
- }
+ uint32_t port = LPC24XX_IO_PORT(index);
+ uint32_t port_bit = LPC24XX_IO_PORT_BIT(index);
+ uint32_t output = (settings & LPC24XX_GPIO_OUTPUT) != 0 ? 1U : 0U;
+ uint32_t resistor = settings & 0x3U;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ uint32_t select = LPC24XX_PIN_SELECT(index);
+ uint32_t shift = LPC24XX_PIN_SELECT_SHIFT(index);
+
+ /* Get resistor flags */
+ switch (resistor) {
+ case LPC24XX_GPIO_RESISTOR_PULL_UP:
+ resistor = 0x0U;
+ break;
+ case LPC24XX_GPIO_RESISTOR_NONE:
+ resistor = 0x2U;
+ break;
+ case LPC24XX_GPIO_RESISTOR_PULL_DOWN:
+ resistor = 0x3U;
+ break;
+ default:
+ return RTEMS_INVALID_NUMBER;
+ }
+ #endif
rtems_interrupt_disable(level);
- /* Resistor */
- LPC24XX_PINMODE [select] =
- (LPC24XX_PINMODE [select] & ~(LPC24XX_PIN_SELECT_MASK << shift))
- | ((resistor & LPC24XX_PIN_SELECT_MASK) << shift);
+ #ifdef ARM_MULTILIB_ARCH_V4
+ /* Resistor */
+ LPC24XX_PINMODE [select] =
+ (LPC24XX_PINMODE [select] & ~(LPC24XX_PIN_SELECT_MASK << shift))
+ | ((resistor & LPC24XX_PIN_SELECT_MASK) << shift);
+ #endif
rtems_interrupt_flash(level);
/* Input or output */
LPC24XX_FIO [port].dir =
- (LPC24XX_FIO [port].dir & ~(1U << bit)) | (output << bit);
+ (LPC24XX_FIO [port].dir & ~(1U << port_bit)) | (output << port_bit);
rtems_interrupt_enable(level);
} else {
@@ -94,27 +99,41 @@
} lpc24xx_module_entry;
static const lpc24xx_module_entry lpc24xx_module_table [] = {
- LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_ACF, 0, 1, 15),
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_ACF, 0, 1, 15),
+ #endif
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_ADC, 1, 1, 12),
- LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_BAT_RAM, 0, 1, 16),
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_BAT_RAM, 0, 1, 16),
+ #endif
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_CAN_0, 1, 1, 13),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_CAN_1, 1, 1, 14),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_DAC, 0, 1, 11),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_EMC, 1, 0, 11),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_ETHERNET, 1, 0, 30),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_GPDMA, 1, 1, 29),
- LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_GPIO, 0, 1, 17),
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_GPIO, 0, 1, 17),
+ #else
+ LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_GPIO, 0, 1, 15),
+ #endif
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2C_0, 1, 1, 7),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2C_1, 1, 1, 19),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2C_2, 1, 1, 26),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2S, 1, 1, 27),
- LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_LCD, 1, 0, 20),
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_LCD, 1, 0, 20),
+ #else
+ LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_LCD, 1, 0, 0),
+ #endif
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_MCI, 1, 1, 28),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PCB, 0, 1, 18),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PWM_0, 1, 1, 5),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PWM_1, 1, 1, 6),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_RTC, 1, 1, 9),
- LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SPI, 1, 1, 8),
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SPI, 1, 1, 8),
+ #endif
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SSP_0, 1, 1, 21),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SSP_1, 1, 1, 10),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SYSCON, 0, 1, 30),
@@ -126,8 +145,10 @@
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_1, 1, 1, 4),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_2, 1, 1, 24),
LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_3, 1, 1, 25),
- LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_USB, 1, 0, 31),
- LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_WDT, 0, 1, 0)
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_WDT, 0, 1, 0),
+ #endif
+ LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_USB, 1, 0, 31)
};
static rtems_status_code lpc24xx_module_do_enable(
@@ -145,9 +166,23 @@
return RTEMS_INVALID_ID;
}
- if ((clock & ~LPC24XX_MODULE_CLOCK_MASK) != 0U) {
- return RTEMS_INVALID_NUMBER;
- }
+ #ifdef ARM_MULTILIB_ARCH_V4
+ if (clock == LPC24XX_MODULE_PCLK_DEFAULT) {
+ #if LPC24XX_PCLKDIV == 1U
+ clock = LPC24XX_MODULE_CCLK;
+ #elif LPC24XX_PCLKDIV == 2U
+ clock = LPC24XX_MODULE_CCLK_2;
+ #elif LPC24XX_PCLKDIV == 4U
+ clock = LPC24XX_MODULE_CCLK_4;
+ #elif LPC24XX_PCLKDIV == 8U
+ clock = LPC24XX_MODULE_CCLK_8;
+ #endif
+ }
+
+ if ((clock & ~LPC24XX_MODULE_CLOCK_MASK) != 0U) {
+ return RTEMS_INVALID_CLOCK;
+ }
+ #endif
has_power = lpc24xx_module_table [module].power;
has_clock = lpc24xx_module_table [module].clock;
@@ -157,39 +192,51 @@
if (enable) {
if (has_power) {
rtems_interrupt_disable(level);
- PCONP |= 1U << index;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ PCONP |= 1U << index;
+ #endif
rtems_interrupt_enable(level);
}
if (module != LPC24XX_MODULE_USB) {
if (has_clock) {
- unsigned clock_shift = 2U * index;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ unsigned clock_shift = 2U * index;
- rtems_interrupt_disable(level);
- if (clock_shift < 32U) {
- PCLKSEL0 = (PCLKSEL0 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
- | (clock << clock_shift);
- } else {
- clock_shift -= 32U;
- PCLKSEL1 = (PCLKSEL1 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
- | (clock << clock_shift);
- }
- rtems_interrupt_enable(level);
+ rtems_interrupt_disable(level);
+ if (clock_shift < 32U) {
+ PCLKSEL0 = (PCLKSEL0 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
+ | (clock << clock_shift);
+ } else {
+ clock_shift -= 32U;
+ PCLKSEL1 = (PCLKSEL1 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
+ | (clock << clock_shift);
+ }
+ rtems_interrupt_enable(level);
+ #endif
}
} else {
- unsigned pllclk = lpc24xx_pllclk();
- unsigned usbsel = pllclk / 48000000U - 1U;
-
- if (usbsel > 15U || (usbsel % 2U != 1U) || (pllclk % 48000000U) != 0U) {
- return RTEMS_INCORRECT_STATE;
- }
+ #ifdef ARM_MULTILIB_ARCH_V4
+ unsigned pllclk = lpc24xx_pllclk();
+ unsigned usbsel = pllclk / 48000000U - 1U;
+
+ if (
+ usbsel > 15U
+ || (usbsel % 2U != 1U)
+ || (pllclk % 48000000U) != 0U
+ ) {
+ return RTEMS_INCORRECT_STATE;
+ }
- USBCLKCFG = usbsel;
+ USBCLKCFG = usbsel;
+ #endif
}
} else {
if (has_power) {
rtems_interrupt_disable(level);
- PCONP &= ~(1U << index);
+ #ifdef ARM_MULTILIB_ARCH_V4
+ PCONP &= ~(1U << index);
+ #endif
rtems_interrupt_enable(level);
}
}
@@ -213,49 +260,63 @@
}
typedef rtems_status_code (*lpc24xx_pin_visitor)(
- volatile uint32_t *pinsel,
- uint32_t pinsel_mask,
- uint32_t pinsel_value,
+ #ifdef ARM_MULTILIB_ARCH_V4
+ volatile uint32_t *pinsel,
+ uint32_t pinsel_mask,
+ uint32_t pinsel_value,
+ #endif
volatile uint32_t *fio_dir,
uint32_t fio_bit
);
-static rtems_status_code lpc24xx_pin_set_function(
- volatile uint32_t *pinsel,
- uint32_t pinsel_mask,
- uint32_t pinsel_value,
+static BSP_START_TEXT_SECTION __attribute__((flatten)) rtems_status_code
+lpc24xx_pin_set_function(
+ #ifdef ARM_MULTILIB_ARCH_V4
+ volatile uint32_t *pinsel,
+ uint32_t pinsel_mask,
+ uint32_t pinsel_value,
+ #endif
volatile uint32_t *fio_dir,
uint32_t fio_bit
)
{
- rtems_interrupt_level level;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ rtems_interrupt_level level;
- rtems_interrupt_disable(level);
- *pinsel = (*pinsel & ~pinsel_mask) | pinsel_value;
- rtems_interrupt_enable(level);
+ rtems_interrupt_disable(level);
+ *pinsel = (*pinsel & ~pinsel_mask) | pinsel_value;
+ rtems_interrupt_enable(level);
+ #endif
return RTEMS_SUCCESSFUL;
}
-static rtems_status_code lpc24xx_pin_check_function(
- volatile uint32_t *pinsel,
- uint32_t pinsel_mask,
- uint32_t pinsel_value,
+static BSP_START_TEXT_SECTION rtems_status_code lpc24xx_pin_check_function(
+ #ifdef ARM_MULTILIB_ARCH_V4
+ volatile uint32_t *pinsel,
+ uint32_t pinsel_mask,
+ uint32_t pinsel_value,
+ #endif
volatile uint32_t *fio_dir,
uint32_t fio_bit
)
{
- if ((*pinsel & pinsel_mask) == pinsel_value) {
- return RTEMS_SUCCESSFUL;
- } else {
- return RTEMS_IO_ERROR;
- }
+ #ifdef ARM_MULTILIB_ARCH_V4
+ if ((*pinsel & pinsel_mask) == pinsel_value) {
+ return RTEMS_SUCCESSFUL;
+ } else {
+ return RTEMS_IO_ERROR;
+ }
+ #endif
}
-static rtems_status_code lpc24xx_pin_set_input(
- volatile uint32_t *pinsel,
- uint32_t pinsel_mask,
- uint32_t pinsel_value,
+static BSP_START_TEXT_SECTION __attribute__((flatten)) rtems_status_code
+lpc24xx_pin_set_input(
+ #ifdef ARM_MULTILIB_ARCH_V4
+ volatile uint32_t *pinsel,
+ uint32_t pinsel_mask,
+ uint32_t pinsel_value,
+ #endif
volatile uint32_t *fio_dir,
uint32_t fio_bit
)
@@ -264,35 +325,49 @@
rtems_interrupt_disable(level);
*fio_dir &= ~fio_bit;
- *pinsel &= ~pinsel_mask;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ *pinsel &= ~pinsel_mask;
+ #endif
rtems_interrupt_enable(level);
return RTEMS_SUCCESSFUL;
}
-static rtems_status_code lpc24xx_pin_check_input(
- volatile uint32_t *pinsel,
- uint32_t pinsel_mask,
- uint32_t pinsel_value,
+static BSP_START_TEXT_SECTION rtems_status_code lpc24xx_pin_check_input(
+ #ifdef ARM_MULTILIB_ARCH_V4
+ volatile uint32_t *pinsel,
+ uint32_t pinsel_mask,
+ uint32_t pinsel_value,
+ #endif
volatile uint32_t *fio_dir,
uint32_t fio_bit
)
{
- if ((*pinsel & pinsel_mask) == 0 && (*fio_dir & fio_bit) == 0) {
- return RTEMS_SUCCESSFUL;
- } else {
- return RTEMS_IO_ERROR;
+ rtems_status_code sc = RTEMS_IO_ERROR;
+ bool is_input = (*fio_dir & fio_bit) == 0;
+
+ if (is_input) {
+ #ifdef ARM_MULTILIB_ARCH_V4
+ bool is_gpio = (*pinsel & pinsel_mask) == 0;
+ #endif
+
+ if (is_gpio) {
+ sc = RTEMS_SUCCESSFUL;
+ }
}
+
+ return sc;
}
-static const lpc24xx_pin_visitor lpc24xx_pin_visitors [] = {
+static BSP_START_DATA_SECTION const lpc24xx_pin_visitor
+ lpc24xx_pin_visitors [] = {
[LPC24XX_PIN_SET_FUNCTION] = lpc24xx_pin_set_function,
[LPC24XX_PIN_CHECK_FUNCTION] = lpc24xx_pin_check_function,
[LPC24XX_PIN_SET_INPUT] = lpc24xx_pin_set_input,
[LPC24XX_PIN_CHECK_INPUT] = lpc24xx_pin_check_input
};
-rtems_status_code lpc24xx_pin_config(
+BSP_START_TEXT_SECTION rtems_status_code lpc24xx_pin_config(
const lpc24xx_pin_range *pins,
lpc24xx_pin_action action
)
@@ -302,29 +377,42 @@
if ((unsigned) action <= LPC24XX_PIN_CHECK_INPUT) {
lpc24xx_pin_visitor visitor = lpc24xx_pin_visitors [action];
lpc24xx_pin_range terminal = LPC24XX_PIN_TERMINAL;
+ lpc24xx_pin_range pin_range = *pins;
+ uint32_t previous_port_bit = pin_range.fields.port_bit;
- while (sc == RTEMS_SUCCESSFUL && pins->value != terminal.value) {
- uint32_t port = pins->fields.port;
- uint32_t index = pins->fields.index_begin;
- uint32_t last = pins->fields.index_last;
- uint32_t function = pins->fields.function;
+ while (sc == RTEMS_SUCCESSFUL && pin_range.value != terminal.value) {
+ uint32_t port = pin_range.fields.port;
+ uint32_t port_bit = pin_range.fields.port_bit;
+ uint32_t port_bit_last = port_bit;
+ uint32_t range = pin_range.fields.range;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ uint32_t function = pin_range.fields.function;
+ #endif
volatile uint32_t *fio_dir = &LPC24XX_FIO [port].dir;
- while (sc == RTEMS_SUCCESSFUL && index <= last) {
- uint32_t pin = LPC24XX_IO_INDEX_BY_PORT(port, index);
- uint32_t select = LPC24XX_PIN_SELECT(pin);
- uint32_t shift = LPC24XX_PIN_SELECT_SHIFT(pin);
- volatile uint32_t *pinsel = &LPC24XX_PINSEL [select];
- uint32_t pinsel_mask = LPC24XX_PIN_SELECT_MASK << shift;
- uint32_t pinsel_value = (function & LPC24XX_PIN_SELECT_MASK) << shift;
- uint32_t fio_bit = 1U << index;
+ if (range) {
+ port_bit = previous_port_bit;
+ }
+
+ while (sc == RTEMS_SUCCESSFUL && port_bit <= port_bit_last) {
+ uint32_t index = LPC24XX_IO_INDEX_BY_PORT(port, port_bit);
+ uint32_t fio_bit = 1U << port_bit;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ uint32_t select = LPC24XX_PIN_SELECT(index);
+ uint32_t shift = LPC24XX_PIN_SELECT_SHIFT(index);
+ volatile uint32_t *pinsel = &LPC24XX_PINSEL [select];
+ uint32_t pinsel_mask = LPC24XX_PIN_SELECT_MASK << shift;
+ uint32_t pinsel_value = (function & LPC24XX_PIN_SELECT_MASK) << shift;
- sc = (*visitor)(pinsel, pinsel_mask, pinsel_value, fio_dir, fio_bit);
+ sc = (*visitor)(pinsel, pinsel_mask, pinsel_value, fio_dir, fio_bit);
+ #endif
- ++index;
+ ++port_bit;
}
++pins;
+ previous_port_bit = port_bit;
+ pin_range = *pins;
}
} else {
sc = RTEMS_NOT_DEFINED;
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/misc/lcd.c:1.2 rtems/c/src/lib/libbsp/arm/lpc24xx/misc/lcd.c:1.3
--- rtems/c/src/lib/libbsp/arm/lpc24xx/misc/lcd.c:1.2 Thu May 19 07:30:00 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/misc/lcd.c Tue Nov 8 04:39:46 2011
@@ -24,10 +24,13 @@
#include <bsp/lpc24xx.h>
#include <bsp/lcd.h>
+#include <bsp/lpc-lcd.h>
#include <bsp/utility.h>
#include <bsp/system-clocks.h>
-#define LCD_ENABLE BSP_BIT32(0)
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define LCD_ENABLE BSP_BIT32(0)
+#endif
rtems_status_code lpc24xx_lcd_set_mode(
lpc24xx_lcd_mode mode,
@@ -61,7 +64,9 @@
sc = lpc24xx_module_enable(LPC24XX_MODULE_LCD, LPC24XX_MODULE_PCLK_DEFAULT);
assert(sc == RTEMS_SUCCESSFUL);
- PINSEL11 = BSP_FLD32(mode, 1, 3) | LCD_ENABLE;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ PINSEL11 = BSP_FLD32(mode, 1, 3) | LCD_ENABLE;
+ #endif
sc = lpc24xx_pin_config(pins, LPC24XX_PIN_SET_FUNCTION);
assert(sc == RTEMS_SUCCESSFUL);
@@ -83,7 +88,9 @@
sc = lpc24xx_pin_config(pins, LPC24XX_PIN_SET_INPUT);
assert(sc == RTEMS_SUCCESSFUL);
- PINSEL11 = 0;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ PINSEL11 = 0;
+ #endif
sc = lpc24xx_module_disable(LPC24XX_MODULE_LCD);
assert(sc == RTEMS_SUCCESSFUL);
@@ -95,11 +102,13 @@
lpc24xx_lcd_mode lpc24xx_lcd_current_mode(void)
{
- uint32_t pinsel11 = PINSEL11;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ uint32_t pinsel11 = PINSEL11;
- if ((PCONP & BSP_BIT32(20)) != 0 && (pinsel11 & LCD_ENABLE) != 0) {
- return BSP_FLD32GET(pinsel11, 1, 3);
- } else {
- return LCD_MODE_DISABLED;
- }
+ if ((PCONP & BSP_BIT32(20)) != 0 && (pinsel11 & LCD_ENABLE) != 0) {
+ return BSP_FLD32GET(pinsel11, 1, 3);
+ } else {
+ return LCD_MODE_DISABLED;
+ }
+ #endif
}
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/misc/restart.c:1.1 rtems/c/src/lib/libbsp/arm/lpc24xx/misc/restart.c:1.2
--- rtems/c/src/lib/libbsp/arm/lpc24xx/misc/restart.c:1.1 Mon Feb 21 06:56:34 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/misc/restart.c Tue Nov 8 04:39:46 2011
@@ -28,16 +28,18 @@
void bsp_restart(void *addr)
{
- ARM_SWITCH_REGISTERS;
- rtems_interrupt_level level;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ ARM_SWITCH_REGISTERS;
+ rtems_interrupt_level level;
- rtems_interrupt_disable(level);
+ rtems_interrupt_disable(level);
- asm volatile (
- ARM_SWITCH_TO_ARM
- "mov pc, %[addr]\n"
- ARM_SWITCH_BACK
- : ARM_SWITCH_OUTPUT
- : [addr] "r" (addr)
- );
+ asm volatile (
+ ARM_SWITCH_TO_ARM
+ "mov pc, %[addr]\n"
+ ARM_SWITCH_BACK
+ : ARM_SWITCH_OUTPUT
+ : [addr] "r" (addr)
+ );
+ #endif
}
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c:1.12 rtems/c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c:1.13
--- rtems/c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c:1.12 Fri Nov 12 07:45:33 2010
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c Tue Nov 8 04:39:46 2011
@@ -7,15 +7,19 @@
*/
/*
- * Copyright (c) 2008
- * Embedded Brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * rtems at embedded-brains.de
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
- * The license and distribution terms for this file may be found in the file
- * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
*/
#include <bsp.h>
@@ -62,7 +66,7 @@
void lpc24xx_micro_seconds_delay(unsigned us)
{
unsigned start = lpc24xx_timer();
- unsigned delay = us * (LPC24XX_CCLK / 1000000);
+ unsigned delay = us * (LPC24XX_PCLK / 1000000);
unsigned elapsed = 0;
do {
@@ -72,46 +76,50 @@
unsigned lpc24xx_pllclk(void)
{
- unsigned clksrc = GET_CLKSRCSEL_CLKSRC(CLKSRCSEL);
- unsigned pllinclk = 0;
- unsigned pllclk = 0;
-
- /* Get PLL input frequency */
- switch (clksrc) {
- case 0:
- pllinclk = LPC24XX_OSCILLATOR_INTERNAL;
- break;
- case 1:
- pllinclk = LPC24XX_OSCILLATOR_MAIN;
- break;
- case 2:
- pllinclk = LPC24XX_OSCILLATOR_RTC;
- break;
- default:
- return 0;
- }
-
- /* Get PLL output frequency */
- if ((PLLSTAT & PLLSTAT_PLLC) != 0) {
- uint32_t pllcfg = PLLCFG;
- unsigned n = GET_PLLCFG_NSEL(pllcfg) + 1;
- unsigned m = GET_PLLCFG_MSEL(pllcfg) + 1;
-
- pllclk = (pllinclk / n) * 2 * m;
- } else {
- pllclk = pllinclk;
- }
+ #ifdef ARM_MULTILIB_ARCH_V4
+ unsigned clksrc = GET_CLKSRCSEL_CLKSRC(CLKSRCSEL);
+ unsigned pllinclk = 0;
+ unsigned pllclk = 0;
+
+ /* Get PLL input frequency */
+ switch (clksrc) {
+ case 0:
+ pllinclk = LPC24XX_OSCILLATOR_INTERNAL;
+ break;
+ case 1:
+ pllinclk = LPC24XX_OSCILLATOR_MAIN;
+ break;
+ case 2:
+ pllinclk = LPC24XX_OSCILLATOR_RTC;
+ break;
+ default:
+ return 0;
+ }
+
+ /* Get PLL output frequency */
+ if ((PLLSTAT & PLLSTAT_PLLC) != 0) {
+ uint32_t pllcfg = PLLCFG;
+ unsigned n = GET_PLLCFG_NSEL(pllcfg) + 1;
+ unsigned m = GET_PLLCFG_MSEL(pllcfg) + 1;
+
+ pllclk = (pllinclk / n) * 2 * m;
+ } else {
+ pllclk = pllinclk;
+ }
+ #endif
return pllclk;
}
unsigned lpc24xx_cclk(void)
{
- /* Get PLL output frequency */
- unsigned pllclk = lpc24xx_pllclk();
-
- /* Get CPU frequency */
- unsigned cclk = pllclk / (GET_CCLKCFG_CCLKSEL(CCLKCFG) + 1);
+ #ifdef ARM_MULTILIB_ARCH_V4
+ /* Get PLL output frequency */
+ unsigned pllclk = lpc24xx_pllclk();
+
+ /* Get CPU frequency */
+ unsigned cclk = pllclk / (GET_CCLKCFG_CCLKSEL(CCLKCFG) + 1);
+ #endif
return cclk;
}
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/preinstall.am:1.23 rtems/c/src/lib/libbsp/arm/lpc24xx/preinstall.am:1.24
--- rtems/c/src/lib/libbsp/arm/lpc24xx/preinstall.am:1.23 Mon Oct 17 05:39:59 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/preinstall.am Tue Nov 8 04:39:46 2011
@@ -121,6 +121,10 @@
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lcd.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lcd.h
+$(PROJECT_INCLUDE)/bsp/lpc17xx.h: include/lpc17xx.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc17xx.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc17xx.h
+
$(PROJECT_INCLUDE)/bsp/lpc24xx.h: include/lpc24xx.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc24xx.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc24xx.h
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/ssp/ssp.c:1.7 rtems/c/src/lib/libbsp/arm/lpc24xx/ssp/ssp.c:1.8
--- rtems/c/src/lib/libbsp/arm/lpc24xx/ssp/ssp.c:1.7 Thu May 20 09:23:13 2010
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/ssp/ssp.c Tue Nov 8 04:39:46 2011
@@ -25,6 +25,7 @@
#include <bsp/irq.h>
#include <bsp/system-clocks.h>
#include <bsp/dma.h>
+#include <bsp/io.h>
#define RTEMS_STATUS_CHECKS_USE_PRINTK
@@ -181,6 +182,7 @@
unsigned pclk = lpc24xx_cclk();
unsigned pre =
((pclk + LPC24XX_SSP_BAUD_RATE - 1) / LPC24XX_SSP_BAUD_RATE + 1) & ~1U;
+ lpc24xx_module module = LPC24XX_MODULE_SSP_0;
rtems_vector_number vector = UINT32_MAX;
if (lpc24xx_ssp_dma_data.status == LPC24XX_SSP_DMA_NOT_INITIALIZED) {
@@ -213,26 +215,23 @@
/* Disable module */
regs->cr1 = 0;
- /* Set clock select and get vector number */
switch ((uintptr_t) regs) {
case SSP0_BASE_ADDR:
- rtems_interrupt_disable(level);
- PCLKSEL1 = SET_PCLKSEL1_PCLK_SSP0(PCLKSEL1, 1);
- rtems_interrupt_enable(level);
-
+ module = LPC24XX_MODULE_SSP_0;
vector = LPC24XX_IRQ_SPI_SSP_0;
break;
case SSP1_BASE_ADDR:
- rtems_interrupt_disable(level);
- PCLKSEL0 = SET_PCLKSEL0_PCLK_SSP1(PCLKSEL0, 1);
- rtems_interrupt_enable(level);
-
+ module = LPC24XX_MODULE_SSP_1;
vector = LPC24XX_IRQ_SSP_1;
break;
default:
return RTEMS_IO_ERROR;
}
+ /* Set clock select */
+ sc = lpc24xx_module_enable(module, LPC24XX_MODULE_PCLK_DEFAULT);
+ RTEMS_CHECK_SC(sc, "enable module clock");
+
/* Set serial clock rate to save value */
regs->cr0 = SET_SSP_CR0_SCR(0, 255);
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c:1.3 rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c:1.4
--- rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c:1.3 Tue Dec 15 09:20:46 2009
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c Tue Nov 8 04:39:46 2011
@@ -22,19 +22,22 @@
#include <bsp/bootcard.h>
#include <bsp/lpc24xx.h>
+#include <bsp/start.h>
-void bsp_reset(void)
+BSP_START_TEXT_SECTION __attribute__((flatten)) void bsp_reset(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
- /* Trigger watchdog reset */
- WDCLKSEL = 0;
- WDTC = 0xff;
- WDMOD = 0x3;
- WDFEED = 0xaa;
- WDFEED = 0x55;
+ #ifdef ARM_MULTILIB_ARCH_V4
+ /* Trigger watchdog reset */
+ WDCLKSEL = 0;
+ WDTC = 0xff;
+ WDMOD = 0x3;
+ WDFEED = 0xaa;
+ WDFEED = 0x55;
+ #endif
while (true) {
/* Do nothing */
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c:1.10 rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c:1.11
--- rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c:1.10 Thu May 19 07:30:00 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c Tue Nov 8 04:39:46 2011
@@ -71,7 +71,7 @@
LPC24XX_PIN_TERMINAL
};
- lpc24xx_module_enable(LPC24XX_MODULE_UART_0, LPC24XX_MODULE_CCLK);
+ lpc24xx_module_enable(LPC24XX_MODULE_UART_0, LPC24XX_MODULE_PCLK_DEFAULT);
lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION);
BSP_CONSOLE_UART_INIT(lpc24xx_cclk() / 16 / LPC24XX_UART_BAUD);
#endif
@@ -80,7 +80,7 @@
void bsp_start(void)
{
/* Initialize Timer 1 */
- lpc24xx_module_enable(LPC24XX_MODULE_TIMER_1, LPC24XX_MODULE_CCLK);
+ lpc24xx_module_enable(LPC24XX_MODULE_TIMER_1, LPC24XX_MODULE_PCLK_DEFAULT);
/* Initialize standard timer */
lpc24xx_timer_initialize();
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c:1.10 rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c:1.11
--- rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c:1.10 Mon Oct 17 05:39:59 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c Tue Nov 8 04:39:46 2011
@@ -22,14 +22,16 @@
#include <stdbool.h>
+#include <rtems/score/armv7m.h>
+
#include <bspopts.h>
+#include <bsp/io.h>
#include <bsp/start.h>
-#include <bsp/linker-symbols.h>
#include <bsp/lpc24xx.h>
#include <bsp/lpc-emc.h>
#include <bsp/start-config.h>
-static void BSP_START_TEXT_SECTION lpc24xx_cpu_delay(unsigned ticks)
+static BSP_START_TEXT_SECTION void lpc24xx_cpu_delay(unsigned ticks)
{
unsigned i = 0;
@@ -41,21 +43,20 @@
}
}
-static void BSP_START_TEXT_SECTION lpc24xx_udelay(unsigned us)
+static BSP_START_TEXT_SECTION void lpc24xx_udelay(unsigned us)
{
lpc24xx_cpu_delay(us * (LPC24XX_CCLK / 1000000));
}
-static void BSP_START_TEXT_SECTION lpc24xx_init_emc_pinsel(void)
+static BSP_START_TEXT_SECTION void lpc24xx_init_pinsel(void)
{
- bsp_start_memcpy(
- (int *) &PINSEL5,
- (const int *) &lpc24xx_start_config_pinsel_5_9,
- lpc24xx_start_config_pinsel_5_9_size
+ lpc24xx_pin_config(
+ &lpc24xx_start_config_pinsel [0],
+ LPC24XX_PIN_SET_FUNCTION
);
}
-static void BSP_START_TEXT_SECTION lpc24xx_init_emc_static(void)
+static BSP_START_TEXT_SECTION void lpc24xx_init_emc_static(void)
{
size_t i = 0;
size_t chip_count = lpc24xx_start_config_emc_static_chip_count;
@@ -79,13 +80,7 @@
}
}
-static void BSP_START_TEXT_SECTION lpc24xx_init_emc_memory_map(void)
-{
- /* Use normal memory map */
- EMC_CTRL &= ~0x2U;
-}
-
-static void BSP_START_TEXT_SECTION lpc24xx_init_emc_dynamic(void)
+static BSP_START_TEXT_SECTION void lpc24xx_init_emc_dynamic(void)
{
size_t chip_count = lpc24xx_start_config_emc_dynamic_chip_count;
@@ -159,12 +154,26 @@
chip_select->config = config | EMC_DYN_CFG_B;
}
- emc->dynamiccontrol = dynamiccontrol;
+ emc->dynamiccontrol = 0;
}
}
}
-static void BSP_START_TEXT_SECTION lpc24xx_pll_config(
+static BSP_START_TEXT_SECTION void lpc24xx_init_main_oscillator(void)
+{
+ #ifdef ARM_MULTILIB_ARCH_V4
+ if ((SCS & 0x40) == 0) {
+ SCS |= 0x20;
+ while ((SCS & 0x40) == 0) {
+ /* Wait */
+ }
+ }
+ #endif
+}
+
+#ifdef ARM_MULTILIB_ARCH_V4
+
+static BSP_START_TEXT_SECTION void lpc24xx_pll_config(
uint32_t val
)
{
@@ -187,7 +196,7 @@
* @param cclksel Selects the divide value for creating the CPU clock (CCLK)
* from the PLL output.
*/
-static void BSP_START_TEXT_SECTION lpc24xx_set_pll(
+static BSP_START_TEXT_SECTION void lpc24xx_set_pll(
unsigned clksrc,
unsigned nsel,
unsigned msel,
@@ -243,151 +252,133 @@
lpc24xx_pll_config(PLLCON_PLLE | PLLCON_PLLC);
}
-static void BSP_START_TEXT_SECTION lpc24xx_init_pll(void)
-{
- /* Enable main oscillator */
- if ((SCS & 0x40) == 0) {
- SCS |= 0x20;
- while ((SCS & 0x40) == 0) {
- /* Wait */
- }
- }
+#endif /* ARM_MULTILIB_ARCH_V4 */
- /* Set PLL */
- #if LPC24XX_OSCILLATOR_MAIN == 12000000U
- #if LPC24XX_CCLK == 72000000U
- lpc24xx_set_pll(1, 0, 11, 3);
- #elif LPC24XX_CCLK == 51612800U
- lpc24xx_set_pll(1, 30, 399, 5);
- #else
- #error "unexpected CCLK"
- #endif
- #elif LPC24XX_OSCILLATOR_MAIN == 3686400U
- #if LPC24XX_CCLK == 58982400U
- lpc24xx_set_pll(1, 0, 47, 5);
+static BSP_START_TEXT_SECTION void lpc24xx_init_pll(void)
+{
+ #ifdef ARM_MULTILIB_ARCH_V4
+ #if LPC24XX_OSCILLATOR_MAIN == 12000000U
+ #if LPC24XX_CCLK == 72000000U
+ lpc24xx_set_pll(1, 0, 11, 3);
+ #elif LPC24XX_CCLK == 51612800U
+ lpc24xx_set_pll(1, 30, 399, 5);
+ #else
+ #error "unexpected CCLK"
+ #endif
+ #elif LPC24XX_OSCILLATOR_MAIN == 3686400U
+ #if LPC24XX_CCLK == 58982400U
+ lpc24xx_set_pll(1, 0, 47, 5);
+ #else
+ #error "unexpected CCLK"
+ #endif
#else
- #error "unexpected CCLK"
+ #error "unexpected main oscillator frequency"
#endif
- #else
- #error "unexpected main oscillator frequency"
#endif
}
-static void BSP_START_TEXT_SECTION lpc24xx_clear_bss(void)
+static BSP_START_TEXT_SECTION void lpc24xx_init_memory_map(void)
{
- const int *end = (const int *) bsp_section_bss_end;
- int *out = (int *) bsp_section_bss_begin;
-
- /* Clear BSS */
- while (out != end) {
- *out = 0;
- ++out;
- }
-}
+ #ifdef ARM_MULTILIB_ARCH_V4
+ /* Re-map interrupt vectors to internal RAM */
+ MEMMAP = SET_MEMMAP_MAP(MEMMAP, 2);
+ #endif
-void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
-{
- lpc24xx_init_pll();
- lpc24xx_init_emc_pinsel();
- lpc24xx_init_emc_static();
+ /* Use normal memory map */
+ EMC_CTRL &= ~0x2U;
}
-void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
+static BSP_START_TEXT_SECTION void lpc24xx_init_memory_accelerator(void)
{
- /* Re-map interrupt vectors to internal RAM */
- MEMMAP = SET_MEMMAP_MAP(MEMMAP, 2);
+ #ifdef ARM_MULTILIB_ARCH_V4
+ /* Fully enable memory accelerator module functions (MAM) */
+ MAMCR = 0;
+ #if LPC24XX_CCLK <= 20000000U
+ MAMTIM = 0x1;
+ #elif LPC24XX_CCLK <= 40000000U
+ MAMTIM = 0x2;
+ #elif LPC24XX_CCLK <= 60000000U
+ MAMTIM = 0x3;
+ #else
+ MAMTIM = 0x4;
+ #endif
+ MAMCR = 0x2;
- /* Fully enable memory accelerator module functions (MAM) */
- MAMCR = 0;
- #if LPC24XX_CCLK <= 20000000U
- MAMTIM = 0x1;
- #elif LPC24XX_CCLK <= 40000000U
- MAMTIM = 0x2;
- #elif LPC24XX_CCLK <= 60000000U
- MAMTIM = 0x3;
- #else
- MAMTIM = 0x4;
+ /* Enable fast IO for ports 0 and 1 */
+ SCS |= 0x1;
#endif
- MAMCR = 0x2;
-
- /* Enable fast IO for ports 0 and 1 */
- SCS |= 0x1;
-
- /* Set fast IO */
- FIO0DIR = 0;
- FIO1DIR = 0;
- FIO2DIR = 0;
- FIO3DIR = 0;
- FIO4DIR = 0;
- FIO0CLR = 0xffffffff;
- FIO1CLR = 0xffffffff;
- FIO2CLR = 0xffffffff;
- FIO3CLR = 0xffffffff;
- FIO4CLR = 0xffffffff;
-
- lpc24xx_init_emc_memory_map();
- lpc24xx_init_emc_dynamic();
+}
+static BSP_START_TEXT_SECTION void lpc24xx_stop_gpdma(void)
+{
#ifdef LPC24XX_STOP_GPDMA
- if ((PCONP & PCONP_GPDMA) != 0) {
+ #ifdef ARM_MULTILIB_ARCH_V4
+ bool has_power = (PCONP & PCONP_GPDMA) != 0;
+ #endif
+
+ if (has_power) {
GPDMA_CONFIG = 0;
- PCONP &= ~PCONP_GPDMA;
+
+ #ifdef ARM_MULTILIB_ARCH_V4
+ PCONP &= ~PCONP_GPDMA;
+ #endif
}
#endif
+}
+static BSP_START_TEXT_SECTION void lpc24xx_stop_ethernet(void)
+{
#ifdef LPC24XX_STOP_ETHERNET
- if ((PCONP & PCONP_ETHERNET) != 0) {
+ #ifdef ARM_MULTILIB_ARCH_V4
+ bool has_power = (PCONP & PCONP_ETHERNET) != 0;
+ #endif
+
+ if (has_power) {
MAC_COMMAND = 0x38;
MAC_MAC1 = 0xcf00;
MAC_MAC1 = 0;
- PCONP &= ~PCONP_ETHERNET;
+
+ #ifdef ARM_MULTILIB_ARCH_V4
+ PCONP &= ~PCONP_ETHERNET;
+ #endif
}
#endif
+}
+static BSP_START_TEXT_SECTION void lpc24xx_stop_usb(void)
+{
#ifdef LPC24XX_STOP_USB
- if ((PCONP & PCONP_USB) != 0) {
+ #ifdef ARM_MULTILIB_ARCH_V4
+ bool has_power = (PCONP & PCONP_USB) != 0;
+ #endif
+
+ if (has_power) {
OTG_CLK_CTRL = 0;
- PCONP &= ~PCONP_USB;
+
+ #ifdef ARM_MULTILIB_ARCH_V4
+ PCONP &= ~PCONP_USB;
+ #endif
}
#endif
+}
- /* Copy .text section */
- bsp_start_memcpy(
- (int *) bsp_section_text_begin,
- (const int *) bsp_section_text_load_begin,
- (size_t) bsp_section_text_size
- );
-
- /* Copy .rodata section */
- bsp_start_memcpy(
- (int *) bsp_section_rodata_begin,
- (const int *) bsp_section_rodata_load_begin,
- (size_t) bsp_section_rodata_size
- );
-
- /* Copy .data section */
- bsp_start_memcpy(
- (int *) bsp_section_data_begin,
- (const int *) bsp_section_data_load_begin,
- (size_t) bsp_section_data_size
- );
-
- /* Copy .fast_text section */
- bsp_start_memcpy(
- (int *) bsp_section_fast_text_begin,
- (const int *) bsp_section_fast_text_load_begin,
- (size_t) bsp_section_fast_text_size
- );
-
- /* Copy .fast_data section */
- bsp_start_memcpy(
- (int *) bsp_section_fast_data_begin,
- (const int *) bsp_section_fast_data_load_begin,
- (size_t) bsp_section_fast_data_size
- );
+BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
+{
+ lpc24xx_init_main_oscillator();
+ lpc24xx_init_pll();
+ lpc24xx_init_pinsel();
+ lpc24xx_init_emc_static();
+}
- /* Clear .bss section */
- lpc24xx_clear_bss();
+BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
+{
+ lpc24xx_init_memory_map();
+ lpc24xx_init_memory_accelerator();
+ lpc24xx_init_emc_dynamic();
+ lpc24xx_stop_gpdma();
+ lpc24xx_stop_ethernet();
+ lpc24xx_stop_usb();
+ bsp_start_copy_sections();
/* At this point we can use objects outside the .start section */
}
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c:1.1 rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c:1.2
--- rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c:1.1 Mon Oct 17 05:40:00 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c Tue Nov 8 04:39:46 2011
@@ -25,9 +25,9 @@
#include <bsp/start-config.h>
#include <bsp/lpc24xx.h>
-const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_config
+BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
lpc24xx_start_config_emc_dynamic [] = {
-#if defined(LPC24XX_EMC_MICRON)
+#if defined(LPC24XX_EMC_MT48LC4M16A2)
/* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
{
/* Auto-refresh command every 15.6 us */
@@ -69,6 +69,48 @@
/* Load mode register to active or refresh command period 2 tCK */
.tmrd = 1
}
+#elif defined(LPC24XX_EMC_W9825G2JB75I)
+ /* Dynamic Memory 0: Winbond W9825G2JB75I at 51612800Hz (tCK = 19.4ns) */
+ {
+ /* (n * 16) clock cycles -> 15.5us <= 15.6 us */
+ .refresh = 50,
+
+ /* Use command delayed strategy */
+ .readconfig = 1,
+
+ /* (n + 1) clock cycles -> 38.8ns >= 20ns */
+ .trp = 1,
+
+ /* (n + 1) clock cycles -> 58.1ns >= 45ns */
+ .tras = 2,
+
+ /* (n + 1) clock cycles -> 77.5ns >= 75ns (tXSR) */
+ .tsrex = 3,
+
+ /* (n + 1) clock cycles -> 38.8ns >= 20ns (tRCD) */
+ .tapr = 1,
+
+ /* n clock cycles -> 77.5ns >= tWR + tRP -> 2 * tCK + 20ns */
+ .tdal = 4,
+
+ /* (n + 1) clock cycles == 2 * tCK */
+ .twr = 1,
+
+ /* (n + 1) clock cycles = 77.5ns >= 65ns */
+ .trc = 3,
+
+ /* (n + 1) clock cycles = 77.5ns >= 65ns (tRC) */
+ .trfc = 3,
+
+ /* (n + 1) clock cycles = 77.5ns >= 75ns */
+ .txsr = 3,
+
+ /* (n + 1) clock cycles == 2 * tCK */
+ .trrd = 1,
+
+ /* (n + 1) clock cycles == 2 * tCK (tRSC)*/
+ .tmrd = 1
+ }
#elif defined(LPC24XX_EMC_K4S561632E)
{
.refresh = 35,
@@ -85,24 +127,103 @@
.trrd = 3,
.tmrd = 2
}
+#elif defined(LPC24XX_EMC_IS42S32800B)
+ #if LPC24XX_EMCCLK == 72000000U
+ {
+ /* tCK = 13.888ns at 72MHz */
+
+ /* (n * 16) clock cycles -> 15.556us <= 15.6us */
+ .refresh = 70,
+
+ .readconfig = 1,
+
+ /* (n + 1) clock cycles -> 27.8ns >= 20ns */
+ .trp = 1,
+
+ /* (n + 1) clock cycles -> 55.5ns >= 45ns */
+ .tras = 3,
+
+ /* (n + 1) clock cycles -> 69.4ns >= 70ns (tRC) */
+ .tsrex = 5,
+
+ /* (n + 1) clock cycles -> 41.7ns >= FIXME */
+ .tapr = 2,
+
+ /* n clock cycles -> 55.5ns >= tWR + tRP = 47.8ns */
+ .tdal = 4,
+
+ /* (n + 1) clock cycles == 2 * tCK */
+ .twr = 1,
+
+ /* (n + 1) clock cycles -> 83.3ns >= 70ns */
+ .trc = 5,
+
+ /* (n + 1) clock cycles -> 83.3ns >= 70ns */
+ .trfc = 5,
+
+ /* (n + 1) clock cycles -> 69.4ns >= 70ns (tRC) */
+ .txsr = 5,
+
+ /* (n + 1) clock cycles -> 27.8ns >= 14ns */
+ .trrd = 1,
+
+ /* (n + 1) clock cycles == 2 * tCK */
+ .tmrd = 1,
+
+ /* FIXME */
+ .emcdlyctl = 0x1112
+ }
+ #elif LPC24XX_EMCCLK == 60000000U
+ {
+ .refresh = 0x3a,
+ .readconfig = 1,
+ .trp = 1,
+ .tras = 3,
+ .tsrex = 5,
+ .tapr = 2,
+ .tdal = 3,
+ .twr = 1,
+ .trc = 4,
+ .trfc = 4,
+ .txsr = 5,
+ .trrd = 1,
+ .tmrd = 1,
+ .emcdlyctl = 0x1112
+ }
+ #else
+ #error "unexpected EMCCLK"
+ #endif
#endif
};
-const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_chip_config
+BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
lpc24xx_start_config_emc_dynamic_chip [] = {
-#if defined(LPC24XX_EMC_MICRON)
+#if defined(LPC24XX_EMC_MT48LC4M16A2)
{
.chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
/*
* Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected
- * writes.
+ * writes. 4 banks, 12 row lines, 8 column lines.
*/
.config = 0x280,
.rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
.mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
}
+#elif defined(LPC24XX_EMC_W9825G2JB75I)
+ {
+ .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
+
+ /* 32-bit data bus, 4 banks, 12 row lines, 9 column lines, RBC */
+ .config = 0x4280,
+
+ /* RAS based on tRCD = 20ns */
+ .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
+
+ /* CAS 2, burst length 8, */
+ .mode = 0xa0000000 | (0x23 << (2 + 2 + 9))
+ }
#elif defined(LPC24XX_EMC_K4S561632E)
{
.chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
@@ -110,10 +231,27 @@
.rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
.mode = 0xa0000000 | (0x33 << 12)
}
+#elif defined(LPC24XX_EMC_IS42S32800B)
+ {
+ .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
+
+ /* 256MBit, 8Mx32, 4 banks, row = 12, column = 9, RBC */
+ .config = 0x4480,
+
+ #if LPC24XX_EMCCLK == 72000000U
+ .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
+ .mode = 0xa0000000 | (0x32 << (2 + 2 + 9))
+ #elif LPC24XX_EMCCLK == 60000000U
+ .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
+ .mode = 0xa0000000 | (0x22 << (2 + 2 + 9))
+ #else
+ #error "unexpected EMCCLK"
+ #endif
+ }
#endif
};
-const BSP_START_DATA_SECTION size_t
+BSP_START_DATA_SECTION const size_t
lpc24xx_start_config_emc_dynamic_chip_count =
sizeof(lpc24xx_start_config_emc_dynamic_chip)
/ sizeof(lpc24xx_start_config_emc_dynamic_chip [0]);
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-static.c:1.1 rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-static.c:1.2
--- rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-static.c:1.1 Mon Oct 17 05:40:00 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-static.c Tue Nov 8 04:39:46 2011
@@ -25,9 +25,9 @@
#include <bsp/start-config.h>
#include <bsp/lpc24xx.h>
-const BSP_START_DATA_SECTION lpc24xx_emc_static_chip_config
+BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
lpc24xx_start_config_emc_static_chip [] = {
-#ifdef LPC24XX_EMC_NUMONYX
+#if defined(LPC24XX_EMC_NUMONYX_M29W160E)
/*
* Static Memory 1: Numonyx M29W160EB
*
@@ -66,10 +66,40 @@
.waitrun = 0xf
}
}
-#endif /* LPC24XX_EMC_NUMONYX */
+#elif defined(LPC24XX_EMC_SST39VF3201)
+ /* Static Memory 1: SST SST39VF3201 at 51612800Hz (tCK = 19.4ns) */
+ {
+ .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0,
+ .config = {
+ /*
+ * 16 bit, page mode disabled, active LOW chip select, extended wait
+ * disabled, writes not protected, byte lane state LOW/LOW.
+ */
+ .config = 0x81,
+
+ /* (n + 1) clock cycles -> 19.4ns >= 0ns (tCS, tAS) */
+ .waitwen = 0,
+
+ /* (n + 1) clock cycles -> 19.4ns >= 0ns (tOES) */
+ .waitoen = 0,
+
+ /* (n + 1) clock cycles -> 77.5ns >= 70ns (tRC) */
+ .waitrd = 2,
+
+ /* (n + 1) clock cycles -> 77.5ns >= 70ns (tRC) */
+ .waitpage = 2,
+
+ /* (n + 2) clock cycles -> 38.8ns >= 20ns (tCHZ, TOHZ) */
+ .waitwr = 0,
+
+ /* (n + 1) clock cycles -> 38.8ns >= 20ns (tCHZ, TOHZ) */
+ .waitrun = 1
+ }
+ }
+#endif
};
-const BSP_START_DATA_SECTION size_t
+BSP_START_DATA_SECTION const size_t
lpc24xx_start_config_emc_static_chip_count =
sizeof(lpc24xx_start_config_emc_static_chip)
/ sizeof(lpc24xx_start_config_emc_static_chip [0]);
diff -u rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c:1.1 rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c:1.2
--- rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c:1.1 Mon Oct 17 05:40:00 2011
+++ rtems/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c Tue Nov 8 04:39:46 2011
@@ -24,23 +24,53 @@
#include <bsp/start-config.h>
-const BSP_START_DATA_SECTION uint32_t lpc24xx_start_config_pinsel_5_9 [] = {
-#if defined(LPC24XX_EMC_MICRON) \
- || defined(LPC24XX_EMC_K4S561632E) \
- || defined(LPC24XX_EMC_NUMONYX)
- 0x05010115,
- 0x55555555,
- 0x0,
- #ifdef LPC24XX_EMC_K4S561632E
- 0x15555555,
- 0x0a040000
- #else
- 0x55555555,
- 0x40050155
- #endif
+BSP_START_DATA_SECTION const lpc24xx_pin_range
+ lpc24xx_start_config_pinsel [] = {
+#if defined(LPC24XX_EMC_MT48LC4M16A2) \
+ && defined(LPC24XX_EMC_NUMONYX_M29W160E)
+ LPC24XX_PIN_EMC_A_0_20,
+ LPC24XX_PIN_EMC_D_0_15,
+ LPC24XX_PIN_EMC_RAS,
+ LPC24XX_PIN_EMC_CAS,
+ LPC24XX_PIN_EMC_WE,
+ LPC24XX_PIN_EMC_DYCS_0,
+ LPC24XX_PIN_EMC_CLK_0,
+ LPC24XX_PIN_EMC_CKE_0,
+ LPC24XX_PIN_EMC_DQM_0,
+ LPC24XX_PIN_EMC_DQM_1,
+ LPC24XX_PIN_EMC_OE,
+ LPC24XX_PIN_EMC_CS_1,
#endif
+#if defined(LPC24XX_EMC_W9825G2JB75I) \
+ && defined(LPC24XX_EMC_SST39VF3201)
+ LPC24XX_PIN_EMC_A_0_22,
+ LPC24XX_PIN_EMC_D_0_31,
+ LPC24XX_PIN_EMC_RAS,
+ LPC24XX_PIN_EMC_CAS,
+ LPC24XX_PIN_EMC_WE,
+ LPC24XX_PIN_EMC_DYCS_0,
+ LPC24XX_PIN_EMC_CLK_0,
+ LPC24XX_PIN_EMC_CKE_0,
+ LPC24XX_PIN_EMC_DQM_0,
+ LPC24XX_PIN_EMC_DQM_1,
+ LPC24XX_PIN_EMC_DQM_2,
+ LPC24XX_PIN_EMC_DQM_3,
+ LPC24XX_PIN_EMC_OE,
+ LPC24XX_PIN_EMC_CS_0,
+#endif
+#if defined(LPC24XX_EMC_IS42S32800B)
+ LPC24XX_PIN_EMC_A_0_14,
+ LPC24XX_PIN_EMC_D_0_31,
+ LPC24XX_PIN_EMC_RAS,
+ LPC24XX_PIN_EMC_CAS,
+ LPC24XX_PIN_EMC_WE,
+ LPC24XX_PIN_EMC_DYCS_0,
+ LPC24XX_PIN_EMC_CLK_0,
+ LPC24XX_PIN_EMC_CKE_0,
+ LPC24XX_PIN_EMC_DQM_0,
+ LPC24XX_PIN_EMC_DQM_1,
+ LPC24XX_PIN_EMC_DQM_2,
+ LPC24XX_PIN_EMC_DQM_3,
+#endif
+ LPC24XX_PIN_TERMINAL
};
-
-const BSP_START_DATA_SECTION size_t
- lpc24xx_start_config_pinsel_5_9_size =
- sizeof(lpc24xx_start_config_pinsel_5_9);
--
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