[rtems-libbsd commit] Added pcib.
Jennifer Averett
jennifer at rtems.org
Mon Jun 11 14:38:46 UTC 2012
Module: rtems-libbsd
Branch: master
Commit: 58ea5ee27a1844d69023357241f5d75dba9000a1
Changeset: http://git.rtems.org/rtems-libbsd/commit/?id=58ea5ee27a1844d69023357241f5d75dba9000a1
Author: Jennifer Averett <jennifer.averett at oarcorp.com>
Date: Mon Jun 11 09:42:08 2012 -0500
Added pcib.
---
Makefile | 4 +
freebsd-to-rtems.py | 10 +-
freebsd/dev/pci/pci_pci.c | 738 +++++++++++++++++++++
freebsd/i386/include/freebsd/machine/legacyvar.h | 57 ++
freebsd/i386/include/freebsd/machine/pci_cfgreg.h | 52 ++
freebsd/i386/pci/pci_bus.c | 713 ++++++++++++++++++++
6 files changed, 1573 insertions(+), 1 deletions(-)
diff --git a/Makefile b/Makefile
index ce7a47d..c48040c 100644
--- a/Makefile
+++ b/Makefile
@@ -384,6 +384,10 @@ C_FILES += freebsd/kern/kern_resource.c
C_FILES += freebsd/kern/subr_bufring.c
C_FILES += freebsd/dev/led/led.c
C_FILES += freebsd/kern/subr_unit.c
+C_FILES += freebsd/dev/pci/pci_pci.c
+ifeq ($(RTEMS_CPU), i386)
+C_FILES += freebsd/i386/pci/pci_bus.c
+endif
C_FILES += freebsd/dev/re/if_re.c
C_FILES += freebsd/dev/fxp/if_fxp.c
C_FILES += freebsd/dev/e1000/e1000_80003es2lan.c
diff --git a/freebsd-to-rtems.py b/freebsd-to-rtems.py
index c18eee4..f11c42b 100755
--- a/freebsd-to-rtems.py
+++ b/freebsd-to-rtems.py
@@ -1205,9 +1205,16 @@ devNic.addCPUDependentHeaderFiles(
'i386/include/specialreg.h',
'i386/include/md_var.h',
'i386/include/intr_machdep.h',
+ 'i386/include/legacyvar.h',
+ 'i386/include/pci_cfgreg.h',
+ ]
+)
+devNic.addCPUDependentSourceFiles(
+ 'i386',
+ [
+ 'i386/pci/pci_bus.c',
]
)
-
devNic.addSourceFiles(
[
# 'kern/subr_taskqueue.c',
@@ -1235,6 +1242,7 @@ devNic.addSourceFiles(
'kern/subr_bufring.c',
'dev/led/led.c',
'kern/subr_unit.c',
+ 'dev/pci/pci_pci.c',
]
)
diff --git a/freebsd/dev/pci/pci_pci.c b/freebsd/dev/pci/pci_pci.c
new file mode 100644
index 0000000..f65c0b8
--- /dev/null
+++ b/freebsd/dev/pci/pci_pci.c
@@ -0,0 +1,738 @@
+#include <freebsd/machine/rtems-bsd-config.h>
+
+/*-
+ * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
+ * Copyright (c) 2000 Michael Smith <msmith at freebsd.org>
+ * Copyright (c) 2000 BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <freebsd/sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * PCI:PCI bridge support.
+ */
+
+#include <freebsd/sys/param.h>
+#include <freebsd/sys/systm.h>
+#include <freebsd/sys/kernel.h>
+#include <freebsd/sys/module.h>
+#include <freebsd/sys/bus.h>
+#include <freebsd/machine/bus.h>
+#include <freebsd/sys/rman.h>
+#include <freebsd/sys/sysctl.h>
+
+#include <freebsd/machine/resource.h>
+
+#include <freebsd/dev/pci/pcivar.h>
+#include <freebsd/dev/pci/pcireg.h>
+#include <freebsd/dev/pci/pcib_private.h>
+
+#include <freebsd/local/pcib_if.h>
+
+static int pcib_probe(device_t dev);
+
+static device_method_t pcib_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, pcib_probe),
+ DEVMETHOD(device_attach, pcib_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_read_ivar, pcib_read_ivar),
+ DEVMETHOD(bus_write_ivar, pcib_write_ivar),
+ DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, pcib_maxslots),
+ DEVMETHOD(pcib_read_config, pcib_read_config),
+ DEVMETHOD(pcib_write_config, pcib_write_config),
+ DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
+ DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
+ DEVMETHOD(pcib_release_msi, pcib_release_msi),
+ DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
+ DEVMETHOD(pcib_release_msix, pcib_release_msix),
+ DEVMETHOD(pcib_map_msi, pcib_map_msi),
+
+ { 0, 0 }
+};
+
+static devclass_t pcib_devclass;
+
+DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
+DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
+
+/*
+ * Is the prefetch window open (eg, can we allocate memory in it?)
+ */
+static int
+pcib_is_prefetch_open(struct pcib_softc *sc)
+{
+ return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
+}
+
+/*
+ * Is the nonprefetch window open (eg, can we allocate memory in it?)
+ */
+static int
+pcib_is_nonprefetch_open(struct pcib_softc *sc)
+{
+ return (sc->membase > 0 && sc->membase < sc->memlimit);
+}
+
+/*
+ * Is the io window open (eg, can we allocate ports in it?)
+ */
+static int
+pcib_is_io_open(struct pcib_softc *sc)
+{
+ return (sc->iobase > 0 && sc->iobase < sc->iolimit);
+}
+
+/*
+ * Generic device interface
+ */
+static int
+pcib_probe(device_t dev)
+{
+ if ((pci_get_class(dev) == PCIC_BRIDGE) &&
+ (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
+ device_set_desc(dev, "PCI-PCI bridge");
+ return(-10000);
+ }
+ return(ENXIO);
+}
+
+void
+pcib_attach_common(device_t dev)
+{
+ struct pcib_softc *sc;
+ uint8_t iolow;
+ struct sysctl_ctx_list *sctx;
+ struct sysctl_oid *soid;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+
+ /*
+ * Get current bridge configuration.
+ */
+ sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
+ sc->domain = pci_get_domain(dev);
+ sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1);
+ sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
+ sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
+ sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
+ sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
+ sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
+
+ /*
+ * Setup sysctl reporting nodes
+ */
+ sctx = device_get_sysctl_ctx(dev);
+ soid = device_get_sysctl_tree(dev);
+ SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
+ CTLFLAG_RD, &sc->domain, 0, "Domain number");
+ SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
+ CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
+ SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
+ CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number");
+ SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
+ CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number");
+
+ /*
+ * Determine current I/O decode.
+ */
+ if (sc->command & PCIM_CMD_PORTEN) {
+ iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
+ if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
+ sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
+ pci_read_config(dev, PCIR_IOBASEL_1, 1));
+ } else {
+ sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
+ }
+
+ iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
+ if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
+ sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
+ pci_read_config(dev, PCIR_IOLIMITL_1, 1));
+ } else {
+ sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
+ }
+ }
+
+ /*
+ * Determine current memory decode.
+ */
+ if (sc->command & PCIM_CMD_MEMEN) {
+ sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
+ sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
+ iolow = pci_read_config(dev, PCIR_PMBASEL_1, 1);
+ if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
+ sc->pmembase = PCI_PPBMEMBASE(
+ pci_read_config(dev, PCIR_PMBASEH_1, 4),
+ pci_read_config(dev, PCIR_PMBASEL_1, 2));
+ else
+ sc->pmembase = PCI_PPBMEMBASE(0,
+ pci_read_config(dev, PCIR_PMBASEL_1, 2));
+ iolow = pci_read_config(dev, PCIR_PMLIMITL_1, 1);
+ if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
+ sc->pmemlimit = PCI_PPBMEMLIMIT(
+ pci_read_config(dev, PCIR_PMLIMITH_1, 4),
+ pci_read_config(dev, PCIR_PMLIMITL_1, 2));
+ else
+ sc->pmemlimit = PCI_PPBMEMLIMIT(0,
+ pci_read_config(dev, PCIR_PMLIMITL_1, 2));
+ }
+
+ /*
+ * Quirk handling.
+ */
+ switch (pci_get_devid(dev)) {
+ case 0x12258086: /* Intel 82454KX/GX (Orion) */
+ {
+ uint8_t supbus;
+
+ supbus = pci_read_config(dev, 0x41, 1);
+ if (supbus != 0xff) {
+ sc->secbus = supbus + 1;
+ sc->subbus = supbus + 1;
+ }
+ break;
+ }
+
+ /*
+ * The i82380FB mobile docking controller is a PCI-PCI bridge,
+ * and it is a subtractive bridge. However, the ProgIf is wrong
+ * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
+ * happen. There's also a Toshiba bridge that behaves this
+ * way.
+ */
+ case 0x124b8086: /* Intel 82380FB Mobile */
+ case 0x060513d7: /* Toshiba ???? */
+ sc->flags |= PCIB_SUBTRACTIVE;
+ break;
+
+ /* Compaq R3000 BIOS sets wrong subordinate bus number. */
+ case 0x00dd10de:
+ {
+ char *cp;
+
+ if ((cp = getenv("smbios.planar.maker")) == NULL)
+ break;
+ if (strncmp(cp, "Compal", 6) != 0) {
+ freeenv(cp);
+ break;
+ }
+ freeenv(cp);
+ if ((cp = getenv("smbios.planar.product")) == NULL)
+ break;
+ if (strncmp(cp, "08A0", 4) != 0) {
+ freeenv(cp);
+ break;
+ }
+ freeenv(cp);
+ if (sc->subbus < 0xa) {
+ pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
+ sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
+ }
+ break;
+ }
+ }
+
+ if (pci_msi_device_blacklisted(dev))
+ sc->flags |= PCIB_DISABLE_MSI;
+
+ /*
+ * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
+ * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
+ * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
+ * This means they act as if they were subtractively decoding
+ * bridges and pass all transactions. Mark them and real ProgIf 1
+ * parts as subtractive.
+ */
+ if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
+ pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
+ sc->flags |= PCIB_SUBTRACTIVE;
+
+ if (bootverbose) {
+ device_printf(dev, " domain %d\n", sc->domain);
+ device_printf(dev, " secondary bus %d\n", sc->secbus);
+ device_printf(dev, " subordinate bus %d\n", sc->subbus);
+ device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
+ if (pcib_is_nonprefetch_open(sc))
+ device_printf(dev, " memory decode 0x%jx-0x%jx\n",
+ (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
+ if (pcib_is_prefetch_open(sc))
+ device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
+ (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
+ else
+ device_printf(dev, " no prefetched decode\n");
+ if (sc->flags & PCIB_SUBTRACTIVE)
+ device_printf(dev, " Subtractively decoded bridge.\n");
+ }
+
+ /*
+ * XXX If the secondary bus number is zero, we should assign a bus number
+ * since the BIOS hasn't, then initialise the bridge. A simple
+ * bus_alloc_resource with the a couple of busses seems like the right
+ * approach, but we don't know what busses the BIOS might have already
+ * assigned to other bridges on this bus that probe later than we do.
+ *
+ * If the subordinate bus number is less than the secondary bus number,
+ * we should pick a better value. One sensible alternative would be to
+ * pick 255; the only tradeoff here is that configuration transactions
+ * would be more widely routed than absolutely necessary. We could
+ * then do a walk of the tree later and fix it.
+ */
+}
+
+int
+pcib_attach(device_t dev)
+{
+ struct pcib_softc *sc;
+ device_t child;
+
+ pcib_attach_common(dev);
+ sc = device_get_softc(dev);
+ if (sc->secbus != 0) {
+ child = device_add_child(dev, "pci", sc->secbus);
+ if (child != NULL)
+ return(bus_generic_attach(dev));
+ }
+
+ /* no secondary bus; we should have fixed this */
+ return(0);
+}
+
+int
+pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+ struct pcib_softc *sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = sc->domain;
+ return(0);
+ case PCIB_IVAR_BUS:
+ *result = sc->secbus;
+ return(0);
+ }
+ return(ENOENT);
+}
+
+int
+pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
+{
+ struct pcib_softc *sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ return(EINVAL);
+ case PCIB_IVAR_BUS:
+ sc->secbus = value;
+ return(0);
+ }
+ return(ENOENT);
+}
+
+/*
+ * We have to trap resource allocation requests and ensure that the bridge
+ * is set up to, or capable of handling them.
+ */
+struct resource *
+pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct pcib_softc *sc = device_get_softc(dev);
+ const char *name, *suffix;
+ int ok;
+
+ /*
+ * Fail the allocation for this range if it's not supported.
+ */
+ name = device_get_nameunit(child);
+ if (name == NULL) {
+ name = "";
+ suffix = "";
+ } else
+ suffix = " ";
+ switch (type) {
+ case SYS_RES_IOPORT:
+ ok = 0;
+ if (!pcib_is_io_open(sc))
+ break;
+ ok = (start >= sc->iobase && end <= sc->iolimit);
+
+ /*
+ * Make sure we allow access to VGA I/O addresses when the
+ * bridge has the "VGA Enable" bit set.
+ */
+ if (!ok && pci_is_vga_ioport_range(start, end))
+ ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
+
+ if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
+ if (!ok) {
+ if (start < sc->iobase)
+ start = sc->iobase;
+ if (end > sc->iolimit)
+ end = sc->iolimit;
+ if (start < end)
+ ok = 1;
+ }
+ } else {
+ ok = 1;
+#if 0
+ /*
+ * If we overlap with the subtractive range, then
+ * pick the upper range to use.
+ */
+ if (start < sc->iolimit && end > sc->iobase)
+ start = sc->iolimit + 1;
+#endif
+ }
+ if (end < start) {
+ device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
+ end, start);
+ start = 0;
+ end = 0;
+ ok = 0;
+ }
+ if (!ok) {
+ device_printf(dev, "%s%srequested unsupported I/O "
+ "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
+ name, suffix, start, end, sc->iobase, sc->iolimit);
+ return (NULL);
+ }
+ if (bootverbose)
+ device_printf(dev,
+ "%s%srequested I/O range 0x%lx-0x%lx: in range\n",
+ name, suffix, start, end);
+ break;
+
+ case SYS_RES_MEMORY:
+ ok = 0;
+ if (pcib_is_nonprefetch_open(sc))
+ ok = ok || (start >= sc->membase && end <= sc->memlimit);
+ if (pcib_is_prefetch_open(sc))
+ ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
+
+ /*
+ * Make sure we allow access to VGA memory addresses when the
+ * bridge has the "VGA Enable" bit set.
+ */
+ if (!ok && pci_is_vga_memory_range(start, end))
+ ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
+
+ if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
+ if (!ok) {
+ ok = 1;
+ if (flags & RF_PREFETCHABLE) {
+ if (pcib_is_prefetch_open(sc)) {
+ if (start < sc->pmembase)
+ start = sc->pmembase;
+ if (end > sc->pmemlimit)
+ end = sc->pmemlimit;
+ } else {
+ ok = 0;
+ }
+ } else { /* non-prefetchable */
+ if (pcib_is_nonprefetch_open(sc)) {
+ if (start < sc->membase)
+ start = sc->membase;
+ if (end > sc->memlimit)
+ end = sc->memlimit;
+ } else {
+ ok = 0;
+ }
+ }
+ }
+ } else if (!ok) {
+ ok = 1; /* subtractive bridge: always ok */
+#if 0
+ if (pcib_is_nonprefetch_open(sc)) {
+ if (start < sc->memlimit && end > sc->membase)
+ start = sc->memlimit + 1;
+ }
+ if (pcib_is_prefetch_open(sc)) {
+ if (start < sc->pmemlimit && end > sc->pmembase)
+ start = sc->pmemlimit + 1;
+ }
+#endif
+ }
+ if (end < start) {
+ device_printf(dev, "memory: end (%lx) < start (%lx)\n",
+ end, start);
+ start = 0;
+ end = 0;
+ ok = 0;
+ }
+ if (!ok && bootverbose)
+ device_printf(dev,
+ "%s%srequested unsupported memory range %#lx-%#lx "
+ "(decoding %#jx-%#jx, %#jx-%#jx)\n",
+ name, suffix, start, end,
+ (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
+ (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
+ if (!ok)
+ return (NULL);
+ if (bootverbose)
+ device_printf(dev,"%s%srequested memory range "
+ "0x%lx-0x%lx: good\n",
+ name, suffix, start, end);
+ break;
+
+ default:
+ break;
+ }
+ /*
+ * Bridge is OK decoding this resource, so pass it up.
+ */
+ return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
+ count, flags));
+}
+
+/*
+ * PCIB interface.
+ */
+int
+pcib_maxslots(device_t dev)
+{
+ return(PCI_SLOTMAX);
+}
+
+/*
+ * Since we are a child of a PCI bus, its parent must support the pcib interface.
+ */
+uint32_t
+pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
+{
+ return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
+}
+
+void
+pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
+{
+ PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
+}
+
+/*
+ * Route an interrupt across a PCI bridge.
+ */
+int
+pcib_route_interrupt(device_t pcib, device_t dev, int pin)
+{
+ device_t bus;
+ int parent_intpin;
+ int intnum;
+
+ /*
+ *
+ * The PCI standard defines a swizzle of the child-side device/intpin to
+ * the parent-side intpin as follows.
+ *
+ * device = device on child bus
+ * child_intpin = intpin on child bus slot (0-3)
+ * parent_intpin = intpin on parent bus slot (0-3)
+ *
+ * parent_intpin = (device + child_intpin) % 4
+ */
+ parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
+
+ /*
+ * Our parent is a PCI bus. Its parent must export the pcib interface
+ * which includes the ability to route interrupts.
+ */
+ bus = device_get_parent(pcib);
+ intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
+ if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
+ device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
+ pci_get_slot(dev), 'A' + pin - 1, intnum);
+ }
+ return(intnum);
+}
+
+/* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
+int
+pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
+{
+ struct pcib_softc *sc = device_get_softc(pcib);
+ device_t bus;
+
+ if (sc->flags & PCIB_DISABLE_MSI)
+ return (ENXIO);
+ bus = device_get_parent(pcib);
+ return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
+ irqs));
+}
+
+/* Pass request to release MSI/MSI-X messages up to the parent bridge. */
+int
+pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
+{
+ device_t bus;
+
+ bus = device_get_parent(pcib);
+ return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
+}
+
+/* Pass request to alloc an MSI-X message up to the parent bridge. */
+int
+pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
+{
+ struct pcib_softc *sc = device_get_softc(pcib);
+ device_t bus;
+
+ if (sc->flags & PCIB_DISABLE_MSI)
+ return (ENXIO);
+ bus = device_get_parent(pcib);
+ return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
+}
+
+/* Pass request to release an MSI-X message up to the parent bridge. */
+int
+pcib_release_msix(device_t pcib, device_t dev, int irq)
+{
+ device_t bus;
+
+ bus = device_get_parent(pcib);
+ return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
+}
+
+/* Pass request to map MSI/MSI-X message up to parent bridge. */
+int
+pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
+ uint32_t *data)
+{
+ device_t bus;
+ int error;
+
+ bus = device_get_parent(pcib);
+ error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
+ if (error)
+ return (error);
+
+ pci_ht_map_msi(pcib, *addr);
+ return (0);
+}
+
+/*
+ * Try to read the bus number of a host-PCI bridge using appropriate config
+ * registers.
+ */
+int
+host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
+ uint8_t *busnum)
+{
+ uint32_t id;
+
+ id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
+ if (id == 0xffffffff)
+ return (0);
+
+ switch (id) {
+ case 0x12258086:
+ /* Intel 824?? */
+ /* XXX This is a guess */
+ /* *busnum = read_config(bus, slot, func, 0x41, 1); */
+ *busnum = bus;
+ break;
+ case 0x84c48086:
+ /* Intel 82454KX/GX (Orion) */
+ *busnum = read_config(bus, slot, func, 0x4a, 1);
+ break;
+ case 0x84ca8086:
+ /*
+ * For the 450nx chipset, there is a whole bundle of
+ * things pretending to be host bridges. The MIOC will
+ * be seen first and isn't really a pci bridge (the
+ * actual busses are attached to the PXB's). We need to
+ * read the registers of the MIOC to figure out the
+ * bus numbers for the PXB channels.
+ *
+ * Since the MIOC doesn't have a pci bus attached, we
+ * pretend it wasn't there.
+ */
+ return (0);
+ case 0x84cb8086:
+ switch (slot) {
+ case 0x12:
+ /* Intel 82454NX PXB#0, Bus#A */
+ *busnum = read_config(bus, 0x10, func, 0xd0, 1);
+ break;
+ case 0x13:
+ /* Intel 82454NX PXB#0, Bus#B */
+ *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
+ break;
+ case 0x14:
+ /* Intel 82454NX PXB#1, Bus#A */
+ *busnum = read_config(bus, 0x10, func, 0xd3, 1);
+ break;
+ case 0x15:
+ /* Intel 82454NX PXB#1, Bus#B */
+ *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
+ break;
+ }
+ break;
+
+ /* ServerWorks -- vendor 0x1166 */
+ case 0x00051166:
+ case 0x00061166:
+ case 0x00081166:
+ case 0x00091166:
+ case 0x00101166:
+ case 0x00111166:
+ case 0x00171166:
+ case 0x01011166:
+ case 0x010f1014:
+ case 0x01101166:
+ case 0x02011166:
+ case 0x02251166:
+ case 0x03021014:
+ *busnum = read_config(bus, slot, func, 0x44, 1);
+ break;
+
+ /* Compaq/HP -- vendor 0x0e11 */
+ case 0x60100e11:
+ *busnum = read_config(bus, slot, func, 0xc8, 1);
+ break;
+ default:
+ /* Don't know how to read bus number. */
+ return 0;
+ }
+
+ return 1;
+}
diff --git a/freebsd/i386/include/freebsd/machine/legacyvar.h b/freebsd/i386/include/freebsd/machine/legacyvar.h
new file mode 100644
index 0000000..4771faf
--- /dev/null
+++ b/freebsd/i386/include/freebsd/machine/legacyvar.h
@@ -0,0 +1,57 @@
+/*-
+ * Copyright (c) 2000 Peter Wemm <peter at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _MACHINE_LEGACYVAR_HH_
+#define _MACHINE_LEGACYVAR_HH_
+
+enum legacy_device_ivars {
+ LEGACY_IVAR_PCIDOMAIN,
+ LEGACY_IVAR_PCIBUS
+};
+
+#define LEGACY_ACCESSOR(var, ivar, type) \
+ __BUS_ACCESSOR(legacy, var, LEGACY, ivar, type)
+
+LEGACY_ACCESSOR(pcidomain, PCIDOMAIN, uint32_t)
+LEGACY_ACCESSOR(pcibus, PCIBUS, uint32_t)
+
+#undef LEGACY_ACCESSOR
+
+int legacy_pcib_maxslots(device_t dev);
+uint32_t legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
+ u_int reg, int bytes);
+int legacy_pcib_read_ivar(device_t dev, device_t child, int which,
+ uintptr_t *result);
+void legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
+ u_int reg, u_int32_t data, int bytes);
+int legacy_pcib_write_ivar(device_t dev, device_t child, int which,
+ uintptr_t value);
+struct resource *legacy_pcib_alloc_resource(device_t dev, device_t child,
+ int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
+
+#endif /* !_MACHINE_LEGACYVAR_HH_ */
diff --git a/freebsd/i386/include/freebsd/machine/pci_cfgreg.h b/freebsd/i386/include/freebsd/machine/pci_cfgreg.h
new file mode 100644
index 0000000..bc72418
--- /dev/null
+++ b/freebsd/i386/include/freebsd/machine/pci_cfgreg.h
@@ -0,0 +1,52 @@
+/*-
+ * Copyright (c) 1997, Stefan Esser <se at freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#define CONF1_ADDR_PORT 0x0cf8
+#define CONF1_DATA_PORT 0x0cfc
+
+#define CONF1_ENABLE 0x80000000ul
+#define CONF1_ENABLE_CHK 0x80000000ul
+#define CONF1_ENABLE_MSK 0x7f000000ul
+#define CONF1_ENABLE_CHK1 0xff000001ul
+#define CONF1_ENABLE_MSK1 0x80000001ul
+#define CONF1_ENABLE_RES1 0x80000000ul
+
+#define CONF2_ENABLE_PORT 0x0cf8
+#define CONF2_FORWARD_PORT 0x0cfa
+
+#define CONF2_ENABLE_CHK 0x0e
+#define CONF2_ENABLE_RES 0x0e
+
+int pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus);
+int pci_cfgregopen(void);
+u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes);
+void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes);
+void pci_pir_open(void);
+int pci_pir_probe(int bus, int require_parse);
+int pci_pir_route_interrupt(int bus, int device, int func, int pin);
diff --git a/freebsd/i386/pci/pci_bus.c b/freebsd/i386/pci/pci_bus.c
new file mode 100644
index 0000000..51c463e
--- /dev/null
+++ b/freebsd/i386/pci/pci_bus.c
@@ -0,0 +1,713 @@
+#include <freebsd/machine/rtems-bsd-config.h>
+
+/*-
+ * Copyright (c) 1997, Stefan Esser <se at freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <freebsd/sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <freebsd/local/opt_cpu.h>
+
+#include <freebsd/sys/param.h>
+#include <freebsd/sys/systm.h>
+#include <freebsd/sys/bus.h>
+#include <freebsd/sys/kernel.h>
+#include <freebsd/sys/malloc.h>
+#include <freebsd/sys/module.h>
+#include <freebsd/sys/sysctl.h>
+
+#include <freebsd/dev/pci/pcivar.h>
+#include <freebsd/dev/pci/pcireg.h>
+#include <freebsd/dev/pci/pcib_private.h>
+#include <freebsd/isa/isavar.h>
+#ifdef CPU_ELAN
+#include <freebsd/machine/md_var.h>
+#endif
+#include <freebsd/machine/legacyvar.h>
+#include <freebsd/machine/pci_cfgreg.h>
+#include <freebsd/machine/resource.h>
+
+#include <freebsd/local/pcib_if.h>
+
+static int pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
+ int pin);
+
+int
+legacy_pcib_maxslots(device_t dev)
+{
+ return 31;
+}
+
+/* read configuration space register */
+
+u_int32_t
+legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
+ u_int reg, int bytes)
+{
+ return(pci_cfgregread(bus, slot, func, reg, bytes));
+}
+
+/* write configuration space register */
+
+void
+legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
+ u_int reg, u_int32_t data, int bytes)
+{
+ pci_cfgregwrite(bus, slot, func, reg, data, bytes);
+}
+
+/* Pass MSI requests up to the nexus. */
+
+static int
+legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
+ int *irqs)
+{
+ device_t bus;
+
+ bus = device_get_parent(pcib);
+ return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
+ irqs));
+}
+
+static int
+legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
+{
+ device_t bus;
+
+ bus = device_get_parent(pcib);
+ return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
+}
+
+static int
+legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
+ uint32_t *data)
+{
+ device_t bus;
+
+ bus = device_get_parent(pcib);
+ return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data));
+}
+
+static const char *
+legacy_pcib_is_host_bridge(int bus, int slot, int func,
+ uint32_t id, uint8_t class, uint8_t subclass,
+ uint8_t *busnum)
+{
+ const char *s = NULL;
+ static uint8_t pxb[4]; /* hack for 450nx */
+
+ *busnum = 0;
+
+ switch (id) {
+ case 0x12258086:
+ s = "Intel 824?? host to PCI bridge";
+ /* XXX This is a guess */
+ /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
+ *busnum = bus;
+ break;
+ case 0x71208086:
+ s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
+ break;
+ case 0x71228086:
+ s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
+ break;
+ case 0x71248086:
+ s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
+ break;
+ case 0x11308086:
+ s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
+ break;
+ case 0x71808086:
+ s = "Intel 82443LX (440 LX) host to PCI bridge";
+ break;
+ case 0x71908086:
+ s = "Intel 82443BX (440 BX) host to PCI bridge";
+ break;
+ case 0x71928086:
+ s = "Intel 82443BX host to PCI bridge (AGP disabled)";
+ break;
+ case 0x71948086:
+ s = "Intel 82443MX host to PCI bridge";
+ break;
+ case 0x71a08086:
+ s = "Intel 82443GX host to PCI bridge";
+ break;
+ case 0x71a18086:
+ s = "Intel 82443GX host to AGP bridge";
+ break;
+ case 0x71a28086:
+ s = "Intel 82443GX host to PCI bridge (AGP disabled)";
+ break;
+ case 0x84c48086:
+ s = "Intel 82454KX/GX (Orion) host to PCI bridge";
+ *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
+ break;
+ case 0x84ca8086:
+ /*
+ * For the 450nx chipset, there is a whole bundle of
+ * things pretending to be host bridges. The MIOC will
+ * be seen first and isn't really a pci bridge (the
+ * actual busses are attached to the PXB's). We need to
+ * read the registers of the MIOC to figure out the
+ * bus numbers for the PXB channels.
+ *
+ * Since the MIOC doesn't have a pci bus attached, we
+ * pretend it wasn't there.
+ */
+ pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
+ 0xd0, 1); /* BUSNO[0] */
+ pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
+ 0xd1, 1) + 1; /* SUBA[0]+1 */
+ pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
+ 0xd3, 1); /* BUSNO[1] */
+ pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
+ 0xd4, 1) + 1; /* SUBA[1]+1 */
+ return NULL;
+ case 0x84cb8086:
+ switch (slot) {
+ case 0x12:
+ s = "Intel 82454NX PXB#0, Bus#A";
+ *busnum = pxb[0];
+ break;
+ case 0x13:
+ s = "Intel 82454NX PXB#0, Bus#B";
+ *busnum = pxb[1];
+ break;
+ case 0x14:
+ s = "Intel 82454NX PXB#1, Bus#A";
+ *busnum = pxb[2];
+ break;
+ case 0x15:
+ s = "Intel 82454NX PXB#1, Bus#B";
+ *busnum = pxb[3];
+ break;
+ }
+ break;
+ case 0x1A308086:
+ s = "Intel 82845 Host to PCI bridge";
+ break;
+
+ /* AMD -- vendor 0x1022 */
+ case 0x30001022:
+ s = "AMD Elan SC520 host to PCI bridge";
+#ifdef CPU_ELAN
+ init_AMD_Elan_sc520();
+#else
+ printf(
+"*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
+#endif
+ break;
+ case 0x70061022:
+ s = "AMD-751 host to PCI bridge";
+ break;
+ case 0x700e1022:
+ s = "AMD-761 host to PCI bridge";
+ break;
+
+ /* SiS -- vendor 0x1039 */
+ case 0x04961039:
+ s = "SiS 85c496";
+ break;
+ case 0x04061039:
+ s = "SiS 85c501";
+ break;
+ case 0x06011039:
+ s = "SiS 85c601";
+ break;
+ case 0x55911039:
+ s = "SiS 5591 host to PCI bridge";
+ break;
+ case 0x00011039:
+ s = "SiS 5591 host to AGP bridge";
+ break;
+
+ /* VLSI -- vendor 0x1004 */
+ case 0x00051004:
+ s = "VLSI 82C592 Host to PCI bridge";
+ break;
+
+ /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
+ /* totally. Please let me know if anything wrong. -F */
+ /* XXX need info on the MVP3 -- any takers? */
+ case 0x05981106:
+ s = "VIA 82C598MVP (Apollo MVP3) host bridge";
+ break;
+
+ /* AcerLabs -- vendor 0x10b9 */
+ /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
+ /* id is '10b9" but the register always shows "10b9". -Foxfair */
+ case 0x154110b9:
+ s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
+ break;
+
+ /* OPTi -- vendor 0x1045 */
+ case 0xc7011045:
+ s = "OPTi 82C700 host to PCI bridge";
+ break;
+ case 0xc8221045:
+ s = "OPTi 82C822 host to PCI Bridge";
+ break;
+
+ /* ServerWorks -- vendor 0x1166 */
+ case 0x00051166:
+ s = "ServerWorks NB6536 2.0HE host to PCI bridge";
+ *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
+ break;
+
+ case 0x00061166:
+ /* FALLTHROUGH */
+ case 0x00081166:
+ /* FALLTHROUGH */
+ case 0x02011166:
+ /* FALLTHROUGH */
+ case 0x010f1014: /* IBM re-badged ServerWorks chipset */
+ s = "ServerWorks host to PCI bridge";
+ *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
+ break;
+
+ case 0x00091166:
+ s = "ServerWorks NB6635 3.0LE host to PCI bridge";
+ *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
+ break;
+
+ case 0x00101166:
+ s = "ServerWorks CIOB30 host to PCI bridge";
+ *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
+ break;
+
+ case 0x00111166:
+ /* FALLTHROUGH */
+ case 0x03021014: /* IBM re-badged ServerWorks chipset */
+ s = "ServerWorks CMIC-HE host to PCI-X bridge";
+ *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
+ break;
+
+ /* XXX unknown chipset, but working */
+ case 0x00171166:
+ /* FALLTHROUGH */
+ case 0x01011166:
+ case 0x01101166:
+ case 0x02251166:
+ s = "ServerWorks host to PCI bridge(unknown chipset)";
+ *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
+ break;
+
+ /* Compaq/HP -- vendor 0x0e11 */
+ case 0x60100e11:
+ s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
+ *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
+ break;
+
+ /* Integrated Micro Solutions -- vendor 0x10e0 */
+ case 0x884910e0:
+ s = "Integrated Micro Solutions VL Bridge";
+ break;
+
+ default:
+ if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
+ s = "Host to PCI bridge";
+ break;
+ }
+
+ return s;
+}
+
+/*
+ * Scan the first pci bus for host-pci bridges and add pcib instances
+ * to the nexus for each bridge.
+ */
+static void
+legacy_pcib_identify(driver_t *driver, device_t parent)
+{
+ int bus, slot, func;
+ u_int8_t hdrtype;
+ int found = 0;
+ int pcifunchigh;
+ int found824xx = 0;
+ int found_orion = 0;
+ device_t child;
+ devclass_t pci_devclass;
+
+ if (pci_cfgregopen() == 0)
+ return;
+ /*
+ * Check to see if we haven't already had a PCI bus added
+ * via some other means. If we have, bail since otherwise
+ * we're going to end up duplicating it.
+ */
+ if ((pci_devclass = devclass_find("pci")) &&
+ devclass_get_device(pci_devclass, 0))
+ return;
+
+
+ bus = 0;
+ retry:
+ for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
+ func = 0;
+ hdrtype = legacy_pcib_read_config(0, bus, slot, func,
+ PCIR_HDRTYPE, 1);
+ /*
+ * When enumerating bus devices, the standard says that
+ * one should check the header type and ignore the slots whose
+ * header types that the software doesn't know about. We use
+ * this to filter out devices.
+ */
+ if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
+ continue;
+ if ((hdrtype & PCIM_MFDEV) &&
+ (!found_orion || hdrtype != 0xff))
+ pcifunchigh = PCI_FUNCMAX;
+ else
+ pcifunchigh = 0;
+ for (func = 0; func <= pcifunchigh; func++) {
+ /*
+ * Read the IDs and class from the device.
+ */
+ u_int32_t id;
+ u_int8_t class, subclass, busnum;
+ const char *s;
+ device_t *devs;
+ int ndevs, i;
+
+ id = legacy_pcib_read_config(0, bus, slot, func,
+ PCIR_DEVVENDOR, 4);
+ if (id == -1)
+ continue;
+ class = legacy_pcib_read_config(0, bus, slot, func,
+ PCIR_CLASS, 1);
+ subclass = legacy_pcib_read_config(0, bus, slot, func,
+ PCIR_SUBCLASS, 1);
+
+ s = legacy_pcib_is_host_bridge(bus, slot, func,
+ id, class, subclass,
+ &busnum);
+ if (s == NULL)
+ continue;
+
+ /*
+ * Check to see if the physical bus has already
+ * been seen. Eg: hybrid 32 and 64 bit host
+ * bridges to the same logical bus.
+ */
+ if (device_get_children(parent, &devs, &ndevs) == 0) {
+ for (i = 0; s != NULL && i < ndevs; i++) {
+ if (strcmp(device_get_name(devs[i]),
+ "pcib") != 0)
+ continue;
+ if (legacy_get_pcibus(devs[i]) == busnum)
+ s = NULL;
+ }
+ free(devs, M_TEMP);
+ }
+
+ if (s == NULL)
+ continue;
+ /*
+ * Add at priority 100 to make sure we
+ * go after any motherboard resources
+ */
+ child = BUS_ADD_CHILD(parent, 100,
+ "pcib", busnum);
+ device_set_desc(child, s);
+ legacy_set_pcibus(child, busnum);
+
+ found = 1;
+ if (id == 0x12258086)
+ found824xx = 1;
+ if (id == 0x84c48086)
+ found_orion = 1;
+ }
+ }
+ if (found824xx && bus == 0) {
+ bus++;
+ goto retry;
+ }
+
+ /*
+ * Make sure we add at least one bridge since some old
+ * hardware doesn't actually have a host-pci bridge device.
+ * Note that pci_cfgregopen() thinks we have PCI devices..
+ */
+ if (!found) {
+ if (bootverbose)
+ printf(
+ "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
+ child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
+ legacy_set_pcibus(child, 0);
+ }
+}
+
+static int
+legacy_pcib_probe(device_t dev)
+{
+
+ if (pci_cfgregopen() == 0)
+ return ENXIO;
+ return -100;
+}
+
+static int
+legacy_pcib_attach(device_t dev)
+{
+ device_t pir;
+ int bus;
+
+ /*
+ * Look for a PCI BIOS interrupt routing table as that will be
+ * our method of routing interrupts if we have one.
+ */
+ bus = pcib_get_bus(dev);
+ if (pci_pir_probe(bus, 0)) {
+ pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
+ if (pir != NULL)
+ device_probe_and_attach(pir);
+ }
+ device_add_child(dev, "pci", bus);
+ return bus_generic_attach(dev);
+}
+
+int
+legacy_pcib_read_ivar(device_t dev, device_t child, int which,
+ uintptr_t *result)
+{
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = 0;
+ return 0;
+ case PCIB_IVAR_BUS:
+ *result = legacy_get_pcibus(dev);
+ return 0;
+ }
+ return ENOENT;
+}
+
+int
+legacy_pcib_write_ivar(device_t dev, device_t child, int which,
+ uintptr_t value)
+{
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ return EINVAL;
+ case PCIB_IVAR_BUS:
+ legacy_set_pcibus(dev, value);
+ return 0;
+ }
+ return ENOENT;
+}
+
+SYSCTL_DECL(_hw_pci);
+
+static unsigned long legacy_host_mem_start = 0x80000000;
+TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
+SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
+ &legacy_host_mem_start, 0x80000000,
+ "Limit the host bridge memory to being above this address. Must be\n\
+set at boot via a tunable.");
+
+struct resource *
+legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ /*
+ * If no memory preference is given, use upper 32MB slot most
+ * bioses use for their memory window. Typically other bridges
+ * before us get in the way to assert their preferences on memory.
+ * Hardcoding like this sucks, so a more MD/MI way needs to be
+ * found to do it. This is typically only used on older laptops
+ * that don't have pci busses behind pci bridge, so assuming > 32MB
+ * is liekly OK.
+ *
+ * However, this can cause problems for other chipsets, so we make
+ * this tunable by hw.pci.host_mem_start.
+ */
+ if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
+ start = legacy_host_mem_start;
+ if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
+ start = 0x1000;
+ return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
+ count, flags));
+}
+
+static device_method_t legacy_pcib_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_identify, legacy_pcib_identify),
+ DEVMETHOD(device_probe, legacy_pcib_probe),
+ DEVMETHOD(device_attach, legacy_pcib_attach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
+ DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
+ DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
+ DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
+ DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
+ DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
+ DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
+ DEVMETHOD(pcib_release_msi, pcib_release_msi),
+ DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
+ DEVMETHOD(pcib_release_msix, pcib_release_msix),
+ DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi),
+
+ { 0, 0 }
+};
+
+static devclass_t hostb_devclass;
+
+DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
+DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
+
+
+/*
+ * Install placeholder to claim the resources owned by the
+ * PCI bus interface. This could be used to extract the
+ * config space registers in the extreme case where the PnP
+ * ID is available and the PCI BIOS isn't, but for now we just
+ * eat the PnP ID and do nothing else.
+ *
+ * XXX we should silence this probe, as it will generally confuse
+ * people.
+ */
+static struct isa_pnp_id pcibus_pnp_ids[] = {
+ { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
+ { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
+ { 0 }
+};
+
+static int
+pcibus_pnp_probe(device_t dev)
+{
+ int result;
+
+ if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
+ device_quiet(dev);
+ return(result);
+}
+
+static int
+pcibus_pnp_attach(device_t dev)
+{
+ return(0);
+}
+
+static device_method_t pcibus_pnp_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, pcibus_pnp_probe),
+ DEVMETHOD(device_attach, pcibus_pnp_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+ { 0, 0 }
+};
+
+static devclass_t pcibus_pnp_devclass;
+
+DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
+DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
+
+
+/*
+ * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
+ * that appear in the PCIBIOS Interrupt Routing Table to use the routing
+ * table for interrupt routing when possible.
+ */
+static int pcibios_pcib_probe(device_t bus);
+
+static device_method_t pcibios_pcib_pci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, pcibios_pcib_probe),
+ DEVMETHOD(device_attach, pcib_attach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_read_ivar, pcib_read_ivar),
+ DEVMETHOD(bus_write_ivar, pcib_write_ivar),
+ DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, pcib_maxslots),
+ DEVMETHOD(pcib_read_config, pcib_read_config),
+ DEVMETHOD(pcib_write_config, pcib_write_config),
+ DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
+ DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
+ DEVMETHOD(pcib_release_msi, pcib_release_msi),
+ DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
+ DEVMETHOD(pcib_release_msix, pcib_release_msix),
+ DEVMETHOD(pcib_map_msi, pcib_map_msi),
+
+ {0, 0}
+};
+
+static devclass_t pcib_devclass;
+
+DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
+ sizeof(struct pcib_softc));
+DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
+
+static int
+pcibios_pcib_probe(device_t dev)
+{
+ int bus;
+
+ if ((pci_get_class(dev) != PCIC_BRIDGE) ||
+ (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
+ return (ENXIO);
+ bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
+ if (bus == 0)
+ return (ENXIO);
+ if (!pci_pir_probe(bus, 1))
+ return (ENXIO);
+ device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
+ return (-2000);
+}
+
+static int
+pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
+{
+ return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
+ pci_get_function(dev), pin));
+}
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