[rtems commit] v850 port: Initial addition with BSP for simulator in GDB
Joel Sherrill
joel at rtems.org
Mon Jun 11 21:26:32 UTC 2012
Module: rtems
Branch: master
Commit: 2d7ae960bbdbc82f795814ee6c600e93200ddf4d
Changeset: http://git.rtems.org/rtems/commit/?id=2d7ae960bbdbc82f795814ee6c600e93200ddf4d
Author: Joel Sherrill <joel.sherrill at oarcorp.com>
Date: Mon Jun 11 13:37:29 2012 -0500
v850 port: Initial addition with BSP for simulator in GDB
Port
+ v850 does not have appear to have any optimized bit scan instructions
+ v850 does have single instructions for wap u16 and u32
+ Code path optimization preferences set
+ Add BSP variants for each GCC CPU model flag and a README
- v850e1 variant does not work (fails during BSP initialization)
BSP for GDB v850 Simulator
+ linkcmds matches defaults in GDB simulator with RTEMS mods
+ crt1.c added from v850 newlib port for __main()
+ BSP exits cleanly
+ printk and console I/O work
+ uses clock tick from IDLE task
+ Tests not requiring real clock ISR work
Documentation
+ CPU Supplment chapter for v850 added
---
c/src/aclocal/rtems-cpu-subdirs.m4 | 1 +
c/src/lib/libbsp/v850/Makefile.am | 15 +
c/src/lib/libbsp/v850/acinclude.m4 | 10 +
c/src/lib/libbsp/v850/configure.ac | 20 +
c/src/lib/libbsp/v850/gdbv850sim/Makefile.am | 53 +
c/src/lib/libbsp/v850/gdbv850sim/README | 7 +
c/src/lib/libbsp/v850/gdbv850sim/bsp_specs | 15 +
c/src/lib/libbsp/v850/gdbv850sim/configure.ac | 20 +
.../libbsp/v850/gdbv850sim/console/console-io.c | 61 +
c/src/lib/libbsp/v850/gdbv850sim/include/bsp.h | 37 +
.../libbsp/v850/gdbv850sim/include/bspopts.h.in | 31 +
c/src/lib/libbsp/v850/gdbv850sim/include/syscall.h | 47 +
.../v850/gdbv850sim/make/custom/v850e1sim.cfg | 7 +
.../v850/gdbv850sim/make/custom/v850e2sim.cfg | 7 +
.../v850/gdbv850sim/make/custom/v850e2v3sim.cfg | 7 +
.../v850/gdbv850sim/make/custom/v850esim.cfg | 7 +
.../v850/gdbv850sim/make/custom/v850essim.cfg | 7 +
.../libbsp/v850/gdbv850sim/make/custom/v850sim.cfg | 8 +
.../libbsp/v850/gdbv850sim/make/custom/v850sim.inc | 12 +
c/src/lib/libbsp/v850/gdbv850sim/preinstall.am | 71 ++
c/src/lib/libbsp/v850/gdbv850sim/start/start.S | 78 ++
.../lib/libbsp/v850/gdbv850sim/startup/bspreset.c | 23 +
c/src/lib/libbsp/v850/gdbv850sim/startup/linkcmds | 214 ++++
c/src/lib/libbsp/v850/gdbv850sim/startup/trap.S | 14 +
c/src/lib/libbsp/v850/preinstall.am | 7 +
c/src/lib/libbsp/v850/shared/crt1.c | 21 +
cpukit/configure.ac | 1 +
cpukit/librpc/src/xdr/xdr_float.c | 3 +-
cpukit/score/cpu/Makefile.am | 1 +
cpukit/score/cpu/v850/Makefile.am | 17 +
cpukit/score/cpu/v850/cpu.c | 98 ++
cpukit/score/cpu/v850/cpu_asm.S | 213 ++++
cpukit/score/cpu/v850/preinstall.am | 45 +
cpukit/score/cpu/v850/rtems/asm.h | 125 ++
cpukit/score/cpu/v850/rtems/score/cpu.h | 1188 ++++++++++++++++++++
cpukit/score/cpu/v850/rtems/score/cpu_asm.h | 71 ++
cpukit/score/cpu/v850/rtems/score/types.h | 41 +
cpukit/score/cpu/v850/rtems/score/v850.h | 126 +++
doc/cpu_supplement/Makefile.am | 9 +-
doc/cpu_supplement/v850.t | 104 ++
40 files changed, 2839 insertions(+), 3 deletions(-)
diff --git a/c/src/aclocal/rtems-cpu-subdirs.m4 b/c/src/aclocal/rtems-cpu-subdirs.m4
index 59c8211..c18096a 100644
--- a/c/src/aclocal/rtems-cpu-subdirs.m4
+++ b/c/src/aclocal/rtems-cpu-subdirs.m4
@@ -26,6 +26,7 @@ _RTEMS_CPU_SUBDIR([powerpc],[$1]);;
_RTEMS_CPU_SUBDIR([sh],[$1]);;
_RTEMS_CPU_SUBDIR([sparc],[$1]);;
_RTEMS_CPU_SUBDIR([sparc64],[$1]);;
+_RTEMS_CPU_SUBDIR([v850],[$1]);;
*) AC_MSG_ERROR([Invalid RTEMS_CPU <[$]{RTEMS_CPU}>])
esac
])
diff --git a/c/src/lib/libbsp/v850/Makefile.am b/c/src/lib/libbsp/v850/Makefile.am
new file mode 100644
index 0000000..d5747be
--- /dev/null
+++ b/c/src/lib/libbsp/v850/Makefile.am
@@ -0,0 +1,15 @@
+##
+##
+
+ACLOCAL_AMFLAGS = -I ../../../aclocal
+
+## Descend into the @RTEMS_BSP_FAMILY@ directory
+## Currently, the shared directory is not explicitly
+## added but it is present in the source tree.
+SUBDIRS = @RTEMS_BSP_FAMILY@
+
+EXTRA_DIST =
+
+include $(srcdir)/preinstall.am
+include $(top_srcdir)/../../../automake/subdirs.am
+include $(top_srcdir)/../../../automake/local.am
diff --git a/c/src/lib/libbsp/v850/acinclude.m4 b/c/src/lib/libbsp/v850/acinclude.m4
new file mode 100644
index 0000000..f506ece
--- /dev/null
+++ b/c/src/lib/libbsp/v850/acinclude.m4
@@ -0,0 +1,10 @@
+# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY)
+AC_DEFUN([RTEMS_CHECK_BSPDIR],
+[
+ case "$1" in
+ gdbv850sim )
+ AC_CONFIG_SUBDIRS([gdbv850sim]);;
+ *)
+ AC_MSG_ERROR([Invalid BSP]);;
+ esac
+])
diff --git a/c/src/lib/libbsp/v850/configure.ac b/c/src/lib/libbsp/v850/configure.ac
new file mode 100644
index 0000000..58160c0
--- /dev/null
+++ b/c/src/lib/libbsp/v850/configure.ac
@@ -0,0 +1,20 @@
+## Process this file with autoconf to produce a configure script.
+##
+
+AC_PREREQ([2.68])
+AC_INIT([rtems-c-src-lib-libbsp-v850],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
+AC_CONFIG_SRCDIR([gdbv850sim])
+RTEMS_TOP(../../../../..)
+
+RTEMS_CANONICAL_TARGET_CPU
+AM_INIT_AUTOMAKE([no-define foreign 1.11.1])
+AM_MAINTAINER_MODE
+
+RTEMS_ENV_RTEMSBSP
+RTEMS_PROJECT_ROOT
+
+RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY])
+
+# Explicitly list all Makefiles here
+AC_CONFIG_FILES([Makefile])
+AC_OUTPUT
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/Makefile.am b/c/src/lib/libbsp/v850/gdbv850sim/Makefile.am
new file mode 100644
index 0000000..e7e4c49
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/Makefile.am
@@ -0,0 +1,53 @@
+##
+##
+
+ACLOCAL_AMFLAGS = -I ../../../../aclocal
+
+include $(top_srcdir)/../../../../automake/compile.am
+include $(top_srcdir)/../../bsp.am
+
+include_bspdir = $(includedir)/bsp
+
+dist_project_lib_DATA = bsp_specs
+
+include_HEADERS = include/bsp.h
+include_HEADERS += ../../shared/include/tm27.h
+include_bsp_HEADERS = include/syscall.h
+
+nodist_include_HEADERS = include/bspopts.h
+nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
+DISTCLEANFILES = include/bspopts.h
+noinst_PROGRAMS =
+
+nodist_include_HEADERS += ../../shared/include/coverhd.h
+
+EXTRA_DIST = start/start.S
+start.$(OBJEXT): start/start.S
+ $(CPPASCOMPILE) -o $@ -c $<
+project_lib_DATA = start.$(OBJEXT)
+
+dist_project_lib_DATA += startup/linkcmds
+
+libbsp_a_SOURCES = ../../shared/bspclean.c
+libbsp_a_SOURCES += ../../shared/bsplibc.c
+libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
+libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
+libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
+libbsp_a_SOURCES += ../../shared/bsppost.c
+libbsp_a_SOURCES += ../../shared/bspstart.c
+libbsp_a_SOURCES += ../../shared/bootcard.c
+libbsp_a_SOURCES += ../../shared/sbrk.c
+libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
+libbsp_a_SOURCES += startup/bspreset.c
+libbsp_a_SOURCES += ../../v850/shared/crt1.c
+libbsp_a_SOURCES += startup/trap.S
+
+libbsp_a_SOURCES += ../../shared/clock_driver_simidle.c
+libbsp_a_SOURCES += ../../shared/console-polled.c
+libbsp_a_SOURCES += console/console-io.c
+libbsp_a_SOURCES += ../../shared/timerstub.c
+
+noinst_LIBRARIES = libbsp.a
+
+include $(srcdir)/preinstall.am
+include $(top_srcdir)/../../../../automake/local.am
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/README b/c/src/lib/libbsp/v850/gdbv850sim/README
new file mode 100644
index 0000000..ab456d2
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/README
@@ -0,0 +1,7 @@
+This directory contains a family of BSPs for the v850 simulator
+found in the GNU Debugger. A variant is provided for each CPU
+model option flag found in the GCC SVN head as of 30 May 2012.
+
+This simulator is an instruction simulator and does not include
+devices for a clock tick or benchmark timer driver. Traps are used
+to provide console I/O.
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/bsp_specs b/c/src/lib/libbsp/v850/gdbv850sim/bsp_specs
new file mode 100644
index 0000000..bb7833b
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/bsp_specs
@@ -0,0 +1,15 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+%rename link old_link
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: start.o%s -e _start}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: %(old_endfile)} \
+%{!nostdlib: %{qrtems:}}
+
+*link:
+%(old_link) %{!qrtems: %(old_link)} %{qrtems: %(old_link)}
+
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/configure.ac b/c/src/lib/libbsp/v850/gdbv850sim/configure.ac
new file mode 100644
index 0000000..84e66e9
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/configure.ac
@@ -0,0 +1,20 @@
+## Process this file with autoconf to produce a configure script.
+
+AC_PREREQ([2.68])
+AC_INIT([rtems-c-src-lib-libbsp-v850-gdbv850sim],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
+AC_CONFIG_SRCDIR([bsp_specs])
+RTEMS_TOP(../../../../../..)
+
+RTEMS_CANONICAL_TARGET_CPU
+AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.11.1])
+RTEMS_BSP_CONFIGURE
+
+RTEMS_PROG_CC_FOR_TARGET
+RTEMS_CANONICALIZE_TOOLS
+RTEMS_PROG_CCAS
+
+RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
+
+# Explicitly list all Makefiles here
+AC_CONFIG_FILES([Makefile])
+AC_OUTPUT
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/console/console-io.c b/c/src/lib/libbsp/v850/gdbv850sim/console/console-io.c
new file mode 100644
index 0000000..ddaa115
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/console/console-io.c
@@ -0,0 +1,61 @@
+/*
+ * COPYRIGHT (c) 1989-2012.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <rtems/libio.h>
+#include <bsp/syscall.h>
+
+/*
+ * console_initialize_hardware
+ *
+ * This routine initializes the console hardware.
+ */
+void console_initialize_hardware(void)
+{
+}
+
+/*
+ * console_outbyte_polled
+ *
+ * This routine transmits a character using polling.
+ */
+void console_outbyte_polled(
+ int port,
+ char ch
+)
+{
+ TRAP0(SYS_write, 1, &ch, 1);
+}
+
+/*
+ * console_inbyte_nonblocking
+ *
+ * This routine polls for a character.
+ */
+
+int console_inbyte_nonblocking(
+ int port
+)
+{
+ char ch;
+ int rc;
+
+ rc = TRAP0 (SYS_read, 0, &ch, 1);
+
+ if ( rc != 1 )
+ return -1;
+ return ch;
+}
+
+#include <rtems/bspIo.h>
+
+void console_output_char(char c) { console_outbyte_polled( 0, c ); }
+
+BSP_output_char_function_type BSP_output_char = console_output_char;
+BSP_polling_getchar_function_type BSP_poll_char = NULL;
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/include/bsp.h b/c/src/lib/libbsp/v850/gdbv850sim/include/bsp.h
new file mode 100644
index 0000000..807203f
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/include/bsp.h
@@ -0,0 +1,37 @@
+/*
+ * This include file contains some definitions specific to the
+ * GDB simulator in gdb.
+ */
+
+/*
+ * COPYRIGHT (c) 1989-2012.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef _BSP_H
+#define _BSP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <bspopts.h>
+
+#include <rtems.h>
+#include <rtems/iosupp.h>
+#include <rtems/console.h>
+#include <rtems/clockdrv.h>
+
+/* support for simulated clock tick */
+Thread clock_driver_sim_idle_body(uintptr_t);
+#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/include/bspopts.h.in b/c/src/lib/libbsp/v850/gdbv850sim/include/bspopts.h.in
new file mode 100644
index 0000000..40e048c
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/include/bspopts.h.in
@@ -0,0 +1,31 @@
+/* include/bspopts.h.in. Generated from configure.ac by autoheader. */
+
+/* If defined, then the BSP Framework will put a non-zero pattern into the
+ RTEMS Workspace and C program heap. This should assist in finding code that
+ assumes memory starts set to zero. */
+#undef BSP_DIRTY_MEMORY
+
+/* If defined, print a message and wait until pressed before resetting board
+ when application exits. */
+#undef BSP_PRESS_KEY_FOR_RESET
+
+/* If defined, reset the board when the application exits. */
+#undef BSP_RESET_BOARD_AT_EXIT
+
+/* Define to the address where bug reports for this package should be sent. */
+#undef PACKAGE_BUGREPORT
+
+/* Define to the full name of this package. */
+#undef PACKAGE_NAME
+
+/* Define to the full name and version of this package. */
+#undef PACKAGE_STRING
+
+/* Define to the one symbol short name of this package. */
+#undef PACKAGE_TARNAME
+
+/* Define to the home page for this package. */
+#undef PACKAGE_URL
+
+/* Define to the version of this package. */
+#undef PACKAGE_VERSION
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/include/syscall.h b/c/src/lib/libbsp/v850/gdbv850sim/include/syscall.h
new file mode 100644
index 0000000..d8eebdd
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/include/syscall.h
@@ -0,0 +1,47 @@
+/* from libgloss/v850 */
+#ifndef _SYS_SYSCALL_H_
+#define _SYS_SYSCALL_H_
+
+#ifndef ASM
+extern int __trap0 (int function, int p1, int p2, int p3);
+
+#define TRAP0(f, p1, p2, p3) __trap0(f, (int)(p1), (int)(p2), (int)(p3))
+#endif
+
+#define SYS_exit 1
+#define SYS_fork 2
+
+#define SYS_read 3
+#define SYS_write 4
+#define SYS_open 5
+#define SYS_close 6
+#define SYS_wait4 7
+#define SYS_creat 8
+#define SYS_link 9
+#define SYS_unlink 10
+#define SYS_execv 11
+#define SYS_chdir 12
+#define SYS_mknod 14
+#define SYS_chmod 15
+#define SYS_chown 16
+#define SYS_lseek 19
+#define SYS_getpid 20
+#define SYS_isatty 21
+#define SYS_fstat 22
+#define SYS_time 23
+
+
+#define SYS_ARG 24
+#define SYS_stat 38
+
+
+#define SYS_pipe 42
+#define SYS_execve 59
+#define SYS_times 43
+#define SYS_gettimeofday 116
+#define SYS_rename 134
+
+#define SYS_utime 201 /* not really a system call */
+#define SYS_wait 202 /* nor is this */
+
+#endif
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e1sim.cfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e1sim.cfg
new file mode 100644
index 0000000..7aefdcf
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e1sim.cfg
@@ -0,0 +1,7 @@
+#
+# Base Config file for the v850 GDB Simulator as v850e1
+#
+
+CPU_CFLAGS = -mv850e1
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2sim.cfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2sim.cfg
new file mode 100644
index 0000000..0313ab8
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2sim.cfg
@@ -0,0 +1,7 @@
+#
+# Base Config file for the v850 GDB Simulator as v850e2
+#
+
+CPU_CFLAGS = -mv850e2
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2v3sim.cfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2v3sim.cfg
new file mode 100644
index 0000000..ac2740e
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2v3sim.cfg
@@ -0,0 +1,7 @@
+#
+# Base Config file for the v850 GDB Simulator as v850e2v3
+#
+
+CPU_CFLAGS = -mv850e2v3
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850esim.cfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850esim.cfg
new file mode 100644
index 0000000..0c0a4a9
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850esim.cfg
@@ -0,0 +1,7 @@
+#
+# Base Config file for the v850 GDB Simulator as v850e
+#
+
+CPU_CFLAGS = -mv850e
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850essim.cfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850essim.cfg
new file mode 100644
index 0000000..7759459
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850essim.cfg
@@ -0,0 +1,7 @@
+#
+# Base Config file for the v850 GDB Simulator as v850es
+#
+
+CPU_CFLAGS = -mv850es
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.cfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.cfg
new file mode 100644
index 0000000..9dcc918
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.cfg
@@ -0,0 +1,8 @@
+#
+# Base Config file for the v850 GDB Simulator as v850
+#
+
+# This is the same as not specifying a CPU model flag.
+CPU_CFLAGS = -mv850
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.inc b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.inc
new file mode 100644
index 0000000..50de3fa
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.inc
@@ -0,0 +1,12 @@
+#
+# Shared config file for the v850 GDB Simulator
+#
+# CPU_CFLAGS is set by each specific variant.
+
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU=v850
+RTEMS_CPU_MODEL=v850
+
+# optimize flag: typically -O2
+CFLAGS_OPTIMIZE_V = -O2 -g
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/preinstall.am b/c/src/lib/libbsp/v850/gdbv850sim/preinstall.am
new file mode 100644
index 0000000..1fc9abe
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/preinstall.am
@@ -0,0 +1,71 @@
+## Automatically generated by ampolish3 - Do not edit
+
+if AMPOLISH3
+$(srcdir)/preinstall.am: Makefile.am
+ $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
+endif
+
+PREINSTALL_DIRS =
+DISTCLEANFILES += $(PREINSTALL_DIRS)
+
+all-local: $(TMPINSTALL_FILES)
+
+TMPINSTALL_FILES =
+CLEANFILES = $(TMPINSTALL_FILES)
+
+all-am: $(PREINSTALL_FILES)
+
+PREINSTALL_FILES =
+CLEANFILES += $(PREINSTALL_FILES)
+
+$(PROJECT_LIB)/$(dirstamp):
+ @$(MKDIR_P) $(PROJECT_LIB)
+ @: > $(PROJECT_LIB)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
+
+$(PROJECT_INCLUDE)/$(dirstamp):
+ @$(MKDIR_P) $(PROJECT_INCLUDE)
+ @: > $(PROJECT_INCLUDE)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
+
+$(PROJECT_INCLUDE)/bsp/$(dirstamp):
+ @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
+ @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+
+$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
+PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
+
+$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
+
+$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
+
+$(PROJECT_INCLUDE)/bsp/syscall.h: include/syscall.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/syscall.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/syscall.h
+
+$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
+
+$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
+
+$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
+
+$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
+TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
+
+$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
+PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
+
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/start/start.S b/c/src/lib/libbsp/v850/gdbv850sim/start/start.S
new file mode 100644
index 0000000..419e635
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/start/start.S
@@ -0,0 +1,78 @@
+# NEC V850 startup code
+
+ .section .text
+ .global _start
+
+_start:
+
+#if defined(__v850e__) || defined(__v850e2__) || defined(__v850e2v3__)
+
+ movea 255, r0, r20
+ mov 65535, r21
+ mov hilo(_stack), sp
+ mov hilo(__ep), ep
+ mov hilo(__gp), gp
+ mov hilo(__ctbp), r6
+ ldsr r6, ctbp
+ mov hilo(_edata), r6
+ mov hilo(_end), r7
+.L0:
+ st.w r0, 0[r6]
+ addi 4, r6, r6
+ cmp r7, r6
+ bl .L0
+.L1:
+ jarl ___main, r31
+ addi -16, sp, sp
+ mov 0, r6
+ mov 0, r7
+ mov 0, r8
+ /* jarl _main, r31 */
+ jarl _boot_card, r31
+ mov r10, r6
+ jarl _exit, r31
+
+# else
+ movea 255, r0, r20
+ mov r0, r21
+ ori 65535, r0, r21
+ movhi hi(_stack), r0, sp
+ movea lo(_stack), sp, sp
+ movhi hi(__ep), r0, ep
+ movea lo(__ep), ep, ep
+ movhi hi(__gp), r0, gp
+ movea lo(__gp), gp, gp
+
+ movhi hi(_edata), r0, r6
+ movea lo(_edata), r6, r6
+ movhi hi(_end), r0, r7
+ movea lo(_end), r7, r7
+.L0:
+ st.b r0, 0[r6]
+ addi 1, r6, r6
+ cmp r7, r6
+ bl .L0
+.L1:
+ /* jarl ___main, r31 */
+ addi -16, sp, sp
+ mov 0, r6
+ mov 0, r7
+ mov 0, r8
+ /* jarl _main, r31 */
+ jarl _boot_card, r31
+ mov r10, r6
+.L2:
+ br .L2
+ /* jarl _exit, r31 */
+# endif
+
+#if 0
+ .section .stack
+_stack: .long 1
+#endif
+
+ .section .data
+ .global ___dso_handle
+ .weak ___dso_handle
+___dso_handle:
+ .long 0
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/startup/bspreset.c b/c/src/lib/libbsp/v850/gdbv850sim/startup/bspreset.c
new file mode 100644
index 0000000..a57512c
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/startup/bspreset.c
@@ -0,0 +1,23 @@
+/**
+ * @file
+ *
+ * This routine exits the simulator.
+ */
+
+/*
+ * COPYRIGHT (c) 1989-2012.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <bsp/bootcard.h>
+#include <bsp/syscall.h>
+
+void bsp_reset( void )
+{
+ TRAP0 (SYS_exit, 0, 0, 0);
+}
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/startup/linkcmds b/c/src/lib/libbsp/v850/gdbv850sim/startup/linkcmds
new file mode 100644
index 0000000..cf30f3b
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/startup/linkcmds
@@ -0,0 +1,214 @@
+/*
+ * Declare some sizes.
+ */
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x100000; /* RAM starts at 1MB */
+_RamSize = DEFINED(_RamSize) ? _RamSize : 0x100000; /* default is 1MB */
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
+
+/* Default linker script, for normal executables */
+OUTPUT_FORMAT("elf32-v850", "elf32-v850",
+ "elf32-v850")
+OUTPUT_ARCH(v850)
+ENTRY(_start)
+/* GROUP(-lc -lsim -lgcc) */
+SEARCH_DIR(.);
+EXTERN(__ctbp __ep __gp);
+SECTIONS
+{
+ /* This saves a little space in the ELF file, since the zda starts
+ at a higher location that the ELF headers take up. */
+ .zdata 0x160 :
+ {
+ *(.zdata)
+ *(.zbss)
+ *(reszdata)
+ *(.zcommon)
+ }
+ /* This is the read only part of the zero data area.
+ Having it as a seperate section prevents its
+ attributes from being inherited by the zdata
+ section. Specifically it prevents the zdata
+ section from being marked READONLY. */
+ .rozdata ALIGN (4) :
+ {
+ *(.rozdata)
+ *(romzdata)
+ *(romzbss)
+ }
+ /* Read-only sections, merged into text segment. */
+ . = 0x100000;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.gcc_except_table : { *(.rel.gcc_except_table) }
+ .rela.gcc_except_table : { *(.rela.gcc_except_table) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.init : { *(.rel.init) }
+ .rela.init : { *(.rela.init) }
+ .rel.fini : { *(.rel.fini) }
+ .rela.fini : { *(.rela.fini) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { KEEP (*(.init)) } =0
+ .plt : { *(.plt) }
+ .text :
+ {
+ *(.text)
+ *(.text.*)
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.gnu.linkonce.t*)
+ } =0
+ _etext = .;
+ PROVIDE (etext = .);
+ /* This is special code area at the end of the normal text section.
+ It contains a small lookup table at the start followed by the
+ code pointed to by entries in the lookup table. */
+ .call_table_data ALIGN (4) :
+ {
+ PROVIDE(__ctbp = .);
+ *(.call_table_data)
+ } = 0xff /* Fill gaps with 0xff. */
+ .call_table_text :
+ {
+ *(.call_table_text)
+ }
+ .fini : { KEEP (*(.fini)) } =0
+ .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) }
+ .rodata1 : { *(.rodata1) }
+ .data :
+ {
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+ CONSTRUCTORS
+ }
+ .data1 : { *(.data1) }
+ .ctors :
+ {
+ ___ctors = .;
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend(.ctors))
+ ___ctors_end = .;
+ }
+ .dtors :
+ {
+ ___dtors = .;
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ ___dtors_end = .;
+ }
+ .jcr :
+ {
+ KEEP (*(.jcr))
+ }
+ .gcc_except_table : { *(.gcc_except_table) }
+ .got : { *(.got.plt) *(.got) }
+ .dynamic : { *(.dynamic) }
+ .tdata ALIGN (4) :
+ {
+ PROVIDE (__ep = .);
+ *(.tbyte)
+ *(.tcommon_byte)
+ *(.tdata)
+ *(.tbss)
+ *(.tcommon)
+ }
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ .sdata ALIGN (4) :
+ {
+ PROVIDE (__gp = . + 0x8000);
+ *(.sdata)
+ }
+ /* See comment about .rozdata. */
+ .rosdata ALIGN (4) :
+ {
+ *(.rosdata)
+ }
+ /* We place the .sbss data section AFTER the .rosdata section, so that
+ it can directly preceed the .bss section. This allows runtime startup
+ code to initialise all the zero-data sections by simply taking the
+ value of '_edata' and zeroing until it reaches '_end'. */
+ .sbss :
+ {
+ __sbss_start = .;
+ *(.sbss)
+ *(.scommon)
+ }
+ _edata = DEFINED (__sbss_start) ? __sbss_start : . ;
+ PROVIDE (edata = _edata);
+ .bss :
+ {
+ __bss_start = DEFINED (__sbss_start) ? __sbss_start : . ;
+ __real_bss_start = . ;
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ . += _StackSize;
+ _stack = .;
+ _WorkAreaBase = .;
+ _end = . ;
+ PROVIDE (end = .);
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions. */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* libgloss - User stack. */
+/*
+ .stack 0x200000 :
+ {
+ __stack = .;
+ *(.stack)
+ }
+*/
+}
+
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/startup/trap.S b/c/src/lib/libbsp/v850/gdbv850sim/startup/trap.S
new file mode 100644
index 0000000..b6003b2
--- /dev/null
+++ b/c/src/lib/libbsp/v850/gdbv850sim/startup/trap.S
@@ -0,0 +1,14 @@
+/* from libgloss/v850 */
+ .text
+ .global ___trap0
+___trap0:
+ trap 31
+ tst r10,r10
+ bz .L0
+/*
+ * Libgloss cares about the errno from this. We don't
+ movhi hi(_errno),r0,r6
+ st.w r10,lo(_errno)[r6]
+*/
+.L0:
+ jmp [r31]
diff --git a/c/src/lib/libbsp/v850/preinstall.am b/c/src/lib/libbsp/v850/preinstall.am
new file mode 100644
index 0000000..dba6cc4
--- /dev/null
+++ b/c/src/lib/libbsp/v850/preinstall.am
@@ -0,0 +1,7 @@
+## Automatically generated by ampolish3 - Do not edit
+
+if AMPOLISH3
+$(srcdir)/preinstall.am: Makefile.am
+ $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
+endif
+
diff --git a/c/src/lib/libbsp/v850/shared/crt1.c b/c/src/lib/libbsp/v850/shared/crt1.c
new file mode 100644
index 0000000..18c240b
--- /dev/null
+++ b/c/src/lib/libbsp/v850/shared/crt1.c
@@ -0,0 +1,21 @@
+/*
+ * From newlib ==> libc/sys/sysnecv850/crt1.c
+ *
+ * Obtained newlib 29 May 2012
+ */
+void __main ()
+{
+ static int initialized;
+ if (! initialized)
+ {
+ typedef void (*pfunc) ();
+ extern pfunc __ctors[];
+ extern pfunc __ctors_end[];
+ pfunc *p;
+
+ initialized = 1;
+ for (p = __ctors_end; p > __ctors; )
+ (*--p) ();
+
+ }
+}
diff --git a/cpukit/configure.ac b/cpukit/configure.ac
index 85b10c3..20f43a0 100644
--- a/cpukit/configure.ac
+++ b/cpukit/configure.ac
@@ -366,6 +366,7 @@ score/cpu/powerpc/Makefile
score/cpu/sh/Makefile
score/cpu/sparc/Makefile
score/cpu/sparc64/Makefile
+score/cpu/v850/Makefile
score/cpu/no_cpu/Makefile
posix/Makefile
libblock/Makefile
diff --git a/cpukit/librpc/src/xdr/xdr_float.c b/cpukit/librpc/src/xdr/xdr_float.c
index 544a52b..2517072 100644
--- a/cpukit/librpc/src/xdr/xdr_float.c
+++ b/cpukit/librpc/src/xdr/xdr_float.c
@@ -75,7 +75,8 @@ static char *rcsid = "$FreeBSD: src/lib/libc/xdr/xdr_float.c,v 1.7 1999/08/28 00
defined(__AVR__) || \
defined(__BFIN__) || \
defined(__m32c__) || \
- defined(__M32R__)
+ defined(__M32R__) || \
+ defined(__v850)
#include <rtems/endian.h>
#if !defined(IEEEFP)
diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am
index 3647989..a84eb07 100644
--- a/cpukit/score/cpu/Makefile.am
+++ b/cpukit/score/cpu/Makefile.am
@@ -17,6 +17,7 @@ DIST_SUBDIRS += powerpc
DIST_SUBDIRS += sh
DIST_SUBDIRS += sparc
DIST_SUBDIRS += sparc64
+DIST_SUBDIRS += v850
include $(top_srcdir)/automake/subdirs.am
include $(top_srcdir)/automake/local.am
diff --git a/cpukit/score/cpu/v850/Makefile.am b/cpukit/score/cpu/v850/Makefile.am
new file mode 100644
index 0000000..2119f62
--- /dev/null
+++ b/cpukit/score/cpu/v850/Makefile.am
@@ -0,0 +1,17 @@
+include $(top_srcdir)/automake/compile.am
+
+include_rtemsdir = $(includedir)/rtems
+include_rtems_HEADERS = rtems/asm.h
+
+include_rtems_scoredir = $(includedir)/rtems/score
+include_rtems_score_HEADERS = rtems/score/cpu.h
+include_rtems_score_HEADERS += rtems/score/v850.h
+include_rtems_score_HEADERS += rtems/score/cpu_asm.h rtems/score/types.h
+
+noinst_LIBRARIES = libscorecpu.a
+libscorecpu_a_SOURCES = cpu.c
+libscorecpu_a_SOURCES += cpu_asm.S
+libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
+
+include $(srcdir)/preinstall.am
+include $(top_srcdir)/automake/local.am
diff --git a/cpukit/score/cpu/v850/cpu.c b/cpukit/score/cpu/v850/cpu.c
new file mode 100644
index 0000000..6a7dd20
--- /dev/null
+++ b/cpukit/score/cpu/v850/cpu.c
@@ -0,0 +1,98 @@
+/**
+ * @file
+ *
+ * v850 CPU Dependent Source
+ */
+
+/*
+ * COPYRIGHT (c) 1989-2012.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems/system.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/wkspace.h>
+
+#include <string.h> /* for memset */
+
+/*
+ * v850 Specific Information:
+ *
+ * So far nothing known to be needed at this point during initialization.
+ */
+void _CPU_Initialize(void)
+{
+}
+
+/*
+ * v850 Specific Information:
+ *
+ * This method returns 0 if interrupts are enabled and 1 if they are disabled.
+ * The v850 only has two interrupt levels (on and off).
+ */
+uint32_t _CPU_ISR_Get_level( void )
+{
+ unsigned int psw;
+
+ v850_get_psw( psw );
+
+ if ( (psw & V850_PSW_INTERRUPT_DISABLE_MASK) == V850_PSW_INTERRUPT_DISABLE )
+ return 1;
+
+ return 0;
+}
+
+/*
+ * v850 Specific Information:
+ *
+ * This method initializes a v850 context control structure.
+ */
+void _CPU_Context_Initialize(
+ Context_Control *the_context,
+ uint32_t *stack_base,
+ uint32_t size,
+ uint32_t new_level,
+ void *entry_point,
+ bool is_fp
+)
+{
+ uint32_t stack_high; /* highest "stack aligned" address */
+ uint32_t psw; /* highest "stack aligned" address */
+
+ memset( the_context, 0, sizeof(Context_Control) );
+
+ /*
+ * On CPUs with stacks which grow down, we build the stack
+ * based on the stack_high address.
+ */
+ stack_high = ((uint32_t)(stack_base) + size);
+ stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
+
+ v850_get_psw( psw );
+ psw &= ~V850_PSW_INTERRUPT_DISABLE_MASK;
+ if ( new_level )
+ psw |= V850_PSW_INTERRUPT_DISABLE;
+ else
+ psw |= V850_PSW_INTERRUPT_ENABLE;
+
+ the_context->r31 = (uint32_t) entry_point;
+ the_context->r3_stack_pointer = stack_high;
+ the_context->psw = psw;
+
+#if 0
+ printk( "the_context = %p\n", the_context );
+ printk( "stack base = 0x%08x\n", stack_base );
+ printk( "stack size = 0x%08x\n", size );
+ printk( "sp = 0x%08x\n", the_context->r3_stack_pointer );
+ printk( "psw = 0x%08x\n", the_context->psw );
+#endif
+}
+
diff --git a/cpukit/score/cpu/v850/cpu_asm.S b/cpukit/score/cpu/v850/cpu_asm.S
new file mode 100644
index 0000000..d96e3ba
--- /dev/null
+++ b/cpukit/score/cpu/v850/cpu_asm.S
@@ -0,0 +1,213 @@
+/**
+ * @file
+ *
+ * This file contains the basic algorithms for all assembly code used
+ * in an specific CPU port of RTEMS. These algorithms must be implemented
+ * in assembly language
+ */
+
+/*
+ * COPYRIGHT (c) 1989-2012.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#if 0
+/**
+ * This routine is responsible for saving the FP context
+ * at *fp_context_ptr. If the point to load the FP context
+ * from is changed then the pointer is modified by this routine.
+ *
+ * Sometimes a macro implementation of this is in cpu.h which dereferences
+ * the ** and a similarly named routine in this file is passed something
+ * like a (Context_Control_fp *). The general rule on making this decision
+ * is to avoid writing assembly language.
+ *
+ * v850 Specific Information:
+ *
+ * The v850 appears to always have soft float.
+ */
+void _CPU_Context_save_fp(
+ Context_Control_fp **fp_context_ptr
+)
+{
+}
+
+/**
+ * This routine is responsible for restoring the FP context
+ * at *fp_context_ptr. If the point to load the FP context
+ * from is changed then the pointer is modified by this routine.
+ *
+ * Sometimes a macro implementation of this is in cpu.h which dereferences
+ * the ** and a similarly named routine in this file is passed something
+ * like a (Context_Control_fp *). The general rule on making this decision
+ * is to avoid writing assembly language.
+ *
+ * v850 Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+void _CPU_Context_restore_fp(
+ Context_Control_fp **fp_context_ptr
+)
+{
+}
+#endif
+
+/**
+ * This routine performs a normal non-FP context switch.
+ *
+ * v850 Specific Information:
+ *
+ * + r6 - running thread
+ * + r7 - heir thread
+ */
+#define V850_CONTEXT_CONTROL_R1_OFFSET 0
+#define V850_CONTEXT_CONTROL_R3_OFFSET 4
+#define V850_CONTEXT_CONTROL_R20_OFFSET 8
+#define V850_CONTEXT_CONTROL_R21_OFFSET 12
+#define V850_CONTEXT_CONTROL_R22_OFFSET 16
+#define V850_CONTEXT_CONTROL_R23_OFFSET 20
+#define V850_CONTEXT_CONTROL_R24_OFFSET 24
+#define V850_CONTEXT_CONTROL_R25_OFFSET 28
+#define V850_CONTEXT_CONTROL_R26_OFFSET 32
+#define V850_CONTEXT_CONTROL_R27_OFFSET 36
+#define V850_CONTEXT_CONTROL_R28_OFFSET 40
+#define V850_CONTEXT_CONTROL_R29_OFFSET 44
+#define V850_CONTEXT_CONTROL_R31_OFFSET 48
+#define V850_CONTEXT_CONTROL_PSW_OFFSET 52
+
+ .section .text
+ .global __CPU_Context_switch
+ .type __CPU_Context_switch, @function
+__CPU_Context_switch:
+ st.w r1,V850_CONTEXT_CONTROL_R1_OFFSET[r6]
+ st.w r3,V850_CONTEXT_CONTROL_R3_OFFSET[r6]
+ st.w r20,V850_CONTEXT_CONTROL_R20_OFFSET[r6]
+ st.w r21,V850_CONTEXT_CONTROL_R21_OFFSET[r6]
+ st.w r22,V850_CONTEXT_CONTROL_R22_OFFSET[r6]
+ st.w r23,V850_CONTEXT_CONTROL_R23_OFFSET[r6]
+ st.w r24,V850_CONTEXT_CONTROL_R24_OFFSET[r6]
+ st.w r25,V850_CONTEXT_CONTROL_R25_OFFSET[r6]
+ st.w r26,V850_CONTEXT_CONTROL_R27_OFFSET[r6]
+ st.w r27,V850_CONTEXT_CONTROL_R27_OFFSET[r6]
+ st.w r28,V850_CONTEXT_CONTROL_R28_OFFSET[r6]
+ st.w r29,V850_CONTEXT_CONTROL_R29_OFFSET[r6]
+ st.w r31,V850_CONTEXT_CONTROL_R31_OFFSET[r6]
+ stsr psw,r21
+ st.w r21,V850_CONTEXT_CONTROL_PSW_OFFSET[r6]
+restore:
+ ld.w V850_CONTEXT_CONTROL_R1_OFFSET[r7],r1
+ ld.w V850_CONTEXT_CONTROL_R3_OFFSET[r7],r3
+ ld.w V850_CONTEXT_CONTROL_R20_OFFSET[r7],r20
+ ld.w V850_CONTEXT_CONTROL_R21_OFFSET[r7],r21
+ ld.w V850_CONTEXT_CONTROL_R22_OFFSET[r7],r22
+ ld.w V850_CONTEXT_CONTROL_R23_OFFSET[r7],r23
+ ld.w V850_CONTEXT_CONTROL_R24_OFFSET[r7],r24
+ ld.w V850_CONTEXT_CONTROL_R25_OFFSET[r7],r25
+ ld.w V850_CONTEXT_CONTROL_R27_OFFSET[r7],r26
+ ld.w V850_CONTEXT_CONTROL_R27_OFFSET[r7],r27
+ ld.w V850_CONTEXT_CONTROL_R28_OFFSET[r7],r28
+ ld.w V850_CONTEXT_CONTROL_R29_OFFSET[r7],r29
+ ld.w V850_CONTEXT_CONTROL_R31_OFFSET[r7],r31
+ ld.w V850_CONTEXT_CONTROL_PSW_OFFSET[r7],r7
+ ldsr r7,psw
+ jmp [r31]
+
+
+/**
+ * This routine is generally used only to restart self in an
+ * efficient manner. It may simply be a label in _CPU_Context_switch.
+ *
+ * NOTE: May be unnecessary to reload some registers.
+ *
+ * v850 Specific Information:
+ *
+ * Move second parameter to first and jump to normal restore
+ */
+ .section .text
+ .global __CPU_Context_restore
+ .type __CPU_Context_restore, @function
+__CPU_Context_restore:
+ mov r6, r7 /* move to second parameter register */
+ br restore
+
+#if 0
+/**
+ * This routine provides the RTEMS interrupt management.
+ *
+ * v850 Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+void _ISR_Handler(void); /* C warning avoidance */
+void _ISR_Handler(void)
+{
+ /*
+ * This discussion ignores a lot of the ugly details in a real
+ * implementation such as saving enough registers/state to be
+ * able to do something real. Keep in mind that the goal is
+ * to invoke a user's ISR handler which is written in C and
+ * uses a certain set of registers.
+ *
+ * Also note that the exact order is to a large extent flexible.
+ * Hardware will dictate a sequence for a certain subset of
+ * _ISR_Handler while requirements for setting
+ */
+
+ /*
+ * At entry to "common" _ISR_Handler, the vector number must be
+ * available. On some CPUs the hardware puts either the vector
+ * number or the offset into the vector table for this ISR in a
+ * known place. If the hardware does not give us this information,
+ * then the assembly portion of RTEMS for this port will contain
+ * a set of distinct interrupt entry points which somehow place
+ * the vector number in a known place (which is safe if another
+ * interrupt nests this one) and branches to _ISR_Handler.
+ *
+ * save some or all context on stack
+ * may need to save some special interrupt information for exit
+ *
+ * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+ * if ( _ISR_Nest_level == 0 )
+ * switch to software interrupt stack
+ * #endif
+ *
+ * _ISR_Nest_level++;
+ *
+ * _Thread_Dispatch_disable_level++;
+ *
+ * (*_ISR_Vector_table[ vector ])( vector );
+ *
+ * _Thread_Dispatch_disable_level--;
+ *
+ * --_ISR_Nest_level;
+ *
+ * if ( _ISR_Nest_level )
+ * goto the label "exit interrupt (simple case)"
+ *
+ * if ( _Thread_Dispatch_disable_level )
+ * goto the label "exit interrupt (simple case)"
+ *
+ * if ( _Thread_Dispatch_necessary ) {
+ * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
+ * prepare to get out of interrupt
+ * return from interrupt (maybe to _ISR_Dispatch)
+ *
+ * LABEL "exit interrupt (simple case):
+ * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+ * if outermost interrupt
+ * restore stack
+ * #endif
+ * prepare to get out of interrupt
+ * return from interrupt
+ */
+}
+#endif
diff --git a/cpukit/score/cpu/v850/preinstall.am b/cpukit/score/cpu/v850/preinstall.am
new file mode 100644
index 0000000..c3d98e5
--- /dev/null
+++ b/cpukit/score/cpu/v850/preinstall.am
@@ -0,0 +1,45 @@
+## Automatically generated by ampolish3 - Do not edit
+
+if AMPOLISH3
+$(srcdir)/preinstall.am: Makefile.am
+ $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
+endif
+
+PREINSTALL_DIRS =
+DISTCLEANFILES = $(PREINSTALL_DIRS)
+
+all-am: $(PREINSTALL_FILES)
+
+PREINSTALL_FILES =
+CLEANFILES = $(PREINSTALL_FILES)
+
+$(PROJECT_INCLUDE)/rtems/$(dirstamp):
+ @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
+ @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
+
+$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
+ @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
+ @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
+
+$(PROJECT_INCLUDE)/rtems/score/v850.h: rtems/score/v850.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/v850.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/v850.h
+
+$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
+
+$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
+
diff --git a/cpukit/score/cpu/v850/rtems/asm.h b/cpukit/score/cpu/v850/rtems/asm.h
new file mode 100644
index 0000000..09e64da
--- /dev/null
+++ b/cpukit/score/cpu/v850/rtems/asm.h
@@ -0,0 +1,125 @@
+/**
+ * @file rtems/asm.h
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets. It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ */
+
+/*
+ * NOTE: The spacing in the use of these macros
+ * is critical to them working as advertised.
+ *
+ * COPYRIGHT:
+ *
+ * This file is based on similar code found in newlib available
+ * from ftp.cygnus.com. The file which was used had no copyright
+ * notice. This file is freely distributable as long as the source
+ * of the file is noted. This file is:
+ */
+
+/*
+ * COPYRIGHT (c) 1994-2012.
+ * On-Line Applications Research Corporation (OAR).
+ */
+
+#ifndef _RTEMS_ASM_H
+#define _RTEMS_ASM_H
+
+/*
+ * Indicate we are in an assembly file and get the basic CPU definitions.
+ */
+
+#ifndef ASM
+#define ASM
+#endif
+#include <rtems/score/cpuopts.h>
+#include <rtems/score/no_cpu.h>
+
+#ifndef __USER_LABEL_PREFIX__
+/**
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents. If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
+ *
+ * This symbol is prefixed to all C program symbols.
+ */
+#define __USER_LABEL_PREFIX__ _
+#endif
+
+#ifndef __REGISTER_PREFIX__
+/**
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents. If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
+ *
+ * This symbol is prefixed to all register names.
+ */
+#define __REGISTER_PREFIX__
+#endif
+
+#include <rtems/concat.h>
+
+/** Use the right prefix for global labels. */
+#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+/** Use the right prefix for registers. */
+#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+
+/*
+ * define macros for all of the registers on this CPU
+ *
+ * EXAMPLE: #define d0 REG (d0)
+ */
+
+/*
+ * Define macros to handle section beginning and ends.
+ */
+
+
+/** This macro is used to denote the beginning of a code declaration. */
+#define BEGIN_CODE_DCL .text
+/** This macro is used to denote the end of a code declaration. */
+#define END_CODE_DCL
+/** This macro is used to denote the beginning of a data declaration section. */
+#define BEGIN_DATA_DCL .data
+/** This macro is used to denote the end of a data declaration section. */
+#define END_DATA_DCL
+/** This macro is used to denote the beginning of a code section. */
+#define BEGIN_CODE .text
+/** This macro is used to denote the end of a code section. */
+#define END_CODE
+/** This macro is used to denote the beginning of a data section. */
+#define BEGIN_DATA
+/** This macro is used to denote the end of a data section. */
+#define END_DATA
+/** This macro is used to denote the beginning of the
+ * unitialized data section.
+ */
+#define BEGIN_BSS
+/** This macro is used to denote the end of the unitialized data section. */
+#define END_BSS
+/** This macro is used to denote the end of the assembly file. */
+#define END
+
+/**
+ * This macro is used to declare a public global symbol.
+ *
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
+ */
+#define PUBLIC(sym) .globl SYM (sym)
+
+/**
+ * This macro is used to prototype a public global symbol.
+ *
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
+ */
+#define EXTERN(sym) .globl SYM (sym)
+
+#endif
diff --git a/cpukit/score/cpu/v850/rtems/score/cpu.h b/cpukit/score/cpu/v850/rtems/score/cpu.h
new file mode 100644
index 0000000..591af00
--- /dev/null
+++ b/cpukit/score/cpu/v850/rtems/score/cpu.h
@@ -0,0 +1,1188 @@
+/**
+ * @file rtems/score/cpu.h
+ */
+
+/*
+ * This include file contains information pertaining to the v850
+ * processor.
+ */
+
+/*
+ * COPYRIGHT (c) 1989-2012.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef _RTEMS_SCORE_CPU_H
+#define _RTEMS_SCORE_CPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/types.h>
+#include <rtems/score/v850.h>
+
+/* conditional compilation parameters */
+
+/**
+ * Should the calls to @ref _Thread_Enable_dispatch be inlined?
+ *
+ * If TRUE, then they are inlined.
+ * If FALSE, then a subroutine call is made.
+ *
+ * This conditional is an example of the classic trade-off of size
+ * versus speed. Inlining the call (TRUE) typically increases the
+ * size of RTEMS while speeding up the enabling of dispatching.
+ *
+ * @note In general, the @ref _Thread_Dispatch_disable_level will
+ * only be 0 or 1 unless you are in an interrupt handler and that
+ * interrupt handler invokes the executive.] When not inlined
+ * something calls @ref _Thread_Enable_dispatch which in turns calls
+ * @ref _Thread_Dispatch. If the enable dispatch is inlined, then
+ * one subroutine call is avoided entirely.
+ *
+ * Port Specific Information:
+ *
+ * The v850 is a RISC CPU which typically has enough memory to justify
+ * the inlining of this method.
+ */
+#define CPU_INLINE_ENABLE_DISPATCH TRUE
+
+/**
+ * Should the body of the search loops in _Thread_queue_Enqueue_priority
+ * be unrolled one time? In unrolled each iteration of the loop examines
+ * two "nodes" on the chain being searched. Otherwise, only one node
+ * is examined per iteration.
+ *
+ * If TRUE, then the loops are unrolled.
+ * If FALSE, then the loops are not unrolled.
+ *
+ * The primary factor in making this decision is the cost of disabling
+ * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ * body of the loop. On some CPUs, the flash is more expensive than
+ * one iteration of the loop body. In this case, it might be desirable
+ * to unroll the loop. It is important to note that on some CPUs, this
+ * code is the longest interrupt disable period in RTEMS. So it is
+ * necessary to strike a balance when setting this parameter.
+ *
+ * Port Specific Information:
+ *
+ * The v850 is a RISC CPU which typically has enough memory to justify
+ * the unrolling of this method.
+ */
+#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
+
+/**
+ * Does RTEMS manage a dedicated interrupt stack in software?
+ *
+ * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
+ * If FALSE, nothing is done.
+ *
+ * If the CPU supports a dedicated interrupt stack in hardware,
+ * then it is generally the responsibility of the BSP to allocate it
+ * and set it up.
+ *
+ * If the CPU does not support a dedicated interrupt stack, then
+ * the porter has two options: (1) execute interrupts on the
+ * stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ * interrupt stack.
+ *
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ *
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
+ * possible that both are FALSE for a particular CPU. Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
+ *
+ * Port Specific Information:
+ *
+ * The v850 does not have support for a hardware interrupt stack.
+ */
+#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
+
+/**
+ * Does the CPU follow the simple vectored interrupt model?
+ *
+ * If TRUE, then RTEMS allocates the vector table it internally manages.
+ * If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
+ *
+ * Port Specific Information:
+ *
+ * This port uses the Progammable Interrupt Controller interrupt model.
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
+
+/**
+ * Does this CPU have hardware support for a dedicated interrupt stack?
+ *
+ * If TRUE, then it must be installed during initialization.
+ * If FALSE, then no installation is performed.
+ *
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ *
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
+ * possible that both are FALSE for a particular CPU. Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
+ *
+ * Port Specific Information:
+ *
+ * The v850 does not have support for a hardware interrupt stack.
+ */
+#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
+
+/**
+ * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ *
+ * If TRUE, then the memory is allocated during initialization.
+ * If FALSE, then the memory is allocated during initialization.
+ *
+ * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
+
+/**
+ * @def CPU_HARDWARE_FP
+ *
+ * Does the CPU have hardware floating point?
+ *
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ *
+ * If there is a FP coprocessor such as the i387 or mc68881, then
+ * the answer is TRUE.
+ *
+ * The macro name "V850_HAS_FPU" should be made CPU specific.
+ * It indicates whether or not this CPU model has FP support. For
+ * example, it would be possible to have an i386_nofp CPU model
+ * which set this to false to indicate that you have an i386 without
+ * an i387 and wish to leave floating point support out of RTEMS.
+ */
+
+/**
+ * @def CPU_SOFTWARE_FP
+ *
+ * Does the CPU have no hardware floating point and GCC provides a
+ * software floating point implementation which must be context
+ * switched?
+ *
+ * This feature conditional is used to indicate whether or not there
+ * is software implemented floating point that must be context
+ * switched. The determination of whether or not this applies
+ * is very tool specific and the state saved/restored is also
+ * compiler specific.
+ *
+ * Port Specific Information:
+ *
+ * Some v850 models do have IEEE hardware floating point support but
+ * they do not have any special registers to save or bit(s) which
+ * determine if the FPU is enabled. In short, there appears to be nothing
+ * related to the floating point operations which impact the RTEMS
+ * thread context switch. Thus from an RTEMS perspective, there is really
+ * no FPU to manage.
+ */
+#define CPU_HARDWARE_FP FALSE
+#define CPU_SOFTWARE_FP FALSE
+
+/**
+ * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ *
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ *
+ * So far, the only CPUs in which this option has been used are the
+ * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and
+ * gcc both implicitly used the floating point registers to perform
+ * integer multiplies. Similarly, the PowerPC port of gcc has been
+ * seen to allocate floating point local variables and touch the FPU
+ * even when the flow through a subroutine (like vfprintf()) might
+ * not use floating point formats.
+ *
+ * If a function which you would not think utilize the FP unit DOES,
+ * then one can not easily predict which tasks will use the FP hardware.
+ * In this case, this option should be TRUE.
+ *
+ * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ *
+ * Port Specific Information:
+ *
+ * This should be false until it has been demonstrated that gcc for the
+ * v850 generates FPU code when it is unexpected. But even this would
+ * not matter since there are no FP specific registers or bits which
+ * would be corrupted if an FP operation occurred in an integer only
+ * thread.
+ */
+#define CPU_ALL_TASKS_ARE_FP FALSE
+
+/**
+ * Should the IDLE task have a floating point context?
+ *
+ * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ * and it has a floating point context which is switched in and out.
+ * If FALSE, then the IDLE task does not have a floating point context.
+ *
+ * Setting this to TRUE negatively impacts the time required to preempt
+ * the IDLE task from an interrupt because the floating point context
+ * must be saved as part of the preemption.
+ *
+ * Port Specific Information:
+ *
+ * The IDLE thread should not be using the FPU. Leave this off.
+ */
+#define CPU_IDLE_TASK_IS_FP FALSE
+
+/**
+ * Should the saving of the floating point registers be deferred
+ * until a context switch is made to another different floating point
+ * task?
+ *
+ * If TRUE, then the floating point context will not be stored until
+ * necessary. It will remain in the floating point registers and not
+ * disturned until another floating point task is switched to.
+ *
+ * If FALSE, then the floating point context is saved when a floating
+ * point task is switched out and restored when the next floating point
+ * task is restored. The state of the floating point registers between
+ * those two operations is not specified.
+ *
+ * If the floating point context does NOT have to be saved as part of
+ * interrupt dispatching, then it should be safe to set this to TRUE.
+ *
+ * Setting this flag to TRUE results in using a different algorithm
+ * for deciding when to save and restore the floating point context.
+ * The deferred FP switch algorithm minimizes the number of times
+ * the FP context is saved and restored. The FP context is not saved
+ * until a context switch is made to another, different FP task.
+ * Thus in a system with only one FP task, the FP context will never
+ * be saved or restored.
+ *
+ * Port Specific Information:
+ *
+ * See earlier comments. There is no FPU state to manage.
+ */
+#define CPU_USE_DEFERRED_FP_SWITCH TRUE
+
+/**
+ * Does this port provide a CPU dependent IDLE task implementation?
+ *
+ * If TRUE, then the routine @ref _CPU_Thread_Idle_body
+ * must be provided and is the default IDLE thread body instead of
+ * @ref _CPU_Thread_Idle_body.
+ *
+ * If FALSE, then use the generic IDLE thread body if the BSP does
+ * not provide one.
+ *
+ * This is intended to allow for supporting processors which have
+ * a low power or idle mode. When the IDLE thread is executed, then
+ * the CPU can be powered down.
+ *
+ * The order of precedence for selecting the IDLE thread body is:
+ *
+ * -# BSP provided
+ * -# CPU dependent (if provided)
+ * -# generic (if no BSP and no CPU dependent)
+ *
+ * Port Specific Information:
+ *
+ * There does not appear to be a reason for the v850 port itself to provide
+ * a special idle task.
+ */
+#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
+
+/**
+ * Does the stack grow up (toward higher addresses) or down
+ * (toward lower addresses)?
+ *
+ * If TRUE, then the grows upward.
+ * If FALSE, then the grows toward smaller addresses.
+ *
+ * Port Specific Information:
+ *
+ * The v850 stack grows from high addresses to low addresses.
+ */
+#define CPU_STACK_GROWS_UP FALSE
+
+/**
+ * The following is the variable attribute used to force alignment
+ * of critical RTEMS structures. On some processors it may make
+ * sense to have these aligned on tighter boundaries than
+ * the minimum requirements of the compiler in order to have as
+ * much of the critical data area as possible in a cache line.
+ *
+ * The placement of this macro in the declaration of the variables
+ * is based on the syntactically requirements of the GNU C
+ * "__attribute__" extension. For example with GNU C, use
+ * the following to force a structures to a 32 byte boundary.
+ *
+ * __attribute__ ((aligned (32)))
+ *
+ * @note Currently only the Priority Bit Map table uses this feature.
+ * To benefit from using this, the data must be heavily
+ * used so it will stay in the cache and used frequently enough
+ * in the executive to justify turning this on.
+ *
+ * Port Specific Information:
+ *
+ * Until proven otherwise, use the compiler default.
+ */
+#define CPU_STRUCTURE_ALIGNMENT
+
+/**
+ * The v850 should use 64-bit timestamps and inline them.
+ */
+#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
+
+/**
+ * @defgroup CPUEndian Processor Dependent Endianness Support
+ *
+ * This group assists in issues related to processor endianness.
+ */
+
+/**
+ * @ingroup CPUEndian
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
+ *
+ * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
+ *
+ * @see CPU_LITTLE_ENDIAN
+ *
+ * Port Specific Information:
+ *
+ * The v850 is little endian.
+ */
+#define CPU_BIG_ENDIAN FALSE
+
+/**
+ * @ingroup CPUEndian
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
+ *
+ * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
+ *
+ * @see CPU_BIG_ENDIAN
+ *
+ * Port Specific Information:
+ *
+ * The v850 is little endian.
+ */
+#define CPU_LITTLE_ENDIAN TRUE
+
+/**
+ * @ingroup CPUInterrupt
+ * The following defines the number of bits actually used in the
+ * interrupt field of the task mode. How those bits map to the
+ * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
+ *
+ * Port Specific Information:
+ *
+ * The v850 only has a single bit in the CPU for interrupt disable/enable.
+ */
+#define CPU_MODES_INTERRUPT_MASK 0x00000001
+
+/**
+ * @defgroup CPUContext Processor Dependent Context Management
+ *
+ * From the highest level viewpoint, there are 2 types of context to save.
+ *
+ * -# Interrupt registers to save
+ * -# Task level registers to save
+ *
+ * Since RTEMS handles integer and floating point contexts separately, this
+ * means we have the following 3 context items:
+ *
+ * -# task level context stuff:: Context_Control
+ * -# floating point task stuff:: Context_Control_fp
+ * -# special interrupt level context :: CPU_Interrupt_frame
+ *
+ * On some processors, it is cost-effective to save only the callee
+ * preserved registers during a task context switch. This means
+ * that the ISR code needs to save those registers which do not
+ * persist across function calls. It is not mandatory to make this
+ * distinctions between the caller/callee saves registers for the
+ * purpose of minimizing context saved during task switch and on interrupts.
+ * If the cost of saving extra registers is minimal, simplicity is the
+ * choice. Save the same context on interrupt entry as for tasks in
+ * this case.
+ *
+ * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ * care should be used in designing the context area.
+ *
+ * On some CPUs with hardware floating point support, the Context_Control_fp
+ * structure will not be used or it simply consist of an array of a
+ * fixed number of bytes. This is done when the floating point context
+ * is dumped by a "FP save context" type instruction and the format
+ * is not really defined by the CPU. In this case, there is no need
+ * to figure out the exact format -- only the size. Of course, although
+ * this is enough information for RTEMS, it is probably not enough for
+ * a debugger such as gdb. But that is another problem.
+ *
+ * Port Specific Information:
+ *
+ * On the v850, this port saves special registers and those that are
+ * callee saved.
+ */
+
+/**
+ * @ingroup CPUContext Management
+ * This defines the minimal set of integer and processor state registers
+ * that must be saved during a voluntary context switch from one thread
+ * to another.
+ */
+typedef struct {
+ uint32_t r1;
+ /** This field is the stack pointer (e.g. r3). */
+ uint32_t r3_stack_pointer;
+ uint32_t r20;
+ uint32_t r21;
+ uint32_t r22;
+ uint32_t r23;
+ uint32_t r24;
+ uint32_t r25;
+ uint32_t r26;
+ uint32_t r27;
+ uint32_t r28;
+ uint32_t r29;
+ uint32_t r31;
+ uint32_t psw;
+} Context_Control;
+
+/**
+ * @ingroup CPUContext Management
+ *
+ * This macro returns the stack pointer associated with @a _context.
+ *
+ * @param[in] _context is the thread context area to access
+ *
+ * @return This method returns the stack pointer.
+ */
+#define _CPU_Context_Get_SP( _context ) \
+ (_context)->r3_stack_pointer
+
+/**
+ * @ingroup CPUContext Management
+ * This defines the complete set of floating point registers that must
+ * be saved during any context switch from one thread to another.
+ */
+typedef struct {
+ /** FPU registers are listed here */
+ double some_float_register;
+} Context_Control_fp;
+
+/**
+ * @ingroup CPUContext Management
+ * This defines the set of integer and processor state registers that must
+ * be saved during an interrupt. This set does not include any which are
+ * in @ref Context_Control.
+ */
+typedef struct {
+ /** This field is a hint that a port will have a number of integer
+ * registers that need to be saved when an interrupt occurs or
+ * when a context switch occurs at the end of an ISR.
+ */
+ uint32_t special_interrupt_register;
+} CPU_Interrupt_frame;
+
+/**
+ * @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ *
+ * On some CPUs, RTEMS supports a software managed interrupt stack.
+ * This stack is allocated by the Interrupt Manager and the switch
+ * is performed in @ref _ISR_Handler. These variables contain pointers
+ * to the lowest and highest addresses in the chunk of memory allocated
+ * for the interrupt stack. Since it is unknown whether the stack
+ * grows up or down (in general), this give the CPU dependent
+ * code the option of picking the version it wants to use.
+ *
+ * @note These two variables are required if the macro
+ * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+
+/**
+ * @ingroup CPUContext
+ * The size of the floating point context area. On some CPUs this
+ * will not be a "sizeof" because the format of the floating point
+ * area is not defined -- only the size is. This is usually on
+ * CPUs with a "floating point save context" instruction.
+ *
+ * Port Specific Information:
+ *
+ * The v850 does not need a floating point context but this needs to be
+ * defined so confdefs.h.
+ */
+/* #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) */
+#define CPU_CONTEXT_FP_SIZE 0
+
+/**
+ * Amount of extra stack (above minimum stack size) required by
+ * MPCI receive server thread. Remember that in a multiprocessor
+ * system this thread must exist and be able to process all directives.
+ *
+ * Port Specific Information:
+ *
+ * There is no reason to think the v850 needs extra MPCI receive
+ * server stack.
+ */
+#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
+
+/* XXX this should not be needed on PIC architectures */
+/* XXX evaluate removing it */
+#if 0
+/**
+ * @ingroup CPUInterrupt
+ * This defines the number of entries in the @ref _ISR_Vector_table managed
+ * by RTEMS.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
+#endif
+
+/**
+ * @ingroup CPUInterrupt
+ * This defines the highest interrupt vector number for this port.
+ */
+#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
+
+/**
+ * @ingroup CPUInterrupt
+ * This is defined if the port has a special way to report the ISR nesting
+ * level. Most ports maintain the variable @a _ISR_Nest_level.
+ */
+#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
+
+/**
+ * @ingroup CPUContext
+ * Should be large enough to run all RTEMS tests. This ensures
+ * that a "reasonable" small application should not have any problems.
+ *
+ * Port Specific Information:
+ *
+ * This should be very conservative on the v850.
+ */
+#define CPU_STACK_MINIMUM_SIZE (1024*4)
+
+/**
+ * CPU's worst alignment requirement for data types on a byte boundary. This
+ * alignment does not take into account the requirements for the stack.
+ *
+ * Port Specific Information:
+ *
+ * There is no apparent reason why this should be larger than 8.
+ */
+#define CPU_ALIGNMENT 8
+
+/**
+ * This number corresponds to the byte alignment requirement for the
+ * heap handler. This alignment requirement may be stricter than that
+ * for the data types alignment specified by @ref CPU_ALIGNMENT. It is
+ * common for the heap to follow the same alignment requirement as
+ * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for
+ * the heap, then this should be set to @ref CPU_ALIGNMENT.
+ *
+ * @note This does not have to be a power of 2 although it should be
+ * a multiple of 2 greater than or equal to 2. The requirement
+ * to be a multiple of 2 is because the heap uses the least
+ * significant field of the front and back flags to indicate
+ * that a block is in use or free. So you do not want any odd
+ * length blocks really putting length data in that bit.
+ *
+ * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
+ * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
+ * elements allocated from the heap meet all restrictions.
+ *
+ * Port Specific Information:
+ *
+ * There is no apparent reason why this should be larger than CPU_ALIGNMENT.
+ */
+#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
+
+/**
+ * This number corresponds to the byte alignment requirement for memory
+ * buffers allocated by the partition manager. This alignment requirement
+ * may be stricter than that for the data types alignment specified by
+ * @ref CPU_ALIGNMENT. It is common for the partition to follow the same
+ * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is
+ * strict enough for the partition, then this should be set to
+ * @ref CPU_ALIGNMENT.
+ *
+ * @note This does not have to be a power of 2. It does have to
+ * be greater or equal to than @ref CPU_ALIGNMENT.
+ *
+ * Port Specific Information:
+ *
+ * There is no apparent reason why this should be larger than CPU_ALIGNMENT.
+ */
+#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
+
+/**
+ * This number corresponds to the byte alignment requirement for the
+ * stack. This alignment requirement may be stricter than that for the
+ * data types alignment specified by @ref CPU_ALIGNMENT. If the
+ * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
+ * set to 0.
+ *
+ * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
+ *
+ * Port Specific Information:
+ *
+ * The v850 has enough RAM where alignment to 16 may be desirable depending
+ * on the cache properties. But this remains to be demonstrated.
+ */
+#define CPU_STACK_ALIGNMENT 4
+
+/*
+ * ISR handler macros
+ */
+
+/**
+ * @ingroup CPUInterrupt
+ * Disable all interrupts for an RTEMS critical section. The previous
+ * level is returned in @a _isr_cookie.
+ *
+ * @param[out] _isr_cookie will contain the previous level cookie
+ *
+ * Port Specific Information:
+ *
+ * On the v850, we need to save the PSW and use "di" to disable interrupts.
+ */
+#define _CPU_ISR_Disable( _isr_cookie ) \
+ do { \
+ unsigned int _psw; \
+ \
+ v850_get_psw( _psw ); \
+ __asm__ __volatile__( "di" ); \
+ _isr_cookie = _psw; \
+ } while (0)
+
+/**
+ * @ingroup CPUInterrupt
+ * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ * This indicates the end of an RTEMS critical section. The parameter
+ * @a _isr_cookie is not modified.
+ *
+ * @param[in] _isr_cookie contain the previous level cookie
+ *
+ * Port Specific Information:
+ *
+ * On the v850, we simply need to restore the PSW.
+ */
+#define _CPU_ISR_Enable( _isr_cookie ) \
+ do { \
+ unsigned int _psw = (_isr_cookie); \
+ \
+ v850_set_psw( _psw ); \
+ } while (0)
+
+/**
+ * @ingroup CPUInterrupt
+ * This temporarily restores the interrupt to @a _isr_cookie before immediately
+ * disabling them again. This is used to divide long RTEMS critical
+ * sections into two or more parts. The parameter @a _isr_cookie is not
+ * modified.
+ *
+ * @param[in] _isr_cookie contain the previous level cookie
+ *
+ * Port Specific Information:
+ *
+ * This saves at least one instruction over using enable/disable back to back.
+ */
+#define _CPU_ISR_Flash( _isr_cookie ) \
+ do { \
+ unsigned int _psw = (_isr_cookie); \
+ v850_set_psw( _psw ); \
+ __asm__ __volatile__( "di" ); \
+ } while (0)
+
+/**
+ * @ingroup CPUInterrupt
+ *
+ * This routine and @ref _CPU_ISR_Get_level
+ * Map the interrupt level in task mode onto the hardware that the CPU
+ * actually provides. Currently, interrupt levels which do not
+ * map onto the CPU in a generic fashion are undefined. Someday,
+ * it would be nice if these were "mapped" by the application
+ * via a callout. For example, m68k has 8 levels 0 - 7, levels
+ * 8 - 255 would be available for bsp/application specific meaning.
+ * This could be used to manage a programmable interrupt controller
+ * via the rtems_task_mode directive.
+ *
+ * Port Specific Information:
+ *
+ * On the v850, level 0 is enabled. Non-zero is disabled.
+ */
+#define _CPU_ISR_Set_level( new_level ) \
+ do { \
+ if ( new_level ) \
+ __asm__ __volatile__( "di" ); \
+ else \
+ __asm__ __volatile__( "ei" ); \
+ } while (0)
+
+/**
+ * @ingroup CPUInterrupt
+ * Return the current interrupt disable level for this task in
+ * the format used by the interrupt level portion of the task mode.
+ *
+ * @note This routine usually must be implemented as a subroutine.
+ *
+ * Port Specific Information:
+ *
+ * This method is implemented in C on the v850.
+ */
+uint32_t _CPU_ISR_Get_level( void );
+
+/* end of ISR handler macros */
+
+/* Context handler macros */
+
+/**
+ * @ingroup CPUContext
+ * Initialize the context to a state suitable for starting a
+ * task after a context restore operation. Generally, this
+ * involves:
+ *
+ * - setting a starting address
+ * - preparing the stack
+ * - preparing the stack and frame pointers
+ * - setting the proper interrupt level in the context
+ * - initializing the floating point context
+ *
+ * This routine generally does not set any unnecessary register
+ * in the context. The state of the "general data" registers is
+ * undefined at task start time.
+ *
+ * @param[in] _the_context is the context structure to be initialized
+ * @param[in] _stack_base is the lowest physical address of this task's stack
+ * @param[in] _size is the size of this task's stack
+ * @param[in] _isr is the interrupt disable level
+ * @param[in] _entry_point is the thread's entry point. This is
+ * always @a _Thread_Handler
+ * @param[in] _is_fp is TRUE if the thread is to be a floating
+ * point thread. This is typically only used on CPUs where the
+ * FPU may be easily disabled by software such as on the SPARC
+ * where the PSR contains an enable FPU bit.
+ *
+ * Port Specific Information:
+ *
+ * This method is implemented in C on the v850.
+ */
+void _CPU_Context_Initialize(
+ Context_Control *the_context,
+ uint32_t *stack_base,
+ uint32_t size,
+ uint32_t new_level,
+ void *entry_point,
+ bool is_fp
+);
+
+/**
+ * This routine is responsible for somehow restarting the currently
+ * executing task. If you are lucky, then all that is necessary
+ * is restoring the context. Otherwise, there will need to be
+ * a special assembly routine which does something special in this
+ * case. For many ports, simply adding a label to the restore path
+ * of @ref _CPU_Context_switch will work. On other ports, it may be
+ * possibly to load a few arguments and jump to the restore path. It will
+ * not work if restarting self conflicts with the stack frame
+ * assumptions of restoring a context.
+ *
+ * Port Specific Information:
+ *
+ * On the v850, we require a special entry point to restart a task.
+ */
+#define _CPU_Context_Restart_self( _the_context ) \
+ _CPU_Context_restore( (_the_context) );
+
+/* XXX this should be possible to remove */
+#if 0
+/**
+ * @ingroup CPUContext
+ * The purpose of this macro is to allow the initial pointer into
+ * a floating point context area (used to save the floating point
+ * context) to be at an arbitrary place in the floating point
+ * context area.
+ *
+ * This is necessary because some FP units are designed to have
+ * their context saved as a stack which grows into lower addresses.
+ * Other FP units can be saved by simply moving registers into offsets
+ * from the base of the context area. Finally some FP units provide
+ * a "dump context" instruction which could fill in from high to low
+ * or low to high based on the whim of the CPU designers.
+ *
+ * @param[in] _base is the lowest physical address of the floating point
+ * context area
+ * @param[in] _offset is the offset into the floating point area
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+#define _CPU_Context_Fp_start( _base, _offset ) \
+ ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
+#endif
+
+/* XXX this should be possible to remove */
+#if 0
+/**
+ * This routine initializes the FP context area passed to it to.
+ * There are a few standard ways in which to initialize the
+ * floating point context. The code included for this macro assumes
+ * that this is a CPU in which a "initial" FP context was saved into
+ * @a _CPU_Null_fp_context and it simply copies it to the destination
+ * context passed to it.
+ *
+ * Other floating point context save/restore models include:
+ * -# not doing anything, and
+ * -# putting a "null FP status word" in the correct place in the FP context.
+ *
+ * @param[in] _destination is the floating point context area
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+#define _CPU_Context_Initialize_fp( _destination ) \
+ { \
+ }
+#endif
+
+/* end of Context handler macros */
+
+/* Fatal Error manager macros */
+
+/**
+ * This routine copies _error into a known place -- typically a stack
+ * location or a register, optionally disables interrupts, and
+ * halts/stops the CPU.
+ *
+ * Port Specific Information:
+ *
+ * Move the error code into r10, disable interrupts and halt.
+ */
+#define _CPU_Fatal_halt( _error ) \
+ do { \
+ __asm__ __volatile__ ( "di" ); \
+ __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \
+ __asm__ __volatile__ ( "halt" ); \
+ } while (0)
+
+/* end of Fatal Error manager macros */
+
+/* Bitfield handler macros */
+
+/**
+ * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ *
+ * This set of routines are used to implement fast searches for
+ * the most important ready task.
+ */
+
+/**
+ * @ingroup CPUBitfield
+ * This definition is set to TRUE if the port uses the generic bitfield
+ * manipulation implementation.
+ */
+#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
+
+/**
+ * @ingroup CPUBitfield
+ * This definition is set to TRUE if the port uses the data tables provided
+ * by the generic bitfield manipulation implementation.
+ * This can occur when actually using the generic bitfield manipulation
+ * implementation or when implementing the same algorithm in assembly
+ * language for improved performance. It is unlikely that a port will use
+ * the data if it has a bitfield scan instruction.
+ *
+ * Port Specific Information:
+ *
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning. The empty
+ * stub routines are left as a place holder in case someone figures
+ * out how to do a v850 implementation better than the generic algorithm.
+ */
+#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
+
+/**
+ * @ingroup CPUBitfield
+ * This routine sets @a _output to the bit number of the first bit
+ * set in @a _value. @a _value is of CPU dependent type
+ * @a Priority_bit_map_Control. This type may be either 16 or 32 bits
+ * wide although only the 16 least significant bits will be used.
+ *
+ * There are a number of variables in using a "find first bit" type
+ * instruction.
+ *
+ * -# What happens when run on a value of zero?
+ * -# Bits may be numbered from MSB to LSB or vice-versa.
+ * -# The numbering may be zero or one based.
+ * -# The "find first bit" instruction may search from MSB or LSB.
+ *
+ * RTEMS guarantees that (1) will never happen so it is not a concern.
+ * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
+ * @ref _CPU_Priority_bits_index. These three form a set of routines
+ * which must logically operate together. Bits in the _value are
+ * set and cleared based on masks built by @ref _CPU_Priority_Mask.
+ * The basic major and minor values calculated by @ref _Priority_Major
+ * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
+ * to properly range between the values returned by the "find first bit"
+ * instruction. This makes it possible for @ref _Priority_Get_highest to
+ * calculate the major and directly index into the minor table.
+ * This mapping is necessary to ensure that 0 (a high priority major/minor)
+ * is the first bit found.
+ *
+ * This entire "find first bit" and mapping process depends heavily
+ * on the manner in which a priority is broken into a major and minor
+ * components with the major being the 4 MSB of a priority and minor
+ * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
+ * to the lowest priority.
+ *
+ * If your CPU does not have a "find first bit" instruction, then
+ * there are ways to make do without it. Here are a handful of ways
+ * to implement this in software:
+ *
+ at verbatim
+ - a series of 16 bit test instructions
+ - a "binary search using if's"
+ - _number = 0
+ if _value > 0x00ff
+ _value >>=8
+ _number = 8;
+
+ if _value > 0x0000f
+ _value >=8
+ _number += 4
+
+ _number += bit_set_table[ _value ]
+ at endverbatim
+
+ * where bit_set_table[ 16 ] has values which indicate the first
+ * bit set
+ *
+ * @param[in] _value is the value to be scanned
+ * @param[in] _output is the first bit set
+ *
+ * Port Specific Information:
+ *
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning.
+ */
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
+ { \
+ (_output) = 0; /* do something to prevent warnings */ \
+ }
+#endif
+
+/* end of Bitfield handler macros */
+
+/**
+ * This routine builds the mask which corresponds to the bit fields
+ * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion
+ * for that routine.
+ *
+ * Port Specific Information:
+ *
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning.
+ */
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+#define _CPU_Priority_Mask( _bit_number ) \
+ ( 1 << (_bit_number) )
+
+#endif
+
+/**
+ * @ingroup CPUBitfield
+ * This routine translates the bit numbers returned by
+ * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
+ * a major or minor component of a priority. See the discussion
+ * for that routine.
+ *
+ * @param[in] _priority is the major or minor number to translate
+ *
+ * Port Specific Information:
+ *
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning.
+ */
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+#define _CPU_Priority_bits_index( _priority ) \
+ (_priority)
+
+#endif
+
+/* end of Priority handler macros */
+
+/* functions */
+
+/**
+ * This routine performs CPU dependent initialization.
+ *
+ * Port Specific Information:
+ *
+ * This is implemented in C.
+ */
+void _CPU_Initialize(void);
+
+/**
+ * @ingroup CPUContext
+ * This routine switches from the run context to the heir context.
+ *
+ * @param[in] run points to the context of the currently executing task
+ * @param[in] heir points to the context of the heir task
+ *
+ * Port Specific Information:
+ *
+ * This is implemented in assembly on the v850.
+ */
+void _CPU_Context_switch(
+ Context_Control *run,
+ Context_Control *heir
+);
+
+/**
+ * @ingroup CPUContext
+ * This routine is generally used only to restart self in an
+ * efficient manner. It may simply be a label in @ref _CPU_Context_switch.
+ *
+ * @param[in] new_context points to the context to be restored.
+ *
+ * @note May be unnecessary to reload some registers.
+ *
+ * Port Specific Information:
+ *
+ * This is implemented in assembly on the v850.
+ */
+void _CPU_Context_restore(
+ Context_Control *new_context
+) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
+
+/* XXX this should be possible to remove */
+#if 0
+/**
+ * @ingroup CPUContext
+ * This routine saves the floating point context passed to it.
+ *
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area
+ *
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_restore_fp to restore this context.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+void _CPU_Context_save_fp(
+ Context_Control_fp **fp_context_ptr
+);
+#endif
+
+/* XXX this should be possible to remove */
+#if 0
+/**
+ * @ingroup CPUContext
+ * This routine restores the floating point context passed to it.
+ *
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area to restore
+ *
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_save_fp to save this context.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+void _CPU_Context_restore_fp(
+ Context_Control_fp **fp_context_ptr
+);
+#endif
+
+/**
+ * @ingroup CPUEndian
+ * The following routine swaps the endian format of an unsigned int.
+ * It must be static because it is referenced indirectly.
+ *
+ * This version will work on any processor, but if there is a better
+ * way for your CPU PLEASE use it. The most common way to do this is to:
+ *
+ * swap least significant two bytes with 16-bit rotate
+ * swap upper and lower 16-bits
+ * swap most significant two bytes with 16-bit rotate
+ *
+ * Some CPUs have special instructions which swap a 32-bit quantity in
+ * a single instruction (e.g. i486). It is probably best to avoid
+ * an "endian swapping control bit" in the CPU. One good reason is
+ * that interrupts would probably have to be disabled to ensure that
+ * an interrupt does not try to access the same "chunk" with the wrong
+ * endian. Another good reason is that on some CPUs, the endian bit
+ * endianness for ALL fetches -- both code and data -- so the code
+ * will be fetched incorrectly.
+ *
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
+ *
+ * Port Specific Information:
+ *
+ * The v850 has a single instruction to swap endianness on a 32 bit quantity.
+ */
+static inline uint32_t CPU_swap_u32(
+ uint32_t value
+)
+{
+ unsigned int v, swapped;
+
+ v = value;
+ __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) );
+ return swapped;
+}
+
+/**
+ * @ingroup CPUEndian
+ * This routine swaps a 16 bir quantity.
+ *
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
+ *
+ * Port Specific Information:
+ *
+ * The v850 has a single instruction to swap endianness on a 16 bit quantity.
+ */
+static inline uint16_t CPU_swap_u16( uint16_t value )
+{
+ unsigned int v, swapped;
+
+ v = value;
+ __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) );
+ return swapped;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cpukit/score/cpu/v850/rtems/score/cpu_asm.h b/cpukit/score/cpu/v850/rtems/score/cpu_asm.h
new file mode 100644
index 0000000..49a44a9
--- /dev/null
+++ b/cpukit/score/cpu/v850/rtems/score/cpu_asm.h
@@ -0,0 +1,71 @@
+/**
+ * @file rtems/score/cpu_asm.h
+ */
+
+/*
+ * Very loose template for an include file for the cpu_asm.? file
+ * if it is implemented as a ".S" file (preprocessed by cpp) instead
+ * of a ".s" file (preprocessed by gm4 or gasp).
+ */
+
+/*
+ * COPYRIGHT (c) 1989-2012.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef _RTEMS_SCORE_CPU_ASM_H
+#define _RTEMS_SCORE_CPU_ASM_H
+
+/* pull in the generated offsets */
+
+#include <rtems/score/offsets.h>
+
+/*
+ * Hardware General Registers
+ */
+
+/* put something here */
+
+/*
+ * Hardware Floating Point Registers
+ */
+
+/* put something here */
+
+/*
+ * Hardware Control Registers
+ */
+
+/* put something here */
+
+/*
+ * Calling Convention
+ */
+
+/* put something here */
+
+/*
+ * Temporary registers
+ */
+
+/* put something here */
+
+/*
+ * Floating Point Registers - SW Conventions
+ */
+
+/* put something here */
+
+/*
+ * Temporary floating point registers
+ */
+
+/* put something here */
+
+#endif
+
+/* end of file */
diff --git a/cpukit/score/cpu/v850/rtems/score/types.h b/cpukit/score/cpu/v850/rtems/score/types.h
new file mode 100644
index 0000000..32ff881
--- /dev/null
+++ b/cpukit/score/cpu/v850/rtems/score/types.h
@@ -0,0 +1,41 @@
+/**
+ * @file rtems/score/types.h
+ */
+
+/*
+ * This include file contains type definitions pertaining to the
+ * v850 processor family.
+ *
+ * COPYRIGHT (c) 1989-2011.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef _RTEMS_SCORE_TYPES_H
+#define _RTEMS_SCORE_TYPES_H
+
+#include <rtems/score/basedefs.h>
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This section defines the basic types for this processor.
+ */
+
+/** This defines the type for a priority bit map entry. */
+typedef uint16_t Priority_bit_map_Control;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !ASM */
+
+#endif
diff --git a/cpukit/score/cpu/v850/rtems/score/v850.h b/cpukit/score/cpu/v850/rtems/score/v850.h
new file mode 100644
index 0000000..b76ddbc
--- /dev/null
+++ b/cpukit/score/cpu/v850/rtems/score/v850.h
@@ -0,0 +1,126 @@
+/*
+ * This file sets up basic CPU dependency settings based on
+ * compiler settings. For example, it can determine if
+ * floating point is available. This particular implementation
+ * is specified to the Renesas v850 port.
+ */
+
+/*
+ * COPYRIGHT (c) 1989-2012.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef _RTEMS_SCORE_V850_H
+#define _RTEMS_SCORE_V850_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This file contains the information required to build
+ * RTEMS for a particular member of the NO CPU family.
+ * It does this by setting variables to indicate which
+ * implementation dependent features are present in a particular
+ * member of the family.
+ *
+ * This is a good place to list all the known CPU models
+ * that this port supports and which RTEMS CPU model they correspond
+ * to.
+ */
+
+#if defined(rtems_multilib)
+/*
+ * Figure out all CPU Model Feature Flags based upon compiler
+ * predefines.
+ */
+#define CPU_MODEL_NAME "rtems_multilib"
+#define V850_HAS_FPU 0
+
+#elif defined(__v850e2v3__)
+#define CPU_MODEL_NAME "v850e2v3"
+#define V850_HAS_FPU 1
+
+#elif defined(__v850e2__)
+#define CPU_MODEL_NAME "v850e2"
+#define V850_HAS_FPU 0
+
+#elif defined(__v850es__)
+#define CPU_MODEL_NAME "v850es"
+#define V850_HAS_FPU 0
+
+#elif defined(__v850e1__)
+#define CPU_MODEL_NAME "v850e1"
+#define V850_HAS_FPU 0
+
+#elif defined(__v850e__)
+#define CPU_MODEL_NAME "v850e"
+#define V850_HAS_FPU 0
+
+#else
+#define CPU_MODEL_NAME "v850"
+#define V850_HAS_FPU 0
+
+#endif
+
+/*
+ * Define the name of the CPU family.
+ */
+#define CPU_NAME "v850 CPU"
+
+/*
+ * Method to set the Program Status Word (PSW)
+ */
+#define v850_set_psw( _psw ) \
+ __asm__ __volatile__( "ldsr %0, psw" : : "r" (_psw) )
+
+/*
+ * Method to obtain the Program Status Word (PSW)
+ */
+#define v850_get_psw( _psw ) \
+ __asm__ __volatile__( "stsr psw, %0" : "=&r" (_psw) )
+
+/*
+ * Masks and bits in the Program Status Word (PSW)
+ */
+#define V850_PSW_ZERO_MASK 0x01
+#define V850_PSW_IS_ZERO 0x01
+#define V850_PSW_IS_NOT 0x00
+
+#define V850_PSW_SIGN_MASK 0x02
+#define V850_PSW_SIGN_IS_NEGATIVE 0x02
+#define V850_PSW_SIGN_IS_ZERO_OR_POSITIVE 0x00
+
+#define V850_PSW_OVERFLOW_MASK 0x02
+#define V850_PSW_OVERFLOW_OCCURRED 0x02
+#define V850_PSW_OVERFLOW_DID_NOT_OCCUR 0x00
+
+#define V850_PSW_CARRY_OR_BORROW_MASK 0x04
+#define V850_PSW_CARRY_OR_BORROW_OCCURRED 0x04
+#define V850_PSW_CARRY_OR_BORROW_DID_NOT_OCCUR 0x00
+
+#define V850_PSW_SATURATION_MASK 0x10
+#define V850_PSW_SATURATION_OCCURRED 0x10
+#define V850_PSW_SATURATION_DID_NOT_OCCUR 0x00
+
+#define V850_PSW_INTERRUPT_DISABLE_MASK 0x20
+#define V850_PSW_INTERRUPT_DISABLE 0x20
+#define V850_PSW_INTERRUPT_ENABLE 0x00
+
+#define V850_PSW_EXCEPTION_IN_PROCESS_MASK 0x40
+#define V850_PSW_EXCEPTION_IN_PROCESS 0x40
+#define V850_PSW_EXCEPTION_NOT_IN_PROCESS 0x00
+
+#define V850_PSW_NMI_IN_PROCESS_MASK 0x80
+#define V850_PSW_NMI_IN_PROCESS 0x80
+#define V850_PSW_NMI_NOT_IN_PROCESS 0x00
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTEMS_SCORE_V850_H */
diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am
index 970ea7a..8d117cf 100644
--- a/doc/cpu_supplement/Makefile.am
+++ b/doc/cpu_supplement/Makefile.am
@@ -1,5 +1,5 @@
#
-# COPYRIGHT (c) 1988-2002.
+# COPYRIGHT (c) 1988-2012.
# On-Line Applications Research Corporation (OAR).
# All rights reserved.
@@ -11,7 +11,7 @@ include $(top_srcdir)/main.am
REPLACE2 = $(PERL) $(top_srcdir)/tools/word-replace2
GENERATED_FILES = general.texi arm.texi avr.texi bfin.texi i386.texi lm32.texi \
- m68k.texi mips.texi powerpc.texi sh.texi sparc.texi sparc64.texi
+ m68k.texi mips.texi powerpc.texi sh.texi sparc.texi sparc64.texi v850.texi
COMMON_FILES += $(top_srcdir)/common/cpright.texi
@@ -84,6 +84,11 @@ sparc64.texi: sparc64.t
-u "Top" \
-n "" < $< > $@
+v850.texi: v850.t
+ $(BMENU2) -p "" \
+ -u "Top" \
+ -n "" < $< > $@
+
CLEANFILES += cpu_supplement.info
CLEANFILES += cpu_supplement.info-1
CLEANFILES += cpu_supplement.info-2
diff --git a/doc/cpu_supplement/v850.t b/doc/cpu_supplement/v850.t
new file mode 100644
index 0000000..072e10e
--- /dev/null
+++ b/doc/cpu_supplement/v850.t
@@ -0,0 +1,104 @@
+ at c
+ at c COPYRIGHT (c) 1988-2002.
+ at c On-Line Applications Research Corporation (OAR).
+ at c All rights reserved.
+
+ at ifinfo
+ at end ifinfo
+ at chapter V850 Specific Information
+
+This chapter discusses the
+ at uref{http://en.wikipedia.org/wiki/V850,V850 architecture}
+dependencies in this port of RTEMS. The V850 was originally manufactured
+by NEC but is now part of the Renesas Electronics product line.
+
+ at subheading Architecture Documents
+
+For information on the V850 architecture refer to the
+ at uref{http://am.renesas.com/products/mpumcu/v850/index.jsp,Renesas v850 product page}.
+
+ at section CPU Model Dependent Features
+
+This section presents the set of features which vary across V850 implementations and are of importance to RTEMS. The set of CPU model feature macros are defined in the file @file{cpukit/score/cpu/v850/rtems/score/v850.h} based upon the particular CPU
+model flags specified on the compilation command line.
+
+ at subsection CPU Model Name
+
+The macro @code{CPU_MODEL_NAME} is a string which designates
+the architectural level of this CPU model. See in
+ at file{cpukit/score/cpu/v850/rtems/score/v850.h} for the values.
+
+ at subsection Count Leading Zeroes Instruction
+
+The V850v5 and later has the count leading zeroes @code{clz} instruction which
+could be used to speed up the find first bit operation. The use of this
+instruction should significantly speed up the scheduling associated with a
+thread blocking. This is currently not used.
+
+ at subsection Floating Point Unit
+
+A floating point unit is currently not supported.
+
+ at section Calling Conventions
+
+Please refer to the
+ at uref{http://www.filibeto.org/unix/tru64/lib/ossc/doc/cygnus_doc-99r1/html/6_embed/embV850.html,
+Procedure Call Standard for the V850 Architecture} or the GCC source
+code for detailed information on the calling conventions.
+
+ at subsection Register Usage
+
+Fixed registers are never available for register allocation in the
+compiler. By default the following registers are fixed in GCC:
+
+ at itemize @bullet
+ at item r0 (zero)
+ at item r3 (sp)
+ at item r4 (gp)
+ at item r30 (ep)
+ at end itemize
+
+ at c r1 is mentioned as special purpose but I do not see a purpose
+
+Caller saved registers can be used by the compiler to hold values that
+do not live across function calls. The caller saved registers are r2,
+r5 through r19, and r31.
+
+Callee saved registers retain their value across function calls. The
+callee saved registers are r20 through r29.
+
+r6 through r9 are parameter registers while r10 and r11 are function return registers. r31 is the return pointer.
+
+r29 is used as the frame pointer in some functions.
+
+ at section Memory Model
+
+A flat 32-bit memory model is supported.
+
+ at section Interrupt Processing
+
+The V850 architecture has ...
+
+ at subsection Interrupt Levels
+
+The RTEMS interrupt level mapping scheme for the V850 is very simple. If
+the requested interrupt level is 1, then interrupts are disabled in the
+PSW register using the @code{di} instruction. If the requested interrupt
+level is 0, then interrupts are enabled in the PSW register using the
+ at code{ei} instruction or restoring the previous value of the PSW register.
+
+ at subsection Interrupt Stack
+
+The board support package must initialize the interrupt stack. The memory for
+the stacks is usually reserved in the linker script.
+
+ at section Default Fatal Error Processing
+
+The default fatal error handler for this architecture performs the
+following actions:
+
+ at itemize @bullet
+ at item disables operating system supported interrupts (IRQ),
+ at item places the error code in @code{r10}, and
+ at item executes a halt processor instruction.
+ at end itemize
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