[rtems commit] bsp/lpc24xx: New BSP variant
Joel Sherrill
joel at rtems.org
Thu Mar 29 14:14:31 UTC 2012
Module: rtems
Branch: master
Commit: bfb92cd5e20f276360faf505495ba26b0abbfdcb
Changeset: http://git.rtems.org/rtems/commit/?id=bfb92cd5e20f276360faf505495ba26b0abbfdcb
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Wed Mar 14 16:45:26 2012 +0100
bsp/lpc24xx: New BSP variant
---
c/src/lib/libbsp/arm/lpc24xx/Makefile.am | 1 +
c/src/lib/libbsp/arm/lpc24xx/configure.ac | 17 ++++--
.../arm/lpc24xx/make/custom/lpc24xx_plx800_ram.cfg | 5 ++
.../lpc24xx/make/custom/lpc24xx_plx800_rom_int.cfg | 2 -
.../lpc24xx/startup/linkcmds.lpc24xx_plx800_ram | 31 ++++++++++++
.../startup/linkcmds.lpc24xx_plx800_rom_int | 7 ++-
.../arm/lpc24xx/startup/start-config-emc-dynamic.c | 51 ++++++++++++++++++--
.../arm/lpc24xx/startup/start-config-emc-static.c | 34 ++++++++++++-
.../arm/lpc24xx/startup/start-config-pinsel.c | 20 +-------
9 files changed, 134 insertions(+), 34 deletions(-)
diff --git a/c/src/lib/libbsp/arm/lpc24xx/Makefile.am b/c/src/lib/libbsp/arm/lpc24xx/Makefile.am
index 1abe3b2..e64fd56 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/Makefile.am
+++ b/c/src/lib/libbsp/arm/lpc24xx/Makefile.am
@@ -74,6 +74,7 @@ EXTRA_DIST += startup/linkcmds.lpc24xx_ea
EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_ram
EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_ext
EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_int
+EXTRA_DIST += startup/linkcmds.lpc24xx_plx800_ram
EXTRA_DIST += startup/linkcmds.lpc24xx_plx800_rom_int
###############################################################################
diff --git a/c/src/lib/libbsp/arm/lpc24xx/configure.ac b/c/src/lib/libbsp/arm/lpc24xx/configure.ac
index 9584473..e2d23bc 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/configure.ac
+++ b/c/src/lib/libbsp/arm/lpc24xx/configure.ac
@@ -36,7 +36,7 @@ RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc17*],[120000000U])
#RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc17*],[96000000U])
#RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc17*],[48000000U])
RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc23*],[58982400U])
-RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc24xx_plx800*],[51612800U])
+RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc24xx_plx800_*],[51612800U])
RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[*],[72000000U])
RTEMS_BSPOPTS_HELP([LPC24XX_CCLK],[CPU clock in Hz])
@@ -58,16 +58,20 @@ RTEMS_BSPOPTS_HELP([LPC24XX_ETHERNET_RMII],[enable RMII for Ethernet])
RTEMS_BSPOPTS_SET([LPC24XX_EMC_MT48LC4M16A2],[lpc24xx_ncs_rom_*],[1])
RTEMS_BSPOPTS_HELP([LPC24XX_EMC_MT48LC4M16A2],[enable Micron MT48LC4M16A2 configuration for EMC])
-RTEMS_BSPOPTS_SET([LPC24XX_EMC_W9825G2JB75I],[lpc24xx_plx800_rom_*],[1])
RTEMS_BSPOPTS_HELP([LPC24XX_EMC_W9825G2JB75I],[enable Winbond W9825G2JB75I configuration for EMC])
+RTEMS_BSPOPTS_SET([LPC24XX_EMC_IS42S32800D7],[lpc24xx_plx800_rom_*],[1])
+RTEMS_BSPOPTS_HELP([LPC24XX_EMC_IS42S32800D7],[enable ISSI IS42S32800D7 configuration for EMC])
+
RTEMS_BSPOPTS_SET([LPC24XX_EMC_IS42S32800B],[lpc17xx_ea_rom_*],[1])
RTEMS_BSPOPTS_HELP([LPC24XX_EMC_IS42S32800B],[enable ISSI IS42S32800B configuration for EMC])
-RTEMS_BSPOPTS_SET([LPC24XX_EMC_NUMONYX_M29W160E],[lpc24xx_ncs_rom_*],[1])
-RTEMS_BSPOPTS_HELP([LPC24XX_EMC_NUMONYX_M29W160E],[enable Numonyx M29W160E configuration for EMC])
+RTEMS_BSPOPTS_SET([LPC24XX_EMC_M29W160E],[lpc24xx_ncs_rom_*],[1])
+RTEMS_BSPOPTS_HELP([LPC24XX_EMC_M29W160E],[enable M29W160E configuration for EMC])
+
+RTEMS_BSPOPTS_SET([LPC24XX_EMC_M29W320E70],[lpc24xx_plx800_rom_*],[1])
+RTEMS_BSPOPTS_HELP([LPC24XX_EMC_M29W320E70],[enable M29W320E70 configuration for EMC])
-RTEMS_BSPOPTS_SET([LPC24XX_EMC_SST39VF3201],[lpc24xx_plx800_rom_*],[1])
RTEMS_BSPOPTS_HELP([LPC24XX_EMC_SST39VF3201],[enable SST39VF3201 configuration for EMC])
RTEMS_BSPOPTS_SET([LPC24XX_EMC_TEST],[*],[])
@@ -80,11 +84,12 @@ RTEMS_BSPOPTS_HELP([LPC24XX_SPECIAL_TASK_STACKS_SUPPORT],[enable special task st
RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_CONSOLE],[*],[0])
RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_CONSOLE],[configuration for console (UART 0)])
-RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_UART_1],[*],[])
+RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_UART_1],[lpc24xx_plx800_*],[0])
RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_UART_1],[configuration for UART 1])
RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_UART_2],[lpc23*],[0])
RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_UART_2],[lpc24xx_ncs_*],[0])
+RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_UART_2],[lpc24xx_plx800_*],[0])
RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_UART_2],[configuration for UART 2])
RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_UART_3],[lpc23*],[0])
diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc24xx_plx800_ram.cfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc24xx_plx800_ram.cfg
new file mode 100644
index 0000000..6e25ad5
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc24xx_plx800_ram.cfg
@@ -0,0 +1,5 @@
+#
+# Config file for LPC24XX (PLX800).
+#
+
+include $(RTEMS_ROOT)/make/custom/lpc24xx.inc
diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc24xx_plx800_rom_int.cfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc24xx_plx800_rom_int.cfg
index 7e87334..6e25ad5 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc24xx_plx800_rom_int.cfg
+++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc24xx_plx800_rom_int.cfg
@@ -1,7 +1,5 @@
#
# Config file for LPC24XX (PLX800).
#
-# $Id$
-#
include $(RTEMS_ROOT)/make/custom/lpc24xx.inc
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_plx800_ram b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_plx800_ram
new file mode 100644
index 0000000..6198b58
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_plx800_ram
@@ -0,0 +1,31 @@
+/**
+ * @file
+ *
+ * @brief Memory map for PLX800 (LPC2478).
+ */
+
+MEMORY {
+ RAM_INT : ORIGIN = 0x40000000, LENGTH = 64k
+ RAM_EXT : ORIGIN = 0xa0000000, LENGTH = 32M
+ ROM_INT : ORIGIN = 0x00000000, LENGTH = 512k - 8k
+ ROM_EXT : ORIGIN = 0x80000000, LENGTH = 4M
+ NIRVANA : ORIGIN = 0, LENGTH = 0
+}
+
+REGION_ALIAS ("REGION_START", RAM_EXT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+
+INCLUDE linkcmds.armv4
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_plx800_rom_int b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_plx800_rom_int
index 66532bd..f49b884 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_plx800_rom_int
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_plx800_rom_int
@@ -5,9 +5,10 @@
*/
MEMORY {
- RAM_INT (AIW) : ORIGIN = 0x40000000, LENGTH = 64k
- RAM_EXT (AIW) : ORIGIN = 0xa0000000, LENGTH = 8M
- ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 512k - 8k
+ RAM_INT : ORIGIN = 0x40000000, LENGTH = 64k
+ RAM_EXT : ORIGIN = 0xa0000000, LENGTH = 32M
+ ROM_INT : ORIGIN = 0x00000000, LENGTH = 512k - 8k
+ ROM_EXT : ORIGIN = 0x80000000, LENGTH = 4M
NIRVANA : ORIGIN = 0, LENGTH = 0
}
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c b/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c
index 6a062c9..219aa3e 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c
@@ -69,6 +69,48 @@ BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
/* Load mode register to active or refresh command period 2 tCK */
.tmrd = 1
}
+#elif defined(LPC24XX_EMC_IS42S32800D7)
+ /* Dynamic Memory 0: ISSI IS42S32800D7 at 51612800Hz (tCK = 19.4ns) */
+ {
+ /* (n * 16) clock cycles -> 15.5us <= 15.6 us */
+ .refresh = 50,
+
+ /* Use command delayed strategy */
+ .readconfig = 1,
+
+ /* (n + 1) clock cycles -> 38.8ns >= 20ns */
+ .trp = 1,
+
+ /* (n + 1) clock cycles -> 58.1ns >= 45ns */
+ .tras = 2,
+
+ /* (n + 1) clock cycles -> 77.5ns >= 70ns (tXSR) */
+ .tsrex = 3,
+
+ /* (n + 1) clock cycles -> 38.8ns >= 20ns (tRCD) */
+ .tapr = 1,
+
+ /* n clock cycles -> 38.8ns >= 35ns */
+ .tdal = 2,
+
+ /* (n + 1) clock cycles = 19.4ns >= 14ns (tDPL) */
+ .twr = 0,
+
+ /* (n + 1) clock cycles = 77.5ns >= 67.5ns */
+ .trc = 3,
+
+ /* (n + 1) clock cycles = 77.5ns >= 67.5ns (tRC) */
+ .trfc = 3,
+
+ /* (n + 1) clock cycles = 77.5ns >= 70ns */
+ .txsr = 3,
+
+ /* (n + 1) clock cycles = 19.4ns >= 14ns */
+ .trrd = 0,
+
+ /* (n + 1) clock cycles = 19.4ns >= 14ns */
+ .tmrd = 0
+ }
#elif defined(LPC24XX_EMC_W9825G2JB75I)
/* Dynamic Memory 0: Winbond W9825G2JB75I at 51612800Hz (tCK = 19.4ns) */
{
@@ -211,18 +253,19 @@ BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
.rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
.mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
}
-#elif defined(LPC24XX_EMC_W9825G2JB75I)
+#elif defined(LPC24XX_EMC_W9825G2JB75I) \
+ || defined(LPC24XX_EMC_IS42S32800D7)
{
.chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
/* 32-bit data bus, 4 banks, 12 row lines, 9 column lines, RBC */
- .config = 0x4280,
+ .config = 0x4480,
/* RAS based on tRCD = 20ns */
.rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
- /* CAS 2, burst length 8, */
- .mode = 0xa0000000 | (0x23 << (2 + 2 + 9))
+ /* CAS 2, burst length 4 */
+ .mode = 0xa0000000 | (0x22 << (2 + 2 + 9))
}
#elif defined(LPC24XX_EMC_K4S561632E)
{
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-static.c b/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-static.c
index c0c5410..b4d4566 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-static.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-static.c
@@ -27,7 +27,7 @@
BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
lpc24xx_start_config_emc_static_chip [] = {
-#if defined(LPC24XX_EMC_NUMONYX_M29W160E)
+#if defined(LPC24XX_EMC_M29W160E)
/*
* Static Memory 1: Numonyx M29W160EB
*
@@ -66,8 +66,38 @@ BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
.waitrun = 0xf
}
}
+#elif defined(LPC24XX_EMC_M29W320E70)
+ /* Static Memory 0: M29W320E70 at 51612800Hz (tCK = 19.4ns) */
+ {
+ .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0,
+ .config = {
+ /*
+ * 16 bit, page mode disabled, active LOW chip select, extended wait
+ * disabled, writes not protected, byte lane state LOW/LOW.
+ */
+ .config = 0x81,
+
+ /* (n + 1) clock cycles -> 38.8ns >= 30ns (tWHWL) */
+ .waitwen = 1,
+
+ /* (n + 1) clock cycles -> 19.4ns >= 0ns */
+ .waitoen = 0,
+
+ /* (n + 1) clock cycles -> 77.5ns >= 70ns (tAVQV, tELQV) */
+ .waitrd = 3,
+
+ /* (n + 1) clock cycles -> 77.5ns >= 70ns (tAVQV, tELQV) */
+ .waitpage = 3,
+
+ /* (n + 2) clock cycles -> 58.1ns >= 45ns (tWLWH) */
+ .waitwr = 1,
+
+ /* (n + 1) clock cycles -> 38.8ns >= 25ns (tEHQZ) */
+ .waitrun = 1
+ }
+ }
#elif defined(LPC24XX_EMC_SST39VF3201)
- /* Static Memory 1: SST SST39VF3201 at 51612800Hz (tCK = 19.4ns) */
+ /* Static Memory 0: SST39VF3201 at 51612800Hz (tCK = 19.4ns) */
{
.chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0,
.config = {
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c b/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c
index 43f12f6..1a93073 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c
@@ -25,7 +25,7 @@
BSP_START_DATA_SECTION const lpc24xx_pin_range
lpc24xx_start_config_pinsel [] = {
#if defined(LPC24XX_EMC_MT48LC4M16A2) \
- && defined(LPC24XX_EMC_NUMONYX_M29W160E)
+ && defined(LPC24XX_EMC_M29W160E)
LPC24XX_PIN_EMC_A_0_20,
LPC24XX_PIN_EMC_D_0_15,
LPC24XX_PIN_EMC_RAS,
@@ -39,22 +39,8 @@ BSP_START_DATA_SECTION const lpc24xx_pin_range
LPC24XX_PIN_EMC_OE,
LPC24XX_PIN_EMC_CS_1,
#endif
-#if defined(LPC24XX_EMC_IS42S32800B)
- LPC24XX_PIN_EMC_A_0_14,
- LPC24XX_PIN_EMC_D_0_31,
- LPC24XX_PIN_EMC_RAS,
- LPC24XX_PIN_EMC_CAS,
- LPC24XX_PIN_EMC_WE,
- LPC24XX_PIN_EMC_DYCS_0,
- LPC24XX_PIN_EMC_CLK_0,
- LPC24XX_PIN_EMC_CKE_0,
- LPC24XX_PIN_EMC_DQM_0,
- LPC24XX_PIN_EMC_DQM_1,
- LPC24XX_PIN_EMC_DQM_2,
- LPC24XX_PIN_EMC_DQM_3,
-#endif
-#if defined(LPC24XX_EMC_W9825G2JB75I) \
- && defined(LPC24XX_EMC_SST39VF3201)
+#if (defined(LPC24XX_EMC_IS42S32800D7) || defined(LPC24XX_EMC_W9825G2JB75I)) \
+ && (defined(LPC24XX_EMC_M29W320E70) || defined(LPC24XX_EMC_SST39VF3201))
LPC24XX_PIN_EMC_A_0_22,
LPC24XX_PIN_EMC_D_0_31,
LPC24XX_PIN_EMC_RAS,
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