[rtems commit] bsp/mpc5200: Fix cache handling
Sebastian Huber
sebh at rtems.org
Tue Apr 23 07:54:58 UTC 2013
Module: rtems
Branch: master
Commit: d5587f9f3bd9279da069148c49a4f7247324e3b8
Changeset: http://git.rtems.org/rtems/commit/?id=d5587f9f3bd9279da069148c49a4f7247324e3b8
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Wed Apr 17 16:03:03 2013 +0200
bsp/mpc5200: Fix cache handling
---
.../lib/libbsp/powerpc/gen5200/startup/bspstart.c | 10 ----------
c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c | 14 ++++++--------
2 files changed, 6 insertions(+), 18 deletions(-)
diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c b/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c
index 4b674d4..821b633 100644
--- a/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c
@@ -165,16 +165,6 @@ void bsp_start(void)
bsp_time_base_frequency = XLB_CLOCK / 4;
bsp_clicks_per_usec = (XLB_CLOCK/4000000);
- /*
- * Enable instruction and data caches. Do not force writethrough mode.
- */
- #if BSP_INSTRUCTION_CACHE_ENABLED
- rtems_cache_enable_instruction();
- #endif
- #if BSP_DATA_CACHE_ENABLED
- rtems_cache_enable_data();
- #endif
-
/* Initialize exception handler */
ppc_exc_cache_wb_check = 0;
ppc_exc_initialize(
diff --git a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
index bd43309..13f98b8 100644
--- a/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
+++ b/c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
@@ -290,8 +290,9 @@ void cpu_init(void)
{
uint32_t msr;
- /* Enable instruction cache */
- PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICE);
+ #if BSP_INSTRUCTION_CACHE_ENABLED
+ rtems_cache_enable_instruction();
+ #endif
/* Set up DBAT registers in MMU */
cpu_init_bsp();
@@ -311,10 +312,7 @@ void cpu_init(void)
/* Update MSR */
ppc_set_machine_state_register( msr);
- /*
- * Enable data cache.
- *
- * NOTE: TRACE32 now supports data cache for MGT5x00.
- */
- PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_DCE);
+ #if BSP_DATA_CACHE_ENABLED
+ rtems_cache_enable_data();
+ #endif
}
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