[rtems commit] bsp/mpc5200: Remove Erratum 342/339 comment
Sebastian Huber
sebh at rtems.org
Tue Apr 23 07:54:59 UTC 2013
Module: rtems
Branch: master
Commit: 27937780a44bfaea9a118541346e08ae57d0b074
Changeset: http://git.rtems.org/rtems/commit/?id=27937780a44bfaea9a118541346e08ae57d0b074
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Fri Apr 19 13:00:14 2013 +0200
bsp/mpc5200: Remove Erratum 342/339 comment
---
c/src/lib/libbsp/powerpc/gen5200/start/start.S | 14 --------------
1 files changed, 0 insertions(+), 14 deletions(-)
diff --git a/c/src/lib/libbsp/powerpc/gen5200/start/start.S b/c/src/lib/libbsp/powerpc/gen5200/start/start.S
index 2d20f17..932db11 100644
--- a/c/src/lib/libbsp/powerpc/gen5200/start/start.S
+++ b/c/src/lib/libbsp/powerpc/gen5200/start/start.S
@@ -515,21 +515,7 @@ SDRAM_init:
stw r29,GPIOPCR(r31)
#endif
- /* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf: */
- /* set 5 delays to their maximum to support two banks */
-#if 0
- LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
-#else
- /* EB 04.12.08:
- * on MPC5200B, Erratum342 is no longer applicable.
- * on MPC5200_, Single Write2Read/Prec is only 3 bits,
- * therefore the MSB of the set value (1100) was ignored
- * in the MPC5200B, this bit is implemented in results in
- * SSSLLLOOOWWW access to SDRAM. To make the mem ctrl settings compatible with the MPC5200_,
- * we use a 4 for now.
- */
LWI r30, 0xC4222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */
-#endif
stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
/* Refr.2No-Read delay=0x06, Write latency=0x0 */
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