[rtems commit] bsp/mpc5200: Set SDELAY register
Sebastian Huber
sebh at rtems.org
Tue Apr 23 07:54:59 UTC 2013
Module: rtems
Branch: master
Commit: d4a4811450b25fe55221cc22362bb3061f5149bb
Changeset: http://git.rtems.org/rtems/commit/?id=d4a4811450b25fe55221cc22362bb3061f5149bb
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Fri Apr 19 14:01:47 2013 +0200
bsp/mpc5200: Set SDELAY register
---
c/src/lib/libbsp/powerpc/gen5200/start/start.S | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/c/src/lib/libbsp/powerpc/gen5200/start/start.S b/c/src/lib/libbsp/powerpc/gen5200/start/start.S
index faf7b1e..057d294 100644
--- a/c/src/lib/libbsp/powerpc/gen5200/start/start.S
+++ b/c/src/lib/libbsp/powerpc/gen5200/start/start.S
@@ -119,6 +119,7 @@
.set CFG1, 0x108
.set CFG2, 0x10C
.set ADRSEL, 0x110
+.set SDELAY, 0x190
/* Register offsets of MPC5x00 GPIO registers needed */
.set GPIOPCR, 0xb00
@@ -522,6 +523,12 @@ SDRAM_init:
stw r29,GPIOPCR(r31)
#endif
+
+ #define SDELAY_VAL 0x00000004
+
+ LWI r3, SDELAY_VAL
+ stw r3, SDELAY(r31)
+
LWI r30, 0xC4222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */
stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
/* Refr.2No-Read delay=0x06, Write latency=0x0 */
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