[rtems commit] bsp/mpc5200: Change SDRAM initialization
Sebastian Huber
sebh at rtems.org
Tue Apr 23 07:54:59 UTC 2013
Module: rtems
Branch: master
Commit: 7a44d06c827497f57b33c62dfb4d14ea6af48c8b
Changeset: http://git.rtems.org/rtems/commit/?id=7a44d06c827497f57b33c62dfb4d14ea6af48c8b
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Fri Apr 19 14:17:09 2013 +0200
bsp/mpc5200: Change SDRAM initialization
Change SDRAM initialization according to application note AN3221.
---
c/src/lib/libbsp/powerpc/gen5200/start/start.S | 154 +++++++++++++++++-------
1 files changed, 112 insertions(+), 42 deletions(-)
diff --git a/c/src/lib/libbsp/powerpc/gen5200/start/start.S b/c/src/lib/libbsp/powerpc/gen5200/start/start.S
index 057d294..9f5379d 100644
--- a/c/src/lib/libbsp/powerpc/gen5200/start/start.S
+++ b/c/src/lib/libbsp/powerpc/gen5200/start/start.S
@@ -146,9 +146,9 @@
.set ADREN_CS1_EN, (1 << (31 - 14))
.set ADREN_WSE, (1 << (31 - 31))
-.set CTRL_PRECHARGE, (1<<1)
-.set CTRL_REFRESH, (1<<2)
-.set CTRL_BA1, (1<<31)
+.set CTRL_PRECHARGE_ALL, (1 << (31 - 30))
+.set CTRL_REFRESH, (1 << (31 - 29))
+.set CTRL_MODE_EN, (1 << (31 - 0))
.set CSCONF_CE, (1<<12)
@@ -496,6 +496,8 @@ twiddle:
#if defined(NEED_LOW_LEVEL_INIT)
SDRAM_init:
+ mflr r12
+
#if defined(MPC5200_BOARD_BRS5L)
/* set GPIO_WKUP7 pin low for 66MHz buffering */
/* or high for 133MHz registered buffering */
@@ -526,65 +528,116 @@ SDRAM_init:
#define SDELAY_VAL 0x00000004
- LWI r3, SDELAY_VAL
- stw r3, SDELAY(r31)
-
- LWI r30, 0xC4222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */
- stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
- /* Refr.2No-Read delay=0x06, Write latency=0x0 */
-
- LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
- stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
-
-#ifdef MPC5200_BOARD_BRS5L
- LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
- stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
+ /*
+ * Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4
+ * Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2
+ */
+ #define CFG1_VAL 0xC4222600
+ /* Refr.2No-Read delay=0x06, Write latency=0x0 */
+ /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
+ /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
+ #define CFG2_VAL 0xCCC70004
+#if defined(MPC5200_BOARD_BRS5L)
+ /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
+ /* Refresh counter=0xFFFF */
+ #define CTRL_VAL 0xD1470000
#else
- LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
- stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
-
-
+ /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
+ /* Refresh counter=0xFFFF */
+ #define CTRL_VAL 0xD04F0000
#endif
- lwz r30, CTRL(r31)
-
-
- SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */
- stw r30, CTRL(r31)
-
-
- stw r30, CTRL(r31)
-
-
- lwz r30, CTRL(r31)
+ /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
+ #define MODE_VAL 0x008D0000
+ /* SDRAM initialization according to application note AN3221 */
- SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */
- stw r30, CTRL(r31)
-
-
- stw r30, CTRL(r31)
+ /* SDRAM controller setup */
+ LWI r3, SDELAY_VAL
+ stw r3, SDELAY(r31)
+ LWI r3, CFG1_VAL
+ stw r3, CFG1(r31)
- LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
- stw r30, MOD(r31)
+ LWI r3, CFG2_VAL
+ stw r3, CFG2(r31)
+ LWI r11, CTRL_VAL
+ stw r11, CTRL(r31)
+ lwz r3, CTRL(r31)
+ /* Perform a PRECHARGE ALL command */
+ ori r3, r11, CTRL_PRECHARGE_ALL
+ stw r3, CTRL(r31)
+ lwz r3, CTRL(r31)
- lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */
+ /* Wait at least tRP time */
+ li r3, 15
+ bl ndelay
+#if defined(EMODE_VAL)
+ /* Write EMODE register */
+ LWI r3, EMODE_VAL
+ stw r3, MOD(r31)
- CLRBITS r30, r29, CTRL_BA1
- stw r30, CTRL(r31)
+ /* Wait at least tMRD time */
+ li r3, 10
+ bl ndelay
+#endif
+ /* Write MODE register */
+ LWI r3, MODE_VAL
+ stw r3, MOD(r31)
+
+ /* Wait at least tMRD time */
+ li r3, 10
+ bl ndelay
+
+ /* Perform a PRECHARGE ALL command */
+ ori r3, r11, CTRL_PRECHARGE_ALL
+ stw r3, CTRL(r31)
+ lwz r3, CTRL(r31)
+
+ /* Wait at least tRP time */
+ li r3, 15
+ bl ndelay
+
+ /* Perform an AUTO REFRESH */
+ ori r3, r11, CTRL_REFRESH
+ stw r3, CTRL(r31)
+ lwz r3, CTRL(r31)
+
+ /* Wait at least tRFC time */
+ li r3, 70
+ bl ndelay
+
+ /* Perform an AUTO REFRESH */
+ ori r3, r11, CTRL_REFRESH
+ stw r3, CTRL(r31)
+ lwz r3, CTRL(r31)
+
+ /* Wait at least tRFC time */
+ li r3, 70
+ bl ndelay
+
+#if defined(SECOND_MODE_VAL)
+ /* Write MODE register */
+ LWI r3, SECOND_MODE_VAL
+ stw r3, MOD(r31)
+#endif
+ /* Disable MODE register access */
+ lis r4, CTRL_MODE_EN at h
+ andc r3, r11, r4
+ stw r3, CTRL(r31)
+ lwz r3, CTRL(r31)
+ mtlr r12
blr
-
copy_image:
mr r27, r28
srwi r28, r28, 2
@@ -901,3 +954,20 @@ XLB_init:
stw r30, ARBDATTO(r31) /* Set ARBDATTO */
blr
+
+ndelay:
+ /*
+ * The maximum core frequency is 396MHz.
+ * We have (396MHz * 1024) / 10**9 == 405.
+ */
+ mulli r3, r3, 405
+ srwi. r3, r3, 10
+
+ beqlr
+
+ mtctr r3
+
+ndelay_loop:
+ bdnz ndelay_loop
+
+ blr
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