[rtems commit] i386: shared: Add doxygen
Gedare Bloom
gedare at rtems.org
Mon Dec 23 19:57:26 UTC 2013
Module: rtems
Branch: master
Commit: 52943a24710905392c7d4375b204e36bcdd514d7
Changeset: http://git.rtems.org/rtems/commit/?id=52943a24710905392c7d4375b204e36bcdd514d7
Author: Chirayu Desai <cdesai at cyanogenmod.org>
Date: Tue Dec 24 00:07:00 2013 +0530
i386: shared: Add doxygen
---
c/src/lib/libbsp/i386/shared/comm/i386_io.h | 15 +++
c/src/lib/libbsp/i386/shared/comm/tty_drv.h | 20 +++-
c/src/lib/libbsp/i386/shared/comm/uart.h | 174 +++++++++++++++------------
c/src/lib/libbsp/i386/shared/doxygen.h | 23 ++++
c/src/lib/libbsp/i386/shared/irq/apic.h | 19 +++-
c/src/lib/libbsp/i386/shared/irq/irq.h | 31 ++++--
c/src/lib/libbsp/i386/shared/irq/irq_asm.h | 22 ++--
c/src/lib/libbsp/i386/shared/pci/pcibios.h | 19 +++-
c/src/lib/libbsp/i386/shared/smp/smp-imps.h | 45 +++++--
9 files changed, 252 insertions(+), 116 deletions(-)
diff --git a/c/src/lib/libbsp/i386/shared/comm/i386_io.h b/c/src/lib/libbsp/i386/shared/comm/i386_io.h
index b396195..1308d58 100644
--- a/c/src/lib/libbsp/i386/shared/comm/i386_io.h
+++ b/c/src/lib/libbsp/i386/shared/comm/i386_io.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ * @ingroup i386_io
+ * @brief I/O
+ */
+
/*
* Copyright (c) 2000 - Rosimildo da Silva. All Rights Reserved.
*
@@ -10,6 +16,13 @@
*
*/
+/**
+ * @defgroup i386_io I/O
+ * @ingroup i386_comm
+ * @brief I/O
+ * @{
+ */
+
#ifndef i386_io_h__
#define i386_io_h__
@@ -56,3 +69,5 @@
#define sti() __asm__ __volatile__("sti");
#endif /* i386_io_h__ */
+
+/** @} */
diff --git a/c/src/lib/libbsp/i386/shared/comm/tty_drv.h b/c/src/lib/libbsp/i386/shared/comm/tty_drv.h
index e52cd51..cbfb346 100644
--- a/c/src/lib/libbsp/i386/shared/comm/tty_drv.h
+++ b/c/src/lib/libbsp/i386/shared/comm/tty_drv.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ * @ingroup i386_tty
+ * @brief ttySx driver
+ */
+
#ifndef __tty_drv__
#define __tty_drv__
/***************************************************************************
@@ -12,13 +18,19 @@
*
****************************************************************************/
+/**
+ * @defgroup i386_tty ttSx
+ * @ingroup i386_comm
+ * @brief i386 tySx driver
+ * @{
+ */
/* functions */
#ifdef __cplusplus
extern "C" {
#endif
-/* ttyS1 entry points */
+/** @brief ttyS1 entry points */
rtems_device_driver tty1_initialize(
rtems_device_major_number,
rtems_device_minor_number,
@@ -37,7 +49,7 @@ rtems_device_driver tty1_control(
void *
);
-/* tty1 & tty2 shared entry points */
+/** @brief tty1 & tty2 shared entry points */
rtems_device_driver tty_close(
rtems_device_major_number,
rtems_device_minor_number,
@@ -56,7 +68,7 @@ rtems_device_driver tty_write(
void *
);
-/* tty2 entry points */
+/** @brief tty2 entry points */
rtems_device_driver tty2_initialize(
rtems_device_major_number,
rtems_device_minor_number,
@@ -83,6 +95,8 @@ rtems_device_driver tty2_control(
{ tty2_initialize, tty2_open, tty_close, \
tty_read, tty_write, tty2_control }
+/** @} */
+
#ifdef __cplusplus
}
#endif
diff --git a/c/src/lib/libbsp/i386/shared/comm/uart.h b/c/src/lib/libbsp/i386/shared/comm/uart.h
index 8f89a43..c23ebc5 100644
--- a/c/src/lib/libbsp/i386/shared/comm/uart.h
+++ b/c/src/lib/libbsp/i386/shared/comm/uart.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ * @ingroup i386_uart
+ * @brief i386 UART definitions
+ */
+
/*
* This software is Copyright (C) 1998 by T.sqware - all rights limited
* It is provided in to the public domain "as is", can be freely modified
@@ -5,6 +11,13 @@
* an endorsement by T.sqware of the product in which it is included.
*/
+/**
+ * @defgroup i386_uart UART
+ * @ingroup i386_comm
+ * @brief i386 UART definitions
+ * @{
+ */
+
#ifndef _BSPUART_H
#define _BSPUART_H
@@ -34,57 +47,58 @@ extern int BSP_poll_char_via_serial(void);
extern void BSP_output_char_via_serial(char val);
extern int BSPConsolePort;
extern int BSPBaseBaud;
-/*
+
+/** @brief
* Command values for BSP_uart_intr_ctrl(),
* values are strange in order to catch errors
* with assert
*/
#define BSP_UART_INTR_CTRL_DISABLE (0)
-#define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */
-#define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */
-#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */
+#define BSP_UART_INTR_CTRL_GDB (0xaa) ///< RX only
+#define BSP_UART_INTR_CTRL_ENABLE (0xbb) ///< Normal operations
+#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) ///< RX & line status
-/* Return values for uart_polled_status() */
-#define BSP_UART_STATUS_ERROR (-1) /* No character */
-#define BSP_UART_STATUS_NOCHAR (0) /* No character */
-#define BSP_UART_STATUS_CHAR (1) /* Character present */
-#define BSP_UART_STATUS_BREAK (2) /* Break point is detected */
+/** @brief Return values for uart_polled_status() */
+#define BSP_UART_STATUS_ERROR (-1) ///< No character
+#define BSP_UART_STATUS_NOCHAR (0) ///< No character
+#define BSP_UART_STATUS_CHAR (1) ///< Character present
+#define BSP_UART_STATUS_BREAK (2) ///< Break point is detected
-/* PC UART definitions */
+/** @brief PC UART definitions */
#define BSP_UART_COM1 (0)
#define BSP_UART_COM2 (1)
-/*
+/** @brief
* Base IO for UART
*/
#define COM1_BASE_IO 0x3F8
#define COM2_BASE_IO 0x2F8
-/*
+/** @brief
* Offsets from base
*/
-/* DLAB 0 */
-#define RBR (0) /* Rx Buffer Register (read) */
-#define THR (0) /* Tx Buffer Register (write) */
-#define IER (1) /* Interrupt Enable Register */
-
-/* DLAB X */
-#define IIR (2) /* Interrupt Ident Register (read) */
-#define FCR (2) /* FIFO Control Register (write) */
-#define LCR (3) /* Line Control Register */
-#define MCR (4) /* Modem Control Register */
-#define LSR (5) /* Line Status Register */
-#define MSR (6) /* Modem Status Register */
-#define SCR (7) /* Scratch register */
-
-/* DLAB 1 */
-#define DLL (0) /* Divisor Latch, LSB */
-#define DLM (1) /* Divisor Latch, MSB */
-#define AFR (2) /* Alternate Function register */
-
-/*
+/** @brief DLAB 0 */
+#define RBR (0) ///< Rx Buffer Register (read)
+#define THR (0) ///< Tx Buffer Register (write)
+#define IER (1) ///< Interrupt Enable Register
+
+/** @brief DLAB X */
+#define IIR (2) ///< Interrupt Ident Register (read)
+#define FCR (2) ///< FIFO Control Register (write)
+#define LCR (3) ///< Line Control Register
+#define MCR (4) ///< Modem Control Register
+#define LSR (5) ///< Line Status Register
+#define MSR (6) ///< Modem Status Register
+#define SCR (7) ///< Scratch register
+
+/** @brief DLAB 1 */
+#define DLL (0) ///< Divisor Latch, LSB
+#define DLM (1) ///< Divisor Latch, MSB
+#define AFR (2) ///< Alternate Function register
+
+/** @brief
* Interrupt source definition via IIR
*/
#define MODEM_STATUS 0
@@ -94,7 +108,7 @@ extern int BSPBaseBaud;
#define RECEIVER_ERROR 6
#define CHARACTER_TIMEOUT_INDICATION 12
-/*
+/** @brief
* Bits definition of IER
*/
#define RECEIVE_ENABLE 0x1
@@ -103,28 +117,28 @@ extern int BSPBaseBaud;
#define MODEM_ENABLE 0x8
#define INTERRUPT_DISABLE 0x0
-/*
+/** @brief
* Bits definition of the Line Status Register (LSR)
*/
-#define DR 0x01 /* Data Ready */
-#define OE 0x02 /* Overrun Error */
-#define PE 0x04 /* Parity Error */
-#define FE 0x08 /* Framing Error */
-#define BI 0x10 /* Break Interrupt */
-#define THRE 0x20 /* Transmitter Holding Register Empty */
-#define TEMT 0x40 /* Transmitter Empty */
-#define ERFIFO 0x80 /* Error receive Fifo */
-
-/*
+#define DR 0x01 ///< Data Ready
+#define OE 0x02 ///< Overrun Error
+#define PE 0x04 ///< Parity Error
+#define FE 0x08 ///< Framing Error
+#define BI 0x10 ///< Break Interrupt
+#define THRE 0x20 ///< Transmitter Holding Register Empty
+#define TEMT 0x40 ///< Transmitter Empty
+#define ERFIFO 0x80 ///< Error receive Fifo
+
+/** @brief
* Bits definition of the MODEM Control Register (MCR)
*/
-#define DTR 0x01 /* Data Terminal Ready */
-#define RTS 0x02 /* Request To Send */
-#define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */
-#define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */
-#define LB 0x10 /* Enable Internal Loop Back */
+#define DTR 0x01 ///< Data Terminal Ready
+#define RTS 0x02 ///< Request To Send
+#define OUT_1 0x04 ///< Output 1, (reserved on COMPAQ I/O Board)
+#define OUT_2 0x08 ///< Output 2, Enable Asynchronous Port Interrupts
+#define LB 0x10 ///< Enable Internal Loop Back
-/*
+/** @brief
* Bits definition of the Line Control Register (LCR)
*/
#define CHR_5_BITS 0
@@ -132,41 +146,43 @@ extern int BSPBaseBaud;
#define CHR_7_BITS 2
#define CHR_8_BITS 3
-#define WL 0x03 /* Word length mask */
-#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */
-#define PEN 0x08 /* Parity Enabled */
-#define EPS 0x10 /* Even Parity Select, otherwise Odd */
-#define SP 0x20 /* Stick Parity */
-#define BCB 0x40 /* Break Control Bit */
-#define DLAB 0x80 /* Enable Divisor Latch Access */
+#define WL 0x03 ///< Word length mask
+#define STB 0x04 ///< 1 Stop Bit, otherwise 2 Stop Bits
+#define PEN 0x08 ///< Parity Enabled
+#define EPS 0x10 ///< Even Parity Select, otherwise Odd
+#define SP 0x20 ///< Stick Parity
+#define BCB 0x40 ///< Break Control Bit
+#define DLAB 0x80 ///< Enable Divisor Latch Access
-/*
+/** @brief
* Bits definition of the MODEM Status Register (MSR)
*/
-#define DCTS 0x01 /* Delta Clear To Send */
-#define DDSR 0x02 /* Delta Data Set Ready */
-#define TERI 0x04 /* Trailing Edge Ring Indicator */
-#define DDCD 0x08 /* Delta Carrier Detect Indicator */
-#define CTS 0x10 /* Clear To Send (when loop back is active) */
-#define DSR 0x20 /* Data Set Ready (when loop back is active) */
-#define RI 0x40 /* Ring Indicator (when loop back is active) */
-#define DCD 0x80 /* Data Carrier Detect (when loop back is active) */
-
-/*
+#define DCTS 0x01 ///< Delta Clear To Send
+#define DDSR 0x02 ///< Delta Data Set Ready
+#define TERI 0x04 ///< Trailing Edge Ring Indicator
+#define DDCD 0x08 ///< Delta Carrier Detect Indicator
+#define CTS 0x10 ///< Clear To Send (when loop back is active)
+#define DSR 0x20 ///< Data Set Ready (when loop back is active)
+#define RI 0x40 ///< Ring Indicator (when loop back is active)
+#define DCD 0x80 ///< Data Carrier Detect (when loop back is active)
+
+/** @brief
* Bits definition of the FIFO Control Register : WD16C552 or NS16550
*/
-#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */
-#define FIFO_EN 0x01 /* Enable the FIFO */
-#define XMIT_RESET 0x02 /* Transmit FIFO Reset */
-#define RCV_RESET 0x04 /* Receive FIFO Reset */
-#define FCR3 0x08 /* do not understand manual! */
-
-#define RECEIVE_FIFO_TRIGGER1 0x0 /* trigger recieve interrupt after 1 byte */
-#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger recieve interrupt after 4 byte */
-#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger recieve interrupt after 8 byte */
-#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger recieve interrupt after 12 byte */
-#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */
+#define FIFO_CTRL 0x01 ///< Set to 1 permit access to other bits
+#define FIFO_EN 0x01 ///< Enable the FIFO
+#define XMIT_RESET 0x02 ///< Transmit FIFO Reset
+#define RCV_RESET 0x04 ///< Receive FIFO Reset
+#define FCR3 0x08 ///< do not understand manual!
+
+#define RECEIVE_FIFO_TRIGGER1 0x0 ///< trigger recieve interrupt after 1 byte
+#define RECEIVE_FIFO_TRIGGER4 0x40 ///< trigger recieve interrupt after 4 byte
+#define RECEIVE_FIFO_TRIGGER8 0x80 ///< trigger recieve interrupt after 8 byte
+#define RECEIVE_FIFO_TRIGGER12 0xc0 ///< trigger recieve interrupt after 12 byte
+#define TRIG_LEVEL 0xc0 ///< Mask for the trigger level
+
+/** @} */
#ifdef __cplusplus
}
diff --git a/c/src/lib/libbsp/i386/shared/doxygen.h b/c/src/lib/libbsp/i386/shared/doxygen.h
new file mode 100644
index 0000000..b1dd495
--- /dev/null
+++ b/c/src/lib/libbsp/i386/shared/doxygen.h
@@ -0,0 +1,23 @@
+/**
+ * @defgroup bsp_i386 i386
+ * @ingroup bsp_kit
+ * @brief i386 Board Support Packages
+ */
+
+/**
+ * @defgroup i386_shared i386 Shared Modules
+ * @ingroup bsp_i386
+ * @brief i386 Shared Modules
+ */
+
+/**
+ * @defgroup i386_comm Comm
+ * @ingroup i386_shared
+ * @brief Comm
+ */
+
+/**
+ * @defgroup i386_pci PCI
+ * @ingroup i386_shared
+ * @brief PCI
+ */
diff --git a/c/src/lib/libbsp/i386/shared/irq/apic.h b/c/src/lib/libbsp/i386/shared/irq/apic.h
index 063d274..9ae103b 100644
--- a/c/src/lib/libbsp/i386/shared/irq/apic.h
+++ b/c/src/lib/libbsp/i386/shared/irq/apic.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ * @ingroup i386_apic
+ * @brief Local and I/O APIC definitions
+ */
+
/*
* Author: Erich Boleyn <erich at uruk.org>
* http://www.uruk.org/~erich/
@@ -27,6 +33,13 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+/**
+ * @defgroup i386_apci
+ * @ingroup i386_pci
+ * @brief Intel Architecture local and I/O APIC definitions
+ * @{
+ */
+
/*
* Header file for Intel Architecture local and I/O APIC definitions.
*
@@ -58,10 +71,10 @@
/*
* Shared defines for I/O and local APIC definitions
*/
-/* APIC version register */
+/** @brief APIC version register */
#define APIC_VERSION(x) ((x) & 0xFF)
#define APIC_MAXREDIR(x) (((x) >> 16) & 0xFF)
-/* APIC id register */
+/** @brief APIC id register */
#define APIC_ID(x) ((x) >> 24)
#define APIC_VER_NEW 0x10
@@ -108,3 +121,5 @@
#define LAPIC_TDCR 0x3E0
#endif /* _APIC_H */
+
+/** @} */
diff --git a/c/src/lib/libbsp/i386/shared/irq/irq.h b/c/src/lib/libbsp/i386/shared/irq/irq.h
index 6439627..e176495 100644
--- a/c/src/lib/libbsp/i386/shared/irq/irq.h
+++ b/c/src/lib/libbsp/i386/shared/irq/irq.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ * @ingroup i386_irq
+ * @brief Interrupt handlers
+ */
+
/* irq.h
*
* This include file describe the data structure and the functions implemented
@@ -16,6 +22,13 @@
* http://www.rtems.com/license/LICENSE.
*/
+/**
+ * @defgroup i386_irq Interrupt handlers
+ * @ingroup i386_shared
+ * @brief Data structure and the functions to write interrupt handlers
+ * @{
+ */
+
#ifndef _IRQ_H_
#define _IRQ_H_
@@ -23,7 +36,7 @@
extern "C" {
#endif
-/*
+/** @brief
* Include some preprocessor value also used by assember code
*/
@@ -37,13 +50,13 @@ extern "C" {
| Constants
+--------------------------------------------------------------------------*/
- /* Base vector for our IRQ handlers. */
+ /** @brief Base vector for our IRQ handlers. */
#define BSP_IRQ_VECTOR_BASE BSP_ASM_IRQ_VECTOR_BASE
#define BSP_IRQ_LINES_NUMBER 17
#define BSP_LOWEST_OFFSET 0
#define BSP_MAX_ON_i8259S (BSP_IRQ_LINES_NUMBER - 2)
#define BSP_MAX_OFFSET (BSP_IRQ_LINES_NUMBER - 1)
- /*
+ /** @brief
* Interrupt offset in comparison to BSP_ASM_IRQ_VECTOR_BASE
* NB : 1) Interrupt vector number in IDT = offset + BSP_ASM_IRQ_VECTOR_BASE
* 2) The same name should be defined on all architecture
@@ -62,7 +75,7 @@ extern "C" {
#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
-/*
+/** @brief
* Type definition for RTEMS managed interrupts
*/
typedef unsigned short rtems_i8259_masks;
@@ -76,19 +89,19 @@ extern rtems_i8259_masks i8259s_cache;
* ------------------------ Intel 8259 (or emulation) Mngt Routines -------
*/
-/*
+/** @brief
* function to disable a particular irq at 8259 level. After calling
* this function, even if the device asserts the interrupt line it will
* not be propagated further to the processor
*/
int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine);
-/*
+/** @brief
* function to enable a particular irq at 8259 level. After calling
* this function, if the device asserts the interrupt line it will
* be propagated further to the processor
*/
int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine);
-/*
+/** @brief
* function to acknoledge a particular irq at 8259 level. After calling
* this function, if a device asserts an enabled interrupt line it will
* be propagated further to the processor. Mainly usefull for people
@@ -96,11 +109,13 @@ int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine);
* handlers.
*/
int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine);
-/*
+/** @brief
* function to check if a particular irq is enabled at 8259 level. After calling
*/
int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine);
+/** @} */
+
#ifdef __cplusplus
}
#endif
diff --git a/c/src/lib/libbsp/i386/shared/irq/irq_asm.h b/c/src/lib/libbsp/i386/shared/irq/irq_asm.h
index a2d9d16..455e6a3 100644
--- a/c/src/lib/libbsp/i386/shared/irq/irq_asm.h
+++ b/c/src/lib/libbsp/i386/shared/irq/irq_asm.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ * @ingroup i386_irq
+ * @brief
+ */
+
/* irq_asm.h
*
* This include file has defines to represent some contant used
@@ -14,14 +20,14 @@
#define __IRQ_ASM_H__
#define BSP_ASM_IRQ_VECTOR_BASE 0x20
- /* PIC's command and mask registers */
-#define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */
-#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */
-#define PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */
-#define PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */
+ /** @brief PIC's command and mask registers */
+#define PIC_MASTER_COMMAND_IO_PORT 0x20 ///< Master PIC command register
+#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 ///< Slave PIC command register
+#define PIC_MASTER_IMR_IO_PORT 0x21 ///< Master PIC Interrupt Mask Register
+#define PIC_SLAVE_IMR_IO_PORT 0xa1 ///< Slave PIC Interrupt Mask Register
- /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
-#define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */
-#define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */
+ /** @brief Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
+#define PIC_EOSI 0x60 ///< End of Specific Interrupt (EOSI)
+#define PIC_EOI 0x20 ///< Generic End of Interrupt (EOI)
#endif
diff --git a/c/src/lib/libbsp/i386/shared/pci/pcibios.h b/c/src/lib/libbsp/i386/shared/pci/pcibios.h
index 1a628cc..0bd693a 100644
--- a/c/src/lib/libbsp/i386/shared/pci/pcibios.h
+++ b/c/src/lib/libbsp/i386/shared/pci/pcibios.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ * @ingroup i386_pcibios
+ * @brief
+ */
+
/*
* This software is Copyright (C) 1998 by T.sqware - all rights limited
* It is provided in to the public domain "as is", can be freely modified
@@ -5,18 +11,25 @@
* an endorsement by T.sqware of the product in which it is included.
*/
+/**
+ * @defgroup i386_pcibios
+ * @ingroup i386_pci
+ * @brief
+ * @{
+ */
+
#ifndef _PCIB_H
#define _PCIB_H
#include <rtems/pci.h>
-/*
+/** @brief
* Make device signature from bus number, device numebr and function
* number
*/
#define PCIB_DEVSIG_MAKE(b,d,f) ((b<<8)|(d<<3)|(f))
-/*
+/** @brief
* Extract valrous part from device signature
*/
#define PCIB_DEVSIG_BUS(x) (((x)>>8) &0xff)
@@ -40,6 +53,8 @@ int
pci_find_device( unsigned short vendorid, unsigned short deviceid,
int instance, int *pbus, int *pdev, int *pfun );
+/** @} */
+
#ifdef __cplusplus
}
#endif
diff --git a/c/src/lib/libbsp/i386/shared/smp/smp-imps.h b/c/src/lib/libbsp/i386/shared/smp/smp-imps.h
index 7870420..12a74b1 100644
--- a/c/src/lib/libbsp/i386/shared/smp/smp-imps.h
+++ b/c/src/lib/libbsp/i386/shared/smp/smp-imps.h
@@ -1,3 +1,10 @@
+/**
+ * @file
+ * @ingroup i386_smp
+ * @brief Intel MultiProcessor Specification (MPS)
+ * version 1.1 and 1.4 SMP hardware control
+ */
+
/*
* Author: Erich Boleyn <erich at uruk.org>
* http://www.uruk.org/~erich/
@@ -51,6 +58,15 @@
* http://www.rtems.com/license/LICENSE.
*/
+/**
+ * @defgroup i386_smp SMP
+ * @ingroup i386_shared
+ * @brief
+ * Header file implementing Intel MultiProcessor Specification (MPS)
+ * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs,
+ * with hooks for running correctly on a standard PC without the hardware.
+ */
+
#ifndef _SMP_IMPS_H
#define _SMP_IMPS_H
@@ -74,7 +90,7 @@
#define IMPS_MAX_CPUS APIC_BCAST_ID
-/*
+/** @brief
* This is the value that must be in the "sig" member of the MP
* Floating Pointer Structure.
*/
@@ -82,13 +98,13 @@
#define IMPS_FPS_IMCRP_BIT 0x80
#define IMPS_FPS_DEFAULT_MAX 7
-/*
+/** @brief
* This is the value that must be in the "sig" member of the MP
* Configuration Table Header.
*/
#define IMPS_CTH_SIGNATURE ('P' | ('C'<<8) | ('M'<<16) | ('P'<<24))
-/*
+/** @brief
* These are the "type" values for Base MP Configuration Table entries.
*/
#define IMPS_FLAG_ENABLED 1
@@ -108,8 +124,8 @@
* Typedefs and data item definitions done here.
*/
-typedef struct imps_fps imps_fps; /* MP floating pointer structure */
-typedef struct imps_cth imps_cth; /* MP configuration table header */
+typedef struct imps_fps imps_fps; ///< MP floating pointer structure
+typedef struct imps_cth imps_cth; ///< MP configuration table header
typedef struct imps_processor imps_processor;
typedef struct imps_bus imps_bus;
typedef struct imps_ioapic imps_ioapic;
@@ -120,7 +136,7 @@ typedef struct imps_interrupt imps_interrupt;
* Data structures defined here
*/
-/*
+/** @brief
* MP Floating Pointer Structure (fps)
*
* Look at page 4-3 of the MP spec for the starting definitions of
@@ -136,7 +152,7 @@ struct imps_fps
unsigned char feature_info[5];
};
-/*
+/** @brief
* MP Configuration Table Header (cth)
*
* Look at page 4-5 of the MP spec for the starting definitions of
@@ -159,7 +175,7 @@ struct imps_cth
char reserved[1];
};
-/*
+/** @brief
* Base MP Configuration Table Types. They are sorted according to
* type (i.e. all of type 0 come first, etc.). Look on page 4-6 for
* the start of the descriptions.
@@ -167,7 +183,7 @@ struct imps_cth
struct imps_processor
{
- unsigned char type; /* must be 0 */
+ unsigned char type; ///< must be 0
unsigned char apic_id;
unsigned char apic_ver;
unsigned char flags;
@@ -178,14 +194,14 @@ struct imps_processor
struct imps_bus
{
- unsigned char type; /* must be 1 */
+ unsigned char type; ///< must be 1
unsigned char id;
char bus_type[6];
};
struct imps_ioapic
{
- unsigned char type; /* must be 2 */
+ unsigned char type; ///< must be 2
unsigned char id;
unsigned char ver;
unsigned char flags;
@@ -194,7 +210,7 @@ struct imps_ioapic
struct imps_interrupt
{
- unsigned char type; /* must be 3 or 4 */
+ unsigned char type; ///< must be 3 or 4
unsigned char int_type;
unsigned short flags;
unsigned char source_bus_id;
@@ -207,13 +223,13 @@ struct imps_interrupt
* Exported globals here.
*/
-/*
+/** @brief
* These map from virtual cpu numbers to APIC id's and back.
*/
extern unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS];
extern unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
-/* base address of application processor reset code at 0x70000 */
+/** @brief base address of application processor reset code at 0x70000 */
extern char _binary_appstart_bin_start[];
extern char _binary_appstart_bin_size[];
@@ -226,3 +242,4 @@ extern char _binary_appstart_bin_size[];
#endif /* !_SMP_IMPS_H */
+/** @} */
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