[rtems commit] bfin_eZKit533: added new doxygen
Gedare Bloom
gedare at rtems.org
Tue Dec 24 18:12:24 UTC 2013
Module: rtems
Branch: master
Commit: 997f22342c149333aa1740d7ae31c8dd667d0be0
Changeset: http://git.rtems.org/rtems/commit/?id=997f22342c149333aa1740d7ae31c8dd667d0be0
Author: Daniel Ramirez <javamonn at gmail.com>
Date: Tue Dec 24 12:06:55 2013 -0600
bfin_eZKit533: added new doxygen
---
c/src/lib/libbsp/bfin/eZKit533/include/bsp.h | 109 ++++++++++++++++---------
c/src/lib/libbsp/bfin/eZKit533/include/cplb.h | 15 ++++
c/src/lib/libbsp/bfin/eZKit533/include/tm27.h | 15 ++++
3 files changed, 102 insertions(+), 37 deletions(-)
diff --git a/c/src/lib/libbsp/bfin/eZKit533/include/bsp.h b/c/src/lib/libbsp/bfin/eZKit533/include/bsp.h
index 3840ed5..59fa0a4 100644
--- a/c/src/lib/libbsp/bfin/eZKit533/include/bsp.h
+++ b/c/src/lib/libbsp/bfin/eZKit533/include/bsp.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ * @ingroup bfin_ezkit533
+ * @brief Global BSP definitions.
+ */
+
/* bsp.h
*
* This include file contains all board IO definitions for eZKit533.
@@ -30,55 +36,72 @@ extern "C" {
#include <rtems/score/bfin.h>
#include <rtems/bfin/bf533.h>
-/*
- * PLL and clock setup values:
+/**
+ * @defgroup bfin_ezkit533 eZKit533 Support
+ * @ingroup bsp_bfin
+ * @brief eZKit533 Board Support Package
+ * @{
*/
-/*
- * PLL configuration for ezkit533
+/**
+ * @name PLL and clock setup values:
+ * @brief PLL configuration for ezkit533
*
* XTL = 27 MHz
* CLKIN = 13 MHz
* VCO = 391 MHz
* CCLK = 391 MHz
* SCLK = 130 MHz
+ *
+ * @{
+ *
*/
-#define PLL_CSEL 0x0000 /* CCLK = VCO */
-#define PLL_SSEL 0x0003 /* SCLK = CCLK/3 */
-#define PLL_MSEL 0x3A00 /* VCO = 29xCLKIN */
-#define PLL_DF 0x0001 /* CLKIN = XTL/2 */
+#define PLL_CSEL 0x0000 ///< @brief CCLK = VCO */
+#define PLL_SSEL 0x0003 ///< @brief SCLK = CCLK/3 */
+#define PLL_MSEL 0x3A00 ///< @brief VCO = 29xCLKIN */
+#define PLL_DF 0x0001 ///< @brief CLKIN = XTL/2 */
-#define CCLK 391000000 /* CORE CLOCK */
-#define SCLK 130000000 /* SYSTEM CLOCK */
+#define CCLK 391000000 ///< @brief CORE CLOCK */
+#define SCLK 130000000 ///< @brief SYSTEM CLOCK */
-/*
- * UART setup values
+/** @} */
+
+/**
+ * @name UART setup values
+ * @{
*/
-#define BAUDRATE 57600 /* Console Baudrate */
-#define WORD_5BITS 0x00 /* 5 bits word */
-#define WORD_6BITS 0x01 /* 6 bits word */
-#define WORD_7BITS 0x02 /* 7 bits word */
-#define WORD_8BITS 0x03 /* 8 bits word */
-#define EVEN_PARITY 0x18 /* Enable EVEN parity */
-#define ODD_PARITY 0x08 /* Enable ODD parity */
-#define TWO_STP_BIT 0x04 /* 2 stop bits */
-
-/*
- * Ezkit flash ports
+
+#define BAUDRATE 57600 ///< @brief Console Baudrate */
+#define WORD_5BITS 0x00 ///< @brief 5 bits word */
+#define WORD_6BITS 0x01 ///< @brief 6 bits word */
+#define WORD_7BITS 0x02 ///< @brief 7 bits word */
+#define WORD_8BITS 0x03 ///< @brief 8 bits word */
+#define EVEN_PARITY 0x18 ///< @brief Enable EVEN parity */
+#define ODD_PARITY 0x08 ///< @brief Enable ODD parity */
+#define TWO_STP_BIT 0x04 ///< @brief 2 stop bits */
+
+/** @} */
+
+/**
+ * @name Ezkit flash ports
+ * @{
*/
+
#define FlashA_PortB_Dir 0x20270007L
#define FlashA_PortB_Data 0x20270005L
-/*
- * Blackfin environment memory map
+/** @} */
+
+/**
+ * @brief Blackfin environment memory map
*/
#define L1_DATA_SRAM_A 0xff800000L
#define FIFOLENGTH 0x100
-/*
- * Simple spin delay in microsecond units for device drivers.
+/**
+ * @brief Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target.
*/
@@ -86,30 +109,42 @@ extern "C" {
{ \
}
-/* Constants */
+/**
+ * @name Constants
+ * @{
+ */
#define RAM_START 0
#define RAM_END 0x100000
-/* functions */
+/** @} */
-/*
- * Helper Function to use the EzKits LEDS.
+/**
+ * @name functions
+ * @{
+ */
+
+/**
+ * @brief Helper Function to use the EzKits LEDS.
* Can be used by the Application.
*/
void setLED (uint8_t value);
-/*
- * Helper Function to use the EzKits LEDS
+/**
+ * @brief Helper Function to use the EzKits LEDS
*/
uint8_t getLED (void);
-rtems_isr_entry set_vector( /* returns old vector */
- rtems_isr_entry handler, /* isr routine */
- rtems_vector_number vector, /* vector number */
- int type /* RTEMS or RAW intr */
+rtems_isr_entry set_vector( ///< @brief returns old vector */
+ rtems_isr_entry handler, ///< @brief isr routine */
+ rtems_vector_number vector, ///< @brief vector number */
+ int type ///< @brief RTEMS or RAW intr */
);
+/** @} */
+
+/** @} */
+
#ifdef __cplusplus
}
#endif
diff --git a/c/src/lib/libbsp/bfin/eZKit533/include/cplb.h b/c/src/lib/libbsp/bfin/eZKit533/include/cplb.h
index 9b10845..45b5712 100644
--- a/c/src/lib/libbsp/bfin/eZKit533/include/cplb.h
+++ b/c/src/lib/libbsp/bfin/eZKit533/include/cplb.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ * @ingroup ezkit533_cplb
+ * @brief CPLB configurations.
+ */
+
/* cplb.h
*
* Copyright (c) 2006 by Atos Automacao Industrial Ltda.
@@ -10,6 +16,13 @@
#ifndef _CPLB_H
#define _CPLB_H
+/**
+ * @defgroup ezkit533_cplb CPLB Configuration
+ * @ingroup bfin_ezkit533
+ * @brief CPLB Configuration
+ * @{
+ */
+
/* CPLB configurations */
#define CPLB_DEF_CACHE_WT CPLB_L1_CHBL | CPLB_WT
#define CPLB_DEF_CACHE_WB CPLB_L1_CHBL
@@ -29,4 +42,6 @@
#define CPLB_DDOCACHE_WT CPLB_DNOCACHE | CPLB_DEF_CACHE_WT
#define CPLB_DDOCACHE_WB CPLB_DNOCACHE | CPLB_DEF_CACHE_WB
+/** @} */
+
#endif /* _CPLB_H */
diff --git a/c/src/lib/libbsp/bfin/eZKit533/include/tm27.h b/c/src/lib/libbsp/bfin/eZKit533/include/tm27.h
index 343b835..b5d5f49 100644
--- a/c/src/lib/libbsp/bfin/eZKit533/include/tm27.h
+++ b/c/src/lib/libbsp/bfin/eZKit533/include/tm27.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ * @ingroup ezkit533_tm27
+ * @brief Interrupt mechanisms for the tm27 test.
+ */
+
/*
* tm27.h
*
@@ -13,6 +19,13 @@
#ifndef __tm27_h
#define __tm27_h
+/**
+ * @defgroup ezkit533_tm27 TM27 Test Support
+ * @ingroup bfin_ezkit533
+ * @brief Interrupt Mechanisms for TM27
+ * @{
+ */
+
/*
* Define the interrupt mechanism for Time Test 27
*/
@@ -30,4 +43,6 @@
#define Lower_tm27_intr() /* empty */
+/** @} */
+
#endif
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