[rtems commit] bsp/stm32f4: Add STM32F10XXX support.
Sebastian Huber
sebh at rtems.org
Thu Sep 19 11:14:08 UTC 2013
Module: rtems
Branch: master
Commit: 1485a58ce30c4ced71446976036f03a5c32f451d
Changeset: http://git.rtems.org/rtems/commit/?id=1485a58ce30c4ced71446976036f03a5c32f451d
Author: Christian Mauderer <Christian.Mauderer at embedded-brains.de>
Date: Wed Sep 18 15:44:42 2013 +0200
bsp/stm32f4: Add STM32F10XXX support.
---
c/src/lib/libbsp/arm/stm32f4/Makefile.am | 6 +
c/src/lib/libbsp/arm/stm32f4/configure.ac | 10 +
c/src/lib/libbsp/arm/stm32f4/console/usart.c | 2 +
c/src/lib/libbsp/arm/stm32f4/include/io.h | 204 ++++++++++++++++++-
c/src/lib/libbsp/arm/stm32f4/include/rcc.h | 64 ++++++-
c/src/lib/libbsp/arm/stm32f4/include/stm32_usart.h | 95 +++++++++
.../libbsp/arm/stm32f4/include/stm32f10xxx_gpio.h | 36 ++++
.../libbsp/arm/stm32f4/include/stm32f10xxx_rcc.h | 33 +++
c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 153 +++-------------
.../libbsp/arm/stm32f4/include/stm32f4xxxx_gpio.h | 33 +++
.../libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h | 44 +++++
.../libbsp/arm/stm32f4/make/custom/stm32f105rc.cfg | 1 +
c/src/lib/libbsp/arm/stm32f4/preinstall.am | 20 ++
c/src/lib/libbsp/arm/stm32f4/startup/io.c | 147 ++++++++++++++-
.../arm/stm32f4/startup/linkcmds.stm32f105rc | 22 ++
c/src/lib/libbsp/arm/stm32f4/startup/rcc.c | 9 +
.../libbsp/arm/stm32f4/startup/start-config-io.c | 24 +++
17 files changed, 758 insertions(+), 145 deletions(-)
diff --git a/c/src/lib/libbsp/arm/stm32f4/Makefile.am b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
index 6203aa3..ef2c232 100644
--- a/c/src/lib/libbsp/arm/stm32f4/Makefile.am
+++ b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
@@ -19,6 +19,7 @@ project_lib_DATA += start.$(OBJEXT)
project_lib_DATA += startup/linkcmds
EXTRA_DIST = startup/linkcmds.stm32f4
+EXTRA_DIST += startup/linkcmds.stm32f105rc
###############################################################################
# Header #
@@ -46,6 +47,11 @@ include_bsp_HEADERS += ../shared/armv7m/include/armv7m-irq.h
include_bsp_HEADERS += include/irq.h
include_bsp_HEADERS += include/usart.h
include_bsp_HEADERS += include/stm32f4.h
+include_bsp_HEADERS += include/stm32f10xxx_gpio.h
+include_bsp_HEADERS += include/stm32f10xxx_rcc.h
+include_bsp_HEADERS += include/stm32f4xxxx_gpio.h
+include_bsp_HEADERS += include/stm32f4xxxx_rcc.h
+include_bsp_HEADERS += include/stm32_usart.h
include_bsp_HEADERS += include/io.h
include_bsp_HEADERS += include/rcc.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/configure.ac b/c/src/lib/libbsp/arm/stm32f4/configure.ac
index 14630a9..db3175c 100644
--- a/c/src/lib/libbsp/arm/stm32f4/configure.ac
+++ b/c/src/lib/libbsp/arm/stm32f4/configure.ac
@@ -17,18 +17,28 @@ AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
RTEMS_BSPOPTS_SET([BSP_SMALL_MEMORY],[*],[])
RTEMS_BSPOPTS_HELP([BSP_SMALL_MEMORY],[disable testsuite samples with high memory demands])
+RTEMS_BSPOPTS_SET([STM32F4_FAMILY_F10XXX],[stm32f1*],[1])
+RTEMS_BSPOPTS_HELP([STM32F4_FAMILY_F10XXX],[Chip belongs to the STM32F10XXX family.])
+
+RTEMS_BSPOPTS_SET([STM32F4_FAMILY_F4XXXX],[stm32f4*],[1])
+RTEMS_BSPOPTS_HELP([STM32F4_FAMILY_F4XXXX],[Chip belongs to the STM32F4XXXX family.])
+
RTEMS_BSPOPTS_SET([STM32F4_HSE_OSCILLATOR],[*],[8000000])
RTEMS_BSPOPTS_HELP([STM32F4_HSE_OSCILLATOR],[HSE oscillator frequency in Hz])
+RTEMS_BSPOPTS_SET([STM32F4_SYSCLK],[stm32f1*],[8000000])
RTEMS_BSPOPTS_SET([STM32F4_SYSCLK],[*],[16000000])
RTEMS_BSPOPTS_HELP([STM32F4_SYSCLK],[SYSCLK frequency in Hz])
+RTEMS_BSPOPTS_SET([STM32F4_HCLK],[stm32f1*],[8000000])
RTEMS_BSPOPTS_SET([STM32F4_HCLK],[*],[16000000])
RTEMS_BSPOPTS_HELP([STM32F4_HCLK],[HCLK frequency in Hz])
+RTEMS_BSPOPTS_SET([STM32F4_PCLK1],[stm32f1*],[8000000])
RTEMS_BSPOPTS_SET([STM32F4_PCLK1],[*],[16000000])
RTEMS_BSPOPTS_HELP([STM32F4_PCLK1],[PCLK1 frequency in Hz])
+RTEMS_BSPOPTS_SET([STM32F4_PCLK1],[stm32f1*],[8000000])
RTEMS_BSPOPTS_SET([STM32F4_PCLK2],[*],[16000000])
RTEMS_BSPOPTS_HELP([STM32F4_PCLK2],[PCLK2 frequency in Hz])
diff --git a/c/src/lib/libbsp/arm/stm32f4/console/usart.c b/c/src/lib/libbsp/arm/stm32f4/console/usart.c
index d072b51..e0671e4 100644
--- a/c/src/lib/libbsp/arm/stm32f4/console/usart.c
+++ b/c/src/lib/libbsp/arm/stm32f4/console/usart.c
@@ -39,7 +39,9 @@ static const stm32f4_rcc_index usart_rcc_index [] = {
STM32F4_RCC_USART3,
STM32F4_RCC_UART4,
STM32F4_RCC_UART5,
+#ifdef STM32F4_FAMILY_F4XXXX
STM32F4_RCC_USART6
+#endif /* STM32F4_FAMILY_F4XXXX */
};
static stm32f4_rcc_index usart_get_rcc_index(const console_tbl *ct)
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/io.h b/c/src/lib/libbsp/arm/stm32f4/include/io.h
index 032664c..1d8c512 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/io.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/io.h
@@ -16,13 +16,21 @@
#define LIBBSP_ARM_STM32F4_IO_H
#include <stdbool.h>
-
-#include <bsp/stm32f4.h>
+#include <stdint.h>
+#include <bspopts.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
+#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff)
+
+#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf)
+
+#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf)
+
+#ifdef STM32F4_FAMILY_F4XXXX
+
typedef enum {
STM32F4_GPIO_MODE_INPUT,
STM32F4_GPIO_MODE_OUTPUT,
@@ -86,12 +94,6 @@ typedef enum {
STM32F4_GPIO_AF_EVENTOUT = 15
} stm32f4_gpio_af;
-#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff)
-
-#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf)
-
-#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf)
-
typedef union {
struct {
uint32_t pin_first : 8;
@@ -108,15 +110,141 @@ typedef union {
uint32_t value;
} stm32f4_gpio_config;
+#define STM32F4_GPIO_CONFIG_TERMINAL \
+ { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } }
+
+#endif /* STM32F4_FAMILY_F4XXXX */
+#ifdef STM32F4_FAMILY_F10XXX
+
+typedef enum {
+ STM32F4_GPIO_MODE_INPUT,
+ STM32F4_GPIO_MODE_OUTPUT_10MHz,
+ STM32F4_GPIO_MODE_OUTPUT_2MHz,
+ STM32F4_GPIO_MODE_OUTPUT_50MHz
+} stm32f4_gpio_mode;
+
+typedef enum {
+ STM32F4_GPIO_CNF_IN_ANALOG = 0,
+ STM32F4_GPIO_CNF_IN_FLOATING = 1,
+ STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2,
+
+ STM32F4_GPIO_CNF_OUT_GPIO_PP = 0,
+ STM32F4_GPIO_CNF_OUT_GPIO_OD = 1,
+ STM32F4_GPIO_CNF_OUT_AF_PP = 2,
+ STM32F4_GPIO_CNF_OUT_AF_OD = 3,
+} stm32f4_gpio_cnf;
+
+typedef enum {
+ STM32F4_GPIO_REMAP_DONT_CHANGE,
+ STM32F4_GPIO_REMAP_SPI1_0,
+ STM32F4_GPIO_REMAP_SPI1_1,
+ STM32F4_GPIO_REMAP_I2C1_0,
+ STM32F4_GPIO_REMAP_I2C1_1,
+ STM32F4_GPIO_REMAP_USART1_0,
+ STM32F4_GPIO_REMAP_USART1_1,
+ STM32F4_GPIO_REMAP_USART2_0,
+ STM32F4_GPIO_REMAP_USART2_1,
+ STM32F4_GPIO_REMAP_USART3_0,
+ STM32F4_GPIO_REMAP_USART3_1,
+ STM32F4_GPIO_REMAP_USART3_3,
+ STM32F4_GPIO_REMAP_TIM1_0,
+ STM32F4_GPIO_REMAP_TIM1_1,
+ STM32F4_GPIO_REMAP_TIM1_3,
+ STM32F4_GPIO_REMAP_TIM2_0,
+ STM32F4_GPIO_REMAP_TIM2_1,
+ STM32F4_GPIO_REMAP_TIM2_2,
+ STM32F4_GPIO_REMAP_TIM2_3,
+ STM32F4_GPIO_REMAP_TIM3_0,
+ STM32F4_GPIO_REMAP_TIM3_2,
+ STM32F4_GPIO_REMAP_TIM3_3,
+ STM32F4_GPIO_REMAP_TIM4_0,
+ STM32F4_GPIO_REMAP_TIM4_1,
+ STM32F4_GPIO_REMAP_CAN1_0,
+ STM32F4_GPIO_REMAP_CAN1_2,
+ STM32F4_GPIO_REMAP_CAN1_3,
+ STM32F4_GPIO_REMAP_PD01_0,
+ STM32F4_GPIO_REMAP_PD01_1,
+ STM32F4_GPIO_REMAP_TIM5CH4_0,
+ STM32F4_GPIO_REMAP_TIM5CH4_1,
+ STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0,
+ STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1,
+ STM32F4_GPIO_REMAP_ADC1_ETRGREG_0,
+ STM32F4_GPIO_REMAP_ADC1_ETRGREG_1,
+ STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0,
+ STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1,
+ STM32F4_GPIO_REMAP_ADC2_ETRGREG_0,
+ STM32F4_GPIO_REMAP_ADC2_ETRGREG_1,
+ STM32F4_GPIO_REMAP_ETH_0,
+ STM32F4_GPIO_REMAP_ETH_1,
+ STM32F4_GPIO_REMAP_CAN2_0,
+ STM32F4_GPIO_REMAP_CAN2_1,
+ STM32F4_GPIO_REMAP_MII_RMII_0,
+ STM32F4_GPIO_REMAP_MII_RMII_1,
+ STM32F4_GPIO_REMAP_SWJ_0,
+ STM32F4_GPIO_REMAP_SWJ_1,
+ STM32F4_GPIO_REMAP_SWJ_2,
+ STM32F4_GPIO_REMAP_SWJ_4,
+ STM32F4_GPIO_REMAP_SPI3_0,
+ STM32F4_GPIO_REMAP_SPI3_1,
+ STM32F4_GPIO_REMAP_TIM2ITR1_0,
+ STM32F4_GPIO_REMAP_TIM2ITR1_1,
+ STM32F4_GPIO_REMAP_PTP_PPS_0,
+ STM32F4_GPIO_REMAP_PTP_PPS_1,
+ STM32F4_GPIO_REMAP_TIM15_0,
+ STM32F4_GPIO_REMAP_TIM15_1,
+ STM32F4_GPIO_REMAP_TIM16_0,
+ STM32F4_GPIO_REMAP_TIM16_1,
+ STM32F4_GPIO_REMAP_TIM17_0,
+ STM32F4_GPIO_REMAP_TIM17_1,
+ STM32F4_GPIO_REMAP_CEC_0,
+ STM32F4_GPIO_REMAP_CEC_1,
+ STM32F4_GPIO_REMAP_TIM1_DMA_0,
+ STM32F4_GPIO_REMAP_TIM1_DMA_1,
+ STM32F4_GPIO_REMAP_TIM9_0,
+ STM32F4_GPIO_REMAP_TIM9_1,
+ STM32F4_GPIO_REMAP_TIM10_0,
+ STM32F4_GPIO_REMAP_TIM10_1,
+ STM32F4_GPIO_REMAP_TIM11_0,
+ STM32F4_GPIO_REMAP_TIM11_1,
+ STM32F4_GPIO_REMAP_TIM13_0,
+ STM32F4_GPIO_REMAP_TIM13_1,
+ STM32F4_GPIO_REMAP_TIM14_0,
+ STM32F4_GPIO_REMAP_TIM14_1,
+ STM32F4_GPIO_REMAP_FSMC_0,
+ STM32F4_GPIO_REMAP_FSMC_1,
+ STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0,
+ STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1,
+ STM32F4_GPIO_REMAP_TIM12_0,
+ STM32F4_GPIO_REMAP_TIM12_1,
+ STM32F4_GPIO_REMAP_MISC_0,
+ STM32F4_GPIO_REMAP_MISC_1,
+} stm32f4_gpio_remap;
+
+typedef union {
+ struct {
+ uint32_t pin_first : 8;
+ uint32_t pin_last : 8;
+ uint32_t mode : 2;
+ uint32_t cnf : 2;
+ uint32_t output : 1;
+ uint32_t remap : 8;
+ uint32_t reserved : 3;
+ } fields;
+
+ uint32_t value;
+} stm32f4_gpio_config;
+
+#define STM32F4_GPIO_CONFIG_TERMINAL \
+ { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } }
+
+#endif /* STM32F4_FAMILY_F10XXX */
+
extern const stm32f4_gpio_config stm32f4_start_config_gpio [];
void stm32f4_gpio_set_clock(int pin, bool set);
void stm32f4_gpio_set_config(const stm32f4_gpio_config *config);
-#define STM32F4_GPIO_CONFIG_TERMINAL \
- { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } }
-
/**
* @brief Sets the GPIO configuration of an array terminated by
* STM32F4_GPIO_CONFIG_TERMINAL.
@@ -127,6 +255,8 @@ void stm32f4_gpio_set_output(int pin, bool set);
bool stm32f4_gpio_get_input(int pin);
+#ifdef STM32F4_FAMILY_F4XXXX
+
#define STM32F4_PIN_USART(port, idx, altfunc) \
{ \
{ \
@@ -166,6 +296,58 @@ bool stm32f4_gpio_get_input(int pin);
#define STM32F4_PIN_USART6_TX_PC6 STM32F4_PIN_USART(2, 6, STM32F4_GPIO_AF_USART6)
#define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6)
+#endif /* STM32F4_FAMILY_F4XXXX */
+#ifdef STM32F4_FAMILY_F10XXX
+
+#define STM32F4_PIN_USART_TX(port, idx, remapvalue) \
+ { \
+ { \
+ .pin_first = STM32F4_GPIO_PIN(port, idx), \
+ .pin_last = STM32F4_GPIO_PIN(port, idx), \
+ .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \
+ .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \
+ .output = 0, \
+ .remap = remapvalue \
+ } \
+ }
+
+#define STM32F4_PIN_USART_RX(port, idx, remapvalue) \
+ { \
+ { \
+ .pin_first = STM32F4_GPIO_PIN(port, idx), \
+ .pin_last = STM32F4_GPIO_PIN(port, idx), \
+ .mode = STM32F4_GPIO_MODE_INPUT, \
+ .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \
+ .output = 0, \
+ .remap = remapvalue \
+ } \
+ }
+
+#define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0, 9, STM32F4_GPIO_REMAP_USART1_0)
+#define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0)
+#define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1, 6, STM32F4_GPIO_REMAP_USART1_1)
+#define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1, 7, STM32F4_GPIO_REMAP_USART1_1)
+
+#define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0, 2, STM32F4_GPIO_REMAP_USART2_0)
+#define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0, 3, STM32F4_GPIO_REMAP_USART2_0)
+#define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3, 5, STM32F4_GPIO_REMAP_USART2_1)
+#define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3, 6, STM32F4_GPIO_REMAP_USART2_1)
+
+#define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0)
+#define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0)
+#define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1)
+#define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1)
+#define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3, 8, STM32F4_GPIO_REMAP_USART3_3)
+#define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3, 9, STM32F4_GPIO_REMAP_USART3_3)
+
+#define STM32F4_PIN_UART4_TX STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE)
+#define STM32F4_PIN_UART4_RX STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE)
+
+#define STM32F4_PIN_UART5_TX STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE)
+#define STM32F4_PIN_UART5_RX STM32F4_PIN_USART_RX(3, 2, STM32F4_GPIO_REMAP_DONT_CHANGE)
+
+#endif /* STM32F4_FAMILY_F10XXX */
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/rcc.h b/c/src/lib/libbsp/arm/stm32f4/include/rcc.h
index 7d49527..c105470 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/rcc.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/rcc.h
@@ -16,8 +16,7 @@
#define LIBBSP_ARM_STM32F4_RCC_H
#include <stdbool.h>
-
-#include <bsp/stm32f4.h>
+#include <bspopts.h>
#ifdef __cplusplus
extern "C" {
@@ -26,6 +25,7 @@ extern "C" {
#define STM32F4_RCC_INDEX(reg, idx) (((reg) << 5) | (idx))
typedef enum {
+#ifdef STM32F4_FAMILY_F4XXXX
STM32F4_RCC_OTGHS = STM32F4_RCC_INDEX(0, 29),
STM32F4_RCC_ETHMAC = STM32F4_RCC_INDEX(0, 25),
STM32F4_RCC_DMA2 = STM32F4_RCC_INDEX(0, 22),
@@ -86,6 +86,64 @@ typedef enum {
STM32F4_RCC_USART1 = STM32F4_RCC_INDEX(5, 4),
STM32F4_RCC_TIM8 = STM32F4_RCC_INDEX(5, 1),
STM32F4_RCC_TIM1 = STM32F4_RCC_INDEX(5, 0),
+#endif /* STM32F4_FAMILY_F4XXXX */
+#ifdef STM32F4_FAMILY_F10XXX
+ STM32F4_RCC_DMA1 = STM32F4_RCC_INDEX(0, 0),
+ STM32F4_RCC_DMA2 = STM32F4_RCC_INDEX(0, 1),
+ STM32F4_RCC_SRAM = STM32F4_RCC_INDEX(0, 2),
+ STM32F4_RCC_FLITF = STM32F4_RCC_INDEX(0, 4),
+ STM32F4_RCC_CRCEN = STM32F4_RCC_INDEX(0, 6),
+ STM32F4_RCC_FSMC = STM32F4_RCC_INDEX(0, 8),
+ STM32F4_RCC_SDIO = STM32F4_RCC_INDEX(0, 10),
+ STM32F4_RCC_OTGFS = STM32F4_RCC_INDEX(0, 12),
+ STM32F4_RCC_ETHMAC = STM32F4_RCC_INDEX(0, 14),
+ STM32F4_RCC_ETHMACTX = STM32F4_RCC_INDEX(0, 15),
+ STM32F4_RCC_ETHMACRX = STM32F4_RCC_INDEX(0, 16),
+
+ STM32F4_RCC_AFIO = STM32F4_RCC_INDEX(1, 0),
+ STM32F4_RCC_GPIOA = STM32F4_RCC_INDEX(1, 2),
+ STM32F4_RCC_GPIOB = STM32F4_RCC_INDEX(1, 3),
+ STM32F4_RCC_GPIOC = STM32F4_RCC_INDEX(1, 4),
+ STM32F4_RCC_GPIOD = STM32F4_RCC_INDEX(1, 5),
+ STM32F4_RCC_GPIOE = STM32F4_RCC_INDEX(1, 6),
+ STM32F4_RCC_GPIOF = STM32F4_RCC_INDEX(1, 7),
+ STM32F4_RCC_GPIOG = STM32F4_RCC_INDEX(1, 8),
+ STM32F4_RCC_ADC1 = STM32F4_RCC_INDEX(1, 9),
+ STM32F4_RCC_ADC2 = STM32F4_RCC_INDEX(1, 10),
+ STM32F4_RCC_TIM1 = STM32F4_RCC_INDEX(1, 11),
+ STM32F4_RCC_SPI1 = STM32F4_RCC_INDEX(1, 12),
+ STM32F4_RCC_TIM8 = STM32F4_RCC_INDEX(1, 13),
+ STM32F4_RCC_USART1 = STM32F4_RCC_INDEX(1, 14),
+ STM32F4_RCC_ADC3 = STM32F4_RCC_INDEX(1, 15),
+ STM32F4_RCC_TIM9 = STM32F4_RCC_INDEX(1, 19),
+ STM32F4_RCC_TIM10 = STM32F4_RCC_INDEX(1, 20),
+ STM32F4_RCC_TIM11 = STM32F4_RCC_INDEX(1, 21),
+
+ STM32F4_RCC_TIM2 = STM32F4_RCC_INDEX(2, 0),
+ STM32F4_RCC_TIM3 = STM32F4_RCC_INDEX(2, 1),
+ STM32F4_RCC_TIM4 = STM32F4_RCC_INDEX(2, 2),
+ STM32F4_RCC_TIM5 = STM32F4_RCC_INDEX(2, 3),
+ STM32F4_RCC_TIM6 = STM32F4_RCC_INDEX(2, 4),
+ STM32F4_RCC_TIM7 = STM32F4_RCC_INDEX(2, 5),
+ STM32F4_RCC_TIM12 = STM32F4_RCC_INDEX(2, 6),
+ STM32F4_RCC_TIM13 = STM32F4_RCC_INDEX(2, 7),
+ STM32F4_RCC_TIM14 = STM32F4_RCC_INDEX(2, 8),
+ STM32F4_RCC_WWDG = STM32F4_RCC_INDEX(2, 11),
+ STM32F4_RCC_SPI2 = STM32F4_RCC_INDEX(2, 14),
+ STM32F4_RCC_SPI3 = STM32F4_RCC_INDEX(2, 15),
+ STM32F4_RCC_USART2 = STM32F4_RCC_INDEX(2, 17),
+ STM32F4_RCC_USART3 = STM32F4_RCC_INDEX(2, 18),
+ STM32F4_RCC_UART4 = STM32F4_RCC_INDEX(2, 19),
+ STM32F4_RCC_UART5 = STM32F4_RCC_INDEX(2, 20),
+ STM32F4_RCC_I2C1 = STM32F4_RCC_INDEX(2, 21),
+ STM32F4_RCC_I2C2 = STM32F4_RCC_INDEX(2, 22),
+ STM32F4_RCC_USB = STM32F4_RCC_INDEX(2, 23),
+ STM32F4_RCC_CAN1 = STM32F4_RCC_INDEX(2, 24),
+ STM32F4_RCC_CAN2 = STM32F4_RCC_INDEX(2, 25),
+ STM32F4_RCC_BKP = STM32F4_RCC_INDEX(2, 27),
+ STM32F4_RCC_PWR = STM32F4_RCC_INDEX(2, 28),
+ STM32F4_RCC_DAC = STM32F4_RCC_INDEX(2, 29),
+#endif /* STM32F4_FAMILY_F10XXX */
} stm32f4_rcc_index;
void stm32f4_rcc_reset(stm32f4_rcc_index index);
@@ -94,7 +152,9 @@ void stm32f4_rcc_set_reset(stm32f4_rcc_index index, bool set);
void stm32f4_rcc_set_clock(stm32f4_rcc_index index, bool set);
+#ifdef STM32F4_FAMILY_F4XXXX
void stm32f4_rcc_set_low_power_clock(stm32f4_rcc_index index, bool set);
+#endif /* STM32F4_FAMILY_F4XXXX */
#ifdef __cplusplus
}
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32_usart.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32_usart.h
new file mode 100644
index 0000000..933171a
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32_usart.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32_USART_H
+#define LIBBSP_ARM_STM32F4_STM32_USART_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+ uint32_t sr;
+#define STM32F4_USART_SR_CTS BSP_BIT32(9)
+#define STM32F4_USART_SR_LBD BSP_BIT32(8)
+#define STM32F4_USART_SR_TXE BSP_BIT32(7)
+#define STM32F4_USART_SR_TC BSP_BIT32(6)
+#define STM32F4_USART_SR_RXNE BSP_BIT32(5)
+#define STM32F4_USART_SR_IDLE BSP_BIT32(4)
+#define STM32F4_USART_SR_ORE BSP_BIT32(3)
+#define STM32F4_USART_SR_NF BSP_BIT32(2)
+#define STM32F4_USART_SR_FE BSP_BIT32(1)
+#define STM32F4_USART_SR_PE BSP_BIT32(0)
+ uint32_t dr;
+#define STM32F4_USART_DR(val) BSP_FLD32(val, 0, 7)
+#define STM32F4_USART_DR_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define STM32F4_USART_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+ uint32_t bbr;
+#define STM32F4_USART_BBR_DIV_MANTISSA(val) BSP_FLD32(val, 4, 15)
+#define STM32F4_USART_BBR_DIV_MANTISSA_GET(reg) BSP_FLD32GET(reg, 4, 15)
+#define STM32F4_USART_BBR_DIV_MANTISSA_SET(reg, val) BSP_FLD32SET(reg, val, 4, 15)
+#define STM32F4_USART_BBR_DIV_FRACTION(val) BSP_FLD32(val, 0, 3)
+#define STM32F4_USART_BBR_DIV_FRACTION_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define STM32F4_USART_BBR_DIV_FRACTION_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+ uint32_t cr1;
+#define STM32F4_USART_CR1_OVER8 BSP_BIT32(15)
+#define STM32F4_USART_CR1_UE BSP_BIT32(13)
+#define STM32F4_USART_CR1_M BSP_BIT32(12)
+#define STM32F4_USART_CR1_WAKE BSP_BIT32(11)
+#define STM32F4_USART_CR1_PCE BSP_BIT32(10)
+#define STM32F4_USART_CR1_PS BSP_BIT32(9)
+#define STM32F4_USART_CR1_PEIE BSP_BIT32(8)
+#define STM32F4_USART_CR1_TXEIE BSP_BIT32(7)
+#define STM32F4_USART_CR1_TCIE BSP_BIT32(6)
+#define STM32F4_USART_CR1_RXNEIE BSP_BIT32(5)
+#define STM32F4_USART_CR1_IDLEIE BSP_BIT32(4)
+#define STM32F4_USART_CR1_TE BSP_BIT32(3)
+#define STM32F4_USART_CR1_RE BSP_BIT32(2)
+#define STM32F4_USART_CR1_RWU BSP_BIT32(1)
+#define STM32F4_USART_CR1_SBK BSP_BIT32(0)
+ uint32_t cr2;
+#define STM32F4_USART_CR2_LINEN BSP_BIT32(14)
+#define STM32F4_USART_CR2_STOP(val) BSP_FLD32(val, 12, 13)
+#define STM32F4_USART_CR2_STOP_GET(reg) BSP_FLD32GET(reg, 12, 13)
+#define STM32F4_USART_CR2_STOP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
+#define STM32F4_USART_CR2_CLKEN BSP_BIT32(11)
+#define STM32F4_USART_CR2_CPOL BSP_BIT32(10)
+#define STM32F4_USART_CR2_CPHA BSP_BIT32(9)
+#define STM32F4_USART_CR2_LBCL BSP_BIT32(8)
+#define STM32F4_USART_CR2_LBDIE BSP_BIT32(6)
+#define STM32F4_USART_CR2_LBDL BSP_BIT32(5)
+#define STM32F4_USART_CR2_ADD(val) BSP_FLD32(val, 0, 3)
+#define STM32F4_USART_CR2_ADD_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define STM32F4_USART_CR2_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+ uint32_t cr3;
+#define STM32F4_USART_CR3_ONEBIT BSP_BIT32(11)
+#define STM32F4_USART_CR3_CTSIE BSP_BIT32(10)
+#define STM32F4_USART_CR3_CTSE BSP_BIT32(9)
+#define STM32F4_USART_CR3_RTSE BSP_BIT32(8)
+#define STM32F4_USART_CR3_DMAT BSP_BIT32(7)
+#define STM32F4_USART_CR3_DMAR BSP_BIT32(6)
+#define STM32F4_USART_CR3_SCEN BSP_BIT32(5)
+#define STM32F4_USART_CR3_NACK BSP_BIT32(4)
+#define STM32F4_USART_CR3_HDSEL BSP_BIT32(3)
+#define STM32F4_USART_CR3_IRLP BSP_BIT32(2)
+#define STM32F4_USART_CR3_IREN BSP_BIT32(1)
+#define STM32F4_USART_CR3_EIE BSP_BIT32(0)
+ uint32_t gtpr;
+#define STM32F4_USART_GTPR_GT(val) BSP_FLD32(val, 8, 15)
+#define STM32F4_USART_GTPR_GT_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define STM32F4_USART_GTPR_GT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define STM32F4_USART_GTPR_PSC(val) BSP_FLD32(val, 0, 7)
+#define STM32F4_USART_GTPR_PSC_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define STM32F4_USART_GTPR_PSC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+} stm32f4_usart;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32_USART_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_gpio.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_gpio.h
new file mode 100644
index 0000000..a2742bf
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_gpio.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2013 Christian Mauderer. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H
+#define LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+ uint32_t cr[2];
+ uint32_t idr;
+ uint32_t odr;
+ uint32_t bsrr;
+ uint32_t brr;
+ uint32_t lckr;
+} stm32f4_gpio;
+
+typedef struct {
+ uint32_t evcr;
+ uint32_t mapr;
+ uint32_t exticr[4];
+ uint32_t mapr2;
+} stm32f4_afio;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_rcc.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_rcc.h
new file mode 100644
index 0000000..75b3081
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_rcc.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2013 Christian Mauderer. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H
+#define LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+ uint32_t cr;
+ uint32_t cfgr;
+ uint32_t cir;
+ uint32_t apbrstr [2];
+ uint32_t ahbenr [1];
+ uint32_t apbenr [2];
+ uint32_t bdcr;
+ uint32_t csr;
+ uint32_t ahbstr;
+ uint32_t cfgr2;
+} stm32f4_rcc;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
index b07933f..37547fc 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
@@ -16,125 +16,19 @@
#define LIBBSP_ARM_STM32F4_STM32F4_H
#include <bsp/utility.h>
+#include <bspopts.h>
#define STM32F4_BASE 0x00
-typedef struct {
- uint32_t moder;
- uint32_t otyper;
- uint32_t ospeedr;
- uint32_t pupdr;
- uint32_t idr;
- uint32_t odr;
- uint32_t bsrr;
- uint32_t lckr;
- uint32_t afr [2];
- uint32_t reserved_28 [246];
-} stm32f4_gpio;
+#ifdef STM32F4_FAMILY_F4XXXX
+#include <bsp/stm32f4xxxx_gpio.h>
#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40020000) + (i))
-typedef struct {
- uint32_t cr;
- uint32_t pllcfgr;
- uint32_t cfgr;
- uint32_t cir;
- uint32_t ahbrstr [3];
- uint32_t reserved_1c;
- uint32_t apbrstr [2];
- uint32_t reserved_28 [2];
- uint32_t ahbenr [3];
- uint32_t reserved_3c;
- uint32_t apbenr [2];
- uint32_t reserved_48 [2];
- uint32_t ahblpenr [3];
- uint32_t reserved_5c;
- uint32_t apblpenr [2];
- uint32_t reserved_68 [2];
- uint32_t bdcr;
- uint32_t csr;
- uint32_t reserved_78 [2];
- uint32_t sscgr;
- uint32_t plli2scfgr;
-} stm32f4_rcc;
-
+#include <bsp/stm32f4xxxx_rcc.h>
#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_BASE + 0x40023800))
-typedef struct {
- uint32_t sr;
-#define STM32F4_USART_SR_CTS BSP_BIT32(9)
-#define STM32F4_USART_SR_LBD BSP_BIT32(8)
-#define STM32F4_USART_SR_TXE BSP_BIT32(7)
-#define STM32F4_USART_SR_TC BSP_BIT32(6)
-#define STM32F4_USART_SR_RXNE BSP_BIT32(5)
-#define STM32F4_USART_SR_IDLE BSP_BIT32(4)
-#define STM32F4_USART_SR_ORE BSP_BIT32(3)
-#define STM32F4_USART_SR_NF BSP_BIT32(2)
-#define STM32F4_USART_SR_FE BSP_BIT32(1)
-#define STM32F4_USART_SR_PE BSP_BIT32(0)
- uint32_t dr;
-#define STM32F4_USART_DR(val) BSP_FLD32(val, 0, 7)
-#define STM32F4_USART_DR_GET(reg) BSP_FLD32GET(reg, 0, 7)
-#define STM32F4_USART_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
- uint32_t bbr;
-#define STM32F4_USART_BBR_DIV_MANTISSA(val) BSP_FLD32(val, 4, 15)
-#define STM32F4_USART_BBR_DIV_MANTISSA_GET(reg) BSP_FLD32GET(reg, 4, 15)
-#define STM32F4_USART_BBR_DIV_MANTISSA_SET(reg, val) BSP_FLD32SET(reg, val, 4, 15)
-#define STM32F4_USART_BBR_DIV_FRACTION(val) BSP_FLD32(val, 0, 3)
-#define STM32F4_USART_BBR_DIV_FRACTION_GET(reg) BSP_FLD32GET(reg, 0, 3)
-#define STM32F4_USART_BBR_DIV_FRACTION_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
- uint32_t cr1;
-#define STM32F4_USART_CR1_OVER8 BSP_BIT32(15)
-#define STM32F4_USART_CR1_UE BSP_BIT32(13)
-#define STM32F4_USART_CR1_M BSP_BIT32(12)
-#define STM32F4_USART_CR1_WAKE BSP_BIT32(11)
-#define STM32F4_USART_CR1_PCE BSP_BIT32(10)
-#define STM32F4_USART_CR1_PS BSP_BIT32(9)
-#define STM32F4_USART_CR1_PEIE BSP_BIT32(8)
-#define STM32F4_USART_CR1_TXEIE BSP_BIT32(7)
-#define STM32F4_USART_CR1_TCIE BSP_BIT32(6)
-#define STM32F4_USART_CR1_RXNEIE BSP_BIT32(5)
-#define STM32F4_USART_CR1_IDLEIE BSP_BIT32(4)
-#define STM32F4_USART_CR1_TE BSP_BIT32(3)
-#define STM32F4_USART_CR1_RE BSP_BIT32(2)
-#define STM32F4_USART_CR1_RWU BSP_BIT32(1)
-#define STM32F4_USART_CR1_SBK BSP_BIT32(0)
- uint32_t cr2;
-#define STM32F4_USART_CR2_LINEN BSP_BIT32(14)
-#define STM32F4_USART_CR2_STOP(val) BSP_FLD32(val, 12, 13)
-#define STM32F4_USART_CR2_STOP_GET(reg) BSP_FLD32GET(reg, 12, 13)
-#define STM32F4_USART_CR2_STOP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
-#define STM32F4_USART_CR2_CLKEN BSP_BIT32(11)
-#define STM32F4_USART_CR2_CPOL BSP_BIT32(10)
-#define STM32F4_USART_CR2_CPHA BSP_BIT32(9)
-#define STM32F4_USART_CR2_LBCL BSP_BIT32(8)
-#define STM32F4_USART_CR2_LBDIE BSP_BIT32(6)
-#define STM32F4_USART_CR2_LBDL BSP_BIT32(5)
-#define STM32F4_USART_CR2_ADD(val) BSP_FLD32(val, 0, 3)
-#define STM32F4_USART_CR2_ADD_GET(reg) BSP_FLD32GET(reg, 0, 3)
-#define STM32F4_USART_CR2_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
- uint32_t cr3;
-#define STM32F4_USART_CR3_ONEBIT BSP_BIT32(11)
-#define STM32F4_USART_CR3_CTSIE BSP_BIT32(10)
-#define STM32F4_USART_CR3_CTSE BSP_BIT32(9)
-#define STM32F4_USART_CR3_RTSE BSP_BIT32(8)
-#define STM32F4_USART_CR3_DMAT BSP_BIT32(7)
-#define STM32F4_USART_CR3_DMAR BSP_BIT32(6)
-#define STM32F4_USART_CR3_SCEN BSP_BIT32(5)
-#define STM32F4_USART_CR3_NACK BSP_BIT32(4)
-#define STM32F4_USART_CR3_HDSEL BSP_BIT32(3)
-#define STM32F4_USART_CR3_IRLP BSP_BIT32(2)
-#define STM32F4_USART_CR3_IREN BSP_BIT32(1)
-#define STM32F4_USART_CR3_EIE BSP_BIT32(0)
- uint32_t gtpr;
-#define STM32F4_USART_GTPR_GT(val) BSP_FLD32(val, 8, 15)
-#define STM32F4_USART_GTPR_GT_GET(reg) BSP_FLD32GET(reg, 8, 15)
-#define STM32F4_USART_GTPR_GT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
-#define STM32F4_USART_GTPR_PSC(val) BSP_FLD32(val, 0, 7)
-#define STM32F4_USART_GTPR_PSC_GET(reg) BSP_FLD32GET(reg, 0, 7)
-#define STM32F4_USART_GTPR_PSC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
-} stm32f4_usart;
-
+#include <bsp/stm32_usart.h>
#define STM32F4_USART_1 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011000))
#define STM32F4_USART_2 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400))
#define STM32F4_USART_3 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800))
@@ -142,25 +36,24 @@ typedef struct {
#define STM32F4_USART_5 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000))
#define STM32F4_USART_6 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011400))
-typedef struct {
- uint32_t reserved_00 [268439808];
- stm32f4_usart usart_2;
- uint32_t reserved_4000441c [249];
- stm32f4_usart usart_3;
- uint32_t reserved_4000481c [249];
- stm32f4_usart usart_4;
- uint32_t reserved_40004c1c [249];
- stm32f4_usart usart_5;
- uint32_t reserved_4000501c [12281];
- stm32f4_usart usart_1;
- uint32_t reserved_4001101c [249];
- stm32f4_usart usart_6;
- uint32_t reserved_4001141c [15097];
- stm32f4_gpio gpio [9];
- uint32_t reserved_40022400 [1280];
- stm32f4_rcc rcc;
-} stm32f4;
+#endif /* STM32F4_FAMILY_F4XXXX */
+
+#ifdef STM32F4_FAMILY_F10XXX
+
+#include <bsp/stm32f10xxx_gpio.h>
+#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40010800 + i * 0x400))
+#define STM32F4_AFIO ((volatile stm32f4_afio *) (STM32F4_BASE + 0x40010000))
+
+#include <bsp/stm32f10xxx_rcc.h>
+#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_BASE + 0x40021000))
+
+#include <bsp/stm32_usart.h>
+#define STM32F4_USART_1 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40013800))
+#define STM32F4_USART_2 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400))
+#define STM32F4_USART_3 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800))
+#define STM32F4_USART_4 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00))
+#define STM32F4_USART_5 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000))
-#define STM32F4 (*(volatile stm32f4 *) (STM32F4_BASE))
+#endif /* STM32F4_FAMILY_F10XXX */
#endif /* LIBBSP_ARM_STM32F4_STM32F4_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_gpio.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_gpio.h
new file mode 100644
index 0000000..b421a8e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_gpio.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H
+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t idr;
+ uint32_t odr;
+ uint32_t bsrr;
+ uint32_t lckr;
+ uint32_t afr [2];
+ uint32_t reserved_28 [246];
+} stm32f4_gpio;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h
new file mode 100644
index 0000000..61e8d5f
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H
+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+ uint32_t cr;
+ uint32_t pllcfgr;
+ uint32_t cfgr;
+ uint32_t cir;
+ uint32_t ahbrstr [3];
+ uint32_t reserved_1c;
+ uint32_t apbrstr [2];
+ uint32_t reserved_28 [2];
+ uint32_t ahbenr [3];
+ uint32_t reserved_3c;
+ uint32_t apbenr [2];
+ uint32_t reserved_48 [2];
+ uint32_t ahblpenr [3];
+ uint32_t reserved_5c;
+ uint32_t apblpenr [2];
+ uint32_t reserved_68 [2];
+ uint32_t bdcr;
+ uint32_t csr;
+ uint32_t reserved_78 [2];
+ uint32_t sscgr;
+ uint32_t plli2scfgr;
+} stm32f4_rcc;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f105rc.cfg b/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f105rc.cfg
new file mode 100644
index 0000000..b0a522e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f105rc.cfg
@@ -0,0 +1 @@
+include $(RTEMS_ROOT)/make/custom/stm32f4.cfg
diff --git a/c/src/lib/libbsp/arm/stm32f4/preinstall.am b/c/src/lib/libbsp/arm/stm32f4/preinstall.am
index 130079b..388d510 100644
--- a/c/src/lib/libbsp/arm/stm32f4/preinstall.am
+++ b/c/src/lib/libbsp/arm/stm32f4/preinstall.am
@@ -105,6 +105,26 @@ $(PROJECT_INCLUDE)/bsp/stm32f4.h: include/stm32f4.h $(PROJECT_INCLUDE)/bsp/$(dir
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4.h
+$(PROJECT_INCLUDE)/bsp/stm32f10xxx_gpio.h: include/stm32f10xxx_gpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f10xxx_gpio.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f10xxx_gpio.h
+
+$(PROJECT_INCLUDE)/bsp/stm32f10xxx_rcc.h: include/stm32f10xxx_rcc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f10xxx_rcc.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f10xxx_rcc.h
+
+$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h: include/stm32f4xxxx_gpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h
+
+$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h: include/stm32f4xxxx_rcc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h
+
+$(PROJECT_INCLUDE)/bsp/stm32_usart.h: include/stm32_usart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32_usart.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32_usart.h
+
$(PROJECT_INCLUDE)/bsp/io.h: include/io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/io.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/io.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/io.c b/c/src/lib/libbsp/arm/stm32f4/startup/io.c
index 5ecbabe..b067823 100644
--- a/c/src/lib/libbsp/arm/stm32f4/startup/io.c
+++ b/c/src/lib/libbsp/arm/stm32f4/startup/io.c
@@ -14,6 +14,7 @@
#include <bsp/io.h>
#include <bsp/rcc.h>
+#include <bsp/stm32f4.h>
#include <rtems.h>
@@ -44,15 +45,139 @@ static void clear_and_set(
*reg = val;
}
+#ifdef STM32F4_FAMILY_F10XXX
+#define STM32F4_AFIO_REMAP_ENTRY(mod, afio_reg_v, start_v, width_v, value_v) \
+ [mod] = { \
+ .afio_reg = afio_reg_v, \
+ .start = start_v, \
+ .width = width_v, \
+ .value = value_v, \
+ .reserved = 0 \
+ }
+
+typedef struct {
+ uint16_t afio_reg : 3;
+ uint16_t start : 5;
+ uint16_t width : 2;
+ uint16_t value : 3;
+ uint16_t reserved : 3;
+} stm32f4_afio_remap_entry;
+
+static const stm32f4_afio_remap_entry stm32f4_afio_remap_table [] = {
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_DONT_CHANGE, 0, 0, 0, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI1_0, 1, 0, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI1_1, 1, 0, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_I2C1_0, 1, 1, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_I2C1_1, 1, 1, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART1_0, 1, 2, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART1_1, 1, 2, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART2_0, 1, 3, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART2_1, 1, 3, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_0, 1, 4, 2, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_1, 1, 4, 2, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_3, 1, 4, 2, 3),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_0, 1, 6, 2, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_1, 1, 6, 2, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_3, 1, 6, 2, 3),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_0, 1, 8, 2, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_1, 1, 8, 2, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_2, 1, 8, 2, 2),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_3, 1, 8, 2, 3),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_0, 1, 10, 2, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_2, 1, 10, 2, 2),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_3, 1, 10, 2, 3),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM4_0, 1, 12, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM4_1, 1, 12, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_0, 1, 13, 2, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_2, 1, 13, 2, 2),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_3, 1, 13, 2, 3),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PD01_0, 1, 15, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PD01_1, 1, 15, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM5CH4_0, 1, 16, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM5CH4_1, 1, 16, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0, 1, 17, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1, 1, 17, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGREG_0, 1, 18, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGREG_1, 1, 18, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0, 1, 19, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1, 1, 19, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGREG_0, 1, 20, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGREG_1, 1, 20, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ETH_0, 1, 21, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ETH_1, 1, 21, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN2_0, 1, 22, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN2_1, 1, 22, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MII_RMII_0, 1, 23, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MII_RMII_1, 1, 23, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_0, 1, 24, 3, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_1, 1, 24, 3, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_2, 1, 24, 3, 2),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_4, 1, 24, 3, 4),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI3_0, 1, 28, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI3_1, 1, 28, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2ITR1_0, 1, 29, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2ITR1_1, 1, 29, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PTP_PPS_0, 1, 30, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PTP_PPS_1, 1, 30, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM15_0, 6, 0, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM15_1, 6, 0, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM16_0, 6, 1, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM16_1, 6, 1, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM17_0, 6, 2, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM17_1, 6, 2, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CEC_0, 6, 3, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CEC_1, 6, 3, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_DMA_0, 6, 4, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_DMA_1, 6, 4, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM9_0, 6, 5, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM9_1, 6, 5, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM10_0, 6, 6, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM10_1, 6, 6, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM11_0, 6, 7, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM11_1, 6, 7, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM13_0, 6, 8, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM13_1, 6, 8, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM14_0, 6, 9, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM14_1, 6, 9, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_FSMC_0, 6, 10, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_FSMC_1, 6, 10, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0, 6, 11, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1, 6, 11, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM12_0, 6, 12, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM12_1, 6, 12, 1, 1),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MISC_0, 6, 13, 1, 0),
+ STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MISC_1, 6, 13, 1, 1),
+};
+
+static void set_remap_config(stm32f4_gpio_remap remap)
+{
+ if(remap != STM32F4_GPIO_REMAP_DONT_CHANGE)
+ {
+ stm32f4_afio_remap_entry entry = stm32f4_afio_remap_table[remap];
+ volatile stm32f4_afio *afio = STM32F4_AFIO;
+ volatile uint32_t *reg = ((uint32_t*) afio) + entry.afio_reg;
+ uint32_t mask = (1 << entry.width) - 1;
+ uint32_t value = *reg;
+
+ value &= mask << entry.start;
+ value |= entry.value << entry.start;
+
+ *reg = value;
+ }
+}
+
+#endif /* STM32F4_FAMILY_F10XXX */
+
static void set_config(unsigned pin, const stm32f4_gpio_config *config)
{
unsigned port = STM32F4_GPIO_PORT_OF_PIN(pin);
volatile stm32f4_gpio *gpio = STM32F4_GPIO(port);
unsigned index = STM32F4_GPIO_INDEX_OF_PIN(pin);
+ rtems_interrupt_level level;
+ int set_or_clear_offset = config->fields.output ? 0 : 16;
+#ifdef STM32F4_FAMILY_F4XXXX
unsigned af_reg = index >> 3;
unsigned af_index = index & 0x7;
- int set_or_clear_offset = config->fields.output ? 0 : 16;
- rtems_interrupt_level level;
rtems_interrupt_disable(level);
gpio->bsrr = 1U << (index + set_or_clear_offset);
@@ -62,6 +187,20 @@ static void set_config(unsigned pin, const stm32f4_gpio_config *config)
clear_and_set(&gpio->afr [af_reg], af_index, 4, config->fields.af);
clear_and_set(&gpio->moder, index, 2, config->fields.mode);
rtems_interrupt_enable(level);
+
+#endif /* STM32F4_FAMILY_F4XXXX */
+#ifdef STM32F4_FAMILY_F10XXX
+ unsigned cr_reg = index >> 3;
+ unsigned cr_index = index & 3;
+
+ rtems_interrupt_disable(level);
+ gpio->bsrr = 1U << (index + set_or_clear_offset);
+ clear_and_set(&gpio->cr[cr_reg], cr_index, 4,
+ (config->fields.cnf << 2) | config->fields.mode);
+ set_remap_config(config->fields.remap);
+ rtems_interrupt_enable(level);
+
+#endif /* STM32F4_FAMILY_F10XXX */
}
void stm32f4_gpio_set_config(const stm32f4_gpio_config *config)
@@ -69,6 +208,10 @@ void stm32f4_gpio_set_config(const stm32f4_gpio_config *config)
int current = config->fields.pin_first;
int last = config->fields.pin_last;
+#ifdef STM32F4_FAMILY_F10XXX
+ stm32f4_rcc_set_clock(STM32F4_RCC_AFIO, true);
+#endif /* STM32F4_FAMILY_F10XXX */
+
while (current <= last) {
stm32f4_gpio_set_clock(current, true);
set_config(current, config);
diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/linkcmds.stm32f105rc b/c/src/lib/libbsp/arm/stm32f4/startup/linkcmds.stm32f105rc
new file mode 100644
index 0000000..58e8094
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/startup/linkcmds.stm32f105rc
@@ -0,0 +1,22 @@
+MEMORY {
+ RAM_INT : ORIGIN = 0x20000000, LENGTH = 64k
+ ROM_INT : ORIGIN = 0x00000000, LENGTH = 256k
+}
+
+REGION_ALIAS ("REGION_START", ROM_INT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", ROM_INT);
+REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_RODATA", ROM_INT);
+REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_DATA", RAM_INT);
+REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_BSS", RAM_INT);
+REGION_ALIAS ("REGION_WORK", RAM_INT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+
+INCLUDE linkcmds.armv7m
diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c b/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
index b2cbadf..a5f3f79 100644
--- a/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
+++ b/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
@@ -13,6 +13,7 @@
*/
#include <bsp/rcc.h>
+#include <bsp/stm32f4.h>
#include <rtems.h>
@@ -49,7 +50,13 @@ void stm32f4_rcc_set_reset(stm32f4_rcc_index index, bool set)
{
volatile stm32f4_rcc *rcc = STM32F4_RCC;
+#ifdef STM32F4_FAMILY_F4XXXX
rcc_set(index, set, &rcc->ahbrstr [0]);
+#endif/* STM32F4_FAMILY_F4XXXX */
+#ifdef STM32F4_FAMILY_F10XXX
+ /* The first register is missing for the reset-block */
+ rcc_set(index, set, &rcc->cir);
+#endif /* STM32F4_FAMILY_F10XXX */
}
void stm32f4_rcc_set_clock(stm32f4_rcc_index index, bool set)
@@ -59,9 +66,11 @@ void stm32f4_rcc_set_clock(stm32f4_rcc_index index, bool set)
rcc_set(index, set, &rcc->ahbenr [0]);
}
+#ifdef STM32F4_FAMILY_F4XXXX
void stm32f4_rcc_set_low_power_clock(stm32f4_rcc_index index, bool set)
{
volatile stm32f4_rcc *rcc = STM32F4_RCC;
rcc_set(index, set, &rcc->ahblpenr [0]);
}
+#endif /* STM32F4_FAMILY_F4XXXX */
diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/start-config-io.c b/c/src/lib/libbsp/arm/stm32f4/startup/start-config-io.c
index 2cd542c..2ec8635 100644
--- a/c/src/lib/libbsp/arm/stm32f4/startup/start-config-io.c
+++ b/c/src/lib/libbsp/arm/stm32f4/startup/start-config-io.c
@@ -16,6 +16,7 @@
#include <bsp.h>
const stm32f4_gpio_config stm32f4_start_config_gpio [] = {
+#ifdef STM32F4_FAMILY_F4XXXX
#ifdef STM32F4_ENABLE_USART_1
STM32F4_PIN_USART1_TX_PA9,
STM32F4_PIN_USART1_RX_PA10,
@@ -40,5 +41,28 @@ const stm32f4_gpio_config stm32f4_start_config_gpio [] = {
STM32F4_PIN_USART6_TX_PC6,
STM32F4_PIN_USART6_RX_PC7,
#endif
+#endif /* STM32F4_FAMILY_F4XXXX */
+#ifdef STM32F4_FAMILY_F10XXX
+ #ifdef STM32F4_ENABLE_USART_1
+ STM32F4_PIN_USART1_TX_MAP_0,
+ STM32F4_PIN_USART1_RX_MAP_0,
+ #endif
+ #ifdef STM32F4_ENABLE_USART_2
+ STM32F4_PIN_USART2_TX_MAP_0,
+ STM32F4_PIN_USART2_RX_MAP_0,
+ #endif
+ #ifdef STM32F4_ENABLE_USART_3
+ STM32F4_PIN_USART3_TX_MAP_0,
+ STM32F4_PIN_USART3_RX_MAP_0,
+ #endif
+ #ifdef STM32F4_ENABLE_UART_4
+ STM32F4_PIN_UART4_TX,
+ STM32F4_PIN_UART4_RX,
+ #endif
+ #ifdef STM32F4_ENABLE_UART_5
+ STM32F4_PIN_UART5_TX,
+ STM32F4_PIN_UART5_RX,
+ #endif
+#endif /* STM32F4_FAMILY_F10XXX */
STM32F4_GPIO_CONFIG_TERMINAL
};
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