From sebh at rtems.org Tue Aug 5 08:05:21 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 05 Aug 2014 03:05:21 -0500 Subject: [rtems commit] rbtree: Add and use RBTree_Compare_result Message-ID: <20140805080521.6750870008C@git.rtems.org> Module: rtems Branch: master Commit: 60fe374247eba365afb7f1a7055298af575434c7 Changeset: http://git.rtems.org/rtems/commit/?id=60fe374247eba365afb7f1a7055298af575434c7 Author: Sebastian Huber Date: Sun Aug 3 13:02:58 2014 +0200 rbtree: Add and use RBTree_Compare_result --- cpukit/posix/include/rtems/posix/keyimpl.h | 2 +- cpukit/posix/src/key.c | 4 +- cpukit/sapi/include/rtems/rbheap.h | 1 - cpukit/sapi/include/rtems/rbtree.h | 9 ++- cpukit/sapi/src/rbheap.c | 72 +++++++++++--------- cpukit/score/include/rtems/score/rbtree.h | 11 +++- cpukit/score/include/rtems/score/rbtreeimpl.h | 8 ++- .../score/include/rtems/score/scheduleredfimpl.h | 2 +- cpukit/score/include/rtems/score/threadqimpl.h | 2 +- cpukit/score/src/rbtreefind.c | 4 +- cpukit/score/src/rbtreeinsert.c | 13 +++- cpukit/score/src/scheduleredf.c | 2 +- cpukit/score/src/threadq.c | 2 +- testsuites/libtests/rbheap01/init.c | 17 ----- testsuites/sptests/sprbtree01/init.c | 2 +- 15 files changed, 83 insertions(+), 68 deletions(-) diff --git a/cpukit/posix/include/rtems/posix/keyimpl.h b/cpukit/posix/include/rtems/posix/keyimpl.h index aff9749..ded030d 100644 --- a/cpukit/posix/include/rtems/posix/keyimpl.h +++ b/cpukit/posix/include/rtems/posix/keyimpl.h @@ -64,7 +64,7 @@ void _POSIX_Key_Manager_initialization(void); * * This routine compares the rbtree node */ -int _POSIX_Keys_Key_value_compare( +RBTree_Compare_result _POSIX_Keys_Key_value_compare( const RBTree_Node *node1, const RBTree_Node *node2 ); diff --git a/cpukit/posix/src/key.c b/cpukit/posix/src/key.c index e231299..67c6e27 100644 --- a/cpukit/posix/src/key.c +++ b/cpukit/posix/src/key.c @@ -44,7 +44,7 @@ RBTREE_DEFINE_EMPTY( _POSIX_Keys_Key_value_lookup_tree ); * impossible */ -int _POSIX_Keys_Key_value_compare( +RBTree_Compare_result _POSIX_Keys_Key_value_compare( const RBTree_Node *node1, const RBTree_Node *node2 ) @@ -52,7 +52,7 @@ int _POSIX_Keys_Key_value_compare( POSIX_Keys_Key_value_pair *n1; POSIX_Keys_Key_value_pair *n2; Objects_Id thread_id1, thread_id2; - int diff; + RBTree_Compare_result diff; n1 = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node1 ); n2 = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node2 ); diff --git a/cpukit/sapi/include/rtems/rbheap.h b/cpukit/sapi/include/rtems/rbheap.h index 0848b69..c008721 100644 --- a/cpukit/sapi/include/rtems/rbheap.h +++ b/cpukit/sapi/include/rtems/rbheap.h @@ -154,7 +154,6 @@ struct rtems_rbheap_control { * @param[in] handler_arg The handler argument. * * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_INVALID_NUMBER The alignment is not positive. * @retval RTEMS_INVALID_ADDRESS The memory area is invalid. * @retval RTEMS_NO_MEMORY Not enough chunk descriptors. */ diff --git a/cpukit/sapi/include/rtems/rbtree.h b/cpukit/sapi/include/rtems/rbtree.h index eaf2b6e..0e2ea2c 100644 --- a/cpukit/sapi/include/rtems/rbtree.h +++ b/cpukit/sapi/include/rtems/rbtree.h @@ -55,9 +55,12 @@ typedef RBTree_Node rtems_rbtree_node; typedef RBTree_Control rtems_rbtree_control; /** - * This type defines function pointers for user-provided comparison - * function. The function compares two nodes in order to determine - * the order in a red-black tree. + * @copydoc RBTree_Compare_result + */ +typedef RBTree_Compare_result rtems_rbtree_compare_result; + +/** + * @copydoc RBTree_Compare */ typedef RBTree_Compare rtems_rbtree_compare; diff --git a/cpukit/sapi/src/rbheap.c b/cpukit/sapi/src/rbheap.c index 20338eb..049a64d 100644 --- a/cpukit/sapi/src/rbheap.c +++ b/cpukit/sapi/src/rbheap.c @@ -46,12 +46,16 @@ static uintptr_t align_down(uintptr_t alignment, uintptr_t value) return value - excess; } -static int chunk_compare(const rtems_rbtree_node *a, const rtems_rbtree_node *b) +static rtems_rbtree_compare_result chunk_compare( + const rtems_rbtree_node *a, + const rtems_rbtree_node *b +) { const rtems_rbheap_chunk *left = rtems_rbheap_chunk_of_node(a); const rtems_rbheap_chunk *right = rtems_rbheap_chunk_of_node(b); - return (int) (left->begin - right->begin); + return (rtems_rbtree_compare_result) + ((left->begin >> 1) - (right->begin >> 1)); } static rtems_rbheap_chunk *get_chunk(rtems_rbheap_control *control) @@ -93,39 +97,43 @@ rtems_status_code rtems_rbheap_initialize( ) { rtems_status_code sc = RTEMS_SUCCESSFUL; + uintptr_t begin = (uintptr_t) area_begin; + uintptr_t end = begin + area_size; + uintptr_t aligned_begin; + uintptr_t aligned_end; - if (alignment > 0) { - uintptr_t begin = (uintptr_t) area_begin; - uintptr_t end = begin + area_size; - uintptr_t aligned_begin = align_up(alignment, begin); - uintptr_t aligned_end = align_down(alignment, end); - - if (begin < end && begin <= aligned_begin && aligned_begin < aligned_end) { - rtems_chain_control *free_chain = &control->free_chunk_chain; - rtems_rbtree_control *chunk_tree = &control->chunk_tree; - rtems_rbheap_chunk *first = NULL; - - rtems_chain_initialize_empty(free_chain); - rtems_chain_initialize_empty(&control->spare_descriptor_chain); - rtems_rbtree_initialize_empty(chunk_tree); - control->alignment = alignment; - control->handler_arg = handler_arg; - control->extend_descriptors = extend_descriptors; - - first = get_chunk(control); - if (first != NULL) { - first->begin = aligned_begin; - first->size = aligned_end - aligned_begin; - add_to_chain(free_chain, first); - insert_into_tree(chunk_tree, first); - } else { - sc = RTEMS_NO_MEMORY; - } + /* + * Ensure that the alignment is at least two, so that we can keep + * chunk_compare() that simple. + */ + alignment = alignment < 2 ? 2 : alignment; + + aligned_begin = align_up(alignment, begin); + aligned_end = align_down(alignment, end); + + if (begin < end && begin <= aligned_begin && aligned_begin < aligned_end) { + rtems_chain_control *free_chain = &control->free_chunk_chain; + rtems_rbtree_control *chunk_tree = &control->chunk_tree; + rtems_rbheap_chunk *first = NULL; + + rtems_chain_initialize_empty(free_chain); + rtems_chain_initialize_empty(&control->spare_descriptor_chain); + rtems_rbtree_initialize_empty(chunk_tree); + control->alignment = alignment; + control->handler_arg = handler_arg; + control->extend_descriptors = extend_descriptors; + + first = get_chunk(control); + if (first != NULL) { + first->begin = aligned_begin; + first->size = aligned_end - aligned_begin; + add_to_chain(free_chain, first); + insert_into_tree(chunk_tree, first); } else { - sc = RTEMS_INVALID_ADDRESS; + sc = RTEMS_NO_MEMORY; } } else { - sc = RTEMS_INVALID_NUMBER; + sc = RTEMS_INVALID_ADDRESS; } return sc; diff --git a/cpukit/score/include/rtems/score/rbtree.h b/cpukit/score/include/rtems/score/rbtree.h index d23808f..aa84558 100644 --- a/cpukit/score/include/rtems/score/rbtree.h +++ b/cpukit/score/include/rtems/score/rbtree.h @@ -90,6 +90,15 @@ typedef enum { } RBTree_Direction; /** + * @brief Integer type for compare results. + * + * The type is large enough to represent pointers and 32-bit signed integers. + * + * @see RBTree_Compare. + */ +typedef long RBTree_Compare_result; + +/** * @brief Compares two red-black tree nodes. * * @param[in] first The first node. @@ -102,7 +111,7 @@ typedef enum { * @retval negative The key value of the first node is less than the one of the * second node. */ -typedef int ( *RBTree_Compare )( +typedef RBTree_Compare_result ( *RBTree_Compare )( const RBTree_Node *first, const RBTree_Node *second ); diff --git a/cpukit/score/include/rtems/score/rbtreeimpl.h b/cpukit/score/include/rtems/score/rbtreeimpl.h index f3af7fe..451b5f4 100644 --- a/cpukit/score/include/rtems/score/rbtreeimpl.h +++ b/cpukit/score/include/rtems/score/rbtreeimpl.h @@ -144,20 +144,22 @@ RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Parent_sibling( return _RBTree_Sibling(the_node->parent); } -RTEMS_INLINE_ROUTINE bool _RBTree_Is_equal( int compare_result ) +RTEMS_INLINE_ROUTINE bool _RBTree_Is_equal( + RBTree_Compare_result compare_result +) { return compare_result == 0; } RTEMS_INLINE_ROUTINE bool _RBTree_Is_greater( - int compare_result + RBTree_Compare_result compare_result ) { return compare_result > 0; } RTEMS_INLINE_ROUTINE bool _RBTree_Is_lesser( - int compare_result + RBTree_Compare_result compare_result ) { return compare_result < 0; diff --git a/cpukit/score/include/rtems/score/scheduleredfimpl.h b/cpukit/score/include/rtems/score/scheduleredfimpl.h index 50e40bc..a98fb0f 100644 --- a/cpukit/score/include/rtems/score/scheduleredfimpl.h +++ b/cpukit/score/include/rtems/score/scheduleredfimpl.h @@ -44,7 +44,7 @@ RTEMS_INLINE_ROUTINE Scheduler_EDF_Node *_Scheduler_EDF_Thread_get_node( return (Scheduler_EDF_Node *) _Scheduler_Thread_get_node( the_thread ); } -int _Scheduler_EDF_Compare( +RBTree_Compare_result _Scheduler_EDF_Compare( const RBTree_Node* n1, const RBTree_Node* n2 ); diff --git a/cpukit/score/include/rtems/score/threadqimpl.h b/cpukit/score/include/rtems/score/threadqimpl.h index 0e139cd..5931d22 100644 --- a/cpukit/score/include/rtems/score/threadqimpl.h +++ b/cpukit/score/include/rtems/score/threadqimpl.h @@ -260,7 +260,7 @@ void _Thread_queue_Process_timeout( * @retval 0 The @left node is of equal importance with @right node. * @retval 1 The @left node is less important than @right node. */ -int _Thread_queue_Compare_priority( +RBTree_Compare_result _Thread_queue_Compare_priority( const RBTree_Node *left, const RBTree_Node *right ); diff --git a/cpukit/score/src/rbtreefind.c b/cpukit/score/src/rbtreefind.c index f767626..168a108 100644 --- a/cpukit/score/src/rbtreefind.c +++ b/cpukit/score/src/rbtreefind.c @@ -30,8 +30,8 @@ RBTree_Node *_RBTree_Find( RBTree_Node *found = NULL; while ( iter_node != NULL ) { - int compare_result = ( *compare )( the_node, iter_node ); - RBTree_Direction dir; + RBTree_Compare_result compare_result = ( *compare )( the_node, iter_node ); + RBTree_Direction dir; if ( _RBTree_Is_equal( compare_result ) ) { found = iter_node; diff --git a/cpukit/score/src/rbtreeinsert.c b/cpukit/score/src/rbtreeinsert.c index afff1ef..3bccba5 100644 --- a/cpukit/score/src/rbtreeinsert.c +++ b/cpukit/score/src/rbtreeinsert.c @@ -12,6 +12,16 @@ #include +RTEMS_STATIC_ASSERT( + sizeof( RBTree_Compare_result ) >= sizeof( intptr_t ), + RBTree_Compare_result_intptr_t +); + +RTEMS_STATIC_ASSERT( + sizeof( RBTree_Compare_result ) >= sizeof( int32_t ), + RBTree_Compare_result_int32_t +); + /** @brief Validate and fix-up tree properties for a new insert/colored node * * This routine checks and fixes the Red-Black Tree properties based on @@ -77,7 +87,8 @@ RBTree_Node *_RBTree_Insert( } else { /* typical binary search tree insert, descend tree to leaf and insert */ while ( iter_node ) { - int compare_result = ( *compare )( the_node, iter_node ); + RBTree_Compare_result compare_result = + ( *compare )( the_node, iter_node ); if ( is_unique && _RBTree_Is_equal( compare_result ) ) return iter_node; diff --git a/cpukit/score/src/scheduleredf.c b/cpukit/score/src/scheduleredf.c index 6dfa288..00b6181 100644 --- a/cpukit/score/src/scheduleredf.c +++ b/cpukit/score/src/scheduleredf.c @@ -20,7 +20,7 @@ #include -int _Scheduler_EDF_Compare( +RBTree_Compare_result _Scheduler_EDF_Compare( const RBTree_Node* n1, const RBTree_Node* n2 ) diff --git a/cpukit/score/src/threadq.c b/cpukit/score/src/threadq.c index b146ad4..aa08541 100644 --- a/cpukit/score/src/threadq.c +++ b/cpukit/score/src/threadq.c @@ -24,7 +24,7 @@ #include #include -int _Thread_queue_Compare_priority( +RBTree_Compare_result _Thread_queue_Compare_priority( const RBTree_Node *left, const RBTree_Node *right ) diff --git a/testsuites/libtests/rbheap01/init.c b/testsuites/libtests/rbheap01/init.c index 93813b8..6fd86db 100644 --- a/testsuites/libtests/rbheap01/init.c +++ b/testsuites/libtests/rbheap01/init.c @@ -94,22 +94,6 @@ static bool chunk_visitor( return false; } -static void test_init_chunk_alignment(void) -{ - rtems_status_code sc = RTEMS_SUCCESSFUL; - rtems_rbheap_control control; - - sc = rtems_rbheap_initialize( - &control, - area, - sizeof(area), - 0, - extend_descriptors, - NULL - ); - rtems_test_assert(sc == RTEMS_INVALID_NUMBER); -} - static void test_init_begin_greater_than_end(void) { rtems_status_code sc = RTEMS_SUCCESSFUL; @@ -597,7 +581,6 @@ static void Init(rtems_task_argument arg) { TEST_BEGIN(); - test_init_chunk_alignment(); test_init_begin_greater_than_end(); test_init_begin_greater_than_aligned_begin(); test_init_aligned_begin_greater_than_aligned_end(); diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index d78790f..2dd08f5 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -33,7 +33,7 @@ typedef struct { rtems_rbtree_node Node; } test_node; -static int test_compare_function ( +static rtems_rbtree_compare_result test_compare_function ( const rtems_rbtree_node *n1, const rtems_rbtree_node *n2 ) From sebh at rtems.org Tue Aug 5 08:05:21 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 05 Aug 2014 03:05:21 -0500 Subject: [rtems commit] posix: Simplify key implementation Message-ID: <20140805080521.7C7AC7007F6@git.rtems.org> Module: rtems Branch: master Commit: 390cfcda71c5bb0d53493210bcf4a15ee29c0498 Changeset: http://git.rtems.org/rtems/commit/?id=390cfcda71c5bb0d53493210bcf4a15ee29c0498 Author: Sebastian Huber Date: Sat Aug 2 15:49:26 2014 +0200 posix: Simplify key implementation --- cpukit/posix/include/rtems/posix/key.h | 33 +++++++++++++++++++++------ cpukit/posix/include/rtems/posix/keyimpl.h | 4 +- cpukit/posix/src/key.c | 20 ++++++++++------ cpukit/posix/src/keygetspecific.c | 2 +- cpukit/posix/src/keysetspecific.c | 6 +++- 5 files changed, 44 insertions(+), 21 deletions(-) diff --git a/cpukit/posix/include/rtems/posix/key.h b/cpukit/posix/include/rtems/posix/key.h index bfa05b1..7cc179c 100644 --- a/cpukit/posix/include/rtems/posix/key.h +++ b/cpukit/posix/include/rtems/posix/key.h @@ -25,6 +25,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -39,20 +40,36 @@ extern "C" { /**@{**/ /** - * @brief The rbtree node used to manage a POSIX key and value. + * @brief Represents POSIX key and value pair. */ typedef struct { - /** This field is the chain node structure. */ + /** + * @brief The chain node for the per-thread value chain. + */ Chain_Node Key_values_per_thread_node; - /** This field is the rbtree node structure. */ + + /** + * @brief The tree node for the lookup tree. + */ RBTree_Node Key_value_lookup_node; - /** This field is the POSIX key used as an rbtree key */ + + /** + * @brief The POSIX key identifier used in combination with the thread + * pointer as the tree key. + */ pthread_key_t key; - /** This field is the Thread id also used as an rbtree key */ - Objects_Id thread_id; - /** This field points to the POSIX key value of specific thread */ + + /** + * @brief The thread pointer used in combination with the POSIX key + * identifier as the tree key. + */ + Thread_Control *thread; + + /** + * @brief The thread specific POSIX key value. + */ const void *value; -} POSIX_Keys_Key_value_pair; +} POSIX_Keys_Key_value_pair; /** * @brief The data structure used to manage a POSIX key. diff --git a/cpukit/posix/include/rtems/posix/keyimpl.h b/cpukit/posix/include/rtems/posix/keyimpl.h index ded030d..42989b0 100644 --- a/cpukit/posix/include/rtems/posix/keyimpl.h +++ b/cpukit/posix/include/rtems/posix/keyimpl.h @@ -170,12 +170,12 @@ RTEMS_INLINE_ROUTINE void _POSIX_Keys_Key_value_pair_free( RTEMS_INLINE_ROUTINE RBTree_Node *_POSIX_Keys_Find( pthread_key_t key, - Objects_Id thread_id, + Thread_Control *thread, POSIX_Keys_Key_value_pair *search_node ) { search_node->key = key; - search_node->thread_id = thread_id; + search_node->thread = thread; return _RBTree_Find( &_POSIX_Keys_Key_value_lookup_tree, diff --git a/cpukit/posix/src/key.c b/cpukit/posix/src/key.c index 67c6e27..6753d57 100644 --- a/cpukit/posix/src/key.c +++ b/cpukit/posix/src/key.c @@ -51,7 +51,8 @@ RBTree_Compare_result _POSIX_Keys_Key_value_compare( { POSIX_Keys_Key_value_pair *n1; POSIX_Keys_Key_value_pair *n2; - Objects_Id thread_id1, thread_id2; + Thread_Control *thread1; + Thread_Control *thread2; RBTree_Compare_result diff; n1 = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node1 ); @@ -61,15 +62,18 @@ RBTree_Compare_result _POSIX_Keys_Key_value_compare( if ( diff ) return diff; - thread_id1 = n1->thread_id; - thread_id2 = n2->thread_id; + thread1 = n1->thread; + thread2 = n2->thread; - /** - * if thread_id1 or thread_id2 equals to 0, only key1 and key2 is valued. - * it enables us search node only by pthread_key_t type key. + /* + * If thread1 or thread2 equals to NULL, only key1 and key2 is valued. It + * enables us search node only by pthread_key_t type key. Exploit that the + * thread control alignment is at least two to avoid integer overflows. */ - if ( thread_id1 && thread_id2 ) - return thread_id1 - thread_id2; + if ( thread1 != NULL && thread2 != NULL ) + return (RBTree_Compare_result) ( (uintptr_t) thread1 >> 1 ) + - (RBTree_Compare_result) ( (uintptr_t) thread2 >> 1 ); + return 0; } diff --git a/cpukit/posix/src/keygetspecific.c b/cpukit/posix/src/keygetspecific.c index f7e7b71..5ab37a7 100644 --- a/cpukit/posix/src/keygetspecific.c +++ b/cpukit/posix/src/keygetspecific.c @@ -49,7 +49,7 @@ void *pthread_getspecific( switch ( location ) { case OBJECTS_LOCAL: - p = _POSIX_Keys_Find( key, _Thread_Executing->Object.id, &search_node ); + p = _POSIX_Keys_Find( key, _Thread_Executing, &search_node ); if ( p != NULL ) { value_pair_p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( p ); key_data = value_pair_p->value; diff --git a/cpukit/posix/src/keysetspecific.c b/cpukit/posix/src/keysetspecific.c index ec17d47..ee85ac2 100644 --- a/cpukit/posix/src/keysetspecific.c +++ b/cpukit/posix/src/keysetspecific.c @@ -39,12 +39,14 @@ int pthread_setspecific( POSIX_Keys_Key_value_pair *value_pair_ptr; RBTree_Node *p; POSIX_Keys_Key_value_pair search_node; + Thread_Control *executing; the_key = _POSIX_Keys_Get( key, &location ); switch ( location ) { case OBJECTS_LOCAL: - p = _POSIX_Keys_Find( key, _Thread_Executing->Object.id, &search_node ); + executing = _Thread_Executing; + p = _POSIX_Keys_Find( key, executing, &search_node ); if ( p != NULL ) { value_pair_ptr = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( p ); value_pair_ptr->value = value; @@ -58,7 +60,7 @@ int pthread_setspecific( } value_pair_ptr->key = key; - value_pair_ptr->thread_id = _Thread_Executing->Object.id; + value_pair_ptr->thread = executing; value_pair_ptr->value = value; /* The insert can only go wrong if the same node is already in a unique * tree. This has been already checked with the _RBTree_Find() */ From sebh at rtems.org Tue Aug 5 08:05:21 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 05 Aug 2014 03:05:21 -0500 Subject: [rtems commit] Add and use RTEMS_CONTAINER_OF() Message-ID: <20140805080521.2CC8D7007F7@git.rtems.org> Module: rtems Branch: master Commit: 40dcafaf80a29c20d74594853a8ff04441eabd9c Changeset: http://git.rtems.org/rtems/commit/?id=40dcafaf80a29c20d74594853a8ff04441eabd9c Author: Sebastian Huber Date: Sat Aug 2 16:22:31 2014 +0200 Add and use RTEMS_CONTAINER_OF() --- cpukit/libblock/src/bdbuf.c | 4 +- cpukit/posix/include/rtems/posix/keyimpl.h | 3 + cpukit/posix/src/key.c | 4 +- cpukit/posix/src/keyfreememory.c | 8 ++-- cpukit/posix/src/keygetspecific.c | 4 +- cpukit/posix/src/keysetspecific.c | 5 +-- cpukit/sapi/include/rtems/rbheap.h | 2 +- cpukit/sapi/include/rtems/rbtree.h | 10 ---- cpukit/score/include/rtems/score/basedefs.h | 10 ++++ cpukit/score/include/rtems/score/mrspimpl.h | 2 +- cpukit/score/include/rtems/score/rbtree.h | 14 ------ .../score/include/rtems/score/scheduleredfimpl.h | 2 +- cpukit/score/include/rtems/score/schedulerimpl.h | 2 +- cpukit/score/include/rtems/score/threadimpl.h | 18 ++++---- cpukit/score/src/resourceiterate.c | 6 +-- cpukit/score/src/schedulerchangeroot.c | 2 +- cpukit/score/src/scheduleredf.c | 10 +++-- cpukit/score/src/threadq.c | 12 +++--- cpukit/score/src/threadqdequeue.c | 2 +- cpukit/score/src/threadqfirst.c | 5 +- testsuites/sptests/sprbtree01/init.c | 44 ++++++++++---------- 21 files changed, 76 insertions(+), 93 deletions(-) diff --git a/cpukit/libblock/src/bdbuf.c b/cpukit/libblock/src/bdbuf.c index 31dd289..f215911 100644 --- a/cpukit/libblock/src/bdbuf.c +++ b/cpukit/libblock/src/bdbuf.c @@ -3178,8 +3178,8 @@ rtems_bdbuf_read_ahead_task (rtems_task_argument arg) while ((node = rtems_chain_get_unprotected (chain)) != NULL) { - rtems_disk_device *dd = (rtems_disk_device *) - ((char *) node - offsetof (rtems_disk_device, read_ahead.node)); + rtems_disk_device *dd = + RTEMS_CONTAINER_OF (node, rtems_disk_device, read_ahead.node); rtems_blkdev_bnum block = dd->read_ahead.next; rtems_blkdev_bnum media_block = 0; rtems_status_code sc = diff --git a/cpukit/posix/include/rtems/posix/keyimpl.h b/cpukit/posix/include/rtems/posix/keyimpl.h index b21c1d3..aff9749 100644 --- a/cpukit/posix/include/rtems/posix/keyimpl.h +++ b/cpukit/posix/include/rtems/posix/keyimpl.h @@ -49,6 +49,9 @@ extern RBTree_Control _POSIX_Keys_Key_value_lookup_tree; */ POSIX_EXTERN Freechain_Control _POSIX_Keys_Keypool; +#define POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node ) \ + RTEMS_CONTAINER_OF( node, POSIX_Keys_Key_value_pair, Key_value_lookup_node ) + /** * @brief POSIX key manager initialization. * diff --git a/cpukit/posix/src/key.c b/cpukit/posix/src/key.c index 105706a..e231299 100644 --- a/cpukit/posix/src/key.c +++ b/cpukit/posix/src/key.c @@ -54,8 +54,8 @@ int _POSIX_Keys_Key_value_compare( Objects_Id thread_id1, thread_id2; int diff; - n1 = _RBTree_Container_of( node1, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); - n2 = _RBTree_Container_of( node2, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); + n1 = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node1 ); + n2 = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node2 ); diff = n1->key - n2->key; if ( diff ) diff --git a/cpukit/posix/src/keyfreememory.c b/cpukit/posix/src/keyfreememory.c index b419f1f..4e19832 100644 --- a/cpukit/posix/src/keyfreememory.c +++ b/cpukit/posix/src/keyfreememory.c @@ -39,17 +39,17 @@ void _POSIX_Keys_Free_memory( * find the smallest thread_id node in the rbtree. */ next = _RBTree_Next( iter, RBT_LEFT ); - p = _RBTree_Container_of( next, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); + p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( next ); while ( next != NULL && p->key == key_id) { iter = next; next = _RBTree_Next( iter, RBT_LEFT ); - p = _RBTree_Container_of( next, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); + p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( next ); } /** * delete all nodes belongs to the_key from the rbtree and chain. */ - p = _RBTree_Container_of( iter, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); + p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( iter ); while ( iter != NULL && p->key == key_id ) { next = _RBTree_Next( iter, RBT_RIGHT ); _RBTree_Extract( &_POSIX_Keys_Key_value_lookup_tree, iter ); @@ -57,6 +57,6 @@ void _POSIX_Keys_Free_memory( _POSIX_Keys_Key_value_pair_free( p ); iter = next; - p = _RBTree_Container_of( iter, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); + p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( iter ); } } diff --git a/cpukit/posix/src/keygetspecific.c b/cpukit/posix/src/keygetspecific.c index 9c54112..f7e7b71 100644 --- a/cpukit/posix/src/keygetspecific.c +++ b/cpukit/posix/src/keygetspecific.c @@ -51,9 +51,7 @@ void *pthread_getspecific( case OBJECTS_LOCAL: p = _POSIX_Keys_Find( key, _Thread_Executing->Object.id, &search_node ); if ( p != NULL ) { - value_pair_p = _RBTree_Container_of( p, - POSIX_Keys_Key_value_pair, - Key_value_lookup_node ); + value_pair_p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( p ); key_data = value_pair_p->value; } else { key_data = NULL; diff --git a/cpukit/posix/src/keysetspecific.c b/cpukit/posix/src/keysetspecific.c index 0f7c682..ec17d47 100644 --- a/cpukit/posix/src/keysetspecific.c +++ b/cpukit/posix/src/keysetspecific.c @@ -46,10 +46,7 @@ int pthread_setspecific( case OBJECTS_LOCAL: p = _POSIX_Keys_Find( key, _Thread_Executing->Object.id, &search_node ); if ( p != NULL ) { - value_pair_ptr = _RBTree_Container_of( p, - POSIX_Keys_Key_value_pair, - Key_value_lookup_node ); - + value_pair_ptr = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( p ); value_pair_ptr->value = value; } else { value_pair_ptr = _POSIX_Keys_Key_value_pair_allocate(); diff --git a/cpukit/sapi/include/rtems/rbheap.h b/cpukit/sapi/include/rtems/rbheap.h index 7c44f11..0848b69 100644 --- a/cpukit/sapi/include/rtems/rbheap.h +++ b/cpukit/sapi/include/rtems/rbheap.h @@ -254,7 +254,7 @@ void rtems_rbheap_extend_descriptors_with_malloc( /* Private API */ #define rtems_rbheap_chunk_of_node(node) \ - rtems_rbtree_container_of(node, rtems_rbheap_chunk, tree_node) + RTEMS_CONTAINER_OF(node, rtems_rbheap_chunk, tree_node) static inline bool rtems_rbheap_is_chunk_free(const rtems_rbheap_chunk *chunk) { diff --git a/cpukit/sapi/include/rtems/rbtree.h b/cpukit/sapi/include/rtems/rbtree.h index 4e6d852..eaf2b6e 100644 --- a/cpukit/sapi/include/rtems/rbtree.h +++ b/cpukit/sapi/include/rtems/rbtree.h @@ -74,16 +74,6 @@ typedef RBTree_Compare rtems_rbtree_compare; RBTREE_DEFINE_EMPTY(name) /** - * @brief macro to return the structure containing the @a node. - * - * This macro returns a pointer of type @a object_type that points - * to the structure containing @a node, where @a object_member is the - * field name of the rtems_rbtree_node structure in objects of @a object_type. - */ -#define rtems_rbtree_container_of(node,object_type, object_member) \ - _RBTree_Container_of(node,object_type,object_member) - -/** * @brief Initialize a RBTree header. * * This routine initializes @a the_rbtree structure to manage the diff --git a/cpukit/score/include/rtems/score/basedefs.h b/cpukit/score/include/rtems/score/basedefs.h index 382a97a..ec93951 100644 --- a/cpukit/score/include/rtems/score/basedefs.h +++ b/cpukit/score/include/rtems/score/basedefs.h @@ -217,6 +217,16 @@ */ #define RTEMS_ZERO_LENGTH_ARRAY 0 +/** + * @brief Returns a pointer to the container of a specified member pointer. + * + * @param[in] _m The pointer to a member of the container. + * @param[in] _type The type of the container. + * @param[in] _member_name The designator name of the container member. + */ +#define RTEMS_CONTAINER_OF( _m, _type, _member_name ) \ + ( (_type *) ( (uintptr_t) ( _m ) - offsetof( _type, _member_name ) ) ) + #ifndef ASM #ifdef RTEMS_DEPRECATED_TYPES typedef bool boolean; diff --git a/cpukit/score/include/rtems/score/mrspimpl.h b/cpukit/score/include/rtems/score/mrspimpl.h index 4aaa50b..1571594 100644 --- a/cpukit/score/include/rtems/score/mrspimpl.h +++ b/cpukit/score/include/rtems/score/mrspimpl.h @@ -181,7 +181,7 @@ RTEMS_INLINE_ROUTINE MRSP_Status _MRSP_Wait_for_ownership( _Scheduler_Thread_change_resource_root( executing, - _Thread_Resource_node_to_thread( _Resource_Node_get_root( owner ) ) + THREAD_RESOURCE_NODE_TO_THREAD( _Resource_Node_get_root( owner ) ) ); if ( timeout > 0 ) { diff --git a/cpukit/score/include/rtems/score/rbtree.h b/cpukit/score/include/rtems/score/rbtree.h index c4effce..d23808f 100644 --- a/cpukit/score/include/rtems/score/rbtree.h +++ b/cpukit/score/include/rtems/score/rbtree.h @@ -82,20 +82,6 @@ struct RBTree_Node_struct { }; /** - * @brief Macro to return the structure containing the @a node. - * - * This macro returns a pointer of type @a container_type that points - * to the structure containing @a node, where @a node_field_name is the - * field name of the RBTree_Node structure in @a container_type. - * - */ -#define _RBTree_Container_of(node, container_type, node_field_name) \ -( \ - (container_type*) \ - ( (uintptr_t)(node) - offsetof(container_type, node_field_name) ) \ -) - -/** * This type indicates the direction. */ typedef enum { diff --git a/cpukit/score/include/rtems/score/scheduleredfimpl.h b/cpukit/score/include/rtems/score/scheduleredfimpl.h index 019c544..50e40bc 100644 --- a/cpukit/score/include/rtems/score/scheduleredfimpl.h +++ b/cpukit/score/include/rtems/score/scheduleredfimpl.h @@ -89,7 +89,7 @@ RTEMS_INLINE_ROUTINE void _Scheduler_EDF_Schedule_body( _Scheduler_EDF_Get_context( scheduler ); RBTree_Node *first = _RBTree_First( &context->Ready, RBT_LEFT ); Scheduler_EDF_Node *node = - _RBTree_Container_of(first, Scheduler_EDF_Node, Node); + RTEMS_CONTAINER_OF( first, Scheduler_EDF_Node, Node ); Thread_Control *heir = node->thread; ( void ) the_thread; diff --git a/cpukit/score/include/rtems/score/schedulerimpl.h b/cpukit/score/include/rtems/score/schedulerimpl.h index 4f71408..45a2f8d 100644 --- a/cpukit/score/include/rtems/score/schedulerimpl.h +++ b/cpukit/score/include/rtems/score/schedulerimpl.h @@ -164,7 +164,7 @@ RTEMS_INLINE_ROUTINE bool _Scheduler_Ask_for_help_visitor( Thread_Control *previous_needs_help = help_context->needs_help; Thread_Control *next_needs_help; Thread_Control *offers_help = - _Thread_Resource_node_to_thread( resource_node ); + THREAD_RESOURCE_NODE_TO_THREAD( resource_node ); const Scheduler_Control *scheduler = _Scheduler_Get_own( offers_help ); next_needs_help = ( *scheduler->Operations.ask_for_help )( diff --git a/cpukit/score/include/rtems/score/threadimpl.h b/cpukit/score/include/rtems/score/threadimpl.h index a527c8b..9321c01 100644 --- a/cpukit/score/include/rtems/score/threadimpl.h +++ b/cpukit/score/include/rtems/score/threadimpl.h @@ -76,6 +76,14 @@ SCORE_EXTERN Thread_Control *_Thread_Allocated_fp; SCORE_EXTERN struct _reent **_Thread_libc_reent; #endif +#define THREAD_RBTREE_NODE_TO_THREAD( node ) \ + RTEMS_CONTAINER_OF( node, Thread_Control, RBNode ) + +#if defined(RTEMS_SMP) +#define THREAD_RESOURCE_NODE_TO_THREAD( node ) \ + RTEMS_CONTAINER_OF( node, Thread_Control, Resource_node ) +#endif + /** * @brief Initialize thread handler. * @@ -846,16 +854,6 @@ RTEMS_INLINE_ROUTINE bool _Thread_Owns_resources( return owns_resources; } -#if defined(RTEMS_SMP) -RTEMS_INLINE_ROUTINE Thread_Control *_Thread_Resource_node_to_thread( - Resource_Node *node -) -{ - return (Thread_Control *) - ( (char *) node - offsetof( Thread_Control, Resource_node ) ); -} -#endif - RTEMS_INLINE_ROUTINE void _Thread_Debug_set_real_processor( Thread_Control *the_thread, Per_CPU_Control *cpu diff --git a/cpukit/score/src/resourceiterate.c b/cpukit/score/src/resourceiterate.c index 26f9234..ac8b8b0 100644 --- a/cpukit/score/src/resourceiterate.c +++ b/cpukit/score/src/resourceiterate.c @@ -16,14 +16,12 @@ static Resource_Control *_Resource_Rival_head_to_resource( Chain_Node *head ) { - return (Resource_Control *) - ( (char *) head - offsetof( Resource_Control, Rivals.Head.Node ) ); + return RTEMS_CONTAINER_OF( head, Resource_Control, Rivals.Head.Node ); } static Resource_Node *_Resource_Resource_tail_to_rival( Chain_Node *tail ) { - return (Resource_Node *) - ( (char *) tail - offsetof( Resource_Node, Resources.Tail.Node ) ); + return RTEMS_CONTAINER_OF( tail, Resource_Node, Resources.Tail.Node ); } void _Resource_Iterate( diff --git a/cpukit/score/src/schedulerchangeroot.c b/cpukit/score/src/schedulerchangeroot.c index eba852b..f731117 100644 --- a/cpukit/score/src/schedulerchangeroot.c +++ b/cpukit/score/src/schedulerchangeroot.c @@ -32,7 +32,7 @@ RTEMS_INLINE_ROUTINE bool _Scheduler_Set_root_visitor( Thread_Control *root = ctx->root; Thread_Control *needs_help = root; Thread_Control *offers_help = - _Thread_Resource_node_to_thread( resource_node ); + THREAD_RESOURCE_NODE_TO_THREAD( resource_node ); const Scheduler_Control *scheduler = _Scheduler_Get_own( offers_help ); Thread_Control *needs_help_too; diff --git a/cpukit/score/src/scheduleredf.c b/cpukit/score/src/scheduleredf.c index 01b5244..6dfa288 100644 --- a/cpukit/score/src/scheduleredf.c +++ b/cpukit/score/src/scheduleredf.c @@ -25,10 +25,12 @@ int _Scheduler_EDF_Compare( const RBTree_Node* n2 ) { - Priority_Control value1 = _RBTree_Container_of - (n1,Scheduler_EDF_Node,Node)->thread->current_priority; - Priority_Control value2 = _RBTree_Container_of - (n2,Scheduler_EDF_Node,Node)->thread->current_priority; + Scheduler_EDF_Node *edf1 = + RTEMS_CONTAINER_OF( n1, Scheduler_EDF_Node, Node ); + Scheduler_EDF_Node *edf2 = + RTEMS_CONTAINER_OF( n2, Scheduler_EDF_Node, Node ); + Priority_Control value1 = edf1->thread->current_priority; + Priority_Control value2 = edf2->thread->current_priority; /* * This function compares only numbers for the red-black tree, diff --git a/cpukit/score/src/threadq.c b/cpukit/score/src/threadq.c index 0ffbfad..b146ad4 100644 --- a/cpukit/score/src/threadq.c +++ b/cpukit/score/src/threadq.c @@ -20,19 +20,19 @@ #include #include -#include - #include +#include +#include int _Thread_queue_Compare_priority( const RBTree_Node *left, const RBTree_Node *right ) { - Priority_Control left_priority = _RBTree_Container_of - (left,Thread_Control,RBNode)->current_priority; - Priority_Control right_priority = _RBTree_Container_of - (right,Thread_Control,RBNode)->current_priority; + Priority_Control left_priority = + THREAD_RBTREE_NODE_TO_THREAD( left )->current_priority; + Priority_Control right_priority = + THREAD_RBTREE_NODE_TO_THREAD( right )->current_priority; /* * SuperCore priorities use lower numbers to indicate greater importance. diff --git a/cpukit/score/src/threadqdequeue.c b/cpukit/score/src/threadqdequeue.c index d745ef2..e364aa9 100644 --- a/cpukit/score/src/threadqdequeue.c +++ b/cpukit/score/src/threadqdequeue.c @@ -50,7 +50,7 @@ Thread_Control *_Thread_queue_Dequeue( first = _RBTree_Get( &the_thread_queue->Queues.Priority, RBT_LEFT ); if ( first ) { - the_thread = _RBTree_Container_of( first, Thread_Control, RBNode ); + the_thread = THREAD_RBTREE_NODE_TO_THREAD( first ); } } diff --git a/cpukit/score/src/threadqfirst.c b/cpukit/score/src/threadqfirst.c index 39f7c3f..5d97ae1 100644 --- a/cpukit/score/src/threadqfirst.c +++ b/cpukit/score/src/threadqfirst.c @@ -18,9 +18,10 @@ #include "config.h" #endif +#include #include #include -#include +#include Thread_Control *_Thread_queue_First( Thread_queue_Control *the_thread_queue @@ -41,7 +42,7 @@ Thread_Control *_Thread_queue_First( first = _RBTree_First( &the_thread_queue->Queues.Priority, RBT_LEFT ); if ( first ) - thread = _RBTree_Container_of( first, Thread_Control, RBNode ); + thread = THREAD_RBTREE_NODE_TO_THREAD( first ); } _ISR_Enable( level ); diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index c43871a..d78790f 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -38,8 +38,8 @@ static int test_compare_function ( const rtems_rbtree_node *n2 ) { - int key1 = rtems_rbtree_container_of( n1, test_node, Node )->key; - int key2 = rtems_rbtree_container_of( n2, test_node, Node )->key; + int key1 = RTEMS_CONTAINER_OF( n1, test_node, Node )->key; + int key2 = RTEMS_CONTAINER_OF( n2, test_node, Node )->key; return key1 - key2; } @@ -262,7 +262,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 1 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 2 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -290,7 +290,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 1 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 1 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -345,9 +345,9 @@ rtems_task Init( rtems_task_argument ignored ) rb_insert_unique( &rbtree1, &node2.Node ); puts( "INIT - Verify rtems_rbtree_peek_max/min, rtems_rbtree_extract" ); - test_node *t1 = rtems_rbtree_container_of(rtems_rbtree_peek_max(&rbtree1), + test_node *t1 = RTEMS_CONTAINER_OF(rtems_rbtree_peek_max(&rbtree1), test_node,Node); - test_node *t2 = rtems_rbtree_container_of(rtems_rbtree_peek_min(&rbtree1), + test_node *t2 = RTEMS_CONTAINER_OF(rtems_rbtree_peek_min(&rbtree1), test_node,Node); if (t1->key - t2->key != 1) { puts( "INIT - Peek Min - Max failed" ); @@ -355,7 +355,7 @@ rtems_task Init( rtems_task_argument ignored ) } p = rtems_rbtree_peek_max(&rbtree1); rtems_rbtree_extract(&rbtree1, p); - t1 = rtems_rbtree_container_of(p,test_node,Node); + t1 = RTEMS_CONTAINER_OF(p,test_node,Node); if (t1->key != 2) { puts( "INIT - rtems_rbtree_extract failed"); rtems_test_exit(0); @@ -365,7 +365,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 1 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 2 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -390,7 +390,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -423,7 +423,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -467,7 +467,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0, i = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p, test_node, Node); + test_node *t = RTEMS_CONTAINER_OF(p, test_node, Node); while ( id == numbers_sorted[i] ) { /* skip if expected minimum (id) is in the set of extracted numbers */ @@ -529,7 +529,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_max(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_max(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -561,20 +561,20 @@ rtems_task Init( rtems_task_argument ignored ) puts( "INIT - Verify rtems_rbtree_find" ); search_node.key = 30; p = rb_find_unique(&rbtree1, &search_node.Node); - if(rtems_rbtree_container_of(p,test_node,Node)->id != 30) { + if(RTEMS_CONTAINER_OF(p,test_node,Node)->id != 30) { puts ("INIT - ERROR ON RBTREE ID MISMATCH"); rtems_test_exit(0); } puts( "INIT - Verify rtems_rbtree_predecessor/successor"); p = rtems_rbtree_predecessor(p); - if(p && rtems_rbtree_container_of(p,test_node,Node)->id != 29) { + if(p && RTEMS_CONTAINER_OF(p,test_node,Node)->id != 29) { puts ("INIT - ERROR ON RBTREE ID MISMATCH"); rtems_test_exit(0); } p = rb_find_unique(&rbtree1, &search_node.Node); p = rtems_rbtree_successor(p); - if(p && rtems_rbtree_container_of(p,test_node,Node)->id != 31) { + if(p && RTEMS_CONTAINER_OF(p,test_node,Node)->id != 31) { puts ("INIT - ERROR ON RBTREE ID MISMATCH"); rtems_test_exit(0); } @@ -601,7 +601,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_max(&rbtree1), id = 99 ; p ; p = rtems_rbtree_get_max(&rbtree1) , id-- ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id < 0 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -634,7 +634,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 19 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -666,7 +666,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -703,7 +703,7 @@ rtems_task Init( rtems_task_argument ignored ) puts( "INIT - Verify rtems_rbtree_find in a duplicate tree" ); search_node.key = 2; p = rb_find_multi(&rbtree1, &search_node.Node); - if(rtems_rbtree_container_of(p,test_node,Node)->id != 2) { + if(RTEMS_CONTAINER_OF(p,test_node,Node)->id != 2) { puts ("INIT - ERROR ON RBTREE ID MISMATCH"); rtems_test_exit(0); } @@ -712,7 +712,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -744,7 +744,7 @@ rtems_task Init( rtems_task_argument ignored ) puts( "INIT - Verify rtems_rbtree_find in a duplicate tree" ); search_node.key = 2; p = rb_find_multi(&rbtree1, &search_node.Node); - if(rtems_rbtree_container_of(p,test_node,Node)->id != 97) { + if(RTEMS_CONTAINER_OF(p,test_node,Node)->id != 97) { puts ("INIT - ERROR ON RBTREE ID MISMATCH"); rtems_test_exit(0); } @@ -753,7 +753,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); From sebh at rtems.org Tue Aug 5 13:11:33 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 05 Aug 2014 08:11:33 -0500 Subject: [rtems commit] sptests/sprbtree01: Reduce stack usage Message-ID: <20140805131133.D3B197007F6@git.rtems.org> Module: rtems Branch: master Commit: 888edf69a9f9db980914fc5f0ed61d62fecaf3f9 Changeset: http://git.rtems.org/rtems/commit/?id=888edf69a9f9db980914fc5f0ed61d62fecaf3f9 Author: Sebastian Huber Date: Tue Aug 5 13:52:45 2014 +0200 sptests/sprbtree01: Reduce stack usage --- testsuites/sptests/sprbtree01/init.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index 2dd08f5..742bd89 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -33,6 +33,8 @@ typedef struct { rtems_rbtree_node Node; } test_node; +static test_node node_array[100]; + static rtems_rbtree_compare_result test_compare_function ( const rtems_rbtree_node *n1, const rtems_rbtree_node *n2 @@ -225,7 +227,6 @@ rtems_task Init( rtems_task_argument ignored ) rtems_rbtree_control rbtree1; rtems_rbtree_node *p; test_node node1, node2; - test_node node_array[100]; test_node search_node; int id; int i; From sebh at rtems.org Tue Aug 5 13:11:33 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 05 Aug 2014 08:11:33 -0500 Subject: [rtems commit] sptests/sprbtree01: Check tree layout Message-ID: <20140805131133.C267C7007F7@git.rtems.org> Module: rtems Branch: master Commit: d472d2178019e3c03359ebdfbd9dcca1be40dfba Changeset: http://git.rtems.org/rtems/commit/?id=d472d2178019e3c03359ebdfbd9dcca1be40dfba Author: Sebastian Huber Date: Tue Aug 5 14:07:07 2014 +0200 sptests/sprbtree01: Check tree layout --- testsuites/sptests/sprbtree01/init.c | 620 ++++++++++++++++++++++++++++++++++ 1 files changed, 620 insertions(+), 0 deletions(-) diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index 742bd89..ffb91b1 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -222,6 +222,614 @@ static void test_rbtree_min_max(void) rtems_test_assert( rtems_rbtree_is_empty( &tree ) ); } +#define TN( i ) &node_array[ i ].Node + +typedef struct { + int key; + const rtems_rbtree_node *parent; + const rtems_rbtree_node *left; + const rtems_rbtree_node *right; + RBTree_Color color; +} test_node_description; + +static const test_node_description test_insert_tree_0[] = { + { 52, NULL, NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_1[] = { + { 52, NULL, NULL, TN( 1 ) , RBT_BLACK }, + { 99, TN( 0 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_2[] = { + { 0, TN( 0 ), NULL, NULL , RBT_RED }, + { 52, NULL, TN( 2 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 0 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_3[] = { + { 0, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 52, NULL, TN( 2 ), TN( 1 ) , RBT_BLACK }, + { 85, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 0 ), TN( 3 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_4[] = { + { 0, TN( 0 ), NULL, TN( 4 ) , RBT_BLACK }, + { 43, TN( 2 ), NULL, NULL , RBT_RED }, + { 52, NULL, TN( 2 ), TN( 1 ) , RBT_BLACK }, + { 85, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 0 ), TN( 3 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_5[] = { + { 0, TN( 4 ), NULL, NULL , RBT_RED }, + { 43, TN( 0 ), TN( 2 ), TN( 5 ) , RBT_BLACK }, + { 44, TN( 4 ), NULL, NULL , RBT_RED }, + { 52, NULL, TN( 4 ), TN( 1 ) , RBT_BLACK }, + { 85, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 0 ), TN( 3 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_6[] = { + { 0, TN( 4 ), NULL, TN( 6 ) , RBT_BLACK }, + { 10, TN( 2 ), NULL, NULL , RBT_RED }, + { 43, TN( 0 ), TN( 2 ), TN( 5 ) , RBT_RED }, + { 44, TN( 4 ), NULL, NULL , RBT_BLACK }, + { 52, NULL, TN( 4 ), TN( 1 ) , RBT_BLACK }, + { 85, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 0 ), TN( 3 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_7[] = { + { 0, TN( 4 ), NULL, TN( 6 ) , RBT_BLACK }, + { 10, TN( 2 ), NULL, NULL , RBT_RED }, + { 43, TN( 0 ), TN( 2 ), TN( 5 ) , RBT_RED }, + { 44, TN( 4 ), NULL, NULL , RBT_BLACK }, + { 52, NULL, TN( 4 ), TN( 3 ) , RBT_BLACK }, + { 60, TN( 3 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 3 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_8[] = { + { 0, TN( 4 ), NULL, TN( 6 ) , RBT_BLACK }, + { 10, TN( 2 ), NULL, NULL , RBT_RED }, + { 43, TN( 0 ), TN( 2 ), TN( 5 ) , RBT_RED }, + { 44, TN( 4 ), NULL, TN( 8 ) , RBT_BLACK }, + { 50, TN( 5 ), NULL, NULL , RBT_RED }, + { 52, NULL, TN( 4 ), TN( 3 ) , RBT_BLACK }, + { 60, TN( 3 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 3 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_9[] = { + { 0, TN( 6 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 6 ), NULL, NULL , RBT_RED }, + { 43, TN( 0 ), TN( 6 ), TN( 5 ) , RBT_RED }, + { 44, TN( 4 ), NULL, TN( 8 ) , RBT_BLACK }, + { 50, TN( 5 ), NULL, NULL , RBT_RED }, + { 52, NULL, TN( 4 ), TN( 3 ) , RBT_BLACK }, + { 60, TN( 3 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 3 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_10[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_RED }, + { 19, TN( 6 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 0 ), NULL, TN( 8 ) , RBT_BLACK }, + { 50, TN( 5 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 5 ), TN( 3 ) , RBT_RED }, + { 60, TN( 3 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 3 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_11[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 6 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 0 ), NULL, TN( 8 ) , RBT_BLACK }, + { 50, TN( 5 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 5 ), TN( 3 ) , RBT_BLACK }, + { 60, TN( 3 ), NULL, TN( 11 ) , RBT_BLACK }, + { 68, TN( 7 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_RED }, + { 99, TN( 3 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_12[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 6 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 12 ), TN( 3 ) , RBT_BLACK }, + { 60, TN( 3 ), NULL, TN( 11 ) , RBT_BLACK }, + { 68, TN( 7 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_RED }, + { 99, TN( 3 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_13[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 6 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 12 ), TN( 3 ) , RBT_BLACK }, + { 57, TN( 7 ), NULL, NULL , RBT_RED }, + { 60, TN( 3 ), TN( 13 ), TN( 11 ) , RBT_BLACK }, + { 68, TN( 7 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_RED }, + { 99, TN( 3 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_14[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 17, TN( 9 ), NULL, NULL , RBT_RED }, + { 19, TN( 6 ), TN( 14 ), NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 12 ), TN( 3 ) , RBT_BLACK }, + { 57, TN( 7 ), NULL, NULL , RBT_RED }, + { 60, TN( 3 ), TN( 13 ), TN( 11 ) , RBT_BLACK }, + { 68, TN( 7 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_RED }, + { 99, TN( 3 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_15[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 17, TN( 9 ), NULL, NULL , RBT_RED }, + { 19, TN( 6 ), TN( 14 ), NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_RED }, + { 68, TN( 3 ), TN( 15 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_RED }, + { 99, TN( 3 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_16[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 17, TN( 9 ), NULL, NULL , RBT_RED }, + { 19, TN( 6 ), TN( 14 ), NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_RED }, + { 68, TN( 3 ), TN( 15 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_RED }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_17[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 14 ) , RBT_BLACK }, + { 12, TN( 14 ), NULL, NULL , RBT_RED }, + { 17, TN( 6 ), TN( 17 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_RED }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_RED }, + { 68, TN( 3 ), TN( 15 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_RED }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_18[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 14 ) , RBT_BLACK }, + { 12, TN( 14 ), NULL, NULL , RBT_RED }, + { 17, TN( 6 ), TN( 17 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_RED }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_RED }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_BLACK }, + { 77, TN( 11 ), NULL, NULL , RBT_RED }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_RED }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_19[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 14 ) , RBT_BLACK }, + { 12, TN( 14 ), NULL, NULL , RBT_RED }, + { 17, TN( 6 ), TN( 17 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_RED }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_RED }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description *const test_insert_trees[] = { + &test_insert_tree_0[ 0 ], + &test_insert_tree_1[ 0 ], + &test_insert_tree_2[ 0 ], + &test_insert_tree_3[ 0 ], + &test_insert_tree_4[ 0 ], + &test_insert_tree_5[ 0 ], + &test_insert_tree_6[ 0 ], + &test_insert_tree_7[ 0 ], + &test_insert_tree_8[ 0 ], + &test_insert_tree_9[ 0 ], + &test_insert_tree_10[ 0 ], + &test_insert_tree_11[ 0 ], + &test_insert_tree_12[ 0 ], + &test_insert_tree_13[ 0 ], + &test_insert_tree_14[ 0 ], + &test_insert_tree_15[ 0 ], + &test_insert_tree_16[ 0 ], + &test_insert_tree_17[ 0 ], + &test_insert_tree_18[ 0 ], + &test_insert_tree_19[ 0 ] +}; + +static const test_node_description test_remove_tree_0[] = { + { 8, TN( 6 ), NULL, NULL , RBT_BLACK }, + { 10, TN( 4 ), TN( 10 ), TN( 14 ) , RBT_BLACK }, + { 12, TN( 14 ), NULL, NULL , RBT_RED }, + { 17, TN( 6 ), TN( 17 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_RED }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_RED }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_1[] = { + { 10, TN( 14 ), NULL, TN( 17 ) , RBT_BLACK }, + { 12, TN( 6 ), NULL, NULL , RBT_RED }, + { 17, TN( 4 ), TN( 6 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 14 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_RED }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_2[] = { + { 12, TN( 14 ), NULL, NULL , RBT_BLACK }, + { 17, TN( 4 ), TN( 17 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 14 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_RED }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_3[] = { + { 17, TN( 4 ), NULL, TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_RED }, + { 43, TN( 7 ), TN( 14 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 4 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_4[] = { + { 19, TN( 4 ), NULL, NULL , RBT_BLACK }, + { 43, TN( 7 ), TN( 9 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 4 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_5[] = { + { 43, TN( 12 ), NULL, TN( 5 ) , RBT_BLACK }, + { 44, TN( 4 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 4 ), TN( 8 ) , RBT_RED }, + { 50, TN( 12 ), NULL, NULL , RBT_BLACK }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_6[] = { + { 44, TN( 12 ), NULL, NULL , RBT_BLACK }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_RED }, + { 50, TN( 12 ), NULL, NULL , RBT_BLACK }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_7[] = { + { 48, TN( 0 ), NULL, TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_8[] = { + { 50, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 52, TN( 7 ), TN( 8 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_9[] = { + { 52, TN( 7 ), NULL, TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_RED }, + { 60, TN( 11 ), TN( 0 ), TN( 15 ) , RBT_BLACK }, + { 67, TN( 7 ), NULL, NULL , RBT_BLACK }, + { 68, NULL, TN( 7 ), TN( 3 ) , RBT_BLACK }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 3 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 11 ), TN( 18 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_10[] = { + { 57, TN( 7 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 11 ), TN( 13 ), TN( 15 ) , RBT_BLACK }, + { 67, TN( 7 ), NULL, NULL , RBT_BLACK }, + { 68, NULL, TN( 7 ), TN( 3 ) , RBT_BLACK }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 3 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 11 ), TN( 18 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_11[] = { + { 60, TN( 11 ), NULL, TN( 15 ) , RBT_BLACK }, + { 67, TN( 7 ), NULL, NULL , RBT_RED }, + { 68, NULL, TN( 7 ), TN( 3 ) , RBT_BLACK }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 3 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 11 ), TN( 18 ), TN( 1 ) , RBT_RED }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_12[] = { + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, NULL, TN( 15 ), TN( 3 ) , RBT_BLACK }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 3 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 11 ), TN( 18 ), TN( 1 ) , RBT_RED }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_13[] = { + { 68, TN( 19 ), NULL, NULL , RBT_BLACK }, + { 71, TN( 3 ), TN( 11 ), TN( 18 ) , RBT_RED }, + { 77, TN( 19 ), NULL, NULL , RBT_BLACK }, + { 85, NULL, TN( 19 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_14[] = { + { 71, TN( 3 ), NULL, TN( 18 ) , RBT_BLACK }, + { 77, TN( 19 ), NULL, NULL , RBT_RED }, + { 85, NULL, TN( 19 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_15[] = { + { 77, TN( 3 ), NULL, NULL , RBT_BLACK }, + { 85, NULL, TN( 18 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_16[] = { + { 85, TN( 16 ), NULL, NULL , RBT_BLACK }, + { 90, NULL, TN( 3 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 16 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_17[] = { + { 90, NULL, NULL, TN( 1 ) , RBT_BLACK }, + { 99, TN( 16 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_remove_tree_18[] = { + { 99, NULL, NULL, NULL , RBT_BLACK } +}; + +static const test_node_description *const test_remove_trees[] = { + &test_remove_tree_0[ 0 ], + &test_remove_tree_1[ 0 ], + &test_remove_tree_2[ 0 ], + &test_remove_tree_3[ 0 ], + &test_remove_tree_4[ 0 ], + &test_remove_tree_5[ 0 ], + &test_remove_tree_6[ 0 ], + &test_remove_tree_7[ 0 ], + &test_remove_tree_8[ 0 ], + &test_remove_tree_9[ 0 ], + &test_remove_tree_10[ 0 ], + &test_remove_tree_11[ 0 ], + &test_remove_tree_12[ 0 ], + &test_remove_tree_13[ 0 ], + &test_remove_tree_14[ 0 ], + &test_remove_tree_15[ 0 ], + &test_remove_tree_16[ 0 ], + &test_remove_tree_17[ 0 ], + &test_remove_tree_18[ 0 ] +}; + +typedef struct { + int current; + int count; + const test_node_description *tree; +} visitor_context; + +static bool visit_nodes( + const RBTree_Node *node, + RBTree_Direction dir, + void *visitor_arg +) +{ + visitor_context *ctx = visitor_arg; + const test_node_description *td = &ctx->tree[ ctx->current ]; + const test_node *tn = RTEMS_CONTAINER_OF( node, test_node, Node ); + + rtems_test_assert( ctx->current < ctx->count ); + + rtems_test_assert( td->key == tn->id ); + rtems_test_assert( td->key == tn->key ); + + if ( td->parent == NULL ) { + rtems_test_assert( td->parent == tn->Node.parent->parent ); + } else { + rtems_test_assert( td->parent == tn->Node.parent ); + } + + rtems_test_assert( td->left == tn->Node.child[ RBT_LEFT ] ); + rtems_test_assert( td->right == tn->Node.child[ RBT_RIGHT ] ); + rtems_test_assert( td->color == tn->Node.color ); + + ++ctx->current; + + return false; +} + rtems_task Init( rtems_task_argument ignored ) { rtems_rbtree_control rbtree1; @@ -623,10 +1231,15 @@ rtems_task Init( rtems_task_argument ignored ) puts("INIT - Insert 20 random numbers"); for (i = 0; i < 20; i++) { + visitor_context ctx = { 0, i + 1, test_insert_trees[ i ] }; + node_array[i].id = numbers[i]; node_array[i].key = numbers[i]; rb_insert_unique( &rbtree1, &node_array[i].Node ); + _RBTree_Iterate( &rbtree1, RBT_RIGHT, visit_nodes, &ctx ); + rtems_test_assert( ctx.current == ctx.count ); + if (!rb_assert(rbtree1.root) ) puts( "INIT - FAILED TREE CHECK" ); } @@ -647,6 +1260,13 @@ rtems_task Init( rtems_task_argument ignored ) if (!rb_assert(rbtree1.root) ) puts( "INIT - FAILED TREE CHECK" ); + + if ( id < 19 ) { + visitor_context ctx = { 0, 20 - id - 1, test_remove_trees[ id ] }; + + _RBTree_Iterate( &rbtree1, RBT_RIGHT, visit_nodes, &ctx ); + rtems_test_assert( ctx.current == ctx.count ); + } } if(!rtems_rbtree_is_empty(&rbtree1)) { From sebh at rtems.org Thu Aug 7 13:51:57 2014 From: sebh at rtems.org (Sebastian Huber) Date: Thu, 07 Aug 2014 08:51:57 -0500 Subject: [rtems commit] rbtree: Simplify _RBTree_Extract() Message-ID: <20140807135157.7C9677007F7@git.rtems.org> Module: rtems Branch: master Commit: 0ef6e3bfb9f763b4de46a8693d1e7cd59beb754e Changeset: http://git.rtems.org/rtems/commit/?id=0ef6e3bfb9f763b4de46a8693d1e7cd59beb754e Author: Sebastian Huber Date: Thu Jul 24 17:50:58 2014 +0200 rbtree: Simplify _RBTree_Extract() --- cpukit/score/src/rbtreeextract.c | 18 ++++++++++-------- 1 files changed, 10 insertions(+), 8 deletions(-) diff --git a/cpukit/score/src/rbtreeextract.c b/cpukit/score/src/rbtreeextract.c index f3a7328..1aaba27 100644 --- a/cpukit/score/src/rbtreeextract.c +++ b/cpukit/score/src/rbtreeextract.c @@ -23,7 +23,6 @@ static void _RBTree_Extract_validate( RBTree_Node *the_node ) { RBTree_Node *parent; - RBTree_Direction dir; parent = the_node->parent; @@ -40,11 +39,13 @@ static void _RBTree_Extract_validate( RBTree_Node *the_node ) * update sibling pointer. */ if ( _RBTree_Is_red( sibling ) ) { + RBTree_Direction dir = _RBTree_Direction( the_node, parent ); + RBTree_Direction opp_dir = _RBTree_Opposite_direction( dir ); + parent->color = RBT_RED; sibling->color = RBT_BLACK; - dir = the_node != parent->child[ 0 ]; _RBTree_Rotate( parent, dir ); - sibling = parent->child[ _RBTree_Opposite_direction( dir ) ]; + sibling = parent->child[ opp_dir ]; } /* sibling is black, see if both of its children are also black. */ @@ -66,20 +67,21 @@ static void _RBTree_Extract_validate( RBTree_Node *the_node ) * and if so rotate in the proper direction and update sibling pointer. * Then switch the sibling and parent colors, and rotate through parent. */ - dir = the_node != parent->child[ 0 ]; + RBTree_Direction dir = _RBTree_Direction( the_node, parent ); + RBTree_Direction opp_dir = _RBTree_Opposite_direction( dir ); if ( - !_RBTree_Is_red( sibling->child[ _RBTree_Opposite_direction( dir ) ] ) + !_RBTree_Is_red( sibling->child[ opp_dir ] ) ) { sibling->color = RBT_RED; sibling->child[ dir ]->color = RBT_BLACK; - _RBTree_Rotate( sibling, _RBTree_Opposite_direction( dir ) ); - sibling = parent->child[ _RBTree_Opposite_direction( dir ) ]; + _RBTree_Rotate( sibling, opp_dir ); + sibling = parent->child[ opp_dir ]; } sibling->color = parent->color; parent->color = RBT_BLACK; - sibling->child[ _RBTree_Opposite_direction( dir ) ]->color = RBT_BLACK; + sibling->child[ opp_dir ]->color = RBT_BLACK; _RBTree_Rotate( parent, dir ); break; /* done */ } From sebh at rtems.org Thu Aug 7 13:51:57 2014 From: sebh at rtems.org (Sebastian Huber) Date: Thu, 07 Aug 2014 08:51:57 -0500 Subject: [rtems commit] rbtree: Simplify insert and extract Message-ID: <20140807135157.5CD9270072E@git.rtems.org> Module: rtems Branch: master Commit: 993f5acd25cc3d140689c7a0f2c1912da7b2f0f3 Changeset: http://git.rtems.org/rtems/commit/?id=993f5acd25cc3d140689c7a0f2c1912da7b2f0f3 Author: Sebastian Huber Date: Wed Jul 23 13:03:54 2014 +0200 rbtree: Simplify insert and extract Simplify _RBTree_Insert() and _RBTree_Extract(). Remove more superfluous NULL pointer checks. Change _RBTree_Is_root() to use only the node. Add parent parameter to _RBTree_Sibling(). Delete _RBTree_Grandparent() and _RBTree_Parent_sibling(). --- cpukit/sapi/include/rtems/rbtree.h | 12 +---- cpukit/score/include/rtems/score/rbtree.h | 44 +++++++++++++------ cpukit/score/include/rtems/score/rbtreeimpl.h | 53 ++++------------------- cpukit/score/src/rbtreeextract.c | 7 +-- cpukit/score/src/rbtreeinsert.c | 57 ++++++++++++++++--------- testsuites/sptests/sprbtree01/init.c | 14 ++---- 6 files changed, 87 insertions(+), 100 deletions(-) diff --git a/cpukit/sapi/include/rtems/rbtree.h b/cpukit/sapi/include/rtems/rbtree.h index 0e2ea2c..900506f 100644 --- a/cpukit/sapi/include/rtems/rbtree.h +++ b/cpukit/sapi/include/rtems/rbtree.h @@ -195,9 +195,7 @@ RTEMS_INLINE_ROUTINE rtems_rbtree_node *rtems_rbtree_right( } /** - * @brief Return pointer to the parent child node from this node. - * - * This function returns a pointer to the parent node of @a the_node. + * @copydoc _RBTree_Parent() */ RTEMS_INLINE_ROUTINE rtems_rbtree_node *rtems_rbtree_parent( const rtems_rbtree_node *the_node @@ -248,17 +246,13 @@ RTEMS_INLINE_ROUTINE bool rtems_rbtree_is_max( } /** - * @brief Is this node the RBTree root. - * - * This function returns true if @a the_node is the root of @a the_rbtree and - * false otherwise. + * @copydoc _RBTree_Is_root() */ RTEMS_INLINE_ROUTINE bool rtems_rbtree_is_root( - const rtems_rbtree_control *the_rbtree, const rtems_rbtree_node *the_node ) { - return _RBTree_Is_root( the_rbtree, the_node ); + return _RBTree_Is_root( the_node ); } /** diff --git a/cpukit/score/include/rtems/score/rbtree.h b/cpukit/score/include/rtems/score/rbtree.h index aa84558..299b75a 100644 --- a/cpukit/score/include/rtems/score/rbtree.h +++ b/cpukit/score/include/rtems/score/rbtree.h @@ -300,9 +300,16 @@ RTEMS_INLINE_ROUTINE bool _RBTree_Is_node_off_tree( } /** - * @brief Return pointer to RBTree's root node. + * @brief Returns a pointer to root node of the red-black tree. * - * This function returns a pointer to the root node of @a the_rbtree. + * The root node may change after insert or extract operations. + * + * @param[in] the_rbtree The red-black tree control. + * + * @retval NULL The tree is empty. + * @retval root The root node. + * + * @see _RBTree_Is_root(). */ RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Root( const RBTree_Control *the_rbtree @@ -326,15 +333,21 @@ RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_First( } /** - * @brief Return pointer to the parent of this node. + * @brief Returns a pointer to the parent of this node. + * + * The node must have a parent, thus it is invalid to use this function for the + * root node or a node that is not part of a tree. To test for the root node + * compare with _RBTree_Root() or use _RBTree_Is_root(). + * + * @param[in] the_node The node of interest. * - * This function returns a pointer to the parent node of @a the_node. + * @retval parent The parent of this node. + * @retval undefined The node is the root node or not part of a tree. */ RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Parent( const RBTree_Node *the_node ) { - if (!the_node->parent->parent) return NULL; return the_node->parent; } @@ -409,20 +422,25 @@ RTEMS_INLINE_ROUTINE bool _RBTree_Is_first( } /** - * @brief Is this node the RBTree root. - * - * This function returns true if @a the_node is the root of @a the_rbtree and + * @brief Returns true if this node is the root node of a red-black tree, and * false otherwise. * - * @retval true @a the_node is the root of @a the_rbtree. - * @retval false @a the_node is not the root of @a the_rbtree. + * The root node may change after insert or extract operations. In case the + * node is not a node of a tree, then this function yields unpredictable + * results. + * + * @param[in] the_node The node of interest. + * + * @retval true The node is the root node. + * @retval false Otherwise. + * + * @see _RBTree_Root(). */ RTEMS_INLINE_ROUTINE bool _RBTree_Is_root( - const RBTree_Control *the_rbtree, - const RBTree_Node *the_node + const RBTree_Node *the_node ) { - return (the_node == _RBTree_Root(the_rbtree)); + return _RBTree_Parent( _RBTree_Parent( the_node ) ) == NULL; } /** diff --git a/cpukit/score/include/rtems/score/rbtreeimpl.h b/cpukit/score/include/rtems/score/rbtreeimpl.h index 5f5e783..ed4cbd5 100644 --- a/cpukit/score/include/rtems/score/rbtreeimpl.h +++ b/cpukit/score/include/rtems/score/rbtreeimpl.h @@ -107,56 +107,23 @@ RTEMS_INLINE_ROUTINE bool _RBTree_Is_red( } /** - * @brief Return a pointer to node's grandparent. + * @brief Returns the sibling of the node. * - * This function returns a pointer to the grandparent of @a the_node if it - * exists, and NULL if not. - */ -RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Grandparent( - const RBTree_Node *the_node -) -{ - if(!the_node) return NULL; - if(!(the_node->parent)) return NULL; - if(!(the_node->parent->parent)) return NULL; - if(!(the_node->parent->parent->parent)) return NULL; - return(the_node->parent->parent); -} - -/** - * @brief Return a pointer to node's sibling. + * @param[in] the_node The node of interest. + * @param[in] parent The parent of the node. The parent must exist, thus it is + * invalid to use this function for the root node. * - * This function returns a pointer to the sibling of @a the_node if it - * exists, and NULL if not. + * @retval NULL No sibling exists. + * @retval sibling The sibling of the node. */ RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Sibling( - const RBTree_Node *the_node -) -{ - if(!the_node) return NULL; - if(!(the_node->parent)) return NULL; - if(!(the_node->parent->parent)) return NULL; - - if(the_node == the_node->parent->child[RBT_LEFT]) - return the_node->parent->child[RBT_RIGHT]; - else - return the_node->parent->child[RBT_LEFT]; -} - -/** - * @brief Return a pointer to node's parent's sibling. - * - * This function returns a pointer to the sibling of the parent of - * @a the_node if it exists, and NULL if not. - */ -RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Parent_sibling( - const RBTree_Node *the_node + const RBTree_Node *the_node, + const RBTree_Node *parent ) { - if(!the_node) return NULL; - if(_RBTree_Grandparent(the_node) == NULL) return NULL; + RBTree_Node *left_child = parent->child[ RBT_LEFT ]; - return _RBTree_Sibling(the_node->parent); + return the_node == left_child ? parent->child[ RBT_RIGHT ] : left_child; } RTEMS_INLINE_ROUTINE bool _RBTree_Is_equal( diff --git a/cpukit/score/src/rbtreeextract.c b/cpukit/score/src/rbtreeextract.c index a1896a9..f3a7328 100644 --- a/cpukit/score/src/rbtreeextract.c +++ b/cpukit/score/src/rbtreeextract.c @@ -22,7 +22,7 @@ */ static void _RBTree_Extract_validate( RBTree_Node *the_node ) { - RBTree_Node *parent, *sibling; + RBTree_Node *parent; RBTree_Direction dir; parent = the_node->parent; @@ -30,10 +30,10 @@ static void _RBTree_Extract_validate( RBTree_Node *the_node ) if ( !parent->parent ) return; - sibling = _RBTree_Sibling( the_node ); - /* continue to correct tree as long as the_node is black and not the root */ while ( !_RBTree_Is_red( the_node ) && parent->parent ) { + RBTree_Node *sibling = _RBTree_Sibling( the_node, parent ); + /* if sibling is red, switch parent (black) and sibling colors, * then rotate parent left, making the sibling be the_node's grandparent. * Now the_node has a black sibling and red parent. After rotation, @@ -59,7 +59,6 @@ static void _RBTree_Extract_validate( RBTree_Node *the_node ) the_node = parent; /* done if parent is red */ parent = the_node->parent; - sibling = _RBTree_Sibling( the_node ); } else { /* at least one of sibling's children is red. we now proceed in two * cases, either the_node is to the left or the right of the parent. diff --git a/cpukit/score/src/rbtreeinsert.c b/cpukit/score/src/rbtreeinsert.c index 3bccba5..a7be449 100644 --- a/cpukit/score/src/rbtreeinsert.c +++ b/cpukit/score/src/rbtreeinsert.c @@ -32,40 +32,55 @@ RTEMS_STATIC_ASSERT( */ static void _RBTree_Validate_insert( RBTree_Node *the_node ) { - RBTree_Node *u, *g; + RBTree_Node *parent = _RBTree_Parent( the_node ); + RBTree_Node *grandparent = _RBTree_Parent( parent ); /* note: the insert root case is handled already */ /* if the parent is black, nothing needs to be done * otherwise may need to loop a few times */ - while ( _RBTree_Is_red( _RBTree_Parent( the_node ) ) ) { - u = _RBTree_Parent_sibling( the_node ); - g = the_node->parent->parent; - - /* if uncle is red, repaint uncle/parent black and grandparent red */ - if ( _RBTree_Is_red( u ) ) { - the_node->parent->color = RBT_BLACK; - u->color = RBT_BLACK; - g->color = RBT_RED; - the_node = g; - } else { /* if uncle is black */ - RBTree_Direction dir = the_node != the_node->parent->child[ 0 ]; - RBTree_Direction pdir = the_node->parent != g->child[ 0 ]; + while ( parent->color == RBT_RED ) { + /* The root is black, so the grandparent must exist */ + RBTree_Node *uncle = _RBTree_Sibling( parent, grandparent ); + + /* + * If uncle exists and is red, repaint uncle/parent black and grandparent + * red. + */ + if ( uncle != NULL && uncle->color == RBT_RED ) { + parent->color = RBT_BLACK; + uncle->color = RBT_BLACK; + grandparent->color = RBT_RED; + the_node = grandparent; + parent = _RBTree_Parent( the_node ); + grandparent = _RBTree_Parent( parent ); + + if ( grandparent == NULL ) + break; + } else { /* If uncle does not exist or is black */ + RBTree_Direction dir = _RBTree_Direction( the_node, parent ); + RBTree_Direction parentdir = _RBTree_Direction( parent, grandparent ); /* ensure node is on the same branch direction as parent */ - if ( dir != pdir ) { - _RBTree_Rotate( the_node->parent, pdir ); - the_node = the_node->child[ pdir ]; + if ( dir != parentdir ) { + RBTree_Node *oldparent = parent; + + parent = the_node; + the_node = oldparent; + _RBTree_Rotate( oldparent, parentdir ); } - the_node->parent->color = RBT_BLACK; - g->color = RBT_RED; + parent->color = RBT_BLACK; + grandparent->color = RBT_RED; /* now rotate grandparent in the other branch direction (toward uncle) */ - _RBTree_Rotate( g, ( 1 - pdir ) ); + _RBTree_Rotate( grandparent, _RBTree_Opposite_direction( parentdir ) ); + + grandparent = _RBTree_Parent( parent ); + break; } } - if ( !the_node->parent->parent ) + if ( grandparent == NULL ) the_node->color = RBT_BLACK; } diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index 734530e..6a02a53 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -816,13 +816,13 @@ static bool visit_nodes( rtems_test_assert( td->key == tn->key ); if ( td->parent == NULL ) { - rtems_test_assert( td->parent == tn->Node.parent->parent ); + rtems_test_assert( rtems_rbtree_is_root( &tn->Node ) ); } else { - rtems_test_assert( td->parent == tn->Node.parent ); + rtems_test_assert( td->parent == rtems_rbtree_parent( &tn->Node ) ); } - rtems_test_assert( td->left == tn->Node.child[ RBT_LEFT ] ); - rtems_test_assert( td->right == tn->Node.child[ RBT_RIGHT ] ); + rtems_test_assert( td->left == rtems_rbtree_left( &tn->Node ) ); + rtems_test_assert( td->right == rtems_rbtree_right( &tn->Node ) ); rtems_test_assert( td->color == tn->Node.color ); ++ctx->current; @@ -1194,12 +1194,6 @@ rtems_task Init( rtems_task_argument ignored ) rtems_test_exit(0); } - if ( _RBTree_Sibling( NULL ) != NULL ) - puts ( "INIT - ERROR ON RBTREE NULL SIBLING MISMATCH" ); - if ( _RBTree_Sibling( rbtree1.root ) != NULL ) - puts ( "INIT - ERROR ON RBTREE NULL SIBLING MISMATCH" ); - if ( _RBTree_Grandparent( NULL ) != NULL ) - puts ( "INIT - ERROR ON RBTREE NULL GRANDPARENT MISMATCH" ); if ( _RBTree_Is_red( NULL ) != 0 ) puts ( "INIT - ERROR ON RBTREE NULL IS RED MISMATCH" ); if ( _RBTree_Is_red( rbtree1.root ) != 0 ) From sebh at rtems.org Thu Aug 7 13:51:57 2014 From: sebh at rtems.org (Sebastian Huber) Date: Thu, 07 Aug 2014 08:51:57 -0500 Subject: [rtems commit] rbtree: Simplify _RBTree_Rotate() Message-ID: <20140807135157.2B2997007F9@git.rtems.org> Module: rtems Branch: master Commit: 4752550f80206d7ab15daefb68532374f1b5a527 Changeset: http://git.rtems.org/rtems/commit/?id=4752550f80206d7ab15daefb68532374f1b5a527 Author: Sebastian Huber Date: Wed Jul 23 13:19:09 2014 +0200 rbtree: Simplify _RBTree_Rotate() Add and use _RBTree_Direction(). --- cpukit/score/include/rtems/score/rbtreeimpl.h | 78 +++++++++++++++++++----- testsuites/sptests/sprbtree01/init.c | 1 - 2 files changed, 61 insertions(+), 18 deletions(-) diff --git a/cpukit/score/include/rtems/score/rbtreeimpl.h b/cpukit/score/include/rtems/score/rbtreeimpl.h index 451b5f4..5f5e783 100644 --- a/cpukit/score/include/rtems/score/rbtreeimpl.h +++ b/cpukit/score/include/rtems/score/rbtreeimpl.h @@ -77,6 +77,21 @@ RTEMS_INLINE_ROUTINE RBTree_Direction _RBTree_Opposite_direction( } /** + * @brief Returns the direction of the node. + * + * @param[in] the_node The node of interest. + * @param[in] parent The parent of the node. The parent must exist, thus it is + * invalid to use this function for the root node. + */ +RTEMS_INLINE_ROUTINE RBTree_Direction _RBTree_Direction( + const RBTree_Node *the_node, + const RBTree_Node *parent +) +{ + return (RBTree_Direction) ( the_node != parent->child[ 0 ] ); +} + +/** * @brief Is this node red. * * This function returns true if @a the_node is red and false otherwise. @@ -166,32 +181,61 @@ RTEMS_INLINE_ROUTINE bool _RBTree_Is_lesser( } /** - * @brief Rotate the_node in the direction passed as second argument. + * @brief Rotates the node in the specified direction. * - * This routine rotates @a the_node to the direction @a dir, swapping - * @a the_node with its child\[@a dir\]. + * The node is swapped with its child in the opposite direction if it exists. + * + * Sub-tree before rotation: + * @dot + * digraph state { + * parent -> the_node; + * the_node -> sibling [label="dir"]; + * the_node -> child [label="opp_dir"]; + * child -> grandchild [label="dir"]; + * child -> grandchildsibling [label="opp_dir"]; + * } + * @enddot + * + * Sub-tree after rotation: + * @dot + * digraph state { + * parent -> child; + * the_node -> sibling [label="dir"]; + * the_node -> grandchild [label="opp_dir"]; + * child -> the_node [label="dir"]; + * child -> grandchildsibling [label="opp_dir"]; + * } + * @enddot + * + * @param[in] the_node The node to rotate. + * @param[in] dir The rotation direction. */ RTEMS_INLINE_ROUTINE void _RBTree_Rotate( - RBTree_Node *the_node, - RBTree_Direction dir - ) + RBTree_Node *the_node, + RBTree_Direction dir +) { - RBTree_Node *c; - if (the_node == NULL) return; - if (the_node->child[_RBTree_Opposite_direction(dir)] == NULL) return; + RBTree_Direction opp_dir = _RBTree_Opposite_direction( dir ); + RBTree_Node *child = the_node->child[ opp_dir ]; + RBTree_Node *grandchild; + RBTree_Node *parent; + + if ( child == NULL) + return; - c = the_node->child[_RBTree_Opposite_direction(dir)]; - the_node->child[_RBTree_Opposite_direction(dir)] = c->child[dir]; + grandchild = child->child[ dir ]; + the_node->child[ opp_dir ] = grandchild; - if (c->child[dir]) - c->child[dir]->parent = the_node; + if ( grandchild != NULL ) + grandchild->parent = the_node; - c->child[dir] = the_node; + child->child[ dir ] = the_node; - the_node->parent->child[the_node != the_node->parent->child[0]] = c; + parent = _RBTree_Parent( the_node ); + parent->child[ _RBTree_Direction( the_node, parent ) ] = child; - c->parent = the_node->parent; - the_node->parent = c; + child->parent = parent; + the_node->parent = child; } /** @} */ diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index ffb91b1..734530e 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -858,7 +858,6 @@ rtems_task Init( rtems_task_argument ignored ) rtems_test_assert( !rtems_rbtree_is_node_off_tree( &node1.Node ) ); - _RBTree_Rotate(NULL, RBT_LEFT); i = (node1.Node.parent == &node2.Node); _RBTree_Rotate( &node1.Node, !node1.Node.child[RBT_LEFT] ? RBT_RIGHT : RBT_LEFT From sebh at rtems.org Fri Aug 8 11:32:40 2014 From: sebh at rtems.org (Sebastian Huber) Date: Fri, 08 Aug 2014 06:32:40 -0500 Subject: [rtems commit] sptests/sprbtree01: Add random ops test case Message-ID: <20140808113240.50F477007F7@git.rtems.org> Module: rtems Branch: master Commit: 0b9fe3ec66ad6db3ac902665a5b6202502542ee7 Changeset: http://git.rtems.org/rtems/commit/?id=0b9fe3ec66ad6db3ac902665a5b6202502542ee7 Author: Sebastian Huber Date: Thu Aug 7 19:41:25 2014 +0200 sptests/sprbtree01: Add random ops test case --- testsuites/sptests/sprbtree01/init.c | 832 +++++++++++++++++++++++++- testsuites/sptests/sprbtree01/sprbtree01.scn | 1 + 2 files changed, 832 insertions(+), 1 deletions(-) diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index 6a02a53..22ed76c 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -812,7 +812,6 @@ static bool visit_nodes( rtems_test_assert( ctx->current < ctx->count ); - rtems_test_assert( td->key == tn->id ); rtems_test_assert( td->key == tn->key ); if ( td->parent == NULL ) { @@ -830,6 +829,836 @@ static bool visit_nodes( return false; } +static const test_node_description random_ops_tree_unique_1[] = { + { 0, NULL, NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_1[] = { + { 0, NULL, NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_2[] = { +}; + +static const test_node_description random_ops_tree_multiple_2[] = { +}; + +static const test_node_description random_ops_tree_unique_3[] = { + { 2, NULL, NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_3[] = { + { 1, NULL, NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_4[] = { + { 0, NULL, NULL, TN( 3 ), RBT_BLACK }, + { 3, TN( 0 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_4[] = { + { 0, NULL, NULL, TN( 3 ), RBT_BLACK }, + { 1, TN( 0 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_5[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, NULL, TN( 0 ), TN( 4 ), RBT_BLACK }, + { 4, TN( 1 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_5[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 0, NULL, TN( 0 ), TN( 4 ), RBT_BLACK }, + { 2, TN( 1 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_6[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 2, NULL, TN( 0 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_6[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 1, NULL, TN( 0 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_7[] = { + { 0, TN( 2 ), NULL, TN( 1 ), RBT_BLACK }, + { 1, TN( 0 ), NULL, NULL, RBT_RED }, + { 2, NULL, TN( 0 ), TN( 5 ), RBT_BLACK }, + { 4, TN( 5 ), NULL, NULL, RBT_RED }, + { 5, TN( 2 ), TN( 4 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_7[] = { + { 0, TN( 2 ), NULL, TN( 1 ), RBT_BLACK }, + { 0, TN( 0 ), NULL, NULL, RBT_RED }, + { 1, NULL, TN( 0 ), TN( 4 ), RBT_BLACK }, + { 2, TN( 4 ), NULL, NULL, RBT_RED }, + { 2, TN( 2 ), TN( 5 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_8[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 5 ), TN( 0 ), NULL, RBT_BLACK }, + { 5, NULL, TN( 1 ), TN( 6 ), RBT_BLACK }, + { 6, TN( 5 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_8[] = { + { 0, TN( 5 ), NULL, TN( 0 ), RBT_BLACK }, + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 2, NULL, TN( 1 ), TN( 6 ), RBT_BLACK }, + { 3, TN( 5 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_9[] = { + { 1, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 6 ), TN( 1 ), TN( 4 ), RBT_RED }, + { 4, TN( 2 ), NULL, TN( 5 ), RBT_BLACK }, + { 5, TN( 4 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 2 ), TN( 7 ), RBT_BLACK }, + { 7, TN( 6 ), NULL, TN( 8 ), RBT_BLACK }, + { 8, TN( 7 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_9[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 6 ), TN( 1 ), TN( 4 ), RBT_RED }, + { 2, TN( 2 ), NULL, TN( 5 ), RBT_BLACK }, + { 2, TN( 4 ), NULL, NULL, RBT_RED }, + { 3, NULL, TN( 2 ), TN( 7 ), RBT_BLACK }, + { 3, TN( 6 ), NULL, TN( 8 ), RBT_BLACK }, + { 4, TN( 7 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_10[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 6 ), TN( 0 ), TN( 4 ), RBT_RED }, + { 3, TN( 4 ), NULL, NULL, RBT_RED }, + { 4, TN( 2 ), TN( 3 ), NULL, RBT_BLACK }, + { 6, NULL, TN( 2 ), TN( 8 ), RBT_BLACK }, + { 8, TN( 6 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_10[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 6 ), TN( 0 ), TN( 4 ), RBT_RED }, + { 1, TN( 4 ), NULL, NULL, RBT_RED }, + { 2, TN( 2 ), TN( 3 ), NULL, RBT_BLACK }, + { 3, NULL, TN( 2 ), TN( 8 ), RBT_BLACK }, + { 4, TN( 6 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_11[] = { + { 2, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 6, NULL, TN( 2 ), TN( 8 ), RBT_BLACK }, + { 7, TN( 8 ), NULL, NULL, RBT_RED }, + { 8, TN( 6 ), TN( 7 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 8 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_11[] = { + { 1, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 3, NULL, TN( 2 ), TN( 8 ), RBT_BLACK }, + { 3, TN( 8 ), NULL, NULL, RBT_RED }, + { 4, TN( 6 ), TN( 7 ), TN( 9 ), RBT_BLACK }, + { 4, TN( 8 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_12[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 3 ), TN( 0 ), TN( 2 ), RBT_BLACK }, + { 2, TN( 1 ), NULL, NULL, RBT_RED }, + { 3, TN( 5 ), TN( 1 ), TN( 4 ), RBT_RED }, + { 4, TN( 3 ), NULL, NULL, RBT_BLACK }, + { 5, NULL, TN( 3 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 5 ), NULL, TN( 11 ), RBT_BLACK }, + { 11, TN( 9 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_12[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 0, TN( 5 ), TN( 0 ), TN( 3 ), RBT_RED }, + { 1, TN( 1 ), NULL, TN( 2 ), RBT_BLACK }, + { 1, TN( 3 ), NULL, NULL, RBT_RED }, + { 2, NULL, TN( 1 ), TN( 9 ), RBT_BLACK }, + { 2, TN( 9 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 5 ), TN( 4 ), TN( 11 ), RBT_RED }, + { 5, TN( 9 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_13[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 3 ), TN( 0 ), NULL, RBT_BLACK }, + { 3, NULL, TN( 1 ), TN( 8 ), RBT_BLACK }, + { 4, TN( 5 ), NULL, NULL, RBT_RED }, + { 5, TN( 8 ), TN( 4 ), TN( 6 ), RBT_BLACK }, + { 6, TN( 5 ), NULL, NULL, RBT_RED }, + { 8, TN( 3 ), TN( 5 ), TN( 11 ), RBT_RED }, + { 10, TN( 11 ), NULL, NULL, RBT_RED }, + { 11, TN( 8 ), TN( 10 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_13[] = { + { 0, TN( 0 ), NULL, NULL, RBT_BLACK }, + { 0, TN( 4 ), TN( 1 ), TN( 3 ), RBT_RED }, + { 1, TN( 0 ), NULL, NULL, RBT_BLACK }, + { 2, NULL, TN( 0 ), TN( 8 ), RBT_BLACK }, + { 2, TN( 6 ), NULL, NULL, RBT_RED }, + { 3, TN( 8 ), TN( 5 ), NULL, RBT_BLACK }, + { 4, TN( 4 ), TN( 6 ), TN( 11 ), RBT_RED }, + { 5, TN( 8 ), NULL, TN( 10 ), RBT_BLACK }, + { 5, TN( 11 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_14[] = { + { 3, TN( 6 ), NULL, TN( 5 ), RBT_BLACK }, + { 5, TN( 3 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 3 ), TN( 12 ), RBT_BLACK }, + { 8, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 12, TN( 6 ), TN( 8 ), TN( 13 ), RBT_RED }, + { 13, TN( 12 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_14[] = { + { 1, TN( 5 ), NULL, NULL, RBT_RED }, + { 2, TN( 6 ), TN( 3 ), NULL, RBT_BLACK }, + { 3, NULL, TN( 5 ), TN( 13 ), RBT_BLACK }, + { 4, TN( 13 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 6 ), TN( 8 ), TN( 12 ), RBT_RED }, + { 6, TN( 13 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_15[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 9 ), TN( 0 ), TN( 8 ), RBT_BLACK }, + { 7, TN( 8 ), NULL, NULL, RBT_RED }, + { 8, TN( 2 ), TN( 7 ), NULL, RBT_BLACK }, + { 9, NULL, TN( 2 ), TN( 12 ), RBT_BLACK }, + { 10, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 12, TN( 9 ), TN( 10 ), TN( 13 ), RBT_BLACK }, + { 13, TN( 12 ), NULL, TN( 14 ), RBT_BLACK }, + { 14, TN( 13 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_15[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 1, TN( 9 ), TN( 0 ), TN( 7 ), RBT_BLACK }, + { 3, TN( 2 ), NULL, NULL, RBT_RED }, + { 4, NULL, TN( 2 ), TN( 13 ), RBT_BLACK }, + { 4, TN( 13 ), NULL, TN( 10 ), RBT_BLACK }, + { 5, TN( 8 ), NULL, NULL, RBT_RED }, + { 6, TN( 9 ), TN( 8 ), TN( 12 ), RBT_RED }, + { 6, TN( 13 ), NULL, TN( 14 ), RBT_BLACK }, + { 7, TN( 12 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_16[] = { + { 0, TN( 5 ), NULL, TN( 3 ), RBT_BLACK }, + { 3, TN( 0 ), NULL, NULL, RBT_RED }, + { 5, NULL, TN( 0 ), TN( 10 ), RBT_BLACK }, + { 7, TN( 10 ), NULL, NULL, RBT_BLACK }, + { 10, TN( 5 ), TN( 7 ), TN( 12 ), RBT_RED }, + { 12, TN( 10 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_16[] = { + { 0, TN( 3 ), NULL, NULL, RBT_RED }, + { 1, TN( 7 ), TN( 0 ), TN( 5 ), RBT_BLACK }, + { 2, TN( 3 ), NULL, NULL, RBT_RED }, + { 3, NULL, TN( 3 ), TN( 12 ), RBT_BLACK }, + { 5, TN( 12 ), NULL, NULL, RBT_RED }, + { 6, TN( 7 ), TN( 10 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_17[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 5 ), TN( 0 ), TN( 3 ), RBT_BLACK }, + { 3, TN( 1 ), NULL, TN( 4 ), RBT_BLACK }, + { 4, TN( 3 ), NULL, NULL, RBT_RED }, + { 5, NULL, TN( 1 ), TN( 9 ), RBT_BLACK }, + { 7, TN( 9 ), NULL, TN( 8 ), RBT_BLACK }, + { 8, TN( 7 ), NULL, NULL, RBT_RED }, + { 9, TN( 5 ), TN( 7 ), TN( 16 ), RBT_BLACK }, + { 16, TN( 9 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_17[] = { + { 0, TN( 0 ), NULL, NULL, RBT_BLACK }, + { 0, TN( 5 ), TN( 1 ), TN( 3 ), RBT_BLACK }, + { 1, TN( 0 ), NULL, NULL, RBT_BLACK }, + { 2, NULL, TN( 0 ), TN( 9 ), RBT_BLACK }, + { 2, TN( 9 ), NULL, TN( 7 ), RBT_BLACK }, + { 3, TN( 4 ), NULL, NULL, RBT_RED }, + { 4, TN( 5 ), TN( 4 ), TN( 16 ), RBT_BLACK }, + { 4, TN( 16 ), NULL, NULL, RBT_RED }, + { 8, TN( 9 ), TN( 8 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_18[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 3 ), TN( 0 ), TN( 2 ), RBT_BLACK }, + { 2, TN( 1 ), NULL, NULL, RBT_RED }, + { 3, TN( 6 ), TN( 1 ), TN( 4 ), RBT_BLACK }, + { 4, TN( 3 ), NULL, TN( 5 ), RBT_BLACK }, + { 5, TN( 4 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 3 ), TN( 14 ), RBT_BLACK }, + { 7, TN( 8 ), NULL, NULL, RBT_RED }, + { 8, TN( 10 ), TN( 7 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 8 ), NULL, NULL, RBT_RED }, + { 10, TN( 14 ), TN( 8 ), TN( 12 ), RBT_RED }, + { 12, TN( 10 ), NULL, NULL, RBT_BLACK }, + { 14, TN( 6 ), TN( 10 ), TN( 17 ), RBT_BLACK }, + { 17, TN( 14 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_18[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 0, TN( 2 ), TN( 0 ), TN( 3 ), RBT_BLACK }, + { 1, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 6 ), TN( 1 ), TN( 4 ), RBT_BLACK }, + { 2, TN( 2 ), NULL, TN( 5 ), RBT_BLACK }, + { 2, TN( 4 ), NULL, NULL, RBT_RED }, + { 3, NULL, TN( 2 ), TN( 12 ), RBT_BLACK }, + { 3, TN( 8 ), NULL, NULL, RBT_RED }, + { 4, TN( 9 ), TN( 7 ), NULL, RBT_BLACK }, + { 4, TN( 12 ), TN( 8 ), TN( 10 ), RBT_RED }, + { 5, TN( 9 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 6 ), TN( 9 ), TN( 14 ), RBT_BLACK }, + { 7, TN( 12 ), NULL, TN( 17 ), RBT_BLACK }, + { 8, TN( 14 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_19[] = { + { 1, TN( 2 ), NULL, NULL, RBT_RED }, + { 2, TN( 6 ), TN( 1 ), NULL, RBT_BLACK }, + { 6, TN( 9 ), TN( 2 ), TN( 8 ), RBT_BLACK }, + { 8, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 9, NULL, TN( 6 ), TN( 12 ), RBT_BLACK }, + { 11, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 12, TN( 9 ), TN( 11 ), TN( 16 ), RBT_BLACK }, + { 14, TN( 16 ), NULL, NULL, RBT_RED }, + { 16, TN( 12 ), TN( 14 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_19[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 1, TN( 6 ), TN( 1 ), NULL, RBT_BLACK }, + { 3, TN( 8 ), TN( 2 ), TN( 9 ), RBT_BLACK }, + { 4, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 4, NULL, TN( 6 ), TN( 12 ), RBT_BLACK }, + { 5, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 8 ), TN( 11 ), TN( 16 ), RBT_BLACK }, + { 7, TN( 16 ), NULL, NULL, RBT_RED }, + { 8, TN( 12 ), TN( 14 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_20[] = { + { 0, TN( 3 ), NULL, TN( 1 ), RBT_BLACK }, + { 1, TN( 0 ), NULL, NULL, RBT_RED }, + { 3, TN( 9 ), TN( 0 ), TN( 4 ), RBT_RED }, + { 4, TN( 3 ), NULL, TN( 7 ), RBT_BLACK }, + { 7, TN( 4 ), NULL, NULL, RBT_RED }, + { 9, NULL, TN( 3 ), TN( 14 ), RBT_BLACK }, + { 10, TN( 14 ), NULL, TN( 12 ), RBT_BLACK }, + { 12, TN( 10 ), NULL, NULL, RBT_RED }, + { 14, TN( 9 ), TN( 10 ), TN( 18 ), RBT_RED }, + { 17, TN( 18 ), NULL, NULL, RBT_RED }, + { 18, TN( 14 ), TN( 17 ), TN( 19 ), RBT_BLACK }, + { 19, TN( 18 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_20[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 0, TN( 4 ), TN( 0 ), TN( 3 ), RBT_BLACK }, + { 1, TN( 1 ), NULL, NULL, RBT_RED }, + { 2, TN( 9 ), TN( 1 ), TN( 7 ), RBT_BLACK }, + { 3, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, NULL, TN( 4 ), TN( 12 ), RBT_BLACK }, + { 5, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 9 ), TN( 10 ), TN( 17 ), RBT_BLACK }, + { 7, TN( 17 ), NULL, NULL, RBT_BLACK }, + { 8, TN( 12 ), TN( 14 ), TN( 18 ), RBT_RED }, + { 9, TN( 17 ), NULL, TN( 19 ), RBT_BLACK }, + { 9, TN( 18 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_21[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 8 ), TN( 0 ), TN( 4 ), RBT_BLACK }, + { 3, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 1 ), TN( 3 ), TN( 5 ), RBT_RED }, + { 5, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 8, NULL, TN( 1 ), TN( 13 ), RBT_BLACK }, + { 11, TN( 13 ), NULL, NULL, RBT_BLACK }, + { 13, TN( 8 ), TN( 11 ), TN( 16 ), RBT_BLACK }, + { 15, TN( 16 ), NULL, NULL, RBT_BLACK }, + { 16, TN( 13 ), TN( 15 ), TN( 17 ), RBT_RED }, + { 17, TN( 16 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_21[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 0, TN( 8 ), TN( 0 ), TN( 4 ), RBT_BLACK }, + { 1, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 1 ), TN( 3 ), TN( 5 ), RBT_RED }, + { 2, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, NULL, TN( 1 ), TN( 13 ), RBT_BLACK }, + { 5, TN( 13 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 8 ), TN( 11 ), TN( 17 ), RBT_BLACK }, + { 7, TN( 17 ), NULL, NULL, RBT_BLACK }, + { 8, TN( 13 ), TN( 15 ), TN( 16 ), RBT_RED }, + { 8, TN( 17 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_22[] = { + { 1, TN( 3 ), NULL, TN( 2 ), RBT_BLACK }, + { 2, TN( 1 ), NULL, NULL, RBT_RED }, + { 3, TN( 8 ), TN( 1 ), TN( 4 ), RBT_BLACK }, + { 4, TN( 3 ), NULL, TN( 7 ), RBT_BLACK }, + { 7, TN( 4 ), NULL, NULL, RBT_RED }, + { 8, NULL, TN( 3 ), TN( 14 ), RBT_BLACK }, + { 10, TN( 11 ), NULL, NULL, RBT_RED }, + { 11, TN( 14 ), TN( 10 ), NULL, RBT_BLACK }, + { 14, TN( 8 ), TN( 11 ), TN( 18 ), RBT_BLACK }, + { 15, TN( 18 ), NULL, NULL, RBT_BLACK }, + { 18, TN( 14 ), TN( 15 ), TN( 21 ), RBT_RED }, + { 21, TN( 18 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_22[] = { + { 0, TN( 3 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 8 ), TN( 1 ), TN( 4 ), RBT_BLACK }, + { 1, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 3 ), TN( 2 ), TN( 7 ), RBT_RED }, + { 3, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, NULL, TN( 3 ), TN( 14 ), RBT_BLACK }, + { 5, TN( 14 ), NULL, TN( 10 ), RBT_BLACK }, + { 5, TN( 11 ), NULL, NULL, RBT_RED }, + { 7, TN( 8 ), TN( 11 ), TN( 18 ), RBT_BLACK }, + { 7, TN( 18 ), NULL, NULL, RBT_BLACK }, + { 9, TN( 14 ), TN( 15 ), TN( 21 ), RBT_RED }, + { 10, TN( 18 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_23[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 8 ), TN( 0 ), TN( 7 ), RBT_BLACK }, + { 7, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 8, NULL, TN( 2 ), TN( 16 ), RBT_BLACK }, + { 11, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 12, TN( 16 ), TN( 11 ), TN( 14 ), RBT_RED }, + { 13, TN( 14 ), NULL, NULL, RBT_RED }, + { 14, TN( 12 ), TN( 13 ), TN( 15 ), RBT_BLACK }, + { 15, TN( 14 ), NULL, NULL, RBT_RED }, + { 16, TN( 8 ), TN( 12 ), TN( 20 ), RBT_BLACK }, + { 17, TN( 20 ), NULL, NULL, RBT_RED }, + { 20, TN( 16 ), TN( 17 ), TN( 21 ), RBT_BLACK }, + { 21, TN( 20 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_23[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 8 ), TN( 0 ), TN( 7 ), RBT_RED }, + { 3, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 12 ), TN( 2 ), TN( 11 ), RBT_BLACK }, + { 5, TN( 8 ), NULL, NULL, RBT_BLACK }, + { 6, NULL, TN( 8 ), TN( 17 ), RBT_BLACK }, + { 6, TN( 15 ), NULL, NULL, RBT_BLACK }, + { 7, TN( 17 ), TN( 13 ), TN( 16 ), RBT_RED }, + { 7, TN( 16 ), NULL, NULL, RBT_RED }, + { 8, TN( 15 ), TN( 14 ), NULL, RBT_BLACK }, + { 8, TN( 12 ), TN( 15 ), TN( 20 ), RBT_BLACK }, + { 10, TN( 17 ), NULL, TN( 21 ), RBT_BLACK }, + { 10, TN( 20 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_24[] = { + { 4, TN( 5 ), NULL, NULL, RBT_BLACK }, + { 5, TN( 8 ), TN( 4 ), TN( 6 ), RBT_RED }, + { 6, TN( 5 ), NULL, NULL, RBT_BLACK }, + { 8, TN( 14 ), TN( 5 ), TN( 10 ), RBT_BLACK }, + { 10, TN( 8 ), NULL, NULL, RBT_BLACK }, + { 14, NULL, TN( 8 ), TN( 20 ), RBT_BLACK }, + { 15, TN( 16 ), NULL, NULL, RBT_RED }, + { 16, TN( 20 ), TN( 15 ), NULL, RBT_BLACK }, + { 20, TN( 14 ), TN( 16 ), TN( 22 ), RBT_BLACK }, + { 22, TN( 20 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_24[] = { + { 2, TN( 6 ), NULL, TN( 5 ), RBT_BLACK }, + { 2, TN( 4 ), NULL, NULL, RBT_RED }, + { 3, TN( 10 ), TN( 4 ), TN( 8 ), RBT_BLACK }, + { 4, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 5, NULL, TN( 6 ), TN( 16 ), RBT_BLACK }, + { 7, TN( 16 ), NULL, TN( 15 ), RBT_BLACK }, + { 7, TN( 14 ), NULL, NULL, RBT_RED }, + { 8, TN( 10 ), TN( 14 ), TN( 22 ), RBT_BLACK }, + { 10, TN( 22 ), NULL, NULL, RBT_RED }, + { 11, TN( 16 ), TN( 20 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_25[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 13 ), TN( 0 ), TN( 4 ), RBT_BLACK }, + { 3, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 1 ), TN( 3 ), TN( 6 ), RBT_RED }, + { 5, TN( 6 ), NULL, NULL, RBT_RED }, + { 6, TN( 4 ), TN( 5 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 6 ), NULL, NULL, RBT_RED }, + { 13, NULL, TN( 1 ), TN( 19 ), RBT_BLACK }, + { 14, TN( 15 ), NULL, NULL, RBT_RED }, + { 15, TN( 16 ), TN( 14 ), NULL, RBT_BLACK }, + { 16, TN( 19 ), TN( 15 ), TN( 17 ), RBT_RED }, + { 17, TN( 16 ), NULL, NULL, RBT_BLACK }, + { 19, TN( 13 ), TN( 16 ), TN( 23 ), RBT_BLACK }, + { 23, TN( 19 ), NULL, TN( 24 ), RBT_BLACK }, + { 24, TN( 23 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_25[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 0, TN( 5 ), TN( 0 ), TN( 3 ), RBT_RED }, + { 1, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 13 ), TN( 1 ), TN( 6 ), RBT_BLACK }, + { 2, TN( 6 ), NULL, NULL, RBT_RED }, + { 3, TN( 5 ), TN( 4 ), TN( 9 ), RBT_BLACK }, + { 4, TN( 6 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 5 ), TN( 19 ), RBT_BLACK }, + { 7, TN( 17 ), NULL, TN( 14 ), RBT_BLACK }, + { 7, TN( 15 ), NULL, NULL, RBT_RED }, + { 8, TN( 19 ), TN( 15 ), TN( 16 ), RBT_RED }, + { 8, TN( 17 ), NULL, NULL, RBT_BLACK }, + { 9, TN( 13 ), TN( 17 ), TN( 23 ), RBT_BLACK }, + { 11, TN( 19 ), NULL, TN( 24 ), RBT_BLACK }, + { 12, TN( 23 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_26[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 6 ), TN( 0 ), TN( 3 ), RBT_BLACK }, + { 3, TN( 1 ), NULL, NULL, RBT_RED }, + { 6, TN( 11 ), TN( 1 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 6 ), NULL, TN( 10 ), RBT_BLACK }, + { 10, TN( 9 ), NULL, NULL, RBT_RED }, + { 11, NULL, TN( 6 ), TN( 14 ), RBT_BLACK }, + { 12, TN( 14 ), NULL, TN( 13 ), RBT_BLACK }, + { 13, TN( 12 ), NULL, NULL, RBT_RED }, + { 14, TN( 11 ), TN( 12 ), TN( 20 ), RBT_BLACK }, + { 18, TN( 20 ), NULL, NULL, RBT_BLACK }, + { 20, TN( 14 ), TN( 18 ), TN( 23 ), RBT_RED }, + { 21, TN( 23 ), NULL, NULL, RBT_RED }, + { 23, TN( 20 ), TN( 21 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_26[] = { + { 0, TN( 0 ), NULL, NULL, RBT_RED }, + { 0, TN( 6 ), TN( 1 ), TN( 3 ), RBT_BLACK }, + { 1, TN( 0 ), NULL, NULL, RBT_RED }, + { 3, TN( 12 ), TN( 0 ), TN( 11 ), RBT_BLACK }, + { 4, TN( 11 ), NULL, NULL, RBT_RED }, + { 5, TN( 6 ), TN( 9 ), TN( 10 ), RBT_BLACK }, + { 5, TN( 11 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 6 ), TN( 18 ), RBT_BLACK }, + { 6, TN( 14 ), NULL, NULL, RBT_RED }, + { 7, TN( 18 ), TN( 13 ), NULL, RBT_BLACK }, + { 9, TN( 12 ), TN( 14 ), TN( 21 ), RBT_BLACK }, + { 10, TN( 21 ), NULL, NULL, RBT_RED }, + { 10, TN( 18 ), TN( 20 ), TN( 23 ), RBT_BLACK }, + { 11, TN( 21 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_27[] = { + { 3, TN( 8 ), NULL, NULL, RBT_BLACK }, + { 8, TN( 19 ), TN( 3 ), TN( 17 ), RBT_RED }, + { 12, TN( 17 ), NULL, NULL, RBT_RED }, + { 17, TN( 8 ), TN( 12 ), NULL, RBT_BLACK }, + { 19, NULL, TN( 8 ), TN( 23 ), RBT_BLACK }, + { 20, TN( 23 ), NULL, TN( 21 ), RBT_BLACK }, + { 21, TN( 20 ), NULL, NULL, RBT_RED }, + { 23, TN( 19 ), TN( 20 ), TN( 25 ), RBT_RED }, + { 24, TN( 25 ), NULL, NULL, RBT_RED }, + { 25, TN( 23 ), TN( 24 ), TN( 26 ), RBT_BLACK }, + { 26, TN( 25 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_27[] = { + { 1, TN( 8 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 19 ), TN( 3 ), TN( 17 ), RBT_RED }, + { 6, TN( 17 ), NULL, NULL, RBT_RED }, + { 8, TN( 8 ), TN( 12 ), NULL, RBT_BLACK }, + { 9, NULL, TN( 8 ), TN( 23 ), RBT_BLACK }, + { 10, TN( 23 ), NULL, TN( 21 ), RBT_BLACK }, + { 10, TN( 20 ), NULL, NULL, RBT_RED }, + { 11, TN( 19 ), TN( 20 ), TN( 24 ), RBT_RED }, + { 12, TN( 24 ), NULL, NULL, RBT_RED }, + { 12, TN( 23 ), TN( 25 ), TN( 26 ), RBT_BLACK }, + { 13, TN( 24 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_28[] = { + { 0, TN( 5 ), NULL, NULL, RBT_BLACK }, + { 5, TN( 13 ), TN( 0 ), TN( 7 ), RBT_RED }, + { 7, TN( 5 ), NULL, NULL, RBT_BLACK }, + { 13, NULL, TN( 5 ), TN( 17 ), RBT_BLACK }, + { 15, TN( 17 ), NULL, NULL, RBT_BLACK }, + { 17, TN( 13 ), TN( 15 ), TN( 26 ), RBT_RED }, + { 21, TN( 26 ), NULL, NULL, RBT_RED }, + { 26, TN( 17 ), TN( 21 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_28[] = { + { 0, TN( 5 ), NULL, NULL, RBT_RED }, + { 2, TN( 7 ), TN( 0 ), NULL, RBT_BLACK }, + { 3, NULL, TN( 5 ), TN( 15 ), RBT_BLACK }, + { 6, TN( 15 ), NULL, NULL, RBT_BLACK }, + { 7, TN( 7 ), TN( 13 ), TN( 21 ), RBT_RED }, + { 8, TN( 21 ), NULL, NULL, RBT_RED }, + { 10, TN( 15 ), TN( 17 ), TN( 26 ), RBT_BLACK }, + { 13, TN( 21 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_29[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 4 ), TN( 0 ), TN( 3 ), RBT_BLACK }, + { 3, TN( 1 ), NULL, NULL, RBT_RED }, + { 4, TN( 11 ), TN( 1 ), TN( 7 ), RBT_BLACK }, + { 6, TN( 7 ), NULL, NULL, RBT_RED }, + { 7, TN( 4 ), TN( 6 ), TN( 8 ), RBT_BLACK }, + { 8, TN( 7 ), NULL, NULL, RBT_RED }, + { 11, NULL, TN( 4 ), TN( 13 ), RBT_BLACK }, + { 12, TN( 13 ), NULL, NULL, RBT_BLACK }, + { 13, TN( 11 ), TN( 12 ), TN( 22 ), RBT_BLACK }, + { 14, TN( 17 ), NULL, NULL, RBT_RED }, + { 17, TN( 22 ), TN( 14 ), NULL, RBT_BLACK }, + { 22, TN( 13 ), TN( 17 ), TN( 25 ), RBT_RED }, + { 25, TN( 22 ), NULL, TN( 27 ), RBT_BLACK }, + { 27, TN( 25 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_29[] = { + { 0, TN( 3 ), NULL, TN( 1 ), RBT_BLACK }, + { 0, TN( 0 ), NULL, NULL, RBT_RED }, + { 1, TN( 11 ), TN( 0 ), TN( 6 ), RBT_BLACK }, + { 2, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 3, TN( 3 ), TN( 4 ), TN( 7 ), RBT_RED }, + { 3, TN( 6 ), NULL, TN( 8 ), RBT_BLACK }, + { 4, TN( 7 ), NULL, NULL, RBT_RED }, + { 5, NULL, TN( 3 ), TN( 12 ), RBT_BLACK }, + { 6, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 11 ), TN( 13 ), TN( 22 ), RBT_BLACK }, + { 7, TN( 17 ), NULL, NULL, RBT_RED }, + { 8, TN( 22 ), TN( 14 ), NULL, RBT_BLACK }, + { 11, TN( 12 ), TN( 17 ), TN( 25 ), RBT_RED }, + { 12, TN( 22 ), NULL, TN( 27 ), RBT_BLACK }, + { 13, TN( 25 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_30[] = { + { 0, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 12 ), TN( 0 ), TN( 8 ), RBT_RED }, + { 6, TN( 8 ), NULL, NULL, RBT_RED }, + { 8, TN( 4 ), TN( 6 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 8 ), NULL, NULL, RBT_RED }, + { 12, TN( 14 ), TN( 4 ), TN( 13 ), RBT_BLACK }, + { 13, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 14, NULL, TN( 12 ), TN( 17 ), RBT_BLACK }, + { 16, TN( 17 ), NULL, NULL, RBT_BLACK }, + { 17, TN( 14 ), TN( 16 ), TN( 20 ), RBT_BLACK }, + { 18, TN( 20 ), NULL, NULL, RBT_BLACK }, + { 20, TN( 17 ), TN( 18 ), TN( 28 ), RBT_RED }, + { 27, TN( 28 ), NULL, NULL, RBT_RED }, + { 28, TN( 20 ), TN( 27 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_30[] = { + { 0, TN( 4 ), NULL, NULL, RBT_RED }, + { 2, TN( 6 ), TN( 0 ), NULL, RBT_BLACK }, + { 3, TN( 12 ), TN( 4 ), TN( 8 ), RBT_RED }, + { 4, TN( 8 ), NULL, NULL, RBT_RED }, + { 4, TN( 6 ), TN( 9 ), TN( 13 ), RBT_BLACK }, + { 6, TN( 8 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 6 ), TN( 18 ), RBT_BLACK }, + { 7, TN( 17 ), NULL, NULL, RBT_RED }, + { 8, TN( 18 ), TN( 14 ), TN( 16 ), RBT_BLACK }, + { 8, TN( 17 ), NULL, NULL, RBT_RED }, + { 9, TN( 12 ), TN( 17 ), TN( 27 ), RBT_RED }, + { 10, TN( 27 ), NULL, NULL, RBT_RED }, + { 13, TN( 18 ), TN( 20 ), TN( 28 ), RBT_BLACK }, + { 14, TN( 27 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_31[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 2, TN( 5 ), TN( 0 ), NULL, RBT_BLACK }, + { 5, TN( 14 ), TN( 2 ), TN( 9 ), RBT_BLACK }, + { 7, TN( 9 ), NULL, NULL, RBT_RED }, + { 9, TN( 5 ), TN( 7 ), TN( 11 ), RBT_BLACK }, + { 11, TN( 9 ), NULL, NULL, RBT_RED }, + { 14, NULL, TN( 5 ), TN( 21 ), RBT_BLACK }, + { 16, TN( 21 ), NULL, TN( 18 ), RBT_BLACK }, + { 18, TN( 16 ), NULL, NULL, RBT_RED }, + { 21, TN( 14 ), TN( 16 ), TN( 30 ), RBT_BLACK }, + { 30, TN( 21 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_31[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 1, TN( 5 ), TN( 0 ), NULL, RBT_BLACK }, + { 2, TN( 11 ), TN( 2 ), TN( 9 ), RBT_BLACK }, + { 3, TN( 9 ), NULL, NULL, RBT_RED }, + { 4, TN( 5 ), TN( 7 ), NULL, RBT_BLACK }, + { 5, NULL, TN( 5 ), TN( 21 ), RBT_BLACK }, + { 7, TN( 16 ), NULL, NULL, RBT_RED }, + { 8, TN( 21 ), TN( 14 ), TN( 18 ), RBT_BLACK }, + { 9, TN( 16 ), NULL, NULL, RBT_RED }, + { 10, TN( 11 ), TN( 16 ), TN( 30 ), RBT_BLACK }, + { 15, TN( 21 ), NULL, NULL, RBT_BLACK } +}; + +#define RANDOM_OPS_TREE( i ) \ + { &random_ops_tree_multiple_ ## i[ 0 ], &random_ops_tree_unique_ ## i[ 0 ] } + +static const test_node_description *const random_ops_trees[][2] = { + RANDOM_OPS_TREE( 1 ), + RANDOM_OPS_TREE( 2 ), + RANDOM_OPS_TREE( 3 ), + RANDOM_OPS_TREE( 4 ), + RANDOM_OPS_TREE( 5 ), + RANDOM_OPS_TREE( 6 ), + RANDOM_OPS_TREE( 7 ), + RANDOM_OPS_TREE( 8 ), + RANDOM_OPS_TREE( 9 ), + RANDOM_OPS_TREE( 10 ), + RANDOM_OPS_TREE( 11 ), + RANDOM_OPS_TREE( 12 ), + RANDOM_OPS_TREE( 13 ), + RANDOM_OPS_TREE( 14 ), + RANDOM_OPS_TREE( 15 ), + RANDOM_OPS_TREE( 16 ), + RANDOM_OPS_TREE( 17 ), + RANDOM_OPS_TREE( 18 ), + RANDOM_OPS_TREE( 19 ), + RANDOM_OPS_TREE( 20 ), + RANDOM_OPS_TREE( 21 ), + RANDOM_OPS_TREE( 22 ), + RANDOM_OPS_TREE( 23 ), + RANDOM_OPS_TREE( 24 ), + RANDOM_OPS_TREE( 25 ), + RANDOM_OPS_TREE( 26 ), + RANDOM_OPS_TREE( 27 ), + RANDOM_OPS_TREE( 28 ), + RANDOM_OPS_TREE( 29 ), + RANDOM_OPS_TREE( 30 ), + RANDOM_OPS_TREE( 31 ) +}; + +#define RANDOM_OPS_TREE_COUNT( i ) \ + { \ + RTEMS_ARRAY_SIZE( random_ops_tree_multiple_ ## i ), \ + RTEMS_ARRAY_SIZE( random_ops_tree_unique_ ## i ) \ + } + +static const size_t random_ops_tree_counts[][2] = { + RANDOM_OPS_TREE_COUNT( 1 ), + RANDOM_OPS_TREE_COUNT( 2 ), + RANDOM_OPS_TREE_COUNT( 3 ), + RANDOM_OPS_TREE_COUNT( 4 ), + RANDOM_OPS_TREE_COUNT( 5 ), + RANDOM_OPS_TREE_COUNT( 6 ), + RANDOM_OPS_TREE_COUNT( 7 ), + RANDOM_OPS_TREE_COUNT( 8 ), + RANDOM_OPS_TREE_COUNT( 9 ), + RANDOM_OPS_TREE_COUNT( 10 ), + RANDOM_OPS_TREE_COUNT( 11 ), + RANDOM_OPS_TREE_COUNT( 12 ), + RANDOM_OPS_TREE_COUNT( 13 ), + RANDOM_OPS_TREE_COUNT( 14 ), + RANDOM_OPS_TREE_COUNT( 15 ), + RANDOM_OPS_TREE_COUNT( 16 ), + RANDOM_OPS_TREE_COUNT( 17 ), + RANDOM_OPS_TREE_COUNT( 18 ), + RANDOM_OPS_TREE_COUNT( 19 ), + RANDOM_OPS_TREE_COUNT( 20 ), + RANDOM_OPS_TREE_COUNT( 21 ), + RANDOM_OPS_TREE_COUNT( 22 ), + RANDOM_OPS_TREE_COUNT( 23 ), + RANDOM_OPS_TREE_COUNT( 24 ), + RANDOM_OPS_TREE_COUNT( 25 ), + RANDOM_OPS_TREE_COUNT( 26 ), + RANDOM_OPS_TREE_COUNT( 27 ), + RANDOM_OPS_TREE_COUNT( 28 ), + RANDOM_OPS_TREE_COUNT( 29 ), + RANDOM_OPS_TREE_COUNT( 30 ), + RANDOM_OPS_TREE_COUNT( 31 ) +}; + +static uint32_t simple_random( uint32_t v ) +{ + v *= 1664525; + v += 1013904223; + + return v; +} + +static void random_ops( size_t n, bool unique ) +{ + visitor_context ctx = { + 0, + random_ops_tree_counts[ n - 1 ][ unique ], + random_ops_trees[ n - 1 ][ unique ] + }; + rtems_rbtree_control tree; + test_node *nodes = &node_array[ 0 ]; + size_t m = n * n * n; + size_t s = unique ? 1 : 2; + uint32_t v = 0xdeadbeef; + size_t i; + + rtems_rbtree_initialize_empty( &tree ); + + memset( nodes, 0, n * sizeof( *nodes ) ); + + for ( i = 0; i < n; ++i ) { + nodes[ i ].key = (int) ( i / s ); + } + + for ( i = 0; i < m; ++i ) { + size_t j = ( v >> 13 ) % n; + test_node *tn = &nodes[ j ]; + + if ( tn->id == 0 ) { + tn->id = 1; + rtems_rbtree_insert( &tree, &tn->Node, test_compare_function, unique ); + } else { + tn->id = 0; + rtems_rbtree_extract( &tree, &tn->Node ); + } + + rtems_test_assert( rb_assert( tree.root ) != -1 ); + + v = simple_random( v ); + } + + _RBTree_Iterate( &tree, RBT_RIGHT, visit_nodes, &ctx ); + rtems_test_assert( ctx.current == ctx.count ); +} + +static void test_rbtree_random_ops( void ) +{ + size_t n; + + puts( "INIT - Random operations" ); + + for ( n = 1; n < RTEMS_ARRAY_SIZE( random_ops_trees ); ++n ) { + random_ops( n, true ); + random_ops( n, false ); + } +} + rtems_task Init( rtems_task_argument ignored ) { rtems_rbtree_control rbtree1; @@ -1387,6 +2216,7 @@ rtems_task Init( rtems_task_argument ignored ) } test_rbtree_min_max(); + test_rbtree_random_ops(); TEST_END(); rtems_test_exit(0); diff --git a/testsuites/sptests/sprbtree01/sprbtree01.scn b/testsuites/sptests/sprbtree01/sprbtree01.scn index 73491be..a18a17f 100644 --- a/testsuites/sptests/sprbtree01/sprbtree01.scn +++ b/testsuites/sptests/sprbtree01/sprbtree01.scn @@ -32,4 +32,5 @@ INIT - Verify rtems_rbtree_insert with 100 nodes value [99,0] INIT - Verify rtems_rbtree_find in a duplicate tree INIT - Removing 100 nodes INIT - Verify min/max node updates +INIT - Random operations *** END OF TEST SPRBTREE 1 *** From sebh at rtems.org Mon Aug 11 06:02:44 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 11 Aug 2014 01:02:44 -0500 Subject: [rtems commit] bsp/altera-cyclone-v: Add socal from hwlib. Message-ID: <20140811060246.78B90700340@git.rtems.org> Module: rtems Branch: master Commit: 1642d27e4c0b0f057430f5a5a3d00209db1aa1ca Changeset: http://git.rtems.org/rtems/commit/?id=1642d27e4c0b0f057430f5a5a3d00209db1aa1ca Author: Christian Mauderer Date: Fri Jul 18 12:29:29 2014 +0200 bsp/altera-cyclone-v: Add socal from hwlib. Some of the headers from the hwlib need the files from the socal subdirectory. --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 17 +++++++- .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 45 ++++++++++++++++++++ 2 files changed, 60 insertions(+), 2 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index 6d7115b..e92e728 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -10,6 +10,7 @@ ACLOCAL_AMFLAGS = -I ../../../../aclocal include $(top_srcdir)/../../../../automake/compile.am include_bspdir = $(includedir)/bsp +include_bsp_socaldir = $(includedir)/bsp/socal include_libcpudir = $(includedir)/libcpu dist_project_lib_DATA = bsp_specs @@ -27,6 +28,8 @@ nodist_include_HEADERS = ../../shared/include/coverhd.h \ nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h include_bsp_HEADERS = +include_bsp_socal_HEADERS = + include_bsp_HEADERS += ../../shared/include/utility.h include_bsp_HEADERS += ../../shared/include/irq-generic.h include_bsp_HEADERS += ../../shared/include/irq-info.h @@ -71,8 +74,18 @@ include_bsp_HEADERS += hwlib/include/hwlib.h #include_bsp_HEADERS += hwlib/include/alt_watchdog.h #The following Altera hwlib headers would be problematic with RTEMS: #include_bsp_HEADERS += hwlib/include/alt_interrupt.h -#All header files from hwlib/include/socal are regarded as BSP -#internal and thus not installed + +# Some of the headers from hwlib need the files from socal. Install them. +include_bsp_socal_HEADERS += hwlib/include/socal/alt_clkmgr.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_gpio.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_i2c.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_l3.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_rstmgr.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_sdr.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_sysmgr.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_uart.h +include_bsp_socal_HEADERS += hwlib/include/socal/hps.h +include_bsp_socal_HEADERS += hwlib/include/socal/socal.h include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 3f83665..8873d31 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -33,6 +33,11 @@ $(PROJECT_INCLUDE)/bsp/$(dirstamp): @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) +$(PROJECT_INCLUDE)/bsp/socal/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp/socal + @: > $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) @@ -174,6 +179,46 @@ $(PROJECT_INCLUDE)/bsp/hwlib.h: hwlib/include/hwlib.h $(PROJECT_INCLUDE)/bsp/$(d $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwlib.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwlib.h +$(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h: hwlib/include/socal/alt_clkmgr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h: hwlib/include/socal/alt_gpio.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_i2c.h: hwlib/include/socal/alt_i2c.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_i2c.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_i2c.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_l3.h: hwlib/include/socal/alt_l3.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_l3.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_l3.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h: hwlib/include/socal/alt_rstmgr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_sdr.h: hwlib/include/socal/alt_sdr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_sdr.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_sdr.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_sysmgr.h: hwlib/include/socal/alt_sysmgr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_sysmgr.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_sysmgr.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_uart.h: hwlib/include/socal/alt_uart.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_uart.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_uart.h + +$(PROJECT_INCLUDE)/bsp/socal/hps.h: hwlib/include/socal/hps.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/hps.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/hps.h + +$(PROJECT_INCLUDE)/bsp/socal/socal.h: hwlib/include/socal/socal.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/socal.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/socal.h + $(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h From sebh at rtems.org Mon Aug 11 06:02:44 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 11 Aug 2014 01:02:44 -0500 Subject: [rtems commit] bsp/altera-cyclone-v: Add RTC driver. Message-ID: <20140811060246.0AFD5700121@git.rtems.org> Module: rtems Branch: master Commit: 81329f9ecf7c289c67cf0ff7ee54898d9311429e Changeset: http://git.rtems.org/rtems/commit/?id=81329f9ecf7c289c67cf0ff7ee54898d9311429e Author: Christian Mauderer Date: Tue Jul 15 16:20:37 2014 +0200 bsp/altera-cyclone-v: Add RTC driver. --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 4 + c/src/lib/libbsp/arm/altera-cyclone-v/README | 15 +- .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 6 +- c/src/lib/libbsp/arm/altera-cyclone-v/rtc/rtc.c | 360 ++++++++++++++++++++ 4 files changed, 381 insertions(+), 4 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index 01b0272..939ccc7 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -200,6 +200,10 @@ libbsp_a_SOURCES += i2c/i2cdrv.c libbsp_a_SOURCES += i2c/i2cdrv-config.c include_bsp_HEADERS += include/i2cdrv.h +# RTC +libbsp_a_SOURCES += ../../shared/tod.c +libbsp_a_SOURCES += rtc/rtc.c + # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/README b/c/src/lib/libbsp/arm/altera-cyclone-v/README index 575b72e..0a5bc05 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/README +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/README @@ -1,3 +1,16 @@ +Overview +-------- Evaluation board for this BSP: - Cyclone V SoC FPGA Development Kit -- DK-DEV-5CSXC6N/ES-0L \ No newline at end of file +- DK-DEV-5CSXC6N/ES-0L + +RTC +--- +The evaluation board contains a DS1339C RTC connected to I2C0. To use it you +have to set the following options: + + #define CONFIGURE_APPLICATION_NEEDS_RTC_DRIVER + #define CONFIGURE_BSP_PREREQUISITE_DRIVERS I2C_DRIVER_TABLE_ENTRY + +Additional there has to be one free file descriptor to access the i2c. Set the +CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS accordingly. diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index c13ef6a..4e3b586 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/rtc/rtc.c b/c/src/lib/libbsp/arm/altera-cyclone-v/rtc/rtc.c new file mode 100644 index 0000000..3c18d1c --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/rtc/rtc.c @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* + * Driver for the DS1339 RTC. + * + * Please note the following points: + * - The day of week is ignored. + * - The century bit is interpreted the following way: + * - century not set: TOD_BASE_YEAR .. 1999 + * - century set: 2000 .. 2099 + * - century not set: 2100 .. (TOD_BASE_YEAR + 200) + */ + +#include +#include +#include +#include +#include +#include +#include + +#define ALTERA_CYCLONE_V_RTC_NUMBER 1 + +#define DS1339_I2C_ADDRESS 0x68 +#define DS1339_I2C_BUS_DEVICE "/dev/i2c0" + +#define DS1339_ADDR_CTRL 0x0E +#define DS1339_CTRL_EOSC 0x80 +#define DS1339_CTRL_BBSQI 0x20 +#define DS1339_CTRL_RS2 0x10 +#define DS1339_CTRL_RS1 0x08 +#define DS1339_CTRL_INTCN 0x04 +#define DS1339_CTRL_A2IE 0x02 +#define DS1339_CTRL_A1IE 0x01 + +#define DS1339_CTRL_DEFAULT (0x00) + +#define DS1339_ADDR_TIME 0x00 +#define DS1339_ADDR_STATUS 0x0F +#define DS1339_STATUS_OSF 0x80 +#define DS1339_STATUS_A2F 0x02 +#define DS1339_STATUS_A1F 0x01 + +#define DS1339_STATUS_CLEAR (0x00) + +typedef struct { + uint8_t seconds; + uint8_t minutes; + uint8_t hours; +#define DS1339_HOURS_12_24_FLAG 0x40 +#define DS1339_HOURS_AM_PM_FLAG_OR_20_HOURS 0x20 +#define DS1339_HOURS_10_HOURS 0x10 + uint8_t weekday; + uint8_t date; + uint8_t month; +#define DS1339_MONTH_CENTURY 0x80 + uint8_t year; +} ds1339_time_t; + +/* The longest write transmission is writing the time + one address bit */ +#define DS1339_MAX_WRITE_SIZE (sizeof(ds1339_time_t) + 1) + +/* Functions for converting the fields */ +static unsigned int get_seconds (ds1339_time_t *time) { + uint8_t tens = time->seconds >> 4; + uint8_t ones = time->seconds & 0x0F; + return tens * 10 + ones; +} + +static unsigned int get_minutes (ds1339_time_t *time) { + uint8_t tens = time->minutes >> 4; + uint8_t ones = time->minutes & 0x0F; + return tens * 10 + ones; +} + +static unsigned int get_hours (ds1339_time_t *time) { + uint8_t value = time->hours & 0x0F; + + if(time->hours & DS1339_HOURS_10_HOURS) { + value += 10; + } + if(time->hours & DS1339_HOURS_AM_PM_FLAG_OR_20_HOURS) { + if(time->hours & DS1339_HOURS_12_24_FLAG) { + value += 12; + } else { + value += 20; + } + } + + return value; +} + +static unsigned int get_day_of_month (ds1339_time_t *time) { + uint8_t tens = time->date >> 4; + uint8_t ones = time->date & 0x0F; + return tens * 10 + ones; +} + +static unsigned int get_month (ds1339_time_t *time) { + uint8_t tens = (time->month >> 4) & 0x07; + uint8_t ones = time->month & 0x0F; + return tens * 10 + ones; +} + +static unsigned int get_year (ds1339_time_t *time) { + unsigned int year = 1900; + year += (time->year >> 4) * 10; + year += time->year & 0x0F; + if(time->month & DS1339_MONTH_CENTURY) { + year += 100; + } + if(year < TOD_BASE_YEAR) { + year += 200; + } + return year; +} + +static void set_time ( + ds1339_time_t *time, + unsigned int second, + unsigned int minute, + unsigned int hour, + unsigned int day, + unsigned int month, + unsigned int year +) { + unsigned int tens; + unsigned int ones; + uint8_t century = 0; + + tens = second / 10; + ones = second % 10; + time->seconds = tens << 4 | ones; + + tens = minute / 10; + ones = minute % 10; + time->minutes = tens << 4 | ones; + + tens = hour / 10; + ones = hour % 10; + time->hours = tens << 4 | ones; + + /* Weekday is not used. Therefore it can be set to an arbitrary valid value */ + time->weekday = 1; + + tens = day / 10; + ones = day % 10; + time->date = tens << 4 | ones; + + tens = month / 10; + ones = month % 10; + if(year >= 2000 && year < 2100) { + century = DS1339_MONTH_CENTURY; + } + time->month = century | tens << 4 | ones; + + tens = (year % 100) / 10; + ones = year % 10; + time->year = tens << 4 | ones; +} + +static rtems_status_code ds1339_open_file(int *fd) +{ + int rv = 0; + rtems_status_code sc = RTEMS_SUCCESSFUL; + + *fd = open(DS1339_I2C_BUS_DEVICE, O_RDWR); + if ( *fd == -1 ) { + sc = RTEMS_IO_ERROR; + } + + if ( sc == RTEMS_SUCCESSFUL ) { + rv = ioctl(*fd, I2C_IOC_SET_SLAVE_ADDRESS, DS1339_I2C_ADDRESS); + if ( rv == -1 ) { + sc = RTEMS_IO_ERROR; + } + } + + return sc; +} + +/* Read size bytes from ds1339 register address addr to buf. */ +static rtems_status_code ds1339_read(uint8_t addr, void *buf, size_t size) +{ + int fd = -1; + int rv = 0; + rtems_status_code sc = RTEMS_SUCCESSFUL; + + sc = ds1339_open_file(&fd); + + if ( sc == RTEMS_SUCCESSFUL ) { + rv = write(fd, &addr, sizeof(addr)); + if ( rv != sizeof(addr) ) { + sc = RTEMS_IO_ERROR; + } + } + + if ( sc == RTEMS_SUCCESSFUL ) { + rv = read(fd, buf, size); + if ( rv != size ) { + sc = RTEMS_IO_ERROR; + } + } + + rv = close(fd); + if ( rv != 0 ) { + sc = RTEMS_IO_ERROR; + } + + return sc; +} + +/* Write size bytes from buf to ds1339 register address addr. */ +static rtems_status_code ds1339_write(uint8_t addr, void *buf, size_t size) +{ + int fd = -1; + int rv = 0; + rtems_status_code sc = RTEMS_SUCCESSFUL; + /* The driver never writes many bytes. Therefore it should be less expensive + * to reserve the maximum number of bytes that will be written in one go than + * use a malloc. */ + uint8_t local_buf[DS1339_MAX_WRITE_SIZE]; + int write_size = size + 1; + + assert(write_size <= DS1339_MAX_WRITE_SIZE); + + local_buf[0] = addr; + memcpy(&local_buf[1], buf, size); + + sc = ds1339_open_file(&fd); + + if ( sc == RTEMS_SUCCESSFUL ) { + rv = write(fd, local_buf, write_size); + if ( rv != write_size ) { + sc = RTEMS_IO_ERROR; + } + } + + rv = close(fd); + if ( rv != 0 ) { + sc = RTEMS_IO_ERROR; + } + + return RTEMS_SUCCESSFUL; +} + +static void altera_cyclone_v_rtc_initialize(int minor) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + uint8_t status = 0; + + /* Check RTC valid */ + sc = ds1339_read(DS1339_ADDR_STATUS, &status, sizeof(status)); + assert(sc == RTEMS_SUCCESSFUL); + if(status & DS1339_STATUS_OSF) { + /* RTC has been stopped. Initialise it. */ + ds1339_time_t time; + + uint8_t write = DS1339_CTRL_DEFAULT; + sc = ds1339_write(DS1339_ADDR_CTRL, &write, sizeof(write)); + assert(sc == RTEMS_SUCCESSFUL); + + write = DS1339_STATUS_CLEAR; + sc = ds1339_write(DS1339_ADDR_STATUS, &write, sizeof(write)); + assert(sc == RTEMS_SUCCESSFUL); + + set_time(&time, 0, 0, 0, 1, 1, TOD_BASE_YEAR); + sc = ds1339_write(DS1339_ADDR_TIME, &time, sizeof(time)); + assert(sc == RTEMS_SUCCESSFUL); + } +} + +static int altera_cyclone_v_rtc_get_time(int minor, rtems_time_of_day *tod) +{ + ds1339_time_t time; + rtems_status_code sc = RTEMS_SUCCESSFUL; + rtems_time_of_day temp_tod; + + sc = ds1339_read(DS1339_ADDR_TIME, &time, sizeof(time)); + + if ( sc == RTEMS_SUCCESSFUL ) { + temp_tod.ticks = 0; + temp_tod.second = get_seconds(&time); + temp_tod.minute = get_minutes(&time); + temp_tod.hour = get_hours(&time); + temp_tod.day = get_day_of_month(&time); + temp_tod.month = get_month(&time); + temp_tod.year = get_year(&time); + + if ( _TOD_Validate(&temp_tod) ) { + memcpy(tod, &temp_tod, sizeof(temp_tod)); + } else { + sc = RTEMS_INVALID_CLOCK; + } + } + + return -sc; +} + +static int altera_cyclone_v_rtc_set_time(int minor, const rtems_time_of_day *tod) +{ + ds1339_time_t time; + rtems_status_code sc = RTEMS_SUCCESSFUL; + + set_time ( + &time, + tod->second, + tod->minute, + tod->hour, + tod->day, + tod->month, + tod->year + ); + + sc = ds1339_write(DS1339_ADDR_TIME, &time, sizeof(time)); + + return -sc; +} + +static bool altera_cyclone_v_rtc_probe(int minor) +{ + /* FIXME: Probe for i2c device */ + return true; +} + +const rtc_fns altera_cyclone_v_rtc_ops = { + .deviceInitialize = altera_cyclone_v_rtc_initialize, + .deviceGetTime = altera_cyclone_v_rtc_get_time, + .deviceSetTime = altera_cyclone_v_rtc_set_time +}; + +size_t RTC_Count = ALTERA_CYCLONE_V_RTC_NUMBER; + +rtems_device_minor_number RTC_Minor = 0; + +rtc_tbl RTC_Table [ALTERA_CYCLONE_V_RTC_NUMBER] = { + { + .sDeviceName = "/dev/rtc", + .deviceType = RTC_CUSTOM, + .pDeviceFns = &altera_cyclone_v_rtc_ops, + .deviceProbe = altera_cyclone_v_rtc_probe, + .pDeviceParams = NULL, + .ulCtrlPort1 = 0, + .ulDataPort = 0, + .getRegister = NULL, + .setRegister = NULL + } +}; From sebh at rtems.org Tue Aug 12 18:25:25 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 12 Aug 2014 13:25:25 -0500 Subject: [rtems commit] arm: Add support for FPv4-SP floating point unit Message-ID: <20140812182526.1721970098F@git.rtems.org> Module: rtems Branch: master Commit: 8ae373235b316ff10c3b6f30ac1f2efed9bec011 Changeset: http://git.rtems.org/rtems/commit/?id=8ae373235b316ff10c3b6f30ac1f2efed9bec011 Author: Sebastian Huber Date: Sun Aug 10 18:36:30 2014 +0200 arm: Add support for FPv4-SP floating point unit This floating point unit is available in Cortex-M4 processors and defined by ARMv7-M. This adds basic support for other VFP-D16 variants. --- c/src/lib/libbsp/arm/shared/start/start.S | 15 ++++++++ cpukit/score/cpu/arm/arm-context-validate.S | 31 ++++++++++------ .../score/cpu/arm/arm-context-volatile-clobber.S | 8 +++-- cpukit/score/cpu/arm/arm_exc_interrupt.S | 12 ++++-- cpukit/score/cpu/arm/armv4-exception-default.S | 24 ++++++++++--- cpukit/score/cpu/arm/armv7m-context-switch.c | 13 ++++++- cpukit/score/cpu/arm/armv7m-exception-default.c | 38 ++++++++++++++++++- cpukit/score/cpu/arm/armv7m-isr-dispatch.c | 30 +++++++++++++--- cpukit/score/cpu/arm/cpu.c | 2 +- cpukit/score/cpu/arm/cpu_asm.S | 4 +- cpukit/score/cpu/arm/rtems/score/arm.h | 17 +++++++-- cpukit/score/cpu/arm/rtems/score/armv7m.h | 37 ++++++++++++++++++- cpukit/score/cpu/arm/rtems/score/cpu.h | 8 ++-- 13 files changed, 194 insertions(+), 45 deletions(-) diff --git a/c/src/lib/libbsp/arm/shared/start/start.S b/c/src/lib/libbsp/arm/shared/start/start.S index 096e9bd..63b3250 100644 --- a/c/src/lib/libbsp/arm/shared/start/start.S +++ b/c/src/lib/libbsp/arm/shared/start/start.S @@ -266,6 +266,8 @@ twiddle: #elif defined(ARM_MULTILIB_ARCH_V7M) +#include + .syntax unified .extern bsp_stack_main_end @@ -300,6 +302,19 @@ bsp_start_vector_table_end: _start: +#ifdef ARM_MULTILIB_VFP + /* + * Enable CP10 and CP11 coprocessors for privileged and user mode in + * CPACR (bits 20-23). Ensure that write to register completes. + */ + ldr r0, =ARMV7M_CPACR + ldr r1, [r0] + orr r1, r1, #(0xf << 20) + str r1, [r0] + dsb + isb +#endif + ldr sp, =bsp_stack_main_end ldr lr, =bsp_start_hook_0_done + 1 b bsp_start_hook_0 diff --git a/cpukit/score/cpu/arm/arm-context-validate.S b/cpukit/score/cpu/arm/arm-context-validate.S index f2772b4..fdfb6c1 100644 --- a/cpukit/score/cpu/arm/arm-context-validate.S +++ b/cpukit/score/cpu/arm/arm-context-validate.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -29,7 +29,7 @@ #define FRAME_OFFSET_R11 28 #define FRAME_OFFSET_LR 32 -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP #define FRAME_OFFSET_D8 40 #define FRAME_OFFSET_D9 48 #define FRAME_OFFSET_D10 56 @@ -71,7 +71,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) mov r1, lr str r1, [sp, #FRAME_OFFSET_LR] -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP vstr d8, [sp, #FRAME_OFFSET_D8] vstr d9, [sp, #FRAME_OFFSET_D9] vstr d10, [sp, #FRAME_OFFSET_D10] @@ -96,11 +96,15 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) .endm -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP /* R3 contains the FPSCR */ vmrs r3, FPSCR movs r4, #0x001f +#ifdef ARM_MULTILIB_ARCH_V7M + movt r4, #0xf000 +#else movt r4, #0xf800 +#endif bic r3, r3, r4 and r4, r4, r0 orr r3, r3, r4 @@ -120,7 +124,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) fill_register r12 fill_register lr -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP .macro fill_vfp_register reg add r1, r1, #1 vmov \reg, r1, r1 @@ -142,6 +146,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) fill_vfp_register d13 fill_vfp_register d14 fill_vfp_register d15 +#ifdef ARM_MULTILIB_VFP_D32 fill_vfp_register d16 fill_vfp_register d17 fill_vfp_register d18 @@ -158,7 +163,8 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) fill_vfp_register d29 fill_vfp_register d30 fill_vfp_register d31 -#endif +#endif /* ARM_MULTILIB_VFP_D32 */ +#endif /* ARM_MULTILIB_VFP */ /* Check */ check: @@ -174,7 +180,7 @@ check: mov r1, r0 -#ifndef ARM_MULTILIB_VFP_D32 +#ifndef ARM_MULTILIB_VFP check_register r3 #endif @@ -189,7 +195,7 @@ check: check_register r12 check_register lr -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP b check_vfp #endif @@ -217,7 +223,7 @@ restore: ldr r1, [sp, #FRAME_OFFSET_LR] mov lr, r1 -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP vldr d8, [sp, #FRAME_OFFSET_D8] vldr d9, [sp, #FRAME_OFFSET_D9] vldr d10, [sp, #FRAME_OFFSET_D10] @@ -234,7 +240,7 @@ restore: FUNCTION_END(_CPU_Context_validate) -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP check_vfp: .macro check_vfp_register reg @@ -270,6 +276,7 @@ check_vfp: check_vfp_register d13 check_vfp_register d14 check_vfp_register d15 +#ifdef ARM_MULTILIB_VFP_D32 check_vfp_register d16 check_vfp_register d17 check_vfp_register d18 @@ -286,6 +293,7 @@ check_vfp: check_vfp_register d29 check_vfp_register d30 check_vfp_register d31 +#endif /* ARM_MULTILIB_VFP_D32 */ /* Restore r4 and r5 */ mov r1, r0 @@ -293,5 +301,4 @@ check_vfp: fill_register r5 b check - -#endif +#endif /* ARM_MULTILIB_VFP */ diff --git a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S index 459acba..7970b8e 100644 --- a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S +++ b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -27,7 +27,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber) mov \reg, r0 .endm -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP vmrs r1, FPSCR movs r2, #0x001f movt r2, #0xf800 @@ -49,6 +49,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber) clobber_vfp_register d5 clobber_vfp_register d6 clobber_vfp_register d7 +#ifdef ARM_MULTILIB_VFP_D32 clobber_vfp_register d16 clobber_vfp_register d17 clobber_vfp_register d18 @@ -65,7 +66,8 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber) clobber_vfp_register d29 clobber_vfp_register d30 clobber_vfp_register d31 -#endif +#endif /* ARM_MULTILIB_VFP_D32 */ +#endif /* ARM_MULTILIB_VFP */ clobber_register r1 clobber_register r2 diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S b/cpukit/score/cpu/arm/arm_exc_interrupt.S index e8026c8..7930c32 100644 --- a/cpukit/score/cpu/arm/arm_exc_interrupt.S +++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S @@ -75,13 +75,15 @@ _ARMV4_Exception_interrupt: stmdb sp!, CONTEXT_LIST stmdb sp!, {SP_OF_INTERRUPTED_CONTEXT, lr} -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP /* Save VFP context */ vmrs r0, FPSCR vstmdb sp!, {d0-d7} +#ifdef ARM_MULTILIB_VFP_D32 vstmdb sp!, {d16-d31} - stmdb sp!, {r0, r1} #endif + stmdb sp!, {r0, r1} +#endif /* ARM_MULTILIB_VFP */ /* Get per-CPU control of current processor */ GET_SELF_CPU_CONTROL SELF_CPU_CONTROL, r1 @@ -166,13 +168,15 @@ thread_dispatch_done: /* Switch to ARM instructions if necessary */ SWITCH_FROM_THUMB_TO_ARM -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP /* Restore VFP context */ ldmia sp!, {r0, r1} +#ifdef ARM_MULTILIB_VFP_D32 vldmia sp!, {d16-d31} +#endif vldmia sp!, {d0-d7} vmsr FPSCR, r0 -#endif +#endif /* ARM_MULTILIB_VFP */ /* Restore SP_OF_INTERRUPTED_CONTEXT register and link register */ ldmia sp!, {SP_OF_INTERRUPTED_CONTEXT, lr} diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S index 950ad67..a0ee46c 100644 --- a/cpukit/score/cpu/arm/armv4-exception-default.S +++ b/cpukit/score/cpu/arm/armv4-exception-default.S @@ -118,13 +118,18 @@ save_more_context: /* Argument for high level handler */ mov r0, sp -#ifdef ARM_MULTILIB_VFP_D32 + /* Clear VFP context pointer */ + add r3, sp, #ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET + mov r1, #0 + str r1, [r3] + +#ifdef ARM_MULTILIB_VFP /* Ensure that the FPU is enabled */ vmrs r1, FPEXC tst r1, #(1 << 30) - beq fpu_save_done + beq 1f - add r3, sp, #ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET + /* Save VFP context */ sub sp, #(ARM_VFP_CONTEXT_SIZE + 4) add r4, sp, #4 bic r4, r4, #7 @@ -132,10 +137,19 @@ save_more_context: vmrs r2, FPSCR stmia r4!, {r1-r2} vstmia r4!, {d0-d15} +#ifdef ARM_MULTILIB_VFP_D32 vstmia r4!, {d16-d31} - -fpu_save_done: +#else + mov r1, #0 + mov r2, #0 + adds r3, r4, #128 +2: + stmia r4!, {r1-r2} + cmp r4, r3 + bne 2b #endif +1: +#endif /* ARM_MULTILIB_VFP */ /* Call high level handler */ SWITCH_FROM_ARM_TO_THUMB r1 diff --git a/cpukit/score/cpu/arm/armv7m-context-switch.c b/cpukit/score/cpu/arm/armv7m-context-switch.c index eabf2c8..359a1a7 100644 --- a/cpukit/score/cpu/arm/armv7m-context-switch.c +++ b/cpukit/score/cpu/arm/armv7m-context-switch.c @@ -5,7 +5,7 @@ */ /* - * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * Copyright (c) 2011-2014 Sebastian Huber. All rights reserved. * * embedded brains GmbH * Obere Lagerstr. 30 @@ -37,17 +37,26 @@ void __attribute__((naked)) _CPU_Context_switch( "movt r2, #:upper16:_Per_CPU_Information\n" "ldr r3, [r2, %[isrpcpuoff]]\n" "stm r0, {r4-r11, lr}\n" +#ifdef ARM_MULTILIB_VFP + "add r4, r0, %[d8off]\n" + "vstm r4, {d8-d15}\n" +#endif "str sp, [r0, %[spctxoff]]\n" "str r3, [r0, %[isrctxoff]]\n" "ldr r3, [r1, %[isrctxoff]]\n" "ldr sp, [r1, %[spctxoff]]\n" +#ifdef ARM_MULTILIB_VFP + "add r4, r1, %[d8off]\n" + "vldm r4, {d8-d15}\n" +#endif "ldm r1, {r4-r11, lr}\n" "str r3, [r2, %[isrpcpuoff]]\n" "bx lr\n" : : [spctxoff] "J" (offsetof(Context_Control, register_sp)), [isrctxoff] "J" (offsetof(Context_Control, isr_nest_level)), - [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level)) + [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level)), + [d8off] "J" (ARM_CONTEXT_CONTROL_D8_OFFSET) ); } diff --git a/cpukit/score/cpu/arm/armv7m-exception-default.c b/cpukit/score/cpu/arm/armv7m-exception-default.c index dde1014..e890cdf 100644 --- a/cpukit/score/cpu/arm/armv7m-exception-default.c +++ b/cpukit/score/cpu/arm/armv7m-exception-default.c @@ -38,15 +38,49 @@ void __attribute__((naked)) _ARMV7M_Exception_default( void ) "stm r1, {r3-r5}\n" "mrs r1, ipsr\n" "str r1, [sp, %[cpuvecoff]]\n" + + /* Argument for high level handler */ "mov r0, sp\n" + + /* Clear VFP context pointer */ + "add r3, sp, %[cpuvfpoff]\n" + "mov r1, #0\n" + "str r1, [r3]\n" + +#ifdef ARM_MULTILIB_VFP + /* Ensure that the FPU is enabled */ + "ldr r4, =%[cpacr]\n" + "tst r4, #(0xf << 20)\n" + "bne 1f\n" + + /* Save VFP context */ + "sub sp, %[vfpsz]\n" + "add r4, sp, #4\n" + "bic r4, r4, #7\n" + "str r4, [r3]\n" + "vmrs r2, FPSCR\n" + "stmia r4!, {r1-r2}\n" + "vstmia r4!, {d0-d15}\n" + "mov r1, #0\n" + "mov r2, #0\n" + "adds r3, r4, #128\n" + "2:\n" + "stmia r4!, {r1-r2}\n" + "cmp r4, r3\n" + "bne 2b\n" + "1:\n" +#endif + "b _ARM_Exception_default\n" : : [cpufsz] "i" (sizeof(CPU_Exception_frame)), [v7mfsz] "i" (sizeof(ARMV7M_Exception_frame)), - [cpuspoff] "J" (offsetof(CPU_Exception_frame, register_sp)), [cpulroff] "i" (offsetof(CPU_Exception_frame, register_lr)), [v7mlroff] "i" (offsetof(ARMV7M_Exception_frame, register_lr)), - [cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector)) + [cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector)), + [cpuvfpoff] "i" (ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET), + [cpacr] "i" (ARMV7M_CPACR), + [vfpsz] "i" (ARM_VFP_CONTEXT_SIZE) ); } diff --git a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c index 048ffa8..e460e9c 100644 --- a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c +++ b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c @@ -5,7 +5,7 @@ */ /* - * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * Copyright (c) 2011-2014 Sebastian Huber. All rights reserved. * * embedded brains GmbH * Obere Lagerstr. 30 @@ -37,13 +37,27 @@ static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void ) ); } +static void _ARMV7M_Trigger_lazy_floating_point_context_save( void ) +{ +#ifdef ARM_MULTILIB_VFP + __asm__ volatile ( + "vmov.f32 s0, s0\n" + ); +#endif +} + void _ARMV7M_Pendable_service_call( void ) { + ARMV7M_Exception_frame *ef; + _ISR_Nest_level = 1; + _ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR; - ARMV7M_Exception_frame *ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP(); + _ARMV7M_Trigger_lazy_floating_point_context_save(); + + ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP(); --ef; - _ARMV7M_Set_PSP((uint32_t) ef); + _ARMV7M_Set_PSP( (uint32_t) ef ); /* * According to "ARMv7-M Architecture Reference Manual" section B1.5.6 @@ -57,11 +71,17 @@ void _ARMV7M_Pendable_service_call( void ) void _ARMV7M_Supervisor_call( void ) { - ARMV7M_Exception_frame *ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP(); + ARMV7M_Exception_frame *ef; + + _ARMV7M_Trigger_lazy_floating_point_context_save(); + + ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP(); ++ef; - _ARMV7M_Set_PSP((uint32_t) ef); + _ARMV7M_Set_PSP( (uint32_t) ef ); + _ISR_Nest_level = 0; RTEMS_COMPILER_MEMORY_BARRIER(); + if ( _Thread_Dispatch_necessary ) { _ARMV7M_Pendable_service_call(); } diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c index 089826e..9942c4a 100644 --- a/cpukit/score/cpu/arm/cpu.c +++ b/cpukit/score/cpu/arm/cpu.c @@ -35,7 +35,7 @@ #include #include -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP RTEMS_STATIC_ASSERT( offsetof( Context_Control, register_d8 ) == ARM_CONTEXT_CONTROL_D8_OFFSET, ARM_CONTEXT_CONTROL_D8_OFFSET diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S index d4355b4..344512b 100644 --- a/cpukit/score/cpu/arm/cpu_asm.S +++ b/cpukit/score/cpu/arm/cpu_asm.S @@ -58,7 +58,7 @@ DEFINE_FUNCTION_ARM(_CPU_Context_switch) mrs r2, CPSR stmia r0, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14} -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP add r3, r0, #ARM_CONTEXT_CONTROL_D8_OFFSET vstm r3, {d8-d15} #endif @@ -101,7 +101,7 @@ DEFINE_FUNCTION_ARM(_CPU_Context_switch) mcr p15, 0, r3, c13, c0, 3 #endif -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP add r3, r1, #ARM_CONTEXT_CONTROL_D8_OFFSET vldm r3, {d8-d15} #endif diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h index a105f17..586a8cb 100644 --- a/cpukit/score/cpu/arm/rtems/score/arm.h +++ b/cpukit/score/cpu/arm/rtems/score/arm.h @@ -50,10 +50,19 @@ extern "C" { #define ARM_MULTILIB_HAS_THREAD_ID_REGISTER #endif -#if defined(__ARM_NEON__) - #define ARM_MULTILIB_VFP_D32 -#elif !defined(__SOFTFP__) - #error "FPU support not implemented" +#if !defined(__SOFTFP__) + #if defined(__ARM_NEON__) + #define ARM_MULTILIB_VFP_D32 + #elif defined(__VFP_FP__) + #define ARM_MULTILIB_VFP_D16 + #else + #error "FPU support not implemented" + #endif +#endif + +#if defined(ARM_MULTILIB_VFP_D16) \ + || defined(ARM_MULTILIB_VFP_D32) + #define ARM_MULTILIB_VFP #endif /* diff --git a/cpukit/score/cpu/arm/rtems/score/armv7m.h b/cpukit/score/cpu/arm/rtems/score/armv7m.h index b545859..c5e473e 100644 --- a/cpukit/score/cpu/arm/rtems/score/armv7m.h +++ b/cpukit/score/cpu/arm/rtems/score/armv7m.h @@ -5,7 +5,7 @@ */ /* - * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * Copyright (c) 2011-2014 Sebastian Huber. All rights reserved. * * embedded brains GmbH * Obere Lagerstr. 30 @@ -29,6 +29,11 @@ extern "C" { #ifdef ARM_MULTILIB_ARCH_V7M +/* Coprocessor Access Control Register, CPACR */ +#define ARMV7M_CPACR 0xe000ed88 + +#ifndef ASM + typedef struct { uint32_t reserved_0; uint32_t ictr; @@ -47,6 +52,26 @@ typedef struct { void *register_lr; void *register_pc; uint32_t register_xpsr; +#ifdef ARM_MULTILIB_VFP + uint32_t register_s0; + uint32_t register_s1; + uint32_t register_s2; + uint32_t register_s3; + uint32_t register_s4; + uint32_t register_s5; + uint32_t register_s6; + uint32_t register_s7; + uint32_t register_s8; + uint32_t register_s9; + uint32_t register_s10; + uint32_t register_s11; + uint32_t register_s12; + uint32_t register_s13; + uint32_t register_s14; + uint32_t register_s15; + uint32_t register_fpscr; + uint32_t reserved; +#endif } ARMV7M_Exception_frame; typedef struct { @@ -97,6 +122,14 @@ typedef struct { uint32_t mmfar; uint32_t bfar; uint32_t afsr; + uint32_t reserved_e000ed40[18]; + uint32_t cpacr; + uint32_t reserved_e000ed8c[106]; + uint32_t fpccr; + uint32_t fpcar; + uint32_t fpdscr; + uint32_t mvfr0; + uint32_t mvfr1; } ARMV7M_SCB; typedef struct { @@ -504,6 +537,8 @@ void _ARMV7M_Pendable_service_call( void ); void _ARMV7M_Supervisor_call( void ); +#endif /* ASM */ + #endif /* ARM_MULTILIB_ARCH_V7M */ #ifdef __cplusplus diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h index ad070df..089fc27 100644 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/rtems/score/cpu.h @@ -8,7 +8,7 @@ * This include file contains information pertaining to the ARM * processor. * - * Copyright (c) 2009-2013 embedded brains GmbH. + * Copyright (c) 2009-2014 embedded brains GmbH. * * Copyright (c) 2007 Ray Xu * @@ -212,12 +212,12 @@ #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 #endif -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 #endif #ifdef RTEMS_SMP - #ifdef ARM_MULTILIB_VFP_D32 + #ifdef ARM_MULTILIB_VFP #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 #else #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 @@ -278,7 +278,7 @@ typedef struct { #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER uint32_t thread_id; #endif -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP uint64_t register_d8; uint64_t register_d9; uint64_t register_d10; From sebh at rtems.org Tue Aug 12 18:25:25 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 12 Aug 2014 13:25:25 -0500 Subject: [rtems commit] bsp/lpc24xx: Add LPC40XX variants Message-ID: <20140812182526.BFA6C700903@git.rtems.org> Module: rtems Branch: master Commit: 6cdc090ff0574a87fbfb17a7095d64583fc9c669 Changeset: http://git.rtems.org/rtems/commit/?id=6cdc090ff0574a87fbfb17a7095d64583fc9c669 Author: Sebastian Huber Date: Sun Aug 10 18:35:27 2014 +0200 bsp/lpc24xx: Add LPC40XX variants --- c/src/lib/libbsp/arm/lpc24xx/Makefile.am | 27 +++++----- c/src/lib/libbsp/arm/lpc24xx/configure.ac | 12 ++-- .../lib/libbsp/arm/lpc24xx/make/custom/lpc40xx.inc | 11 ++++ .../arm/lpc24xx/make/custom/lpc40xx_ea_ram.cfg | 5 ++ .../arm/lpc24xx/make/custom/lpc40xx_ea_rom_int.cfg | 5 ++ c/src/lib/libbsp/arm/lpc24xx/preinstall.am | 56 ++++++++++++++++++++ .../arm/lpc24xx/startup/linkcmds.lpc40xx_ea_ram | 1 + .../lpc24xx/startup/linkcmds.lpc40xx_ea_rom_int | 1 + 8 files changed, 99 insertions(+), 19 deletions(-) diff --git a/c/src/lib/libbsp/arm/lpc24xx/Makefile.am b/c/src/lib/libbsp/arm/lpc24xx/Makefile.am index 3b5c94f..b2fdd5f 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/Makefile.am +++ b/c/src/lib/libbsp/arm/lpc24xx/Makefile.am @@ -66,19 +66,20 @@ libbspstart_a_SOURCES = ../shared/start/start.S project_lib_DATA = start.$(OBJEXT) project_lib_DATA += startup/linkcmds -EXTRA_DIST = -EXTRA_DIST += startup/linkcmds.lpc17xx_ea_ram -EXTRA_DIST += startup/linkcmds.lpc17xx_ea_rom_int -EXTRA_DIST += startup/linkcmds.lpc17xx_plx800_ram -EXTRA_DIST += startup/linkcmds.lpc17xx_plx800_rom_int -EXTRA_DIST += startup/linkcmds.lpc2362 -EXTRA_DIST += startup/linkcmds.lpc23xx_tli800 -EXTRA_DIST += startup/linkcmds.lpc24xx_ea -EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_ram -EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_ext -EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_int -EXTRA_DIST += startup/linkcmds.lpc24xx_plx800_ram -EXTRA_DIST += startup/linkcmds.lpc24xx_plx800_rom_int +project_lib_DATA += startup/linkcmds.lpc17xx_ea_ram +project_lib_DATA += startup/linkcmds.lpc17xx_ea_rom_int +project_lib_DATA += startup/linkcmds.lpc17xx_plx800_ram +project_lib_DATA += startup/linkcmds.lpc17xx_plx800_rom_int +project_lib_DATA += startup/linkcmds.lpc2362 +project_lib_DATA += startup/linkcmds.lpc23xx_tli800 +project_lib_DATA += startup/linkcmds.lpc24xx_ea +project_lib_DATA += startup/linkcmds.lpc24xx_ncs_ram +project_lib_DATA += startup/linkcmds.lpc24xx_ncs_rom_ext +project_lib_DATA += startup/linkcmds.lpc24xx_ncs_rom_int +project_lib_DATA += startup/linkcmds.lpc24xx_plx800_ram +project_lib_DATA += startup/linkcmds.lpc24xx_plx800_rom_int +project_lib_DATA += startup/linkcmds.lpc40xx_ea_ram +project_lib_DATA += startup/linkcmds.lpc40xx_ea_rom_int ############################################################################### # LibBSP # diff --git a/c/src/lib/libbsp/arm/lpc24xx/configure.ac b/c/src/lib/libbsp/arm/lpc24xx/configure.ac index 737501f..e3747d5 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/configure.ac +++ b/c/src/lib/libbsp/arm/lpc24xx/configure.ac @@ -28,17 +28,17 @@ RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_MAIN],[main oscillator frequency in Hz]) RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_RTC],[*],[32768U]) RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_RTC],[RTC oscillator frequency in Hz]) -RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc17xx_ea*],[96000000U]) +RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc17xx_ea* | lpc40xx_ea*],[96000000U]) RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc23*],[58982400U]) RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc24xx_plx800_*],[51612800U]) RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[*],[72000000U]) RTEMS_BSPOPTS_HELP([LPC24XX_CCLK],[CPU clock in Hz]) -RTEMS_BSPOPTS_SET([LPC24XX_PCLKDIV],[lpc17xx_ea*],[2U]) +RTEMS_BSPOPTS_SET([LPC24XX_PCLKDIV],[lpc17xx_ea* | lpc40xx_ea*],[2U]) RTEMS_BSPOPTS_SET([LPC24XX_PCLKDIV],[*],[1U]) RTEMS_BSPOPTS_HELP([LPC24XX_PCLKDIV],[clock divider for default PCLK (PCLK = CCLK / PCLKDIV)]) -RTEMS_BSPOPTS_SET([LPC24XX_EMCCLKDIV],[lpc17xx_ea*],[2U]) +RTEMS_BSPOPTS_SET([LPC24XX_EMCCLKDIV],[lpc17xx_ea* | lpc40xx_ea*],[2U]) RTEMS_BSPOPTS_SET([LPC24XX_EMCCLKDIV],[*],[1U]) RTEMS_BSPOPTS_HELP([LPC24XX_EMCCLKDIV],[clock divider for EMCCLK (EMCCLK = CCLK / EMCCLKDIV)]) @@ -60,7 +60,7 @@ RTEMS_BSPOPTS_HELP([LPC24XX_EMC_W9825G2JB75I],[enable Winbond W9825G2JB75I confi RTEMS_BSPOPTS_SET([LPC24XX_EMC_IS42S32800D7],[*_plx800_rom_*],[1]) RTEMS_BSPOPTS_HELP([LPC24XX_EMC_IS42S32800D7],[enable ISSI IS42S32800D7 configuration for EMC]) -RTEMS_BSPOPTS_SET([LPC24XX_EMC_IS42S32800B],[lpc17xx_ea_rom_*],[1]) +RTEMS_BSPOPTS_SET([LPC24XX_EMC_IS42S32800B],[lpc17xx_ea_rom_* | lpc40xx_ea_rom_*],[1]) RTEMS_BSPOPTS_HELP([LPC24XX_EMC_IS42S32800B],[enable ISSI IS42S32800B configuration for EMC]) RTEMS_BSPOPTS_SET([LPC24XX_EMC_M29W160E],[lpc24xx_ncs_rom_*],[1]) @@ -112,14 +112,14 @@ RTEMS_BSPOPTS_SET([LPC24XX_STOP_USB],[lpc23*],[]) RTEMS_BSPOPTS_SET([LPC24XX_STOP_USB],[*],[1]) RTEMS_BSPOPTS_HELP([LPC24XX_STOP_USB],[stop USB controller at start-up to avoid DMA interference]) -RTEMS_BSPOPTS_SET([LPC_DMA_CHANNEL_COUNT],[lpc17*],[8]) +RTEMS_BSPOPTS_SET([LPC_DMA_CHANNEL_COUNT],[lpc17* | lpc40*],[8]) RTEMS_BSPOPTS_SET([LPC_DMA_CHANNEL_COUNT],[*],[2]) RTEMS_BSPOPTS_HELP([LPC_DMA_CHANNEL_COUNT],[DMA channel count]) RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[lpc24xx_ncs_rom_ext],[0x80000040]) RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) -RTEMS_BSPOPTS_SET([BSP_USB_OTG_TRANSCEIVER_I2C_ADDR],[lpc17xx_ea*],[(0x2f << 1)]) +RTEMS_BSPOPTS_SET([BSP_USB_OTG_TRANSCEIVER_I2C_ADDR],[lpc17xx_ea* | lpc40xx_ea*],[(0x2f << 1)]) RTEMS_BSPOPTS_HELP([BSP_USB_OTG_TRANSCEIVER_I2C_ADDR],[USB OTG transceiver I2C address used by USB stack]) RTEMS_BSP_CLEANUP_OPTIONS(0, 1) diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx.inc b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx.inc new file mode 100644 index 0000000..2c921db --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx.inc @@ -0,0 +1,11 @@ +# +# Config file for LPC40XX. +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = arm + +CPU_CFLAGS = -mthumb -march=armv7-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mtune=cortex-m4 + +CFLAGS_OPTIMIZE_V = -O2 -g diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_ram.cfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_ram.cfg new file mode 100644 index 0000000..4c4eb4d --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_ram.cfg @@ -0,0 +1,5 @@ +# +# Config file for LPC40XX OEM Board from Embedded Artists. +# + +include $(RTEMS_ROOT)/make/custom/lpc40xx.inc diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int.cfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int.cfg new file mode 100644 index 0000000..4c4eb4d --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int.cfg @@ -0,0 +1,5 @@ +# +# Config file for LPC40XX OEM Board from Embedded Artists. +# + +include $(RTEMS_ROOT)/make/custom/lpc40xx.inc diff --git a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am index a022b02..3bf67a6 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am @@ -173,3 +173,59 @@ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds +$(PROJECT_LIB)/linkcmds.lpc17xx_ea_ram: startup/linkcmds.lpc17xx_ea_ram $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc17xx_ea_ram +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc17xx_ea_ram + +$(PROJECT_LIB)/linkcmds.lpc17xx_ea_rom_int: startup/linkcmds.lpc17xx_ea_rom_int $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc17xx_ea_rom_int +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc17xx_ea_rom_int + +$(PROJECT_LIB)/linkcmds.lpc17xx_plx800_ram: startup/linkcmds.lpc17xx_plx800_ram $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc17xx_plx800_ram +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc17xx_plx800_ram + +$(PROJECT_LIB)/linkcmds.lpc17xx_plx800_rom_int: startup/linkcmds.lpc17xx_plx800_rom_int $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc17xx_plx800_rom_int +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc17xx_plx800_rom_int + +$(PROJECT_LIB)/linkcmds.lpc2362: startup/linkcmds.lpc2362 $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc2362 +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc2362 + +$(PROJECT_LIB)/linkcmds.lpc23xx_tli800: startup/linkcmds.lpc23xx_tli800 $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc23xx_tli800 +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc23xx_tli800 + +$(PROJECT_LIB)/linkcmds.lpc24xx_ea: startup/linkcmds.lpc24xx_ea $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_ea +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_ea + +$(PROJECT_LIB)/linkcmds.lpc24xx_ncs_ram: startup/linkcmds.lpc24xx_ncs_ram $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_ram +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_ram + +$(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_ext: startup/linkcmds.lpc24xx_ncs_rom_ext $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_ext +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_ext + +$(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_int: startup/linkcmds.lpc24xx_ncs_rom_int $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_int +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_int + +$(PROJECT_LIB)/linkcmds.lpc24xx_plx800_ram: startup/linkcmds.lpc24xx_plx800_ram $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_plx800_ram +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_plx800_ram + +$(PROJECT_LIB)/linkcmds.lpc24xx_plx800_rom_int: startup/linkcmds.lpc24xx_plx800_rom_int $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_plx800_rom_int +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_plx800_rom_int + +$(PROJECT_LIB)/linkcmds.lpc40xx_ea_ram: startup/linkcmds.lpc40xx_ea_ram $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc40xx_ea_ram +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc40xx_ea_ram + +$(PROJECT_LIB)/linkcmds.lpc40xx_ea_rom_int: startup/linkcmds.lpc40xx_ea_rom_int $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc40xx_ea_rom_int +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc40xx_ea_rom_int + diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_ram b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_ram new file mode 100644 index 0000000..d453596 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_ram @@ -0,0 +1 @@ +INCLUDE linkcmds.lpc17xx_ea_ram diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_rom_int b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_rom_int new file mode 100644 index 0000000..612f491 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_rom_int @@ -0,0 +1 @@ +INCLUDE linkcmds.lpc17xx_ea_rom_int From joel at rtems.org Tue Aug 12 18:32:17 2014 From: joel at rtems.org (Joel Sherrill) Date: Tue, 12 Aug 2014 13:32:17 -0500 Subject: [rtems commit] Add support for OpenRISC - Fixed issues Message-ID: <20140812183217.2DD1B700903@git.rtems.org> Module: rtems Branch: master Commit: 94d45f6ffe22c640566ddc4432adcb97ab6c907f Changeset: http://git.rtems.org/rtems/commit/?id=94d45f6ffe22c640566ddc4432adcb97ab6c907f Author: Hesham ALMatary Date: Tue Aug 12 10:57:42 2014 -0500 Add support for OpenRISC - Fixed issues This work is based on the old or32 port (that has been removed back in 2005) authored by Chris Ziomkowski. The patch includes the basic functions every port should implement like: context switch, exception handling, OpenRISC ABI and machine definitions and configurations. --- cpukit/configure.ac | 1 + cpukit/score/cpu/Makefile.am | 1 + cpukit/score/cpu/or1k/Makefile.am | 36 + cpukit/score/cpu/or1k/cpu.c | 112 +++ cpukit/score/cpu/or1k/or1k-context-initialize.c | 43 + cpukit/score/cpu/or1k/or1k-context-switch.S | 114 +++ cpukit/score/cpu/or1k/or1k-exception-default.c | 23 + cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 22 + cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 216 ++++ cpukit/score/cpu/or1k/rtems/asm.h | 99 ++ cpukit/score/cpu/or1k/rtems/score/cpu.h | 1051 ++++++++++++++++++++ cpukit/score/cpu/or1k/rtems/score/cpu_asm.h | 74 ++ cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 371 +++++++ cpukit/score/cpu/or1k/rtems/score/or1k.h | 49 + cpukit/score/cpu/or1k/rtems/score/types.h | 51 + 15 files changed, 2263 insertions(+), 0 deletions(-) diff --git a/cpukit/configure.ac b/cpukit/configure.ac index 19e5b81..56815e2 100644 --- a/cpukit/configure.ac +++ b/cpukit/configure.ac @@ -382,6 +382,7 @@ score/cpu/m32r/Makefile score/cpu/mips/Makefile score/cpu/moxie/Makefile score/cpu/nios2/Makefile +score/cpu/or1k/Makefile score/cpu/powerpc/Makefile score/cpu/sh/Makefile score/cpu/sparc/Makefile diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am index 8d28fc2..69abcd6 100644 --- a/cpukit/score/cpu/Makefile.am +++ b/cpukit/score/cpu/Makefile.am @@ -14,6 +14,7 @@ DIST_SUBDIRS += mips DIST_SUBDIRS += moxie DIST_SUBDIRS += nios2 DIST_SUBDIRS += no_cpu +DIST_SUBDIRS += or1k DIST_SUBDIRS += powerpc DIST_SUBDIRS += sh DIST_SUBDIRS += sparc diff --git a/cpukit/score/cpu/or1k/Makefile.am b/cpukit/score/cpu/or1k/Makefile.am new file mode 100644 index 0000000..cb96856 --- /dev/null +++ b/cpukit/score/cpu/or1k/Makefile.am @@ -0,0 +1,36 @@ +include $(top_srcdir)/automake/compile.am + +CLEANFILES = +DISTCLEANFILES = + +include_rtemsdir = $(includedir)/rtems + +include_rtems_HEADERS = rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score + +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += rtems/score/cpu.h +include_rtems_score_HEADERS += rtems/score/cpu_asm.h +include_rtems_score_HEADERS += rtems/score/types.h +include_rtems_score_HEADERS += rtems/score/or1k.h +include_rtems_score_HEADERS += rtems/score/or1k-utility.h + + + +noinst_LIBRARIES = libscorecpu.a + +libscorecpu_a_SOURCES = +libscorecpu_a_SOURCES += cpu.c +libscorecpu_a_SOURCES += or1k-context-switch.S +libscorecpu_a_SOURCES += or1k-context-initialize.c +libscorecpu_a_SOURCES += or1k-exception-default.c +libscorecpu_a_SOURCES += or1k-exception-frame-print.c +libscorecpu_a_SOURCES += or1k-exception-handler-low.S + +libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) + +all-local: $(PREINSTALL_FILES) + +include $(srcdir)/preinstall.am +include $(top_srcdir)/automake/local.am diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c new file mode 100644 index 0000000..9d1ae49 --- /dev/null +++ b/cpukit/score/cpu/or1k/cpu.c @@ -0,0 +1,112 @@ +/* + * Opencore OR1K CPU Dependent Source + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#include +#include +#include +#include +#include + +/** + * @brief Performs processor dependent initialization. + */ +void _CPU_Initialize(void) +{ + /* Do nothing */ +} + +/** + * @brief Sets the hardware interrupt level by the level value. + * + * @param[in] level for or1k can only range over two values: + * 0 (enable interrupts) and 1 (disable interrupts). In future + * implementations if fast context switch is implemented, the level + * can range from 0 to 15. @see OpenRISC architecture manual. + * + */ +void _CPU_ISR_Set_level(uint32_t level) +{ + uint32_t sr = 0; + level = (level > 0)? 1 : 0; + + /* map level bit to or1k interrupt enable/disable bit in sr register */ + level <<= CPU_OR1K_SPR_SR_SHAMT_IEE; + + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + + if (level == 0){ /* Enable all interrupts */ + sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE; + + } else{ + sr &= ~CPU_OR1K_SPR_SR_IEE; + } + + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); + } + +uint32_t _CPU_ISR_Get_level( void ) +{ + uint32_t sr = 0; + + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + + return (sr & CPU_OR1K_SPR_SR_IEE)? 0 : 1; +} + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ +} + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + proc_ptr *table = + (proc_ptr *) bsp_start_vector_table_begin; + proc_ptr current_handler; + + ISR_Level level; + + _ISR_Disable( level ); + + current_handler = table [vector]; + + /* The current handler is now the old one */ + if (old_handler != NULL) { + *old_handler = (proc_ptr) current_handler; + } + + /* Write only if necessary to avoid writes to a maybe read-only memory */ + if (current_handler != new_handler) { + table [vector] = new_handler; + } + + _ISR_Enable( level ); +} + +void _CPU_Install_interrupt_stack( void ) +{ +} + +void _CPU_Thread_Idle_body( void ) +{ + do { + _OR1K_CPU_Sleep(); + } while (1); +} diff --git a/cpukit/score/cpu/or1k/or1k-context-initialize.c b/cpukit/score/cpu/or1k/or1k-context-initialize.c new file mode 100644 index 0000000..7ac2875 --- /dev/null +++ b/cpukit/score/cpu/or1k/or1k-context-initialize.c @@ -0,0 +1,43 @@ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * COPYRIGHT (c) 1989-2006 + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include + +#include +#include +#include + +void _CPU_Context_Initialize( + Context_Control *context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +) +{ + uint32_t stack = (uint32_t) stack_area_begin; + uint32_t sr; + + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + + memset(context, 0, sizeof(*context)); + + context->r1 = stack; + context->r2 = stack; + context->r9 = (uint32_t) entry_point; + context->sr = sr; +} diff --git a/cpukit/score/cpu/or1k/or1k-context-switch.S b/cpukit/score/cpu/or1k/or1k-context-switch.S new file mode 100644 index 0000000..91521e4 --- /dev/null +++ b/cpukit/score/cpu/or1k/or1k-context-switch.S @@ -0,0 +1,114 @@ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include +#include "rtems/score/or1k-utility.h" + +.text +.align 4 + +PUBLIC(_CPU_Context_switch) +PUBLIC(_CPU_Context_restore) +PUBLIC(_CPU_Context_restore_fp) +PUBLIC(_CPU_Context_save_fp) + +SYM(_CPU_Context_switch): + l.sw 0(r3),r1 + l.sw 4(r3),r2 + l.sw 8(r3),r3 + l.sw 12(r3),r4 + l.sw 16(r3),r5 + l.sw 20(r3),r6 + l.sw 24(r3),r7 + l.sw 28(r3),r8 + l.sw 32(r3),r9 + /* Skip r10 as it's preserved to be used by TLS */ + /* The following set if registers are preserved across function calls */ + l.sw 52(r3),r14 + l.sw 60(r3),r16 + l.sw 68(r3),r18 + l.sw 76(r3),r20 + l.sw 84(r3),r22 + l.sw 92(r3),r24 + l.sw 100(r3),r26 + l.sw 108(r3),r28 + l.sw 116(r3),r30 + + /* Supervision Register */ + l.mfspr r13,r0, CPU_OR1K_SPR_SR + l.sw 124(r3),r13 + + /* EPCR */ + l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0 + l.sw 128(r3), r13 /* epcr */ + + /* EEAR */ + l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0 + l.sw 132(r3), r13 /* eear */ + + /* ESR */ + l.mfspr r13, r0, CPU_OR1K_SPR_ESR0 + l.sw 136(r3), r13 /* esr */ + +SYM(restore): + l.lwz r13,124(r4) + l.mtspr r0,r13, CPU_OR1K_SPR_SR + + /* Exception level related registers */ + + /* EPCR */ + l.lwz r13, 128(r4) + l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0 + + /* EEAR */ + l.lwz r13, 132(r4) + l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0 + + /* ESR */ + l.lwz r13, 136(r4) + l.mtspr r0, r13, CPU_OR1K_SPR_ESR0 + + l.lwz r1,0(r4) + l.lwz r2,4(r4) + l.lwz r3,8(r4) + /* Skip r4 as it contains the current buffer address */ + l.lwz r5,16(r4) + l.lwz r6,20(r4) + l.lwz r7,24(r4) + l.lwz r8,28(r4) + l.lwz r9,32(r4) + l.lwz r14,52(r4) + l.lwz r16,60(r4) + l.lwz r18,68(r4) + l.lwz r20,76(r4) + l.lwz r22,84(r4) + l.lwz r24,92(r4) + l.lwz r26,100(r4) + l.lwz r28,108(r4) + l.lwz r30,116(r4) + + l.lwz r4,12(r4) + + l.jr r9 + l.nop + + SYM(_CPU_Context_restore): + l.add r4,r3,r0 + l.add r13,r0,r0 + l.j restore + l.nop + + SYM(_CPU_Context_restore_fp): + l.nop + + SYM(_CPU_Context_save_fp): + l.nop diff --git a/cpukit/score/cpu/or1k/or1k-exception-default.c b/cpukit/score/cpu/or1k/or1k-exception-default.c new file mode 100644 index 0000000..645a7f9 --- /dev/null +++ b/cpukit/score/cpu/or1k/or1k-exception-default.c @@ -0,0 +1,23 @@ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include +#include +#include +#include + +void _OR1K_Exception_default(uint32_t vector, CPU_Exception_frame *frame); + +void _OR1K_Exception_default(uint32_t vector, CPU_Exception_frame *frame) +{ + rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame ); +} diff --git a/cpukit/score/cpu/or1k/or1k-exception-frame-print.c b/cpukit/score/cpu/or1k/or1k-exception-frame-print.c new file mode 100644 index 0000000..75e169c --- /dev/null +++ b/cpukit/score/cpu/or1k/or1k-exception-frame-print.c @@ -0,0 +1,22 @@ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include +#include + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) +{ + uint32_t i; + for ( i = 0; i < 32; ++i ) { + printk( "r%02i = 0x%016x\n",i, frame->r[i]); + } +} diff --git a/cpukit/score/cpu/or1k/or1k-exception-handler-low.S b/cpukit/score/cpu/or1k/or1k-exception-handler-low.S new file mode 100644 index 0000000..964a054 --- /dev/null +++ b/cpukit/score/cpu/or1k/or1k-exception-handler-low.S @@ -0,0 +1,216 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief OR1K exception support implementation. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include "rtems/score/or1k-utility.h" + +.align 4 +.text +PUBLIC(_ISR_Handler) +.type _ISR_Handler, at function + + SYM(_ISR_Handler): + + l.addi r1, r1, -140 + + l.sw 8(r1),r2 + /* r3 is saved by BSP exception handler */ + l.sw 16(r1),r4 + l.sw 20(r1),r5 + l.sw 24(r1),r6 + l.sw 28(r1),r7 + l.sw 32(r1),r8 + l.sw 36(r1),r9 + l.sw 40(r1),r10 + l.sw 44(r1),r11 + l.sw 48(r1),r12 + l.sw 52(r1),r13 + l.sw 56(r1),r14 + l.sw 60(r1),r15 + l.sw 64(r1),r16 + l.sw 68(r1),r17 + l.sw 72(r1),r18 + l.sw 76(r1),r19 + l.sw 80(r1),r20 + l.sw 84(r1),r21 + l.sw 88(r1),r22 + l.sw 92(r1),r23 + l.sw 96(r1),r24 + l.sw 100(r1),r25 + l.sw 104(r1),r26 + l.sw 108(r1),r27 + l.sw 112(r1),r28 + l.sw 116(r1),r29 + l.sw 120(r1),r30 + l.sw 124(r1),r31 + + /* Exception level related registers */ + + /* EPCR */ + l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0 + l.sw 128(r1), r13 /* epcr */ + + /* EEAR */ + l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0 + l.sw 132(r1), r13 /* eear */ + + /* ESR */ + l.mfspr r13, r0, CPU_OR1K_SPR_ESR0 + l.sw 136(r1), r13 /* esr */ + + /* Increment nesting level */ + l.movhi r6, hi(ISR_NEST_LEVEL) + l.ori r6, r6, lo(ISR_NEST_LEVEL) + + /* Disable multitasking */ + l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL) + l.ori r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL) + + l.lwz r5, 0(r6) + l.lwz r7, 0(r8) + l.addi r5, r5, 1 + l.addi r7, r7, 1 + l.sw 0(r6), r5 + l.sw 0(r8), r7 + + /* Save interrupted task stack pointer */ + l.addi r4, r1, 144 + l.sw 4(r1), r4 + + /* Save interrupted task r3 (first arg) value */ + l.addi r4, r1, 140 + l.lwz r4, 0(r4) + l.sw 12(r1), r4 + + /* Keep r1 (Exception frame address) in r14 */ + l.add r14, r1, r0 + + /* Call the exception handler from vector table */ + + /* First function arg for C handler is vector number, + * and the second is a pointer to exception frame. + */ + l.add r13, r3, r0 + l.add r4, r1, r0 + l.slli r13, r13, 2 + l.addi r13, r13, lo(bsp_start_vector_table_begin) + l.lwz r13, 0(r13) + + /* Do not switch stacks if we are in a nested interrupt. At + * this point r5 should be holding ISR_NEST_LEVEL value. + */ + l.sfgtui r5, 2 + l.bf jump_to_c_handler + l.nop + + /* Switch to RTEMS dedicated interrupt stack */ + l.movhi r1, hi(INTERRUPT_STACK_HIGH) + l.ori r1, r1, lo(INTERRUPT_STACK_HIGH) + l.lwz r1, 0(r1) + +jump_to_c_handler: + l.jalr r13 + l.nop + + /* Switch back to the interrupted task stack */ + l.add r1, r14, r0 + + /* Check if dispatch needed */ + l.movhi r31, hi(DISPATCH_NEEDED) + l.ori r31, r31, lo(DISPATCH_NEEDED) + l.lwz r31, 0(r31) + l.sfeq r31, r0 + l.bf exception_frame_restore + l.nop + + l.movhi r13, hi(_Thread_Dispatch) + l.ori r13, r13, lo(_Thread_Dispatch) + l.jalr r13 + l.nop + + SYM(exception_frame_restore): + + /* Exception level related registers */ + + /* EPCR */ + l.lwz r13, 128(r1) + l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0 + + /* EEAR */ + l.lwz r13, 132(r1) + l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0 + + /* ESR */ + l.lwz r13, 136(r1) + l.mtspr r0, r13, CPU_OR1K_SPR_ESR0 + + /* Increment nesting level */ + l.movhi r6, hi(ISR_NEST_LEVEL) + l.ori r6, r6, lo(ISR_NEST_LEVEL) + + /* Disable multitasking */ + l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL) + l.ori r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL) + + l.lwz r5, 0(r6) + l.lwz r7, 0(r8) + l.addi r5, r5, -1 + l.addi r7, r7, -1 + l.sw 0(r6), r5 + l.sw 0(r8), r7 + + l.lwz r2, 8(r1) + l.lwz r3, 12(r1) + l.lwz r4, 16(r1) + l.lwz r5, 20(r1) + l.lwz r6, 24(r1) + l.lwz r7, 28(r1) + l.lwz r8, 32(r1) + l.lwz r9, 36(r1) + l.lwz r10, 40(r1) + l.lwz r11, 44(r1) + l.lwz r12, 48(r1) + l.lwz r13, 52(r1) + l.lwz r14, 56(r1) + l.lwz r15, 60(r1) + l.lwz r16, 64(r1) + l.lwz r17, 68(r1) + l.lwz r18, 72(r1) + l.lwz r19, 76(r1) + l.lwz r20, 80(r1) + l.lwz r21, 84(r1) + l.lwz r22, 88(r1) + l.lwz r23, 92(r1) + l.lwz r24, 96(r1) + l.lwz r25, 100(r1) + l.lwz r26, 104(r1) + l.lwz r27, 108(r1) + l.lwz r28, 112(r1) + l.lwz r29, 116(r1) + l.lwz r30, 120(r1) + + l.addi r1, r1, 140 + + l.addi r1, r1, 4 + + l.rfe + l.nop diff --git a/cpukit/score/cpu/or1k/rtems/asm.h b/cpukit/score/cpu/or1k/rtems/asm.h new file mode 100644 index 0000000..4d2c226 --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/asm.h @@ -0,0 +1,99 @@ +/** + * @file rtems/asm.h + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + */ + +/* + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + * + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-1997. + * On-Line Applications Research Corporation (OAR). + * + */ + +#ifndef __OR1K_ASM_h +#define __OR1K_ASM_h + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +/* ANSI concatenation macros. */ + +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a ## b + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .global SYM (sym) +#define EXTERN(sym) .global SYM (sym) + +#endif diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h b/cpukit/score/cpu/or1k/rtems/score/cpu.h new file mode 100644 index 0000000..01e07a2 --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/score/cpu.h @@ -0,0 +1,1051 @@ +/** + * @file rtems/score/cpu.h + */ + +/* + * This include file contains macros pertaining to the Opencores + * or1k processor family. + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * This file adapted from no_cpu example of the RTEMS distribution. + * The body has been modified for the Opencores OR1k implementation by + * Chris Ziomkowski. + * + */ + +#ifndef _OR1K_CPU_H +#define _OR1K_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#include /* pick up machine definitions */ +#include +#include +#ifndef ASM +#include +#include +#include /* for printk */ +#endif + +/* conditional compilation parameters */ + +/* + * Should the calls to _Thread_Enable_dispatch be inlined? + * + * If TRUE, then they are inlined. + * If FALSE, then a subroutine call is made. + * + * Basically this is an example of the classic trade-off of size + * versus speed. Inlining the call (TRUE) typically increases the + * size of RTEMS while speeding up the enabling of dispatching. + * [NOTE: In general, the _Thread_Dispatch_disable_level will + * only be 0 or 1 unless you are in an interrupt handler and that + * interrupt handler invokes the executive.] When not inlined + * something calls _Thread_Enable_dispatch which in turns calls + * _Thread_Dispatch. If the enable dispatch is inlined, then + * one subroutine call is avoided entirely.] + * + */ + +#define CPU_INLINE_ENABLE_DISPATCH FALSE + +/* + * Should the body of the search loops in _Thread_queue_Enqueue_priority + * be unrolled one time? In unrolled each iteration of the loop examines + * two "nodes" on the chain being searched. Otherwise, only one node + * is examined per iteration. + * + * If TRUE, then the loops are unrolled. + * If FALSE, then the loops are not unrolled. + * + * The primary factor in making this decision is the cost of disabling + * and enabling interrupts (_ISR_Flash) versus the cost of rest of the + * body of the loop. On some CPUs, the flash is more expensive than + * one iteration of the loop body. In this case, it might be desirable + * to unroll the loop. It is important to note that on some CPUs, this + * code is the longest interrupt disable period in RTEMS. So it is + * necessary to strike a balance when setting this parameter. + * + */ + +#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Currently, for or1k port, _ISR_Handler is responsible for switching to + * RTEMS dedicated interrupt task. + * + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/* + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + */ + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE + * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. + * + */ + +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + */ + +#define CPU_ISR_PASSES_FRAME_POINTER 1 + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "OR1K_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + * + * The CPU_SOFTWARE_FP is used to indicate whether or not there + * is software implemented floating point that must be context + * switched. The determination of whether or not this applies + * is very tool specific and the state saved/restored is also + * compiler specific. + * + * Or1k Specific Information: + * + * At this time there are no implementations of Or1k that are + * expected to implement floating point. More importantly, the + * floating point architecture is expected to change significantly + * before such chips are fabricated. + */ + +#define CPU_HARDWARE_FP FALSE +#define CPU_SOFTWARE_FP FALSE + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + */ + +#define CPU_ALL_TASKS_ARE_FP FALSE + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + * + */ + +#define CPU_IDLE_TASK_IS_FP FALSE + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + */ + +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + * + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + */ + +#define CPU_STACK_GROWS_UP FALSE + +/* + * The following is the variable attribute used to force alignment + * of critical RTEMS structures. On some processors it may make + * sense to have these aligned on tighter boundaries than + * the minimum requirements of the compiler in order to have as + * much of the critical data area as possible in a cache line. + * + * The placement of this macro in the declaration of the variables + * is based on the syntactically requirements of the GNU C + * "__attribute__" extension. For example with GNU C, use + * the following to force a structures to a 32 byte boundary. + * + * __attribute__ ((aligned (32))) + * + * NOTE: Currently only the Priority Bit Map table uses this feature. + * To benefit from using this, the data must be heavily + * used so it will stay in the cache and used frequently enough + * in the executive to justify turning this on. + * + */ + +#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) + +/* + * Define what is required to specify how the network to host conversion + * routines are handled. + * + * Or1k Specific Information: + * + * This version of RTEMS is designed specifically to run with + * big endian architectures. If you want little endian, you'll + * have to make the appropriate adjustments here and write + * efficient routines for byte swapping. The Or1k architecture + * doesn't do this very well. + */ + +#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE +#define CPU_BIG_ENDIAN TRUE +#define CPU_LITTLE_ENDIAN FALSE + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + * + */ + +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +/* + * Processor defined structures required for cpukit/score. + */ + + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + * + * + */ +#ifndef ASM +#ifdef OR1K_64BIT_ARCH +#define or1kreg uint64_t +#else +#define or1kreg uint32_t +#endif + +typedef struct { + uint32_t r1; /* Stack pointer */ + uint32_t r2; /* Frame pointer */ + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t r13; + uint32_t r14; + uint32_t r15; + uint32_t r16; + uint32_t r17; + uint32_t r18; + uint32_t r19; + uint32_t r20; + uint32_t r21; + uint32_t r22; + uint32_t r23; + uint32_t r24; + uint32_t r25; + uint32_t r26; + uint32_t r27; + uint32_t r28; + uint32_t r29; + uint32_t r30; + uint32_t r31; + + uint32_t sr; /* Current supervision register non persistent values */ + uint32_t epcr; + uint32_t eear; + uint32_t esr; +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->r1 + +typedef struct { + /** FPU registers are listed here */ + double some_float_register; +} Context_Control_fp; + +typedef Context_Control CPU_Interrupt_frame; + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + * + * Or1k Specific Information: + * + */ + +#define CPU_CONTEXT_FP_SIZE 0 +SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; + +/* + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + * + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * Should be large enough to run all RTEMS tests. This insures + * that a "reasonable" small application should not have any problems. + * + */ + +#define CPU_STACK_MINIMUM_SIZE 4096 + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + */ + +#define CPU_ALIGNMENT 8 + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/** + * Size of a pointer. + * + * This must be an integer literal that can be used by the assembler. This + * value will be used to calculate offsets of structure members. These + * offsets will be used in assembler code. + */ +#define CPU_SIZEOF_POINTER 4 + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2 although it should be + * a multiple of 2 greater than or equal to 2. The requirement + * to be a multiple of 2 is because the heap uses the least + * significant field of the front and back flags to indicate + * that a block is in use or free. So you do not want any odd + * length blocks really putting length data in that bit. + * + * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will + * have to be greater or equal to than CPU_ALIGNMENT to ensure that + * elements allocated from the heap meet all restrictions. + * + */ + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + * + */ + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + * + */ + +#define CPU_STACK_ALIGNMENT 0 + +/* ISR handler macros */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +#define _CPU_Initialize_vectors() + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + * + */ + +static inline uint32_t or1k_interrupt_disable( void ) +{ + uint32_t sr; + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + + _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)); + + return sr; +} + +static inline void or1k_interrupt_enable(uint32_t level) +{ + uint32_t sr; + + /* Enable interrupts and restore rs */ + sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE; + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); + +} + +#define _CPU_ISR_Disable( _level ) \ + _level = or1k_interrupt_disable() + + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _level is not modified. + * + */ + +#define _CPU_ISR_Enable( _level ) \ + or1k_interrupt_enable( _level ) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + * + */ + +#define _CPU_ISR_Flash( _level ) \ + do{ \ + _CPU_ISR_Enable( _level ); \ + _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \ + } while(0) + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * The get routine usually must be implemented as a subroutine. + * + */ + +void _CPU_ISR_Set_level( uint32_t level ); + +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +#define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * + */ + +/** + * @brief Initializes the CPU context. + * + * The following steps are performed: + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * + * @param[in] context points to the context area + * @param[in] stack_area_begin is the low address of the allocated stack area + * @param[in] stack_area_size is the size of the stack area in bytes + * @param[in] new_level is the interrupt level for the task + * @param[in] entry_point is the task's entry point + * @param[in] is_fp is set to @c true if the task is a floating point task + * @param[in] tls_area is the thread-local storage (TLS) area + */ +void _CPU_Context_Initialize( + Context_Control *context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + * + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* + * The purpose of this macro is to allow the initial pointer into + * a floating point context area (used to save the floating point + * context) to be at an arbitrary place in the floating point + * context area. + * + * This is necessary because some FP units are designed to have + * their context saved as a stack which grows into lower addresses. + * Other FP units can be saved by simply moving registers into offsets + * from the base of the context area. Finally some FP units provide + * a "dump context" instruction which could fill in from high to low + * or low to high based on the whim of the CPU designers. + * + */ + +#define _CPU_Context_Fp_start( _base, _offset ) \ + ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) + +/* + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other models include (1) not doing anything, and (2) putting + * a "null FP status word" in the correct place in the FP context. + * + */ + +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + * + */ + +#define _CPU_Fatal_halt( _error ) \ + printk("Fatal Error %d Halted\n",_error); \ + for(;;) + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +/* + * This routine sets _output to the bit number of the first bit + * set in _value. _value is of CPU dependent type Priority_Bit_map_control. + * This type may be either 16 or 32 bits wide although only the 16 + * least significant bits will be used. + * + * There are a number of variables in using a "find first bit" type + * instruction. + * + * (1) What happens when run on a value of zero? + * (2) Bits may be numbered from MSB to LSB or vice-versa. + * (3) The numbering may be zero or one based. + * (4) The "find first bit" instruction may search from MSB or LSB. + * + * RTEMS guarantees that (1) will never happen so it is not a concern. + * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and + * _CPU_Priority_bits_index(). These three form a set of routines + * which must logically operate together. Bits in the _value are + * set and cleared based on masks built by _CPU_Priority_mask(). + * The basic major and minor values calculated by _Priority_Major() + * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() + * to properly range between the values returned by the "find first bit" + * instruction. This makes it possible for _Priority_Get_highest() to + * calculate the major and directly index into the minor table. + * This mapping is necessary to ensure that 0 (a high priority major/minor) + * is the first bit found. + * + * This entire "find first bit" and mapping process depends heavily + * on the manner in which a priority is broken into a major and minor + * components with the major being the 4 MSB of a priority and minor + * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest + * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next + * to the lowest priority. + * + * If your CPU does not have a "find first bit" instruction, then + * there are ways to make do without it. Here are a handful of ways + * to implement this in software: + * + * - a series of 16 bit test instructions + * - a "binary search using if's" + * - _number = 0 + * if _value > 0x00ff + * _value >>=8 + * _number = 8; + * + * if _value > 0x0000f + * _value >=8 + * _number += 4 + * + * _number += bit_set_table[ _value ] + * + * where bit_set_table[ 16 ] has values which indicate the first + * bit set + * + */ + + /* #define CPU_USE_GENERIC_BITFIELD_CODE FALSE */ +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE +#define CPU_USE_GENERIC_BITFIELD_DATA TRUE + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + + /* Get a value between 0 and N where N is the bit size */ + /* This routine makes use of the fact that CPUCFGR defines + OB32S to have value 32, and OB64S to have value 64. If + this ever changes then this routine will fail. */ +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + asm volatile ("l.mfspr %0,r0,0x2 \n\t"\ + "l.andi %0,%0,0x60 \n\t"\ + "l.ff1 %1,%1,r0 \n\t"\ + "l.sub %0,%0,%1 \n\t" : "=&r" (_output), "+r" (_value)); + +#endif + +/* end of Bitfield handler macros */ + +/* + * This routine builds the mask which corresponds to the bit fields + * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion + * for that routine. + * + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_Mask( _bit_number ) \ + (1 << _bit_number) + +#endif + +/* + * This routine translates the bit numbers returned by + * _CPU_Bitfield_Find_first_bit() into something suitable for use as + * a major or minor component of a priority. See the discussion + * for that routine. + * + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +#endif + +#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE +#define CPU_TIMESTAMP_USE_INT64 TRUE +#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE + +typedef struct { +/* There is no CPU specific per-CPU state */ +} CPU_Per_CPU_control; +#endif /* ASM */ + +#define CPU_SIZEOF_POINTER 4 +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM +typedef uint32_t CPU_Counter_ticks; +typedef uint16_t Priority_bit_map_Word; + +typedef struct { + uint32_t r[32]; + + /* The following registers must be saved if we have + fast context switch disabled and nested interrupt + levels are enabled. + */ +#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED + uint32_t epcr; /* exception PC register */ + uint32_t eear; /* exception effective address register */ + uint32_t esr; /* exception supervision register */ +#endif + +} CPU_Exception_frame; + +/** + * @brief Prints the exception frame via printk(). + * + * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. + */ +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + + +/* end of Priority handler macros */ + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + * + */ + +void _CPU_Initialize( + void +); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + * + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + * + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Thread_Idle_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + * + */ + +void _CPU_Thread_Idle_body( void ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + * + * Or1k Specific Information: + * + * Please see the comments in the .c file for a description of how + * this function works. There are several things to be aware of. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + * + */ + +void _CPU_Context_restore( + Context_Control *new_context +); + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + * + */ + +void _CPU_Context_save_fp( + void **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + * + */ + +void _CPU_Context_restore_fp( + void **fp_context_ptr +); + +/* The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to insure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + */ + +static inline unsigned int CPU_swap_u32( + unsigned int value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +); + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h b/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h new file mode 100644 index 0000000..a5659f3 --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h @@ -0,0 +1,74 @@ +/** + * @file + * + * @brief OR1K Assembly File + * + * Very loose template for an include file for the cpu_asm.? file + * if it is implemented as a ".S" file (preprocessed by cpp) instead + * of a ".s" file (preprocessed by gm4 or gasp). + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + +/* pull in the generated offsets */ + +/* +#include +*/ + +/* + * Hardware General Registers + */ + +/* put something here */ + +/* + * Hardware Floating Point Registers + */ + +/* put something here */ + +/* + * Hardware Control Registers + */ + +/* put something here */ + +/* + * Calling Convention + */ + +/* put something here */ + +/* + * Temporary registers + */ + +/* put something here */ + +/* + * Floating Point Registers - SW Conventions + */ + +/* put something here */ + +/* + * Temporary floating point registers + */ + +/* put something here */ + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h new file mode 100644 index 0000000..74c14d7 --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h @@ -0,0 +1,371 @@ +/** + * @file + * + * @brief OR1K utility + */ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_OR1K_UTILITY_H +#define _RTEMS_SCORE_OR1K_UTILITY_H + +/* SPR groups definitions */ +#define SPR_GRP_SHAMT 11 +#define SPR_GRP0_SYS_CTRL (0 << SPR_GRP_SHAMT) +#define SPR_GRP1_DMMU (1 << SPR_GRP_SHAMT) +#define SPR_GRP2_IMMU (2 << SPR_GRP_SHAMT) +#define SPR_GRP3_DC (3 << SPR_GRP_SHAMT) +#define SPR_GRP4_IC (4 << SPR_GRP_SHAMT) +#define SPR_GRP5_MAC (5 << SPR_GRP_SHAMT) +#define SPR_GRP6_DEBUG (6 << SPR_GRP_SHAMT) +#define SPR_GRP7_PERF_CTR (7 << SPR_GRP_SHAMT) +#define SPR_GRP8_PWR_MNG (8 << SPR_GRP_SHAMT) +#define SPR_GRP9_PIC (9 << SPR_GRP_SHAMT) +#define SPR_GPR10_TICK_TMR (10 << SPR_GRP_SHAMT) +#define SPR_GPR11_FPU (11 << SPR_GRP_SHAMT) + +/* SPR registers definitions */ + +/* Group 0: System control registers */ +#define CPU_OR1K_SPR_VR (SPR_GRP0_SYS_CTRL + 0) +#define CPU_OR1K_SPR_UPR (SPR_GRP0_SYS_CTRL + 1) +#define CPU_OR1K_SPR_CPUCFGR (SPR_GRP0_SYS_CTRL + 2) +#define CPU_OR1K_SPR_DMMUCFGR (SPR_GRP0_SYS_CTRL + 3) +#define CPU_OR1K_SPR_IMMUCFGR (SPR_GRP0_SYS_CTRL + 4) +#define CPU_OR1K_SPR_DCCFGR (SPR_GRP0_SYS_CTRL + 5) +#define CPU_OR1K_SPR_ICCFGR (SPR_GRP0_SYS_CTRL + 6) +#define CPU_OR1K_SPR_DCFGR (SPR_GRP0_SYS_CTRL + 7) +#define CPU_OR1K_SPR_PCCFGR (SPR_GRP0_SYS_CTRL + 8) +#define CPU_OR1K_SPR_VR2 (SPR_GRP0_SYS_CTRL + 9) +#define CPU_OR1K_SPR_AVR (SPR_GRP0_SYS_CTRL + 10) +#define CPU_OR1K_SPR_EVBAR (SPR_GRP0_SYS_CTRL + 11) +#define CPU_OR1K_SPR_AECR (SPR_GRP0_SYS_CTRL + 12) +#define CPU_OR1K_SPR_AESR (SPR_GRP0_SYS_CTRL + 13) +#define CPU_OR1K_SPR_NPC (SPR_GRP0_SYS_CTRL + 16) +#define CPU_OR1K_SPR_SR (SPR_GRP0_SYS_CTRL + 17) +#define CPU_OR1K_SPR_PPC (SPR_GRP0_SYS_CTRL + 18) +#define CPU_OR1K_SPR_FPCSR (SPR_GRP0_SYS_CTRL + 20) +#define CPU_OR1K_SPR_EPCR0 (SPR_GRP0_SYS_CTRL + 32) +#define CPU_OR1K_SPR_EPCR1 (SPR_GRP0_SYS_CTRL + 33) +#define CPU_OR1K_SPR_EPCR2 (SPR_GRP0_SYS_CTRL + 34) +#define CPU_OR1K_SPR_EPCR3 (SPR_GRP0_SYS_CTRL + 35) +#define CPU_OR1K_SPR_EPCR4 (SPR_GRP0_SYS_CTRL + 36) +#define CPU_OR1K_SPR_EPCR5 (SPR_GRP0_SYS_CTRL + 37) +#define CPU_OR1K_SPR_EPCR6 (SPR_GRP0_SYS_CTRL + 38) +#define CPU_OR1K_SPR_EPCR7 (SPR_GRP0_SYS_CTRL + 39) +#define CPU_OR1K_SPR_EPCR8 (SPR_GRP0_SYS_CTRL + 40) +#define CPU_OR1K_SPR_EPCR9 (SPR_GRP0_SYS_CTRL + 41) +#define CPU_OR1K_SPR_EPCR10 (SPR_GRP0_SYS_CTRL + 42) +#define CPU_OR1K_SPR_EPCR11 (SPR_GRP0_SYS_CTRL + 43) +#define CPU_OR1K_SPR_EPCR12 (SPR_GRP0_SYS_CTRL + 44) +#define CPU_OR1K_SPR_EPCR13 (SPR_GRP0_SYS_CTRL + 45) +#define CPU_OR1K_SPR_EPCR14 (SPR_GRP0_SYS_CTRL + 46) +#define CPU_OR1K_SPR_EPCR15 (SPR_GRP0_SYS_CTRL + 47) +#define CPU_OR1K_SPR_EEAR0 (SPR_GRP0_SYS_CTRL + 48) +#define CPU_OR1K_SPR_EEAR1 (SPR_GRP0_SYS_CTRL + 49) +#define CPU_OR1K_SPR_EEAR2 (SPR_GRP0_SYS_CTRL + 50) +#define CPU_OR1K_SPR_EEAR3 (SPR_GRP0_SYS_CTRL + 51) +#define CPU_OR1K_SPR_EEAR4 (SPR_GRP0_SYS_CTRL + 52) +#define CPU_OR1K_SPR_EEAR5 (SPR_GRP0_SYS_CTRL + 53) +#define CPU_OR1K_SPR_EEAR6 (SPR_GRP0_SYS_CTRL + 54) +#define CPU_OR1K_SPR_EEAR7 (SPR_GRP0_SYS_CTRL + 55) +#define CPU_OR1K_SPR_EEAR8 (SPR_GRP0_SYS_CTRL + 56) +#define CPU_OR1K_SPR_EEAR9 (SPR_GRP0_SYS_CTRL + 57) +#define CPU_OR1K_SPR_EEAR10 (SPR_GRP0_SYS_CTRL + 58) +#define CPU_OR1K_SPR_EEAR11 (SPR_GRP0_SYS_CTRL + 59) +#define CPU_OR1K_SPR_EEAR12 (SPR_GRP0_SYS_CTRL + 60) +#define CPU_OR1K_SPR_EEAR13 (SPR_GRP0_SYS_CTRL + 61) +#define CPU_OR1K_SPR_EEAR14 (SPR_GRP0_SYS_CTRL + 62) +#define CPU_OR1K_SPR_EEAR15 (SPR_GRP0_SYS_CTRL + 63) +#define CPU_OR1K_SPR_ESR0 (SPR_GRP0_SYS_CTRL + 64) +#define CPU_OR1K_SPR_ESR1 (SPR_GRP0_SYS_CTRL + 65) +#define CPU_OR1K_SPR_ESR2 (SPR_GRP0_SYS_CTRL + 66) +#define CPU_OR1K_SPR_ESR3 (SPR_GRP0_SYS_CTRL + 67) +#define CPU_OR1K_SPR_ESR4 (SPR_GRP0_SYS_CTRL + 68) +#define CPU_OR1K_SPR_ESR5 (SPR_GRP0_SYS_CTRL + 69) +#define CPU_OR1K_SPR_ESR6 (SPR_GRP0_SYS_CTRL + 70) +#define CPU_OR1K_SPR_ESR7 (SPR_GRP0_SYS_CTRL + 71) +#define CPU_OR1K_SPR_ESR8 (SPR_GRP0_SYS_CTRL + 72) +#define CPU_OR1K_SPR_ESR9 (SPR_GRP0_SYS_CTRL + 73) +#define CPU_OR1K_SPR_ESR10 (SPR_GRP0_SYS_CTRL + 74) +#define CPU_OR1K_SPR_ESR11 (SPR_GRP0_SYS_CTRL + 75) +#define CPU_OR1K_SPR_ESR12 (SPR_GRP0_SYS_CTRL + 76) +#define CPU_OR1K_SPR_ESR13 (SPR_GRP0_SYS_CTRL + 77) +#define CPU_OR1K_SPR_ESR14 (SPR_GRP0_SYS_CTRL + 78) +#define CPU_OR1K_SPR_ESR15 (SPR_GRP0_SYS_CTRL + 79) + +/* Shadow registers base */ +#define CPU_OR1K_SPR_GPR32 (SPR_GRP0_SYS_CTRL + 1024) + +/* Group1: Data MMU registers */ +#define CPU_OR1K_SPR_DMMUCR (SPR_GRP1_DMMU + 0) +#define CPU_OR1K_SPR_DMMUPR (SPR_GRP1_DMMU + 1) +#define CPU_OR1K_SPR_DTLBEIR (SPR_GRP1_DMMU + 2) +#define CPU_OR1K_SPR_DATBMR0 (SPR_GRP1_DMMU + 4) +#define CPU_OR1K_SPR_DATBMR1 (SPR_GRP1_DMMU + 5) +#define CPU_OR1K_SPR_DATBMR2 (SPR_GRP1_DMMU + 6) +#define CPU_OR1K_SPR_DATBMR3 (SPR_GRP1_DMMU + 7) +#define CPU_OR1K_SPR_DATBTR0 (SPR_GRP1_DMMU + 8) +#define CPU_OR1K_SPR_DATBTR1 (SPR_GRP1_DMMU + 9) +#define CPU_OR1K_SPR_DATBTR2 (SPR_GRP1_DMMU + 10) +#define CPU_OR1K_SPR_DATBTR3 (SPR_GRP1_DMMU + 11) + +/* Group2: Instruction MMU registers */ +#define CPU_OR1K_SPR_IMMUCR (SPR_GRP2_IMMU + 0) +#define CPU_OR1K_SPR_IMMUPR (SPR_GRP2_IMMU + 1) +#define CPU_OR1K_SPR_ITLBEIR (SPR_GRP2_IMMU + 2) +#define CPU_OR1K_SPR_IATBMR0 (SPR_GRP2_IMMU + 4) +#define CPU_OR1K_SPR_IATBMR1 (SPR_GRP2_IMMU + 5) +#define CPU_OR1K_SPR_IATBMR2 (SPR_GRP2_IMMU + 6) +#define CPU_OR1K_SPR_IATBMR3 (SPR_GRP2_IMMU + 7) +#define CPU_OR1K_SPR_IATBTR0 (SPR_GRP2_IMMU + 8) +#define CPU_OR1K_SPR_IATBTR1 (SPR_GRP2_IMMU + 9) +#define CPU_OR1K_SPR_IATBTR2 (SPR_GRP2_IMMU + 10) +#define CPU_OR1K_SPR_IATBTR3 (SPR_GRP2_IMMU + 11) + +/* Group3: Data Cache registers */ +#define CPU_OR1K_SPR_DCCR (SPR_GRP3_DC + 0) +#define CPU_OR1K_SPR_DCBPR (SPR_GRP3_DC + 1) +#define CPU_OR1K_SPR_DCBFR (SPR_GRP3_DC + 2) +#define CPU_OR1K_SPR_DCBIR (SPR_GRP3_DC + 3) +#define CPU_OR1K_SPR_DCBWR (SPR_GRP3_DC + 4) +#define CPU_OR1K_SPR_DCBLR (SPR_GRP3_DC + 5) + +/* Group4: Instruction Cache registers */ +#define CPU_OR1K_SPR_ICCR (SPR_GRP4_IC + 0) +#define CPU_OR1K_SPR_ICBPR (SPR_GRP4_IC + 1) +#define CPU_OR1K_SPR_ICBIR (SPR_GRP4_IC + 2) +#define CPU_OR1K_SPR_ICBLR (SPR_GRP4_IC + 3) + +/* Group5: MAC registers */ +#define CPU_OR1K_SPR_MACLO (SPR_GRP5_MAC + 1) +#define CPU_OR1K_SPR_MACHI (SPR_GRP5_MAC + 2) + +/* Group6: Debug registers */ +#define CPU_OR1K_SPR_DVR0 (SPR_GRP6_DEBUG + 0) +#define CPU_OR1K_SPR_DVR1 (SPR_GRP6_DEBUG + 1) +#define CPU_OR1K_SPR_DVR2 (SPR_GRP6_DEBUG + 2) +#define CPU_OR1K_SPR_DVR3 (SPR_GRP6_DEBUG + 3) +#define CPU_OR1K_SPR_DVR4 (SPR_GRP6_DEBUG + 4) +#define CPU_OR1K_SPR_DVR5 (SPR_GRP6_DEBUG + 5) +#define CPU_OR1K_SPR_DVR6 (SPR_GRP6_DEBUG + 6) +#define CPU_OR1K_SPR_DVR7 (SPR_GRP6_DEBUG + 7) +#define CPU_OR1K_SPR_DCR0 (SPR_GRP6_DEBUG + 8) +#define CPU_OR1K_SPR_DCR1 (SPR_GRP6_DEBUG + 9) +#define CPU_OR1K_SPR_DCR2 (SPR_GRP6_DEBUG + 10) +#define CPU_OR1K_SPR_DCR3 (SPR_GRP6_DEBUG + 11) +#define CPU_OR1K_SPR_DCR4 (SPR_GRP6_DEBUG + 12) +#define CPU_OR1K_SPR_DCR5 (SPR_GRP6_DEBUG + 13) +#define CPU_OR1K_SPR_DCR6 (SPR_GRP6_DEBUG + 14) +#define CPU_OR1K_SPR_DCR7 (SPR_GRP6_DEBUG + 15) +#define CPU_OR1K_SPR_DMR1 (SPR_GRP6_DEBUG + 16) +#define CPU_OR1K_SPR_DMR2 (SPR_GRP6_DEBUG + 17) +#define CPU_OR1K_SPR_DCWR0 (SPR_GRP6_DEBUG + 18) +#define CPU_OR1K_SPR_DCWR1 (SPR_GRP6_DEBUG + 19) +#define CPU_OR1K_SPR_DSR (SPR_GRP6_DEBUG + 20) +#define CPU_OR1K_SPR_DRR (SPR_GRP6_DEBUG + 21) + +/* Group7: Performance counters registers */ +#define CPU_OR1K_SPR_PCCR0 (SPR_GRP7_PERF_CTR + 0) +#define CPU_OR1K_SPR_PCCR1 (SPR_GRP7_PERF_CTR + 1) +#define CPU_OR1K_SPR_PCCR2 (SPR_GRP7_PERF_CTR + 2) +#define CPU_OR1K_SPR_PCCR3 (SPR_GRP7_PERF_CTR + 3) +#define CPU_OR1K_SPR_PCCR4 (SPR_GRP7_PERF_CTR + 4) +#define CPU_OR1K_SPR_PCCR5 (SPR_GRP7_PERF_CTR + 5) +#define CPU_OR1K_SPR_PCCR6 (SPR_GRP7_PERF_CTR + 6) +#define CPU_OR1K_SPR_PCCR7 (SPR_GRP7_PERF_CTR + 7) +#define CPU_OR1K_SPR_PCMR0 (SPR_GRP7_PERF_CTR + 8) +#define CPU_OR1K_SPR_PCMR1 (SPR_GRP7_PERF_CTR + 9) +#define CPU_OR1K_SPR_PCMR2 (SPR_GRP7_PERF_CTR + 10) +#define CPU_OR1K_SPR_PCMR3 (SPR_GRP7_PERF_CTR + 11) +#define CPU_OR1K_SPR_PCMR4 (SPR_GRP7_PERF_CTR + 12) +#define CPU_OR1K_SPR_PCMR5 (SPR_GRP7_PERF_CTR + 13) +#define CPU_OR1K_SPR_PCMR6 (SPR_GRP7_PERF_CTR + 14) +#define CPU_OR1K_SPR_PCMR7 (SPR_GRP7_PERF_CTR + 15) + +/* Group8: Power management register */ +#define CPU_OR1K_SPR_PMR (SPR_GRP8_PWR_MNG + 0) + +/* Group9: PIC registers */ +#define CPU_OR1K_SPR_PICMR (SPR_GRP9_PIC + 0) +#define CPU_OR1K_SPR_PICSR (SPR_GRP9_PIC + 2) + +/* Group10: Tick Timer registers */ +#define CPU_OR1K_SPR_TTMR (SPR_GPR10_TICK_TMR + 0) +#define CPU_OR1K_SPR_TTCR (SPR_GPR10_TICK_TMR + 1) + + /* Shift amount macros for bits position in Supervision Register */ +#define CPU_OR1K_SPR_SR_SHAMT_SM (0) +#define CPU_OR1K_SPR_SR_SHAMT_TEE (1) +#define CPU_OR1K_SPR_SR_SHAMT_IEE (2) +#define CPU_OR1K_SPR_SR_SHAMT_DCE (3) +#define CPU_OR1K_SPR_SR_SHAMT_ICE (4) +#define CPU_OR1K_SPR_SR_SHAMT_DME (5) +#define CPU_OR1K_SPR_SR_SHAMT_IME (6) +#define CPU_OR1K_SPR_SR_SHAMT_LEE (7) +#define CPU_OR1K_SPR_SR_SHAMT_CE (8) +#define CPU_OR1K_SPR_SR_SHAMT_F (9) +#define CPU_OR1K_SPR_SR_SHAMT_CY (10) +#define CPU_OR1K_SPR_SR_SHAMT_OV (11) +#define CPU_OR1K_SPR_SR_SHAMT_OVE (12) +#define CPU_OR1K_SPR_SR_SHAMT_DSX (13) +#define CPU_OR1K_SPR_SR_SHAMT_EPH (14) +#define CPU_OR1K_SPR_SR_SHAMT_FO (15) +#define CPU_OR1K_SPR_SR_SHAMT_SUMRA (16) +#define CPU_OR1K_SPR_SR_SHAMT_CID (28) + +/* Supervision Mode Register. @see OpenRISC architecture manual*/ + + /* Supervisor Mode */ +#define CPU_OR1K_SPR_SR_SM (1 << CPU_OR1K_SPR_SR_SHAMT_SM) +/* Tick Timer Exception Enabled */ +#define CPU_OR1K_SPR_SR_TEE (1 << CPU_OR1K_SPR_SR_SHAMT_TEE) +/* Interrupt Exception Enabled */ +#define CPU_OR1K_SPR_SR_IEE (1 << CPU_OR1K_SPR_SR_SHAMT_IEE) +/* Data Cache Enable */ +#define CPU_OR1K_SPR_SR_DCE (1 << CPU_OR1K_SPR_SR_SHAMT_DCE) +/* Instruction Cache Enable */ +#define CPU_OR1K_SPR_SR_ICE (1 << CPU_OR1K_SPR_SR_SHAMT_ICE) +/* Data MMU Enable */ +#define CPU_OR1K_SPR_SR_DME (1 << CPU_OR1K_SPR_SR_SHAMT_DME) +/* Instruction MMU Enable */ +#define CPU_OR1K_SPR_SR_IME (1 << CPU_OR1K_SPR_SR_SHAMT_IME) +/* Little Endian Enable */ +#define CPU_OR1K_SPR_SR_LEE (1 << CPU_OR1K_SPR_SR_SHAMT_LEE) +/* CID Enable */ +#define CPU_OR1K_SPR_SR_CE (1 << CPU_OR1K_SPR_SR_SHAMT_CE) +/* Conditional branch flag */ +#define CPU_OR1K_SPR_SR_F (1 << CPU_OR1K_SPR_SR_SHAMT_F) +/* Carry flag */ +#define CPU_OR1K_SPR_SR_CY (1 << CPU_OR1K_SPR_SR_SHAMT_CY) +/* Overflow flag */ +#define CPU_OR1K_SPR_SR_OV (1 << CPU_OR1K_SPR_SR_SHAMT_OV) +/* Overflow flag Exception */ +#define CPU_OR1K_SPR_SR_OVE (1 << CPU_OR1K_SPR_SR_SHAMT_OVE) +/* Delay Slot Exception */ +#define CPU_OR1K_SPR_SR_DSX (1 << CPU_OR1K_SPR_SR_SHAMT_DSX) + /* Exception Prefix High */ +#define CPU_OR1K_SPR_SR_EPH (1 << CPU_OR1K_SPR_SR_SHAMT_EPH) +/* Fixed One */ +#define CPU_OR1K_SPR_SR_FO (1 << CPU_OR1K_SPR_SR_SHAMT_FO) +/* SPRs User Mode Read Access */ +#define CPU_OR1K_SPR_SR_SUMRA (1 << CPU_OR1K_SPR_SR_SHAMT_SUMRA) +/*Context ID (Fast Context Switching) */ +#define CPU_OR1K_SPR_SR_CID (F << CPU_OR1K_SPR_SR_SHAMT_CID) + +/* Power management register bits */ +#define CPU_OR1K_SPR_PMR_SHAMT_SDF 0 +#define CPU_OR1K_SPR_PMR_SHAMT_DME 4 +#define CPU_OR1K_SPR_PMR_SHAMT_SME 5 +#define CPU_OR1K_SPR_PMR_SHAMT_DCGE 6 +#define CPU_OR1K_SPR_PMR_SHAMT_SUME 7 + +#define CPU_OR1K_SPR_PMR_SDF (0xF << CPU_OR1K_SPR_PMR_SHAMT_SDF) +#define CPU_OR1K_SPR_PMR_DME (1 << CPU_OR1K_SPR_PMR_SHAMT_DME) +#define CPU_OR1K_SPR_PMR_SME (1 << CPU_OR1K_SPR_PMR_SHAMT_SME) +#define CPU_OR1K_SPR_PMR_DCGE (1 << CPU_OR1K_SPR_PMR_SHAMT_DCGE) +#define CPU_OR1K_SPR_PMR_SUME (1 << CPU_OR1K_SPR_PMR_SHAMT_SUME) + +/* Shift amount macros for bit positions in Power Management register */ + +#ifndef ASM + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Supervision Mode registers definitions. + * + * @see OpenRISC architecture manual - revision 0. + */ +typedef enum { + OR1K_EXCEPTION_RESET = 1, + OR1K_EXCEPTION_BUS_ERR = 2, + OR1K_EXCEPTION_D_PF = 3, /* Data Page Fault */ + OR1K_EXCEPTION_I_PF = 4, /* Instruction Page Fault */ + OR1K_EXCEPTION_TICK_TIMER = 5, + OR1K_EXCEPTION_ALIGNMENT = 6, + OR1K_EXCEPTION_I_UNDEF= 7, /* Undefiend instruction */ + OR1K_EXCEPTION_IRQ = 8, /* External interrupt */ + OR1K_EXCPETION_D_TLB = 9, /* Data TLB miss */ + OR1K_EXCPETION_I_TLB = 10, /* Instruction TLB miss */ + OR1K_EXCPETION_RANGE = 11, /* Range exception */ + OR1K_EXCPETION_SYS_CALL = 12, + OR1K_EXCPETION_FP = 13, /* Floating point exception */ + OR1K_EXCPETION_TRAP = 14, /* Caused by l.trap instruction or by debug unit */ + OR1K_EXCPETION_RESERVED1 = 15, + OR1K_EXCPETION_RESERVED2 = 16, + OR1K_EXCPETION_RESERVED3 = 17, + MAX_EXCEPTIONS = 17, + OR1K_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff +} OR1K_Symbolic_exception_name; + +static inline uint32_t _OR1K_mfspr(uint32_t reg) +{ + uint32_t spr_value; + + asm volatile ( + "l.mfspr %0, %1, 0;\n\t" + : "=r" (spr_value) : "r" (reg)); + + return spr_value; +} + +static inline void _OR1K_mtspr(uint32_t reg, uint32_t value) +{ + asm volatile ( + "l.mtspr %1, %0, 0;\n\t" + :: "r" (value), "r" (reg) + ); +} + +/** + * @brief The slow down feature takes advantage of the low-power + * dividers in external clock generation circuitry to enable full + * functionality, but at a lower frequency so that power consumption + * is reduced. @see OpenRISC architecture manual, power management section. + * + * @param[in] value is 4 bit value to be written in PMR[SDF]. + * A lower value specifies higher expected performance from the processor core. + * + */ +#define _OR1K_CPU_SlowDown(value) \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, (value & CPU_OR1K_SPR_PMR_SDF)) + + +#define _OR1K_CPU_Doze() \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_DME) + + +#define _OR1K_CPU_Sleep() \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME) + + +#define _OR1K_CPU_Suspend() \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME) + +static inline void _OR1K_Sync_mem( void ) +{ + asm volatile("l.msync"); +} + +static inline void _OR1K_Sync_pipeline( void ) +{ + asm volatile("l.psync"); +} + +#else /* ASM */ + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_OR1K_UTILITY_H */ diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k.h b/cpukit/score/cpu/or1k/rtems/score/or1k.h new file mode 100644 index 0000000..e1a3ddc --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/score/or1k.h @@ -0,0 +1,49 @@ +/** + * @file rtems/score/or1k.h + */ + +/* + * This file contains information pertaining to the OR1K processor. + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * Based on code with the following copyright... + * COPYRIGHT (c) 1989-1999, 2010. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_OR1K_H +#define _RTEMS_SCORE_OR1K_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the OR1K family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + + /* + * Define the name of the CPU family and specific model. + */ + +#define CPU_NAME "OR1K" +#define CPU_MODEL_NAME "OR1200" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_OR1K_H */ diff --git a/cpukit/score/cpu/or1k/rtems/score/types.h b/cpukit/score/cpu/or1k/rtems/score/types.h new file mode 100644 index 0000000..843a10f --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/score/types.h @@ -0,0 +1,51 @@ +/** + * @file + * + * @brief OR1K Architecture Types API + */ + +/* + * This include file contains type definitions pertaining to the + * arm processor family. + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + + #ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup ScoreCPU + */ +/**@{**/ + +/* + * This section defines the basic types for this processor. + */ + +typedef uint16_t Priority_bit_map_Word; +typedef void or1k_isr; +typedef void ( *or1k_isr_entry )( void ); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif From joel at rtems.org Tue Aug 12 18:38:06 2014 From: joel at rtems.org (Joel Sherrill) Date: Tue, 12 Aug 2014 13:38:06 -0500 Subject: [rtems commit] or1k/.../preinstall.am: Add missing file Message-ID: <20140812183806.D5E5D700903@git.rtems.org> Module: rtems Branch: master Commit: 700f97ea675f3fdd9c8b4b9ff315a5c6b2e45c74 Changeset: http://git.rtems.org/rtems/commit/?id=700f97ea675f3fdd9c8b4b9ff315a5c6b2e45c74 Author: Joel Sherrill Date: Tue Aug 12 13:46:49 2014 -0500 or1k/.../preinstall.am: Add missing file --- cpukit/score/cpu/or1k/preinstall.am | 49 +++++++++++++++++++++++++++++++++++ 1 files changed, 49 insertions(+), 0 deletions(-) diff --git a/cpukit/score/cpu/or1k/preinstall.am b/cpukit/score/cpu/or1k/preinstall.am new file mode 100644 index 0000000..f4d7153 --- /dev/null +++ b/cpukit/score/cpu/or1k/preinstall.am @@ -0,0 +1,49 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) + +$(PROJECT_INCLUDE)/rtems/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems + @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h + +$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score + @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h + +$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h + +$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h + +$(PROJECT_INCLUDE)/rtems/score/or1k.h: rtems/score/or1k.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/or1k.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/or1k.h + +$(PROJECT_INCLUDE)/rtems/score/or1k-utility.h: rtems/score/or1k-utility.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/or1k-utility.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/or1k-utility.h + From sebh at rtems.org Thu Aug 14 12:19:47 2014 From: sebh at rtems.org (Sebastian Huber) Date: Thu, 14 Aug 2014 07:19:47 -0500 Subject: [rtems commit] arm: PR2186: Fix compile error Message-ID: <20140814121947.7C3517008D8@git.rtems.org> Module: rtems Branch: master Commit: 1a2d349776f8072ec6a45cc8dfa4fa02d87489f4 Changeset: http://git.rtems.org/rtems/commit/?id=1a2d349776f8072ec6a45cc8dfa4fa02d87489f4 Author: Sebastian Huber Date: Thu Aug 14 14:27:40 2014 +0200 arm: PR2186: Fix compile error --- cpukit/score/cpu/arm/armv7m-context-switch.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/cpukit/score/cpu/arm/armv7m-context-switch.c b/cpukit/score/cpu/arm/armv7m-context-switch.c index 359a1a7..aa09276 100644 --- a/cpukit/score/cpu/arm/armv7m-context-switch.c +++ b/cpukit/score/cpu/arm/armv7m-context-switch.c @@ -54,9 +54,11 @@ void __attribute__((naked)) _CPU_Context_switch( "bx lr\n" : : [spctxoff] "J" (offsetof(Context_Control, register_sp)), +#ifdef ARM_MULTILIB_VFP + [d8off] "J" (ARM_CONTEXT_CONTROL_D8_OFFSET), +#endif [isrctxoff] "J" (offsetof(Context_Control, isr_nest_level)), - [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level)), - [d8off] "J" (ARM_CONTEXT_CONTROL_D8_OFFSET) + [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level)) ); } From joel at rtems.org Mon Aug 18 22:01:22 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 18 Aug 2014 17:01:22 -0500 Subject: [rtems commit] Add or1k tick timer register definitions Message-ID: <20140818220123.390347006BA@git.rtems.org> Module: rtems Branch: master Commit: de62e5d861f41f7f8898ed7c8fbe9ee1201af880 Changeset: http://git.rtems.org/rtems/commit/?id=de62e5d861f41f7f8898ed7c8fbe9ee1201af880 Author: Hesham ALMatary Date: Mon Aug 18 16:06:46 2014 -0500 Add or1k tick timer register definitions --- cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 16 ++++++++++++++-- 1 files changed, 14 insertions(+), 2 deletions(-) diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h index 74c14d7..6b238b1 100644 --- a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h +++ b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h @@ -258,7 +258,21 @@ /*Context ID (Fast Context Switching) */ #define CPU_OR1K_SPR_SR_CID (F << CPU_OR1K_SPR_SR_SHAMT_CID) +/* Tick timer configuration bits */ +#define CPU_OR1K_SPR_TTMR_SHAMT_IP 28 +#define CPU_OR1K_SPR_TTMR_SHAMT_IE 29 +#define CPU_OR1K_SPR_TTMR_SHAMT_MODE 30 + +#define CPU_OR1K_SPR_TTMR_TP_MASK (0x0FFFFFFF) +#define CPU_OR1K_SPR_TTMR_IP (1 << CPU_OR1K_SPR_TTMR_SHAMT_IP) +#define CPU_OR1K_SPR_TTMR_IE (1 << CPU_OR1K_SPR_TTMR_SHAMT_IE) +#define CPU_OR1K_SPR_TTMR_MODE_RESTART (1 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) +#define CPU_OR1K_SPR_TTMR_MODE_ONE_SHOT (2 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) +#define CPU_OR1K_SPR_TTMR_MODE_CONT (3 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) + /* Power management register bits */ + +/* Shift amount macros for bit positions in Power Management register */ #define CPU_OR1K_SPR_PMR_SHAMT_SDF 0 #define CPU_OR1K_SPR_PMR_SHAMT_DME 4 #define CPU_OR1K_SPR_PMR_SHAMT_SME 5 @@ -271,8 +285,6 @@ #define CPU_OR1K_SPR_PMR_DCGE (1 << CPU_OR1K_SPR_PMR_SHAMT_DCGE) #define CPU_OR1K_SPR_PMR_SUME (1 << CPU_OR1K_SPR_PMR_SHAMT_SUME) -/* Shift amount macros for bit positions in Power Management register */ - #ifndef ASM #include From joel at rtems.org Mon Aug 18 23:31:17 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 18 Aug 2014 18:31:17 -0500 Subject: [rtems commit] rtems_termios_puts: Copy and write more than one char at once Message-ID: <20140818233118.0DB4D7006BA@git.rtems.org> Module: rtems Branch: master Commit: 3654667f77851c02b05bb3f964b8e56a5a529912 Changeset: http://git.rtems.org/rtems/commit/?id=3654667f77851c02b05bb3f964b8e56a5a529912 Author: Kolja Waschk Date: Thu Aug 14 10:02:29 2014 -0500 rtems_termios_puts: Copy and write more than one char at once Renamed startXmit(), nToSend is unsigned, just check FL_ORCVXOF, no (void) cast anymore, compute nToSend in single if/else if/else. --- cpukit/libcsupport/src/termios.c | 135 ++++++++++++++++++++++++-------------- 1 files changed, 85 insertions(+), 50 deletions(-) diff --git a/cpukit/libcsupport/src/termios.c b/cpukit/libcsupport/src/termios.c index 2448ea1..33cbacb 100644 --- a/cpukit/libcsupport/src/termios.c +++ b/cpukit/libcsupport/src/termios.c @@ -974,6 +974,49 @@ rtems_termios_ioctl (void *arg) } /* + * Send as many chars at once as possible to device-specific code. + * If transmitting==true then assume transmission is already running and + * an explicit write(0) is needed if output has to stop for flow control. + */ +static unsigned int +startXmit ( + struct rtems_termios_tty *tty, + unsigned int newTail, + bool transmitting +) +{ + unsigned int nToSend; + + tty->rawOutBufState = rob_busy; + + /* if XOFF was received, do not (re)start output */ + if (tty->flow_ctrl & FL_ORCVXOF) { + /* set flag, that output has been stopped */ + tty->flow_ctrl |= FL_OSTOP; + nToSend = 0; + /* stop transmitter */ + if (transmitting) { + (*tty->handler.write) (tty, NULL, 0); + } + } else { + /* when flow control XON or XOF, don't send blocks of data */ + /* to allow fast reaction on incoming flow ctrl and low latency*/ + /* for outgoing flow control */ + if (tty->flow_ctrl & (FL_MDXON | FL_MDXOF)) + nToSend = 1; + else if (newTail > tty->rawOutBuf.Head) + nToSend = tty->rawOutBuf.Size - newTail; + else + nToSend = tty->rawOutBuf.Head - newTail; + + (*tty->handler.write)( + tty, &tty->rawOutBuf.theBuf[newTail], nToSend); + } + + return nToSend; +} + +/* * Send characters to device-specific code */ void @@ -989,21 +1032,16 @@ rtems_termios_puts ( (*tty->handler.write)(tty, buf, len); return; } - newHead = tty->rawOutBuf.Head; + while (len) { - /* - * Performance improvement could be made here. - * Copy multiple bytes to raw buffer: - * if (len > 1) && (space to buffer end, or tail > 1) - * ncopy = MIN (len, space to buffer end or tail) - * memcpy (raw buffer, buf, ncopy) - * buf += ncopy - * len -= ncopy - * - * To minimize latency, the memcpy should be done - * with interrupts enabled. - */ - newHead = (newHead + 1) % tty->rawOutBuf.Size; + size_t nToCopy; + size_t nAvail; + + /* Check space for at least one char */ + newHead = tty->rawOutBuf.Head + 1; + if (newHead >= tty->rawOutBuf.Size) + newHead -= tty->rawOutBuf.Size; + rtems_termios_interrupt_lock_acquire (tty, &lock_context); while (newHead == tty->rawOutBuf.Tail) { tty->rawOutBufState = rob_wait; @@ -1014,21 +1052,41 @@ rtems_termios_puts ( rtems_fatal_error_occurred (sc); rtems_termios_interrupt_lock_acquire (tty, &lock_context); } - tty->rawOutBuf.theBuf[tty->rawOutBuf.Head] = *buf++; + + /* Determine free space up to current tail or end of ring buffer */ + nToCopy = len; + if (tty->rawOutBuf.Tail > tty->rawOutBuf.Head) { + /* Available space is contiguous from Head to Tail */ + nAvail = tty->rawOutBuf.Tail - tty->rawOutBuf.Head - 1; + } else { + /* Available space wraps at buffer end. To keep it simple, utilize + only the free space from Head to end during this iteration */ + nAvail = tty->rawOutBuf.Size - tty->rawOutBuf.Head; + /* Head may not touch Tail after wraparound */ + if (tty->rawOutBuf.Tail == 0) + nAvail--; + } + if (nToCopy > nAvail) + nToCopy = nAvail; + + /* To minimize latency, the memcpy could be done + * with interrupts enabled or with limit on nToCopy (TBD) + */ + memcpy(&tty->rawOutBuf.theBuf[tty->rawOutBuf.Head], buf, nToCopy); + + newHead = tty->rawOutBuf.Head + nToCopy; + if (newHead >= tty->rawOutBuf.Size) + newHead -= tty->rawOutBuf.Size; tty->rawOutBuf.Head = newHead; + if (tty->rawOutBufState == rob_idle) { - /* check, whether XOFF has been received */ - if (!(tty->flow_ctrl & FL_ORCVXOF)) { - (*tty->handler.write)( - tty, &tty->rawOutBuf.theBuf[tty->rawOutBuf.Tail],1); - } else { - /* remember that output has been stopped due to flow ctrl*/ - tty->flow_ctrl |= FL_OSTOP; - } - tty->rawOutBufState = rob_busy; + startXmit (tty, tty->rawOutBuf.Tail, false); } + rtems_termios_interrupt_lock_release (tty, &lock_context); - len--; + + buf += nToCopy; + len -= nToCopy; } } @@ -1678,35 +1736,12 @@ rtems_termios_refill_transmitter (struct rtems_termios_tty *tty) if ( tty->tty_snd.sw_pfn != NULL) { (*tty->tty_snd.sw_pfn)(&tty->termios, tty->tty_snd.sw_arg); } - } - /* check, whether output should stop due to received XOFF */ - else if ((tty->flow_ctrl & (FL_MDXON | FL_ORCVXOF)) - == (FL_MDXON | FL_ORCVXOF)) { - /* Buffer not empty, but output stops due to XOFF */ - /* set flag, that output has been stopped */ - tty->flow_ctrl |= FL_OSTOP; - tty->rawOutBufState = rob_busy; /*apm*/ - (*tty->handler.write) (tty, NULL, 0); - nToSend = 0; } else { /* - * Buffer not empty, start tranmitter + * Buffer not empty, check flow control, start transmitter */ - if (newTail > tty->rawOutBuf.Head) - nToSend = tty->rawOutBuf.Size - newTail; - else - nToSend = tty->rawOutBuf.Head - newTail; - /* when flow control XON or XOF, don't send blocks of data */ - /* to allow fast reaction on incoming flow ctrl and low latency*/ - /* for outgoing flow control */ - if (tty->flow_ctrl & (FL_MDXON | FL_MDXOF)) { - nToSend = 1; - } - tty->rawOutBufState = rob_busy; /*apm*/ - (*tty->handler.write)( - tty, &tty->rawOutBuf.theBuf[newTail], nToSend); + nToSend = startXmit (tty, newTail, true); } - tty->rawOutBuf.Tail = newTail; /*apm*/ } rtems_termios_interrupt_lock_release (tty, &lock_context); From sebh at rtems.org Wed Aug 20 06:09:33 2014 From: sebh at rtems.org (Sebastian Huber) Date: Wed, 20 Aug 2014 01:09:33 -0500 Subject: [rtems commit] score: PR2179: Fix initially locked PI mutex Message-ID: <20140820060933.D651C7006BA@git.rtems.org> Module: rtems Branch: master Commit: bba3507723041f451c9da1ecee43819bcbe57f23 Changeset: http://git.rtems.org/rtems/commit/?id=bba3507723041f451c9da1ecee43819bcbe57f23 Author: Sebastian Huber Date: Tue Aug 19 17:43:36 2014 +0200 score: PR2179: Fix initially locked PI mutex --- cpukit/score/src/coremutex.c | 15 +++++++++++---- testsuites/sptests/sp51/init.c | 36 ++++++++++++++++++++++++++++++++++++ testsuites/sptests/sp51/sp51.doc | 3 +++ 3 files changed, 50 insertions(+), 4 deletions(-) diff --git a/cpukit/score/src/coremutex.c b/cpukit/score/src/coremutex.c index e13c7aa..949aa70 100644 --- a/cpukit/score/src/coremutex.c +++ b/cpukit/score/src/coremutex.c @@ -39,10 +39,14 @@ CORE_mutex_Status _CORE_mutex_Initialize( the_mutex->Attributes = *the_mutex_attributes; if ( initially_locked ) { + bool is_priority_ceiling = + _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ); + the_mutex->nest_count = 1; the_mutex->holder = executing; - if ( _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) || - _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) { + + if ( is_priority_ceiling || + _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) ) { Priority_Control ceiling = the_mutex->Attributes.priority_ceiling; /* @@ -52,7 +56,7 @@ CORE_mutex_Status _CORE_mutex_Initialize( */ _Thread_Disable_dispatch(); - if ( executing->current_priority < ceiling ) { + if ( is_priority_ceiling && executing->current_priority < ceiling ) { _Thread_Enable_dispatch(); return CORE_MUTEX_STATUS_CEILING_VIOLATED; } @@ -65,7 +69,10 @@ CORE_mutex_Status _CORE_mutex_Initialize( executing->resource_count++; - _Thread_Change_priority( executing, ceiling, false ); + if ( is_priority_ceiling ) { + _Thread_Change_priority( executing, ceiling, false ); + } + _Thread_Enable_dispatch(); } } else { diff --git a/testsuites/sptests/sp51/init.c b/testsuites/sptests/sp51/init.c index 98d362f..48f0146 100644 --- a/testsuites/sptests/sp51/init.c +++ b/testsuites/sptests/sp51/init.c @@ -18,6 +18,40 @@ const char rtems_test_name[] = "SP 51"; /* forward declarations to avoid warnings */ rtems_task Init(rtems_task_argument argument); +static void test_create_initially_locked_prio_inherit_sema(void) +{ + rtems_status_code sc; + rtems_id id; + rtems_task_priority prio_a; + rtems_task_priority prio_b; + rtems_task_priority prio_ceiling = 0; + + sc = rtems_task_set_priority(RTEMS_SELF, RTEMS_CURRENT_PRIORITY, &prio_a); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + rtems_test_assert(prio_a != prio_ceiling); + + sc = rtems_semaphore_create( + rtems_build_name( 'S', 'E', 'M', 'A' ), + 0, + RTEMS_BINARY_SEMAPHORE | RTEMS_PRIORITY | RTEMS_INHERIT_PRIORITY, + prio_ceiling, + &id + ); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_task_set_priority(RTEMS_SELF, RTEMS_CURRENT_PRIORITY, &prio_b); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + rtems_test_assert(prio_a == prio_b); + + sc = rtems_semaphore_release(id); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_semaphore_delete(id); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); +} + rtems_task Init( rtems_task_argument argument ) @@ -57,6 +91,8 @@ rtems_task Init( fatal_directive_status( sc, RTEMS_NOT_OWNER_OF_RESOURCE, "rtems_semaphore_release" ); + test_create_initially_locked_prio_inherit_sema(); + TEST_END(); rtems_test_exit( 0 ); } diff --git a/testsuites/sptests/sp51/sp51.doc b/testsuites/sptests/sp51/sp51.doc index a1003db..fac5534 100644 --- a/testsuites/sptests/sp51/sp51.doc +++ b/testsuites/sptests/sp51/sp51.doc @@ -23,3 +23,6 @@ concepts: + Ensure the when the binary semaphore lock fails to acquire the mutex, it is an error to release it since the lock failed. + ++ Verify that creation of an initially locked priority inheritance mutex does + not change the priority of the executing thread. From sebh at rtems.org Wed Aug 20 06:12:24 2014 From: sebh at rtems.org (Sebastian Huber) Date: Wed, 20 Aug 2014 01:12:24 -0500 Subject: [rtems commit] score: PR2179: Fix initially locked PI mutex Message-ID: <20140820061224.8450C7006BA@git.rtems.org> Module: rtems Branch: 4.10 Commit: a62a3c32b1788f8d1dd318b5e36acc1cf16daf69 Changeset: http://git.rtems.org/rtems/commit/?id=a62a3c32b1788f8d1dd318b5e36acc1cf16daf69 Author: Sebastian Huber Date: Tue Aug 19 17:43:36 2014 +0200 score: PR2179: Fix initially locked PI mutex --- cpukit/score/src/coremutex.c | 14 ++++++++++---- testsuites/sptests/sp51/init.c | 36 ++++++++++++++++++++++++++++++++++++ testsuites/sptests/sp51/sp51.doc | 3 +++ 3 files changed, 49 insertions(+), 4 deletions(-) diff --git a/cpukit/score/src/coremutex.c b/cpukit/score/src/coremutex.c index 9745f82..261e18e 100644 --- a/cpukit/score/src/coremutex.c +++ b/cpukit/score/src/coremutex.c @@ -59,14 +59,19 @@ CORE_mutex_Status _CORE_mutex_Initialize( the_mutex->blocked_count = 0; if ( initial_lock == CORE_MUTEX_LOCKED ) { + bool is_priority_ceiling = + _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ); + the_mutex->nest_count = 1; the_mutex->holder = _Thread_Executing; the_mutex->holder_id = _Thread_Executing->Object.id; - if ( _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) || - _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) { + + if ( is_priority_ceiling || + _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) ) { Priority_Control ceiling = the_mutex->Attributes.priority_ceiling; - if ( _Thread_Executing->current_priority < ceiling ) + if ( is_priority_ceiling && + _Thread_Executing->current_priority < ceiling ) return CORE_MUTEX_STATUS_CEILING_VIOLATED; #ifdef __RTEMS_STRICT_ORDER_MUTEX__ _Chain_Prepend_unprotected( &_Thread_Executing->lock_mutex, @@ -75,7 +80,8 @@ CORE_mutex_Status _CORE_mutex_Initialize( #endif _Thread_Executing->resource_count++; - _Thread_Change_priority( _Thread_Executing, ceiling, false ); + if ( is_priority_ceiling ) + _Thread_Change_priority( _Thread_Executing, ceiling, false ); } } else { the_mutex->nest_count = 0; diff --git a/testsuites/sptests/sp51/init.c b/testsuites/sptests/sp51/init.c index 8f34cab..82deb53 100644 --- a/testsuites/sptests/sp51/init.c +++ b/testsuites/sptests/sp51/init.c @@ -11,6 +11,40 @@ #include +static void test_create_initially_locked_prio_inherit_sema(void) +{ + rtems_status_code sc; + rtems_id id; + rtems_task_priority prio_a; + rtems_task_priority prio_b; + rtems_task_priority prio_ceiling = 0; + + sc = rtems_task_set_priority(RTEMS_SELF, RTEMS_CURRENT_PRIORITY, &prio_a); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + rtems_test_assert(prio_a != prio_ceiling); + + sc = rtems_semaphore_create( + rtems_build_name( 'S', 'E', 'M', 'A' ), + 0, + RTEMS_BINARY_SEMAPHORE | RTEMS_PRIORITY | RTEMS_INHERIT_PRIORITY, + prio_ceiling, + &id + ); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_task_set_priority(RTEMS_SELF, RTEMS_CURRENT_PRIORITY, &prio_b); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + rtems_test_assert(prio_a == prio_b); + + sc = rtems_semaphore_release(id); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_semaphore_delete(id); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); +} + rtems_task Init( rtems_task_argument argument ) @@ -50,6 +84,8 @@ rtems_task Init( sc = rtems_semaphore_release( mutex ); directive_failed( sc, "rtems_semaphore_release" ); + test_create_initially_locked_prio_inherit_sema(); + puts( "*** END OF TEST 51 ***" ); rtems_test_exit( 0 ); } diff --git a/testsuites/sptests/sp51/sp51.doc b/testsuites/sptests/sp51/sp51.doc index bbf162a..fee5cf3 100644 --- a/testsuites/sptests/sp51/sp51.doc +++ b/testsuites/sptests/sp51/sp51.doc @@ -26,3 +26,6 @@ concepts: + Ensure the when the binary semaphore lock fails to acquire the mutex, it is an error to release it since the lock failed. + ++ Verify that creation of an initially locked priority inheritance mutex does + not change the priority of the executing thread. From sebh at rtems.org Wed Aug 20 11:34:17 2014 From: sebh at rtems.org (Sebastian Huber) Date: Wed, 20 Aug 2014 06:34:17 -0500 Subject: [rtems commit] lpc24xx/lpc17xx: lpc24xx_pin_set_function() keep LPC4088 W type pin in digital mode for non-analog function. Message-ID: <20140820113417.63B727006BA@git.rtems.org> Module: rtems Branch: master Commit: 0a66c1266f1f0968345b2a0bcb7acbeeba0c1d82 Changeset: http://git.rtems.org/rtems/commit/?id=0a66c1266f1f0968345b2a0bcb7acbeeba0c1d82 Author: Pavel Pisa Date: Sat Aug 16 16:15:17 2014 +0200 lpc24xx/lpc17xx: lpc24xx_pin_set_function() keep LPC4088 W type pin in digital mode for non-analog function. The problem wit incorrect switching of pins into analog mode manifestes on LPC4088 based board. LPC4088 implements pin P1.17 (ENET_MDIO) as new W type (digital pin with analog option). The pin was listed as D category on LPC1788 which does not have analog mode control bit. If analog option is not explicitly switched off on LPC4088 then the pin does not work as digital pin. Code tested on LPC1788 and no problems has been observed even that manual specifies the IOCON_ADMODE field as reserved and should be written as zero. But even RTEMS lpc24xx_gpio_config sets this bit unconditionally. Signed-off-by: Pavel Pisa --- c/src/lib/libbsp/arm/lpc24xx/misc/io.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/arm/lpc24xx/misc/io.c b/c/src/lib/libbsp/arm/lpc24xx/misc/io.c index 45e0c94..c28b518 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/misc/io.c +++ b/c/src/lib/libbsp/arm/lpc24xx/misc/io.c @@ -395,9 +395,14 @@ lpc24xx_pin_set_function( rtems_interrupt_enable(level); #else uint32_t iocon_extra = 0; + uint32_t iocon_not_analog = IOCON_ADMODE; /* TODO */ switch (pin_range.fields.type) { + case LPC17XX_PIN_TYPE_ADC: + case LPC17XX_PIN_TYPE_DAC: + iocon_not_analog = 0; + break; case LPC17XX_PIN_TYPE_I2C_FAST_PLUS: iocon_extra |= IOCON_HS; break; @@ -408,7 +413,7 @@ lpc24xx_pin_set_function( break; } - *iocon = IOCON_FUNC(pin_range.fields.function) | iocon_extra; + *iocon = IOCON_FUNC(pin_range.fields.function) | iocon_extra | iocon_not_analog; #endif return RTEMS_SUCCESSFUL; From gedare at rtems.org Wed Aug 20 17:37:01 2014 From: gedare at rtems.org (Gedare Bloom) Date: Wed, 20 Aug 2014 12:37:01 -0500 Subject: [rtems commit] BSP for TMS570LS31x Hercules Development Kit from TI ( TMS570LS3137) Message-ID: <20140820173701.E2DAB7006BA@git.rtems.org> Module: rtems Branch: master Commit: 4407ee675cb22e8bb870a76eafc590eb6e754315 Changeset: http://git.rtems.org/rtems/commit/?id=4407ee675cb22e8bb870a76eafc590eb6e754315 Author: Premysl Houdek Date: Wed Aug 20 17:24:23 2014 +0200 BSP for TMS570LS31x Hercules Development Kit from TI (TMS570LS3137) Included variants: tms570ls3137_hdk_intram - place code and data into internal SRAM tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM tms570ls3137_hdk - variant prepared for stand-alone RTEMS aplication stored and running directly from flash. Not working yet. Chip initialization code not included in BSP. External startup generated by TI's HalCoGen was used for testing and debugging. More information about TMS570 BSP can be found at http://www.rtems.org/wiki/index.php/Tms570 Patch version 2 - most of the formatting suggestion applied. - BSP converted to use clock shell - console driver "set attributes" tested. Baudrate change working Patch version 3 - more formatting changes. - removed leftover defines and test functions Todo: refactor header files (name register fields) --- c/src/lib/libbsp/arm/tms570/Makefile.am | 145 +++++ c/src/lib/libbsp/arm/tms570/README | 67 +++ c/src/lib/libbsp/arm/tms570/bsp_specs | 13 + c/src/lib/libbsp/arm/tms570/clock/clock.c | 159 ++++++ c/src/lib/libbsp/arm/tms570/configure.ac | 52 ++ .../lib/libbsp/arm/tms570/console/printk-support.c | 85 +++ c/src/lib/libbsp/arm/tms570/console/tms570-sci.c | 559 ++++++++++++++++++++ c/src/lib/libbsp/arm/tms570/include/bsp.h | 59 ++ c/src/lib/libbsp/arm/tms570/include/irq.h | 156 ++++++ c/src/lib/libbsp/arm/tms570/include/tms570-pom.h | 101 ++++ c/src/lib/libbsp/arm/tms570/include/tms570-rti.h | 95 ++++ .../libbsp/arm/tms570/include/tms570-sci-driver.h | 57 ++ c/src/lib/libbsp/arm/tms570/include/tms570-sci.h | 76 +++ c/src/lib/libbsp/arm/tms570/include/tms570-vim.h | 75 +++ c/src/lib/libbsp/arm/tms570/include/tms570.h | 28 + c/src/lib/libbsp/arm/tms570/irq/irq.c | 207 ++++++++ .../make/custom/tms570ls3137_hdk-testsuite.tcfg | 19 + .../arm/tms570/make/custom/tms570ls3137_hdk.cfg | 20 + .../tms570/make/custom/tms570ls3137_hdk_intram.cfg | 20 + .../tms570/make/custom/tms570ls3137_hdk_sdram.cfg | 20 + c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c | 53 ++ c/src/lib/libbsp/arm/tms570/preinstall.am | 123 +++++ c/src/lib/libbsp/arm/tms570/startup/bspreset.c | 36 ++ c/src/lib/libbsp/arm/tms570/startup/bspstart.c | 41 ++ .../lib/libbsp/arm/tms570/startup/bspstarthooks.c | 41 ++ .../arm/tms570/startup/linkcmds.tms570ls3137_hdk | 27 + .../startup/linkcmds.tms570ls3137_hdk_intram | 28 + .../tms570/startup/linkcmds.tms570ls3137_hdk_sdram | 27 + 28 files changed, 2389 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/arm/tms570/Makefile.am b/c/src/lib/libbsp/arm/tms570/Makefile.am new file mode 100644 index 0000000..02d7b66 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/Makefile.am @@ -0,0 +1,145 @@ +## +# +# @file makefile.am +# +# @brief Makefile of LibBSP for the TMS570 boards. +# + +ACLOCAL_AMFLAGS = -I ../../../../aclocal + +include $(top_srcdir)/../../../../automake/compile.am + +include_bspdir = $(includedir)/bsp + +dist_project_lib_DATA = bsp_specs + +# ---------------------------- +# ------ Headers +# ---------------------------- + +include_HEADERS = include/bsp.h + +nodist_include_HEADERS = ../../shared/include/coverhd.h +nodist_include_HEADERS += include/bspopts.h + +nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h + +include_bsp_HEADERS = +include_bsp_HEADERS += ../../shared/include/utility.h +include_bsp_HEADERS += ../../shared/include/irq-generic.h +include_bsp_HEADERS += ../../shared/include/irq-info.h +include_bsp_HEADERS += ../../shared/include/stackalloc.h +include_bsp_HEADERS += ../../shared/include/uart-output-char.h +include_bsp_HEADERS += ../../shared/tod.h +include_bsp_HEADERS += ../shared/include/start.h +include_bsp_HEADERS += include/tms570.h +include_bsp_HEADERS += include/tms570-sci.h +include_bsp_HEADERS += include/irq.h +include_bsp_HEADERS += include/tms570-rti.h +include_bsp_HEADERS += include/tms570-vim.h +include_bsp_HEADERS += include/tms570-pom.h +include_bsp_HEADERS += include/tms570-sci-driver.h + +include_HEADERS += ../../shared/include/tm27.h + +# ---------------------------- +# ------ Data +# ---------------------------- + +noinst_LIBRARIES = libbspstart.a + +libbspstart_a_SOURCES = ../shared/start/start.S + +project_lib_DATA = start.$(OBJEXT) +project_lib_DATA += startup/linkcmds + +EXTRA_DIST = +EXTRA_DIST += startup/linkcmds.tms570ls3137_hdk +EXTRA_DIST += startup/linkcmds.tms570ls3137_hdk_sdram +EXTRA_DIST += startup/linkcmds.tms570ls3137_hdk_intram + +# ---------------------------- +# ------ LibBSP +# ---------------------------- + +noinst_LIBRARIES += libbsp.a + +libbsp_a_SOURCES = +libbsp_a_CPPFLAGS = +libbsp_a_LIBADD = + +# Shared +libbsp_a_SOURCES += ../../shared/bootcard.c +libbsp_a_SOURCES += ../../shared/bspclean.c +libbsp_a_SOURCES += ../../shared/bspgetworkarea.c +libbsp_a_SOURCES += ../../shared/bsplibc.c +libbsp_a_SOURCES += ../../shared/bsppost.c +libbsp_a_SOURCES += ../../shared/bsppredriverhook.c +libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c +libbsp_a_SOURCES += ../../shared/sbrk.c +libbsp_a_SOURCES += ../../shared/src/stackalloc.c + +# Startup +libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S +libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c +libbsp_a_SOURCES += startup/bspreset.c +libbsp_a_SOURCES += startup/bspstart.c + +# POM +libbsp_a_SOURCES += pom/tms570-pom.c + +# IRQ +libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c +libbsp_a_SOURCES += ../../shared/src/irq-generic.c +libbsp_a_SOURCES += ../../shared/src/irq-info.c +libbsp_a_SOURCES += ../../shared/src/irq-legacy.c +libbsp_a_SOURCES += ../../shared/src/irq-server.c +libbsp_a_SOURCES += ../../shared/src/irq-shell.c +libbsp_a_SOURCES += irq/irq.c + +# Console +libbsp_a_SOURCES += ../../shared/console-termios.c +libbsp_a_SOURCES += console/printk-support.c +libbsp_a_SOURCES += console/tms570-sci.c + +# Clock +libbsp_a_SOURCES += ../../shared/clockdrv_shell.h +libbsp_a_SOURCES += clock/clock.c + +# RTC + +# GPIO + +# Timer + +# Benchmark Timer + +# Misc + +# Watchdog + +# Start hooks +libbsp_a_SOURCES += startup/bspstarthooks.c + +# Network + +if HAS_NETWORKING + +noinst_PROGRAMS = network.rel + +network_rel_CPPFLAGS = $(AM_CPPFLAGS) +network_rel_CPPFLAGS += -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE +network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + +libbsp_a_LIBADD += network.rel + +endif + +# ---------------------------- +# ------ Special Rules +# ---------------------------- + +DISTCLEANFILES = include/bspopts.h + +include $(srcdir)/preinstall.am +include $(top_srcdir)/../../../../automake/local.am diff --git a/c/src/lib/libbsp/arm/tms570/README b/c/src/lib/libbsp/arm/tms570/README new file mode 100644 index 0000000..e1be925 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/README @@ -0,0 +1,67 @@ +Development Board: TMS570LS31x Hercules Development Kit from TI + +http://www.ti.com/tool/tmds570ls31hdk + +Drivers: + + o Console + o Clock + o Ethernet - work in progress + +BSP variants: + tms570ls3137_hdk_intram - place code and data into internal SRAM + tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM + tms570ls3137_hdk - variant prepared for stand-alone RTEMS application + stored and running directly from flash. Not working yet. + +Tool-chain + GCC 4.9.0 + Newlib 2.1.0 + Binutils 2.24 configuration: + + CFLAGS="-O2 -pipe" LDFLAGS=-s \ + ../../../src/gcc-4.9/configure --target=arm-rtems4.11 --prefix=/usr \ + --enable-languages=c,c++ \ + --disable-libstdcxx-pch \ + --with-gnu-ld \ + --with-gnu-as \ + --enable-threads \ + --enable-target-optspace \ + --with-system-zlib \ + --verbose \ + --disable-nls --without-included-gettext \ + --disable-win32-registry \ + --with-newlib \ + --enable-plugin \ + --enable-newlib-io-c99-formats \ + --enable-version-specific-runtime-libs \ + --enable-newlib-iconv \ + --disable-lto \ + +Patches required for Cortex-R and big-endian ARM support are already +accepted by the mainline. + +Execution + +Currently, a bootloader is not used. For test and debug purposes, TI's +HalCoGen generated application is used to set up the board and then +the RTEMS application image is loaded using OpenOCD to internal +EEC SRAM or external DRAM. The following features are +not implemented in the BSP: + + + Initial complex CPU and peripheral initialization + + Cores Self-test + +Setup application code is available there: + https://github.com/hornmich/tms570ls3137-hdk-sdram + +Howto setup TMDS570LS31HDK? + + o Unpack board. + o Verify that demo application runs. + o Upload bootloader specified above + o write BSP application either to sdram or intram and jump to RTEMS start code + +Additional information about the board can be found at + http://www.rtems.org/wiki/index.php/Tms570 + +Additional information about the CPU can be found at + http://www.ti.com/product/tms570ls3137 diff --git a/c/src/lib/libbsp/arm/tms570/bsp_specs b/c/src/lib/libbsp/arm/tms570/bsp_specs new file mode 100644 index 0000000..1afa2ba --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/bsp_specs @@ -0,0 +1,13 @@ +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -EB } + +*endfile: +%{!qrtems: *(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s } diff --git a/c/src/lib/libbsp/arm/tms570/clock/clock.c b/c/src/lib/libbsp/arm/tms570/clock/clock.c new file mode 100644 index 0000000..2a8bb5f --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/clock/clock.c @@ -0,0 +1,159 @@ +/** + * @file clock.c + * + * @ingroup tms570 + * + * @brief clock functions definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#include +#include +#include +#include + +/** + * holds HW counter value since last interrupt event + * sets in tms570_clock_driver_support_at_tick + * used in tms570_clock_driver_nanoseconds_since_last_tick + */ +static uint32_t tms570_rti_last_tick_fcr0; + +/** + * @brief Initialize the HW peripheral for clock driver + * + * Clock driver is implemented by RTI module + * + * @retval Void + */ +static void tms570_clock_driver_support_initialize_hardware( void ) +{ + + uint32_t microsec_per_tick = rtems_configuration_get_microseconds_per_tick(); + + /* Hardware specific initialize */ + TMS570_RTI.RTIGCTRL = 0; + TMS570_RTI.RTICPUC0 = BSP_PLL_OUT_CLOCK /1000000 / 2; /* prescaler */ + TMS570_RTI.RTITBCTRL = 2; + TMS570_RTI.RTICAPCTRL = 0; + TMS570_RTI.RTICOMPCTRL = 0; + /* set counter to zero */ + TMS570_RTI.RTIUC0 = 0; + TMS570_RTI.RTIFRC0 = 0; + /* clear interrupts*/ + TMS570_RTI.RTICLEARINTENA = 0x00070f0f; + TMS570_RTI.RTIINTFLAG = 0x0007000f; + /* set timer */ + TMS570_RTI.RTICOMP0 = TMS570_RTI.RTIFRC0 + microsec_per_tick; + TMS570_RTI.RTICOMP0CLR = TMS570_RTI.RTICOMP0 + microsec_per_tick / 2; + TMS570_RTI.RTIUDCP0 = microsec_per_tick; + /* enable interupt */ + TMS570_RTI.RTISETINTENA = 0x1; + /* enable timer */ + TMS570_RTI.RTIGCTRL = 1; +} + +/** + * @brief Clears interrupt source + * + * @retval Void + */ +static void tms570_clock_driver_support_at_tick( void ) +{ + TMS570_RTI.RTIINTFLAG = 0x00000001; + tms570_rti_last_tick_fcr0 = TMS570_RTI.RTICOMP0 - TMS570_RTI.RTIUDCP0; + /* TMS570_RTI.RTICOMP0 += 1000; */ +} + +/** + * @brief registers RTI interrupt handler + * + * @param[in] Clock_isr new ISR handler + * @param[in] Old_ticker old ISR handler (unused and type broken) + * + * @retval Void + */ +static void tms570_clock_driver_support_install_isr( + rtems_isr_entry Clock_isr +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + sc = rtems_interrupt_handler_install( + TMS570_IRQ_TIMER_0, + "Clock", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) Clock_isr, + NULL + ); + if ( sc != RTEMS_SUCCESSFUL ) { + rtems_fatal_error_occurred(0xdeadbeef); + } +} + +/** + * @brief disables RTI interrupt + * + * Called when closing clock driver + * + * @retval Void + */ +static void tms570_clock_driver_support_shutdown_hardware( void ) +{ + /* turn off the timer interrupts */ + TMS570_RTI.RTICLEARINTENA = 0x20000; +} + +/** + * @brief returns the nanoseconds since last tick + * + * Return the nanoseconds since last tick + * + * @retval x nanoseconds + * + */ +static uint32_t tms570_clock_driver_nanoseconds_since_last_tick( void ) +{ + uint32_t actual_fcr0 = TMS570_RTI.RTIFRC0; + uint32_t usec_since_tick; + + usec_since_tick = actual_fcr0 - tms570_rti_last_tick_fcr0; + + return usec_since_tick * 1000; +} + +#define Clock_driver_support_initialize_hardware \ + tms570_clock_driver_support_initialize_hardware +#define Clock_driver_support_at_tick \ + tms570_clock_driver_support_at_tick +#define Clock_driver_support_initialize_hardware \ + tms570_clock_driver_support_initialize_hardware +#define Clock_driver_support_shutdown_hardware \ + tms570_clock_driver_support_shutdown_hardware +#define Clock_driver_nanoseconds_since_last_tick \ + tms570_clock_driver_nanoseconds_since_last_tick + +#define Clock_driver_support_install_isr(Clock_isr, Old_ticker ) \ + tms570_clock_driver_support_install_isr( Clock_isr ) + +void Clock_isr(void *arg); /* to supress warning */ + +#include "../../../shared/clockdrv_shell.h" diff --git a/c/src/lib/libbsp/arm/tms570/configure.ac b/c/src/lib/libbsp/arm/tms570/configure.ac new file mode 100644 index 0000000..10a2920 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/configure.ac @@ -0,0 +1,52 @@ +## +# +# @file configure.ac +# +# @brief Configure script of LibBSP for the TMS570 board. +# + +AC_PREREQ([2.69]) +AC_INIT([rtems-c-src-lib-libbsp-arm-tms570],[_RTEMS_VERSION], + [http://www.rtems.org/bugzilla]) +AC_CONFIG_SRCDIR([bsp_specs]) +RTEMS_TOP(../../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) +RTEMS_BSP_CONFIGURE + +RTEMS_PROG_CC_FOR_TARGET +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +RTEMS_CHECK_NETWORKING +AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "no") + +RTEMS_BSPOPTS_SET([TMS570_SCI_BAUD_RATE],[*],[115200U]) +RTEMS_BSPOPTS_HELP([TMS570_SCI_BAUD_RATE],[baud for UARTs]) + +RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[1]) +RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS], +[The tms570 console driver can operate in either polled or interrupt mode.]) + +RTEMS_BSPOPTS_SET([ARM_TMS570LS3137],[*],[0]) +RTEMS_BSPOPTS_HELP([ARM_TMS570LS3137],[target used for identify TMS570LS3137 board]) + +RTEMS_BSPOPTS_SET([BSP_MINIMUM_TASK_STACK_SIZE],[*],[1024]) +RTEMS_BSPOPTS_HELP([BSP_MINIMUM_TASK_STACK_SIZE],[Suggested minimum task stack + size in bytes]) + +RTEMS_BSPOPTS_SET([TMS570_OSCILLATOR_MAIN],[*],[12000000U]) +RTEMS_BSPOPTS_HELP([TMS570_OSCILLATOR_MAIN],[main oscillator frequency in Hz]) + +RTEMS_BSPOPTS_SET([TMS570_OSCILLATOR_RTC],[*],[32768U]) +RTEMS_BSPOPTS_HELP([TMS570_OSCILLATOR_RTC],[RTC oscillator frequency in Hz]) + +RTEMS_BSPOPTS_SET([TMS570_CCLK],[*],[96000000U]) +RTEMS_BSPOPTS_HELP([TMS570_CCLK],[CPU clock in Hz]) + +RTEMS_BSP_CLEANUP_OPTIONS(0, 1) +RTEMS_BSP_LINKCMDS + +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/arm/tms570/console/printk-support.c b/c/src/lib/libbsp/arm/tms570/console/printk-support.c new file mode 100644 index 0000000..241ca9b --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/console/printk-support.c @@ -0,0 +1,85 @@ +/** + * @file printk-support.c + * + * @ingroup tms570 + * + * @brief definitions of serial line for debugging. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include + + +/** + * @brief Puts chars into peripheral + * + * debug functions always use serial dev 0 peripheral + * + * @retval Void + */ +static void tms570_putc(char ch) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + while ( ( driver_context_table[0].regs->SCIFLR & 0x100 ) == 0) { + rtems_interrupt_flash(level); + } + driver_context_table[0].regs->SCITD = ch; + rtems_interrupt_enable(level); +} + +/** + * @brief debug console output + * + * debug functions always use serial dev 0 peripheral + * + * @retval Void + */ +static void tms570_uart_output(char c) +{ + if ( c == '\n' ) { + char r = '\r'; + tms570_putc(r); + } + tms570_putc(c); +} + +/** + * @brief debug console input + * + * debug functions always use serial dev 0 peripheral + * + * @retval x Read char + * @retval -1 No input character available + */ +static int tms570_uart_input( void ) +{ + if ( driver_context_table[0].regs->SCIFLR & (1<<9) ) { + return driver_context_table[0].regs->SCIRD; + } else { + return -1; + } +} + +BSP_output_char_function_type BSP_output_char = tms570_uart_output; +BSP_polling_getchar_function_type BSP_poll_char = tms570_uart_input; diff --git a/c/src/lib/libbsp/arm/tms570/console/tms570-sci.c b/c/src/lib/libbsp/arm/tms570/console/tms570-sci.c new file mode 100644 index 0000000..8aa3caf --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/console/tms570-sci.c @@ -0,0 +1,559 @@ +/** + * @file tms570-sci.c + * + * @ingroup tms570 + * + * @brief Serial communication interface (SCI) functions definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TMS570_SCI_BUFFER_SIZE 1 + +/** + * @brief Table including all serial drivers + * + * Definitions of all serial drivers + */ +const tms570_sci_context driver_context_table[] = { + { + .device_name = "/dev/console", + .regs = &TMS570_SCI, + .irq = TMS570_IRQ_SCI_LEVEL_0, + }, + { + .device_name = "/dev/ttyS1", + .regs = &TMS570_SCI2, + .irq = TMS570_IRQ_SCI2_LEVEL_0, + } +}; + +/** + * @brief Serial drivers init function + * + * Initialize all serial drivers specified in driver_context_table + * + * @param[in] major + * @param[in] minor + * @param[in] arg + * @retval RTEMS_SUCCESSFUL Initialization completed + */ +rtems_device_driver console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code sc; +#if CONSOLE_USE_INTERRUPTS + const rtems_termios_device_handler *handler = &tms570_sci_handler_interrupt; +#else + const rtems_termios_device_handler *handler = &tms570_sci_handler_polled; +#endif + + /* + * Initialize the Termios infrastructure. If Termios has already + * been initialized by another device driver, then this call will + * have no effect. + */ + rtems_termios_initialize(); + + /* Initialize each device */ + for ( + minor = 0; + minor < RTEMS_ARRAY_SIZE(driver_context_table); + ++minor + ) { + const tms570_sci_context *ctx = &driver_context_table[minor]; + + /* + * Install this device in the file system and Termios. In order + * to use the console (i.e. being able to do printf, scanf etc. + * on stdin, stdout and stderr), one device must be registered as + * "/dev/console" (CONSOLE_DEVICE_NAME). + */ + sc = rtems_termios_device_install( + ctx->device_name, + major, + minor, + handler, + (void *) ctx + ); + if ( sc != RTEMS_SUCCESSFUL ) { + bsp_fatal(BSP_FATAL_CONSOLE_NO_DEV); + } + } + return RTEMS_SUCCESSFUL; +} + +/** + * @brief Reads chars from HW + * + * Reads chars from HW peripheral specified in driver context. + * TMS570 does not have HW buffer for serial line so this function can + * return only 0 or 1 char + * + * @param[in] ctx context of the driver + * @param[out] buf read data buffer + * @param[in] N size of buffer + * @retval x Number of read chars from peripherals + */ +static int tms570_sci_read_received_chars( + tms570_sci_context * ctx, + char * buf, + int N) +{ + if ( N < 1 ) { + return 0; + } + if ( ctx->regs->SCIRD != 0 ) { + buf[0] = ctx->regs->SCIRD; + return 1; + } + return 0; +} + +/** + * @brief Enables RX interrupt + * + * Enables RX interrupt source of SCI peripheral + * specified in the driver context. + * + * @param[in] ctx context of the driver + * @retval Void + */ +static void tms570_sci_enable_interrupts(tms570_sci_context * ctx) +{ + ctx->regs->SCISETINT = (1<<9); +} + +/** + * @brief Disables RX interrupt + * + * Disables RX interrupt source of SCI peripheral specified in the driver + * context. + * + * @param[in] ctx context of the driver + * @retval Void + */ +static void tms570_sci_disable_interrupts(tms570_sci_context * ctx) +{ + ctx->regs->SCICLEARINT = (1<<9); +} + +/** + * @brief Check whether driver has put char in HW + * + * Check whether driver has put char in HW. + * This information is read from the driver context not from a peripheral. + * TMS570 does not have write data buffer asociated with SCI + * so the return can be only 0 or 1. + * + * @param[in] ctx context of the driver + * @retval x + */ +static int tms570_sci_transmitted_chars(tms570_sci_context * ctx) +{ + int ret; + + ret = ctx->tx_chars_in_hw; + if ( ret == 1 ) { + ctx->tx_chars_in_hw = 0; + return 1; + } + return ret; +} + +/** + * @brief Set attributes of the HW peripheral + * + * Sets attributes of the HW peripheral (parity, baud rate, etc.) + * + * @param[in] tty rtems_termios_tty + * @param[in] t termios driver + * @retval true peripheral setting is changed + */ +static bool tms570_sci_set_attributes( + rtems_termios_tty *tty, + const struct termios *t +) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + rtems_interrupt_lock_context lock_context; + int32_t bauddiv; + int32_t baudrate; + + rtems_termios_interrupt_lock_acquire(tty, &lock_context); + + ctx->regs->SCIGCR1 &= ~( (1<<7) | (1<<25) | (1<<24) ); + + ctx->regs->SCIGCR1 &= ~(1<<4); /*one stop bit*/ + ctx->regs->SCIFORMAT = 0x7; + + switch ( t->c_cflag & ( PARENB|PARODD ) ) { + case ( PARENB|PARODD ): + /* Odd parity */ + ctx->regs->SCIGCR1 &= ~(1<<3); + ctx->regs->SCIGCR1 |= (1<<2); + break; + + case PARENB: + /* Even parity */ + ctx->regs->SCIGCR1 |= (1<<3); + ctx->regs->SCIGCR1 |= (1<<2); + break; + + default: + case 0: + case PARODD: + /* No Parity */ + ctx->regs->SCIGCR1 &= ~(1<<2); + } + + /* Baud rate */ + baudrate = rtems_termios_baud_to_number(cfgetospeed(t)); + baudrate *= 2 * 16; + bauddiv = (BSP_PLL_OUT_CLOCK + baudrate / 2) / baudrate; + ctx->regs->BRS = bauddiv; + + ctx->regs->SCIGCR1 |= (1<<7) | (1<<25) | (1<<24); + + rtems_termios_interrupt_lock_release(tty, &lock_context); + + return true; +} + +/** + * @brief sci interrupt handler + * + * Handler checks which interrupt occured and provides nessesary maintenance + * dequeue characters in termios driver whether character is send succesfully + * enqueue characters in termios driver whether character is recieved + * + * @param[in] arg rtems_termios_tty + * @retval Void + */ +static void tms570_sci_interrupt_handler(void * arg) +{ + rtems_termios_tty *tty = arg; + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + char buf[TMS570_SCI_BUFFER_SIZE]; + size_t n; + + /* + * Check if we have received something. + */ + if ( (ctx->regs->SCIFLR & (1<<9) ) == (1<<9) ) { + n = tms570_sci_read_received_chars(ctx, buf, TMS570_SCI_BUFFER_SIZE); + if ( n > 0 ) { + /* Hand the data over to the Termios infrastructure */ + rtems_termios_enqueue_raw_characters(tty, buf, n); + } + } + /* + * Check if we have something transmitted. + */ + if ( (ctx->regs->SCIFLR & (1<<8) ) == (1<<8) ) { + n = tms570_sci_transmitted_chars(ctx); + if ( n > 0 ) { + /* + * Notify Termios that we have transmitted some characters. It + * will call now the interrupt write function if more characters + * are ready for transmission. + */ + rtems_termios_dequeue_characters(tty, n); + } + } +} + +/** + * @brief sci write function called from interrupt + * + * Nonblocking write function. Writes characters to HW peripheral + * TMS570 does not have write data buffer asociated with SCI + * so only one character can be written. + * + * @param[in] tty rtems_termios_tty + * @param[in] buf buffer of characters pending to send + * @param[in] len size of the buffer + * @retval Void + */ +static void tms570_sci_interrupt_write( + rtems_termios_tty *tty, + const char *buf, + size_t len +) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + + if ( len > 0 ) { + /* start UART TX, this will result in an interrupt when done */ + ctx->regs->SCITD = *buf; + /* character written - raise count*/ + ctx->tx_chars_in_hw = 1; + /* Enable TX interrupt (interrupt is edge-triggered) */ + ctx->regs->SCISETINT = (1<<8); + + } else { + /* No more to send, disable TX interrupts */ + ctx->regs->SCICLEARINT = (1<<8); + /* Tell close that we sent everything */ + } +} + +/** + * @brief sci write function + * + * Blocking write function. Waits until HW peripheral is ready and then writes + * character to HW peripheral. Writes all characters in the buffer. + * + * @param[in] tty rtems_termios_tty + * @param[in] buf buffer of characters pending to send + * @param[in] len size of the buffer + * @retval Void + */ +static void tms570_sci_poll_write( + rtems_termios_tty *tty, + const char *buf, + size_t n +) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + size_t i; + + /* Write */ + + for ( i = 0; i < n; ++i ) { + while ( (ctx->regs->SCIFLR & (1<<11) ) == 0) { + ; + } + ctx->regs->SCITD = buf[i]; + } +} + +/** + * @brief See if there is recieved charakter to read + * + * read the RX flag from peripheral specified in context + * + * @param[in] ctx context of the driver + * @retval 0 No character to read + * @retval x Character ready to read + */ +static int TMS570_sci_can_read_char( + tms570_sci_context * ctx +) +{ + return ctx->regs->SCIFLR & (1<<9); +} + +/** + * @brief reads character from peripheral + * + * reads the recieved character from peripheral specified in context + * + * @param[in] ctx context of the driver + * @retval x Character + */ +static char TMS570_sci_read_char( + tms570_sci_context * ctx +) +{ + return ctx->regs->SCIRD; +} + +/** + * @brief sci read function + * + * check if there is recieved character to be read and reads it. + * + * @param[in] tty rtems_termios_tty (context of the driver) + * @retval -1 No character to be read + * @retval x Read character + */ +static int tms570_sci_poll_read(rtems_termios_tty *tty) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + + /* Check if a character is available */ + if ( TMS570_sci_can_read_char(ctx) ) { + return TMS570_sci_read_char(ctx); + } else { + return -1; + } +} + +/** + * @brief initialization of the driver + * + * initialization of the HW peripheral specified in contex of the driver. + * This function is called only once when opening the driver. + * + * @param[in] tty context of the driver + * @param[in] args + * @retval false Error occured during initialization + * @retval true Driver is open and ready + */ +static bool tms570_sci_poll_first_open( + rtems_termios_tty *tty, + rtems_libio_open_close_args_t *args +) +{ + bool ok; + + rtems_termios_set_best_baud(tty, TMS570_SCI_BAUD_RATE); + ok = tms570_sci_set_attributes(tty, rtems_termios_get_termios(tty)); + if ( !ok ) { + return false; + } + return true; +} + +/** + * @brief initialization of the interrupt driven driver + * + * calls tms570_sci_poll_first_open function. + * install and enables interrupts. + * + * @param[in] tty context of the driver + * @param[in] args + * @retval false Error occured during initialization + * @retval true Driver is open and ready + */ +static bool tms570_sci_interrupt_first_open( + rtems_termios_tty *tty, + rtems_libio_open_close_args_t *args +) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + rtems_status_code sc; + bool ret; + + ret = tms570_sci_poll_first_open(tty,args); + if ( ret == false ) { + return false; + } + ctx->regs->SCISETINTLVL = 0; + /* Register Interrupt handler */ + sc = rtems_interrupt_handler_install(ctx->irq, + ctx->device_name, + RTEMS_INTERRUPT_SHARED, + tms570_sci_interrupt_handler, + tty + ); + if ( sc != RTEMS_SUCCESSFUL ) { + return false; + } + tms570_sci_enable_interrupts(rtems_termios_get_device_context(tty)); + return true; +} + +/** + * @brief closes sci peripheral + * + * @param[in] tty context of the driver + * @param[in] args + * @retval false Error occured during initialization + * @retval true Driver is open and ready + */ +static void tms570_sci_poll_last_close( + rtems_termios_tty *tty, + rtems_libio_open_close_args_t *args +) +{ + ; +} + +/** + * @brief closes sci peripheral of interrupt driven driver + * + * calls tms570_sci_poll_last_close and disables interrupts + * + * @param[in] tty context of the driver + * @param[in] args + * @retval false Error occured during initialization + * @retval true Driver is open and ready + */ +static void tms570_sci_interrupt_last_close( + rtems_termios_tty *tty, + rtems_libio_open_close_args_t *args +) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + rtems_interrupt_lock_context lock_context; + + /* Turn off RX interrupts */ + rtems_termios_interrupt_lock_acquire(tty, &lock_context); + tms570_sci_disable_interrupts(ctx); + rtems_termios_interrupt_lock_release(tty, &lock_context); + + /* Flush device */ + while ( ( ctx->regs->SCIFLR & (1<<11) ) > 0 ) { + ;/* Wait until all data has been sent */ + } + + /* uninstall ISR */ + rtems_interrupt_handler_remove(ctx->irq, tms570_sci_interrupt_handler, tty); + + tms570_sci_poll_last_close(tty,args); +} + +/** + * @brief Struct containing definitions of polled driver functions. + * + * Encapsulates polled driver functions. + * Use of this table is determited by not defining TMS570_USE_INTERRUPTS + */ +const rtems_termios_device_handler tms570_sci_handler_polled = { + .first_open = tms570_sci_poll_first_open, + .last_close = tms570_sci_poll_last_close, + .poll_read = tms570_sci_poll_read, + .write = tms570_sci_poll_write, + .set_attributes = tms570_sci_set_attributes, + .stop_remote_tx = NULL, + .start_remote_tx = NULL, + .mode = TERMIOS_POLLED +}; + +/** + * @brief Struct containing definitions of interrupt driven driver functions. + * + * Encapsulates interrupt driven driver functions. + * Use of this table is determited by defining TMS570_USE_INTERRUPTS + */ +const rtems_termios_device_handler tms570_sci_handler_interrupt = { + .first_open = tms570_sci_interrupt_first_open, + .last_close = tms570_sci_interrupt_last_close, + .poll_read = NULL, + .write = tms570_sci_interrupt_write, + .set_attributes = tms570_sci_set_attributes, + .stop_remote_tx = NULL, + .start_remote_tx = NULL, + .mode = TERMIOS_IRQ_DRIVEN +}; diff --git a/c/src/lib/libbsp/arm/tms570/include/bsp.h b/c/src/lib/libbsp/arm/tms570/include/bsp.h new file mode 100644 index 0000000..81bc4cd --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/bsp.h @@ -0,0 +1,59 @@ +/** + * @file bsp.h + * + * @ingroup tms570 + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_BSP_H +#define LIBBSP_ARM_TMS570_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include +#include +#include +#include + +#define BSP_OSCILATOR_CLOCK 8000000 +#define BSP_PLL_OUT_CLOCK 160000000 + +/** Define operation count for Tests */ +#define OPERATION_COUNT 4 + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct rtems_bsdnet_ifconfig; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_TMS570_BSP_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/irq.h b/c/src/lib/libbsp/arm/tms570/include/irq.h new file mode 100644 index 0000000..f35e7fe --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/irq.h @@ -0,0 +1,156 @@ +/** + * @file irq.h + * + * @ingroup tms570 + * + * @brief TMS570 interrupt definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_IRQ_H +#define LIBBSP_ARM_TMS570_IRQ_H + +#ifndef ASM +#include +#include +#include +#endif + +#define BSP_INTERRUPT_VECTOR_MIN 0U +#define TMS570_IRQ_ESM_HIGH 0 +#define TMS570_IRQ_RESERVED 1 +#define TMS570_IRQ_TIMER_0 2 +#define TMS570_IRQ_TIMER_1 3 +#define TMS570_IRQ_TIMER_2 4 +#define TMS570_IRQ_TIMER_3 5 +#define TMS570_IRQ_RTI_OVERFLOW_0 6 +#define TMS570_IRQ_RTI_OVERFLOW_1 7 +#define TMS570_IRQ_RTI_TIMEBASE 8 +#define TMS570_IRQ_GIO_HIGH 9 +#define TMS570_IRQ_HET_HIGH 10 +#define TMS570_IRQ_HET_TU_HIGH 11 +#define TMS570_IRQ_MIBSPI1_HIGH 12 +#define TMS570_IRQ_SCI_LEVEL_0 13 +#define TMS570_IRQ_ADC1_EVENT 14 +#define TMS570_IRQ_ADC1_GROUP_1 15 +#define TMS570_IRQ_CAN1_HIGH 16 +#define TMS570_IRQ_RESERVED 17 +#define TMS570_IRQ_FLEXRAY_HIGH 18 +#define TMS570_IRQ_CRC_1 19 +#define TMS570_IRQ_ESM_LOW 20 +#define TMS570_IRQ_SSI 21 +#define TMS570_IRQ_PMU 22 +#define TMS570_IRQ_GIO_LOW 23 +#define TMS570_IRQ_HET_LOW 24 +#define TMS570_IRQ_HET_TU_LOW 25 +#define TMS570_IRQ_MIBSPI1_LOW 26 +#define TMS570_IRQ_SCI_LEVEL_1 27 +#define TMS570_IRQ_ADC1_GROUP_2 28 +#define TMS570_IRQ_CAN1_LOW 29 +#define TMS570_IRQ_RESERVED +#define TMS570_IRQ_ADC1_MAG 31 +#define TMS570_IRQ_FLEXRAY_LOW 32 +#define TMS570_IRQ_DMA_FTCA 33 +#define TMS570_IRQ_DMA_LFSA 34 +#define TMS570_IRQ_CAN2_HIGH 35 +#define TMS570_IRQ_DMM_HIGH 36 +#define TMS570_IRQ_MIBSPI3_HIGH 37 +#define TMS570_IRQ_MIBSPI3_LOW 38 +#define TMS570_IRQ_DMA_HBCA 39 +#define TMS570_IRQ_DMA_BTCA 40 +#define TMS570_IRQ_DMA_BERA 41 +#define TMS570_IRQ_CAN2_LOW 42 +#define TMS570_IRQ_DMM_LOW 43 +#define TMS570_IRQ_CAN1_IF3 44 +#define TMS570_IRQ_CAN3_HIGH 45 +#define TMS570_IRQ_CAN2_IF3 46 +#define TMS570_IRQ_FPU 47 +#define TMS570_IRQ_FLEXRAY_TU 48 +#define TMS570_IRQ_SPI4_HIGH 49 +#define TMS570_IRQ_ADC2_EVENT 50 +#define TMS570_IRQ_ADC2_GROUP_1 51 +#define TMS570_IRQ_FLEXRAY_T0C 52 +#define TMS570_IRQ_MIBSPIP5_HIGH 53 +#define TMS570_IRQ_SPI4_LOW 54 +#define TMS570_IRQ_CAN3_LOW 55 +#define TMS570_IRQ_MIBSPIP5_LOW 56 +#define TMS570_IRQ_ADC2_GROUP_2 57 +#define TMS570_IRQ_FLEXRAY_TU_ERROR 58 +#define TMS570_IRQ_ADC2_MAG 59 +#define TMS570_IRQ_CAN3_IF3 60 +#define TMS570_IRQ_FSM_DONE 61 +#define TMS570_IRQ_FLEXRAY_T1C 62 +#define TMS570_IRQ_HET2_LEVEL_0 63 +#define TMS570_IRQ_SCI2_LEVEL_0 64 +#define TMS570_IRQ_HET_TU2_LEVEL_0 65 +#define TMS570_IRQ_IC2_INTERRUPT 66 +#define TMS570_IRQ_HET2_LEVEL_1 73 +#define TMS570_IRQ_SCI2_LEVEL_1 74 +#define TMS570_IRQ_HET_TU2_LEVEL_1 75 +#define TMS570_IRQ_HWA_INT_REQ_H 80 +#define TMS570_IRQ_HWA_INT_REQ_H 81 +#define TMS570_IRQ_DCC_DONE_INTERRUPT 82 +#define TMS570_IRQ_DCC2_DONE_INTERRUPT 83 +#define TMS570_IRQ_HWAG1_INT_REQ_L 88 +#define TMS570_IRQ_HWAG2_INT_REQ_L 89 +#define BSP_INTERRUPT_VECTOR_MAX 94 + +#define TMS570_IRQ_PRIORITY_VALUE_MIN 0U +#define TMS570_IRQ_PRIORITY_VALUE_MAX 0U + +#define TMS570_IRQ_PRIORITY_COUNT ( TMS570_IRQ_PRIORITY_VALUE_MAX + 1U ) +#define TMS570_IRQ_PRIORITY_HIGHEST TMS570_IRQ_PRIORITY_VALUE_MIN +#define TMS570_IRQ_PRIORITY_LOWEST TMS570_IRQ_PRIORITY_VALUE_MAX + +#ifndef ASM + +/** + * @brief Set priority of the interrupt vector. + * + * This function is here because of compability. It should set + * priority of the interrupt vector. + * @warning It does not set any priority at HW layer. It is nearly imposible to + * @warning set priority of the interrupt on TMS570 in a nice way. + * @param[in] vector vector of isr + * @param[in] priority new priority assigned to the vector + * @return Void + */ +void tms570_irq_set_priority( + rtems_vector_number vector, + unsigned priority +); + +/** + * @brief Gets priority of the interrupt vector. + * + * This function is here because of compability. It returns priority + * of the isr vector last set by tms570_irq_set_priority function. + * + * @warning It does not return any real priority of the HW layer. + * @param[in] vector vector of isr + * @retval 0 vector is invalid. + * @retval priority priority of the interrupt + */ +unsigned tms570_irq_get_priority( rtems_vector_number vector ); + +#endif /* ASM */ + +/** @} */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570-pom.h b/c/src/lib/libbsp/arm/tms570/include/tms570-pom.h new file mode 100644 index 0000000..a447711 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570-pom.h @@ -0,0 +1,101 @@ +/** + * @file tms570-pom.h + * @ingroup tms570 + * @brief Parameter Overlay Module (POM) header file + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_POM_H +#define LIBBSP_ARM_TMS570_POM_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define TMS570_POM_REGIONS 32 +#define TMS570_POM_GLBCTRL_ENABLE 0x000000a0a + +/* Specification of memory size used for field REGSIZE of tms570_pom_region_t */ +#define TMS570_POM_REGSIZE_DISABLED 0x0 +#define TMS570_POM_REGSIZE_64B 0x1 +#define TMS570_POM_REGSIZE_128B 0x2 +#define TMS570_POM_REGSIZE_256B 0x3 +#define TMS570_POM_REGSIZE_512B 0x4 +#define TMS570_POM_REGSIZE_1KB 0x5 +#define TMS570_POM_REGSIZE_2KB 0x6 +#define TMS570_POM_REGSIZE_4KB 0x7 +#define TMS570_POM_REGSIZE_8KB 0x8 +#define TMS570_POM_REGSIZE_16KB 0x9 +#define TMS570_POM_REGSIZE_32KB 0xa +#define TMS570_POM_REGSIZE_64KB 0xb +#define TMS570_POM_REGSIZE_128KB 0xc +#define TMS570_POM_REGSIZE_256KB 0xd + +#define TMS570_POM_REGADDRMASK ((1<<23)-1) + +typedef struct tms570_pom_region_t { + uint32_t PROGSTART; + uint32_t OVLSTART; + uint32_t REGSIZE; + uint32_t res0; +} tms570_pom_region_t; + +typedef struct tms570_pom_t { + uint32_t GLBCTRL; /* 000h Global Control Register */ + uint32_t REV; /* 004h Revision ID */ + uint32_t CLKCTRL; /* 008h Clock Gate Control Register */ + uint32_t FLG; /* 00Ch Status Register */ + uint32_t reserved1[0x1f0/4]; + tms570_pom_region_t REG[TMS570_POM_REGIONS]; /* 200h Program Regions */ + uint32_t reserved2[0xb00/4]; + uint32_t ITCTRL; /* F00h Integration Control Register */ + uint32_t reserved3[0x09c/4]; + uint32_t CLAIMSET; /* FA0h Claim Set Register */ + uint32_t CLAIMCLR; /* FA4h Claim Clear Register */ + uint32_t reserved4[0x008/4]; + uint32_t LOCKACCESS; /* FB0h Lock Access Register */ + uint32_t LOCKSTATUS; /* FB4h Lock Status Register */ + uint32_t AUTHSTATUS; /* FB8h Authentication Status Register */ + uint32_t reserved5[0x00c/4]; + uint32_t DEVID; /* FC8h Device ID Register */ + uint32_t DEVTYPE; /* FCCh Device Type Register */ + uint32_t PERIPHERALID4; /* FD0h Peripheral ID 4 Register */ + uint32_t PERIPHERALID5; /* FD4h Peripheral ID 5 Register */ + uint32_t PERIPHERALID6; /* FD8h Peripheral ID 6 Register */ + uint32_t PERIPHERALID7; /* FDCh Peripheral ID 7 Register */ + uint32_t PERIPHERALID0; /* FE0h Peripheral ID 0 Register */ + uint32_t PERIPHERALID1; /* FE4h Peripheral ID 1 Register */ + uint32_t PERIPHERALID2; /* FE8h Peripheral ID 2 Register */ + uint32_t PERIPHERALID3; /* FECh Peripheral ID 3 Register */ + uint32_t COMPONENTID0; /* FF0h Component ID 0 Register */ + uint32_t COMPONENTID1; /* FF4h Component ID 1 Register */ + uint32_t COMPONENTID2; /* FF8h Component ID 2 Register */ + uint32_t COMPONENTID3; /* FFCh Component ID 3 Register */ +} tms570_pom_t; + +#define TMS570_POM (*(volatile tms570_pom_t*)0xffa04000) + +int mem_dump(void *buf, unsigned long start, unsigned long len, int blen); +void tms570_pom_remap(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_POM_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570-rti.h b/c/src/lib/libbsp/arm/tms570/include/tms570-rti.h new file mode 100644 index 0000000..25c02e5 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570-rti.h @@ -0,0 +1,95 @@ +/** + * @file tms570-rti.h + * + * @ingroup tms570 + * + * @brief Real Time Interrupt module (RTI) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_RTI_H +#define LIBBSP_ARM_TMS570_RTI_H + +#ifndef ASM + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + uint32_t RTIGCTRL; /* RTIGlobalControlRegister */ + uint32_t RTITBCTRL; /* RTITimebaseControlRegister */ + uint32_t RTICAPCTRL; /* RTICaptureControlRegister */ + uint32_t RTICOMPCTRL; /* RTICompareControlRegister */ + uint32_t RTIFRC0; /* RTIFreeRunningCounter0Register */ + uint32_t RTIUC0; /* RTIUpCounter0Register */ + uint32_t RTICPUC0; /* RTICompareUpCounter0Register */ + uint32_t reserved1 [0x4/4]; + uint32_t RTICAFRC0; /* RTICaptureFreeRunningCounter0Register */ + uint32_t RTICAUC0; /* RTICaptureUpCounter0Register */ + uint32_t reserved2 [0x8/4]; + uint32_t RTIFRC1; /* RTIFreeRunningCounter1Register */ + uint32_t RTIUC1; /* RTIUpCounter1Register */ + uint32_t RTICPUC1; /* RTICompareUpCounter1Register */ + uint32_t reserved3 [0x4/4]; + uint32_t RTICAFRC1; /* RTICaptureFreeRunningCounter1Register */ + uint32_t RTICAUC1; /* RTICaptureUpCounter1Register */ + uint32_t reserved4 [0x8/4]; + uint32_t RTICOMP0; /* RTICompare0Register */ + uint32_t RTIUDCP0; /* RTIUpdateCompare0Register */ + uint32_t RTICOMP1; /* RTICompare1Register */ + uint32_t RTIUDCP1; /* RTIUpdateCompare1Register */ + uint32_t RTICOMP2; /* RTICompare2Register */ + uint32_t RTIUDCP2; /* RTIUpdateCompare2Register */ + uint32_t RTICOMP3; /* RTICompare3Register */ + uint32_t RTIUDCP3; /* RTIUpdateCompare3Register */ + uint32_t RTITBLCOMP; /* RTITimebaseLowCompareRegister */ + uint32_t RTITBHCOMP; /* RTITimebaseHighCompareRegister */ + uint32_t reserved5 [0x8/4]; + uint32_t RTISETINTENA; /* RTISetInterruptEnableRegister */ + uint32_t RTICLEARINTENA; /* RTIClearInterruptEnableRegister */ + uint32_t RTIINTFLAG; /* RTIInterruptFlagRegister */ + uint32_t reserved6 [0x4/4]; + uint32_t RTIDWDCTRL; /* DigitalWatchdogControlRegister */ + uint32_t RTIDWDPRLD; /* DigitalWatchdogPreloadRegister */ + uint32_t RTIWDSTATUS; /* WatchdogStatusRegister */ + uint32_t RTIWDKEY; /* RTIWatchdogKeyRegister */ + uint32_t RTIDWDCNTR; /* RTIDigitalWatchdogDownCounterRegister */ + uint32_t RTIWWDRXNCTRL; /* DigitalWindowedWatchdogReactionControlRegister */ + uint32_t RTIWWDSIZECTRL; /* DigitalWindowedWatchdogWindowSizeControlRegister */ + uint32_t RTIINTCLRENABLE;/* RTICompareInterruptClearEnableRegister */ + uint32_t RTICOMP0CLR; /* RTICompare0ClearRegister */ + uint32_t RTICOMP1CLR; /* RTICompare1ClearRegister */ + uint32_t RTICOMP2CLR; /* RTICompare2ClearRegister */ + uint32_t RTICOMP3CLR; /* RTICompare3ClearRegister */ +}tms570_rti_t; + +#define TMS570_RTI (*(volatile tms570_rti_t*)0xFFFFFC00) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570-sci-driver.h b/c/src/lib/libbsp/arm/tms570/include/tms570-sci-driver.h new file mode 100644 index 0000000..5f38908 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570-sci-driver.h @@ -0,0 +1,57 @@ +/** + * @file tms570-sci-driver.h + * + * @ingroup tms570 + * + * @brief Declaration of serial's driver inner structure. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef TMS570_SCI_DRIVER +#define TMS570_SCI_DRIVER + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Low-level driver specific data structure */ +typedef struct { + const char *device_name; + volatile tms570_sci_t *regs; + int tx_chars_in_hw; + rtems_vector_number irq; +} tms570_sci_context; + +extern const rtems_termios_device_handler tms570_sci_handler_polled; + +extern const rtems_termios_device_handler tms570_sci_handler_interrupt; + +extern const tms570_sci_context driver_context_table[]; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* TMS570_SCI_DRIVER */ diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570-sci.h b/c/src/lib/libbsp/arm/tms570/include/tms570-sci.h new file mode 100644 index 0000000..6ed68e2 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570-sci.h @@ -0,0 +1,76 @@ +/** + * @file tms570-sci.h + * + * @ingroup tms570 + * + * @brief Serial Communication Interface (SCI) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_SCI_H +#define LIBBSP_ARM_TMS570_SCI_H + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + uint32_t SCIGCR0; /*SCIGlobalControlRegister0*/ + uint32_t SCIGCR1; /*SCIGlobalControlRegister1*/ + uint32_t reserved1 [0x4/4]; + uint32_t SCISETINT; /*SCISetInterruptRegister*/ + uint32_t SCICLEARINT; /*SCIClearInterruptRegister*/ + uint32_t SCISETINTLVL; /*SCISetInterruptLevelRegister*/ + uint32_t SCICLEARINTLVL; /*SCIClearInterruptLevelRegister*/ + uint32_t SCIFLR; /*SCIFlagsRegister*/ + uint32_t SCIINTVECT0; /*SCIInterruptVectorOffset0*/ + uint32_t SCIINTVECT1; /*SCIInterruptVectorOffset1*/ + uint32_t SCIFORMAT; /*SCIFormatControlRegister*/ + uint32_t BRS; /*BaudRateSelectionRegister*/ + uint32_t SCIED; /*ReceiverEmulationDataBuffer*/ + uint32_t SCIRD; /*ReceiverDataBuffer*/ + uint32_t SCITD; /*TransmitDataBuffer*/ + uint32_t SCIPIO0; /*SCIPinI/OControlRegister0*/ + uint32_t SCIPIO1; /*SCIPinI/OControlRegister1*/ + uint32_t SCIPIO2; /*SCIPinI/OControlRegister2*/ + uint32_t SCIPIO3; /*SCIPinI/OControlRegister3*/ + uint32_t SCIPIO4; /*SCIPinI/OControlRegister4*/ + uint32_t SCIPIO5; /*SCIPinI/OControlRegister5*/ + uint32_t SCIPIO6; /*SCIPinI/OControlRegister6*/ + uint32_t SCIPIO7; /*SCIPinI/OControlRegister7*/ + uint32_t SCIPIO8; /*SCIPinI/OControlRegister8*/ + uint32_t reserved2 [0x30/4]; + uint32_t IODFTCTRL; /*Input/OutputErrorEnableRegister*/ +}tms570_sci_t; + +#define TMS570_SCI (*(volatile tms570_sci_t*)0xFFF7E400U) +#define TMS570_SCI2 (*(volatile tms570_sci_t*)0xFFF7E500U) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570-vim.h b/c/src/lib/libbsp/arm/tms570/include/tms570-vim.h new file mode 100644 index 0000000..136af53 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570-vim.h @@ -0,0 +1,75 @@ +/** + * @file tms570-vim.h + * + * @ingroup tms570 + * + * @brief Vectored Interrupt Module (VIM) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_VIM_H +#define LIBBSP_ARM_TMS570_VIM_H + +#ifndef ASM +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct{ + uint32_t PARFLG; /* InterruptVectorTableParityFlagRegister */ + uint32_t PARCTL; /* InterruptVectorTableParityControlRegister */ + uint32_t ADDERR; /* AddressParityErrorRegister */ + uint32_t FBPARERR; /* Fall-BackAddressParityErrorRegister */ + uint32_t reserved1 [0x4/4]; + uint32_t IRQINDEX; /* IRQIndexOffsetVectorRegister */ + uint32_t FIQINDEX; /* FIQIndexOffsetVectorRegister */ + uint32_t reserved2 [0x8/4]; + uint32_t FIRQPR[3]; /* FIQ/IRQProgramControlRegister0 */ + uint32_t reserved3 [0x4/4]; + uint32_t INTREQ[3]; /* PendingInterruptReadLocationRegister0 */ + uint32_t reserved4 [0x4/4]; + uint32_t REQENASET[3]; /* InterruptEnableSetRegister0 */ + uint32_t reserved5 [0x4/4]; + uint32_t REQENACLR[3]; /* InterruptEnableClearRegister0 */ + uint32_t reserved6 [0x4/4]; + uint32_t WAKEENASET[3]; /* Wake-upEnableSetRegister0 */ + uint32_t reserved7 [0x4/4]; + uint32_t WAKEENACLR[3]; /* Wake-upEnableClearRegister0 */ + uint32_t reserved8 [0x4/4]; + uint32_t IRQVECREG; /* IRQInterruptVectorRegister */ + uint32_t FIQVECREG; /* FIQInterruptVectorRegister */ + uint32_t CAPEVT; /* CaptureEventRegister */ + uint32_t reserved9 [0x4/4]; + uint32_t CHANCTRL [0x5c/4]; /* VIM Interrupt Control Register (PARSER ERROR) */ +}tms570_vim_t; + +#define TMS570_VIM (*(volatile tms570_vim_t*)0xFFFFFDEC) + +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570.h b/c/src/lib/libbsp/arm/tms570/include/tms570.h new file mode 100644 index 0000000..2023a29 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570.h @@ -0,0 +1,28 @@ +/** + * @file tms570.h + * + * @ingroup tms570 + * + * @brief Specific register definitions according to tms570 family boards. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_H +#define LIBBSP_ARM_TMS570_H + +#endif /* LIBBSP_ARM_TMS570_H */ diff --git a/c/src/lib/libbsp/arm/tms570/irq/irq.c b/c/src/lib/libbsp/arm/tms570/irq/irq.c new file mode 100644 index 0000000..2e6e3db --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/irq/irq.c @@ -0,0 +1,207 @@ +/** + * @file irq.c + * + * @ingroup tms570 + * + * @brief TMS570 interrupt support functions definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include +#include + +/** + * @brief Check if isr vector is valid + * + * Check if isr vector is valid by using BSP_INTERRUPT_VECTOR_MAX and + * BSP_INTERRUPT_VECTOR_MIN defined in irq.h + * + * @param[in] vector interrupt vector to be checked. + * @retval TRUE vector is valid. + * @retval FALSE vector is invalid + */ +static inline bool tms570_irq_is_valid( + rtems_vector_number vector +) +{ + return (vector <= BSP_INTERRUPT_VECTOR_MAX) && + (vector > BSP_INTERRUPT_VECTOR_MIN); +} + +unsigned int priorityTable[BSP_INTERRUPT_VECTOR_MAX+1]; + +/** + * @brief Set priority of the interrupt vector. + * + * This function is here because of compability. It should set + * priority of the interrupt vector. + * @warning It does not set any priority at HW layer. It is nearly imposible to + * @warning set priority of the interrupt on TMS570 in a nice way. + * @param[in] vector vector of isr + * @param[in] priority new priority assigned to the vector + * @return Void + */ +void tms570_irq_set_priority( + rtems_vector_number vector, + unsigned priority +) +{ + if ( tms570_irq_is_valid(vector) ) { + priorityTable[vector] = priority; + } +} + +/** + * @brief Gets priority of the interrupt vector. + * + * This function is here because of compability. It returns priority + * of the isr vector last set by tms570_irq_set_priority function. + * + * @warning It does not return any real priority of the HW layer. + * @param[in] vector vector of isr + * @retval 0 vector is invalid. + * @retval priority priority of the interrupt + */ +unsigned tms570_irq_get_priority( + rtems_vector_number vector +) +{ + if ( tms570_irq_is_valid(vector) ) { + return priorityTable[vector]; + } + return 0; +} + +/** + * @brief Interrupt dispatch + * + * Called by OS to determine which interrupt occured. + * Function passes control to interrupt handler. + * + * @return Void + */ +void bsp_interrupt_dispatch(void) +{ + rtems_vector_number vector = TMS570_VIM.IRQINDEX-1; + + bsp_interrupt_handler_dispatch(vector); +} + +/** + * @brief enables interrupt vector in the HW + * + * Enables HW interrupt for specified vector + * + * @param[in] vector vector of the isr which needs to be enabled. + * @retval RTEMS_INVALID_ID vector is invalid. + * @retval RTEMS_SUCCESSFUL interrupt source enabled. + */ +rtems_status_code bsp_interrupt_vector_enable( + rtems_vector_number vector +) +{ + if( !tms570_irq_is_valid(vector) ) { + return RTEMS_INVALID_ID; + } + + TMS570_VIM.REQENASET[vector >> 5] = 1 << (vector & 0x1f); + + return RTEMS_SUCCESSFUL; +} + +/** + * @brief disables interrupt vector in the HW + * + * Disables HW interrupt for specified vector + * + * @param[in] vector vector of the isr which needs to be disabled. + * @retval RTEMS_INVALID_ID vector is invalid. + * @retval RTEMS_SUCCESSFUL interrupt source disabled. + */ +rtems_status_code bsp_interrupt_vector_disable( + rtems_vector_number vector +) +{ + if( !tms570_irq_is_valid(vector) ) { + return RTEMS_INVALID_ID; + } + + TMS570_VIM.REQENACLR[vector >> 5] = 1 << (vector & 0x1f); + + return RTEMS_SUCCESSFUL; +} + +/** + * @brief Init function of interrupt module + * + * Resets vectored interrupt interface to default state. + * Disables all interrupts. + * Set all sources as IRQ (not FIR). + * + * @retval RTEMS_SUCCESSFUL All is set + */ +rtems_status_code bsp_interrupt_facility_initialize(void) +{ + void (**vim_vec)(void) = (void (**)(void)) 0xFFF82000; + unsigned int value = 0x00010203; + unsigned int i = 0; + uint32_t sctlr; + + /* Disable interrupts */ + for ( i = 0; i < 3; i++ ) { + TMS570_VIM.REQENACLR[i] = 0xffffffff; + } + /* Map default events on interrupt vectors */ + for ( i = 0; i < 24; i += 1, value += 0x04040404) { + TMS570_VIM.CHANCTRL[i] = value; + } + /* Set all vectors as IRQ (not FIR) */ + TMS570_VIM.FIRQPR[0] = 3; + TMS570_VIM.FIRQPR[1] = 0; + TMS570_VIM.FIRQPR[2] = 0; + + /* + _CPU_ISR_install_vector( + ARM_EXCEPTION_IRQ, + _ARMV4_Exception_interrupt, + NULL + ); + + Call to setup of interrupt entry in CPU level exception vectors table + is not used (necessary/possible) because the table is provided + by c/src/lib/libbsp/arm/shared/start/start.S and POM overlay + solution remaps that to address zero. + */ + + for ( i = 0; i <= 94; ++i ) { + vim_vec[i] = _ARMV4_Exception_interrupt; + } + /* Clear bit VE in SCTLR register to not use VIM IRQ exception bypass*/ + asm volatile ("mrc p15, 0, %0, c1, c0, 0\n": "=r" (sctlr)); + /* + * Disable bypass of CPU level exception table for interrupt entry which + * can be provided by VIM hardware + */ + sctlr &= ~(1 << 24); + asm volatile ("mcr p15, 0, %0, c1, c0, 0\n": : "r" (sctlr)); + + return RTEMS_SUCCESSFUL; +} diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg new file mode 100644 index 0000000..6f722bc --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg @@ -0,0 +1,19 @@ +# +# tms570ls3137 mbed RTEMS Test Database. +# +# Format is one line per test that is _NOT_ built. +# + +flashdisk01 +utf8proc01 +spstkalloc02 +fsdosfsname01 +jffs2_fserror +jffs2_fslink +jffs2_fspatheval +jffs2_fspermission +jffs2_fsrdwr +jffs2_fssymlink +jffs2_fstime +pppd +mghttpd01 diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg new file mode 100644 index 0000000..eb4a65f --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg @@ -0,0 +1,20 @@ +# +# Config file for TMS570LS3137 board. +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = arm + +CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian + +CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +BINEXT?=.bin + +# This defines the operations performed on the linked executable. +# is currently required. +define bsp-post-link + $(OBJCOPY) -O binary --strip-all \ + $(basename $@)$(EXEEXT) $(basename $@)$(BINEXT) + $(SIZE) $(basename $@)$(EXEEXT) +endef diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg new file mode 100644 index 0000000..eb4a65f --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg @@ -0,0 +1,20 @@ +# +# Config file for TMS570LS3137 board. +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = arm + +CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian + +CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +BINEXT?=.bin + +# This defines the operations performed on the linked executable. +# is currently required. +define bsp-post-link + $(OBJCOPY) -O binary --strip-all \ + $(basename $@)$(EXEEXT) $(basename $@)$(BINEXT) + $(SIZE) $(basename $@)$(EXEEXT) +endef diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg new file mode 100644 index 0000000..eb4a65f --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg @@ -0,0 +1,20 @@ +# +# Config file for TMS570LS3137 board. +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = arm + +CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian + +CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +BINEXT?=.bin + +# This defines the operations performed on the linked executable. +# is currently required. +define bsp-post-link + $(OBJCOPY) -O binary --strip-all \ + $(basename $@)$(EXEEXT) $(basename $@)$(BINEXT) + $(SIZE) $(basename $@)$(EXEEXT) +endef diff --git a/c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c b/c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c new file mode 100644 index 0000000..6514368 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c @@ -0,0 +1,53 @@ +/** + * @file tms570-pom.c + * + * @ingroup tms570 + * + * @brief TMS570 Parameter Overlay Module functions definitions. + */ + + /* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include + +/** + * @brief remaps vector table + * + * transfer the rtems start vector table to address 0x0 + * + * @retval Void + */ +void tms570_pom_remap(void) +{ + int i; + uint32_t vec_overlay_start = 0x08000000; + + memcpy((void*)vec_overlay_start, bsp_start_vector_table_begin, 64); + + TMS570_POM.GLBCTRL = 0; + + for ( i = 0; i < TMS570_POM_REGIONS; ++i ) { + TMS570_POM.REG[i].REGSIZE = TMS570_POM_REGSIZE_DISABLED; + } + + TMS570_POM.REG[0].PROGSTART = 0x0 & TMS570_POM_REGADDRMASK; + TMS570_POM.REG[0].OVLSTART = vec_overlay_start & TMS570_POM_REGADDRMASK; + TMS570_POM.REG[0].REGSIZE = TMS570_POM_REGSIZE_64B; + + TMS570_POM.GLBCTRL = TMS570_POM_GLBCTRL_ENABLE | + (vec_overlay_start & ~TMS570_POM_REGADDRMASK); +} diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am b/c/src/lib/libbsp/arm/tms570/preinstall.am new file mode 100644 index 0000000..81dbad1 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/preinstall.am @@ -0,0 +1,123 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES = $(TMPINSTALL_FILES) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) + +$(PROJECT_LIB)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_LIB) + @: > $(PROJECT_LIB)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) + +$(PROJECT_INCLUDE)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE) + @: > $(PROJECT_INCLUDE)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) + +$(PROJECT_INCLUDE)/bsp/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp + @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) + +$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs +PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs + +$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h + +$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h + +$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h + +$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h + +$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h + +$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h + +$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h + +$(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h + +$(PROJECT_INCLUDE)/bsp/uart-output-char.h: ../../shared/include/uart-output-char.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart-output-char.h + +$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h + +$(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h + +$(PROJECT_INCLUDE)/bsp/tms570.h: include/tms570.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570.h + +$(PROJECT_INCLUDE)/bsp/tms570-sci.h: include/tms570-sci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-sci.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-sci.h + +$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h + +$(PROJECT_INCLUDE)/bsp/tms570-rti.h: include/tms570-rti.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-rti.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-rti.h + +$(PROJECT_INCLUDE)/bsp/tms570-vim.h: include/tms570-vim.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-vim.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-vim.h + +$(PROJECT_INCLUDE)/bsp/tms570-pom.h: include/tms570-pom.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-pom.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-pom.h + +$(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h: include/tms570-sci-driver.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h + +$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h + +$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) +TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) + +$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds + diff --git a/c/src/lib/libbsp/arm/tms570/startup/bspreset.c b/c/src/lib/libbsp/arm/tms570/startup/bspreset.c new file mode 100644 index 0000000..d47920c --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/bspreset.c @@ -0,0 +1,36 @@ +/** + * @file bspreset.c + * + * @ingroup tms570 + * + * @brief Reset code. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#include +#include +#include + +BSP_START_TEXT_SECTION __attribute__( ( flatten ) ) void bsp_reset( void ) +{ + while ( true ) { + /* Do nothing */ + } +} diff --git a/c/src/lib/libbsp/arm/tms570/startup/bspstart.c b/c/src/lib/libbsp/arm/tms570/startup/bspstart.c new file mode 100644 index 0000000..31ad1e7 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/bspstart.c @@ -0,0 +1,41 @@ +/** + * @file bspstart.c + * + * @ingroup tms570 + * + * @brief Startup code. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include +#include + +void bsp_start( void ) +{ + /* set the cpu mode to supervisor and big endian */ + arm_cpu_mode = 0x213; + + tms570_pom_remap(); + + /* Interrupts */ + bsp_interrupt_initialize(); + +} diff --git a/c/src/lib/libbsp/arm/tms570/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/tms570/startup/bspstarthooks.c new file mode 100644 index 0000000..a9e189b --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/bspstarthooks.c @@ -0,0 +1,41 @@ +/** + * @file bspstarthooks.c + * + * @ingroup tms570 + * + * @brief First configurations and initializations to the correct + * functionality of the board. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include + +BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) +{ + ; +} + +BSP_START_TEXT_SECTION void bsp_start_hook_1( void ) +{ + bsp_start_copy_sections(); + bsp_start_clear_bss(); + + /* At this point we can use objects outside the .start section */ +} diff --git a/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk new file mode 100644 index 0000000..e02dcd6 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk @@ -0,0 +1,27 @@ + +MEMORY { + ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M + RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 256k + RAM_EXT (AIWX) : ORIGIN = 0x80000000, LENGTH = 8M +} + +REGION_ALIAS ("REGION_START", ROM_INT); +REGION_ALIAS ("REGION_VECTOR", RAM_INT); +REGION_ALIAS ("REGION_TEXT", ROM_INT); +REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT); +REGION_ALIAS ("REGION_RODATA", ROM_INT); +REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_DATA", RAM_INT); +REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_INT); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_BSS", RAM_INT); +REGION_ALIAS ("REGION_WORK", RAM_INT); +REGION_ALIAS ("REGION_STACK", RAM_INT); + +bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 1024; +bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align); + +INCLUDE linkcmds.armv4 diff --git a/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_intram b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_intram new file mode 100644 index 0000000..19bb7b2 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_intram @@ -0,0 +1,28 @@ + +MEMORY { + ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M + RAM_INT_VEC : ORIGIN = 0x08000000, LENGTH = 1k + RAM_INT (AIWX) : ORIGIN = 0x08000400, LENGTH = 256k - 1k + RAM_EXT (AIW) : ORIGIN = 0x80000000, LENGTH = 8M +} + +REGION_ALIAS ("REGION_START", RAM_INT); +REGION_ALIAS ("REGION_VECTOR", RAM_INT); +REGION_ALIAS ("REGION_TEXT", RAM_INT); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM_INT); +REGION_ALIAS ("REGION_RODATA", RAM_INT); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM_INT); +REGION_ALIAS ("REGION_DATA", RAM_INT); +REGION_ALIAS ("REGION_DATA_LOAD", RAM_INT); +REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_INT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_INT); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_INT); +REGION_ALIAS ("REGION_BSS", RAM_INT); +REGION_ALIAS ("REGION_WORK", RAM_INT); +REGION_ALIAS ("REGION_STACK", RAM_INT); + +bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 1024; +bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align); + +INCLUDE linkcmds.armv4 diff --git a/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_sdram b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_sdram new file mode 100644 index 0000000..110179f --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_sdram @@ -0,0 +1,27 @@ + +MEMORY { + ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M + RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 256k + RAM_EXT (AIWX) : ORIGIN = 0x80000000, LENGTH = 8M +} + +REGION_ALIAS ("REGION_START", RAM_EXT); +REGION_ALIAS ("REGION_VECTOR", RAM_EXT); +REGION_ALIAS ("REGION_TEXT", RAM_EXT); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_RODATA", RAM_EXT); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_DATA", RAM_EXT); +REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_FAST_TEXT", RAM_EXT); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_EXT); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_BSS", RAM_EXT); +REGION_ALIAS ("REGION_WORK", RAM_EXT); +REGION_ALIAS ("REGION_STACK", RAM_EXT); + +bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 1024; +bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align); + +INCLUDE linkcmds.armv4 From joel at rtems.org Wed Aug 20 19:44:36 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 20 Aug 2014 14:44:36 -0500 Subject: [rtems commit] libbsp/arm/acinclude.m4: Regenerate for tms570 Message-ID: <20140820194436.789BB700650@git.rtems.org> Module: rtems Branch: master Commit: 2ed97d94dad5a4370584090853b3d4bc6326ba2c Changeset: http://git.rtems.org/rtems/commit/?id=2ed97d94dad5a4370584090853b3d4bc6326ba2c Author: Joel Sherrill Date: Wed Aug 20 14:53:18 2014 -0500 libbsp/arm/acinclude.m4: Regenerate for tms570 --- c/src/lib/libbsp/arm/acinclude.m4 | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/arm/acinclude.m4 b/c/src/lib/libbsp/arm/acinclude.m4 index 9192267..91c0fff 100644 --- a/c/src/lib/libbsp/arm/acinclude.m4 +++ b/c/src/lib/libbsp/arm/acinclude.m4 @@ -38,6 +38,8 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR], AC_CONFIG_SUBDIRS([smdk2410]);; stm32f4 ) AC_CONFIG_SUBDIRS([stm32f4]);; + tms570 ) + AC_CONFIG_SUBDIRS([tms570]);; xilinx-zynq ) AC_CONFIG_SUBDIRS([xilinx-zynq]);; *) From joel at rtems.org Wed Aug 20 19:44:36 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 20 Aug 2014 14:44:36 -0500 Subject: [rtems commit] Add new (first) OpenRISC BSP called or1ksim. Message-ID: <20140820194436.677E97006E4@git.rtems.org> Module: rtems Branch: master Commit: fd5701587f7961259253e66e4dd8fa8c44e8ee91 Changeset: http://git.rtems.org/rtems/commit/?id=fd5701587f7961259253e66e4dd8fa8c44e8ee91 Author: Hesham ALMatary Date: Wed Aug 20 12:23:20 2014 -0500 Add new (first) OpenRISC BSP called or1ksim. This BSP is intended to run on or1ksim (the main OpenRISC emulator). Fixed version according to Joel comments from the mailing list. --- c/src/aclocal/rtems-cpu-subdirs.m4 | 1 + c/src/lib/libbsp/or1k/Makefile.am | 10 + c/src/lib/libbsp/or1k/acinclude.m4 | 10 + c/src/lib/libbsp/or1k/configure.ac | 19 ++ c/src/lib/libbsp/or1k/or1ksim/Makefile.am | 109 +++++++ c/src/lib/libbsp/or1k/or1ksim/README | 17 + c/src/lib/libbsp/or1k/or1ksim/bsp_specs | 11 + c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c | 104 +++++++ c/src/lib/libbsp/or1k/or1ksim/configure.ac | 30 ++ .../libbsp/or1k/or1ksim/console/console-config.c | 58 ++++ c/src/lib/libbsp/or1k/or1ksim/console/uart.c | 144 +++++++++ c/src/lib/libbsp/or1k/or1ksim/include/bsp.h | 47 +++ c/src/lib/libbsp/or1k/or1ksim/include/irq.h | 45 +++ c/src/lib/libbsp/or1k/or1ksim/include/or1ksim.h | 118 ++++++++ c/src/lib/libbsp/or1k/or1ksim/include/uart.h | 42 +++ c/src/lib/libbsp/or1k/or1ksim/irq/irq.c | 42 +++ .../or1k/or1ksim/make/custom/or1k_or1ksim.cfg | 7 + c/src/lib/libbsp/or1k/or1ksim/preinstall.am | 114 +++++++ c/src/lib/libbsp/or1k/or1ksim/start/start.S | 182 ++++++++++++ c/src/lib/libbsp/or1k/or1ksim/startup/linkcmds | 41 +++ c/src/lib/libbsp/or1k/or1ksim/timer/timer.c | 64 ++++ c/src/lib/libbsp/or1k/preinstall.am | 6 + .../libbsp/or1k/shared/include/linker-symbols.h | 79 +++++ c/src/lib/libbsp/or1k/shared/startup/linkcmds.base | 310 ++++++++++++++++++++ 24 files changed, 1610 insertions(+), 0 deletions(-) diff --git a/c/src/aclocal/rtems-cpu-subdirs.m4 b/c/src/aclocal/rtems-cpu-subdirs.m4 index c5a4a19..9593d34 100644 --- a/c/src/aclocal/rtems-cpu-subdirs.m4 +++ b/c/src/aclocal/rtems-cpu-subdirs.m4 @@ -23,6 +23,7 @@ _RTEMS_CPU_SUBDIR([mips],[$1]);; _RTEMS_CPU_SUBDIR([moxie],[$1]);; _RTEMS_CPU_SUBDIR([nios2],[$1]);; _RTEMS_CPU_SUBDIR([no_cpu],[$1]);; +_RTEMS_CPU_SUBDIR([or1k],[$1]);; _RTEMS_CPU_SUBDIR([powerpc],[$1]);; _RTEMS_CPU_SUBDIR([sh],[$1]);; _RTEMS_CPU_SUBDIR([sparc],[$1]);; diff --git a/c/src/lib/libbsp/or1k/Makefile.am b/c/src/lib/libbsp/or1k/Makefile.am new file mode 100644 index 0000000..0ce20e6 --- /dev/null +++ b/c/src/lib/libbsp/or1k/Makefile.am @@ -0,0 +1,10 @@ +ACLOCAL_AMFLAGS = -I ../../../aclocal + +## Descend into the @RTEMS_BSP_FAMILY@ directory +## Currently, the shared directory is not explicitly +## added but it is present in the source tree. +SUBDIRS = @RTEMS_BSP_FAMILY@ + +include $(srcdir)/preinstall.am +include $(top_srcdir)/../../../automake/subdirs.am +include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libbsp/or1k/acinclude.m4 b/c/src/lib/libbsp/or1k/acinclude.m4 new file mode 100644 index 0000000..c593670 --- /dev/null +++ b/c/src/lib/libbsp/or1k/acinclude.m4 @@ -0,0 +1,10 @@ +# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY) +AC_DEFUN([RTEMS_CHECK_BSPDIR], +[ + case "$1" in + or1ksim ) + AC_CONFIG_SUBDIRS([or1ksim]);; + *) + AC_MSG_ERROR([Invalid BSP]);; + esac +]) diff --git a/c/src/lib/libbsp/or1k/configure.ac b/c/src/lib/libbsp/or1k/configure.ac new file mode 100644 index 0000000..96bba16 --- /dev/null +++ b/c/src/lib/libbsp/or1k/configure.ac @@ -0,0 +1,19 @@ +# Process this file with autoconf to produce a configure script. + +AC_PREREQ([2.69]) +AC_INIT([rtems-c-src-lib-libbsp-or1k],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla]) +AC_CONFIG_SRCDIR([or1ksim]) +RTEMS_TOP(../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define foreign 1.12.2]) +AM_MAINTAINER_MODE + +RTEMS_ENV_RTEMSBSP +RTEMS_PROJECT_ROOT + +RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY]) + +# Explicitly list all Makefiles here +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am new file mode 100644 index 0000000..d5eb10c --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am @@ -0,0 +1,109 @@ +# +# @file +# +# @brief Makefile of LibBSP for the or1ksim BSP. +# + +ACLOCAL_AMFLAGS = -I ../../../../aclocal + +include $(top_srcdir)/../../../../automake/compile.am + +include_bspdir = $(includedir)/bsp +#include_libcpudir = $(includedir)/libcpu + +dist_project_lib_DATA = bsp_specs + +############################################################################### +# Header # +############################################################################### + +include_bsp_HEADERS = +include_HEADERS = include/bsp.h + +nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h + +include_bsp_HEADERS += ../shared/include/linker-symbols.h +include_bsp_HEADERS += ../../../libbsp/shared/include/mm.h +include_bsp_HEADERS += ../../shared/include/utility.h +include_bsp_HEADERS += ../../shared/include/irq-generic.h +include_bsp_HEADERS += ../../shared/include/irq-info.h +include_bsp_HEADERS += ../../shared/include/stackalloc.h +include_bsp_HEADERS += ../../shared/include/uart-output-char.h +include_bsp_HEADERS += ../../shared/tod.h +include_bsp_HEADERS += ../../shared/include/tm27.h +include_bsp_HEADERS += include/irq.h +include_bsp_HEADERS += include/uart.h +include_bsp_HEADERS += include/or1ksim.h + +nodist_include_HEADERS = ../../shared/include/coverhd.h \ + include/bspopts.h + +############################################################################### +# Data # +############################################################################### + +noinst_LIBRARIES = libbspstart.a + +libbspstart_a_SOURCES = start/start.S + +project_lib_DATA = start.$(OBJEXT) + +project_lib_DATA += startup/linkcmds +project_lib_DATA += ../shared/startup/linkcmds.base + +############################################################################### +# LibBSP # +############################################################################### + +noinst_LIBRARIES += libbsp.a + +libbsp_a_SOURCES = +libbsp_a_CPPFLAGS = +libbsp_a_LIBADD = + +# Startup +libbsp_a_SOURCES += ../../shared/bspstart.c +libbsp_a_SOURCES += ../../shared/bspreset.c + +# Shared +libbsp_a_SOURCES += ../../shared/bootcard.c +libbsp_a_SOURCES += ../../shared/bspclean.c +libbsp_a_SOURCES += ../../shared/bspgetworkarea.c +libbsp_a_SOURCES += ../../shared/bsplibc.c +libbsp_a_SOURCES += ../../shared/bsppost.c +libbsp_a_SOURCES += ../../shared/bsppredriverhook.c +libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c +libbsp_a_SOURCES += ../../shared/cpucounterread.c +libbsp_a_SOURCES += ../../shared/cpucounterdiff.c +libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c +libbsp_a_SOURCES += ../../shared/sbrk.c +libbsp_a_SOURCES += ../../shared/src/stackalloc.c + +# Console +libbsp_a_SOURCES += ../../shared/console.c +libbsp_a_SOURCES += ../../shared/console_control.c +libbsp_a_SOURCES += ../../shared/console_read.c +libbsp_a_SOURCES += ../../shared/console_select.c +libbsp_a_SOURCES += ../../shared/console_write.c +libbsp_a_SOURCES += console/console-config.c +libbsp_a_SOURCES += console/uart.c + +# Timer +libbsp_a_SOURCES += timer/timer.c + +# clock +libbsp_a_SOURCES += clock/clockdrv.c ../../../shared/clockdrv_shell.h + +# IRQ +libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c +libbsp_a_SOURCES += ../../shared/src/irq-generic.c +libbsp_a_SOURCES += ../../shared/src/irq-info.c +libbsp_a_SOURCES += irq/irq.c +############################################################################### +# Special Rules # +############################################################################### + +DISTCLEANFILES = include/bspopts.h + +include $(srcdir)/preinstall.am +include $(top_srcdir)/../../../../automake/local.am diff --git a/c/src/lib/libbsp/or1k/or1ksim/README b/c/src/lib/libbsp/or1k/or1ksim/README new file mode 100644 index 0000000..43b4703 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/README @@ -0,0 +1,17 @@ +This BSP should run only on or1ksim: the main simulator for or1k architecture. +or1ksim should be used for testing purposes. + +svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/or1ksim +cd or1ksim +mkdir builddir_or1ksim +cd builddir_or1ksim +../configure --target=or32-elf --prefix=/opt/or1ksim +make all +make install +export PATH=/opt/or1ksim/bin:$PATH + +Configuration file "sim.cfg" should be provided for complex board +configurations at the current directory (which you run or1ksim from) or at +~/.or1k/ + +sim -f sim.cfg hello.exe diff --git a/c/src/lib/libbsp/or1k/or1ksim/bsp_specs b/c/src/lib/libbsp/or1k/or1ksim/bsp_specs new file mode 100644 index 0000000..0fcd2dc --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/bsp_specs @@ -0,0 +1,11 @@ +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*startfile: +%{!qrtems: %(old_startfile)} %{!nostdlib: %{qrtems: \ +%{!qrtems_debug: start.o%s} \ +%{qrtems_debug: start_g.o%s}}} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e _start} diff --git a/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c b/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c new file mode 100644 index 0000000..3877fe0 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c @@ -0,0 +1,104 @@ +/** + * @file + * + * @ingroup bsp_clock + * + * @brief or1ksim clock support. + */ + +/* + * or1ksim Clock driver + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#include +#include +#include +#include +#include +#include + +/* The number of clock cycles before generating a tick timer interrupt. */ +#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT 0xFFED9 +#define OR1KSIM_CLOCK_CYCLE_TIME_NANOSECONDS 10 + +/* This prototype is added here to Avoid warnings */ +void Clock_isr(void *arg); + +static void or1ksim_clock_at_tick(void) +{ + uint32_t TTMR; + + /* For TTMR register, + * The least significant 28 bits are the number of clock cycles + * before generating a tick timer interrupt. While the most + * significant 4 bits are used for mode configuration, tick timer + * interrupt enable and pending interrupts status. + */ + TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE | + (TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT & CPU_OR1K_SPR_TTMR_TP_MASK) + ) & ~(CPU_OR1K_SPR_TTMR_IP); + + _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR); + _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0); +} + +static void or1ksim_clock_handler_install(proc_ptr new_isr, proc_ptr old_isr) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + old_isr = NULL; + _CPU_ISR_install_vector(OR1K_EXCEPTION_TICK_TIMER, + new_isr, + old_isr); + + if (sc != RTEMS_SUCCESSFUL) { + rtems_fatal_error_occurred(0xdeadbeef); + } +} + +static void or1ksim_clock_initialize(void) +{ + uint32_t sr; + + or1ksim_clock_at_tick(); + + /* Enable tick timer */ + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + sr |= CPU_OR1K_SPR_SR_TEE; + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); +} + + static void or1ksim_clock_cleanup(void) +{ +} + +/* + * Return the nanoseconds since last tick + */ +static uint32_t or1ksim_clock_nanoseconds_since_last_tick(void) +{ + return + TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT * OR1KSIM_CLOCK_CYCLE_TIME_NANOSECONDS; +} + +#define Clock_driver_support_at_tick() or1ksim_clock_at_tick() + +#define Clock_driver_support_initialize_hardware() or1ksim_clock_initialize() + +#define Clock_driver_support_install_isr(isr, old_isr) \ + do { \ + or1ksim_clock_handler_install(isr, old_isr); \ + old_isr = NULL; \ + } while (0) + +#define Clock_driver_support_shutdown_hardware() or1ksim_clock_cleanup() + +#define Clock_driver_nanoseconds_since_last_tick \ + or1ksim_clock_nanoseconds_since_last_tick + +#include "../../../shared/clockdrv_shell.h" diff --git a/c/src/lib/libbsp/or1k/or1ksim/configure.ac b/c/src/lib/libbsp/or1k/or1ksim/configure.ac new file mode 100644 index 0000000..8aff7e3 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/configure.ac @@ -0,0 +1,30 @@ +# +# @file +# +# @brief Configure script of LibBSP for or1ksim BSP. +# + +AC_PREREQ(2.69) +AC_INIT([rtems-c-src-lib-libbsp-or1k-or1ksim],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla]) +AC_CONFIG_SRCDIR([bsp_specs]) +RTEMS_TOP(../../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) +RTEMS_BSP_CONFIGURE + +RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) +RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) + +RTEMS_BSPOPTS_SET([BSP_OR1K_OR1KSIM_PERIPHCLK],[*],[100000000U]) +RTEMS_BSPOPTS_HELP([BSP_OR1K_OR1KSIM_PERIPHCLK],[or1ksim PERIPHCLK clock frequency in Hz]) + +RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm]) +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +RTEMS_BSP_CLEANUP_OPTIONS(0, 0) +RTEMS_BSP_LINKCMDS + +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/or1k/or1ksim/console/console-config.c b/c/src/lib/libbsp/or1k/or1ksim/console/console-config.c new file mode 100644 index 0000000..9853f20 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/console/console-config.c @@ -0,0 +1,58 @@ +/** + * @file + * + * @ingroup or1ksim_uart + * + * @brief Console Configuration. + */ + +/* + * Copyright (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#include + +#include + +#include +#include +#include + +console_tbl Console_Configuration_Ports [] = { + { + .sDeviceName = "/dev/ttyS0", + .deviceType = SERIAL_CUSTOM, + .pDeviceFns = &or1ksim_uart_fns, + .deviceProbe = NULL, + .pDeviceFlow = NULL, + .ulCtrlPort1 = OR1KSIM_BSP_UART_BASE, + .ulCtrlPort2 = 0, + .ulClock = OR1KSIM_UART_DEFAULT_BAUD, + .ulIntVector = OR1KSIM_BSP_UART_IRQ + } +}; + +#define PORT_COUNT \ + (sizeof(Console_Configuration_Ports) \ + / sizeof(Console_Configuration_Ports [0])) + +unsigned long Console_Configuration_Count = PORT_COUNT; + +static void output_char(char c) +{ + const console_fns *con = + Console_Configuration_Ports [Console_Port_Minor].pDeviceFns; + + if (c == '\n') { + con->deviceWritePolled((int) Console_Port_Minor, '\r'); + } + con->deviceWritePolled((int) Console_Port_Minor, c); +} + +BSP_output_char_function_type BSP_output_char = output_char; + +BSP_polling_getchar_function_type BSP_poll_char = NULL; diff --git a/c/src/lib/libbsp/or1k/or1ksim/console/uart.c b/c/src/lib/libbsp/or1k/or1ksim/console/uart.c new file mode 100644 index 0000000..f1cfa09 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/console/uart.c @@ -0,0 +1,144 @@ +/** + * @file + * + * @ingroup or1ksim_uart + * + * @brief UART support. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#include +#include +#include +#include +#include +#include + +static rtems_vector_number uart_get_irq_number(const console_tbl *ct) +{ + return ct->ulIntVector; +} + +static uint32_t uart_get_baud(const console_tbl *ct) +{ + return ct->ulClock; +} + +static void uart_set_baud(int baud) +{ + int divisor = (OR1KSIM_BSP_CLOCK_FREQ) / (16 * baud); + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) |= + OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB; + + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_LOW) = divisor & 0xff; + + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_HIGH) = + (divisor >> 8) & 0xff; + + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) &= + ~(OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB); +} + +static void uart_initialize(int minor) +{ + /* Disable all interrupts */ + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_INT_ENABLE) = 0x00; + + /* Reset receiver and transmitter */ + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_FIFO_CTRL) = + OR1KSIM_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO | + OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR | + OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_XMIT | + OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_14; + + /* Set data pattern configuration */ + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) = + OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN8 & + (OR1KSIM_BSP_UART_REG_LINE_CTRL_STOP | + OR1KSIM_BSP_UART_REG_LINE_CTRL_PARITY); + + /* Set baud rate */ + uart_set_baud(OR1KSIM_UART_DEFAULT_BAUD); +} + +static int uart_first_open(int major, int minor, void *arg) +{ + rtems_libio_open_close_args_t *oc = (rtems_libio_open_close_args_t *) arg; + struct rtems_termios_tty *tty = (struct rtems_termios_tty *) oc->iop->data1; + const console_tbl *ct = Console_Port_Tbl [minor]; + console_data *cd = &Console_Port_Data [minor]; + + cd->termios_data = tty; + rtems_termios_set_initial_baud(tty, ct->ulClock); + + return 0; +} + +static int uart_last_close(int major, int minor, void *arg) +{ + return 0; +} + +static int uart_read_polled(int minor) +{ + return -1; +} + +static void uart_write_polled(int minor, char c) +{ + unsigned char lsr; + const uint32_t transmit_finished = + (OR1KSIM_BSP_UART_REG_LINE_STATUS_TEMT | + OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE); + + /* Wait until there is no pending data in the transmitter FIFO (empty) */ + do { + lsr = OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_STATUS); + } while (!(lsr & OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE)); + + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_TX) = c; + + /* Wait until trasmit data is finished */ + do { + lsr = OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_STATUS); + } while ( (lsr & transmit_finished) != transmit_finished ); +} + +static ssize_t uart_write_support_polled( + int minor, + const char *s, + size_t n +) +{ + ssize_t i = 0; + + for (i = 0; i < n; ++i){ + uart_write_polled(minor, s [i]); + } + + return n; +} + +static int uart_set_attributes(int minor, const struct termios *term) +{ + return -1; +} + +const console_fns or1ksim_uart_fns = { + .deviceProbe = libchip_serial_default_probe, + .deviceFirstOpen = uart_first_open, + .deviceLastClose = uart_last_close, + .deviceRead = uart_read_polled, + .deviceWrite = uart_write_support_polled, + .deviceInitialize = uart_initialize, + .deviceWritePolled = uart_write_polled, + .deviceSetAttributes = uart_set_attributes, + .deviceOutputUsesInterrupts = false +}; diff --git a/c/src/lib/libbsp/or1k/or1ksim/include/bsp.h b/c/src/lib/libbsp/or1k/or1ksim/include/bsp.h new file mode 100644 index 0000000..502e4d9 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/include/bsp.h @@ -0,0 +1,47 @@ +/** + * @file + * + * @ingroup or1k_or1ksim + * + * @brief Global BSP definitions. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#ifndef LIBBSP_OR1K_OR1KSIM_H +#define LIBBSP_OR1K_OR1KSIM_H + +#include +#include +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_OR1K_OR1KSIM_H */ + +/** + * @defgroup or1k_or1ksim support + * + * @ingroup bsp_or1k + * + * @brief or1ksim support package + * + */ diff --git a/c/src/lib/libbsp/or1k/or1ksim/include/irq.h b/c/src/lib/libbsp/or1k/or1ksim/include/irq.h new file mode 100644 index 0000000..be669d8 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/include/irq.h @@ -0,0 +1,45 @@ +/** + * @file + * + * @ingroup or1ksim_interrupt + * + * @brief Interrupt definitions. + */ + +/** + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#ifndef LIBBSP_OR1K_OR1KSIM_IRQ_H +#define LIBBSP_OR1K_OR1KSIM_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#define BSP_INTERRUPT_VECTOR_MIN 0x100 +#define BSP_INTERRUPT_VECTOR_MAX 0x1F00 + +/* Interrupt Identification Register */ +#define OR1KSIM_BSP_UART_REG_INT_ID_MSI (0x00) +#define OR1KSIM_BSP_UART_REG_INT_ID_NO_INT (0x01) +#define OR1KSIM_BSP_UART_REG_INT_ID_THRI (0x02) +#define OR1KSIM_BSP_UART_REG_INT_ID_RDI (0x04) +#define OR1KSIM_BSP_UART_REG_INT_ID_ID (0x06) +#define OR1KSIM_BSP_UART_REG_INT_ID_RLSI (0x06) +#define OR1KSIM_BSP_UART_REG_INT_ID_TOI (0x0c) + +/* Interrupt Enable Register */ +#define OR1KSIM_BSP_UART_REG_INT_ENABLE_RDI (0x01) +#define OR1KSIM_BSP_UART_REG_INT_ENABLE_THRI (0x02) +#define OR1KSIM_BSP_UART_REG_INT_ENABLE_RLSI (0x04) +#define OR1KSIM_BSP_UART_REG_INT_ENABLE_MSI (0x08) + +#endif /* ASM */ +#endif /* LIBBSP_OR1K_OR1KSIM_IRQ_H */ diff --git a/c/src/lib/libbsp/or1k/or1ksim/include/or1ksim.h b/c/src/lib/libbsp/or1k/or1ksim/include/or1ksim.h new file mode 100644 index 0000000..8279566 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/include/or1ksim.h @@ -0,0 +1,118 @@ +/** + * @file + * + * @ingroup or1ksim_reg + * + * @brief Register definitions. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#ifndef LIBBSP_OR1K_OR1KSIM_H +#define LIBBSP_OR1K_OR1KSIM_H + +#include + +/** + * @defgroup or1ksim_reg Register Definitions + * + * @ingroup or1k_or1ksim + * + * @brief Register Definitions + * + * @{ + */ + +/** + * @name Register Macros + * + * @{ + */ + + #define OR1KSIM_REG(x) (*((volatile char *) (x))) + #define OR1KSIM_BIT(n) (1 << (n)) + +/** @} */ + +/** + * @name Internal OR1K UART Registers + * + * @{ + */ +#define OR1KSIM_BSP_CLOCK_FREQ 100000000UL +#define OR1KSIM_BSP_UART_BASE 0x90000000 + +#define OR1KSIM_BSP_UART_REG_TX (OR1KSIM_BSP_UART_BASE+0) +#define OR1KSIM_BSP_UART_REG_RX (OR1KSIM_BSP_UART_BASE+0) +#define OR1KSIM_BSP_UART_REG_DEV_LATCH_LOW (OR1KSIM_BSP_UART_BASE+1) +#define OR1KSIM_BSP_UART_REG_DEV_LATCH_HIGH (OR1KSIM_BSP_UART_BASE+1) +#define OR1KSIM_BSP_UART_REG_INT_ENABLE (OR1KSIM_BSP_UART_BASE+2) +#define OR1KSIM_BSP_UART_REG_INT_ID (OR1KSIM_BSP_UART_BASE+2) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL (OR1KSIM_BSP_UART_BASE+2) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL (OR1KSIM_BSP_UART_BASE+3) +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL (OR1KSIM_BSP_UART_BASE+4) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS (OR1KSIM_BSP_UART_BASE+5) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS (OR1KSIM_BSP_UART_BASE+6) +#define OR1KSIM_BSP_UART_REG_SCRATCH (OR1KSIM_BSP_UART_BASE+7) + +/* FIFO Control Register */ +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_1 (0x00) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO (0x01) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR (0x02) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_XMIT (0x03) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_DMA_SELECT (0x08) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_4 (0x40) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_8 (0x80) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_14 (0xC0) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_MASK (0xC0) + +/* Line Control Register */ +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN5 (0x00) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN6 (0x01) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN7 (0x02) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN8 (0x03) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_STOP (0x04) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_PARITY (0x08) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_EPAR (0x10) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_SPAR (0x20) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_SBC (0x40) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB (0x80) + +/* Line Status Register */ +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_DR (0x01) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_OE (0x02) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_PE (0x04) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_FE (0x08) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_BI (0x10) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE (0x20) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_TEMT (0x40) + +/* Modem Control Register */ +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_DTR (0x01) +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_RTS (0x02) +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_OUT1 (0x04) +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_OUT2 (0x08) +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_LOOP (0x10) + +/* Modem Status Register */ +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DCTS (0x01) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DDSR (0x02) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_TERI (0x04) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DDCD (0x08) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_CTS (0x10) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DSR (0x20) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_RI (0x40) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DCD (0x80) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_ANY_DELTA (0x0F) + +/** @} */ + +/** @} */ + +#endif /* LIBBSP_OR1K_OR1KSIM_H */ diff --git a/c/src/lib/libbsp/or1k/or1ksim/include/uart.h b/c/src/lib/libbsp/or1k/or1ksim/include/uart.h new file mode 100644 index 0000000..92ed203 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/include/uart.h @@ -0,0 +1,42 @@ +/** + * @file + * + * @ingroup or1ksim_uart + * + * @brief UART support. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +/** + * @defgroup or1ksim_uart UART Support + * + * @ingroup or1k_or1ksim + * + * @brief Universal Asynchronous Receiver/Transmitter (UART) Support + */ + +#ifndef LIBBSP_OR1K_OR1KSIM_UART_H +#define LIBBSP_OR1K_OR1KSIM_UART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define OR1KSIM_UART_DEFAULT_BAUD 115200 +#define OR1KSIM_BSP_UART_IRQ 13 +extern const console_fns or1ksim_uart_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_OR1K_OR1KSIM_UART_H */ diff --git a/c/src/lib/libbsp/or1k/or1ksim/irq/irq.c b/c/src/lib/libbsp/or1k/or1ksim/irq/irq.c new file mode 100644 index 0000000..c3c4d6d --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/irq/irq.c @@ -0,0 +1,42 @@ +/** + * @file + * + * @ingroup or1k_interrupt + * + * @brief Interrupt support. + */ + +/* + * Copyright (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include + +/* Almost all of the jobs that the following functions should + * do are implemented in cpukit + */ + +void bsp_interrupt_handler_default(rtems_vector_number vector) +{ + printk("spurious interrupt: %u\n", vector); +} + +rtems_status_code bsp_interrupt_facility_initialize() +{ + return 0; +} + +rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) +{ + return 0; +} + +rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) +{ + return 0; +} diff --git a/c/src/lib/libbsp/or1k/or1ksim/make/custom/or1k_or1ksim.cfg b/c/src/lib/libbsp/or1k/or1ksim/make/custom/or1k_or1ksim.cfg new file mode 100644 index 0000000..fff00ae --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/make/custom/or1k_or1ksim.cfg @@ -0,0 +1,7 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = or1k + +CPU_CFLAGS = -O2 + +CFLAGS_OPTIMIZE_V ?= -O0 -g diff --git a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am new file mode 100644 index 0000000..e75733c --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am @@ -0,0 +1,114 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES = $(TMPINSTALL_FILES) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) + +$(PROJECT_LIB)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_LIB) + @: > $(PROJECT_LIB)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) + +$(PROJECT_INCLUDE)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE) + @: > $(PROJECT_INCLUDE)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) + +$(PROJECT_INCLUDE)/bsp/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp + @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) + +$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs +PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs + +$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h + +$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h + +$(PROJECT_INCLUDE)/bsp/linker-symbols.h: ../shared/include/linker-symbols.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/linker-symbols.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/linker-symbols.h + +$(PROJECT_INCLUDE)/bsp/mm.h: ../../../libbsp/shared/include/mm.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mm.h + +$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h + +$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h + +$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h + +$(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h + +$(PROJECT_INCLUDE)/bsp/uart-output-char.h: ../../shared/include/uart-output-char.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart-output-char.h + +$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h + +$(PROJECT_INCLUDE)/bsp/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tm27.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tm27.h + +$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h + +$(PROJECT_INCLUDE)/bsp/uart.h: include/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h + +$(PROJECT_INCLUDE)/bsp/or1ksim.h: include/or1ksim.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/or1ksim.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/or1ksim.h + +$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h + +$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h + +$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) +TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) + +$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds + +$(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base diff --git a/c/src/lib/libbsp/or1k/or1ksim/start/start.S b/c/src/lib/libbsp/or1k/or1ksim/start/start.S new file mode 100644 index 0000000..6942b52 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/start/start.S @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ +#include + +/* The following macro defines the first instructions every exception + * should execute before jumping to its handler function from the + * exception vector table. r3 is saved into the stack and loaded with + * vector number before jumping to _ISR_Handler. r3 value is restored + * back from _ISR_Handler after handling the exception and before + * returning from interrupt. + */ +#define EXCEPTION_SETUP(vector) \ + l.nop ;\ + l.addi r1, r1, -4 ;\ + l.sw 0(r1), r3; \ + l.addi r3, r0, vector; \ + l.j _ISR_Handler; \ + l.nop + + .extern bsp_start + .extern boot_card + .extern bsp_section_bss_begin + .extern bsp_section_bss_end + + .extern bsp_start_vector_table_end + .extern bsp_start_vector_table_size + .extern bsp_vector_table_size + .extern bsp_section_stack_begin + + .extern exception_frame_save + .extern _OR1K_Exception_Process + .extern _OR1K_Exception_default + .extern rtems_clock_tick + .extern _exit + .extern printk + .extern bsp_interrupt_handler_default + + /* Global symbols */ + .global _start + .global bsp_start_vector_table_begin + +/* Popualte HW vector table */ + +.section .vector, "ax" + +.org 0x100 +_reset: + l.j _start + l.nop + +.org 0x200 +_buserr: + EXCEPTION_SETUP(2) + +.org 0x300 +_dPageFault: + EXCEPTION_SETUP(3) + +.org 0x400 +_iPageFaule: + EXCEPTION_SETUP(4) + +.org 0x500 +_timer: + EXCEPTION_SETUP(5) + +.org 0x600 +_unalign: + EXCEPTION_SETUP(6) + +.org 0x700 +_undefIns: + EXCEPTION_SETUP(7) + +.org 0x800 +_exInt: + EXCEPTION_SETUP(8) + +.org 0x900 +_dTLB: + EXCEPTION_SETUP(9) + +.org 0xA00 +_iTLB: + EXCEPTION_SETUP(10) + +.org 0xB00 +_range: + EXCEPTION_SETUP(11) + +.org 0xC00 +_syscall: + EXCEPTION_SETUP(12) + +.org 0xD00 +_fp: + EXCEPTION_SETUP(13) + +.org 0xE00 +_trap: + EXCEPTION_SETUP(14) + +.org 0xF00 +_undef1: + EXCEPTION_SETUP(15) + +.org 0x1500 +_undef2: + EXCEPTION_SETUP(16) + +.org 0x1900 +_undef3: + EXCEPTION_SETUP(17) + +.org 0x1F00 + +bsp_start_vector_table_begin: + + .word 0 + .word _start /* Reset */ + .word _OR1K_Exception_default /* Bus Error */ + .word _OR1K_Exception_default /* Data Page Fault */ + .word _OR1K_Exception_default /* Instruction Page Fault */ + .word _OR1K_Exception_default /* Tick timer */ + .word _OR1K_Exception_default /* Alignment */ + .word _OR1K_Exception_default /* Undefiend Instruction */ + .word _OR1K_Exception_default /* External Interrupt */ + .word _OR1K_Exception_default /* Data TLB Miss */ + .word _OR1K_Exception_default /* Instruction TLB Miss */ + .word _OR1K_Exception_default /* Range Exception */ + .word _OR1K_Exception_default /* System Call */ + .word _OR1K_Exception_default /* Floating Point Exception */ + .word _OR1K_Exception_default /* Trap */ + .word _OR1K_Exception_default /* Reserver for future use */ + .word _OR1K_Exception_default /* Reserved for implementation-specific */ + .word _OR1K_Exception_default /* Reserved for custom exceptions. */ + +bsp_start_vector_table_end: + + .section ".bsp_start_text", "ax" + .type _start, at function + +_start: + /* Set SR register to Supervision mode */ + l.ori r1, r0, 0x1 + l.mtspr r0, r1, 17 + + /* load stack and frame pointers */ + l.movhi r1, hi(bsp_section_stack_begin) + l.ori r1, r1, lo(bsp_section_stack_begin) + l.add r2, r0, r1 + +/* Clearing .bss */ + l.movhi r13, hi(bsp_section_bss_begin) + l.ori r13, r13, lo(bsp_section_bss_begin) + l.movhi r15, hi(bsp_section_bss_end) + l.ori r15, r15, lo(bsp_section_bss_end) + +_loop_clear_bss: + l.sfgeu r13, r15 + l.bf _end_clear_bss + l.addi r13, r13, 4 + l.sw 0(r13), r0 + l.j _loop_clear_bss + l.nop +_end_clear_bss: + + l.j boot_card + l.nop + +/* Temporary code for unhandled exceptions */ +.section .text +.align +.global _unhandled_exception + +unhandled_exception: + l.nop diff --git a/c/src/lib/libbsp/or1k/or1ksim/startup/linkcmds b/c/src/lib/libbsp/or1k/or1ksim/startup/linkcmds new file mode 100644 index 0000000..cef99d3 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/startup/linkcmds @@ -0,0 +1,41 @@ +/** + * @file + * + * @ingroup bsp_linker + * + * @brief Memory map + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +MEMORY + { + VECTOR_RAM (AIW) : ORIGIN = 0x0 , LENGTH = 8260 + RAM : org = 0x00002048, l = 0x1FFDFB8 + UNEXPECTED_SECTIONS : ORIGIN = 0xffffffff, LENGTH = 0 + } + +REGION_ALIAS ("REGION_START", RAM); +REGION_ALIAS ("REGION_VECTOR", VECTOR_RAM); +REGION_ALIAS ("REGION_TEXT", RAM); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM); +REGION_ALIAS ("REGION_RODATA", RAM); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM); +REGION_ALIAS ("REGION_DATA", RAM); +REGION_ALIAS ("REGION_DATA_LOAD", RAM); +REGION_ALIAS ("REGION_FAST_DATA", RAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); +REGION_ALIAS ("REGION_BSS", RAM); +REGION_ALIAS ("REGION_WORK", RAM); +REGION_ALIAS ("REGION_STACK", RAM); + +bsp_section_vector_begin = 0; +bsp_section_stack_begin = 0x1FFDFB8; + +INCLUDE linkcmds.base diff --git a/c/src/lib/libbsp/or1k/or1ksim/timer/timer.c b/c/src/lib/libbsp/or1k/or1ksim/timer/timer.c new file mode 100644 index 0000000..ec3c33e --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/timer/timer.c @@ -0,0 +1,64 @@ +/** + * @file + * + * @ingroup or1ksim + * + * @brief Benchmark timer support. + */ + +/* + * Copyright (c) 2014 by Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#include +#include +#include +#include + +#define OR1KSIM_NANOSECONDS_PER_CLK_CYCLE 10 + +static bool benchmark_timer_find_average_overhead = false; +static uint64_t benchmark_timer_base; + +void benchmark_timer_initialize(void) +{ + benchmark_timer_base = _OR1K_mfspr(CPU_OR1K_SPR_TTCR); +} + +#define AVG_OVERHEAD 0 +#define LEAST_VALID 1 + +uint32_t benchmark_timer_read( void ) +{ + uint64_t clicks; + uint64_t total; + uint64_t delta; + /* + * Read the timer and see how many clicks (clock cycles) + * has passed since timer initialization. + */ + clicks = _OR1K_mfspr(CPU_OR1K_SPR_TTCR); + + delta = clicks - benchmark_timer_base; + + /* total in nanoseconds */ + total = OR1KSIM_NANOSECONDS_PER_CLK_CYCLE * (delta); + + if ( benchmark_timer_find_average_overhead == true ) + return total; /* in nanoseconds microsecond units */ + else { + if ( total < LEAST_VALID ) + return 0; /* below timer resolution */ + + return (total - AVG_OVERHEAD); + } +} + +void benchmark_timer_disable_subtracting_average_overhead(bool find_flag) +{ + benchmark_timer_find_average_overhead = find_flag; +} diff --git a/c/src/lib/libbsp/or1k/preinstall.am b/c/src/lib/libbsp/or1k/preinstall.am new file mode 100644 index 0000000..fe8d090 --- /dev/null +++ b/c/src/lib/libbsp/or1k/preinstall.am @@ -0,0 +1,6 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif diff --git a/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h b/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h new file mode 100644 index 0000000..f0f8377 --- /dev/null +++ b/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h @@ -0,0 +1,79 @@ +#ifndef LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup or1k_linker Linker Support + * + * @ingroup or1k_shared + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM + #define LINKER_SYMBOL(sym) extern char sym []; +#else + #define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_vector_begin) +LINKER_SYMBOL(bsp_section_vector_end) +LINKER_SYMBOL(bsp_section_vector_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_vector_table_begin) +LINKER_SYMBOL(bsp_vector_table_end) +LINKER_SYMBOL(bsp_vector_table_size) + +LINKER_SYMBOL(bsp_start_vector_table_begin) +LINKER_SYMBOL(bsp_start_vector_table_end) +LINKER_SYMBOL(bsp_start_vector_table_size) + +LINKER_SYMBOL(bsp_translation_table_base) +LINKER_SYMBOL(bsp_translation_table_end) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_OR1K_SHARED_LINKER_SYMBOLS_H */ diff --git a/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base b/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base new file mode 100644 index 0000000..31bb92d --- /dev/null +++ b/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base @@ -0,0 +1,310 @@ +/** + * @file + * + * @ingroup bsp_linker + * + * @brief Linker command base file. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +OUTPUT_ARCH (or1k) + +ENTRY (_start) + +/* + * Global symbols that may be defined externally + */ + +bsp_start_vector_table_begin = 0x1F00; +bsp_vector_table_size = DEFINED (bsp_vector_table_size) ? bsp_vector_table_size +: 8260; +/* 8192 for raw vector table, and 17 * 4 for handlers vector. */ + +bsp_section_xbarrier_align = DEFINED (bsp_section_xbarrier_align) ? bsp_section_xbarrier_align : 1; +bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1; +bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1; + +bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 8; + +bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 0; +bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align); + +bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 1; + +SECTIONS { + + .vector : ALIGN_WITH_INPUT { + *(.vector) + . = ALIGN(bsp_vector_table_size); + bsp_section_vector_end = .; + } > REGION_VECTOR AT > REGION_VECTOR + bsp_section_vector_size = bsp_section_vector_end - bsp_section_vector_begin; + bsp_vector_table_begin = bsp_section_vector_begin; + bsp_vector_table_end = bsp_vector_table_begin + bsp_vector_table_size; + + .start : ALIGN_WITH_INPUT { + bsp_section_start_begin = .; + KEEP (*(.bsp_start_text)) + KEEP (*(.bsp_start_data)) + bsp_section_start_end = .; + } > REGION_START AT > REGION_START + bsp_section_start_size = bsp_section_start_end - bsp_section_start_begin; + +.xbarrier : ALIGN_WITH_INPUT { + . = ALIGN (bsp_section_xbarrier_align); + } > REGION_VECTOR AT > REGION_VECTOR + +.text : ALIGN_WITH_INPUT { + bsp_section_text_begin = .; + *(.text.unlikely .text.*_unlikely) + *(.text .stub .text.* .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .init : ALIGN_WITH_INPUT { + KEEP (*(.init)) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .fini : ALIGN_WITH_INPUT { + KEEP (*(.fini)) + bsp_section_text_end = .; + } > REGION_TEXT AT > REGION_TEXT_LOAD + bsp_section_text_size = bsp_section_text_end - bsp_section_text_begin; + bsp_section_text_load_begin = LOADADDR (.text); + bsp_section_text_load_end = bsp_section_text_load_begin + bsp_section_text_size; + +.robarrier : ALIGN_WITH_INPUT { + . = ALIGN (bsp_section_robarrier_align); + } > REGION_RODATA AT > REGION_RODATA + +.rodata : ALIGN_WITH_INPUT { + bsp_section_rodata_begin = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD +.eh_frame : ALIGN_WITH_INPUT { + KEEP (*(.eh_frame)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gcc_except_table : ALIGN_WITH_INPUT { + *(.gcc_except_table .gcc_except_table.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tdata : ALIGN_WITH_INPUT { + _TLS_Data_begin = .; + *(.tdata .tdata.* .gnu.linkonce.td.*) + _TLS_Data_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tbss : ALIGN_WITH_INPUT { + _TLS_BSS_begin = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) + _TLS_BSS_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; + _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; + _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; + _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; + _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; + _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); + .preinit_array : ALIGN_WITH_INPUT { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .init_array : ALIGN_WITH_INPUT { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .fini_array : ALIGN_WITH_INPUT { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .ctors : ALIGN_WITH_INPUT { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dtors : ALIGN_WITH_INPUT { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .data.rel.ro : ALIGN_WITH_INPUT { + *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) + *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .jcr : ALIGN_WITH_INPUT { + KEEP (*(.jcr)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .interp : ALIGN_WITH_INPUT { + *(.interp) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .note.gnu.build-id : ALIGN_WITH_INPUT { + *(.note.gnu.build-id) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .hash : ALIGN_WITH_INPUT { + *(.hash) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.hash : ALIGN_WITH_INPUT { + *(.gnu.hash) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynsym : ALIGN_WITH_INPUT { + *(.dynsym) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynstr : ALIGN_WITH_INPUT { + *(.dynstr) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version : ALIGN_WITH_INPUT { + *(.gnu.version) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version_d : ALIGN_WITH_INPUT { + *(.gnu.version_d) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version_r : ALIGN_WITH_INPUT { + *(.gnu.version_r) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rel.dyn : ALIGN_WITH_INPUT { + *(.rel.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rel.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rel.dtors) + *(.rel.got) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + PROVIDE_HIDDEN (__rel_iplt_start = .); + *(.rel.iplt) + PROVIDE_HIDDEN (__rel_iplt_end = .); + PROVIDE_HIDDEN (__rela_iplt_start = .); + PROVIDE_HIDDEN (__rela_iplt_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rela.dyn : ALIGN_WITH_INPUT { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + PROVIDE_HIDDEN (__rel_iplt_start = .); + PROVIDE_HIDDEN (__rel_iplt_end = .); + PROVIDE_HIDDEN (__rela_iplt_start = .); + *(.rela.iplt) + PROVIDE_HIDDEN (__rela_iplt_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rel.plt : ALIGN_WITH_INPUT { + *(.rel.plt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rela.plt : ALIGN_WITH_INPUT { + *(.rela.plt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .plt : ALIGN_WITH_INPUT { + *(.plt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .iplt : ALIGN_WITH_INPUT { + *(.iplt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynamic : ALIGN_WITH_INPUT { + *(.dynamic) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .got : ALIGN_WITH_INPUT { + *(.got.plt) *(.igot.plt) *(.got) *(.igot) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rtemsroset : ALIGN_WITH_INPUT { + /* Special FreeBSD linker set sections */ + __start_set_sysctl_set = .; + *(set_sysctl_*); + __stop_set_sysctl_set = .; + *(set_domain_*); + *(set_pseudo_*); + + KEEP (*(SORT(.rtemsroset.*))) + bsp_section_rodata_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + bsp_section_rodata_size = bsp_section_rodata_end - bsp_section_rodata_begin; + bsp_section_rodata_load_begin = LOADADDR (.rodata); + bsp_section_rodata_load_end = bsp_section_rodata_load_begin + bsp_section_rodata_size; + +.rwbarrier : ALIGN_WITH_INPUT { + . = ALIGN (bsp_section_rwbarrier_align); + } > REGION_DATA AT > REGION_DATA + +.data : ALIGN_WITH_INPUT { + bsp_section_data_begin = .; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } > REGION_DATA AT > REGION_DATA_LOAD + .data1 : ALIGN_WITH_INPUT { + *(.data1) + } > REGION_DATA AT > REGION_DATA_LOAD + .rtemsrwset : ALIGN_WITH_INPUT { + KEEP (*(SORT(.rtemsrwset.*))) + bsp_section_data_end = .; + } > REGION_DATA AT > REGION_DATA_LOAD + bsp_section_data_size = bsp_section_data_end - bsp_section_data_begin; + bsp_section_data_load_begin = LOADADDR (.data); + bsp_section_data_load_end = bsp_section_data_load_begin + bsp_section_data_size; + + .bss : ALIGN_WITH_INPUT { + bsp_section_bss_begin = .; + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + bsp_section_bss_end = .; + } > REGION_BSS AT > REGION_BSS + bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_begin; + +.work : ALIGN_WITH_INPUT { + /* + * The work section will occupy the remaining REGION_WORK region and + * contains the RTEMS work space and heap. + */ + bsp_section_work_begin = .; + . += ORIGIN (REGION_WORK) + LENGTH (REGION_WORK) - ABSOLUTE (.); + bsp_section_work_end = .; + } > REGION_WORK AT > REGION_WORK + bsp_section_work_size = bsp_section_work_end - bsp_section_work_begin; + + .stack : ALIGN_WITH_INPUT { + bsp_section_stack_end = .; + } > REGION_STACK AT > REGION_STACK + bsp_section_stack_size = bsp_section_stack_begin - bsp_section_stack_end; + + RamBase = ORIGIN (REGION_WORK); + RamSize = LENGTH (REGION_WORK); + WorkAreaBase = bsp_section_work_begin; + HeapSize = 0; +} From joel at rtems.org Wed Aug 20 20:41:01 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 20 Aug 2014 15:41:01 -0500 Subject: [rtems commit] or1k.t: Fix spelling errors Message-ID: <20140820204101.1C1B37006E4@git.rtems.org> Module: rtems Branch: master Commit: a7ec6fac9b3c5821031249791d7446d5bf7fca15 Changeset: http://git.rtems.org/rtems/commit/?id=a7ec6fac9b3c5821031249791d7446d5bf7fca15 Author: Joel Sherrill Date: Wed Aug 20 15:49:42 2014 -0500 or1k.t: Fix spelling errors --- doc/cpu_supplement/or1k.t | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/doc/cpu_supplement/or1k.t b/doc/cpu_supplement/or1k.t index 4f1bf18..cce55fd 100644 --- a/doc/cpu_supplement/or1k.t +++ b/doc/cpu_supplement/or1k.t @@ -59,10 +59,10 @@ There are only two levels: interrupts enabled and interrupts disabled. @subsection Interrupt Stack -OpenRISC RTEMS port uses RTEMS SW interrupt stack. -The stack for interrupts is allocated during interrupt driver initilization. -When an interrup entered, the _ISR_Handler routine is resposible for -switching from the interrupted task stack to RTEMS SW interrupt stack. +The OpenRISC RTEMS port uses a dedicated software interrupt stack. +The stack for interrupts is allocated during interrupt driver initialization. +When an interrupt is entered, the _ISR_Handler routine is responsible for +switching from the interrupted task stack to RTEMS software interrupt stack. @section Default Fatal Error Processing From joel at rtems.org Wed Aug 20 20:41:01 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 20 Aug 2014 15:41:01 -0500 Subject: [rtems commit] Add new documentation section for OpenRISC CPU architecture. Message-ID: <20140820204101.3D44F7006BA@git.rtems.org> Module: rtems Branch: master Commit: b08829228d2efc6c506fa3a05b0266baf70f8681 Changeset: http://git.rtems.org/rtems/commit/?id=b08829228d2efc6c506fa3a05b0266baf70f8681 Author: Hesham ALMatary Date: Sat Aug 16 11:30:19 2014 -0500 Add new documentation section for OpenRISC CPU architecture. --- doc/cpu_supplement/Makefile.am | 6 +++ doc/cpu_supplement/cpu_supplement.texi | 2 + doc/cpu_supplement/or1k.t | 76 ++++++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+), 0 deletions(-) diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am index 3083922..300ff78 100644 --- a/doc/cpu_supplement/Makefile.am +++ b/doc/cpu_supplement/Makefile.am @@ -23,6 +23,7 @@ GENERATED_FILES += m32r.texi GENERATED_FILES += m68k.texi GENERATED_FILES += microblaze.texi GENERATED_FILES += mips.texi +GENERATED_FILES += or1k.texi GENERATED_FILES += powerpc.texi GENERATED_FILES += nios2.texi GENERATED_FILES += sh.texi @@ -101,6 +102,11 @@ mips.texi: mips.t -u "Top" \ -n "" < $< > $@ +or1k.texi: or1k.t + $(BMENU2) -p "" \ + -u "Top" \ + -n "" < $< > $@ + powerpc.texi: powerpc.t $(BMENU2) -p "" \ -u "Top" \ diff --git a/doc/cpu_supplement/cpu_supplement.texi b/doc/cpu_supplement/cpu_supplement.texi index 1087538..5c484d0 100644 --- a/doc/cpu_supplement/cpu_supplement.texi +++ b/doc/cpu_supplement/cpu_supplement.texi @@ -73,6 +73,7 @@ * M68xxx and Coldfire Specific Information:: * Xilinx MicroBlaze Specific Information:: * MIPS Specific Information:: +* OpenRISC 1000 Specific Information:: * Altera Nios II Specific Information:: * PowerPC Specific Information:: * SuperH Specific Information:: @@ -97,6 +98,7 @@ @include microblaze.texi @include mips.texi @include nios2.texi + at include or1k.texi @include powerpc.texi @include sh.texi @include sparc.texi diff --git a/doc/cpu_supplement/or1k.t b/doc/cpu_supplement/or1k.t new file mode 100644 index 0000000..4f1bf18 --- /dev/null +++ b/doc/cpu_supplement/or1k.t @@ -0,0 +1,76 @@ + at c + at c COPYRIGHT (c) 2014 Hesham ALMatary + at c All rights reserved. + + at ifinfo + at end ifinfo + at chapter OpenRISC 1000 Specific Information + +This chapter discusses the + at uref{http://opencores.org/or1k/Main_Page, OpenRISC 1000 architecture} +dependencies in this port of RTEMS. There are many implementations +for OpenRISC like or1200 and mor1kx. Currently RTEMS supports basic +features that all implementations should have. + + at subheading Architecture Documents + +For information on the OpenRISC 1000 architecture refer to the + at uref{http://openrisc.github.io/or1k.html,OpenRISC 1000 architecture manual}. + + at section Calling Conventions + +Please refer to the + at uref{http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882,Function Calling Sequence}. + + at subsection Floating Point Unit + +A floating point unit is currently not supported. + + at section Memory Model + +A flat 32-bit memory model is supported. + + at section Interrupt Processing + +OpenRISC 1000 architecture has 13 exception types: + + at itemize @bullet + + at item Reset + at item Bus Error + at item Data Page Fault + at item Instruction Page Fault + at item Tick Timer + at item Alignment + at item Illegal Instruction + at item External Interrupt + at item D-TLB Miss + at item I-TLB Miss + at item Range + at item System Call + at item Floating Point + at item Trap + + at end itemize + + at subsection Interrupt Levels + +There are only two levels: interrupts enabled and interrupts disabled. + + at subsection Interrupt Stack + +OpenRISC RTEMS port uses RTEMS SW interrupt stack. +The stack for interrupts is allocated during interrupt driver initilization. +When an interrup entered, the _ISR_Handler routine is resposible for +switching from the interrupted task stack to RTEMS SW interrupt stack. + + at section Default Fatal Error Processing + +The default fatal error handler for this architecture performs the +following actions: + + at itemize @bullet + at item disables operating system supported interrupts (IRQ), + at item places the error code in @code{r0}, and + at item executes an infinite loop to simulate a halt processor instruction. + at end itemize From joel at rtems.org Wed Aug 20 22:00:19 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 20 Aug 2014 17:00:19 -0500 Subject: [rtems commit] mpc55xx/misc/flash_support.c: Properly flush cache when writing. Message-ID: <20140820220019.41C827006BA@git.rtems.org> Module: rtems Branch: master Commit: dc661c87e1d8cda26330016976c4416805c65c7c Changeset: http://git.rtems.org/rtems/commit/?id=dc661c87e1d8cda26330016976c4416805c65c7c Author: Peter Dufault Date: Wed Aug 20 17:08:23 2014 -0500 mpc55xx/misc/flash_support.c: Properly flush cache when writing. Also cleanup: * Remove un-needed interrupt disables. * Address errata "e989: FLASH: Disable Prefetch during programming and erase" * Use RTEMS_ARRAY_SIZE() macro instead of own macro. --- .../libcpu/powerpc/mpc55xx/misc/flash_support.c | 85 +++++++++----------- 1 files changed, 39 insertions(+), 46 deletions(-) diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c index 17c4e3f..b286b51 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c +++ b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c @@ -135,8 +135,6 @@ range_set( *p_bits = bits; } -#define N(ARG) (sizeof(ARG)/sizeof(ARG[0])) - /** Return the size of the on-chip flash * verifying that this is a device that we know about. * @return 0 for OK, non-zero for error: @@ -207,7 +205,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) union LMLR_tag lmlr; union SLMLR_tag slmlr; union HLR_tag hlr; - rtems_interrupt_level level; /* If we're already locked return. */ @@ -217,7 +214,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) /* Do we have to lock something in the low or mid block? */ - rtems_interrupt_disable(level); lmlr = FLASH.LMLR; if ((lsel || msel) && (lmlr.B.LME == 0)) { union LMLR_tag lmlr_unlock; @@ -228,7 +224,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) if (lmlr.B.LLOCK != lmlr_unlock.B.LLOCK || lmlr.B.MLOCK != lmlr_unlock.B.MLOCK) { if (p_locked == 0) { - rtems_interrupt_enable(level); return MPC55XX_FLASH_LOCK_ERR; } else { *p_locked = 1; @@ -237,9 +232,7 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) FLASH.LMLR = lmlr_unlock; } } - rtems_interrupt_enable(level); - rtems_interrupt_disable(level); slmlr = FLASH.SLMLR; if ((lsel || msel) && (slmlr.B.SLE == 0)) { union SLMLR_tag slmlr_unlock; @@ -250,7 +243,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) if (slmlr.B.SLLOCK != slmlr_unlock.B.SLLOCK || slmlr.B.SMLOCK != slmlr_unlock.B.SMLOCK) { if (p_locked == 0) { - rtems_interrupt_enable(level); return MPC55XX_FLASH_LOCK_ERR; } else { *p_locked = 1; @@ -259,11 +251,9 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) FLASH.SLMLR = slmlr_unlock; } } - rtems_interrupt_enable(level); /* Do we have to unlock something in the high block? */ - rtems_interrupt_disable(level); hlr = FLASH.HLR; if (hbsel && (hlr.B.HBE == 0)) { union HLR_tag hlr_unlock; @@ -272,7 +262,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) if (hlr.B.HBLOCK != hlr_unlock.B.HBLOCK) { if (p_locked == 0) { return MPC55XX_FLASH_LOCK_ERR; - rtems_interrupt_enable(level); } else { *p_locked = 1; } @@ -280,7 +269,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) FLASH.HLR = hlr_unlock; } } - rtems_interrupt_enable(level); return 0; } @@ -398,24 +386,25 @@ mpc55xx_flash_copy_op( { uint32_t udest, usrc, flash_size; int r; - int peg; /* Program or Erase Good - Did it work? */ + int peg; /* Program or Erase Good - Did it work? */ - int lsel; /* Low block select bits. */ - int msel; /* Mid block select bits. */ - int hbsel; /* High block select bits. */ + int lsel; /* Low block select bits. */ + int msel; /* Mid block select bits. */ + int hbsel; /* High block select bits. */ - int s_lsel; /* Source Low block select bits. */ - int s_msel; /* Source Mid block select bits. */ - int s_hbsel; /* Source High block select bits. */ + int s_lsel; /* Source Low block select bits. */ + int s_msel; /* Source Mid block select bits. */ + int s_hbsel; /* Source High block select bits. */ int unlocked = 0; int *p_unlocked; int i; - int nwords; /* The number of 32 bit words to write. */ - volatile uint32_t *flash; /* Where the flash is mapped in. */ - volatile uint32_t *memory; /* What to copy into flash. */ - uint32_t offset; /* Where the FLASH is mapped into memory. */ - rtems_interrupt_level level; + int nwords; /* The number of 32 bit words to write. */ + volatile uint32_t *flash; /* Where the flash is mapped in. */ + volatile uint32_t *memory; /* What to copy into flash. */ + const void *flashing_from; /* Where we are flahsing from. + * "const" is to match invalidate cache function signature. */ + uint32_t offset; /* Where the FLASH is mapped into memory. */ if ( (r = mpc55xx_flash_size(&flash_size))) { return r; @@ -461,13 +450,13 @@ mpc55xx_flash_copy_op( /* Set up the bit masks for the blocks to program or erase. */ - range_set(udest, udest + nbytes, &lsel, lsel_ranges, N( lsel_ranges)); - range_set(udest, udest + nbytes, &msel, msel_ranges, N( msel_ranges)); - range_set(udest, udest + nbytes, &hbsel, hbsel_ranges, N(hbsel_ranges)); + range_set(udest, udest + nbytes, &lsel, lsel_ranges, RTEMS_ARRAY_SIZE( lsel_ranges)); + range_set(udest, udest + nbytes, &msel, msel_ranges, RTEMS_ARRAY_SIZE( msel_ranges)); + range_set(udest, udest + nbytes, &hbsel, hbsel_ranges, RTEMS_ARRAY_SIZE(hbsel_ranges)); - range_set(usrc, usrc + nbytes, &s_lsel, lsel_ranges, N( lsel_ranges)); - range_set(usrc, usrc + nbytes, &s_msel, msel_ranges, N( msel_ranges)); - range_set(usrc, usrc + nbytes, &s_hbsel, hbsel_ranges, N(hbsel_ranges)); + range_set(usrc, usrc + nbytes, &s_lsel, lsel_ranges, RTEMS_ARRAY_SIZE( lsel_ranges)); + range_set(usrc, usrc + nbytes, &s_msel, msel_ranges, RTEMS_ARRAY_SIZE( msel_ranges)); + range_set(usrc, usrc + nbytes, &s_hbsel, hbsel_ranges, RTEMS_ARRAY_SIZE(hbsel_ranges)); /* Are we attempting overlapping flash? */ @@ -481,33 +470,39 @@ mpc55xx_flash_copy_op( /* In the following sections any "Step N" notes refer to * the steps in "13.4.2.3 Flash Programming" in the reference manual. - * XXX Do parts of this neeed to be protected by interrupt locks? */ if (opmask & MPC55XX_FLASH_ERASE) { /* Erase. */ + uint32_t flash_biucr_r; if ( (r = unlock_once(lsel, msel, hbsel, p_unlocked)) ) { return r; } - rtems_interrupt_disable(level); + /* Per errata "e989: FLASH: Disable Prefetch during programming and erase" */ + flash_biucr_r = FLASH.BIUCR.R; + FLASH.BIUCR.B.PFLIM = 0; + + FLASH.MCR.B.ESUS = 0; /* Be sure ESUS is clear. */ + FLASH.MCR.B.ERS = 1; /* Step 1: Select erase. */ FLASH.LMSR.B.LSEL = lsel; /* Step 2: Select blocks to be erased. */ FLASH.LMSR.B.MSEL = msel; FLASH.HSR.B.HBSEL = hbsel; - flash[0] = 1; /* Step 3: Write to any address in the flash + flash[0] = 0xffffffff; /* Step 3: Write to any address in the flash * (the "erase interlock write)". */ + rtems_cache_flush_multiple_data_lines(flash, sizeof(flash[0])); + FLASH.MCR.B.EHV = 1; /* Step 4: Enable high V to start erase. */ - rtems_interrupt_enable(level); while (FLASH.MCR.B.DONE == 0) { /* Step 5: Wait until done. */ } - rtems_interrupt_disable(level); peg = FLASH.MCR.B.PEG; /* Save result. */ FLASH.MCR.B.EHV = 0; /* Disable high voltage. */ FLASH.MCR.B.ERS = 0; /* De-select erase. */ - rtems_interrupt_enable(level); + FLASH.BIUCR.R = flash_biucr_r; + if (peg == 0) { return MPC55XX_FLASH_ERASE_ERR; /* Flash erase failed. */ } @@ -534,9 +529,7 @@ mpc55xx_flash_copy_op( } FLASH.MCR.B.PGM = 1; /* Step 1 */ - rtems_interrupt_disable(level); - - for (i = 0; i < nwords; i += 2) { + for (flashing_from = (const void *)flash, i = 0; i < nwords; i += 2) { flash[i] = memory[i]; /* Step 2 */ flash[i + 1] = memory[i + 1]; /* Always program in min 64 bits. */ @@ -548,45 +541,45 @@ mpc55xx_flash_copy_op( chunk++; if (chunk == 4) { /* Collected 4 64-bits for a 256 bit chunk. */ + + rtems_cache_flush_multiple_data_lines(flashing_from, 32); /* Flush cache. */ + FLASH.MCR.B.EHV = 1; /* Step 4: Enable high V. */ - rtems_interrupt_enable(level); while (FLASH.MCR.B.DONE == 0) { /* Step 5: Wait until done. */ } - rtems_interrupt_disable(level); peg = FLASH.MCR.B.PEG; /* Step 6: Save result. */ FLASH.MCR.B.EHV = 0; /* Step 7: Disable high V. */ if (peg == 0) { FLASH.MCR.B.PGM = 0; - rtems_interrupt_enable(level); if (p_fail) { *p_fail = (uint32_t)(flash + i); } return MPC55XX_FLASH_PROGRAM_ERR; /* Programming failed. */ } chunk = 0; /* Reset chunk counter. */ + flashing_from = (const void *)(flash + i); } /* Step 8: Back to step 2. */ } if (!chunk) { FLASH.MCR.B.PGM = 0; - rtems_interrupt_enable(level); } else { /* If there is anything left in that last chunk flush it out: */ + + rtems_cache_flush_multiple_data_lines(flashing_from, chunk * 8); + FLASH.MCR.B.EHV = 1; - rtems_interrupt_enable(level); while (FLASH.MCR.B.DONE == 0) { /* Wait until done. */ } - rtems_interrupt_disable(level); peg = FLASH.MCR.B.PEG; /* Save result. */ FLASH.MCR.B.EHV = 0; /* Disable high voltage. */ FLASH.MCR.B.PGM = 0; - rtems_interrupt_enable(level); if (peg == 0) { if (p_fail) { From joel at rtems.org Thu Aug 21 13:33:42 2014 From: joel at rtems.org (Joel Sherrill) Date: Thu, 21 Aug 2014 08:33:42 -0500 Subject: [rtems commit] Add configuration to detect toolset has sigaltstack() prototype Message-ID: <20140821133342.530957006BA@git.rtems.org> Module: rtems Branch: master Commit: 57871880b203d1225065640dbe8c16aa6d0f3c62 Changeset: http://git.rtems.org/rtems/commit/?id=57871880b203d1225065640dbe8c16aa6d0f3c62 Author: Joel Sherrill Date: Wed Aug 20 18:47:02 2014 -0500 Add configuration to detect toolset has sigaltstack() prototype --- cpukit/configure.ac | 12 ++++++++++++ cpukit/libnetworking/rtems/rtems_bsdnet_internal.h | 10 ++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/cpukit/configure.ac b/cpukit/configure.ac index 56815e2..fcf3437 100644 --- a/cpukit/configure.ac +++ b/cpukit/configure.ac @@ -116,6 +116,12 @@ RTEMS_CHECK_FUNC([pthread_getattr_np],[ #include ]) AC_CHECK_HEADERS([sys/cpuset.h]) +# This was added to newlib in August 2014 to improve conformance. +# Disable use of internal definition if it is present. +RTEMS_CHECK_FUNC([sigaltstack],[ + #define _GNU_SOURCE + #include ]) + # Mandated by POSIX, not declared in some versions of newlib. AC_CHECK_DECLS([getrusage],,,[#include sys/resource.h]) @@ -236,6 +242,12 @@ RTEMS_CPUOPT([__RTEMS_HAVE_SYS_CPUSET_H__], [1], [indicate if is present in toolset]) +## Header file differences that need to be known in .h after install +RTEMS_CPUOPT([__RTEMS_HAVE_DECL_SIGALTSTACK__], + [test x"${ac_cv_have_decl_sigaltstack}" = x"yes"], + [1], + [indicate if in toolset has sigaltstack()]) + ## This improves both the size and coverage analysis. RTEMS_CPUOPT([__RTEMS_DO_NOT_INLINE_THREAD_ENABLE_DISPATCH__], [test x"${RTEMS_DO_NOT_INLINE_THREAD_ENABLE_DISPATCH}" = x"1"], diff --git a/cpukit/libnetworking/rtems/rtems_bsdnet_internal.h b/cpukit/libnetworking/rtems/rtems_bsdnet_internal.h index 05e54b2..567cc8a 100644 --- a/cpukit/libnetworking/rtems/rtems_bsdnet_internal.h +++ b/cpukit/libnetworking/rtems/rtems_bsdnet_internal.h @@ -83,11 +83,13 @@ typedef quad_t * qaddr_t; typedef void __sighandler_t(int); typedef __sighandler_t *sig_t; /* type of pointer to a signal function */ #define NSIG 32 -struct sigaltstack { - char *ss_sp; /* signal stack base */ - int ss_size; /* signal stack length */ - int ss_flags; /* SS_DISABLE and/or SS_ONSTACK */ +#if (__RTEMS_HAVE_DECL_SIGALTSTACK__ == 0) +struct sigaltstack { + char *ss_sp; /* signal stack base */ + int ss_size; /* signal stack length */ + int ss_flags; /* SS_DISABLE and/or SS_ONSTACK */ }; +#endif #ifdef _KERNEL typedef int boolean_t; From joel at rtems.org Thu Aug 21 13:59:27 2014 From: joel at rtems.org (Joel Sherrill) Date: Thu, 21 Aug 2014 08:59:27 -0500 Subject: [rtems commit] bsp/tms570: implemented support functions to satisfy complete tests build requirements . Message-ID: <20140821135928.0EE167006BA@git.rtems.org> Module: rtems Branch: master Commit: 46265063e3300ab613c03151d7aaade580b10554 Changeset: http://git.rtems.org/rtems/commit/?id=46265063e3300ab613c03151d7aaade580b10554 Author: Pavel Pisa Date: Thu Aug 21 08:38:24 2014 -0500 bsp/tms570: implemented support functions to satisfy complete tests build requirements. This patch enables to build all RTEMS tests for tms570ls3137_hdk_sdram BSP variant in in default build. Debug build with --enable-rtems-debug set has succeed for samples subset of tests as well. --- c/src/lib/libbsp/arm/tms570/Makefile.am | 9 +++ .../lib/libbsp/arm/tms570/clock/benchmark_timer.c | 61 +++++++++++++++++++ c/src/lib/libbsp/arm/tms570/clock/clock.c | 4 +- .../lib/libbsp/arm/tms570/include/system-clocks.h | 62 ++++++++++++++++++++ .../arm/tms570/make/custom/tms570ls3137_hdk.cfg | 2 +- .../tms570/make/custom/tms570ls3137_hdk_intram.cfg | 2 +- .../tms570/make/custom/tms570ls3137_hdk_sdram.cfg | 2 +- c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c | 44 ++++++++++++++ c/src/lib/libbsp/arm/tms570/preinstall.am | 4 + 9 files changed, 186 insertions(+), 4 deletions(-) diff --git a/c/src/lib/libbsp/arm/tms570/Makefile.am b/c/src/lib/libbsp/arm/tms570/Makefile.am index 02d7b66..e66cf79 100644 --- a/c/src/lib/libbsp/arm/tms570/Makefile.am +++ b/c/src/lib/libbsp/arm/tms570/Makefile.am @@ -39,6 +39,7 @@ include_bsp_HEADERS += include/tms570-rti.h include_bsp_HEADERS += include/tms570-vim.h include_bsp_HEADERS += include/tms570-pom.h include_bsp_HEADERS += include/tms570-sci-driver.h +include_bsp_HEADERS += include/system-clocks.h include_HEADERS += ../../shared/include/tm27.h @@ -78,6 +79,7 @@ libbsp_a_SOURCES += ../../shared/bsppredriverhook.c libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c libbsp_a_SOURCES += ../../shared/sbrk.c libbsp_a_SOURCES += ../../shared/src/stackalloc.c +libbsp_a_SOURCES += ../../shared/cpucounterdiff.c # Startup libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S @@ -105,6 +107,7 @@ libbsp_a_SOURCES += console/tms570-sci.c # Clock libbsp_a_SOURCES += ../../shared/clockdrv_shell.h libbsp_a_SOURCES += clock/clock.c +libbsp_a_SOURCES += clock/benchmark_timer.c # RTC @@ -115,9 +118,15 @@ libbsp_a_SOURCES += clock/clock.c # Benchmark Timer # Misc +libbsp_a_SOURCES += misc/cpucounterread.c # Watchdog +# Cache +libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c +libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h +libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include + # Start hooks libbsp_a_SOURCES += startup/bspstarthooks.c diff --git a/c/src/lib/libbsp/arm/tms570/clock/benchmark_timer.c b/c/src/lib/libbsp/arm/tms570/clock/benchmark_timer.c new file mode 100644 index 0000000..b45f0f4 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/clock/benchmark_timer.c @@ -0,0 +1,61 @@ +/** + * @file benchmark_timer.c + * + * @ingroup tms570 + * + * @brief clock functions definitions. + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#include +#include +#include +#include +#include + +bool benchmark_timer_find_average_overhead = false; + +static uint32_t benchmark_timer_base; + +void benchmark_timer_initialize(void) +{ + benchmark_timer_base = _CPU_Counter_read(); +} + +uint32_t benchmark_timer_read(void) +{ + uint32_t delta = _CPU_Counter_read() - benchmark_timer_base; + + if (benchmark_timer_find_average_overhead) { + return delta; + } else { + /* TODO check on hardware */ + if (delta > 74) { + return delta - 74; + } else { + return 0; + } + } +} + +void benchmark_timer_disable_subtracting_average_overhead(bool find_average_overhead ) +{ + benchmark_timer_find_average_overhead = find_average_overhead; +} diff --git a/c/src/lib/libbsp/arm/tms570/clock/clock.c b/c/src/lib/libbsp/arm/tms570/clock/clock.c index 2a8bb5f..4dba949 100644 --- a/c/src/lib/libbsp/arm/tms570/clock/clock.c +++ b/c/src/lib/libbsp/arm/tms570/clock/clock.c @@ -29,6 +29,7 @@ #include #include #include +#include /** * holds HW counter value since last interrupt event @@ -49,6 +50,8 @@ static void tms570_clock_driver_support_initialize_hardware( void ) uint32_t microsec_per_tick = rtems_configuration_get_microseconds_per_tick(); + rtems_counter_initialize_converter(BSP_PLL_OUT_CLOCK); + /* Hardware specific initialize */ TMS570_RTI.RTIGCTRL = 0; TMS570_RTI.RTICPUC0 = BSP_PLL_OUT_CLOCK /1000000 / 2; /* prescaler */ @@ -80,7 +83,6 @@ static void tms570_clock_driver_support_at_tick( void ) { TMS570_RTI.RTIINTFLAG = 0x00000001; tms570_rti_last_tick_fcr0 = TMS570_RTI.RTICOMP0 - TMS570_RTI.RTIUDCP0; - /* TMS570_RTI.RTICOMP0 += 1000; */ } /** diff --git a/c/src/lib/libbsp/arm/tms570/include/system-clocks.h b/c/src/lib/libbsp/arm/tms570/include/system-clocks.h new file mode 100644 index 0000000..d441ec4 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/system-clocks.h @@ -0,0 +1,62 @@ +/** + * @file benchmark_timer.c + * + * @ingroup tms570 + * + * @brief System clocks. + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H +#define LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup tms570_clock System Clocks + * + * @ingroup tms570 + * + * @brief System clocks. + * + * @{ + */ + +/** + * @brief Returns current standard timer value in microseconds. + * + * This function uses RTI module free running counter 0 used + * which is used as system tick timebase as well. + */ +static inline unsigned tms570_timer(void) +{ + uint32_t actual_fcr0 = TMS570_RTI.RTIFRC0; + return actual_fcr0; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H */ diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg index eb4a65f..e90414a 100644 --- a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg @@ -8,7 +8,7 @@ RTEMS_CPU = arm CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian -CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +CFLAGS_OPTIMIZE_V = -O2 -ggdb BINEXT?=.bin # This defines the operations performed on the linked executable. diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg index eb4a65f..e90414a 100644 --- a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg @@ -8,7 +8,7 @@ RTEMS_CPU = arm CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian -CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +CFLAGS_OPTIMIZE_V = -O2 -ggdb BINEXT?=.bin # This defines the operations performed on the linked executable. diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg index eb4a65f..e90414a 100644 --- a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg @@ -8,7 +8,7 @@ RTEMS_CPU = arm CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian -CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +CFLAGS_OPTIMIZE_V = -O2 -ggdb BINEXT?=.bin # This defines the operations performed on the linked executable. diff --git a/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c b/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c new file mode 100644 index 0000000..f25380c --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c @@ -0,0 +1,44 @@ +/** + * @file + * + * @ingroup tms570_clocks + * + * @brief System clocks. + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#include +#include + + +/** + * @brief returns the actual value of Cortex-R cycle counter register + * + * The register is incremented at each core clock period + * + * @retval x actual core clock counter value + * + */ +CPU_Counter_ticks _CPU_Counter_read(void) +{ + uint32_t ticks; + asm volatile ("mrc p15, 0, %0, c9, c13, 0\n": "=r" (ticks)); + return ticks; +} diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am b/c/src/lib/libbsp/arm/tms570/preinstall.am index 81dbad1..d7ac628 100644 --- a/c/src/lib/libbsp/arm/tms570/preinstall.am +++ b/c/src/lib/libbsp/arm/tms570/preinstall.am @@ -109,6 +109,10 @@ $(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h: include/tms570-sci-driver.h $(PROJEC $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h +$(PROJECT_INCLUDE)/bsp/system-clocks.h: include/system-clocks.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/system-clocks.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/system-clocks.h + $(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h From joel at rtems.org Thu Aug 21 15:47:33 2014 From: joel at rtems.org (Joel Sherrill) Date: Thu, 21 Aug 2014 10:47:33 -0500 Subject: [rtems commit] bsp/tms570: disable huge memory demanding tests for internal RAM build variant. Message-ID: <20140821154733.988F37006BA@git.rtems.org> Module: rtems Branch: master Commit: 66f1ca64c8eda561bc16cb14bd097f4c0778127b Changeset: http://git.rtems.org/rtems/commit/?id=66f1ca64c8eda561bc16cb14bd097f4c0778127b Author: Pavel Pisa Date: Thu Aug 21 09:57:47 2014 -0500 bsp/tms570: disable huge memory demanding tests for internal RAM build variant. BSP completes build with tests and debug enabled for all three variants now tms570ls3137_hdk tms570ls3137_hdk_intram tms570ls3137_hdk_sdram Even that all enabled tests builds for internal RAM variant, many of them are expected to fail on hardware because whole tests including code, data and runtime work area demands has to fit into 256 kB of RAM. --- .../make/custom/tms570ls3137_hdk-testsuite.tcfg | 13 ----------- .../custom/tms570ls3137_hdk_intram-testsuite.tcfg | 23 ++++++++++++++++++++ 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg index 6f722bc..b79994e 100644 --- a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg @@ -4,16 +4,3 @@ # Format is one line per test that is _NOT_ built. # -flashdisk01 -utf8proc01 -spstkalloc02 -fsdosfsname01 -jffs2_fserror -jffs2_fslink -jffs2_fspatheval -jffs2_fspermission -jffs2_fsrdwr -jffs2_fssymlink -jffs2_fstime -pppd -mghttpd01 diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram-testsuite.tcfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram-testsuite.tcfg new file mode 100644 index 0000000..f4f00e8 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram-testsuite.tcfg @@ -0,0 +1,23 @@ +# +# tms570ls3137 RTEMS Test Database. +# +# Format is one line per test that is _NOT_ built. +# + +fileio +iostream +pppd +loopback +syscall01 +utf8proc01 +monitor02 +mghttpd01 +ftp01 +fsdosfsname01 +jffs2_fserror +jffs2_fslink +jffs2_fspatheval +jffs2_fspermission +jffs2_fsrdwr +jffs2_fssymlink +jffs2_fstime From sebh at rtems.org Fri Aug 22 09:40:39 2014 From: sebh at rtems.org (Sebastian Huber) Date: Fri, 22 Aug 2014 04:40:39 -0500 Subject: [rtems commit] libchip/dwmac: Make PHY address user configurable Message-ID: <20140822094039.4169C7006BA@git.rtems.org> Module: rtems Branch: master Commit: d5f543296737df9b9410fccca4b7105679d0e17a Changeset: http://git.rtems.org/rtems/commit/?id=d5f543296737df9b9410fccca4b7105679d0e17a Author: Christian Mauderer Date: Fri Aug 22 08:53:10 2014 +0200 libchip/dwmac: Make PHY address user configurable This patch allows the user to configure the PHY address for the DWMAC driver by giving a pointer to a dwmac_user_cfg structure to network stack via rtems_bsdnet_ifconfig::drv_ctrl. --- c/src/lib/libbsp/arm/altera-cyclone-v/README | 28 +++++++++++++++++++++++ c/src/libchip/network/dwmac-common.h | 1 + c/src/libchip/network/dwmac.c | 31 ++++++++++++++++---------- c/src/libchip/network/dwmac.h | 10 ++++++++ 4 files changed, 58 insertions(+), 12 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/README b/c/src/lib/libbsp/arm/altera-cyclone-v/README index 0a5bc05..658fe77 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/README +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/README @@ -14,3 +14,31 @@ have to set the following options: Additional there has to be one free file descriptor to access the i2c. Set the CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS accordingly. + +Network +------- +The default PHY address can be overwritten by the application. To do this, the +drv_ctrl pointer of the rtems_bsdnet_ifconfig structure should point to a +dwmac_ifconfig_drv_ctrl object with the appropriate settings before the +rtems_bsdnet_initialize_network() is called. E.g.: + + #include + #include + + static dwmac_ifconfig_drv_ctrl drv_ctrl = { + .phy_addr = 1 + }; + + ... + + static struct rtems_bsdnet_ifconfig some_ifconfig = { + .name = RTEMS_BSP_NETWORK_DRIVER_NAME, + .attach = RTEMS_BSP_NETWORK_DRIVER_ATTACH, + .drv_ctrl = &drv_ctrl + }; + + ... + + rtems_bsdnet_initialize_network(); + +If drv_ctrl is the NULL pointer, default values will be used instead. diff --git a/c/src/libchip/network/dwmac-common.h b/c/src/libchip/network/dwmac-common.h index b61b833..05bf941 100644 --- a/c/src/libchip/network/dwmac-common.h +++ b/c/src/libchip/network/dwmac-common.h @@ -227,6 +227,7 @@ typedef struct { struct mbuf **mbuf_addr_rx; struct mbuf **mbuf_addr_tx; const dwmac_cfg *CFG; + int MDIO_BUS_ADDR; } dwmac_common_context; struct dwmac_common_core_ops { diff --git a/c/src/libchip/network/dwmac.c b/c/src/libchip/network/dwmac.c index 20d87dc..ddcf365 100644 --- a/c/src/libchip/network/dwmac.c +++ b/c/src/libchip/network/dwmac.c @@ -131,7 +131,7 @@ static int dwmac_if_mdio_read( if ( phy == -1 ) { reg_value = MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET( reg_value, - self->CFG->MDIO_BUS_ADDR + self->MDIO_BUS_ADDR ); } else { reg_value = MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET( @@ -187,7 +187,7 @@ static int dwmac_if_mdio_write( if ( phy == -1 ) { reg_value = MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET( reg_value, - self->CFG->MDIO_BUS_ADDR + self->MDIO_BUS_ADDR ); } else { reg_value = MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET( @@ -347,7 +347,7 @@ static int dwmac_if_interface_stats( void *arg ) volatile macgrp *macgrp = self->macgrp; int media = 0; bool media_ok = dwmac_if_media_status( - self, &media, self->CFG->MDIO_BUS_ADDR ); + self, &media, self->MDIO_BUS_ADDR ); uint32_t oui; uint8_t model; uint8_t revision; @@ -364,7 +364,7 @@ static int dwmac_if_interface_stats( void *arg ) printf( "\n" ); eno = dwmac_get_phy_info( self, - self->CFG->MDIO_BUS_ADDR, + self->MDIO_BUS_ADDR, &oui, &model, &revision ); @@ -372,7 +372,7 @@ static int dwmac_if_interface_stats( void *arg ) if ( eno == 0 ) { printf( "PHY 0x%02x: OUI = 0x%04" PRIX32 ", Model = 0x%02" PRIX8 ", Rev = " "0x%02" PRIX8 "\n", - self->CFG->MDIO_BUS_ADDR, + self->MDIO_BUS_ADDR, oui, model, revision ); @@ -387,7 +387,7 @@ static int dwmac_if_interface_stats( void *arg ) ); } } else { - printf( "PHY %d communication error\n", self->CFG->MDIO_BUS_ADDR ); + printf( "PHY %d communication error\n", self->MDIO_BUS_ADDR ); } printf( "\nHardware counters:\n" ); @@ -1250,7 +1250,7 @@ static int dwmac_update_autonegotiation_params( dwmac_common_context *self ) uint32_t value = self->macgrp->mac_configuration; int media = 0; bool media_ok = dwmac_if_media_status( - self, &media, self->CFG->MDIO_BUS_ADDR ); + self, &media, self->MDIO_BUS_ADDR ); if ( media_ok ) { @@ -2065,7 +2065,8 @@ static int dwmac_if_attach( const dwmac_callback_cfg *CALLBACK = &driver_config->CALLBACK; const dwmac_common_desc_ops *DESC_OPS = (const dwmac_common_desc_ops *) driver_config->DESC_OPS->ops; - + const dwmac_ifconfig_drv_ctrl *drv_ctrl = + (const dwmac_ifconfig_drv_ctrl *) bsd_config->drv_ctrl; assert( self != NULL ); assert( bsd_config != NULL ); @@ -2135,9 +2136,15 @@ static int dwmac_if_attach( } if ( eno == 0 ) { - assert( 32 >= driver_config->MDIO_BUS_ADDR ); + if ( drv_ctrl == NULL ) { + self->MDIO_BUS_ADDR = driver_config->MDIO_BUS_ADDR; + } else { + self->MDIO_BUS_ADDR = drv_ctrl->phy_addr; + } + + assert( 32 >= self->MDIO_BUS_ADDR ); - if ( 32 < driver_config->MDIO_BUS_ADDR ) { + if ( 32 < self->MDIO_BUS_ADDR ) { eno = EINVAL; } } @@ -2317,7 +2324,7 @@ int dwmac_if_read_from_phy( if ( arg != NULL ) { eno = dwmac_if_mdio_read( - self->CFG->MDIO_BUS_ADDR, + self->MDIO_BUS_ADDR, self, phy_reg, &value ); @@ -2341,7 +2348,7 @@ int dwmac_if_write_to_phy( if ( arg != NULL ) { eno = dwmac_if_mdio_write( - self->CFG->MDIO_BUS_ADDR, + self->MDIO_BUS_ADDR, self, phy_reg, val ); diff --git a/c/src/libchip/network/dwmac.h b/c/src/libchip/network/dwmac.h index 9ccf75a..8270988 100644 --- a/c/src/libchip/network/dwmac.h +++ b/c/src/libchip/network/dwmac.h @@ -31,6 +31,16 @@ extern "C" { #endif /* __cplusplus */ +/** @brief DWMAC user configuration structure. + * + * Gives the user the possibility to overwrite some configuration data by + * setting the drv_ctrl pointer of the @ref rtems_bsdnet_ifconfig structure to a + * object with this type. + */ +typedef struct { + int phy_addr; +} dwmac_ifconfig_drv_ctrl; + /** @brief PHY event. * * Data type to be used for PHY events and event sets. From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] smptests/smpcache01: Test the SMP cache manager Message-ID: <20140822110754.E4916700656@git.rtems.org> Module: rtems Branch: master Commit: 9a9ab85b45260be326d7a59f40c2d7363097eb10 Changeset: http://git.rtems.org/rtems/commit/?id=9a9ab85b45260be326d7a59f40c2d7363097eb10 Author: Daniel Cederman Date: Thu Jul 3 16:42:24 2014 +0200 smptests/smpcache01: Test the SMP cache manager Invokes SMP cache management routines under different scenarios. --- testsuites/smptests/Makefile.am | 1 + testsuites/smptests/configure.ac | 1 + testsuites/smptests/smpcache01/Makefile.am | 19 ++ testsuites/smptests/smpcache01/init.c | 291 +++++++++++++++++++++++++ testsuites/smptests/smpcache01/smpcache01.doc | 16 ++ testsuites/smptests/smpcache01/smpcache01.scn | 14 ++ 6 files changed, 342 insertions(+), 0 deletions(-) diff --git a/testsuites/smptests/Makefile.am b/testsuites/smptests/Makefile.am index a6e7209..1e72d43 100644 --- a/testsuites/smptests/Makefile.am +++ b/testsuites/smptests/Makefile.am @@ -11,6 +11,7 @@ SUBDIRS += smp08 SUBDIRS += smp09 SUBDIRS += smpaffinity01 SUBDIRS += smpatomic01 +SUBDIRS += smpcache01 SUBDIRS += smpfatal01 SUBDIRS += smpfatal02 SUBDIRS += smpfatal03 diff --git a/testsuites/smptests/configure.ac b/testsuites/smptests/configure.ac index d88b9a0..9b6d99b 100644 --- a/testsuites/smptests/configure.ac +++ b/testsuites/smptests/configure.ac @@ -66,6 +66,7 @@ smp08/Makefile smp09/Makefile smpaffinity01/Makefile smpatomic01/Makefile +smpcache01/Makefile smpfatal01/Makefile smpfatal02/Makefile smpfatal03/Makefile diff --git a/testsuites/smptests/smpcache01/Makefile.am b/testsuites/smptests/smpcache01/Makefile.am new file mode 100644 index 0000000..3b092bc --- /dev/null +++ b/testsuites/smptests/smpcache01/Makefile.am @@ -0,0 +1,19 @@ +rtems_tests_PROGRAMS = smpcache01 +smpcache01_SOURCES = init.c + +dist_rtems_tests_DATA = smpcache01.scn smpcache01.doc + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP at .cfg +include $(top_srcdir)/../automake/compile.am +include $(top_srcdir)/../automake/leaf.am + +AM_CPPFLAGS += -I$(top_srcdir)/../support/include + +LINK_OBJS = $(smpcache01_OBJECTS) +LINK_LIBS = $(smpcache01_LDLIBS) + +smpcache01$(EXEEXT): $(smpcache01_OBJECTS) $(smpcache01_DEPENDENCIES) + @rm -f smpcache01$(EXEEXT) + $(make-exe) + +include $(top_srcdir)/../automake/local.am diff --git a/testsuites/smptests/smpcache01/init.c b/testsuites/smptests/smpcache01/init.c new file mode 100644 index 0000000..dd2f9f1 --- /dev/null +++ b/testsuites/smptests/smpcache01/init.c @@ -0,0 +1,291 @@ +/* + * Copyright (c) 2014 Aeroflex Gaisler AB. All rights reserved. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include +#include +#include +#include +#include + +#include "tmacros.h" + +const char rtems_test_name[] = "SMPCACHE 1"; + +#define CPU_COUNT 32 + +#define WORKER_PRIORITY 100 + +typedef void (*Cache_manager_Function_ptr)(const void *d_addr, size_t n_bytes); + +void +_Cache_manager_Send_smp_msg( + const size_t setsize, + const cpu_set_t *set, + Cache_manager_Function_ptr func, + const void * addr, + size_t size + ); + +typedef struct { + SMP_barrier_Control barrier; + uint32_t count[CPU_COUNT]; +} test_context; + +static test_context ctx = { + .barrier = SMP_BARRIER_CONTROL_INITIALIZER, +}; + +static void test_cache_message( const void *d_addr, size_t n_bytes ) +{ + rtems_test_assert(n_bytes == 123); + rtems_test_assert(d_addr == 0); + + ctx.count[rtems_get_current_processor()]++; +} + +static void all_cache_manager_smp_functions( size_t set_size, + cpu_set_t *cpu_set ) +{ + rtems_cache_flush_multiple_data_lines_processor_set( 0, 10, set_size, + cpu_set ); + rtems_cache_invalidate_multiple_data_lines_processor_set( 0, 10, set_size, + cpu_set ); + rtems_cache_flush_entire_data_processor_set( set_size, cpu_set ); + rtems_cache_invalidate_entire_data_processor_set( set_size, cpu_set ); + rtems_cache_invalidate_entire_instruction(); + rtems_cache_invalidate_multiple_instruction_lines( 0, 10 ); +} + +static void standard_funcs_test( size_t set_size, cpu_set_t *cpu_set ) +{ + all_cache_manager_smp_functions( set_size, cpu_set ); +} + +static void standard_funcs_isrdisabled_test( size_t set_size, + cpu_set_t *cpu_set, SMP_barrier_State *bs ) +{ + ISR_Level isr_level; + + _ISR_Disable_without_giant( isr_level ); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + all_cache_manager_smp_functions( set_size, cpu_set ); + + _ISR_Enable_without_giant( isr_level ); +} + +static void standard_funcs_giant_taken_test( size_t set_size, + cpu_set_t *cpu_set, SMP_barrier_State *bs ) +{ + if ( rtems_get_current_processor() == 0) + _Giant_Acquire(); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + all_cache_manager_smp_functions( set_size, cpu_set ); + + if ( rtems_get_current_processor() == 0) + _Giant_Release(); +} + +static void test_func_test( size_t set_size, cpu_set_t *cpu_set, + SMP_barrier_State *bs ) +{ + ctx.count[rtems_get_current_processor()] = 0; + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + _Cache_manager_Send_smp_msg( set_size, cpu_set, test_cache_message, 0, 123 ); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + rtems_test_assert( ctx.count[rtems_get_current_processor()] == + rtems_get_processor_count() ); +} + +static void test_func_isrdisabled_test( size_t set_size, cpu_set_t *cpu_set, + SMP_barrier_State *bs ) +{ + ISR_Level isr_level; + + ctx.count[rtems_get_current_processor()] = 0; + _ISR_Disable_without_giant( isr_level ); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + _Cache_manager_Send_smp_msg( set_size, cpu_set, test_cache_message, 0, 123 ); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + rtems_test_assert( ctx.count[rtems_get_current_processor()] == + rtems_get_processor_count() ); + + _ISR_Enable_without_giant( isr_level ); +} + +static void test_func_giant_taken_test( size_t set_size, cpu_set_t *cpu_set, + SMP_barrier_State *bs ) +{ + ctx.count[rtems_get_current_processor()] = 0; + + if ( rtems_get_current_processor() == 0) + _Giant_Acquire(); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + _Cache_manager_Send_smp_msg( set_size, cpu_set, test_cache_message, 0, 123 ); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + rtems_test_assert( ctx.count[rtems_get_current_processor()] == + rtems_get_processor_count() ); + + if ( rtems_get_current_processor() == 0) + _Giant_Release(); +} + +static void cmlog( const char* str ) +{ + if ( rtems_get_current_processor() == 0 ) + printf( "%s", str ); +} + +static void all_tests( void ) +{ + uint32_t cpu_count = rtems_get_processor_count(); + size_t set_size = CPU_ALLOC_SIZE( rtems_get_processor_count() ); + cpu_set_t *cpu_set = CPU_ALLOC( rtems_get_processor_count() ); + SMP_barrier_State bs = SMP_BARRIER_STATE_INITIALIZER; + + /* Send message to all available CPUs */ + CPU_FILL_S( set_size, cpu_set ); + + /* Call all SMP cache manager functions */ + cmlog( "Calling all standard SMP cache functions\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + standard_funcs_test( set_size, cpu_set ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n"); + + /* Call all SMP cache manager functions with ISR disabled */ + cmlog( "Calling all standard SMP cache functions. With ISR disabled\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + standard_funcs_isrdisabled_test( set_size, cpu_set, &bs ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n" ); + + /* Call all SMP cache manager functions with core 0 holding the giant lock */ + cmlog( "Calling all standard SMP cache functions. With CPU0 holding " + "the giant lock\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + standard_funcs_giant_taken_test( set_size, cpu_set, &bs ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n"); + + /* Call a test function using SMP cache manager and verify that all + * cores invoke the function */ + cmlog( "Calling a test function using the SMP cache manager to " + "verify that all CPUs receive the SMP message\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + test_func_test( set_size, cpu_set, &bs ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n"); + + /* Call a test function using SMP cache manager and verify that all + * cores invoke the function. ISR disabled. */ + cmlog( "Calling a test function using the SMP cache manager to " + "verify that all CPUs receive the SMP message. With ISR disabled\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + test_func_isrdisabled_test( set_size, cpu_set, &bs ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n" ); + + /* Call a test function using SMP cache manager and verify that all + * cores invoke the function. Core 0 holding giant lock. */ + cmlog( "Calling a test function using the SMP cache manager to " + "verify that all CPUs receive the SMP message. With CPU0 " + "holding the giant lock\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + test_func_giant_taken_test( set_size, cpu_set, &bs ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n" ); + + /* Done. Free up memory. */ + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count); + CPU_FREE( cpu_set ); +} + +static void worker_task(rtems_task_argument arg) +{ + rtems_status_code sc; + + all_tests(); + + sc = rtems_task_suspend(RTEMS_SELF); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); +} + +static void test_smp_cache_manager( void ) +{ + rtems_status_code sc; + size_t worker_index; + uint32_t cpu_count = rtems_get_processor_count(); + + for (worker_index = 1; worker_index < cpu_count; ++worker_index) { + rtems_id worker_id; + + sc = rtems_task_create( + rtems_build_name('W', 'R', 'K', '0'+worker_index), + WORKER_PRIORITY, + RTEMS_MINIMUM_STACK_SIZE, + RTEMS_DEFAULT_MODES, + RTEMS_DEFAULT_ATTRIBUTES, + &worker_id + ); + rtems_test_assert( sc == RTEMS_SUCCESSFUL ); + + sc = rtems_task_start( worker_id, worker_task, 0 ); + rtems_test_assert( sc == RTEMS_SUCCESSFUL ); + } + + all_tests(); +} + + +static void Init(rtems_task_argument arg) +{ + TEST_BEGIN(); + + test_smp_cache_manager(); + + TEST_END(); + rtems_test_exit(0); +} + +#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER +#define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER + +#define CONFIGURE_SMP_APPLICATION + +#define CONFIGURE_SMP_MAXIMUM_PROCESSORS CPU_COUNT + +#define CONFIGURE_MAXIMUM_TASKS CPU_COUNT + +#define CONFIGURE_MAXIMUM_TIMERS 1 + +#define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION + +#define CONFIGURE_RTEMS_INIT_TASKS_TABLE + +#define CONFIGURE_INIT + +#include diff --git a/testsuites/smptests/smpcache01/smpcache01.doc b/testsuites/smptests/smpcache01/smpcache01.doc new file mode 100644 index 0000000..f6041b2 --- /dev/null +++ b/testsuites/smptests/smpcache01/smpcache01.doc @@ -0,0 +1,16 @@ +This file describes the directives and concepts tested by this test set. + +test set name: smpcache01 + +directives: + + - rtems_cache_flush_multiple_data_lines_processor_set + - rtems_cache_invalidate_multiple_data_lines_processor_set + - rtems_cache_flush_entire_data_processor_set + - rtems_cache_invalidate_entire_data_processor_set + - rtems_cache_invalidate_entire_instruction + - rtems_cache_invalidate_multiple_instruction_lines + +concepts: + + - Ensure that cache related SMP messages are delivered properly. diff --git a/testsuites/smptests/smpcache01/smpcache01.scn b/testsuites/smptests/smpcache01/smpcache01.scn new file mode 100644 index 0000000..5964d3e --- /dev/null +++ b/testsuites/smptests/smpcache01/smpcache01.scn @@ -0,0 +1,14 @@ +*** BEGIN OF TEST SMPCACHE 1 *** +Calling all standard SMP cache functions +Done! +Calling all standard SMP cache functions. With ISR disabled +Done! +Calling all standard SMP cache functions. With CPU0 holding the giant lock +Done! +Calling a test function using the SMP cache manager to verify that all CPUs receive the SMP message +Done! +Calling a test function using the SMP cache manager to verify that all CPUs receive the SMP message. With ISR disabled +Done! +Calling a test function using the SMP cache manager to verify that all CPUs receive the SMP message. With CPU0 holding the giant lock +Done! +*** END OF TEST SMPCACHE 1 *** From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] score: Rename SMP broadcast message function Message-ID: <20140822110754.D9FD17006FE@git.rtems.org> Module: rtems Branch: master Commit: aed38189be6503f51d2a4f7fb234ba578a3e227e Changeset: http://git.rtems.org/rtems/commit/?id=aed38189be6503f51d2a4f7fb234ba578a3e227e Author: Daniel Cederman Date: Tue Jul 8 11:35:14 2014 +0200 score: Rename SMP broadcast message function Change message type to unsigned long to match other SMP message functions. --- cpukit/score/include/rtems/score/smpimpl.h | 4 ++-- cpukit/score/src/smp.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cpukit/score/include/rtems/score/smpimpl.h b/cpukit/score/include/rtems/score/smpimpl.h index d49f88f..cbc6428 100644 --- a/cpukit/score/include/rtems/score/smpimpl.h +++ b/cpukit/score/include/rtems/score/smpimpl.h @@ -171,8 +171,8 @@ void _SMP_Send_message( uint32_t cpu_index, unsigned long message ); * * @param [in] message is message to send */ -void _SMP_Broadcast_message( - uint32_t message +void _SMP_Send_message_broadcast( + unsigned long message ); /** diff --git a/cpukit/score/src/smp.c b/cpukit/score/src/smp.c index 7140664..09246e3 100644 --- a/cpukit/score/src/smp.c +++ b/cpukit/score/src/smp.c @@ -162,7 +162,7 @@ void _SMP_Send_message( uint32_t cpu_index, unsigned long message ) _CPU_SMP_Send_interrupt( cpu_index ); } -void _SMP_Broadcast_message( uint32_t message ) +void _SMP_Send_message_broadcast( unsigned long message ) { uint32_t cpu_count = _SMP_Get_processor_count(); uint32_t cpu_index_self = _SMP_Get_current_processor(); From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] bsp/sparc: Flush only instruction cache Message-ID: <20140822110755.0D6FD7006BA@git.rtems.org> Module: rtems Branch: master Commit: 62f373fb57a7c3d6b4bc86f59f42169a84bddf06 Changeset: http://git.rtems.org/rtems/commit/?id=62f373fb57a7c3d6b4bc86f59f42169a84bddf06 Author: Daniel Cederman Date: Mon Aug 11 10:02:13 2014 +0200 bsp/sparc: Flush only instruction cache The flush instruction on LEON flushes both the data and the instruction cache. Flushing of just the instruction cache can be done by setting the "flush instruction cache" bit in the cache control register. --- c/src/lib/libbsp/sparc/leon3/include/cache_.h | 5 ++++- c/src/lib/libbsp/sparc/leon3/include/leon.h | 5 +++++ 2 files changed, 9 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/sparc/leon3/include/cache_.h b/c/src/lib/libbsp/sparc/leon3/include/cache_.h index 70c1e2c..c781367 100644 --- a/c/src/lib/libbsp/sparc/leon3/include/cache_.h +++ b/c/src/lib/libbsp/sparc/leon3/include/cache_.h @@ -134,7 +134,10 @@ static inline void _CPU_cache_unfreeze_data(void) static inline void _CPU_cache_invalidate_entire_instruction(void) { - __asm__ volatile ("flush"); + uint32_t cache_reg = leon3_get_cache_control_register(); + + cache_reg |= LEON3_REG_CACHE_CTRL_FI; + leon3_set_cache_control_register(cache_reg); } static inline void _CPU_cache_invalidate_instruction_range( diff --git a/c/src/lib/libbsp/sparc/leon3/include/leon.h b/c/src/lib/libbsp/sparc/leon3/include/leon.h index 1fc4e28..14cbc85 100644 --- a/c/src/lib/libbsp/sparc/leon3/include/leon.h +++ b/c/src/lib/libbsp/sparc/leon3/include/leon.h @@ -86,6 +86,11 @@ extern "C" { #define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ /* 0 = no function */ +/* + * The following defines the bits in the LEON Cache Control Register. + */ +#define LEON3_REG_CACHE_CTRL_FI 0x00200000 /* Flush instruction cache */ + /* LEON3 Interrupt Controller */ extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; /* LEON3 GP Timer */ From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] score/sparc: Add comment on icache flush after trap table update Message-ID: <20140822110755.1D0C2700656@git.rtems.org> Module: rtems Branch: master Commit: bba83e5191eaed493bd619a5458ac5f22501f59b Changeset: http://git.rtems.org/rtems/commit/?id=bba83e5191eaed493bd619a5458ac5f22501f59b Author: Daniel Cederman Date: Fri Jul 11 16:09:41 2014 +0200 score/sparc: Add comment on icache flush after trap table update Changes to the trap table might be missed by other cores. If the system state is up, the other cores can be notified using SMP messages that they need to flush their icache. If the up state has not been reached there is no need to notify other cores. They will do an automatic flush of the icache just after entering the up state, but before enabling interrupts. Cache invalidation is required for both single and multiprocessor systems. --- cpukit/score/cpu/sparc/cpu.c | 17 ++++++++++++++--- 1 files changed, 14 insertions(+), 3 deletions(-) diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c index c616de4..8941bca 100644 --- a/cpukit/score/cpu/sparc/cpu.c +++ b/cpukit/score/cpu/sparc/cpu.c @@ -210,10 +210,21 @@ void _CPU_ISR_install_raw_handler( (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); - /* need to flush icache after this !!! */ - + /* + * There is no instruction cache snooping, so we need to invalidate + * the instruction cache to make sure that the processor sees the + * changes to the trap table. This step is required on both single- + * and multiprocessor systems. + * + * In a SMP configuration a change to the trap table might be + * missed by other cores. If the system state is up, the other + * cores can be notified using SMP messages that they need to + * flush their icache. If the up state has not been reached + * there is no need to notify other cores. They will do an + * automatic flush of the icache just after entering the up + * state, but before enabling interrupts. + */ rtems_cache_invalidate_entire_instruction(); - } void _CPU_ISR_install_vector( From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] score: Add SMP support to the cache manager Message-ID: <20140822110755.1429A7006E4@git.rtems.org> Module: rtems Branch: master Commit: ddbc3f8d83678313ca61d2936e6efd50b3e044b0 Changeset: http://git.rtems.org/rtems/commit/?id=ddbc3f8d83678313ca61d2936e6efd50b3e044b0 Author: Daniel Cederman Date: Fri Jul 11 16:37:56 2014 +0200 score: Add SMP support to the cache manager Adds functions that allows the user to specify which cores that should perform the cache operation. SMP messages are sent to all the specified cores and the caller waits until all cores have acknowledged that they have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is defined the instruction cache invalidation function will perform the operation on all cores using the previous method. --- c/src/lib/libbsp/sparc/leon3/include/cache_.h | 2 + c/src/lib/libcpu/shared/src/cache_manager.c | 258 ++++++++++++++++++++++++- cpukit/rtems/include/rtems/rtems/cache.h | 82 ++++++++ cpukit/score/include/rtems/score/smpimpl.h | 19 ++ 4 files changed, 355 insertions(+), 6 deletions(-) diff --git a/c/src/lib/libbsp/sparc/leon3/include/cache_.h b/c/src/lib/libbsp/sparc/leon3/include/cache_.h index c781367..ced5b6d 100644 --- a/c/src/lib/libbsp/sparc/leon3/include/cache_.h +++ b/c/src/lib/libbsp/sparc/leon3/include/cache_.h @@ -26,6 +26,8 @@ extern "C" { #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS +#define CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING + #define CPU_INSTRUCTION_CACHE_ALIGNMENT 64 #define CPU_DATA_CACHE_ALIGNMENT 64 diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c index 420a013..7dd408f 100644 --- a/c/src/lib/libcpu/shared/src/cache_manager.c +++ b/c/src/lib/libcpu/shared/src/cache_manager.c @@ -37,6 +37,214 @@ #include #include "cache_.h" +#include +#include +#include +#include + +#if defined( RTEMS_SMP ) + +typedef void (*Cache_manager_Function_ptr)(const void *d_addr, size_t n_bytes); + +typedef struct { + Chain_Node Node; + Cache_manager_Function_ptr func; + const void *addr; + size_t size; + cpu_set_t *recipients; + size_t setsize; + Atomic_Ulong done; +} Cache_manager_SMP_node; + +typedef struct { + SMP_lock_Control Lock; + Chain_Control List; +} Cache_manager_SMP_control; + +static Cache_manager_SMP_control _Cache_manager_SMP_control = { + .Lock = SMP_LOCK_INITIALIZER("cachemgr"), + .List = CHAIN_INITIALIZER_EMPTY(_Cache_manager_SMP_control.List) +}; + +void +_SMP_Cache_manager_message_handler(void) +{ + SMP_lock_Context lock_context; + Cache_manager_SMP_node *node; + Cache_manager_SMP_node *next; + uint32_t cpu_self_idx; + + _SMP_lock_ISR_disable_and_acquire( &_Cache_manager_SMP_control.Lock, + &lock_context ); + cpu_self_idx = _SMP_Get_current_processor(); + + node = (Cache_manager_SMP_node*)_Chain_First( + &_Cache_manager_SMP_control.List ); + while ( !_Chain_Is_tail( &_Cache_manager_SMP_control.List, &node->Node ) ) { + next = (Cache_manager_SMP_node*)_Chain_Next( &node->Node ); + if ( CPU_ISSET_S ( cpu_self_idx, node->setsize, node->recipients ) ) { + CPU_CLR_S ( cpu_self_idx, node->setsize, node->recipients ); + + node->func( node->addr, node->size ); + + if ( CPU_COUNT_S( node->setsize, node->recipients ) == 0 ) { + _Chain_Extract_unprotected( &node->Node ); + _Atomic_Store_ulong( &node->done, 1, ATOMIC_ORDER_RELEASE ); + } + } + node = next; + } + + _SMP_lock_Release_and_ISR_enable( &_Cache_manager_SMP_control.Lock, + &lock_context ); +} + +#if defined(CPU_DATA_CACHE_ALIGNMENT) || \ + (defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) && \ + defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING)) + +static void +_Cache_manager_Process_cache_messages( void ) +{ + unsigned long message; + Per_CPU_Control *cpu_self; + ISR_Level isr_level; + + _ISR_Disable_without_giant( isr_level ); + + cpu_self = _Per_CPU_Get(); + + message = _Atomic_Load_ulong( &cpu_self->message, ATOMIC_ORDER_RELAXED ); + + if ( message & SMP_MESSAGE_CACHE_MANAGER ) { + if ( _Atomic_Compare_exchange_ulong( &cpu_self->message, &message, + message & ~SMP_MESSAGE_CACHE_MANAGER, ATOMIC_ORDER_RELAXED, + ATOMIC_ORDER_RELAXED ) ) { + _SMP_Cache_manager_message_handler(); + } + } + + _ISR_Enable_without_giant( isr_level ); +} + +/* + * We can not make this function static as we need to access it + * from the test program. + */ +void +_Cache_manager_Send_smp_msg( + const size_t setsize, + const cpu_set_t *set, + Cache_manager_Function_ptr func, + const void * addr, + size_t size + ); + +void +_Cache_manager_Send_smp_msg( + const size_t setsize, + const cpu_set_t *set, + Cache_manager_Function_ptr func, + const void * addr, + size_t size + ) +{ + uint32_t i; + Cache_manager_SMP_node node; + size_t set_size = CPU_ALLOC_SIZE( _SMP_Get_processor_count() ); + char cpu_set_copy[set_size]; + SMP_lock_Context lock_context; + + if ( ! _System_state_Is_up( _System_state_Get() ) ) { + func( addr, size ); + return; + } + + memset( cpu_set_copy, 0, set_size ); + if( set == NULL ) { + for( i=0; i<_SMP_Get_processor_count(); ++i ) + CPU_SET_S( i, set_size, (cpu_set_t *)cpu_set_copy ); + } else { + for( i=0; i<_SMP_Get_processor_count(); ++i ) + if( CPU_ISSET_S( i, set_size, set ) ) + CPU_SET_S( i, set_size, (cpu_set_t *)cpu_set_copy ); + } + + node.func = func; + node.addr = addr; + node.size = size; + node.setsize = set_size; + node.recipients = (cpu_set_t *)cpu_set_copy; + _Atomic_Store_ulong( &node.done, 0, ATOMIC_ORDER_RELAXED ); + + + _SMP_lock_ISR_disable_and_acquire( &_Cache_manager_SMP_control.Lock, + &lock_context ); + _Chain_Prepend_unprotected( &_Cache_manager_SMP_control.List, &node.Node ); + _SMP_lock_Release_and_ISR_enable( &_Cache_manager_SMP_control.Lock, + &lock_context ); + + _SMP_Send_message_multicast( set_size, node.recipients, + SMP_MESSAGE_CACHE_MANAGER ); + + _Cache_manager_Process_cache_messages(); + + while ( !_Atomic_Load_uint( &node.done, ATOMIC_ORDER_ACQUIRE ) ); +} +#endif + +void +rtems_cache_flush_multiple_data_lines_processor_set( + const void *addr, + size_t size, + const size_t setsize, + const cpu_set_t *set +) +{ +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _Cache_manager_Send_smp_msg( setsize, set, + rtems_cache_flush_multiple_data_lines, addr, size ); +#endif +} + +void +rtems_cache_invalidate_multiple_data_lines_processor_set( + const void *addr, + size_t size, + const size_t setsize, + const cpu_set_t *set +) +{ +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _Cache_manager_Send_smp_msg( setsize, set, + rtems_cache_invalidate_multiple_data_lines, addr, size ); +#endif +} + +void +rtems_cache_flush_entire_data_processor_set( + const size_t setsize, + const cpu_set_t *set +) +{ +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _Cache_manager_Send_smp_msg( setsize, set, + (Cache_manager_Function_ptr)rtems_cache_flush_entire_data, 0, 0 ); +#endif +} + +void +rtems_cache_invalidate_entire_data_processor_set( + const size_t setsize, + const cpu_set_t *set +) +{ +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _Cache_manager_Send_smp_msg( setsize, set, + (Cache_manager_Function_ptr)rtems_cache_invalidate_entire_data, 0, 0 ); +#endif +} +#endif /* * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE @@ -219,18 +427,21 @@ rtems_cache_disable_data( void ) * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE */ + + /* * This function is responsible for performing an instruction cache * invalidate. It must determine how many cache lines need to be invalidated * and then perform the invalidations. */ -void -rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n_bytes ) + +#if !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) +static void +_invalidate_multiple_instruction_lines_no_range_functions( + const void * i_addr, + size_t n_bytes +) { -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) -#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) - _CPU_cache_invalidate_instruction_range( i_addr, n_bytes ); -#else const void * final_address; /* @@ -249,6 +460,35 @@ rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n _CPU_cache_invalidate_1_instruction_line( i_addr ); i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT); } +} +#endif + +void +rtems_cache_invalidate_multiple_instruction_lines( + const void * i_addr, + size_t n_bytes +) +{ +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) +#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) + +#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) + _Cache_manager_Send_smp_msg( 0, 0, _CPU_cache_invalidate_instruction_range, + i_addr, n_bytes ); +#else + _CPU_cache_invalidate_instruction_range( i_addr, n_bytes ); +#endif + +#else + +#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) + _Cache_manager_Send_smp_msg( 0, 0, + _invalidate_multiple_instruction_lines_no_range_functions, i_addr, + n_bytes ); +#else + _invalidate_multiple_instruction_lines_no_range_functions( i_addr, n_bytes ); +#endif + #endif #endif } @@ -266,8 +506,14 @@ rtems_cache_invalidate_entire_instruction( void ) * Call the CPU-specific routine */ +#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) + _Cache_manager_Send_smp_msg( 0, 0, + (Cache_manager_Function_ptr)_CPU_cache_invalidate_entire_instruction, + 0, 0 ); +#else _CPU_cache_invalidate_entire_instruction(); #endif +#endif } diff --git a/cpukit/rtems/include/rtems/rtems/cache.h b/cpukit/rtems/include/rtems/rtems/cache.h index 05f6612..ce399c6 100644 --- a/cpukit/rtems/include/rtems/rtems/cache.h +++ b/cpukit/rtems/include/rtems/rtems/cache.h @@ -113,6 +113,9 @@ void rtems_cache_invalidate_multiple_data_lines( * * The cache lines covering the area are marked as invalid. A later * instruction fetch from the area will result in a load from memory. + * In SMP mode, on processors without instruction cache snooping, this + * operation will invalidate the instruction cache lines on all processors. + * It should not be called from interrupt context in such case. * * @param[in] addr The start address of the area to invalidate. * @param[in] size The size in bytes of the area to invalidate. @@ -188,6 +191,85 @@ void rtems_cache_disable_instruction( void ); */ void *rtems_cache_aligned_malloc ( size_t nbytes ); +#if defined( RTEMS_SMP ) + +/** + * @brief Flushes multiple data cache lines for a set of processors + * + * Dirty cache lines covering the area are transferred to memory. + * Depending on the cache implementation this may mark the lines as invalid. + * + * This operation should not be called from interrupt context. + * + * @param[in] addr The start address of the area to flush. + * @param[in] size The size in bytes of the area to flush. + * @param[in] setsize The size of the processor set. + * @param[in] set The target processor set. + */ +void rtems_cache_flush_multiple_data_lines_processor_set( + const void *addr, + size_t size, + const size_t setsize, + const cpu_set_t *set +); + +/** + * @brief Invalidates multiple data cache lines for a set of processors + * + * The cache lines covering the area are marked as invalid. A later read + * access in the area will load the data from memory. + * + * In case the area is not aligned on cache line boundaries, then this + * operation may destroy unrelated data. + * + * This operation should not be called from interrupt context. + * + * @param[in] addr The start address of the area to invalidate. + * @param[in] size The size in bytes of the area to invalidate. + * @param[in] setsize The size of the processor set. + * @param[in] set The target processor set. + */ +void rtems_cache_invalidate_multiple_data_lines_processor_set( + const void *addr, + size_t size, + const size_t setsize, + const cpu_set_t *set +); + +/** + * @brief Flushes the entire data cache for a set of processors + * + * This operation should not be called from interrupt context. + * + * @see rtems_cache_flush_multiple_data_lines(). + * + * @param[in] setsize The size of the processor set. + * @param[in] set The target processor set. + */ +void rtems_cache_flush_entire_data_processor_set( + const size_t setsize, + const cpu_set_t *set +); + +/** + * @brief Invalidates the entire cache for a set of processors + * + * This function is responsible for performing a data cache + * invalidate. It invalidates the entire cache for a set of + * processors. + * + * This operation should not be called from interrupt context. + * + * @param[in] setsize The size of the processor set. + * @param[in] set The target processor set. + */ +void rtems_cache_invalidate_entire_data_processor_set( + const size_t setsize, + const cpu_set_t *set +); + +#endif + /**@}*/ #ifdef __cplusplus diff --git a/cpukit/score/include/rtems/score/smpimpl.h b/cpukit/score/include/rtems/score/smpimpl.h index cbc6428..dca8a6b 100644 --- a/cpukit/score/include/rtems/score/smpimpl.h +++ b/cpukit/score/include/rtems/score/smpimpl.h @@ -21,6 +21,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -51,6 +52,13 @@ extern "C" { #define SMP_MESSAGE_TEST 0x2UL /** + * @brief SMP message to request a cache manager invocation. + * + * @see _SMP_Send_message(). + */ +#define SMP_MESSAGE_CACHE_MANAGER 0x4UL + +/** * @brief SMP fatal codes. */ typedef enum { @@ -127,6 +135,12 @@ static inline void _SMP_Set_test_message_handler( } /** + * @brief Handles cache invalidation/flush requests from a remote processor. + * + */ +void _SMP_Cache_manager_message_handler( void ); + +/** * @brief Interrupt handler for inter-processor interrupts. */ static inline void _SMP_Inter_processor_interrupt_handler( void ) @@ -148,6 +162,11 @@ static inline void _SMP_Inter_processor_interrupt_handler( void ) if ( ( message & SMP_MESSAGE_TEST ) != 0 ) { ( *_SMP_Test_message_handler )( cpu_self ); } + + if ( ( message & SMP_MESSAGE_CACHE_MANAGER ) != 0 ) { + _SMP_Cache_manager_message_handler(); + } + } } From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] score: Add function to send a SMP message to a set of CPUs Message-ID: <20140822110754.9B5A47006E4@git.rtems.org> Module: rtems Branch: master Commit: a68cc1bb10e72504a6c4169c64eb1cfc1280da67 Changeset: http://git.rtems.org/rtems/commit/?id=a68cc1bb10e72504a6c4169c64eb1cfc1280da67 Author: Daniel Cederman Date: Tue Jul 8 11:33:55 2014 +0200 score: Add function to send a SMP message to a set of CPUs --- cpukit/score/include/rtems/score/smpimpl.h | 15 +++++++++++++++ cpukit/score/src/smp.c | 16 ++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/cpukit/score/include/rtems/score/smpimpl.h b/cpukit/score/include/rtems/score/smpimpl.h index e2fee39..d49f88f 100644 --- a/cpukit/score/include/rtems/score/smpimpl.h +++ b/cpukit/score/include/rtems/score/smpimpl.h @@ -175,6 +175,21 @@ void _SMP_Broadcast_message( uint32_t message ); +/** + * @brief Sends a SMP message to a set of processors. + * + * The sending processor may be part of the set. + * + * @param[in] setsize The size of the set of target processors of the message. + * @param[in] cpus The set of target processors of the message. + * @param[in] message The message. + */ +void _SMP_Send_message_multicast( + const size_t setsize, + const cpu_set_t *cpus, + unsigned long message +); + #endif /* defined( RTEMS_SMP ) */ /** diff --git a/cpukit/score/src/smp.c b/cpukit/score/src/smp.c index f0554fe..7140664 100644 --- a/cpukit/score/src/smp.c +++ b/cpukit/score/src/smp.c @@ -177,4 +177,20 @@ void _SMP_Broadcast_message( uint32_t message ) } } +void _SMP_Send_message_multicast( + const size_t setsize, + const cpu_set_t *cpus, + unsigned long message +) +{ + uint32_t cpu_count = _SMP_Get_processor_count(); + uint32_t cpu_index; + + for ( cpu_index = 0 ; cpu_index < cpu_count ; ++cpu_index ) { + if ( CPU_ISSET_S( cpu_index, setsize, cpus ) ) { + _SMP_Send_message( cpu_index, message ); + } + } +} + SMP_Test_message_handler _SMP_Test_message_handler; From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] bsp/sparc: Flush icache before first time enabling interrupts Message-ID: <20140822110754.A7804700656@git.rtems.org> Module: rtems Branch: master Commit: 54f3476e2493a957efb0e30c77226d496e7fc5a1 Changeset: http://git.rtems.org/rtems/commit/?id=54f3476e2493a957efb0e30c77226d496e7fc5a1 Author: Daniel Cederman Date: Thu Jul 3 11:18:55 2014 +0200 bsp/sparc: Flush icache before first time enabling interrupts A secondary processor might miss changes done to the trap table if the instruction cache is not flushed. Once interrupts are enabled any other required cache flushes can be ordered via the cache manager. --- c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c | 9 +++++++++ cpukit/score/cpu/sparc/rtems/score/cpu.h | 4 ++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c b/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c index 567eecc..9166ad5 100644 --- a/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c +++ b/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -80,3 +81,11 @@ void _CPU_SMP_Send_interrupt(uint32_t target_processor_index) /* send interrupt to destination CPU */ LEON3_IrqCtrl_Regs->force[target_processor_index] = 1 << LEON3_MP_IRQ; } + +void _BSP_Start_multitasking( + Context_Control *heir +) +{ + _CPU_cache_invalidate_entire_instruction(); + _CPU_Context_Restart_self( heir ); +} diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index 39b7825..9c38b55 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -1203,6 +1203,10 @@ register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + void _BSP_Start_multitasking( Context_Control *heir ) + RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + #define _CPU_Start_multitasking _BSP_Start_multitasking + static inline void _CPU_SMP_Processor_event_broadcast( void ) { __asm__ volatile ( "" : : : "memory" ); From joel at rtems.org Fri Aug 22 15:16:09 2014 From: joel at rtems.org (Joel Sherrill) Date: Fri, 22 Aug 2014 10:16:09 -0500 Subject: [rtems commit] bsp/tms570: implemented and tested initialization of Cortex-R performance counters. Message-ID: <20140822151610.0CAB27006BA@git.rtems.org> Module: rtems Branch: master Commit: d13ce7553b86a5b86fb360d8fc530ddd3ceef14a Changeset: http://git.rtems.org/rtems/commit/?id=d13ce7553b86a5b86fb360d8fc530ddd3ceef14a Author: Pavel Pisa Date: Fri Aug 22 10:20:46 2014 -0500 bsp/tms570: implemented and tested initialization of Cortex-R performance counters. The code is written as BSP specific now but it should work for all Cortex-A and R based CPUs and can be moved to ARM generic place in future. StackOverflow suggested sequences of writes to the registers required to start counters is used. http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor --- c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c | 88 ++++++++++++++++++++- 1 files changed, 84 insertions(+), 4 deletions(-) diff --git a/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c b/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c index f25380c..3ce2f63 100644 --- a/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c +++ b/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c @@ -3,7 +3,14 @@ * * @ingroup tms570_clocks * - * @brief System clocks. + * @brief Cortex-R performace counters + * + * The counters setup functions are these which has been suggested + * on StackOverflow + * + * Code is probably for use on Cortex-A without modifications as well. + * + * http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor */ /* @@ -14,9 +21,6 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others - * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.org/license/LICENSE. @@ -27,6 +31,79 @@ #include #include +static int cpu_counter_initialized; + + +/** + * @brief set mode of Cortex-R performance counters + * + * Based on example found on http://stackoverflow.com + * + * @param[in] do_reset if set, values of the counters are reset + * @param[in] enable_divider if set, CCNT counts clocks divided by 64 + * @retval Void + */ +static inline void _CPU_Counter_init_perfcounters( + int32_t do_reset, + int32_t enable_divider +) +{ + /* in general enable all counters (including cycle counter) */ + int32_t value = 1; + + /* peform reset */ + if (do_reset) + { + value |= 2; /* reset all counters to zero */ + value |= 4; /* reset cycle counter to zero */ + } + + if (enable_divider) + value |= 8; /* enable "by 64" divider for CCNT */ + + value |= 16; + + /* program the performance-counter control-register */ + asm volatile ("mcr p15, 0, %0, c9, c12, 0\t\n" :: "r"(value)); + + /* enable all counters */ + asm volatile ("mcr p15, 0, %0, c9, c12, 1\t\n" :: "r"(0x8000000f)); + + /* clear overflows */ + asm volatile ("mcr p15, 0, %0, c9, c12, 3\t\n" :: "r"(0x8000000f)); +} + +/** + * @brief initialize Cortex-R performance counters subsystem + * + * Based on example found on http://stackoverflow.com + * + * @retval Void + * + */ +static void _CPU_Counter_initialize(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + + if ( cpu_counter_initialized ) { + rtems_interrupt_enable(level); + return; + } + + /* enable user-mode access to the performance counter */ + asm volatile ("mcr p15, 0, %0, c9, c14, 0\n\t" :: "r"(1)); + + /* disable counter overflow interrupts (just in case) */ + asm volatile ("mcr p15, 0, %0, c9, c14, 2\n\t" :: "r"(0x8000000f)); + + _CPU_Counter_init_perfcounters(false, false); + + cpu_counter_initialized = 1; + + rtems_interrupt_enable(level); +} /** * @brief returns the actual value of Cortex-R cycle counter register @@ -39,6 +116,9 @@ CPU_Counter_ticks _CPU_Counter_read(void) { uint32_t ticks; + if ( !cpu_counter_initialized ) { + _CPU_Counter_initialize(); + } asm volatile ("mrc p15, 0, %0, c9, c13, 0\n": "=r" (ticks)); return ticks; } From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Add printers to stage. Message-ID: <20140824234534.43ED2700A5D@git.rtems.org> Module: rtems-tools Branch: master Commit: a785e254f2360e946baa14a11fbd3f403047b880 Changeset: http://git.rtems.org/rtems-tools/commit/?id=a785e254f2360e946baa14a11fbd3f403047b880 Author: Dhananjay Balan Date: Fri Jul 12 19:25:46 2013 +0530 Add printers to stage. --- tools/gdb/python/classic_printer.py | 62 +++++++++++++++ tools/gdb/python/supercore.py | 24 ++++++ tools/gdb/python/supercore_printer.py | 140 +++++++++++++++++++++++++++++++++ 3 files changed, 226 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/classic_printer.py b/tools/gdb/python/classic_printer.py new file mode 100644 index 0000000..e9d7cb8 --- /dev/null +++ b/tools/gdb/python/classic_printer.py @@ -0,0 +1,62 @@ +# +# RTEMS Classic pretty printers for GDB +# + +class attribute_printer: + + def __init__(self, attribute): + ''' ToDo: Verify - usage of all ''' + self.attr = classic.attribute(attribute,'all') + + def to_string(self): + return gdb.Value(self.attr.to_string()) + +class semaphore_printer: + """WIP: Print a Semaphore_Control object. Print using the struct display hint + and an iterator. """ + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, semaphore): + self.semaphore = semaphore + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return self.semaphore['Object'] + elif self.count == 2: + attr = attribute(self.semaphore['attribute_set'], + 'semaphore') + return attr.to_string() + elif self.count == 3: + return self.semaphore['Core_control'] + raise StopIteration + + def __init__(self, semaphore): + self.semaphore = semaphore + + def to_string(self): + return '' + + @staticmethod + def key(i): + if i == 0: + return 'Object' + elif i == 1: + return 'attribute_set' + elif i == 2: + return 'Core_control' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.semaphore)) + + def display_hint (self): + return 'struct' diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py new file mode 100644 index 0000000..4378e12 --- /dev/null +++ b/tools/gdb/python/supercore.py @@ -0,0 +1,24 @@ +# +# RTEMS Supercore Objects +# + +import threads + +# ToDo: Move this to helper. +def tasks_printer_rotuine(wait_queue): + tasks = wait_queue.tasks() + print ' Queue: len = %d, state = %s' % (len(tasks),wait_queue.state()) + for t in range(0, len(tasks)): + print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) + +class CORE_message_queue: + '''Manage a Supercore message_queue''' + + def __init__(self, message_queue): + self.queue = message_queue + self.wait_queue = threads.queue(self.queue['Wait_queue']) + # ToDo: self.attribute ='' + # self.buffer + + def show(self): + tasks_printer_rotuine(self.wait_queue) diff --git a/tools/gdb/python/supercore_printer.py b/tools/gdb/python/supercore_printer.py new file mode 100644 index 0000000..cee9097 --- /dev/null +++ b/tools/gdb/python/supercore_printer.py @@ -0,0 +1,140 @@ +# +# RTEMS Supercore pretty printers for GDB +# +import objects +import itertools + +class id_printer: + """Print an object given the ID. Print using the struct display hint and an + iterator.""" + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, id): + self.id = id + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return int(self.id.value()) + elif self.count == 2: + return self.id.node() + elif self.count == 3: + return self.id.api() + elif self.count == 4: + return self.id._class() + elif self.count == 5: + return self.id.index() + raise StopIteration + + def __init__(self, id): + self.id = objects.ident(id) + + def to_string(self): + return '' + + @staticmethod + def key(i): + if i == 0: + return 'id' + elif i == 1: + return 'node' + elif i == 2: + return 'api' + elif i == 3: + return 'class' + elif i == 4: + return 'index' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.id)) + + def display_hint (self): + return 'struct' + +class name_printer: + """Pretty printer for an object's name. It has to guess the type as no + information is available to help determine it.""" + + def __init__(self, nameval): + self.name = objects.name(nameval) + + def to_string(self): + return str(self.name) + +class control_printer: + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, object): + self.object = object + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return self.object.node() + elif self.count == 2: + return self.object.id() + elif self.count == 3: + return self.object.name() + raise StopIteration + + def to_string(self): + return '' + + def __init__(self, object): + self.object = objects.control(object) + + @staticmethod + def key(i): + if i == 0: + return 'Node' + elif i == 1: + return 'id' + elif i == 2: + return 'name' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.object)) + + def display_hint (self): + return 'struct' + + +class state_printer: + + def __init__(self, state): + self.state = threads.state(state) + def to_string(self): + return self.state.to_string() + +class chains_printer: + + def __init__(self,chain): + self.chain = chains.control(chain) + + def to_string(self): + return "First:"+str(self.chain.first())+"\n Last:"+str(self.chain.last()) + +class node_printer: + def __init__(self, node): + self.node = chains.node(node) + + def to_string(self): + return "Node: "+str(self.node)+" Next: "+str(self.node.next())+" Prev: "+str(self.node.previous()) \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Heavy refactoring + Improved mesege queu printing. Message-ID: <20140824234534.B146B700A5B@git.rtems.org> Module: rtems-tools Branch: master Commit: b061a67742d58bedaa161970c5cae028aa440e1f Changeset: http://git.rtems.org/rtems-tools/commit/?id=b061a67742d58bedaa161970c5cae028aa440e1f Author: Dhananjay Balan Date: Fri Jul 12 19:22:37 2013 +0530 Heavy refactoring + Improved mesege queu printing. - pretty printers moved to the corresponding api_printer module - object abstractions moved to - their own name for core modules - supercore for other supercore objects - classic for classic api objects --- tools/gdb/python/__init__.py | 9 ++++++ tools/gdb/python/chains.py | 5 ++- tools/gdb/python/classic.py | 64 ++++-------------------------------------- tools/gdb/python/objects.py | 63 ----------------------------------------- tools/gdb/python/rtems.py | 18 +++++++---- tools/gdb/python/threads.py | 12 -------- 6 files changed, 30 insertions(+), 141 deletions(-) diff --git a/tools/gdb/python/__init__.py b/tools/gdb/python/__init__.py index 0664d21..dd55529 100644 --- a/tools/gdb/python/__init__.py +++ b/tools/gdb/python/__init__.py @@ -3,14 +3,23 @@ if __name__ == "__main__": import sys import os.path sys.path.append(os.path.dirname(__file__)) + import supercore import chains import rtems import classic import objects import threads + + import supercore_printer + import classic_printer + + # Needed to reload code inside gdb source command + reload(supercore) reload(chains) reload(rtems) reload(classic) reload(objects) reload(threads) + reload(supercore_printer) + reload(classic_printer) print 'RTEMS GDB Support loaded' diff --git a/tools/gdb/python/chains.py b/tools/gdb/python/chains.py index d691822..0826ba9 100644 --- a/tools/gdb/python/chains.py +++ b/tools/gdb/python/chains.py @@ -32,6 +32,8 @@ class node: return self.node_val.cast(nodetype) return None + def to_string(self): + return self.node_val['next'] + "Prev: "+self.node_val['previous'] class control: """Manage the Chain_Control.""" @@ -44,4 +46,5 @@ class control: return t def last(self): - return node(self.ctrl['first']) + return node(self.ctrl['Tail']['Node']) + diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index d3f624d..e82078d 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -11,6 +11,7 @@ import re import objects import threads +import supercore class attribute: """The Classic API attribute.""" @@ -98,63 +99,6 @@ class attribute: return True return False -class attribute_printer: - - def __init__(self, attr): - self.attr = attribute(attr,'all') - - def to_string(self): - return gdb.Value(self.attr.to_string()) - -class semaphore_printer: - """Print a Semaphore_Control object. Print using the struct display hint - and an iterator.""" - - class iterator: - """Use an iterator for each field expanded from the id so GDB output - is formatted correctly.""" - - def __init__(self, semaphore): - self.semaphore = semaphore - self.count = 0 - - def __iter__(self): - return self - - def next(self): - self.count += 1 - if self.count == 1: - return self.semaphore['Object'] - elif self.count == 2: - attr = attribute(self.semaphore['attribute_set'], - 'semaphore') - return attr.to_string() - elif self.count == 3: - return self.semaphore['Core_control'] - raise StopIteration - - def __init__(self, semaphore): - self.semaphore = semaphore - - def to_string(self): - return '' - - @staticmethod - def key(i): - if i == 0: - return 'Object' - elif i == 1: - return 'attribute_set' - elif i == 2: - return 'Core_control' - return 'bad' - - def children(self): - counter = itertools.imap (self.key, itertools.count()) - return itertools.izip (counter, self.iterator(self.semaphore)) - - def display_hint (self): - return 'struct' class semaphore: "Print a classic semaphore." @@ -225,9 +169,13 @@ class message_queue: self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], \ 'message_queue') + self.wait_queue = threads.queue( \ + self.object['message_queue']['Wait_queue']) + + self.core_control = supercore.CORE_message_queue(self.object['message_queue']) def show(self, from_tty): print ' Name:', self.object_control.name() print ' Attr:', self.attr.to_string() - + self.core_control.show() \ No newline at end of file diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 25353d7..d2ba216 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -247,71 +247,8 @@ class control: is_string = information.is_string(self._id.api(), self._id._class()) return str(name(self.object['name'], is_string)) -class id_printer: - """Print an object given the ID. Print using the struct display hint and an - iterator.""" - class iterator: - """Use an iterator for each field expanded from the id so GDB output - is formatted correctly.""" - - def __init__(self, id): - self.id = id - self.count = 0 - def __iter__(self): - return self - - def next(self): - self.count += 1 - if self.count == 1: - return int(self.id.value()) - elif self.count == 2: - return self.id.node() - elif self.count == 3: - return self.id.api() - elif self.count == 4: - return self.id._class() - elif self.count == 5: - return self.id.index() - raise StopIteration - - def __init__(self, id): - self.id = ident(id) - - def to_string(self): - return '' - - @staticmethod - def key(i): - if i == 0: - return 'id' - elif i == 1: - return 'node' - elif i == 2: - return 'api' - elif i == 3: - return 'class' - elif i == 4: - return 'index' - return 'bad' - - def children(self): - counter = itertools.imap (self.key, itertools.count()) - return itertools.izip (counter, self.iterator(self.id)) - - def display_hint (self): - return 'struct' - -class name_printer: - """Pretty printer for an object's name. It has to guess the type as no - information is available to help determine it.""" - - def __init__(self, nameval): - self.name = name(nameval) - - def to_string(self): - return gdb.Value(str(self.name)) class control_printer: diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 398f4e5..d530e6e 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -12,6 +12,10 @@ import objects import threads import classic +# ToDo: Move every printing out +import supercore_printer +import classic_printer + nesting = 0 def type_from_value(val): @@ -50,13 +54,13 @@ def lookup_function (val): return None def build_rtems_dict(): - pp_dict[re.compile('^rtems_id$')] = lambda val: objects.id_printer(val) - pp_dict[re.compile('^Objects_Id$')] = lambda val: objects.id_printer(val) - pp_dict[re.compile('^Objects_Name$')] = lambda val: objects.name_printer(val) - pp_dict[re.compile('^Objects_Control$')] = lambda val: objects.control_printer(val) - pp_dict[re.compile('^States_Control$')] = lambda val: threads.state_printer(val) - pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic.attribute_printer(val) - pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic.semaphore_printer(val) + pp_dict[re.compile('^rtems_id$')] = lambda val: supercore_printer.id_printer(val) + pp_dict[re.compile('^Objects_Id$')] = lambda val: supercore_printer.id_printer(val) + pp_dict[re.compile('^Objects_Name$')] = lambda val: supercore_printer.name_printer(val) + pp_dict[re.compile('^Objects_Control$')] = lambda val: supercore_printer.control_printer(val) + pp_dict[re.compile('^States_Control$')] = lambda val: supercore_printer.state_printer(val) + pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic_printer.attribute_printer(val) + pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic_printer.semaphore_printer(val) class rtems(gdb.Command): """Prefix command for RTEMS.""" diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py index 3debbe7..b5ac3fb 100644 --- a/tools/gdb/python/threads.py +++ b/tools/gdb/python/threads.py @@ -191,17 +191,5 @@ class queue: self.que['Queues']['Priority'][ph]))) return t - def to_string(self): - if self.fifo(): - s = 'fifo' - else: - s = 'priority' - return -class state_printer: - def __init__(self, s): - self.s = state(s) - - def to_string(self): - return self.s.to_string() From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Update readme. Message-ID: <20140824234534.C9438700A89@git.rtems.org> Module: rtems-tools Branch: master Commit: 6e75f4ebf5450154231a1f7c1c2ba97e60d2c074 Changeset: http://git.rtems.org/rtems-tools/commit/?id=6e75f4ebf5450154231a1f7c1c2ba97e60d2c074 Author: Dhananjay Balan Date: Tue Jul 9 22:39:27 2013 +0530 Update readme. Included useage instructions. --- tools/gdb/python/README.md | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 567c195..8858a4f 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -2,3 +2,5 @@ rtems-gdb ========= GDB extenstions to RTEMS. + +See [this blog post for instructions](http://dbalan.github.io/blog/2013/06/23/debugging-rtems-with-gdb/) From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Fix typo: Global timer control object name. Message-ID: <20140824234534.BE671700A25@git.rtems.org> Module: rtems-tools Branch: master Commit: 591fbf65d31d167dcab31138fc5b4da0ad5b40e6 Changeset: http://git.rtems.org/rtems-tools/commit/?id=591fbf65d31d167dcab31138fc5b4da0ad5b40e6 Author: Dhananjay Balan Date: Tue Jul 16 18:35:03 2013 +0530 Fix typo: Global timer control object name. --- tools/gdb/python/objects.py | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 23ea7be..c433039 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -14,7 +14,7 @@ class infotables: tables_types = { 'classic/tasks' : ('Thread_Control', '_RTEMS_tasks_Information'), - 'classic/timers' : ('Timer_Control', '_Timers_Information'), + 'classic/timers' : ('Timer_Control', '_Timer_Information'), 'classic/semaphores' : ('Semaphore_Control', '_Semaphore_Information'), 'classic/message_queues' : ('Message_queue_Control', '_Message_queue_Information'), 'classic/partitions' : ('Partition_Control', '_Partition_Information'), From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Initial commit Message-ID: <20140824234534.EDD0D700812@git.rtems.org> Module: rtems-tools Branch: master Commit: 911e71038cee3bcf3b9fa60a415dbda824bc3a80 Changeset: http://git.rtems.org/rtems-tools/commit/?id=911e71038cee3bcf3b9fa60a415dbda824bc3a80 Author: Dhananjay Balan Date: Mon Jun 17 08:31:09 2013 -0700 Initial commit --- tools/gdb/python/.gitignore | 35 +++++++++++++++++++++++++++++++++++ tools/gdb/python/README.md | 4 ++++ 2 files changed, 39 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/.gitignore b/tools/gdb/python/.gitignore new file mode 100644 index 0000000..d2d6f36 --- /dev/null +++ b/tools/gdb/python/.gitignore @@ -0,0 +1,35 @@ +*.py[cod] + +# C extensions +*.so + +# Packages +*.egg +*.egg-info +dist +build +eggs +parts +bin +var +sdist +develop-eggs +.installed.cfg +lib +lib64 + +# Installer logs +pip-log.txt + +# Unit test / coverage reports +.coverage +.tox +nosetests.xml + +# Translations +*.mo + +# Mr Developer +.mr.developer.cfg +.project +.pydevproject diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md new file mode 100644 index 0000000..567c195 --- /dev/null +++ b/tools/gdb/python/README.md @@ -0,0 +1,4 @@ +rtems-gdb +========= + +GDB extenstions to RTEMS. From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Fix pretty printers Message-ID: <20140824234535.21F1F700812@git.rtems.org> Module: rtems-tools Branch: master Commit: 385640641ef618061cc0d26f711a54bf95661124 Changeset: http://git.rtems.org/rtems-tools/commit/?id=385640641ef618061cc0d26f711a54bf95661124 Author: Dhananjay Balan Date: Tue Jul 9 14:55:20 2013 +0530 Fix pretty printers pretty printers for rtems_id and rtems_attribute --- tools/gdb/python/classic.py | 4 +++- tools/gdb/python/objects.py | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 99d6397..d3f624d 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -101,7 +101,7 @@ class attribute: class attribute_printer: def __init__(self, attr): - self.attr = attr + self.attr = attribute(attr,'all') def to_string(self): return gdb.Value(self.attr.to_string()) @@ -229,3 +229,5 @@ class message_queue: def show(self, from_tty): print ' Name:', self.object_control.name() print ' Attr:', self.attr.to_string() + + diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index bedf875..25353d7 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -307,8 +307,8 @@ class name_printer: """Pretty printer for an object's name. It has to guess the type as no information is available to help determine it.""" - def __init__(self, name): - self.name = name(name) + def __init__(self, nameval): + self.name = name(nameval) def to_string(self): return gdb.Value(str(self.name)) From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Object can have index from 1 to 'maximum' Message-ID: <20140824234535.39322700810@git.rtems.org> Module: rtems-tools Branch: master Commit: ce55b57c4c4d6e3a090bdfbf9053a4e931eeb078 Changeset: http://git.rtems.org/rtems-tools/commit/?id=ce55b57c4c4d6e3a090bdfbf9053a4e931eeb078 Author: Dhananjay Balan Date: Mon Jul 8 21:58:21 2013 +0530 Object can have index from 1 to 'maximum' --- tools/gdb/python/objects.py | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 16ceac1..bedf875 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -68,7 +68,7 @@ class infotables: n = self.name(api, _class) self.load(n) max = self.maximum(api, _class) - if index >= max: + if index > max: raise IndexError('object index out of range (%d)' % (max)) table_type = self.tables_types[n] expr = '(' + table_type[0] + '*)' + \ From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Update Readme. Message-ID: <20140824234535.79D4E70080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 52fc20058b33fb877e38ca9af898a24ea28069f5 Changeset: http://git.rtems.org/rtems-tools/commit/?id=52fc20058b33fb877e38ca9af898a24ea28069f5 Author: Dhananjay Balan Date: Fri Aug 23 10:13:07 2013 +0530 Update Readme. Add wiki pages, usage instructions etc. --- tools/gdb/python/README.md | 33 +++++++++++++++++++++++++++++---- 1 files changed, 29 insertions(+), 4 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 8858a4f..1fbbd3e 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -1,6 +1,31 @@ -rtems-gdb -========= +# RTEMS GDB -GDB extenstions to RTEMS. +GDB extensions to help accelarting RTEMS debugging. + +## Usage + - Clone the git repo + - Fire up gdb and use source command +``` +$ sparc-rtems4.11-gdb + +GNU gdb (GDB) 7.5.1 +Copyright (C) 2012 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "--host=x86_64-linux-gnu --target=sparc-rtems4.11". +For bug reporting instructions, please see: +. +(gdb) source path/to/clone/__init__.py +RTEMS GDB Support loaded +(gdb) +``` + +## Commands Implemented + - `rtems object` : Prints rtems objects by ID + - [rtems index subcommands](Subcommands) + +## Developer documentation +We have a document to get started with [pretty printer development](Writing-a-pretty-printer). -See [this blog post for instructions](http://dbalan.github.io/blog/2013/06/23/debugging-rtems-with-gdb/) From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Update README.md Message-ID: <20140824234535.953E3700A25@git.rtems.org> Module: rtems-tools Branch: master Commit: b5c4f41b0e46690e9629eed0db11011994eaca07 Changeset: http://git.rtems.org/rtems-tools/commit/?id=b5c4f41b0e46690e9629eed0db11011994eaca07 Author: Dhananjay Balan Date: Fri Aug 23 10:13:48 2013 +0530 Update README.md Fix indentation. --- tools/gdb/python/README.md | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 1fbbd3e..16ad8dc 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -5,6 +5,7 @@ GDB extensions to help accelarting RTEMS debugging. ## Usage - Clone the git repo - Fire up gdb and use source command + ``` $ sparc-rtems4.11-gdb From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Refactoring Message-ID: <20140824234535.150D9700814@git.rtems.org> Module: rtems-tools Branch: master Commit: 0967a1b679495f728781bd05318379024cadf5c5 Changeset: http://git.rtems.org/rtems-tools/commit/?id=0967a1b679495f728781bd05318379024cadf5c5 Author: Dhananjay Balan Date: Sat Jul 13 16:49:59 2013 +0530 Refactoring - drop _printer suffix from printer classes. --- tools/gdb/python/__init__.py | 3 +- tools/gdb/python/classic.py | 1 + tools/gdb/python/classic_printer.py | 6 ++-- tools/gdb/python/helper.py | 8 +++++ tools/gdb/python/objects.py | 51 +-------------------------------- tools/gdb/python/rtems.py | 14 ++++---- tools/gdb/python/supercore.py | 10 +----- tools/gdb/python/supercore_printer.py | 12 ++++---- 8 files changed, 30 insertions(+), 75 deletions(-) diff --git a/tools/gdb/python/__init__.py b/tools/gdb/python/__init__.py index dd55529..694eb06 100644 --- a/tools/gdb/python/__init__.py +++ b/tools/gdb/python/__init__.py @@ -13,7 +13,7 @@ if __name__ == "__main__": import supercore_printer import classic_printer - # Needed to reload code inside gdb source command + # Needed inorder to reload code from inside gdb reload(supercore) reload(chains) reload(rtems) @@ -22,4 +22,5 @@ if __name__ == "__main__": reload(threads) reload(supercore_printer) reload(classic_printer) + print 'RTEMS GDB Support loaded' diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index e82078d..9af11df 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -79,6 +79,7 @@ class attribute: self.attrtype = attrtype self.attr = attr + #ToDo: Move this out def to_string(self): s = '0x%08x,' % (self.attr) if self.attrtype != 'none': diff --git a/tools/gdb/python/classic_printer.py b/tools/gdb/python/classic_printer.py index e9d7cb8..a25d756 100644 --- a/tools/gdb/python/classic_printer.py +++ b/tools/gdb/python/classic_printer.py @@ -2,7 +2,7 @@ # RTEMS Classic pretty printers for GDB # -class attribute_printer: +class attribute: def __init__(self, attribute): ''' ToDo: Verify - usage of all ''' @@ -11,8 +11,8 @@ class attribute_printer: def to_string(self): return gdb.Value(self.attr.to_string()) -class semaphore_printer: - """WIP: Print a Semaphore_Control object. Print using the struct display hint +class semaphore: + """ToDo: Print a Semaphore_Control object. Print using the struct display hint and an iterator. """ class iterator: diff --git a/tools/gdb/python/helper.py b/tools/gdb/python/helper.py new file mode 100644 index 0000000..ec17400 --- /dev/null +++ b/tools/gdb/python/helper.py @@ -0,0 +1,8 @@ +# +# RTEMS GDB support helper routins. + +def tasks_printer_rotuine(wait_queue): + tasks = wait_queue.tasks() + print ' Queue: len = %d, state = %s' % (len(tasks),wait_queue.state()) + for t in range(0, len(tasks)): + print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) \ No newline at end of file diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index d2ba216..23ea7be 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -245,53 +245,4 @@ class control: def name(self): is_string = information.is_string(self._id.api(), self._id._class()) - return str(name(self.object['name'], is_string)) - - - - -class control_printer: - - class iterator: - """Use an iterator for each field expanded from the id so GDB output - is formatted correctly.""" - - def __init__(self, object): - self.object = object - self.count = 0 - - def __iter__(self): - return self - - def next(self): - self.count += 1 - if self.count == 1: - return self.object.node() - elif self.count == 2: - return self.object.id() - elif self.count == 3: - return self.object.name() - raise StopIteration - - def to_string(self): - return '' - - def __init__(self, object): - self.object = control(object) - - @staticmethod - def key(i): - if i == 0: - return 'Node' - elif i == 1: - return 'id' - elif i == 2: - return 'name' - return 'bad' - - def children(self): - counter = itertools.imap (self.key, itertools.count()) - return itertools.izip (counter, self.iterator(self.object)) - - def display_hint (self): - return 'struct' + return str(name(self.object['name'], is_string)) \ No newline at end of file diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index d530e6e..4622ced 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -54,13 +54,13 @@ def lookup_function (val): return None def build_rtems_dict(): - pp_dict[re.compile('^rtems_id$')] = lambda val: supercore_printer.id_printer(val) - pp_dict[re.compile('^Objects_Id$')] = lambda val: supercore_printer.id_printer(val) - pp_dict[re.compile('^Objects_Name$')] = lambda val: supercore_printer.name_printer(val) - pp_dict[re.compile('^Objects_Control$')] = lambda val: supercore_printer.control_printer(val) - pp_dict[re.compile('^States_Control$')] = lambda val: supercore_printer.state_printer(val) - pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic_printer.attribute_printer(val) - pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic_printer.semaphore_printer(val) + pp_dict[re.compile('^rtems_id$')] = lambda val: supercore_printer.id(val) + pp_dict[re.compile('^Objects_Id$')] = lambda val: supercore_printer.id(val) + pp_dict[re.compile('^Objects_Name$')] = lambda val: supercore_printer.name(val) + pp_dict[re.compile('^Objects_Control$')] = lambda val: supercore_printer.control(val) + pp_dict[re.compile('^States_Control$')] = lambda val: supercore_printer.state(val) + pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic_printer.attribute(val) + pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic_printer.semaphore(val) class rtems(gdb.Command): """Prefix command for RTEMS.""" diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py index 4378e12..7e958b1 100644 --- a/tools/gdb/python/supercore.py +++ b/tools/gdb/python/supercore.py @@ -3,13 +3,7 @@ # import threads - -# ToDo: Move this to helper. -def tasks_printer_rotuine(wait_queue): - tasks = wait_queue.tasks() - print ' Queue: len = %d, state = %s' % (len(tasks),wait_queue.state()) - for t in range(0, len(tasks)): - print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) +import helper class CORE_message_queue: '''Manage a Supercore message_queue''' @@ -21,4 +15,4 @@ class CORE_message_queue: # self.buffer def show(self): - tasks_printer_rotuine(self.wait_queue) + helper.tasks_printer_rotuine(self.wait_queue) diff --git a/tools/gdb/python/supercore_printer.py b/tools/gdb/python/supercore_printer.py index cee9097..ec1d416 100644 --- a/tools/gdb/python/supercore_printer.py +++ b/tools/gdb/python/supercore_printer.py @@ -4,7 +4,7 @@ import objects import itertools -class id_printer: +class id: """Print an object given the ID. Print using the struct display hint and an iterator.""" @@ -60,7 +60,7 @@ class id_printer: def display_hint (self): return 'struct' -class name_printer: +class name: """Pretty printer for an object's name. It has to guess the type as no information is available to help determine it.""" @@ -70,7 +70,7 @@ class name_printer: def to_string(self): return str(self.name) -class control_printer: +class control: class iterator: """Use an iterator for each field expanded from the id so GDB output @@ -117,14 +117,14 @@ class control_printer: return 'struct' -class state_printer: +class state: def __init__(self, state): self.state = threads.state(state) def to_string(self): return self.state.to_string() -class chains_printer: +class chains: def __init__(self,chain): self.chain = chains.control(chain) @@ -132,7 +132,7 @@ class chains_printer: def to_string(self): return "First:"+str(self.chain.first())+"\n Last:"+str(self.chain.last()) -class node_printer: +class node: def __init__(self, node): self.node = chains.node(node) From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Messege Queue Objects Message-ID: <20140824234534.07D58700AB8@git.rtems.org> Module: rtems-tools Branch: master Commit: f814c7629cf5c87f0262ee877116166a02241c84 Changeset: http://git.rtems.org/rtems-tools/commit/?id=f814c7629cf5c87f0262ee877116166a02241c84 Author: Dhananjay Balan Date: Mon Jul 8 22:00:48 2013 +0530 Messege Queue Objects Added intial support for printing --- tools/gdb/python/classic.py | 29 ++++++++++++++++++++++------- tools/gdb/python/rtems.py | 9 +++++---- 2 files changed, 27 insertions(+), 11 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 8748bbf..99d6397 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -36,7 +36,9 @@ class attribute: 'semaphore-pri-ceiling'], 'barrier' : ['scope', 'priority', - 'barrier'] + 'barrier'], + 'message_queue' : ['priority', + 'scope'] } masks = { @@ -64,7 +66,7 @@ class attribute: (0x00000040, 'inherit-pri')], 'semaphore-pri-ceiling' : [(0x00000000, 'no-pri-ceiling'), (0x00000080, 'pri-ceiling')], - 'barrier' : [(0x00000010, 'barrier-auto-release'), + 'barrier' : [(0x00000010, 'barrier-auto-release'), (0x00000000, 'barrier-manual-release')], 'task' : [(0x00000000, 'app-task'), (0x00008000, 'sys-task')] @@ -97,7 +99,7 @@ class attribute: return False class attribute_printer: - + def __init__(self, attr): self.attr = attr @@ -124,7 +126,7 @@ class semaphore_printer: if self.count == 1: return self.semaphore['Object'] elif self.count == 2: - attr = attribute(self.semaphore['attribute_set'], + attr = attribute(self.semaphore['attribute_set'], 'semaphore') return attr.to_string() elif self.count == 3: @@ -162,7 +164,7 @@ class semaphore: self.object = objects.information.object(self.id).dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'semaphore') - + def show(self, from_tty): print ' Name:', self.object_control.name() print ' Attr:', self.attr.to_string() @@ -202,7 +204,7 @@ class task: self.id = id; self.task = \ threads.control(objects.information.object(self.id).dereference()) - + def show(self, from_tty): print ' Name:', self.task.name() print ' State:', self.task.current_state() @@ -213,4 +215,17 @@ class task: print ' Preempt:', self.task.preemptible() print ' T Budget:', self.task.cpu_time_budget() wait_info = self.task.wait_info() - + +class message_queue: + "Print a classic messege queue" + + def __init__(self,id): + self.id = id + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.attr = attribute(self.object['attribute_set'], \ + 'message_queue') + + def show(self, from_tty): + print ' Name:', self.object_control.name() + print ' Attr:', self.attr.to_string() diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index e227c6f..398f4e5 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -72,12 +72,13 @@ class rtems_object(gdb.Command): objects = { 'classic/semaphores': lambda id: classic.semaphore(id), - 'classic/tasks': lambda id: classic.task(id) + 'classic/tasks': lambda id: classic.task(id), + 'classic/message_queues': lambda id: classic.message_queue(id) } def __init__(self): self.__doc__ = 'Display the RTEMS object given a numeric ID.' - super(rtems_object, self).__init__('rtems object', + super(rtems_object, self).__init__('rtems object', gdb.COMMAND_STATUS) def invoke(self, arg, from_tty): @@ -98,7 +99,7 @@ class rtems_object(gdb.Command): object = self.objects[objectname](id) object.show(from_tty) objects.information.invalidate() - + # # Main # @@ -107,4 +108,4 @@ build_rtems_dict() gdb.pretty_printers = [] gdb.pretty_printers.append (lookup_function) rtems() -rtems_object() +rtems_object() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Catch nonvalid indexes. Message-ID: <20140824234536.2C691700A25@git.rtems.org> Module: rtems-tools Branch: master Commit: b743d63fde73cde72ddd80f5cd654e369e7d7bf0 Changeset: http://git.rtems.org/rtems-tools/commit/?id=b743d63fde73cde72ddd80f5cd654e369e7d7bf0 Author: Dhananjay Balan Date: Fri Aug 9 18:04:37 2013 +0530 Catch nonvalid indexes. Catch IndexErrors generated while referancing non existant indexes. --- tools/gdb/python/rtems.py | 10 +++++++--- 1 files changed, 7 insertions(+), 3 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 8eb49c9..dbfd7c7 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -130,10 +130,14 @@ class rtems_semaphore(gdb.Command): except ValueError: print "error: %s is not an index" % (val) return + try: + obj = objects.information.object_return( self.api, + self._class, + index ).dereference() + except IndexError: + print "error: index %s is invalid" % (index) + return - obj = objects.information.object_return( self.api, - self._class, - int(index)).dereference() instance = classic.semaphore(obj) instance.show(from_tty) objects.information.invalidate() From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Add message_queue subcommand. Message-ID: <20140824234536.5A57A700AF5@git.rtems.org> Module: rtems-tools Branch: master Commit: 2c25dc56edf95d1d60c48070431e68a31f9865f1 Changeset: http://git.rtems.org/rtems-tools/commit/?id=2c25dc56edf95d1d60c48070431e68a31f9865f1 Author: Dhananjay Balan Date: Thu Aug 15 20:44:30 2013 +0530 Add message_queue subcommand. --- tools/gdb/python/rtems.py | 35 ++++++++++++++++++++++++++++++++++- 1 files changed, 34 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index dbfd7c7..9ae2105 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -172,6 +172,38 @@ class rtems_task(gdb.Command): instance.show(from_tty) objects.information.invalidate() +class rtems_message_queue(gdb.Command): + '''Message Queue subcommand''' + + api = 'classic' + _class = 'message_queues' + + def __init__(self): + self.__doc__ = 'Display the RTEMS message_queue by index(s)' + super(rtems_message_queue,self).__init__('rtems mqueue', gdb.COMMAND_STATUS) + + def invoke(self, arg, from_tty): + for val in arg.split(): + try: + index = int(val) + except ValueError: + print "error: %s is not an index" % (val) + return + + try: + obj = objects.information.object_return(self.api, + self._class, + index).dereference() + except IndexError: + print "error: index %s is invalid" % (index) + return + + print "Ahi" + instance = classic.message_queue(obj) + instance.show(from_tty) + objects.information.invalidate() + + # # Main # @@ -182,4 +214,5 @@ gdb.pretty_printers.append (lookup_function) rtems() rtems_object() rtems_semaphore() -rtems_task() \ No newline at end of file +rtems_task() +rtems_message_queue() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Update chains structures Message-ID: <20140824234535.4A923700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 10bcd5d4dc77a9296d458855c9385fdd82c97ac0 Changeset: http://git.rtems.org/rtems-tools/commit/?id=10bcd5d4dc77a9296d458855c9385fdd82c97ac0 Author: Dhananjay Balan Date: Mon Jun 24 09:58:59 2013 +0530 Update chains structures - Fixes chains structure parsing - Fix Semaphore node parsing --- tools/gdb/python/chains.py | 12 ++++++++---- tools/gdb/python/objects.py | 7 +++++-- tools/gdb/python/threads.py | 16 ++++++++-------- 3 files changed, 21 insertions(+), 14 deletions(-) diff --git a/tools/gdb/python/chains.py b/tools/gdb/python/chains.py index 961ca2d..d691822 100644 --- a/tools/gdb/python/chains.py +++ b/tools/gdb/python/chains.py @@ -14,15 +14,17 @@ class node: self.node_val = node_val def null(self): - return self.node_val['next'] == 0 + if not self.node_val: + return True + return False def next(self): if not self.null(): - self.node_val = self.node_val['next'].dereference() + self.node_val = self.node_val['next'] def previous(self): if not self.null(): - self.node_val = self.node_val['previous'].dereference() + self.node_val = self.node_val['previous'] def cast(self, typename): if not self.null(): @@ -30,6 +32,7 @@ class node: return self.node_val.cast(nodetype) return None + class control: """Manage the Chain_Control.""" @@ -37,7 +40,8 @@ class control: self.ctrl = ctrl def first(self): - return node(self.ctrl['first'].dereference()) + t = node(self.ctrl['Head']['Node']) + return t def last(self): return node(self.ctrl['first']) diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 22d2b2c..16ceac1 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -62,6 +62,9 @@ class infotables: api = id.api() _class = id._class() index = id.index() + return self.object_return(api, _class, index) + + def object_return(self, api, _class, index): n = self.name(api, _class) self.load(n) max = self.maximum(api, _class) @@ -96,7 +99,7 @@ class ident: { 'index': (0, 15), 'node': (16, 23), 'api': (24, 26), - 'class': (27, 31) } + 'class': (27, 31) } ] OBJECT_16_BITS = 0 @@ -147,7 +150,7 @@ class ident: 'variable_memory_pools', 'fixed_memory_pools') } - + def __init__(self, id): if type(id) != gdb.Value and type(id) != int and type(id) != unicode: raise TypeError('%s: must be gdb.Value, int, unicoded int' % (type(id))) diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py index 906cf5a..3debbe7 100644 --- a/tools/gdb/python/threads.py +++ b/tools/gdb/python/threads.py @@ -14,7 +14,6 @@ def task_chain(chain): tasks = [] node = chain.first() while not node.null(): - print node.addr tasks.append(control(node.cast('Thread_Control'))) node.next() return tasks @@ -62,7 +61,7 @@ class state: WAITING_FOR_EVENT | \ WAITING_ON_THREAD_QUEUE | \ INTERRUPTIBLE_BY_SIGNAL - + masks = { ALL_SET : 'all-set', READY : 'ready', @@ -85,7 +84,7 @@ class state: WAITING_FOR_BARRIER : 'waiting-for-barrier', WAITING_FOR_RWLOCK : 'waiting-for-rwlock' } - + def __init__(self, s): self.s = s @@ -121,16 +120,16 @@ class wait_info: def block2n(self): return task_chain(chains.control(self.info['Block2n'])) - + def queue(self): return task_chain(chains.control(self.info['queue'])) class control: - + def __init__(self, ctrl): self.ctrl = ctrl self.object = objects.control(ctrl['Object']) - + def id(self): return self.object.id() @@ -181,14 +180,15 @@ class queue: def state(self): return state(self.que['state']).to_string() - + def tasks(self): if self.fifo(): t = task_chain(chains.control(self.que['Queues']['Fifo'])) else: t = [] for ph in range(0, self.priority_headers): - t.extend(task_chain(chains.control(self.que['Queues']['Fifo']))) + t.extend(task_chain(chains.control( \ + self.que['Queues']['Priority'][ph]))) return t def to_string(self): From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Add classic barrier. Message-ID: <20140824234535.B65A770080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 8e0de06b2bc6fecf8e055361590176698d0a648b Changeset: http://git.rtems.org/rtems-tools/commit/?id=8e0de06b2bc6fecf8e055361590176698d0a648b Author: Dhananjay Balan Date: Mon Jul 29 10:43:38 2013 +0530 Add classic barrier. - Add support for classic barrier object. - Drop CORE_ from names in supercore --- tools/gdb/python/classic.py | 30 +++++++++++++++++++++++++----- tools/gdb/python/rtems.py | 3 ++- tools/gdb/python/supercore.py | 37 ++++++++++++++++++++++++++++++++++++- 3 files changed, 63 insertions(+), 7 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index e2ecfaa..617a0db 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -39,9 +39,7 @@ class attribute: 'semaphore-type', 'semaphore-pri', 'semaphore-pri-ceiling'], - 'barrier' : ['scope', - 'priority', - 'barrier'], + 'barrier' : ['barrier'], 'message_queue' : ['priority', 'scope'], 'partition' : ['scope'], @@ -149,7 +147,7 @@ class semaphore: print 'semaphore' class task: - "Print a classic tasks." + "Print a classic task" def __init__(self, id): self.id = id; @@ -179,7 +177,7 @@ class message_queue: self.wait_queue = threads.queue( \ self.object['message_queue']['Wait_queue']) - self.core_control = supercore.CORE_message_queue(self.object['message_queue']) + self.core_control = supercore.message_queue(self.object['message_queue']) def show(self, from_tty): print ' Name:', self.object_control.name() @@ -238,3 +236,25 @@ class region: helper.tasks_printer_routine(self.wait_queue) print ' Memory:' self.heap.show() + +class barrier: + '''classic barrier abstraction''' + + def __init__(self,id): + self.id = id + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.attr = attribute(self.object['attribute_set'],'barrier') + self.core_b_control = supercore.barrier_control(self.object['Barrier']) + + def show(self,from_tty): + print ' Name:',self.object_control.name() + print ' Attr:',self.attr.to_string() + + if self.attr.test('barrier','barrier-auto-release'): + max_count = self.core_b_control.max_count() + print 'Aut Count:', max_count + + print ' Waiting:',self.core_b_control.waiting_threads() + helper.tasks_printer_routine(self.core_b_control.tasks()) + diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 8738736..adab86d 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -80,7 +80,8 @@ class rtems_object(gdb.Command): 'classic/message_queues': lambda id: classic.message_queue(id), 'classic/timers' : lambda id: classic.timer(id), 'classic/partitions' : lambda id: classic.partition(id), - 'classic/regions' : lambda id: classic.region(id) + 'classic/regions' : lambda id: classic.region(id), + 'classic/barriers' : lambda id: classic.barrier(id) } def __init__(self): diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py index 073bbd0..e60813a 100644 --- a/tools/gdb/python/supercore.py +++ b/tools/gdb/python/supercore.py @@ -5,7 +5,7 @@ import threads import helper -class CORE_message_queue: +class message_queue: '''Manage a Supercore message_queue''' def __init__(self, message_queue): @@ -16,3 +16,38 @@ class CORE_message_queue: def show(self): helper.tasks_printer_routine(self.wait_queue) + +class barrier_attributes: + '''supercore bbarrier attribute''' + + def __init__(self,attr): + self.attr = attr + + def max_count(self): + c = self.attr['maximum_count'] + return c + + def discipline(self): + d = self.attr['discipline'] + return d + +class barrier_control: + '''Manage a Supercore barrier''' + + def __init__(self, barrier): + self.barrier = barrier + self.wait_queue = threads.queue(self.barrier['Wait_queue']) + self.attr = barrier_attributes(self.barrier['Attributes']) + + def waiting_threads(self): + wt = self.barrier['number_of_waiting_threads'] + return wt + + def max_count(self): + return self.attr.max_count() + + def discipline(self): + return self.attr.discipline() + + def tasks(self): + return self.wait_queue From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Barrier taks queue Message-ID: <20140824234535.D41F3700A25@git.rtems.org> Module: rtems-tools Branch: master Commit: 66d0779c33ac817c8f23a24294d617800581ca36 Changeset: http://git.rtems.org/rtems-tools/commit/?id=66d0779c33ac817c8f23a24294d617800581ca36 Author: Dhananjay Balan Date: Mon Aug 5 00:25:47 2013 +0530 Barrier taks queue Print the barrier taks queue. --- tools/gdb/python/classic.py | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 29ffab5..b919383 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -251,3 +251,4 @@ class barrier: print ' Waiting:',self.core_b_control.waiting_threads() helper.tasks_printer_routine(self.core_b_control.tasks()) + From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Catch invalid object ID. Message-ID: <20140824234536.1136D70080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 559bd50d27023ccd7d65f1c023e075fe965dcbfd Changeset: http://git.rtems.org/rtems-tools/commit/?id=559bd50d27023ccd7d65f1c023e075fe965dcbfd Author: Dhananjay Balan Date: Mon Aug 5 00:35:39 2013 +0530 Catch invalid object ID. --- tools/gdb/python/rtems.py | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index b2dc776..20f44a2 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -100,6 +100,8 @@ class rtems_object(gdb.Command): id = objects.ident(num) if not id.valid(): print 'Invalid object id' + return + print 'API:%s Class:%s Node:%d Index:%d Id:%08X' % \ (id.api(), id._class(), id.node(), id.index(), id.value()) objectname = id.api() + '/' + id._class() From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Abstraction for HEAP. Message-ID: <20140824234536.49A00700A5D@git.rtems.org> Module: rtems-tools Branch: master Commit: c3d06d531c497c665671386bc32dd18fbfac49b3 Changeset: http://git.rtems.org/rtems-tools/commit/?id=c3d06d531c497c665671386bc32dd18fbfac49b3 Author: Dhananjay Balan Date: Sun Jul 28 13:19:06 2013 +0530 Abstraction for HEAP. Heap_Control Abstraction is added. It will need some more grooming though. --- tools/gdb/python/heaps.py | 62 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 62 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/heaps.py b/tools/gdb/python/heaps.py new file mode 100644 index 0000000..4798912 --- /dev/null +++ b/tools/gdb/python/heaps.py @@ -0,0 +1,62 @@ +# +# RTEMS heap +# + +class block: + '''Abstract a heap block structure''' + + def __init__(self, blk): + self.block = blk + self.prev_size = self.block['prev_size'] + self.size_flag = self.block['size_and_flag'] + + def null(self): + if self.block: + return False + return True + + + def next(self): + if not self.null(): + self.block = self.block['next'] + + def prev(self): + if not self.null(): + self.block = self.block['prev'] + +class stats: + ''heap statistics'' + + def __init__(self,stat): + self.stat = stat + + def avail(self): + val = self.stat['size'] + return val + + def free(self): + return self.stat['free_size'] + + # ToDo : incorporate others + +def control: + '''Abstract a heap control structure''' + + def __init__(self, ctl): + self.ctl = ctl + + def first(self): + b = block(self.ctl['first_block']) + return b + + def last(self): + b = block(self.ctl['last_block']) + return b + + def free(self): + b = block(self.ctl['free_list']) + return b + + def stat(self): + st = stats(self.ctl['stats']) + return st \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Update README.md Message-ID: <20140824234536.3AF0D700A87@git.rtems.org> Module: rtems-tools Branch: master Commit: a0bf9f207ac34ddaca42e0506b3743e6f416bd85 Changeset: http://git.rtems.org/rtems-tools/commit/?id=a0bf9f207ac34ddaca42e0506b3743e6f416bd85 Author: Dhananjay Balan Date: Fri Aug 23 10:16:22 2013 +0530 Update README.md Fix Links. --- tools/gdb/python/README.md | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 16ad8dc..dbf3bda 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -25,8 +25,8 @@ RTEMS GDB Support loaded ## Commands Implemented - `rtems object` : Prints rtems objects by ID - - [rtems index subcommands](Subcommands) + - [rtems index subcommands](https://github.com/dbalan/rtems-gdb/wiki/Subcommands) ## Developer documentation -We have a document to get started with [pretty printer development](Writing-a-pretty-printer). +We have a document to get started with [pretty printer development](https://github.com/dbalan/rtems-gdb/wiki/Writing-a-pretty-printer). From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] New todo Message-ID: <20140824234536.00787700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 59c4946ba345c8d7b72e71aadc51f31cceff5354 Changeset: http://git.rtems.org/rtems-tools/commit/?id=59c4946ba345c8d7b72e71aadc51f31cceff5354 Author: Dhananjay Balan Date: Mon Jul 29 10:44:02 2013 +0530 New todo --- tools/gdb/python/README.md | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index c471cd9..6dc9b5e 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -7,3 +7,4 @@ See [this blog post for instructions](http://dbalan.github.io/blog/2013/06/23/de TODO: - classic abstractions address on id - change this to more proper hierarchy. + - Inherit from object_control class From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Intial commit. Message-ID: <20140824234535.54F5D700A87@git.rtems.org> Module: rtems-tools Branch: master Commit: 56a70aec5536a568fe302a3c84b349fcf17db2fa Changeset: http://git.rtems.org/rtems-tools/commit/?id=56a70aec5536a568fe302a3c84b349fcf17db2fa Author: Dhananjay Balan Date: Mon Jun 17 22:58:17 2013 +0530 Intial commit. Chris's intial work on the extenstions. --- tools/gdb/python/__init__.py | 16 ++ tools/gdb/python/chains.py | 43 +++++ tools/gdb/python/classic.py | 216 +++++++++++++++++++++++++ tools/gdb/python/objects.py | 357 ++++++++++++++++++++++++++++++++++++++++++ tools/gdb/python/rtems.py | 110 +++++++++++++ tools/gdb/python/threads.py | 207 ++++++++++++++++++++++++ tools/gdb/python/watchdog.py | 56 +++++++ 7 files changed, 1005 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/__init__.py b/tools/gdb/python/__init__.py new file mode 100644 index 0000000..0664d21 --- /dev/null +++ b/tools/gdb/python/__init__.py @@ -0,0 +1,16 @@ + +if __name__ == "__main__": + import sys + import os.path + sys.path.append(os.path.dirname(__file__)) + import chains + import rtems + import classic + import objects + import threads + reload(chains) + reload(rtems) + reload(classic) + reload(objects) + reload(threads) + print 'RTEMS GDB Support loaded' diff --git a/tools/gdb/python/chains.py b/tools/gdb/python/chains.py new file mode 100644 index 0000000..961ca2d --- /dev/null +++ b/tools/gdb/python/chains.py @@ -0,0 +1,43 @@ +# +# RTEMS Chains Support +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb + +class node: + """Manage the Chain_Node.""" + + def __init__(self, node_val): + self.node_val = node_val + + def null(self): + return self.node_val['next'] == 0 + + def next(self): + if not self.null(): + self.node_val = self.node_val['next'].dereference() + + def previous(self): + if not self.null(): + self.node_val = self.node_val['previous'].dereference() + + def cast(self, typename): + if not self.null(): + nodetype = gdb.lookup_type(typename) + return self.node_val.cast(nodetype) + return None + +class control: + """Manage the Chain_Control.""" + + def __init__(self, ctrl): + self.ctrl = ctrl + + def first(self): + return node(self.ctrl['first'].dereference()) + + def last(self): + return node(self.ctrl['first']) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py new file mode 100644 index 0000000..8748bbf --- /dev/null +++ b/tools/gdb/python/classic.py @@ -0,0 +1,216 @@ +# +# RTEMS Classic API Support +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb +import itertools +import re + +import objects +import threads + +class attribute: + """The Classic API attribute.""" + + groups = { + 'none' : [], + 'all' : ['scope', + 'priority', + 'fpu', + 'semaphore-type', + 'semaphore-pri', + 'semaphore-pri-ceiling', + 'barrier', + 'task'], + 'task' : ['scope', + 'priority', + 'fpu', + 'task'], + 'semaphore' : ['scope', + 'priority', + 'semaphore-type', + 'semaphore-pri', + 'semaphore-pri-ceiling'], + 'barrier' : ['scope', + 'priority', + 'barrier'] + } + + masks = { + 'scope' : 0x00000002, + 'priority' : 0x00000004, + 'fpu' : 0x00000001, + 'semaphore-type' : 0x00000030, + 'semaphore-pri' : 0x00000040, + 'semaphore-pri-ceiling' : 0x00000080, + 'barrier' : 0x00000010, + 'task' : 0x00008000 + } + + fields = { + 'scope' : [(0x00000000, 'local'), + (0x00000002, 'global')], + 'priority' : [(0x00000000, 'fifo'), + (0x00000004, 'pri')], + 'fpu' : [(0x00000000, 'no-fpu'), + (0x00000001, 'fpu')], + 'semaphore-type' : [(0x00000000, 'count-sema'), + (0x00000010, 'bin-sema'), + (0x00000020, 'simple-bin-sema')], + 'semaphore-pri' : [(0x00000000, 'no-inherit-pri'), + (0x00000040, 'inherit-pri')], + 'semaphore-pri-ceiling' : [(0x00000000, 'no-pri-ceiling'), + (0x00000080, 'pri-ceiling')], + 'barrier' : [(0x00000010, 'barrier-auto-release'), + (0x00000000, 'barrier-manual-release')], + 'task' : [(0x00000000, 'app-task'), + (0x00008000, 'sys-task')] + } + + def __init__(self, attr, attrtype = 'none'): + if attrtype not in self.groups: + raise 'invalid attribute type' + self.attrtype = attrtype + self.attr = attr + + def to_string(self): + s = '0x%08x,' % (self.attr) + if self.attrtype != 'none': + for m in self.groups[self.attrtype]: + v = self.attr & self.masks[m] + for f in self.fields[m]: + if f[0] == v: + s += f[1] + ',' + break + return s[:-1] + + def test(self, mask, value): + if self.attrtype != 'none' and \ + mask in self.groups[self.attrtype]: + v = self.masks[mask] & self.attr + for f in self.fields[mask]: + if v == f[0] and value == f[1]: + return True + return False + +class attribute_printer: + + def __init__(self, attr): + self.attr = attr + + def to_string(self): + return gdb.Value(self.attr.to_string()) + +class semaphore_printer: + """Print a Semaphore_Control object. Print using the struct display hint + and an iterator.""" + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, semaphore): + self.semaphore = semaphore + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return self.semaphore['Object'] + elif self.count == 2: + attr = attribute(self.semaphore['attribute_set'], + 'semaphore') + return attr.to_string() + elif self.count == 3: + return self.semaphore['Core_control'] + raise StopIteration + + def __init__(self, semaphore): + self.semaphore = semaphore + + def to_string(self): + return '' + + @staticmethod + def key(i): + if i == 0: + return 'Object' + elif i == 1: + return 'attribute_set' + elif i == 2: + return 'Core_control' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.semaphore)) + + def display_hint (self): + return 'struct' + +class semaphore: + "Print a classic semaphore." + + def __init__(self, id): + self.id = id; + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.attr = attribute(self.object['attribute_set'], 'semaphore') + + def show(self, from_tty): + print ' Name:', self.object_control.name() + print ' Attr:', self.attr.to_string() + if self.attr.test('semaphore-type', 'bin-sema') or \ + self.attr.test('semaphore-type', 'simple-bin-sema'): + core_mutex = self.object['Core_control']['mutex'] + locked = core_mutex['lock'] == 0 + if locked: + s = 'locked' + else: + s = 'unlocked' + print ' Lock:', s + print ' Nesting:', core_mutex['nest_count'] + print ' Blocked:', core_mutex['blocked_count'] + print ' Holder:', + holder = core_mutex['holder'] + if holder and locked: + holder = threads.control(holder.dereference()) + print holder.brief() + elif holder == 0 and locked: + print 'locked but no holder' + else: + print 'unlocked' + wait_queue = threads.queue(core_mutex['Wait_queue']) + tasks = wait_queue.tasks() + print ' Queue: len = %d, state = %s' % (len(tasks), + wait_queue.state()) + for t in range(0, len(tasks)): + print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) + else: + print 'semaphore' + +class task: + "Print a classic tasks." + + def __init__(self, id): + self.id = id; + self.task = \ + threads.control(objects.information.object(self.id).dereference()) + + def show(self, from_tty): + print ' Name:', self.task.name() + print ' State:', self.task.current_state() + print ' Current:', self.task.current_priority() + print ' Real:', self.task.real_priority() + print ' Suspends:', self.task.suspends() + print ' Post Ext:', self.task.post_task_switch_ext() + print ' Preempt:', self.task.preemptible() + print ' T Budget:', self.task.cpu_time_budget() + wait_info = self.task.wait_info() + diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py new file mode 100644 index 0000000..22d2b2c --- /dev/null +++ b/tools/gdb/python/objects.py @@ -0,0 +1,357 @@ +# +# RTEMS Objects Support +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb +import itertools +import re + +class infotables: + """Manage the object information tables.""" + + tables_types = { + 'classic/tasks' : ('Thread_Control', '_RTEMS_tasks_Information'), + 'classic/timers' : ('Timer_Control', '_Timers_Information'), + 'classic/semaphores' : ('Semaphore_Control', '_Semaphore_Information'), + 'classic/message_queues' : ('Message_queue_Control', '_Message_queue_Information'), + 'classic/partitions' : ('Partition_Control', '_Partition_Information'), + 'classic/regions' : ('Region_Control', '_Regions_Information'), + 'classic/ports' : ('Port_Control', '_Port_Information'), + 'classic/periods' : ('Period_Control', '_Period_Information'), + 'classic/extensions' : ('Extension_Control', '_Extension_Information'), + 'classic/barriers' : ('Barrier_Control', '_Barrier_Information') + } + + def __init__(self): + self.invalidate() + + def invalidate(self): + self.tables = {} + + def name(self, api, _class): + return api + '/' + _class + + def load(self, n): + if n in self.tables_types: + if n not in self.tables: + self.tables[n] = gdb.parse_and_eval(self.tables_types[n][1]) + + def get(self, api, _class): + n = self.name(api, _class) + self.load(n) + if n in self.tables: + return self.tables[n] + return None + + def maximum(self, api, _class): + n = self.name(api, _class) + self.load(n) + return int(self.tables[n]['maximum']) + + def object(self, id): + if type(id) == gdb.Value: + id = ident(id) + if type(id) == tuple: + api = id[0] + _class = id[1] + index = id[2] + else: + api = id.api() + _class = id._class() + index = id.index() + n = self.name(api, _class) + self.load(n) + max = self.maximum(api, _class) + if index >= max: + raise IndexError('object index out of range (%d)' % (max)) + table_type = self.tables_types[n] + expr = '(' + table_type[0] + '*)' + \ + table_type[1] + '.local_table[' + str(index) + ']' + return gdb.parse_and_eval(expr) + + def is_string(self, api, _class): + n = self.name(api, _class) + self.load(n) + if n in self.tables: + if self.tables[n]['is_string']: + return True + return False + +# +# Global info tables. These are global in the target. +# +information = infotables() + +class ident: + "An RTEMS object id with support for its bit fields." + + bits = [ + { 'index': (0, 15), + 'node': (0, 0), + 'api': (8, 10), + 'class': (11, 15) }, + { 'index': (0, 15), + 'node': (16, 23), + 'api': (24, 26), + 'class': (27, 31) } + ] + + OBJECT_16_BITS = 0 + OBJECT_31_BITS = 1 + + api_labels = [ + 'none', + 'internal', + 'classic', + 'posix', + 'itron' + ] + + class_labels = { + 'internal' : ('threads', + 'mutexes'), + 'classic' : ('none', + 'tasks', + 'timers', + 'semaphores', + 'message_queues', + 'partitions', + 'regions', + 'ports', + 'periods', + 'extensions', + 'barriers'), + 'posix' : ('none', + 'threads', + 'keys', + 'interrupts', + 'message_queue_fds', + 'message_queues', + 'mutexes', + 'semaphores', + 'condition_variables', + 'timers', + 'barriers', + 'spinlocks', + 'rwlocks'), + 'itron' : ('none', + 'tasks', + 'eventflags', + 'mailboxes', + 'message_buffers', + 'ports', + 'semaphores', + 'variable_memory_pools', + 'fixed_memory_pools') + } + + def __init__(self, id): + if type(id) != gdb.Value and type(id) != int and type(id) != unicode: + raise TypeError('%s: must be gdb.Value, int, unicoded int' % (type(id))) + if type(id) == int: + id = gdb.Value(id) + self.id = id + if self.id.type.sizeof == 2: + self.idSize = self.OBJECT_16_BITS + else: + self.idSize = self.OBJECT_31_BITS + + def get(self, field): + if field in self.bits[self.idSize]: + bits = self.bits[self.idSize][field] + if bits[1] > 0: + return (int(self.id) >> bits[0]) & ((1 << (bits[1] - bits[0] + 1)) - 1) + return 0 + + def value(self): + return int(self.id) + + def index(self): + return self.get('index') + + def node(self): + return self.get('node') + + def api_val(self): + return self.get('api') + + def class_val(self): + return self.get('class') + + def api(self): + api = self.api_val() + if api < len(self.api_labels): + return self.api_labels[api] + return 'none' + + def _class(self): + api = self.api() + if api == 'none': + return 'invalid' + _class = self.class_val() + if _class < len(self.class_labels[api]): + return self.class_labels[api][_class] + return 'invalid' + + def valid(self): + return self.api() != 'none' and self._class() != 'invalid' + +class name: + """The Objects_Name can either be told what the name is or can take a + guess.""" + + def __init__(self, name, is_string = None): + self.name = name + if is_string == None: + self.is_string = 'auto' + else: + if is_string: + self.is_string = 'yes' + else: + self.is_string = 'no' + + def __str__(self): + if self.is_string != 'yes': + u32 = int(self.name['name_u32']) + s = chr((u32 >> 24) & 0xff) + \ + chr((u32 >> 16) & 0xff) + chr((u32 >> 8) & 0xff) + \ + chr(u32 & 0xff) + for c in range(0,4): + if s[c] < ' ' or s[c] > '~': + s = None + break + if s: + return s + return str(self.name['name_p'].dereference()) + +class control: + """The Objects_Control structure.""" + + def __init__(self, object): + self.object = object + self._id = ident(self.object['id']) + + def node(self): + return self.object['Node'] + + def id(self): + return self.object['id'] + + def name(self): + is_string = information.is_string(self._id.api(), self._id._class()) + return str(name(self.object['name'], is_string)) + +class id_printer: + """Print an object given the ID. Print using the struct display hint and an + iterator.""" + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, id): + self.id = id + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return int(self.id.value()) + elif self.count == 2: + return self.id.node() + elif self.count == 3: + return self.id.api() + elif self.count == 4: + return self.id._class() + elif self.count == 5: + return self.id.index() + raise StopIteration + + def __init__(self, id): + self.id = ident(id) + + def to_string(self): + return '' + + @staticmethod + def key(i): + if i == 0: + return 'id' + elif i == 1: + return 'node' + elif i == 2: + return 'api' + elif i == 3: + return 'class' + elif i == 4: + return 'index' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.id)) + + def display_hint (self): + return 'struct' + +class name_printer: + """Pretty printer for an object's name. It has to guess the type as no + information is available to help determine it.""" + + def __init__(self, name): + self.name = name(name) + + def to_string(self): + return gdb.Value(str(self.name)) + +class control_printer: + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, object): + self.object = object + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return self.object.node() + elif self.count == 2: + return self.object.id() + elif self.count == 3: + return self.object.name() + raise StopIteration + + def to_string(self): + return '' + + def __init__(self, object): + self.object = control(object) + + @staticmethod + def key(i): + if i == 0: + return 'Node' + elif i == 1: + return 'id' + elif i == 2: + return 'name' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.object)) + + def display_hint (self): + return 'struct' diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py new file mode 100644 index 0000000..e227c6f --- /dev/null +++ b/tools/gdb/python/rtems.py @@ -0,0 +1,110 @@ +# +# RTEMS Pretty Printers +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb +import re + +import objects +import threads +import classic + +nesting = 0 + +def type_from_value(val): + type = val.type; + # If it points to a reference, get the reference. + if type.code == gdb.TYPE_CODE_REF: + type = type.target () + # Get the unqualified type + return type.unqualified () + +def register_rtems_printers (obj): + "Register RTEMS pretty-printers with objfile Obj." + + if obj == None: + obj = gdb + + obj.pretty_printers.append (lookup_function) + +def lookup_function (val): + "Look-up and return a pretty-printer that can print val." + + global nesting + + typename = str(type_from_value(val)) + + for function in pp_dict: + if function.search (typename): + nesting += 1 + result = pp_dict[function] (val) + nesting -= 1 + if nesting == 0: + objects.information.invalidate() + return result + + # Cannot find a pretty printer. Return None. + return None + +def build_rtems_dict(): + pp_dict[re.compile('^rtems_id$')] = lambda val: objects.id_printer(val) + pp_dict[re.compile('^Objects_Id$')] = lambda val: objects.id_printer(val) + pp_dict[re.compile('^Objects_Name$')] = lambda val: objects.name_printer(val) + pp_dict[re.compile('^Objects_Control$')] = lambda val: objects.control_printer(val) + pp_dict[re.compile('^States_Control$')] = lambda val: threads.state_printer(val) + pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic.attribute_printer(val) + pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic.semaphore_printer(val) + +class rtems(gdb.Command): + """Prefix command for RTEMS.""" + + def __init__(self): + super(rtems, self).__init__('rtems', + gdb.COMMAND_STATUS, + gdb.COMPLETE_NONE, + True) + +class rtems_object(gdb.Command): + """Object sub-command for RTEMS""" + + objects = { + 'classic/semaphores': lambda id: classic.semaphore(id), + 'classic/tasks': lambda id: classic.task(id) + } + + def __init__(self): + self.__doc__ = 'Display the RTEMS object given a numeric ID.' + super(rtems_object, self).__init__('rtems object', + gdb.COMMAND_STATUS) + + def invoke(self, arg, from_tty): + for num in arg.split(): + try: + val = gdb.parse_and_eval(num) + num = int(val) + except: + print 'error: "%s" is not a number' % (num) + return + id = objects.ident(num) + if not id.valid(): + print 'Invalid object id' + print 'API:%s Class:%s Node:%d Index:%d Id:%08X' % \ + (id.api(), id._class(), id.node(), id.index(), id.value()) + objectname = id.api() + '/' + id._class() + if objectname in self.objects: + object = self.objects[objectname](id) + object.show(from_tty) + objects.information.invalidate() + +# +# Main +# +pp_dict = {} +build_rtems_dict() +gdb.pretty_printers = [] +gdb.pretty_printers.append (lookup_function) +rtems() +rtems_object() diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py new file mode 100644 index 0000000..906cf5a --- /dev/null +++ b/tools/gdb/python/threads.py @@ -0,0 +1,207 @@ +# +# RTEMS Threads Support +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb + +import chains +import objects + +def task_chain(chain): + tasks = [] + node = chain.first() + while not node.null(): + print node.addr + tasks.append(control(node.cast('Thread_Control'))) + node.next() + return tasks + +class state: + + ALL_SET = 0x000fffff + READY = 0x00000000 + DORMANT = 0x00000001 + SUSPENDED = 0x00000002 + TRANSIENT = 0x00000004 + DELAYING = 0x00000008 + WAITING_FOR_TIME = 0x00000010 + WAITING_FOR_BUFFER = 0x00000020 + WAITING_FOR_SEGMENT = 0x00000040 + WAITING_FOR_MESSAGE = 0x00000080 + WAITING_FOR_EVENT = 0x00000100 + WAITING_FOR_SEMAPHORE = 0x00000200 + WAITING_FOR_MUTEX = 0x00000400 + WAITING_FOR_CONDITION_VARIABLE = 0x00000800 + WAITING_FOR_JOIN_AT_EXIT = 0x00001000 + WAITING_FOR_RPC_REPLY = 0x00002000 + WAITING_FOR_PERIOD = 0x00004000 + WAITING_FOR_SIGNAL = 0x00008000 + WAITING_FOR_BARRIER = 0x00010000 + WAITING_FOR_RWLOCK = 0x00020000 + INTERRUPTIBLE_BY_SIGNAL = 0x10000000 + LOCALLY_BLOCKED = \ + WAITING_FOR_BUFFER | \ + WAITING_FOR_SEGMENT | \ + WAITING_FOR_MESSAGE | \ + WAITING_FOR_SEMAPHORE | \ + WAITING_FOR_MUTEX | \ + WAITING_FOR_CONDITION_VARIABLE | \ + WAITING_FOR_JOIN_AT_EXIT | \ + WAITING_FOR_SIGNAL | \ + WAITING_FOR_BARRIER | \ + WAITING_FOR_RWLOCK + WAITING_ON_THREAD_QUEUE = \ + LOCALLY_BLOCKED | WAITING_FOR_RPC_REPLY + BLOCKED = \ + DELAYING | \ + WAITING_FOR_TIME | \ + WAITING_FOR_PERIOD | \ + WAITING_FOR_EVENT | \ + WAITING_ON_THREAD_QUEUE | \ + INTERRUPTIBLE_BY_SIGNAL + + masks = { + ALL_SET : 'all-set', + READY : 'ready', + DORMANT : 'dormant', + SUSPENDED : 'suspended', + TRANSIENT : 'transient', + DELAYING : 'delaying', + WAITING_FOR_TIME : 'waiting-for-time', + WAITING_FOR_BUFFER : 'waiting-for-buffer', + WAITING_FOR_SEGMENT : 'waiting-for-segment', + WAITING_FOR_MESSAGE : 'waiting-for-message', + WAITING_FOR_EVENT : 'waiting-for-event', + WAITING_FOR_SEMAPHORE : 'waiting-for-semaphore', + WAITING_FOR_MUTEX : 'waiting-for-mutex', + WAITING_FOR_CONDITION_VARIABLE : 'waiting-for-condition-variable', + WAITING_FOR_JOIN_AT_EXIT : 'waiting-for-join-at-exit', + WAITING_FOR_RPC_REPLY : 'waiting-for-rpc-reply', + WAITING_FOR_PERIOD : 'waiting-for-period', + WAITING_FOR_SIGNAL : 'waiting-for-signal', + WAITING_FOR_BARRIER : 'waiting-for-barrier', + WAITING_FOR_RWLOCK : 'waiting-for-rwlock' + } + + def __init__(self, s): + self.s = s + + def to_string(self): + if (self.s & self.LOCALLY_BLOCKED) == self.LOCALLY_BLOCKED: + return 'locally-blocked' + if (self.s & self.WAITING_ON_THREAD_QUEUE) == self.WAITING_ON_THREAD_QUEUE: + return 'waiting-on-thread-queue' + if (self.s & self.BLOCKED) == self.BLOCKED: + return 'blocked' + s = ',' + for m in self.masks: + if (self.s & m) == m: + s = self.masks[m] + ',' + return s[:-1] + +class wait_info: + + def __init__(self, info): + self.info = info + + def id(self): + return self.info['id'] + + def count(self): + return self.info['count'] + + def return_arg(self): + return self.info['return_argument'] + + def option(self): + return self.info['option'] + + def block2n(self): + return task_chain(chains.control(self.info['Block2n'])) + + def queue(self): + return task_chain(chains.control(self.info['queue'])) + +class control: + + def __init__(self, ctrl): + self.ctrl = ctrl + self.object = objects.control(ctrl['Object']) + + def id(self): + return self.object.id() + + def name(self): + return self.object.name() + + def current_state(self): + return state(self.ctrl['current_state']).to_string() + + def current_priority(self): + return self.ctrl['current_priority'] + + def real_priority(self): + return self.ctrl['real_priority'] + + def suspends(self): + return self.ctrl['suspend_count'] + + def post_task_switch_ext(self): + return self.ctrl['do_post_task_switch_extension'] + + def preemptible(self): + return self.ctrl['is_preemptible'] + + def cpu_time_budget(self): + return self.ctrl['cpu_time_budget'] + + def wait_info(self): + return wait_info(self.ctrl['Wait']) + + def brief(self): + return "'%s' (c:%d, r:%d)" % \ + (self.name(), self.current_priority(), self.real_priority()) + +class queue: + """Manage the Thread_queue_Control.""" + + priority_headers = 4 + + def __init__(self, que): + self.que = que + + def fifo(self): + return str(self.que['discipline']) == 'THREAD_QUEUE_DISCIPLINE_FIFO' + + def priority(self): + return str(self.que['discipline']) == 'THREAD_QUEUE_DISCIPLINE_PRIORITY' + + def state(self): + return state(self.que['state']).to_string() + + def tasks(self): + if self.fifo(): + t = task_chain(chains.control(self.que['Queues']['Fifo'])) + else: + t = [] + for ph in range(0, self.priority_headers): + t.extend(task_chain(chains.control(self.que['Queues']['Fifo']))) + return t + + def to_string(self): + if self.fifo(): + s = 'fifo' + else: + s = 'priority' + return + +class state_printer: + + def __init__(self, s): + self.s = state(s) + + def to_string(self): + return self.s.to_string() diff --git a/tools/gdb/python/watchdog.py b/tools/gdb/python/watchdog.py new file mode 100644 index 0000000..0766575 --- /dev/null +++ b/tools/gdb/python/watchdog.py @@ -0,0 +1,56 @@ +# +# RTEMS Watchdog Support +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb + +import chains +import objects + +class state: + + INACTIVE = 0 + BEING_INSERTED = 1 + ACTIVE = 2 + REMOVE_IT = 3 + + states = { + 0: 'inactive', + 1: 'being-inserted', + 2: 'active', + 3: 'remove-it' + } + + def __init__(self, s): + self.s = s + + def to_string(self): + return self.states[self.s] + +class control: + + def __init__(self, ctrl): + self.ctrl = ctrl + + def state(self): + return state(self.ctrl['state']).to_string() + + def initial(self): + return self.ctrl['initial'] + + def delta_interval(self): + return self.ctrl['delta_interval'] + + def start_time(self): + return self.ctrl['start_time'] + + def stop_time(self): + return self.ctrl['stop_time'] + + def routine(self): + addr = self.ctrl['routine'] + sym = gdb.lookup_symbol(addr) + print sym From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Remove the header. Message-ID: <20140824234537.479F270080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 5a4834c6415f5e621bc753744fe6fafbb064aca0 Changeset: http://git.rtems.org/rtems-tools/commit/?id=5a4834c6415f5e621bc753744fe6fafbb064aca0 Author: Dhananjay Balan Date: Mon Aug 26 21:23:59 2013 +0530 Remove the header. --- tools/gdb/python/rtems.py | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 5f0aa7d..6c987cf 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -229,7 +229,6 @@ class rtems_watchdog_chain(gdb.Command): nd = inst.first() i = 0 - print ' Ticks Chain' while not nd.null(): wd = watchdog.control(nd.cast('Watchdog_Control')) print ' #'+str(i) From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Fix README mistakes. Message-ID: <20140824234535.E3E4D700A5B@git.rtems.org> Module: rtems-tools Branch: master Commit: 4dbd0db60d1d0a3af7c2311911d6a6a638ccca84 Changeset: http://git.rtems.org/rtems-tools/commit/?id=4dbd0db60d1d0a3af7c2311911d6a6a638ccca84 Author: Chris Johns Date: Mon Aug 25 09:48:23 2014 +1000 Fix README mistakes. --- README | 12 +++++++----- 1 files changed, 7 insertions(+), 5 deletions(-) diff --git a/README b/README index 9325e0d..be8aacd 100644 --- a/README +++ b/README @@ -10,13 +10,15 @@ All tools are distributed as source code. They should work on a range of host computers. Windows support may be via cross building on suitable Unix systems. The tools contained in this package each come with documentation so please -locate and refer to it. +locate and refer to that. The RTEMS Tools Project has been developed for the RTEMS Project however these -tools can be used for a range of things no relate to RTEMS. The RTEMS Project -welcomes this and +tools can be used for a range of things not related to RTEMS. The RTEMS Project +welcomes this. If you have a problem or question post to rtems-user at rtems.org or drop by the -RTEMS IRC channel #rtems on chat.freenode.net. Drop by and tell us is you are -using this tools for other uses. +RTEMS IRC channel #rtems on chat.freenode.net. Drop by and tell us if you are +using these tools for other uses. +If you have any patches please post them to the devel at rtems.org mailing list in +git format patches with your details. From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Categories the commands. Message-ID: <20140824234536.6F28D700B15@git.rtems.org> Module: rtems-tools Branch: master Commit: d4fc2d5e54adb8d0f48d94166e5e41926e3f47e3 Changeset: http://git.rtems.org/rtems-tools/commit/?id=d4fc2d5e54adb8d0f48d94166e5e41926e3f47e3 Author: Dhananjay Balan Date: Tue Aug 20 22:16:16 2013 +0530 Categories the commands. The subcommands fall onto DATA. See http://sourceware.org/gdb/onlinedocs/gdb/Commands-In-Python.html#Commands-In-Python --- tools/gdb/python/rtems.py | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index c45d72e..718701c 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -36,9 +36,11 @@ class rtems_object(gdb.Command): } def __init__(self): - self.__doc__ = 'Display the RTEMS object given a numeric ID (Or a reference to rtems_object).' + self.__doc__ = 'Display the RTEMS object given a numeric ID \ + (Or a reference to rtems_object).' super(rtems_object, self).__init__('rtems object', - gdb.COMMAND_STATUS) + gdb.COMMAND_DATA, + gdb.COMPLETE_SYMBOL) def invoke(self, arg, from_tty): for num in arg.split(): @@ -71,8 +73,8 @@ class rtems_semaphore(gdb.Command): def __init__(self): self.__doc__ = 'Display the RTEMS semaphores by index' - super(rtems_semaphore, self).__init__('rtems semaphore', - gdb.COMMAND_STATUS) + super(rtems_semaphore, self).__init__( 'rtems semaphore', + gdb.COMMAND_DATA, gdb.COMPLETE_NONE ) def invoke(self, arg, from_tty): for val in arg.split(): @@ -101,7 +103,8 @@ class rtems_task(gdb.Command): def __init__(self): self.__doc__ = 'Display the RTEMS tasks by index(s)' - super(rtems_task,self).__init__('rtems task', gdb.COMMAND_STATUS) + super(rtems_task,self).__init__('rtems task', + gdb.COMMAND_DATA, gdb.COMPLETE_NONE) def invoke(self, arg, from_tty): for val in arg.split(): @@ -130,7 +133,9 @@ class rtems_message_queue(gdb.Command): def __init__(self): self.__doc__ = 'Display the RTEMS message_queue by index(s)' - super(rtems_message_queue,self).__init__('rtems mqueue', gdb.COMMAND_STATUS) + super(rtems_message_queue,self).__init__('rtems mqueue', + gdb.COMMAND_DATA, + gdb.COMPLETE_NONE) def invoke(self, arg, from_tty): for val in arg.split(): From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] gdb-python: Clean up and ignore waf generated files. Message-ID: <20140824234536.E2F3170080E@git.rtems.org> Module: rtems-tools Branch: master Commit: f750e82bbc904a60ea40116e34fa0a5495020c85 Changeset: http://git.rtems.org/rtems-tools/commit/?id=f750e82bbc904a60ea40116e34fa0a5495020c85 Author: Chris Johns Date: Mon Aug 25 09:39:26 2014 +1000 gdb-python: Clean up and ignore waf generated files. --- tools/gdb/python/.gitignore | 36 ++---------------------------------- 1 files changed, 2 insertions(+), 34 deletions(-) diff --git a/tools/gdb/python/.gitignore b/tools/gdb/python/.gitignore index d2d6f36..7b4e3af 100644 --- a/tools/gdb/python/.gitignore +++ b/tools/gdb/python/.gitignore @@ -1,35 +1,3 @@ -*.py[cod] - -# C extensions -*.so - -# Packages -*.egg -*.egg-info -dist +*.pyc +.lock-waf* build -eggs -parts -bin -var -sdist -develop-eggs -.installed.cfg -lib -lib64 - -# Installer logs -pip-log.txt - -# Unit test / coverage reports -.coverage -.tox -nosetests.xml - -# Translations -*.mo - -# Mr Developer -.mr.developer.cfg -.project -.pydevproject From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Refactor Message-ID: <20140824234537.1E72C700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 6d89e3c34e68e61013abb39ff058bc5715eaa455 Changeset: http://git.rtems.org/rtems-tools/commit/?id=6d89e3c34e68e61013abb39ff058bc5715eaa455 Author: Dhananjay Balan Date: Thu Aug 1 12:38:23 2013 +0530 Refactor - The objects are intialized using the objects rather than the ID. --- tools/gdb/python/classic.py | 36 +++++++++++++++--------------------- tools/gdb/python/rtems.py | 18 ++++++++++-------- 2 files changed, 25 insertions(+), 29 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 50514ff..29ffab5 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -108,9 +108,8 @@ class attribute: class semaphore: "Print a classic semaphore." - def __init__(self, id): - self.id = id; - self.object = objects.information.object(self.id).dereference() + def __init__(self, obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'semaphore') @@ -149,10 +148,10 @@ class semaphore: class task: "Print a classic task" - def __init__(self, id): - self.id = id; + def __init__(self, obj): + self.object = obj self.task = \ - threads.control(objects.information.object(self.id).dereference()) + threads.control(self.object) self.wait_info = self.task.wait_info() def show(self, from_tty): @@ -167,9 +166,8 @@ class task: class message_queue: "Print classic messege queue" - def __init__(self,id): - self.id = id - self.object = objects.information.object(self.id).dereference() + def __init__(self,obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], \ 'message_queue') @@ -187,9 +185,8 @@ class message_queue: class timer: '''Print a classic timer''' - def __init__(self, id): - self.id = id - self.object = objects.information.object(self.id).dereference() + def __init__(self, obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.watchdog = watchdog.control(self.object['Ticker']) @@ -200,9 +197,8 @@ class timer: class partition: ''' Print a rtems partition ''' - def __init__(self, id): - self.id = id - self.object = objects.information.object(self.id).dereference() + def __init__(self, obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'partition') self.starting_addr = self.object['starting_address'] @@ -221,9 +217,8 @@ class partition: class region: "prints a classic region" - def __init__(self,id): - self.id = id - self.object = objects.information.object(self.id).dereference() + def __init__(self,obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'region') self.wait_queue = threads.queue(self.object['Wait_queue']) @@ -239,9 +234,8 @@ class region: class barrier: '''classic barrier abstraction''' - def __init__(self,id): - self.id = id - self.object = objects.information.object(self.id).dereference() + def __init__(self,obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'],'barrier') self.core_b_control = supercore.barrier_control(self.object['Barrier']) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index adab86d..b2dc776 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -75,13 +75,13 @@ class rtems_object(gdb.Command): """Object sub-command for RTEMS""" objects = { - 'classic/semaphores': lambda id: classic.semaphore(id), - 'classic/tasks': lambda id: classic.task(id), - 'classic/message_queues': lambda id: classic.message_queue(id), - 'classic/timers' : lambda id: classic.timer(id), - 'classic/partitions' : lambda id: classic.partition(id), - 'classic/regions' : lambda id: classic.region(id), - 'classic/barriers' : lambda id: classic.barrier(id) + 'classic/semaphores': lambda obj: classic.semaphore(obj), + 'classic/tasks': lambda obj: classic.task(obj), + 'classic/message_queues': lambda obj: classic.message_queue(obj), + 'classic/timers' : lambda obj: classic.timer(obj), + 'classic/partitions' : lambda obj: classic.partition(obj), + 'classic/regions' : lambda obj: classic.region(obj), + 'classic/barriers' : lambda obj: classic.barrier(obj) } def __init__(self): @@ -103,8 +103,10 @@ class rtems_object(gdb.Command): print 'API:%s Class:%s Node:%d Index:%d Id:%08X' % \ (id.api(), id._class(), id.node(), id.index(), id.value()) objectname = id.api() + '/' + id._class() + + obj = objects.information.object(id).dereference() if objectname in self.objects: - object = self.objects[objectname](id) + object = self.objects[objectname](obj) object.show(from_tty) objects.information.invalidate() From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Complete index subcommands. Message-ID: <20140824234537.80060700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 8da0a3745770547d1ebdcaca97702087ce4bc8a5 Changeset: http://git.rtems.org/rtems-tools/commit/?id=8da0a3745770547d1ebdcaca97702087ce4bc8a5 Author: Dhananjay Balan Date: Wed Aug 21 18:49:01 2013 +0530 Complete index subcommands. --- tools/gdb/python/rtems.py | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 48 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 7d26542..b142f23 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -136,3 +136,51 @@ class rtems_message_queue(rtems_index): def instance(self,obj): return classic.message_queue(obj) +class rtems_timer(rtems_index): + '''Index subcommand''' + + _class = 'timers' + + def __init__(self): + self.__doc__ = 'Display RTEMS timer(s) by index(es)' + super(rtems_timer, self).__init__('rtems timer') + + def instance(self,obj): + return classic.timer(obj) + +class rtems_partition(rtems_index): + '''Partition subcommand''' + + _class = 'partitions' + + def __init__(self): + self.__doc__ = 'Display RTEMS partition(s) by index(es)' + super(rtems_partition, self).__init__('rtems partition') + + def instance(self, obj): + return classic.partition(obj) + +class rtems_region(rtems_index): + '''Region subcomamnd''' + + _class = 'regions' + + def __init__(self): + self.__doc__ = 'Display RTEMS region(s) by index(es)' + super(rtems_region , self).__init__('rtems regions') + + def instance(self, obj): + return classic.region(obj) + +class rtems_barrier(rtems_index): + '''Barrier subcommand''' + + _class = 'barriers' + + def __init__(self): + self.__doc__ = 'Display RTEMS barrier(s) by index(es)' + super(rtems_barrier , self).__init__('rtems barrier') + + def instance(self, obj): + return classic.barrier(obj) + From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add helper func. Message-ID: <20140824234537.AB8C270080E@git.rtems.org> Module: rtems-tools Branch: master Commit: a4d0739522651592f5f2b45e51f3957f3d11cdeb Changeset: http://git.rtems.org/rtems-tools/commit/?id=a4d0739522651592f5f2b45e51f3957f3d11cdeb Author: Dhananjay Balan Date: Sun Aug 25 23:22:20 2013 +0530 Add helper func. - tests a bit at specified position. --- tools/gdb/python/helper.py | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/helper.py b/tools/gdb/python/helper.py index 146ee69..dfd01eb 100644 --- a/tools/gdb/python/helper.py +++ b/tools/gdb/python/helper.py @@ -16,3 +16,6 @@ def type_from_value(val): type = type.target () # Get the unqualified type return type.unqualified () + +def test_bit(val, pos): + return bool(val & (1 << (pos-1))) \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Catch empty task names, Message-ID: <20140824234537.B75B0700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 7a415d4e43de67e0eabcca3a1375c4e530f37a07 Changeset: http://git.rtems.org/rtems-tools/commit/?id=7a415d4e43de67e0eabcca3a1375c4e530f37a07 Author: Dhananjay Balan Date: Sat Aug 24 20:44:06 2013 +0530 Catch empty task names, - All the tasks do not have a name. --- tools/gdb/python/classic.py | 2 ++ tools/gdb/python/objects.py | 9 ++++++++- tools/gdb/python/threads.py | 6 ++++-- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index b919383..261f648 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -140,6 +140,8 @@ class semaphore: tasks = wait_queue.tasks() print ' Queue: len = %d, state = %s' % (len(tasks), wait_queue.state()) + print ' Tasks:' + print ' Name (c:current, r:real), (id)' for t in range(0, len(tasks)): print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) else: diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 58c2730..f4ae5e1 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -253,4 +253,11 @@ class control: def name(self): is_string = information.is_string(self._id.api(), self._id._class()) - return str(name(self.object['name'], is_string)) \ No newline at end of file + val = str(name(self.object['name'],is_string)) + + # Normal comaprision is a bit tricky with quotes + # 0 '\000' in hex == '3020275c30303027' + if val.encode('hex') == '3020275c30303027': + val = "" + + return val \ No newline at end of file diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py index 77c7efa..7098481 100644 --- a/tools/gdb/python/threads.py +++ b/tools/gdb/python/threads.py @@ -6,7 +6,6 @@ # import gdb - import chains import objects @@ -134,7 +133,10 @@ class control: return self.object.id() def name(self): - return self.object.name() + val = self.object.name() + if val == "": + val = '*' + return val def current_state(self): return state(self.ctrl['current_state']).to_string() From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add watchdog seconds command Message-ID: <20140824234537.4DF01700810@git.rtems.org> Module: rtems-tools Branch: master Commit: 61154bf302d5f022b54094e0fc58e9a0fc00f983 Changeset: http://git.rtems.org/rtems-tools/commit/?id=61154bf302d5f022b54094e0fc58e9a0fc00f983 Author: Dhananjay Balan Date: Mon Aug 26 21:14:30 2013 +0530 Add watchdog seconds command - prints the watchdog chain managed at second boundaries. --- tools/gdb/python/main.py | 3 ++- tools/gdb/python/objects.py | 1 + tools/gdb/python/rtems.py | 8 ++++++++ 3 files changed, 11 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/main.py b/tools/gdb/python/main.py index a0ff7dc..6fb7c54 100644 --- a/tools/gdb/python/main.py +++ b/tools/gdb/python/main.py @@ -18,4 +18,5 @@ rtems.rtems_semaphore() rtems.rtems_task() rtems.rtems_message_queue() rtems.rtems_tod() -rtems.rtems_wdt() \ No newline at end of file +rtems.rtems_wdt() +rtems.rtems_wsec() \ No newline at end of file diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index ae2a4c7..ee59cbc 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -15,6 +15,7 @@ class infotables: tables_types = { 'internal/time' : ('TOD_Control', '_TOD'), 'internal/wdticks' : ('Chain_Control', '_Watchdog_Ticks_chain'), + 'internal/wdseconds' : ('Chain_Control', '_Watchdog_Seconds_chain'), 'classic/tasks' : ('Thread_Control', '_RTEMS_tasks_Information'), 'classic/timers' : ('Timer_Control', '_Timer_Information'), diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 340c7ff..5f0aa7d 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -245,3 +245,11 @@ class rtems_wdt(rtems_watchdog_chain): self.__doc__ = 'Display watchdog ticks chain' super(rtems_wdt, self).__init__('rtems wdticks') +class rtems_wsec(rtems_watchdog_chain): + + _class = 'wdseconds' + + def __init__(self): + self.__doc__ = 'Display watchdog seconds chain' + super(rtems_wsec, self).__init__('rtems wdseconds') + From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] gdb-python: Add waf script to install under a prefix. Message-ID: <20140824234537.CF124700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 504e1de9de483f6f8ba54c5424c2327db1be6755 Changeset: http://git.rtems.org/rtems-tools/commit/?id=504e1de9de483f6f8ba54c5424c2327db1be6755 Author: Chris Johns Date: Mon Aug 25 09:40:57 2014 +1000 gdb-python: Add waf script to install under a prefix. --- tools/gdb/python/wscript | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/wscript b/tools/gdb/python/wscript new file mode 100644 index 0000000..22d44e8 --- /dev/null +++ b/tools/gdb/python/wscript @@ -0,0 +1,23 @@ +# +# Install the RTEMS gdb python +# + +def configure(conf): + conf.load('python') + +def build(bld): + bld.install_files('${PREFIX}/share/gdb/python/rtems', + ['chains.py', + 'classic.py', + 'classic_printer.py', + 'heaps.py', + 'helper.py', + 'main.py', + 'objects.py', + 'pretty.py', + 'rtems.py', + 'sparc.py', + 'supercore.py', + 'supercore_printer.py', + 'threads.py', + 'watchdog.py']) From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Move todo Message-ID: <20140824234537.893E9700814@git.rtems.org> Module: rtems-tools Branch: master Commit: e282b6efcb7b5cc5611d829663171b5bda9d3bb6 Changeset: http://git.rtems.org/rtems-tools/commit/?id=e282b6efcb7b5cc5611d829663171b5bda9d3bb6 Author: Dhananjay Balan Date: Mon Jul 29 16:42:24 2013 +0530 Move todo Why else is there issues? --- tools/gdb/python/README.md | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 6dc9b5e..8858a4f 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -4,7 +4,3 @@ rtems-gdb GDB extenstions to RTEMS. See [this blog post for instructions](http://dbalan.github.io/blog/2013/06/23/debugging-rtems-with-gdb/) - -TODO: - - classic abstractions address on id - change this to more proper hierarchy. - - Inherit from object_control class From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Add region support. Message-ID: <20140824234537.5474E700679@git.rtems.org> Module: rtems-tools Branch: master Commit: b9ee5df588aa1a4cf0a64cf511b0585309ff5510 Changeset: http://git.rtems.org/rtems-tools/commit/?id=b9ee5df588aa1a4cf0a64cf511b0585309ff5510 Author: Dhananjay Balan Date: Sun Jul 28 15:03:58 2013 +0530 Add region support. Abstractions for classic/region added. --- tools/gdb/python/classic.py | 27 ++++++++++++++++++++++++--- tools/gdb/python/heaps.py | 28 +++++++++++++++++++++++++--- tools/gdb/python/helper.py | 2 +- tools/gdb/python/objects.py | 2 +- tools/gdb/python/rtems.py | 3 ++- tools/gdb/python/supercore.py | 2 +- 6 files changed, 54 insertions(+), 10 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index f7d4dfc..e2ecfaa 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -8,10 +8,13 @@ import gdb import itertools import re +#ToDo This shouldn't be here +import helper import objects import threads import watchdog +import heaps import supercore class attribute: @@ -41,7 +44,8 @@ class attribute: 'barrier'], 'message_queue' : ['priority', 'scope'], - 'partition' : ['scope'] + 'partition' : ['scope'], + 'region' : ['priority'] } masks = { @@ -214,6 +218,23 @@ class partition: print ' Name:', self.object_control.name() print ' Attr:', self.attr.to_string() print ' Length:', self.length - print 'Buffer Size:', self.buffer_size - print 'Used Blocks:', self.used_blocks + print ' B Size:', self.buffer_size + print ' U Blocks:', self.used_blocks +class region: + "prints a classic region" + + def __init__(self,id): + self.id = id + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.attr = attribute(self.object['attribute_set'], 'region') + self.wait_queue = threads.queue(self.object['Wait_queue']) + self.heap = heaps.control(self.object['Memory']) + + def show(self, from_tty): + print ' Name:', self.object_control.name() + print ' Attr:', self.attr.to_string() + helper.tasks_printer_routine(self.wait_queue) + print ' Memory:' + self.heap.show() diff --git a/tools/gdb/python/heaps.py b/tools/gdb/python/heaps.py index 4798912..2cc7907 100644 --- a/tools/gdb/python/heaps.py +++ b/tools/gdb/python/heaps.py @@ -15,6 +15,8 @@ class block: return False return True + def val(self): + return str(self.block) def next(self): if not self.null(): @@ -25,11 +27,15 @@ class block: self.block = self.block['prev'] class stats: - ''heap statistics'' + '''heap statistics''' def __init__(self,stat): self.stat = stat + def inst(self): + i = self.stat['instance'] + return i + def avail(self): val = self.stat['size'] return val @@ -37,9 +43,14 @@ class stats: def free(self): return self.stat['free_size'] + def show(self): + print ' Instance:',self.inst() + print ' Avail:',self.avail() + print ' Free:',self.free() + # ToDo : incorporate others -def control: +class control: '''Abstract a heap control structure''' def __init__(self, ctl): @@ -59,4 +70,15 @@ def control: def stat(self): st = stats(self.ctl['stats']) - return st \ No newline at end of file + return st + + def show(self): + fi = self.first() + la = self.last() + + print ' First:', fi.val() + print ' Last:', la.val() + + stats = self.stat() + print ' stats:' + stats.show() \ No newline at end of file diff --git a/tools/gdb/python/helper.py b/tools/gdb/python/helper.py index ec17400..c9c9a42 100644 --- a/tools/gdb/python/helper.py +++ b/tools/gdb/python/helper.py @@ -1,7 +1,7 @@ # # RTEMS GDB support helper routins. -def tasks_printer_rotuine(wait_queue): +def tasks_printer_routine(wait_queue): tasks = wait_queue.tasks() print ' Queue: len = %d, state = %s' % (len(tasks),wait_queue.state()) for t in range(0, len(tasks)): diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index c433039..1a64a8d 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -18,7 +18,7 @@ class infotables: 'classic/semaphores' : ('Semaphore_Control', '_Semaphore_Information'), 'classic/message_queues' : ('Message_queue_Control', '_Message_queue_Information'), 'classic/partitions' : ('Partition_Control', '_Partition_Information'), - 'classic/regions' : ('Region_Control', '_Regions_Information'), + 'classic/regions' : ('Region_Control', '_Region_Information'), 'classic/ports' : ('Port_Control', '_Port_Information'), 'classic/periods' : ('Period_Control', '_Period_Information'), 'classic/extensions' : ('Extension_Control', '_Extension_Information'), diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index eac5042..8738736 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -79,7 +79,8 @@ class rtems_object(gdb.Command): 'classic/tasks': lambda id: classic.task(id), 'classic/message_queues': lambda id: classic.message_queue(id), 'classic/timers' : lambda id: classic.timer(id), - 'classic/partitions' : lambda id: classic.partition(id) + 'classic/partitions' : lambda id: classic.partition(id), + 'classic/regions' : lambda id: classic.region(id) } def __init__(self): diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py index 7e958b1..073bbd0 100644 --- a/tools/gdb/python/supercore.py +++ b/tools/gdb/python/supercore.py @@ -15,4 +15,4 @@ class CORE_message_queue: # self.buffer def show(self): - helper.tasks_printer_rotuine(self.wait_queue) + helper.tasks_printer_routine(self.wait_queue) From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Refactor Message-ID: <20140824234536.B9CCB700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 8d035f8556f5c121b709c1cd6ed223fa2b70b66c Changeset: http://git.rtems.org/rtems-tools/commit/?id=8d035f8556f5c121b709c1cd6ed223fa2b70b66c Author: Dhananjay Balan Date: Tue Aug 20 22:05:22 2013 +0530 Refactor - pretty printers moved to pretty module - command and subcommands get own module --- tools/gdb/python/__init__.py | 20 +----------- tools/gdb/python/helper.py | 12 +++++++- tools/gdb/python/main.py | 19 +++++++++++ tools/gdb/python/pretty.py | 53 ++++++++++++++++++++++++++++++++ tools/gdb/python/rtems.py | 69 +---------------------------------------- 5 files changed, 86 insertions(+), 87 deletions(-) diff --git a/tools/gdb/python/__init__.py b/tools/gdb/python/__init__.py index 694eb06..36d2c06 100644 --- a/tools/gdb/python/__init__.py +++ b/tools/gdb/python/__init__.py @@ -3,24 +3,6 @@ if __name__ == "__main__": import sys import os.path sys.path.append(os.path.dirname(__file__)) - import supercore - import chains - import rtems - import classic - import objects - import threads - - import supercore_printer - import classic_printer - - # Needed inorder to reload code from inside gdb - reload(supercore) - reload(chains) - reload(rtems) - reload(classic) - reload(objects) - reload(threads) - reload(supercore_printer) - reload(classic_printer) + import main print 'RTEMS GDB Support loaded' diff --git a/tools/gdb/python/helper.py b/tools/gdb/python/helper.py index c9c9a42..146ee69 100644 --- a/tools/gdb/python/helper.py +++ b/tools/gdb/python/helper.py @@ -1,8 +1,18 @@ # # RTEMS GDB support helper routins. +import gdb + def tasks_printer_routine(wait_queue): tasks = wait_queue.tasks() print ' Queue: len = %d, state = %s' % (len(tasks),wait_queue.state()) for t in range(0, len(tasks)): - print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) \ No newline at end of file + print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) + +def type_from_value(val): + type = val.type; + # If it points to a reference, get the reference. + if type.code == gdb.TYPE_CODE_REF: + type = type.target () + # Get the unqualified type + return type.unqualified () diff --git a/tools/gdb/python/main.py b/tools/gdb/python/main.py new file mode 100644 index 0000000..2ef475a --- /dev/null +++ b/tools/gdb/python/main.py @@ -0,0 +1,19 @@ +# +# RTEMS GDB Extensions +# +# main + +import gdb +import pretty +import rtems + +gdb.pretty_printers = [] +gdb.pretty_printers.append(pretty.lookup_function) + +# Register commands +# rtems and subcommands +rtems.rtems() +rtems.rtems_object() +rtems.rtems_semaphore() +rtems.rtems_task() +rtems.rtems_message_queue() \ No newline at end of file diff --git a/tools/gdb/python/pretty.py b/tools/gdb/python/pretty.py new file mode 100644 index 0000000..929c245 --- /dev/null +++ b/tools/gdb/python/pretty.py @@ -0,0 +1,53 @@ +# +# RTEMS pretty printers +# +import re +import helper +import objects + +import supercore_printer +import classic_printer + +pretty_printer = { + + '^rtems_id$' : supercore_printer.id, + '^Objects_Id$' : supercore_printer.id, + '^Objects_Name$' : supercore_printer.name, + '^Objects_Control$' : supercore_printer.control, + '^States_Control$' : supercore_printer.state, + '^rtems_attribute$' : classic_printer.attribute, + '^Semaphore_Control$' : classic_printer.semaphore +} + + +def build_pretty_printer (): + pp_dict = {} + + for name in pretty_printer: + pp_dict[re.compile(name)] = pretty_printer[name] + + return pp_dict + +def lookup_function (val): + "Look-up and return a pretty-printer that can print val." + + global nesting + + typename = str(helper.type_from_value(val)) + + for function in pp_dict: + if function.search (typename): + nesting += 1 + result = pp_dict[function] (val) + nesting -= 1 + if nesting == 0: + objects.information.invalidate() + return result + + # Cannot find a pretty printer. Return None. + return None + +# ToDo: properly document. +nesting = 0 + +pp_dict = build_pretty_printer() diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 9ae2105..c45d72e 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -12,55 +12,6 @@ import objects import threads import classic -# ToDo: Move every printing out -import supercore_printer -import classic_printer - -nesting = 0 - -def type_from_value(val): - type = val.type; - # If it points to a reference, get the reference. - if type.code == gdb.TYPE_CODE_REF: - type = type.target () - # Get the unqualified type - return type.unqualified () - -def register_rtems_printers (obj): - "Register RTEMS pretty-printers with objfile Obj." - - if obj == None: - obj = gdb - - obj.pretty_printers.append (lookup_function) - -def lookup_function (val): - "Look-up and return a pretty-printer that can print val." - - global nesting - - typename = str(type_from_value(val)) - - for function in pp_dict: - if function.search (typename): - nesting += 1 - result = pp_dict[function] (val) - nesting -= 1 - if nesting == 0: - objects.information.invalidate() - return result - - # Cannot find a pretty printer. Return None. - return None - -def build_rtems_dict(): - pp_dict[re.compile('^rtems_id$')] = lambda val: supercore_printer.id(val) - pp_dict[re.compile('^Objects_Id$')] = lambda val: supercore_printer.id(val) - pp_dict[re.compile('^Objects_Name$')] = lambda val: supercore_printer.name(val) - pp_dict[re.compile('^Objects_Control$')] = lambda val: supercore_printer.control(val) - pp_dict[re.compile('^States_Control$')] = lambda val: supercore_printer.state(val) - pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic_printer.attribute(val) - pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic_printer.semaphore(val) class rtems(gdb.Command): """Prefix command for RTEMS.""" @@ -157,8 +108,7 @@ class rtems_task(gdb.Command): try: index = int(val) except ValueError: - print "error: %s is not an index" % (val) - return + raise gdb.GdbError( "Value is not an integer") try: obj = objects.information.object_return(self.api, @@ -198,21 +148,6 @@ class rtems_message_queue(gdb.Command): print "error: index %s is invalid" % (index) return - print "Ahi" instance = classic.message_queue(obj) instance.show(from_tty) - objects.information.invalidate() - - -# -# Main -# -pp_dict = {} -build_rtems_dict() -gdb.pretty_printers = [] -gdb.pretty_printers.append (lookup_function) -rtems() -rtems_object() -rtems_semaphore() -rtems_task() -rtems_message_queue() \ No newline at end of file + objects.information.invalidate() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Add task subcommand Message-ID: <20140824234537.E0910700814@git.rtems.org> Module: rtems-tools Branch: master Commit: a71368892a2010c9a2b8e9ae3ce1c23742b296c3 Changeset: http://git.rtems.org/rtems-tools/commit/?id=a71368892a2010c9a2b8e9ae3ce1c23742b296c3 Author: Dhananjay Balan Date: Fri Aug 9 18:02:18 2013 +0530 Add task subcommand rtems tasks - Prints tasks by index. --- tools/gdb/python/rtems.py | 33 ++++++++++++++++++++++++++++++++- 1 files changed, 32 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index cf1ae07..8eb49c9 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -138,6 +138,36 @@ class rtems_semaphore(gdb.Command): instance.show(from_tty) objects.information.invalidate() +class rtems_task(gdb.Command): + '''tasks subcommand for rtems''' + + api = 'classic' + _class = 'tasks' + + def __init__(self): + self.__doc__ = 'Display the RTEMS tasks by index(s)' + super(rtems_task,self).__init__('rtems task', gdb.COMMAND_STATUS) + + def invoke(self, arg, from_tty): + for val in arg.split(): + try: + index = int(val) + except ValueError: + print "error: %s is not an index" % (val) + return + + try: + obj = objects.information.object_return(self.api, + self._class, + index).dereference() + except IndexError: + print "error: index %s is invalid" % (index) + return + + instance = classic.task(obj) + instance.show(from_tty) + objects.information.invalidate() + # # Main # @@ -147,4 +177,5 @@ gdb.pretty_printers = [] gdb.pretty_printers.append (lookup_function) rtems() rtems_object() -rtems_semaphore() \ No newline at end of file +rtems_semaphore() +rtems_task() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Update Readme. Message-ID: <20140824234537.BBE36700814@git.rtems.org> Module: rtems-tools Branch: master Commit: c63080ddb2231ca0577514e393f4e793f1819d19 Changeset: http://git.rtems.org/rtems-tools/commit/?id=c63080ddb2231ca0577514e393f4e793f1819d19 Author: Dhananjay Balan Date: Sun Jul 28 18:13:22 2013 +0530 Update Readme. ToDo. --- tools/gdb/python/README.md | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 8858a4f..c471cd9 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -4,3 +4,6 @@ rtems-gdb GDB extenstions to RTEMS. See [this blog post for instructions](http://dbalan.github.io/blog/2013/06/23/debugging-rtems-with-gdb/) + +TODO: + - classic abstractions address on id - change this to more proper hierarchy. From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Added register class Message-ID: <20140824234537.D782970080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 04d95ec2b272953b719836a283c35280c816e189 Changeset: http://git.rtems.org/rtems-tools/commit/?id=04d95ec2b272953b719836a283c35280c816e189 Author: Dhananjay Balan Date: Sun Aug 25 18:48:48 2013 +0530 Added register class - sparc.register, basic represenation of sparc's registers. --- tools/gdb/python/sparc.py | 39 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 39 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/sparc.py b/tools/gdb/python/sparc.py index fa7b037..b0e251d 100644 --- a/tools/gdb/python/sparc.py +++ b/tools/gdb/python/sparc.py @@ -68,6 +68,45 @@ class psr: return val +class register: + '''SPARC Registers''' + + def __init__(self,reg): + self.reg = reg + + def global_regs(self): + val = [self.reg['g0_g1']] + + for i in range(2,7): + val.append(int(self.reg['g'+str(i)])) + return val + + def local_regs(self): + val = [] + + for i in range(0,8): + val.append(self.reg['l'+str(i)]) + return val + + def in_regs(self): + val = [] + + for i in range(0,8): + if i==6: + val.append(self.reg['i6_fp']) + else: + val.append(self.reg['i'+str(i)]) + return val + + def out_regs(self): + val = [] + + for i in range(0,8): + if i==6: + val.append(self.reg['o6_sp']) + else: + val.append(self.reg['o'+str(i)]) + return val From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Refactor subcommands Message-ID: <20140824234537.B2DC0700810@git.rtems.org> Module: rtems-tools Branch: master Commit: ddbc5306fa4f92048a8b1e94a35c25227adcf4fb Changeset: http://git.rtems.org/rtems-tools/commit/?id=ddbc5306fa4f92048a8b1e94a35c25227adcf4fb Author: Dhananjay Balan Date: Wed Aug 21 18:30:36 2013 +0530 Refactor subcommands - index commands inherit from a parent class. --- tools/gdb/python/rtems.py | 88 +++++++++++++++++--------------------------- 1 files changed, 34 insertions(+), 54 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 718701c..7d26542 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -65,16 +65,20 @@ class rtems_object(gdb.Command): object.show(from_tty) objects.information.invalidate() -class rtems_semaphore(gdb.Command): - '''Semaphore subcommand for rtems''' +class rtems_index(gdb.Command): + '''Print object by index''' api = 'classic' - _class = 'semaphores' + _class = '' - def __init__(self): - self.__doc__ = 'Display the RTEMS semaphores by index' - super(rtems_semaphore, self).__init__( 'rtems semaphore', - gdb.COMMAND_DATA, gdb.COMPLETE_NONE ) + def __init__(self,command): + super(rtems_index, self).__init__( command, + gdb.COMMAND_DATA, + gdb.COMPLETE_NONE) + + def instance(self,obj): + '''Returns a n instance of corresponding object, the child should extend this''' + return obj def invoke(self, arg, from_tty): for val in arg.split(): @@ -91,68 +95,44 @@ class rtems_semaphore(gdb.Command): print "error: index %s is invalid" % (index) return - instance = classic.semaphore(obj) + instance = self.instance(obj) instance.show(from_tty) objects.information.invalidate() -class rtems_task(gdb.Command): + +class rtems_semaphore(rtems_index): + '''semaphore subcommand''' + _class = 'semaphores' + + def __init__(self): + self.__doc__ = 'Display RTEMS semaphore(s) by index(es)' + super(rtems_semaphore, self).__init__('rtems semaphore') + + def instance(self,obj): + return classic.semaphore(obj) + +class rtems_task(rtems_index): '''tasks subcommand for rtems''' - api = 'classic' _class = 'tasks' def __init__(self): - self.__doc__ = 'Display the RTEMS tasks by index(s)' - super(rtems_task,self).__init__('rtems task', - gdb.COMMAND_DATA, gdb.COMPLETE_NONE) + self.__doc__ = 'Display RTEMS task(s) by index(es)' + super(rtems_task,self).__init__('rtems task') - def invoke(self, arg, from_tty): - for val in arg.split(): - try: - index = int(val) - except ValueError: - raise gdb.GdbError( "Value is not an integer") + def instance(self,obj): + return classic.task(obj) - try: - obj = objects.information.object_return(self.api, - self._class, - index).dereference() - except IndexError: - print "error: index %s is invalid" % (index) - return - instance = classic.task(obj) - instance.show(from_tty) - objects.information.invalidate() - -class rtems_message_queue(gdb.Command): +class rtems_message_queue(rtems_index): '''Message Queue subcommand''' - api = 'classic' _class = 'message_queues' def __init__(self): - self.__doc__ = 'Display the RTEMS message_queue by index(s)' - super(rtems_message_queue,self).__init__('rtems mqueue', - gdb.COMMAND_DATA, - gdb.COMPLETE_NONE) - - def invoke(self, arg, from_tty): - for val in arg.split(): - try: - index = int(val) - except ValueError: - print "error: %s is not an index" % (val) - return + self.__doc__ = 'Display RTEMS message_queue(s) by index(es)' + super(rtems_message_queue,self).__init__('rtems mqueue') - try: - obj = objects.information.object_return(self.api, - self._class, - index).dereference() - except IndexError: - print "error: index %s is invalid" % (index) - return + def instance(self,obj): + return classic.message_queue(obj) - instance = classic.message_queue(obj) - instance.show(from_tty) - objects.information.invalidate() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add sparc PSR Message-ID: <20140824234536.8F521700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 788a71578f394f1938b455385da75f722373232a Changeset: http://git.rtems.org/rtems-tools/commit/?id=788a71578f394f1938b455385da75f722373232a Author: Dhananjay Balan Date: Sun Aug 25 15:14:57 2013 +0530 Add sparc PSR - added a class to print SPARC status register --- tools/gdb/python/sparc.py | 76 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 76 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/sparc.py b/tools/gdb/python/sparc.py new file mode 100644 index 0000000..fa7b037 --- /dev/null +++ b/tools/gdb/python/sparc.py @@ -0,0 +1,76 @@ +# +# RTEMS gdb extensions +# sparc archetecture specific abstractions + +from helper import test_bit + +class psr: + '''status register''' + + sv_table = { + 0 : 'user', + 1 : 'superviser' + } + + + def __init__(self, psr): + self.psr = psr + + def current_window(self): + return int(self.psr & 0xf) + + def traps(self): + return test_bit(self.psr, 5) + + def prev_superviser(self): + return int(test_bit(self.psr,6)) + + def superviser(self): + return int(test_bit(self.psr,7)) + + def interrupt_level(self): + # bits 8 to 11 + return (self.spr & 0x780) >> 7 + + def floating_point_status(self): + return test_bit(self.psr, 12) + + def coproc_status(self): + return test_bit(self.psr,13) + + def carry(self): + return test_bit(self.psr, 20) + + def overflow(self): + return test_bit(self.psr, 21) + + def zero(self): + return test_bit(self.psr, 22) + + def icc(self): + n = test_bit(self.psr,23) + z = test_bit(self.psr,22) + v = test_bit(self.psr,21) + c = test_bit(self.psr,20) + return (n,z,v,c) + + def to_string(self): + val = " Status Register" + val += "\n R Window : " + str(self.current_window()) + val += "\n Traps Enabled : " + str(self.traps()) + val += "\n Flaoting Point : " + str(self.floating_point_status()) + val += "\n Coprocessor : " + str(self.coproc_status()) + val += "\n Processor Mode : " + self.sv_table[self.superviser()] + val += "\n Prev. Mode : " + self.sv_table[self.superviser()] + val += "\n Carry : " + str(int(self.carry())) + val += "\n Overflow : " + str(int(self.overflow())) + val += "\n Zero : " + str(int(self.zero())) + + return val + + + + + + + From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Fix wdticks command Message-ID: <20140824234538.0C7BC700810@git.rtems.org> Module: rtems-tools Branch: master Commit: 1fcff75505e4be2916bcd273a3670828363a0f67 Changeset: http://git.rtems.org/rtems-tools/commit/?id=1fcff75505e4be2916bcd273a3670828363a0f67 Author: Dhananjay Balan Date: Mon Aug 26 20:53:57 2013 +0530 Fix wdticks command - Type is Chain_Control - chain.node.next -> null --- tools/gdb/python/objects.py | 1 + tools/gdb/python/rtems.py | 9 +++++++-- tools/gdb/python/watchdog.py | 17 +++++++++++------ 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index f4ae5e1..ae2a4c7 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -14,6 +14,7 @@ class infotables: tables_types = { 'internal/time' : ('TOD_Control', '_TOD'), + 'internal/wdticks' : ('Chain_Control', '_Watchdog_Ticks_chain'), 'classic/tasks' : ('Thread_Control', '_RTEMS_tasks_Information'), 'classic/timers' : ('Timer_Control', '_Timer_Information'), diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 64c7f1a..340c7ff 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -11,6 +11,7 @@ import re import objects import threads import chains +import watchdog import supercore import classic @@ -227,10 +228,14 @@ class rtems_watchdog_chain(gdb.Command): return nd = inst.first() + i = 0 + print ' Ticks Chain' while not nd.null(): wd = watchdog.control(nd.cast('Watchdog_Control')) - wd.show() - nd = nd.next() + print ' #'+str(i) + print wd.to_string() + nd.next() + i += 1 class rtems_wdt(rtems_watchdog_chain): diff --git a/tools/gdb/python/watchdog.py b/tools/gdb/python/watchdog.py index fef2f39..71a1816 100644 --- a/tools/gdb/python/watchdog.py +++ b/tools/gdb/python/watchdog.py @@ -52,10 +52,15 @@ class control: addr = self.ctrl['routine'] return str(addr) + def to_string(self): + val = "" + val += " State:" + str(self.state()) + val += "\n Intial Interval:" + str(self.initial()) + val += "\n Delta Interval:"+ str(self.delta_interval()) + val += "\n Start time:" + str(self.start_time()) + val += "\n Stop time:" + str(self.stop_time()) + val += "\n WD Routine:" + str(self.routine()) + return val + def show(self): - print " State:", self.state() - print " Intial Interval:", self.initial() - print " Delta Interval:", self.delta_interval() - print " Start time:", self.start_time() - print " Stop time:", self.stop_time() - print " WD Routine:", self.routine() \ No newline at end of file + print self.to_string() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add watchdog ticks command. Message-ID: <20140824234537.6F1DE70080E@git.rtems.org> Module: rtems-tools Branch: master Commit: a7176a8a7e5542d9371026b135a864f15d79e1b5 Changeset: http://git.rtems.org/rtems-tools/commit/?id=a7176a8a7e5542d9371026b135a864f15d79e1b5 Author: Dhananjay Balan Date: Sun Aug 25 23:21:44 2013 +0530 Add watchdog ticks command. - ToDo : Fix watchdog states. --- tools/gdb/python/chains.py | 3 +++ tools/gdb/python/main.py | 3 ++- tools/gdb/python/rtems.py | 35 +++++++++++++++++++++++++++++++++++ tools/gdb/python/watchdog.py | 10 +++------- 4 files changed, 43 insertions(+), 8 deletions(-) diff --git a/tools/gdb/python/chains.py b/tools/gdb/python/chains.py index 0826ba9..ef33ed6 100644 --- a/tools/gdb/python/chains.py +++ b/tools/gdb/python/chains.py @@ -48,3 +48,6 @@ class control: def last(self): return node(self.ctrl['Tail']['Node']) + def empty(self): + if self.last() == self.first().next(): + return True diff --git a/tools/gdb/python/main.py b/tools/gdb/python/main.py index 0ec4a28..a0ff7dc 100644 --- a/tools/gdb/python/main.py +++ b/tools/gdb/python/main.py @@ -17,4 +17,5 @@ rtems.rtems_object() rtems.rtems_semaphore() rtems.rtems_task() rtems.rtems_message_queue() -rtems.rtems_tod() \ No newline at end of file +rtems.rtems_tod() +rtems.rtems_wdt() \ No newline at end of file diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index cf2000a..64c7f1a 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -10,6 +10,7 @@ import re import objects import threads +import chains import supercore import classic @@ -205,3 +206,37 @@ class rtems_tod(gdb.Command): instance = supercore.time_of_day(obj) instance.show() objects.information.invalidate() + +class rtems_watchdog_chain(gdb.Command): + '''Print watchdog ticks chain''' + + api = 'internal' + _class = '' + + def __init__(self,command): + super(rtems_watchdog_chain, self).__init__ \ + (command, gdb.COMMAND_DATA, gdb.COMPLETE_NONE) + + def invoke(self, arg, from_tty): + obj = objects.information.object_return(self.api, self._class) + + inst = chains.control(obj) + + if inst.empty(): + print ' error: empty chain' + return + + nd = inst.first() + while not nd.null(): + wd = watchdog.control(nd.cast('Watchdog_Control')) + wd.show() + nd = nd.next() + +class rtems_wdt(rtems_watchdog_chain): + + _class = 'wdticks' + + def __init__(self): + self.__doc__ = 'Display watchdog ticks chain' + super(rtems_wdt, self).__init__('rtems wdticks') + diff --git a/tools/gdb/python/watchdog.py b/tools/gdb/python/watchdog.py index 3678550..fef2f39 100644 --- a/tools/gdb/python/watchdog.py +++ b/tools/gdb/python/watchdog.py @@ -12,11 +12,6 @@ import objects class state: - INACTIVE = 0 - BEING_INSERTED = 1 - ACTIVE = 2 - REMOVE_IT = 3 - states = { 0: 'inactive', 1: 'being-inserted', @@ -35,9 +30,10 @@ class control: def __init__(self, ctrl): self.ctrl = ctrl - # Not sure if an extra class is needed. + # ToDo: fix this.1 def state(self): - return state(int(self.ctrl['state'])).to_string() + return state(1).to_string() + #return state(int(self.ctrl['state'])).to_string() def initial(self): return self.ctrl['initial'] From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add cpu registers to task output. Message-ID: <20140824234538.00794700679@git.rtems.org> Module: rtems-tools Branch: master Commit: bd0b98d55e4bcb29ce0631e6c717f873739bf80b Changeset: http://git.rtems.org/rtems-tools/commit/?id=bd0b98d55e4bcb29ce0631e6c717f873739bf80b Author: Dhananjay Balan Date: Mon Aug 26 22:30:25 2013 +0530 Add cpu registers to task output. --- tools/gdb/python/classic.py | 5 ++ tools/gdb/python/sparc.py | 135 ++++++++++++++++++++++++++----------------- 2 files changed, 86 insertions(+), 54 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 261f648..e492657 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -16,6 +16,7 @@ import threads import watchdog import heaps import supercore +import sparc class attribute: """The Classic API attribute.""" @@ -155,6 +156,8 @@ class task: self.task = \ threads.control(self.object) self.wait_info = self.task.wait_info() + # ToDo: Insert platform dep. code here. + self.regs = sparc.register(self.object['Registers']) def show(self, from_tty): print ' Name:', self.task.name() @@ -163,6 +166,8 @@ class task: print ' Real:', self.task.real_priority() print ' Preempt:', self.task.preemptible() print ' T Budget:', self.task.cpu_time_budget() + print ' Regsters:' + self.regs.show() class message_queue: diff --git a/tools/gdb/python/sparc.py b/tools/gdb/python/sparc.py index b0e251d..70ef5d3 100644 --- a/tools/gdb/python/sparc.py +++ b/tools/gdb/python/sparc.py @@ -4,72 +4,74 @@ from helper import test_bit -class psr: - '''status register''' - sv_table = { - 0 : 'user', - 1 : 'superviser' - } +class register: + '''SPARC Registers''' - def __init__(self, psr): - self.psr = psr + class psr: + '''status register''' - def current_window(self): - return int(self.psr & 0xf) + sv_table = { + 0 : 'user', + 1 : 'superviser' + } - def traps(self): - return test_bit(self.psr, 5) - def prev_superviser(self): - return int(test_bit(self.psr,6)) + def __init__(self, psr): + self.psr = psr - def superviser(self): - return int(test_bit(self.psr,7)) + def current_window(self): + return int(self.psr & 0xf) - def interrupt_level(self): - # bits 8 to 11 - return (self.spr & 0x780) >> 7 + def traps(self): + return test_bit(self.psr, 5) - def floating_point_status(self): - return test_bit(self.psr, 12) + def prev_superviser(self): + return int(test_bit(self.psr,6)) - def coproc_status(self): - return test_bit(self.psr,13) + def superviser(self): + return int(test_bit(self.psr,7)) - def carry(self): - return test_bit(self.psr, 20) + def interrupt_level(self): + # bits 8 to 11 + return (self.spr & 0x780) >> 7 - def overflow(self): - return test_bit(self.psr, 21) + def floating_point_status(self): + return test_bit(self.psr, 12) - def zero(self): - return test_bit(self.psr, 22) + def coproc_status(self): + return test_bit(self.psr,13) - def icc(self): - n = test_bit(self.psr,23) - z = test_bit(self.psr,22) - v = test_bit(self.psr,21) - c = test_bit(self.psr,20) - return (n,z,v,c) + def carry(self): + return test_bit(self.psr, 20) - def to_string(self): - val = " Status Register" - val += "\n R Window : " + str(self.current_window()) - val += "\n Traps Enabled : " + str(self.traps()) - val += "\n Flaoting Point : " + str(self.floating_point_status()) - val += "\n Coprocessor : " + str(self.coproc_status()) - val += "\n Processor Mode : " + self.sv_table[self.superviser()] - val += "\n Prev. Mode : " + self.sv_table[self.superviser()] - val += "\n Carry : " + str(int(self.carry())) - val += "\n Overflow : " + str(int(self.overflow())) - val += "\n Zero : " + str(int(self.zero())) + def overflow(self): + return test_bit(self.psr, 21) - return val + def zero(self): + return test_bit(self.psr, 22) -class register: - '''SPARC Registers''' + def icc(self): + n = test_bit(self.psr,23) + z = test_bit(self.psr,22) + v = test_bit(self.psr,21) + c = test_bit(self.psr,20) + return (n,z,v,c) + + def to_string(self): + val = " Status Register" + val += "\n R Window : " + str(self.current_window()) + val += "\n Traps Enabled : " + str(self.traps()) + val += "\n Flaoting Point : " + str(self.floating_point_status()) + val += "\n Coprocessor : " + str(self.coproc_status()) + val += "\n Processor Mode : " + self.sv_table[self.superviser()] + val += "\n Prev. Mode : " + self.sv_table[self.superviser()] + val += "\n Carry : " + str(int(self.carry())) + val += "\n Overflow : " + str(int(self.overflow())) + val += "\n Zero : " + str(int(self.zero())) + + return val def __init__(self,reg): self.reg = reg @@ -108,8 +110,33 @@ class register: val.append(self.reg['o'+str(i)]) return val - - - - - + def status(self): + return self.psr(self.reg['psr']) + + def show(self): + print ' Global Regs:', + print ' [', + for i in self.global_regs(): + print str(i)+',', + print '\b\b ]' + + print ' Local Regs:', + print ' [', + for i in self.local_regs(): + print str(i)+',', + print '\b\b ]' + + print ' In Regs:', + print ' [', + for i in self.in_regs(): + print str(i)+',', + print '\b\b ]' + + print ' Out Regs:', + print ' [', + for i in self.out_regs(): + print str(i)+',', + print '\b\b ]' + + sr = self.status() + print sr.to_string() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add subcommand Message-ID: <20140824234537.DBFD6700810@git.rtems.org> Module: rtems-tools Branch: master Commit: a245635a2e3c7b9ef5ebfc480b6115544c3d4340 Changeset: http://git.rtems.org/rtems-tools/commit/?id=a245635a2e3c7b9ef5ebfc480b6115544c3d4340 Author: Dhananjay Balan Date: Sat Aug 24 15:26:16 2013 +0530 Add subcommand rtems tod - prints the time of day. --- tools/gdb/python/main.py | 3 ++- tools/gdb/python/objects.py | 20 ++++++++++++++------ tools/gdb/python/rtems.py | 21 +++++++++++++++++++++ tools/gdb/python/supercore.py | 25 +++++++++++++++++++++++++ 4 files changed, 62 insertions(+), 7 deletions(-) diff --git a/tools/gdb/python/main.py b/tools/gdb/python/main.py index 2ef475a..0ec4a28 100644 --- a/tools/gdb/python/main.py +++ b/tools/gdb/python/main.py @@ -16,4 +16,5 @@ rtems.rtems() rtems.rtems_object() rtems.rtems_semaphore() rtems.rtems_task() -rtems.rtems_message_queue() \ No newline at end of file +rtems.rtems_message_queue() +rtems.rtems_tod() \ No newline at end of file diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 1a64a8d..58c2730 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -13,6 +13,8 @@ class infotables: """Manage the object information tables.""" tables_types = { + 'internal/time' : ('TOD_Control', '_TOD'), + 'classic/tasks' : ('Thread_Control', '_RTEMS_tasks_Information'), 'classic/timers' : ('Timer_Control', '_Timer_Information'), 'classic/semaphores' : ('Semaphore_Control', '_Semaphore_Information'), @@ -64,15 +66,21 @@ class infotables: index = id.index() return self.object_return(api, _class, index) - def object_return(self, api, _class, index): + def object_return(self, api, _class, index=-1): n = self.name(api, _class) self.load(n) - max = self.maximum(api, _class) - if index > max: - raise IndexError('object index out of range (%d)' % (max)) + table_type = self.tables_types[n] - expr = '(' + table_type[0] + '*)' + \ - table_type[1] + '.local_table[' + str(index) + ']' + + if api == 'internal': + expr = '(' + table_type[0] + ')' + table_type[1] + + else: + max = self.maximum(api, _class) + if index > max: + raise IndexError('object index out of range (%d)' % (max)) + expr = '(' + table_type[0] + '*)' + \ + table_type[1] + '.local_table[' + str(index) + ']' return gdb.parse_and_eval(expr) def is_string(self, api, _class): diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index b142f23..cf2000a 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -10,6 +10,7 @@ import re import objects import threads +import supercore import classic @@ -184,3 +185,23 @@ class rtems_barrier(rtems_index): def instance(self, obj): return classic.barrier(obj) +class rtems_tod(gdb.Command): + '''Print rtems time of day''' + + api = 'internal' + _class = 'time' + + def __init__(self): + self.__doc__ = 'Display RTEMS time of day' + super(rtems_tod, self).__init__ \ + ('rtems tod', gdb.COMMAND_STATUS,gdb.COMPLETE_NONE) + + def invoke(self, arg, from_tty): + + if arg: + print "warning: commad takes no arguments!" + + obj = objects.information.object_return(self.api,self._class) + instance = supercore.time_of_day(obj) + instance.show() + objects.information.invalidate() diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py index e60813a..6116626 100644 --- a/tools/gdb/python/supercore.py +++ b/tools/gdb/python/supercore.py @@ -5,6 +5,31 @@ import threads import helper +class time_of_day: + '''Manage time of day object''' + + def __init__(self, tod): + self.tod = tod + + def now(self): + return self.tod['now'] + + def timer(self): + return self.tod['uptime'] + + def is_set(self): + return bool(self.tod['is_set']) + + def show(self): + print ' Time Of Day' + + if not self.is_set(): + print ' Application has not set a TOD' + + print ' Now:', self.now() + print ' Uptime:', self.timer() + + class message_queue: '''Manage a Supercore message_queue''' From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Add subcommand semaphore Message-ID: <20140824234537.9CEC4700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 479717912afe27705874805f3a3786dd9d665bb6 Changeset: http://git.rtems.org/rtems-tools/commit/?id=479717912afe27705874805f3a3786dd9d665bb6 Author: Dhananjay Balan Date: Fri Aug 9 14:25:43 2013 +0530 Add subcommand semaphore rtems semaphore : prints rtems semaphores by index number --- tools/gdb/python/rtems.py | 31 +++++++++++++++++++++++++++++-- 1 files changed, 29 insertions(+), 2 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 20f44a2..cf1ae07 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -85,7 +85,7 @@ class rtems_object(gdb.Command): } def __init__(self): - self.__doc__ = 'Display the RTEMS object given a numeric ID.' + self.__doc__ = 'Display the RTEMS object given a numeric ID (Or a reference to rtems_object).' super(rtems_object, self).__init__('rtems object', gdb.COMMAND_STATUS) @@ -112,6 +112,32 @@ class rtems_object(gdb.Command): object.show(from_tty) objects.information.invalidate() +class rtems_semaphore(gdb.Command): + '''Semaphore subcommand for rtems''' + + api = 'classic' + _class = 'semaphores' + + def __init__(self): + self.__doc__ = 'Display the RTEMS semaphores by index' + super(rtems_semaphore, self).__init__('rtems semaphore', + gdb.COMMAND_STATUS) + + def invoke(self, arg, from_tty): + for val in arg.split(): + try: + index = int(val) + except ValueError: + print "error: %s is not an index" % (val) + return + + obj = objects.information.object_return( self.api, + self._class, + int(index)).dereference() + instance = classic.semaphore(obj) + instance.show(from_tty) + objects.information.invalidate() + # # Main # @@ -120,4 +146,5 @@ build_rtems_dict() gdb.pretty_printers = [] gdb.pretty_printers.append (lookup_function) rtems() -rtems_object() \ No newline at end of file +rtems_object() +rtems_semaphore() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Fix Task and state printer bugs. Message-ID: <20140824234537.848F8700810@git.rtems.org> Module: rtems-tools Branch: master Commit: e60a5eec0b1e8b16d984e4baf7dccb3323b88928 Changeset: http://git.rtems.org/rtems-tools/commit/?id=e60a5eec0b1e8b16d984e4baf7dccb3323b88928 Author: Dhananjay Balan Date: Tue Jul 30 09:12:35 2013 +0530 Fix Task and state printer bugs. - Removed ITRON api objects in thread control - fixes #1 --- tools/gdb/python/classic.py | 5 ++--- tools/gdb/python/supercore_printer.py | 1 + tools/gdb/python/threads.py | 6 ------ 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 617a0db..50514ff 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -153,17 +153,16 @@ class task: self.id = id; self.task = \ threads.control(objects.information.object(self.id).dereference()) + self.wait_info = self.task.wait_info() def show(self, from_tty): print ' Name:', self.task.name() print ' State:', self.task.current_state() print ' Current:', self.task.current_priority() print ' Real:', self.task.real_priority() - print ' Suspends:', self.task.suspends() - print ' Post Ext:', self.task.post_task_switch_ext() print ' Preempt:', self.task.preemptible() print ' T Budget:', self.task.cpu_time_budget() - wait_info = self.task.wait_info() + class message_queue: "Print classic messege queue" diff --git a/tools/gdb/python/supercore_printer.py b/tools/gdb/python/supercore_printer.py index ec1d416..3ce8110 100644 --- a/tools/gdb/python/supercore_printer.py +++ b/tools/gdb/python/supercore_printer.py @@ -3,6 +3,7 @@ # import objects import itertools +import threads class id: """Print an object given the ID. Print using the struct display hint and an diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py index b5ac3fb..77c7efa 100644 --- a/tools/gdb/python/threads.py +++ b/tools/gdb/python/threads.py @@ -145,12 +145,6 @@ class control: def real_priority(self): return self.ctrl['real_priority'] - def suspends(self): - return self.ctrl['suspend_count'] - - def post_task_switch_ext(self): - return self.ctrl['do_post_task_switch_extension'] - def preemptible(self): return self.ctrl['is_preemptible'] From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Support classic/partitions Message-ID: <20140824234538.07EEF70080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 09086b415db7bb08cca41fc3fff212bbaece327a Changeset: http://git.rtems.org/rtems-tools/commit/?id=09086b415db7bb08cca41fc3fff212bbaece327a Author: Dhananjay Balan Date: Sat Jul 27 14:29:19 2013 +0530 Support classic/partitions Added support for partition object. --- tools/gdb/python/classic.py | 29 ++++++++++++++++++++++++++--- tools/gdb/python/classic_printer.py | 4 +++- tools/gdb/python/rtems.py | 3 ++- 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 1f5daf2..f7d4dfc 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -40,7 +40,8 @@ class attribute: 'priority', 'barrier'], 'message_queue' : ['priority', - 'scope'] + 'scope'], + 'partition' : ['scope'] } masks = { @@ -163,7 +164,7 @@ class task: wait_info = self.task.wait_info() class message_queue: - "Print a classic messege queue" + "Print classic messege queue" def __init__(self,id): self.id = id @@ -193,4 +194,26 @@ class timer: def show(self, from_tty): print ' Name:', self.object_control.name() - self.watchdog.show() \ No newline at end of file + self.watchdog.show() + +class partition: + ''' Print a rtems partition ''' + + def __init__(self, id): + self.id = id + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.attr = attribute(self.object['attribute_set'], 'partition') + self.starting_addr = self.object['starting_address'] + self.length = self.object['length'] + self.buffer_size = self.object['buffer_size'] + self.used_blocks = self.object['number_of_used_blocks'] + + def show(self, from_tty): + # ToDo: the printing still somewhat crude. + print ' Name:', self.object_control.name() + print ' Attr:', self.attr.to_string() + print ' Length:', self.length + print 'Buffer Size:', self.buffer_size + print 'Used Blocks:', self.used_blocks + diff --git a/tools/gdb/python/classic_printer.py b/tools/gdb/python/classic_printer.py index a25d756..86e0eeb 100644 --- a/tools/gdb/python/classic_printer.py +++ b/tools/gdb/python/classic_printer.py @@ -1,6 +1,8 @@ # # RTEMS Classic pretty printers for GDB # +import classic +import gdb class attribute: @@ -12,7 +14,7 @@ class attribute: return gdb.Value(self.attr.to_string()) class semaphore: - """ToDo: Print a Semaphore_Control object. Print using the struct display hint + """Print a Semaphore_Control object. Print using the struct display hint and an iterator. """ class iterator: diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index bd2d8e4..eac5042 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -78,7 +78,8 @@ class rtems_object(gdb.Command): 'classic/semaphores': lambda id: classic.semaphore(id), 'classic/tasks': lambda id: classic.task(id), 'classic/message_queues': lambda id: classic.message_queue(id), - 'classic/timers' : lambda id: classic.timer(id) + 'classic/timers' : lambda id: classic.timer(id), + 'classic/partitions' : lambda id: classic.partition(id) } def __init__(self): From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Added support for classic/timers. Message-ID: <20140824234536.A0DEA70080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 086e689955e3b0692d00bf2fc0ea1be7ed244e07 Changeset: http://git.rtems.org/rtems-tools/commit/?id=086e689955e3b0692d00bf2fc0ea1be7ed244e07 Author: Dhananjay Balan Date: Wed Jul 17 16:18:57 2013 +0530 Added support for classic/timers. --- tools/gdb/python/classic.py | 16 +++++++++++++++- tools/gdb/python/rtems.py | 3 ++- tools/gdb/python/watchdog.py | 19 ++++++++++++++----- 3 files changed, 31 insertions(+), 7 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 9af11df..1f5daf2 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -11,6 +11,7 @@ import re import objects import threads +import watchdog import supercore class attribute: @@ -179,4 +180,17 @@ class message_queue: print ' Name:', self.object_control.name() print ' Attr:', self.attr.to_string() - self.core_control.show() \ No newline at end of file + self.core_control.show() + +class timer: + '''Print a classic timer''' + + def __init__(self, id): + self.id = id + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.watchdog = watchdog.control(self.object['Ticker']) + + def show(self, from_tty): + print ' Name:', self.object_control.name() + self.watchdog.show() \ No newline at end of file diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 4622ced..bd2d8e4 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -77,7 +77,8 @@ class rtems_object(gdb.Command): objects = { 'classic/semaphores': lambda id: classic.semaphore(id), 'classic/tasks': lambda id: classic.task(id), - 'classic/message_queues': lambda id: classic.message_queue(id) + 'classic/message_queues': lambda id: classic.message_queue(id), + 'classic/timers' : lambda id: classic.timer(id) } def __init__(self): diff --git a/tools/gdb/python/watchdog.py b/tools/gdb/python/watchdog.py index 0766575..3678550 100644 --- a/tools/gdb/python/watchdog.py +++ b/tools/gdb/python/watchdog.py @@ -16,14 +16,14 @@ class state: BEING_INSERTED = 1 ACTIVE = 2 REMOVE_IT = 3 - + states = { 0: 'inactive', 1: 'being-inserted', 2: 'active', 3: 'remove-it' } - + def __init__(self, s): self.s = s @@ -35,8 +35,9 @@ class control: def __init__(self, ctrl): self.ctrl = ctrl + # Not sure if an extra class is needed. def state(self): - return state(self.ctrl['state']).to_string() + return state(int(self.ctrl['state'])).to_string() def initial(self): return self.ctrl['initial'] @@ -50,7 +51,15 @@ class control: def stop_time(self): return self.ctrl['stop_time'] + # ToDo: Better printing of watchdog. def routine(self): addr = self.ctrl['routine'] - sym = gdb.lookup_symbol(addr) - print sym + return str(addr) + + def show(self): + print " State:", self.state() + print " Intial Interval:", self.initial() + print " Delta Interval:", self.delta_interval() + print " Start time:", self.start_time() + print " Stop time:", self.stop_time() + print " WD Routine:", self.routine() \ No newline at end of file From sebh at rtems.org Mon Aug 25 06:50:14 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 25 Aug 2014 01:50:14 -0500 Subject: [rtems commit] rtems: Inline rtems_clock_get_ticks_since_boot() Message-ID: <20140825065014.CF784700812@git.rtems.org> Module: rtems Branch: master Commit: f553c6ebbe4c61b239da07e6b7d70afa3b10828e Changeset: http://git.rtems.org/rtems/commit/?id=f553c6ebbe4c61b239da07e6b7d70afa3b10828e Author: Sebastian Huber Date: Fri Aug 22 16:39:47 2014 +0200 rtems: Inline rtems_clock_get_ticks_since_boot() Update documentation. --- cpukit/rtems/Makefile.am | 1 - cpukit/rtems/include/rtems/rtems/clock.h | 14 +++++----- cpukit/rtems/src/clockgettickssinceboot.c | 31 ----------------------- cpukit/score/include/rtems/score/watchdog.h | 7 +++++ cpukit/score/include/rtems/score/watchdogimpl.h | 8 ------ doc/user/clock.t | 31 +++++++--------------- 6 files changed, 24 insertions(+), 68 deletions(-) diff --git a/cpukit/rtems/Makefile.am b/cpukit/rtems/Makefile.am index b00e251..a1fafb1 100644 --- a/cpukit/rtems/Makefile.am +++ b/cpukit/rtems/Makefile.am @@ -151,7 +151,6 @@ librtems_a_SOURCES += src/barrierdata.c librtems_a_SOURCES += src/clockget.c librtems_a_SOURCES += src/clockgetsecondssinceepoch.c librtems_a_SOURCES += src/clockgettickspersecond.c -librtems_a_SOURCES += src/clockgettickssinceboot.c librtems_a_SOURCES += src/clockgettod.c librtems_a_SOURCES += src/clockgettodtimeval.c librtems_a_SOURCES += src/clockgetuptime.c diff --git a/cpukit/rtems/include/rtems/rtems/clock.h b/cpukit/rtems/include/rtems/rtems/clock.h index d80218d..ff71665 100644 --- a/cpukit/rtems/include/rtems/rtems/clock.h +++ b/cpukit/rtems/include/rtems/rtems/clock.h @@ -149,15 +149,15 @@ rtems_status_code rtems_clock_get_seconds_since_epoch( ); /** - * @brief Obtain Ticks Since Boot + * @brief Gets the current ticks counter value. * - * This routine implements the rtems_clock_get_ticks_since_boot - * directive. - * - * @retval This method returns the number of ticks since boot. It cannot - * fail since RTEMS always keeps a running count of ticks since boot. + * @return The current tick counter value. With a 1ms clock tick, this counter + * overflows after 50 days since boot. */ -rtems_interval rtems_clock_get_ticks_since_boot(void); +RTEMS_INLINE_ROUTINE rtems_interval rtems_clock_get_ticks_since_boot(void) +{ + return _Watchdog_Ticks_since_boot; +} /** * @brief Obtain Ticks Per Seconds diff --git a/cpukit/rtems/src/clockgettickssinceboot.c b/cpukit/rtems/src/clockgettickssinceboot.c deleted file mode 100644 index 4aced96..0000000 --- a/cpukit/rtems/src/clockgettickssinceboot.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file - * - * @brief Obtain Ticks Since Boot - * @ingroup ClassicClock - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#if HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include -#include -#include -#include - -rtems_interval rtems_clock_get_ticks_since_boot(void) -{ - return _Watchdog_Ticks_since_boot; -} diff --git a/cpukit/score/include/rtems/score/watchdog.h b/cpukit/score/include/rtems/score/watchdog.h index 7327f77..06c87a1 100644 --- a/cpukit/score/include/rtems/score/watchdog.h +++ b/cpukit/score/include/rtems/score/watchdog.h @@ -124,6 +124,13 @@ typedef struct { void *user_data; } Watchdog_Control; +/** + * @brief The watchdog ticks counter. + * + * With a 1ms watchdog tick, this counter overflows after 50 days since boot. + */ +SCORE_EXTERN volatile Watchdog_Interval _Watchdog_Ticks_since_boot; + /**@}*/ #ifdef __cplusplus diff --git a/cpukit/score/include/rtems/score/watchdogimpl.h b/cpukit/score/include/rtems/score/watchdogimpl.h index 72b6b3b..d50e279 100644 --- a/cpukit/score/include/rtems/score/watchdogimpl.h +++ b/cpukit/score/include/rtems/score/watchdogimpl.h @@ -85,14 +85,6 @@ SCORE_EXTERN volatile uint32_t _Watchdog_Sync_level; SCORE_EXTERN volatile uint32_t _Watchdog_Sync_count; /** - * @brief The number of ticks since the system was booted. - * - * This contains the number of ticks since the system was booted. - */ - -SCORE_EXTERN volatile Watchdog_Interval _Watchdog_Ticks_since_boot; - -/** * @brief Watchdog chain which is managed at ticks. * * This is the watchdog chain which is managed at ticks. diff --git a/doc/user/clock.t b/doc/user/clock.t index fdbd91d..921d1cb 100644 --- a/doc/user/clock.t +++ b/doc/user/clock.t @@ -20,7 +20,7 @@ the clock manager are: @item @code{@value{DIRPREFIX}clock_get_tod_timeval} - Get date and time in timeval format @item @code{@value{DIRPREFIX}clock_get_seconds_since_epoch} - Get seconds since epoch @item @code{@value{DIRPREFIX}clock_get_ticks_per_second} - Get ticks per second - at item @code{@value{DIRPREFIX}clock_get_ticks_since_boot} - Get ticks since boot + at item @code{@value{DIRPREFIX}clock_get_ticks_since_boot} - Get current ticks counter value @item @code{@value{DIRPREFIX}clock_get_uptime} - Get time since boot @item @code{@value{DIRPREFIX}clock_get_uptime_timeval} - Get time since boot in timeval format @item @code{@value{DIRPREFIX}clock_get_uptime_seconds} - Get seconds since boot @@ -569,19 +569,16 @@ application has configured. This directive is callable from an ISR. -This directive will not cause the running task to be -preempted. Re-initializing RTEMS causes the system date and -time to be reset to an uninitialized state. Another call to - at code{@value{DIRPREFIX}clock_set} is required to re-initialize the -system date and time to application specific specifications. +This directive will not cause the running task to be preempted. @c @c @c @page - at subsection CLOCK_GET_TICKS_SINCE_BOOT - Get ticks since boot + at subsection CLOCK_GET_TICKS_SINCE_BOOT - Get current ticks counter value @cindex obtain ticks since boot + at cindex get current ticks counter value @subheading CALLING SEQUENCE: @@ -604,25 +601,17 @@ NONE @subheading DESCRIPTION: -This directive returns the number of clock ticks that have elapsed -since the system was booted. This is the historical measure of uptime -in an RTEMS system. The newer service - at code{@value{DIRPREFIX}clock_get_uptime} is another and potentially -more accurate way of obtaining similar information. +This directive returns the current tick counter value. With a 1ms clock tick, +this counter overflows after 50 days since boot. This is the historical +measure of uptime in an RTEMS system. The newer service + at code{@value{DIRPREFIX}clock_get_uptime} is another and potentially more +accurate way of obtaining similar information. @subheading NOTES: This directive is callable from an ISR. -This directive will not cause the running task to be -preempted. Re-initializing RTEMS causes the system date and -time to be reset to an uninitialized state. Another call to - at code{@value{DIRPREFIX}clock_set} is required to re-initialize the -system date and time to application specific specifications. - -This directive simply returns the number of times the dirivective - at code{@value{DIRPREFIX}clock_tick} has been invoked since the -system was booted. +This directive will not cause the running task to be preempted. @c @c From sebh at rtems.org Mon Aug 25 06:50:14 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 25 Aug 2014 01:50:14 -0500 Subject: [rtems commit] score: Add missing define to cache manager Message-ID: <20140825065014.F3D3C70080E@git.rtems.org> Module: rtems Branch: master Commit: e7a42a0cfbafc2311888780b086010aef6556311 Changeset: http://git.rtems.org/rtems/commit/?id=e7a42a0cfbafc2311888780b086010aef6556311 Author: Daniel Cederman Date: Mon Aug 25 08:48:17 2014 +0200 score: Add missing define to cache manager --- c/src/lib/libcpu/shared/src/cache_manager.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c index 7dd408f..7ff1166 100644 --- a/c/src/lib/libcpu/shared/src/cache_manager.c +++ b/c/src/lib/libcpu/shared/src/cache_manager.c @@ -435,6 +435,7 @@ rtems_cache_disable_data( void ) * and then perform the invalidations. */ +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) #if !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) static void _invalidate_multiple_instruction_lines_no_range_functions( @@ -462,6 +463,7 @@ _invalidate_multiple_instruction_lines_no_range_functions( } } #endif +#endif void rtems_cache_invalidate_multiple_instruction_lines( From sebh at rtems.org Mon Aug 25 07:02:40 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 25 Aug 2014 02:02:40 -0500 Subject: [rtems commit] bsp/mpc55xx: Limit flash support to MPC55[56]X Message-ID: <20140825070240.6C219700810@git.rtems.org> Module: rtems Branch: master Commit: 0a314839012ab765a70df05eaadc4dba7440223b Changeset: http://git.rtems.org/rtems/commit/?id=0a314839012ab765a70df05eaadc4dba7440223b Author: Sebastian Huber Date: Mon Aug 25 09:09:45 2014 +0200 bsp/mpc55xx: Limit flash support to MPC55[56]X --- .../libcpu/powerpc/mpc55xx/misc/flash_support.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c index b286b51..74bbd39 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c +++ b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c @@ -38,7 +38,7 @@ #include #include -#if MPC55XX_CHIP_TYPE / 100 == 55 +#if MPC55XX_CHIP_FAMILY == 555 || MPC55XX_CHIP_FAMILY == 556 /* Set up the memory ranges for the flash on * the MPC5553, MPC5554, MPC5566 and MPC5567. From sebh at rtems.org Mon Aug 25 07:22:35 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 25 Aug 2014 02:22:35 -0500 Subject: [rtems commit] bsp/mpc55xx: Add defines for MPC5668 Message-ID: <20140825072235.9D691700810@git.rtems.org> Module: rtems Branch: master Commit: f3237a3c3bbe5a298b5ae30a36b24e6f601c6f8b Changeset: http://git.rtems.org/rtems/commit/?id=f3237a3c3bbe5a298b5ae30a36b24e6f601c6f8b Author: Sebastian Huber Date: Mon Aug 25 09:30:53 2014 +0200 bsp/mpc55xx: Add defines for MPC5668 --- .../libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h | 14 +++++++------- c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h | 6 ++++++ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h index bf388ad..b7a1793 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h +++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h @@ -5184,7 +5184,7 @@ extern "C" { } B; } EISR; /* External Interrupt Status Register */ - union { + union SIU_DIRER_tag { uint32_t R; struct { uint32_t:16; @@ -5207,7 +5207,7 @@ extern "C" { } B; } DIRER; /* DMA/Interrupt Request Enable Register */ - union { + union SIU_DIRSR_tag { uint32_t R; struct { uint32_t:30; @@ -5239,7 +5239,7 @@ extern "C" { } B; } OSR; /* Overrun Status Register */ - union { + union SIU_ORER_tag { uint32_t R; struct { uint32_t:16; @@ -5262,7 +5262,7 @@ extern "C" { } B; } ORER; /* Overrun Request Enable Register */ - union { + union SIU_IREER_tag { uint32_t R; struct { uint32_t NREE0:1; @@ -5287,7 +5287,7 @@ extern "C" { } B; } IREER; /* External IRQ Rising-Edge Event Enable Register */ - union { + union SIU_IFEER_tag { uint32_t R; struct { uint32_t NFEE0:1; @@ -5312,7 +5312,7 @@ extern "C" { } B; } IFEER; /* External IRQ Falling-Edge Event Enable Register */ - union { + union SIU_IDFR_tag { uint32_t R; struct { uint32_t:28; @@ -5354,7 +5354,7 @@ extern "C" { uint16_t PA:2; uint16_t OBE:1; uint16_t IBE:1; - uint16_t:2; + uint16_t DSC:2; uint16_t ODE:1; uint16_t HYS:1; uint16_t SRC:2; diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h index 638d679..4efa922 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h +++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h @@ -223,6 +223,12 @@ extern "C" { #define MPC55XX_IRQ_PIT_CHANNEL(ch) \ ((unsigned) (ch) < 9U ? 148U + (ch) : MPC55XX_IRQ_INVALID) + /* SIU external interrupts */ + #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U + #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U + #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U + #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U + /* eMIOS */ #define MPC55XX_IRQ_EMIOS(ch) \ ((unsigned) (ch) < 24U ? 58U + (ch) : \ From sebh at rtems.org Mon Aug 25 11:31:47 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 25 Aug 2014 06:31:47 -0500 Subject: [rtems commit] bsp/mpc55xx: Fix comment Message-ID: <20140825113147.4CFCA700810@git.rtems.org> Module: rtems Branch: master Commit: 4b104834ebd0faa1d631c037e92dde47c22d2fa2 Changeset: http://git.rtems.org/rtems/commit/?id=4b104834ebd0faa1d631c037e92dde47c22d2fa2 Author: Sebastian Huber Date: Mon Aug 25 13:39:34 2014 +0200 bsp/mpc55xx: Fix comment --- .../libcpu/powerpc/mpc55xx/misc/flash_support.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c index 74bbd39..2769efe 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c +++ b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c @@ -692,4 +692,4 @@ mpc55xx_flash_address(void) return mas2 & 0xFFFFF000; } -#endif /* MPC55XX_CHIP_TYPE / 100 == 55 */ +#endif /* MPC55XX_CHIP_FAMILY == 555 || MPC55XX_CHIP_FAMILY == 556 */ From joel at rtems.org Mon Aug 25 16:05:53 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 11:05:53 -0500 Subject: [rtems commit] Add or1k to the list of targets that use IEEE 754 in xdr_float.c Message-ID: <20140825160553.CEB3A700812@git.rtems.org> Module: rtems Branch: master Commit: e5f6ca87e122b85c1b757dfedd1432f60ea96c85 Changeset: http://git.rtems.org/rtems/commit/?id=e5f6ca87e122b85c1b757dfedd1432f60ea96c85 Author: Hesham ALMatary Date: Fri Aug 22 15:22:04 2014 -0500 Add or1k to the list of targets that use IEEE 754 in xdr_float.c --- cpukit/librpc/src/xdr/xdr_float.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/cpukit/librpc/src/xdr/xdr_float.c b/cpukit/librpc/src/xdr/xdr_float.c index 8640058..cf081a7 100644 --- a/cpukit/librpc/src/xdr/xdr_float.c +++ b/cpukit/librpc/src/xdr/xdr_float.c @@ -69,6 +69,7 @@ static char *rcsid = "$FreeBSD: src/lib/libc/xdr/xdr_float.c,v 1.7 1999/08/28 00 defined(__mips__) || defined(__moxie__) || \ defined(__nios2__) || \ defined(__ns32k__) || \ + defined(__or1k__) || \ defined(__sparc__) || \ defined(__ppc__) || defined(__PPC__) || \ defined(__sh__) || \ From joel at rtems.org Mon Aug 25 16:05:52 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 11:05:52 -0500 Subject: [rtems commit] sptests/spcache01: Make inline assembly conditional to account for OpenRISC l.nop instruction . Message-ID: <20140825160553.B50BD700A25@git.rtems.org> Module: rtems Branch: master Commit: 23b14f87cf701654b231017171a61b1e6fb4a322 Changeset: http://git.rtems.org/rtems/commit/?id=23b14f87cf701654b231017171a61b1e6fb4a322 Author: Hesham ALMatary Date: Fri Aug 22 15:20:16 2014 -0500 sptests/spcache01: Make inline assembly conditional to account for OpenRISC l.nop instruction. --- testsuites/sptests/spcache01/init.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/testsuites/sptests/spcache01/init.c b/testsuites/sptests/spcache01/init.c index 2c9d184..ad9b54f 100644 --- a/testsuites/sptests/spcache01/init.c +++ b/testsuites/sptests/spcache01/init.c @@ -27,7 +27,11 @@ const char rtems_test_name[] = "SPCACHE 1"; -#define I() __asm__ volatile ("nop") +#ifdef __or1k__ + #define I() __asm__ volatile ("l.nop") +#else + #define I() __asm__ volatile ("nop") +#endif #define I8() I(); I(); I(); I(); I(); I(); I(); I() From joel at rtems.org Mon Aug 25 16:05:52 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 11:05:52 -0500 Subject: [rtems commit] Rename or1k_or1ksim BSP to or1ksim Message-ID: <20140825160553.CA29C70080D@git.rtems.org> Module: rtems Branch: master Commit: 9d92a43ff74abb30e6cf9a58560183b58877408e Changeset: http://git.rtems.org/rtems/commit/?id=9d92a43ff74abb30e6cf9a58560183b58877408e Author: Hesham ALMatary Date: Fri Aug 22 15:21:35 2014 -0500 Rename or1k_or1ksim BSP to or1ksim --- .../make/custom/{or1k_or1ksim.cfg => or1ksim.cfg} | 0 1 files changed, 0 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/or1k/or1ksim/make/custom/or1k_or1ksim.cfg b/c/src/lib/libbsp/or1k/or1ksim/make/custom/or1ksim.cfg similarity index 100% rename from c/src/lib/libbsp/or1k/or1ksim/make/custom/or1k_or1ksim.cfg rename to c/src/lib/libbsp/or1k/or1ksim/make/custom/or1ksim.cfg From joel at rtems.org Mon Aug 25 16:05:53 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 11:05:53 -0500 Subject: [rtems commit] or1ksim BSP: Include cache manager stubs, and re-generate preinstall.am files. Message-ID: <20140825160553.A2618700814@git.rtems.org> Module: rtems Branch: master Commit: baa3c91ecb8a3b48ef387b938fcdb6e60b5bdc8a Changeset: http://git.rtems.org/rtems/commit/?id=baa3c91ecb8a3b48ef387b938fcdb6e60b5bdc8a Author: Hesham ALMatary Date: Fri Aug 22 15:22:37 2014 -0500 or1ksim BSP: Include cache manager stubs, and re-generate preinstall.am files. --- c/src/lib/libbsp/or1k/or1ksim/Makefile.am | 9 +++- c/src/lib/libbsp/or1k/or1ksim/preinstall.am | 71 ++++++++++++++------------ c/src/lib/libbsp/or1k/preinstall.am | 2 +- 3 files changed, 46 insertions(+), 36 deletions(-) diff --git a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am index d5eb10c..f1315c4 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am +++ b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am @@ -9,7 +9,7 @@ ACLOCAL_AMFLAGS = -I ../../../../aclocal include $(top_srcdir)/../../../../automake/compile.am include_bspdir = $(includedir)/bsp -#include_libcpudir = $(includedir)/libcpu +include_libcpudir = $(includedir)/libcpu dist_project_lib_DATA = bsp_specs @@ -21,7 +21,6 @@ include_bsp_HEADERS = include_HEADERS = include/bsp.h nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h - include_bsp_HEADERS += ../shared/include/linker-symbols.h include_bsp_HEADERS += ../../../libbsp/shared/include/mm.h include_bsp_HEADERS += ../../shared/include/utility.h @@ -99,6 +98,12 @@ libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c libbsp_a_SOURCES += ../../shared/src/irq-generic.c libbsp_a_SOURCES += ../../shared/src/irq-info.c libbsp_a_SOURCES += irq/irq.c + +# Cache +libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c +libbsp_a_SOURCES += ../../shared/include/cache_.h +libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include + ############################################################################### # Special Rules # ############################################################################### diff --git a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am index e75733c..cbdf3df 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am +++ b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am @@ -2,113 +2,118 @@ if AMPOLISH3 $(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_LIB) - @: > $(PROJECT_LIB)/$(dirstamp) + @$(MKDIR_P) $(PROJECT_LIB) + @: > $(PROJECT_LIB)/$(dirstamp) PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) $(PROJECT_INCLUDE)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE) - @: > $(PROJECT_INCLUDE)/$(dirstamp) + @$(MKDIR_P) $(PROJECT_INCLUDE) + @: > $(PROJECT_INCLUDE)/$(dirstamp) PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) $(PROJECT_INCLUDE)/bsp/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp - @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp + @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) +$(PROJECT_INCLUDE)/libcpu/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu + @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) + $(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs + $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs $(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h $(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h $(PROJECT_INCLUDE)/bsp/linker-symbols.h: ../shared/include/linker-symbols.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/linker-symbols.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/linker-symbols.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/linker-symbols.h $(PROJECT_INCLUDE)/bsp/mm.h: ../../../libbsp/shared/include/mm.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mm.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mm.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mm.h $(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h $(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h $(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h $(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h $(PROJECT_INCLUDE)/bsp/uart-output-char.h: ../../shared/include/uart-output-char.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart-output-char.h $(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h $(PROJECT_INCLUDE)/bsp/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tm27.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tm27.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tm27.h $(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h $(PROJECT_INCLUDE)/bsp/uart.h: include/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h $(PROJECT_INCLUDE)/bsp/or1ksim.h: include/or1ksim.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/or1ksim.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/or1ksim.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/or1ksim.h $(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h $(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) + $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds $(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base diff --git a/c/src/lib/libbsp/or1k/preinstall.am b/c/src/lib/libbsp/or1k/preinstall.am index fe8d090..1143c2e 100644 --- a/c/src/lib/libbsp/or1k/preinstall.am +++ b/c/src/lib/libbsp/or1k/preinstall.am @@ -2,5 +2,5 @@ if AMPOLISH3 $(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif From joel at rtems.org Mon Aug 25 16:05:52 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 11:05:52 -0500 Subject: [rtems commit] libcpu: Add new entry for or1k cpu and include cache manager stubs. Message-ID: <20140825160553.64987700A5B@git.rtems.org> Module: rtems Branch: master Commit: eeea9e30a2c5d3ea01e9fc13202fa77e22bd0f02 Changeset: http://git.rtems.org/rtems/commit/?id=eeea9e30a2c5d3ea01e9fc13202fa77e22bd0f02 Author: Hesham ALMatary Date: Fri Aug 22 15:20:47 2014 -0500 libcpu: Add new entry for or1k cpu and include cache manager stubs. --- c/src/lib/libcpu/or1k/Makefile.am | 20 +++++++++++++++++ c/src/lib/libcpu/or1k/configure.ac | 31 +++++++++++++++++++++++++++ c/src/lib/libcpu/or1k/preinstall.am | 23 ++++++++++++++++++++ c/src/lib/libcpu/or1k/shared/cache/cache_.h | 11 +++++++++ 4 files changed, 85 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libcpu/or1k/Makefile.am b/c/src/lib/libcpu/or1k/Makefile.am new file mode 100644 index 0000000..f4a6372 --- /dev/null +++ b/c/src/lib/libcpu/or1k/Makefile.am @@ -0,0 +1,20 @@ +ACLOCAL_AMFLAGS = -I ../../../aclocal + +include $(top_srcdir)/../../../automake/compile.am + +CLEANFILES = +DISTCLEANFILES = +noinst_PROGRAMS = + +include_libcpudir = $(includedir)/libcpu + +## shared/cache +include_libcpu_HEADERS = ../shared/include/cache.h +noinst_PROGRAMS += shared/cache.rel +shared_cache_rel_SOURCES = ../shared/src/no_cache.c shared/cache/cache_.h +shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache +shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + +include $(srcdir)/preinstall.am + +include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/or1k/configure.ac b/c/src/lib/libcpu/or1k/configure.ac new file mode 100644 index 0000000..c87c0f1 --- /dev/null +++ b/c/src/lib/libcpu/or1k/configure.ac @@ -0,0 +1,31 @@ +## Process this file with autoconf to produce a configure script. + +AC_PREREQ([2.69]) +AC_INIT([rtems-c-src-lib-libcpu-or1k],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla]) +RTEMS_TOP([../../../../..],[../../..]) + +RTEMS_CANONICAL_TARGET_CPU + +AM_INIT_AUTOMAKE([no-define foreign subdir-objects 1.12.2]) +AM_MAINTAINER_MODE + +RTEMS_ENV_RTEMSBSP + +RTEMS_PROJECT_ROOT + +RTEMS_PROG_CC_FOR_TARGET +AM_PROG_CC_C_O +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +# At this time all models should use the shared directory so do this +AM_CONDITIONAL(shared, true) + +AC_PATH_PROG([AMPOLISH3],[ampolish3],[]) + +RTEMS_AMPOLISH3 + +# Explicitly list all Makefiles here +AC_CONFIG_FILES([Makefile +]) +AC_OUTPUT diff --git a/c/src/lib/libcpu/or1k/preinstall.am b/c/src/lib/libcpu/or1k/preinstall.am new file mode 100644 index 0000000..9670596 --- /dev/null +++ b/c/src/lib/libcpu/or1k/preinstall.am @@ -0,0 +1,23 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +$(PROJECT_INCLUDE)/libcpu/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu + @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) + +$(PROJECT_INCLUDE)/libcpu/cache.h: ../shared/include/cache.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache.h diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h b/c/src/lib/libcpu/or1k/shared/cache/cache_.h new file mode 100644 index 0000000..08d9ecc --- /dev/null +++ b/c/src/lib/libcpu/or1k/shared/cache/cache_.h @@ -0,0 +1,11 @@ +/* + * or1k Cache Manager Support + */ + +#ifndef __OR1K_CACHE_H +#define __OR1K_CACHE_H + +#include + +#endif +/* end of include file */ From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] or1k/Makefile.am: libbsp_a_CPPFLAGS was defined twice Message-ID: <20140825222255.7D48E700814@git.rtems.org> Module: rtems Branch: master Commit: 8f1bdcb9ada7d02d9dcc1ef03e3787a48fc7ddf8 Changeset: http://git.rtems.org/rtems/commit/?id=8f1bdcb9ada7d02d9dcc1ef03e3787a48fc7ddf8 Author: Joel Sherrill Date: Mon Aug 25 17:07:12 2014 -0500 or1k/Makefile.am: libbsp_a_CPPFLAGS was defined twice --- c/src/lib/libbsp/or1k/or1ksim/Makefile.am | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am index f1315c4..1ff43ed 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am +++ b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am @@ -102,7 +102,7 @@ libbsp_a_SOURCES += irq/irq.c # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c libbsp_a_SOURCES += ../../shared/include/cache_.h -libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include +libbsp_a_CPPFLAGS += -I$(srcdir)/../../shared/include ############################################################################### # Special Rules # From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] gensh4/bsp_specs: Account for big/little endian Message-ID: <20140825222255.2C0B4700812@git.rtems.org> Module: rtems Branch: master Commit: bf1f8764831eb20cccecc9a45f5ec8e30bbcebc2 Changeset: http://git.rtems.org/rtems/commit/?id=bf1f8764831eb20cccecc9a45f5ec8e30bbcebc2 Author: Joel Sherrill Date: Mon Aug 25 16:52:45 2014 -0500 gensh4/bsp_specs: Account for big/little endian --- c/src/lib/libbsp/sh/gensh4/bsp_specs | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/sh/gensh4/bsp_specs b/c/src/lib/libbsp/sh/gensh4/bsp_specs index 975c0b2..5151eaa 100644 --- a/c/src/lib/libbsp/sh/gensh4/bsp_specs +++ b/c/src/lib/libbsp/sh/gensh4/bsp_specs @@ -7,7 +7,7 @@ %{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}} *link: -%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} %{ml|!mb:-EL}%{mb:-EB} *endfile: %{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s} From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] gensh4: Improve ROM vs RAM startup configuration Message-ID: <20140825222254.E858E700810@git.rtems.org> Module: rtems Branch: master Commit: 3d99c17deb0e61db71e332a6890bce0651500de7 Changeset: http://git.rtems.org/rtems/commit/?id=3d99c17deb0e61db71e332a6890bce0651500de7 Author: Joel Sherrill Date: Mon Aug 25 16:53:13 2014 -0500 gensh4: Improve ROM vs RAM startup configuration --- c/src/lib/libbsp/sh/gensh4/configure.ac | 13 +++++++------ c/src/lib/libbsp/sh/gensh4/start/start.S | 12 +++++++++--- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/c/src/lib/libbsp/sh/gensh4/configure.ac b/c/src/lib/libbsp/sh/gensh4/configure.ac index eeaf6d8..372d65a 100644 --- a/c/src/lib/libbsp/sh/gensh4/configure.ac +++ b/c/src/lib/libbsp/sh/gensh4/configure.ac @@ -23,12 +23,13 @@ AC_DEFINE_UNQUOTED( # START_HW_INIT # This switch selects whether 'early_hw_init()' is called from # 'start.S'; 'bsp_hw_init()' is always called from 'bspstart.c' -# -START_HW_INIT=${START_HW_INIT-1} -AC_DEFINE_UNQUOTED( - [START_HW_INIT], - [$START_HW_INIT], - [Whether to call early_hw_init from start.S]) +RTEMS_BSPOPTS_SET([START_HW_INIT],[*],[0]) +RTEMS_BSPOPTS_HELP([START_HW_INIT], + [Whether to call early_hw_init from start.S]) + +RTEMS_BSPOPTS_SET([COPY_DATA_FROM_ROM],[*],[0]) +RTEMS_BSPOPTS_HELP([COPY_DATA_FROM_ROM], + [Whether to copy data from ROM to RAM in start.S]) RTEMS_BSP_CLEANUP_OPTIONS(0, 0) diff --git a/c/src/lib/libbsp/sh/gensh4/start/start.S b/c/src/lib/libbsp/sh/gensh4/start/start.S index 7dce1a7..a695daa 100644 --- a/c/src/lib/libbsp/sh/gensh4/start/start.S +++ b/c/src/lib/libbsp/sh/gensh4/start/start.S @@ -80,10 +80,10 @@ fake_func: bt hw_init_end nop -#if defined(START_HW_INIT) /* from $RTEMS_BSP.cfg */ +#if START_HW_INIT /* from $RTEMS_BSP.cfg */ ! Initialize minimal hardware ! to run hw_init we need to calculate its address - ! as it is before data coping + ! as it is before data copying mov.l hw_init_k, r0 mov.l copy_start_k, r1 mov.l copy_end_k, r2 @@ -102,6 +102,7 @@ fake_func: #endif /* START_HW_INIT */ hw_init_end: +#if COPY_DATA_FROM_ROM ! copy data from rom to ram mov.l copy_start_k, r0 mov.l copy_end_k, r1 @@ -123,6 +124,7 @@ copy_data_cycle: nop end_of_copy_data_cycle: +#endif ! go to 0x8....... adresses mov.l real_address_k, r0 lds r0, pr @@ -193,12 +195,16 @@ __stop: END_CODE .align 2 +#if START_HW_INIT copy_start_k: .long copy_start copy_end_k: .long copy_end +#endif +#if COPY_DATA_FROM_ROM copy_start_in_rom_k: .long copy_start_in_rom +#endif real_address_k: .long real_address @@ -219,7 +225,7 @@ main_k: exit_k: .long SYM(_exit) -#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ +#if START_HW_INIT /* from $RTEMS_BSP.cfg */ hw_init_k: .long SYM(early_hw_init) #endif /* START_HW_INIT */ From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] simsh2e-testsuite.tcfg: new file Message-ID: <20140825222254.76E1B700A5D@git.rtems.org> Module: rtems Branch: master Commit: d26cded81b50f2b02da5d11823c43265094a851d Changeset: http://git.rtems.org/rtems/commit/?id=d26cded81b50f2b02da5d11823c43265094a851d Author: Joel Sherrill Date: Mon Aug 25 16:51:30 2014 -0500 simsh2e-testsuite.tcfg: new file --- .../sh/shsim/make/custom/simsh2e-testsuite.tcfg | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg index 2374bb2..6cf297a 100644 --- a/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg +++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg @@ -1,5 +1,9 @@ # -# The GDB SH Simulator does not have a tick interrupt. +# The GDB SH Simulator does not have a tick interrupt +# and the simsh2e configuration has limited memory. # include: testdata/require-tick-isr.tcfg + +fsdosfsname01 +utf8proc01 From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] shsim/bsp_specs: Account for big/little endian Message-ID: <20140825222255.0AF80700A25@git.rtems.org> Module: rtems Branch: master Commit: a4d355b426576ec9ad550b3eb0329d5860957e99 Changeset: http://git.rtems.org/rtems/commit/?id=a4d355b426576ec9ad550b3eb0329d5860957e99 Author: Joel Sherrill Date: Mon Aug 25 16:50:13 2014 -0500 shsim/bsp_specs: Account for big/little endian --- c/src/lib/libbsp/sh/shsim/bsp_specs | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/sh/shsim/bsp_specs b/c/src/lib/libbsp/sh/shsim/bsp_specs index 975c0b2..70c5ecb 100644 --- a/c/src/lib/libbsp/sh/shsim/bsp_specs +++ b/c/src/lib/libbsp/sh/shsim/bsp_specs @@ -7,7 +7,7 @@ %{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}} *link: -%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} %{ml:-EL}%{mb:-EB} *endfile: %{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s} From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] simsh4-testsuite.tcfg: new file Message-ID: <20140825222254.CD66370080D@git.rtems.org> Module: rtems Branch: master Commit: e75907d58ea61dad96602027f8c8fb949492d9d9 Changeset: http://git.rtems.org/rtems/commit/?id=e75907d58ea61dad96602027f8c8fb949492d9d9 Author: Joel Sherrill Date: Mon Aug 25 16:51:44 2014 -0500 simsh4-testsuite.tcfg: new file --- .../sh/shsim/make/custom/simsh4-testsuite.tcfg | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg index 2374bb2..6c9e078 100644 --- a/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg +++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg @@ -1,5 +1,9 @@ # -# The GDB SH Simulator does not have a tick interrupt. +# The GDB SH Simulator does not have a tick interrupt +# and the simsh4 configuration has limited memory. # include: testdata/require-tick-isr.tcfg + +fsdosfsname01 +utf8proc01 From chrisj at rtems.org Tue Aug 26 04:51:22 2014 From: chrisj at rtems.org (Chris Johns) Date: Mon, 25 Aug 2014 23:51:22 -0500 Subject: [rtems-tools commit] gdb-python: Update so 'rtems task' lists the classic tasks. Message-ID: <20140826045123.33E55700810@git.rtems.org> Module: rtems-tools Branch: master Commit: 3162858a3a0ec414d2b5ce3d9153ca0efb2c9d27 Changeset: http://git.rtems.org/rtems-tools/commit/?id=3162858a3a0ec414d2b5ce3d9153ca0efb2c9d27 Author: Chris Johns Date: Tue Aug 26 14:57:57 2014 +1000 gdb-python: Update so 'rtems task' lists the classic tasks. This is a first pass at cleaning up the support. To use: $ waf configure --prefix=$HOME/development/rtems/4.11 $ waf build install Start GDB and break at Init: (gdb) py import rtems (gdb) rtems task will list the classic API tasks. --- tools/gdb/python/__init__.py | 44 ++++++++++-- tools/gdb/python/chains.py | 32 ++++++++- tools/gdb/python/classic.py | 95 +++++++++++++++++-------- tools/gdb/python/configuration.py | 110 ++++++++++++++++++++++++++++ tools/gdb/python/heaps.py | 31 ++++++++- tools/gdb/python/helper.py | 31 ++++++++- tools/gdb/python/objects.py | 126 ++++++++++++++++++++------------ tools/gdb/python/percpu.py | 57 +++++++++++++++ tools/gdb/python/pretty.py | 29 ++++++++ tools/gdb/python/rtems.py | 126 +++++++++++++++++++++++---------- tools/gdb/python/sparc.py | 4 +- tools/gdb/python/supercore.py | 29 ++++++++ tools/gdb/python/supercore_printer.py | 31 ++++++++- tools/gdb/python/threads.py | 122 +++++++++++++++++++++++++++++--- tools/gdb/python/watchdog.py | 34 ++++++++- tools/gdb/python/wscript | 34 +++++---- 16 files changed, 778 insertions(+), 157 deletions(-) diff --git a/tools/gdb/python/__init__.py b/tools/gdb/python/__init__.py index 36d2c06..58c8625 100644 --- a/tools/gdb/python/__init__.py +++ b/tools/gdb/python/__init__.py @@ -1,8 +1,40 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# -if __name__ == "__main__": - import sys - import os.path - sys.path.append(os.path.dirname(__file__)) - import main +import gdb +import rtems - print 'RTEMS GDB Support loaded' +def get_architure(): + frame = gdb.selected_frame() + arch = frame.architecture() + return arch.name() + +_cmds = rtems.create() + +print 'RTEMS GDB Support' diff --git a/tools/gdb/python/chains.py b/tools/gdb/python/chains.py index ef33ed6..6ae2518 100644 --- a/tools/gdb/python/chains.py +++ b/tools/gdb/python/chains.py @@ -1,8 +1,34 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Chains Support -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. # -# $Id$ +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# RTEMS Chains Support # import gdb diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index e492657..44a92b4 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -1,8 +1,34 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Classic API Support -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # -# $Id$ +# RTEMS Classic API Support # import gdb @@ -16,7 +42,6 @@ import threads import watchdog import heaps import supercore -import sparc class attribute: """The Classic API attribute.""" @@ -110,7 +135,8 @@ class semaphore: "Print a classic semaphore." def __init__(self, obj): - self.object = obj + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'semaphore') @@ -152,29 +178,38 @@ class task: "Print a classic task" def __init__(self, obj): - self.object = obj - self.task = \ - threads.control(self.object) + self.reference = obj + self.object = obj.dereference() + self.task = threads.control(self.reference) self.wait_info = self.task.wait_info() - # ToDo: Insert platform dep. code here. - self.regs = sparc.register(self.object['Registers']) + self.regs = self.task.registers() + #self.regs = sparc.register(self.object['Registers']) def show(self, from_tty): - print ' Name:', self.task.name() - print ' State:', self.task.current_state() - print ' Current:', self.task.current_priority() - print ' Real:', self.task.real_priority() - print ' Preempt:', self.task.preemptible() - print ' T Budget:', self.task.cpu_time_budget() - print ' Regsters:' - self.regs.show() - + cpu = self.task.executing() + if cpu == -1: + cpu = 'not executing' + print ' Id:', '0x%08x' % (self.task.id()) + print ' Name:', self.task.name() + print ' Active CPU:', cpu + print ' State:', self.task.current_state() + print ' Current:', self.task.current_priority() + print ' Real:', self.task.real_priority() + print ' Preempt:', self.task.preemptible() + print ' T Budget:', self.task.cpu_time_budget() + print ' Time:', self.task.cpu_time_used() + print ' Resources:', self.task.resource_count() + print ' Regsters:' + for name in self.regs.names(): + val = self.regs.get(name) + print ' %20s: %08x (%d)' % (name, val, val) class message_queue: "Print classic messege queue" - def __init__(self,obj): - self.object = obj + def __init__(self, obj): + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], \ 'message_queue') @@ -193,7 +228,8 @@ class timer: '''Print a classic timer''' def __init__(self, obj): - self.object = obj + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.watchdog = watchdog.control(self.object['Ticker']) @@ -205,7 +241,8 @@ class partition: ''' Print a rtems partition ''' def __init__(self, obj): - self.object = obj + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'partition') self.starting_addr = self.object['starting_address'] @@ -224,8 +261,9 @@ class partition: class region: "prints a classic region" - def __init__(self,obj): - self.object = obj + def __init__(self, obj): + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'region') self.wait_queue = threads.queue(self.object['Wait_queue']) @@ -241,8 +279,9 @@ class region: class barrier: '''classic barrier abstraction''' - def __init__(self,obj): - self.object = obj + def __init__(self, obj): + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'],'barrier') self.core_b_control = supercore.barrier_control(self.object['Barrier']) @@ -257,5 +296,3 @@ class barrier: print ' Waiting:',self.core_b_control.waiting_threads() helper.tasks_printer_routine(self.core_b_control.tasks()) - - diff --git a/tools/gdb/python/configuration.py b/tools/gdb/python/configuration.py new file mode 100644 index 0000000..d20224b --- /dev/null +++ b/tools/gdb/python/configuration.py @@ -0,0 +1,110 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# RTEMS Configuration Table +# + +import gdb + +def _table(): + return gdb.parse_and_eval('Configuration') + +def fields(): + return [field.name for field in _table().type.fields()] + +def mp(): + return '_Configuration_MP_table' in fields() + +def smp(): + if 'smp_enabled' in fields(): + return int(_table()['smp_enabled']) != 0 + return False + +def maximum_processors(): + if smp(): + return int(_table()['maximum_processors']) + return 1 + +def work_space_size(): + return long(_table()['work_space_size']) + +def stack_space_size(): + return long(_table()['stack_space_size']) + +def maximum_extensions(): + return long(_table()['maximum_extensions']) + +def maximum_keys(): + return long(_table()['maximum_keys']) + +def maximum_key_value_pairs(): + return long(_table()['maximum_key_value_pairs']) + +def microseconds_per_tick(): + return long(_table()['microseconds_per_tick']) + +def nanoseconds_per_tick(): + return long(_table()['nanoseconds_per_tick']) + +def ticks_per_timeslice(): + return long(_table()['ticks_per_timeslice']) + +def idle_task(): + return long(_table()['idle_task']) + +def idle_task_stack_size(): + return long(_table()['idle_task_stack_size']) + +def interrupt_stack_size(): + return long(_table()['interrupt_stack_size']) + +def stack_allocate_init_hook(): + return long(_table()['stack_allocate_init_hook']) + +def stack_allocate_hook(): + return long(_table()['stack_allocate_hook']) + +def stack_free_hook(): + return long(_table()['stack_free_hook']) + +def do_zero_of_workspace(): + return int(_table()['do_zero_of_workspace']) != 0 + +def unified_work_area(): + return int(_table()['unified_work_area']) != 0 + +def stack_allocator_avoids_work_space(): + return long(_table()['stack_allocator_avoids_work_space']) + +def number_of_initial_extensions(): + return int(_table()['number_of_initial_extensions']) + +def user_extension_table(): + return _table()['User_extension_table'] diff --git a/tools/gdb/python/heaps.py b/tools/gdb/python/heaps.py index 2cc7907..e843f33 100644 --- a/tools/gdb/python/heaps.py +++ b/tools/gdb/python/heaps.py @@ -1,3 +1,32 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # # RTEMS heap # @@ -81,4 +110,4 @@ class control: stats = self.stat() print ' stats:' - stats.show() \ No newline at end of file + stats.show() diff --git a/tools/gdb/python/helper.py b/tools/gdb/python/helper.py index dfd01eb..5efcf02 100644 --- a/tools/gdb/python/helper.py +++ b/tools/gdb/python/helper.py @@ -1,5 +1,34 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # # RTEMS GDB support helper routins. +# import gdb @@ -18,4 +47,4 @@ def type_from_value(val): return type.unqualified () def test_bit(val, pos): - return bool(val & (1 << (pos-1))) \ No newline at end of file + return bool(val & (1 << (pos-1))) diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index ee59cbc..4898d81 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -1,15 +1,41 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Objects Support -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # -# $Id$ +# RTEMS Objects Support # import gdb import itertools import re -class infotables: +class infotables(): """Manage the object information tables.""" tables_types = { @@ -36,7 +62,7 @@ class infotables: self.tables = {} def name(self, api, _class): - return api + '/' + _class + return '%s/%s' % (api, _class) def load(self, n): if n in self.tables_types: @@ -50,6 +76,16 @@ class infotables: return self.tables[n] return None + def minimum_id(self, api, _class): + n = self.name(api, _class) + self.load(n) + return int(self.tables[n]['minimum_id']) + + def maximum_id(self, api, _class): + n = self.name(api, _class) + self.load(n) + return int(self.tables[n]['maximum_id']) + def maximum(self, api, _class): n = self.name(api, _class) self.load(n) @@ -71,18 +107,14 @@ class infotables: def object_return(self, api, _class, index=-1): n = self.name(api, _class) self.load(n) - table_type = self.tables_types[n] - if api == 'internal': - expr = '(' + table_type[0] + ')' + table_type[1] - + expr = '(%s) %s' % (table_type[0], table_type[1]) else: max = self.maximum(api, _class) if index > max: raise IndexError('object index out of range (%d)' % (max)) - expr = '(' + table_type[0] + '*)' + \ - table_type[1] + '.local_table[' + str(index) + ']' + expr = '(%s*) %s.local_table[%d]' % (table_type[0], table_type[1], index) return gdb.parse_and_eval(expr) def is_string(self, api, _class): @@ -98,7 +130,7 @@ class infotables: # information = infotables() -class ident: +class ident(): "An RTEMS object id with support for its bit fields." bits = [ @@ -113,14 +145,13 @@ class ident: ] OBJECT_16_BITS = 0 - OBJECT_31_BITS = 1 + OBJECT_32_BITS = 1 api_labels = [ 'none', 'internal', 'classic', - 'posix', - 'itron' + 'posix' ] class_labels = { @@ -150,15 +181,6 @@ class ident: 'barriers', 'spinlocks', 'rwlocks'), - 'itron' : ('none', - 'tasks', - 'eventflags', - 'mailboxes', - 'message_buffers', - 'ports', - 'semaphores', - 'variable_memory_pools', - 'fixed_memory_pools') } def __init__(self, id): @@ -170,7 +192,7 @@ class ident: if self.id.type.sizeof == 2: self.idSize = self.OBJECT_16_BITS else: - self.idSize = self.OBJECT_31_BITS + self.idSize = self.OBJECT_32_BITS def get(self, field): if field in self.bits[self.idSize]: @@ -212,7 +234,7 @@ class ident: def valid(self): return self.api() != 'none' and self._class() != 'invalid' -class name: +class name(): """The Objects_Name can either be told what the name is or can take a guess.""" @@ -220,6 +242,10 @@ class name: self.name = name if is_string == None: self.is_string = 'auto' + try: + self.name_p = self.name['name_p'] + except gdb.Error: + self.is_string = 'no' else: if is_string: self.is_string = 'yes' @@ -227,25 +253,39 @@ class name: self.is_string = 'no' def __str__(self): + return self.get() + + def get(self): if self.is_string != 'yes': u32 = int(self.name['name_u32']) - s = chr((u32 >> 24) & 0xff) + \ - chr((u32 >> 16) & 0xff) + chr((u32 >> 8) & 0xff) + \ - chr(u32 & 0xff) - for c in range(0,4): - if s[c] < ' ' or s[c] > '~': - s = None - break - if s: - return s - return str(self.name['name_p'].dereference()) - -class control: + if u32 != 0: + s = chr((u32 >> 24) & 0xff) + \ + chr((u32 >> 16) & 0xff) + \ + chr((u32 >> 8) & 0xff) + \ + chr(u32 & 0xff) + for c in range(0, 4): + if s[c] < ' ' or s[c] > '~': + s = None + break + if s: + return s + if self.is_string == 'xno': + return None + try: + name_p = self.name['name_p'] + return str(name_p.dereference()) + except gdb.Error: + pass + return None + +class control(): """The Objects_Control structure.""" def __init__(self, object): self.object = object self._id = ident(self.object['id']) + self._name = name(self.object['name'], + information.is_string(self._id.api(), self._id._class())) def node(self): return self.object['Node'] @@ -254,12 +294,4 @@ class control: return self.object['id'] def name(self): - is_string = information.is_string(self._id.api(), self._id._class()) - val = str(name(self.object['name'],is_string)) - - # Normal comaprision is a bit tricky with quotes - # 0 '\000' in hex == '3020275c30303027' - if val.encode('hex') == '3020275c30303027': - val = "" - - return val \ No newline at end of file + return self._name.get() diff --git a/tools/gdb/python/percpu.py b/tools/gdb/python/percpu.py new file mode 100644 index 0000000..991bdf8 --- /dev/null +++ b/tools/gdb/python/percpu.py @@ -0,0 +1,57 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# RTEMS Per CPU Table +# + +import gdb + +import configuration + +def _table(cpu): + max_cpus = configuration.maximum_processors() + if cpu >= max_cpus: + raise IndexError('cpu index out of range (%d)' % (max_cpus)) + return gdb.parse_and_eval('_Per_CPU_Information[%d].per_cpu' % (cpu)) + +def get(cpu): + return _table(cpu) + +def thread_active(thread): + for cpu in range(0, configuration.maximum_processors()): + if thread == _table(cpu)['executing']: + return cpu + return -1 + +def thread_heir(thread): + for cpu in range(0, configuration.maximum_processors()): + if thread == _table(cpu)['heir']: + return cpu + return -1 diff --git a/tools/gdb/python/pretty.py b/tools/gdb/python/pretty.py index 929c245..3cbe052 100644 --- a/tools/gdb/python/pretty.py +++ b/tools/gdb/python/pretty.py @@ -1,6 +1,35 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # # RTEMS pretty printers # + import re import helper import objects diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 6c987cf..534cb0d 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -1,8 +1,34 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Pretty Printers -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. # -# $Id$ +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# RTEMS Pretty Printers # import gdb @@ -29,18 +55,18 @@ class rtems_object(gdb.Command): """Object sub-command for RTEMS""" objects = { - 'classic/semaphores': lambda obj: classic.semaphore(obj), - 'classic/tasks': lambda obj: classic.task(obj), + 'classic/semaphores': lambda obj: classic.semaphore(obj), + 'classic/tasks': lambda obj: classic.task(obj), 'classic/message_queues': lambda obj: classic.message_queue(obj), - 'classic/timers' : lambda obj: classic.timer(obj), - 'classic/partitions' : lambda obj: classic.partition(obj), - 'classic/regions' : lambda obj: classic.region(obj), - 'classic/barriers' : lambda obj: classic.barrier(obj) - } + 'classic/timers' : lambda obj: classic.timer(obj), + 'classic/partitions' : lambda obj: classic.partition(obj), + 'classic/regions' : lambda obj: classic.region(obj), + 'classic/barriers' : lambda obj: classic.barrier(obj) + } def __init__(self): - self.__doc__ = 'Display the RTEMS object given a numeric ID \ - (Or a reference to rtems_object).' + self.__doc__ = 'Display the RTEMS object given a numeric ID' \ + '(Or a reference to the object).' super(rtems_object, self).__init__('rtems object', gdb.COMMAND_DATA, gdb.COMPLETE_SYMBOL) @@ -79,29 +105,47 @@ class rtems_index(gdb.Command): gdb.COMMAND_DATA, gdb.COMPLETE_NONE) - def instance(self,obj): - '''Returns a n instance of corresponding object, the child should extend this''' + def instance(self, obj): + '''Returns a n instance of corresponding object, the child should extend + this''' return obj def invoke(self, arg, from_tty): - for val in arg.split(): - try: - index = int(val) - except ValueError: - print "error: %s is not an index" % (val) - return - try: - obj = objects.information.object_return( self.api, - self._class, - index ).dereference() - except IndexError: - print "error: index %s is invalid" % (index) - return - - instance = self.instance(obj) - instance.show(from_tty) - objects.information.invalidate() - + maximum = objects.information.maximum(self.api, self._class) + minimum_id = objects.ident(objects.information.minimum_id(self.api, self._class)) + maximum_id = objects.ident(objects.information.minimum_id(self.api, self._class)) + args = arg.split() + if len(args): + for val in args: + try: + index = int(val, base = 0) + if index < maximum: + if index < minimum_id.index(): + print "error: %s is not an index (min is %d)" % (val, + minimum_id.index()) + return + else: + index = objects.ident(index).index() + except ValueError: + print "error: %s is not an index" % (val) + return + try: + obj = objects.information.object_return(self.api, + self._class, + index) + except IndexError: + print "error: index %s is invalid" % (index) + return + instance = self.instance(obj) + instance.show(from_tty) + objects.information.invalidate() + else: + print '-' * 70 + print ' %s: %d [%08x -> %08x]' % (objects.information.name(self.api, self._class), + maximum, minimum_id.value(), maximum_id.value()) + for index in range(minimum_id.index(), minimum_id.index() + maximum): + print '-' * 70 + self.invoke(str(index), from_tty) class rtems_semaphore(rtems_index): '''semaphore subcommand''' @@ -111,7 +155,7 @@ class rtems_semaphore(rtems_index): self.__doc__ = 'Display RTEMS semaphore(s) by index(es)' super(rtems_semaphore, self).__init__('rtems semaphore') - def instance(self,obj): + def instance(self, obj): return classic.semaphore(obj) class rtems_task(rtems_index): @@ -123,10 +167,9 @@ class rtems_task(rtems_index): self.__doc__ = 'Display RTEMS task(s) by index(es)' super(rtems_task,self).__init__('rtems task') - def instance(self,obj): + def instance(self, obj): return classic.task(obj) - class rtems_message_queue(rtems_index): '''Message Queue subcommand''' @@ -136,7 +179,7 @@ class rtems_message_queue(rtems_index): self.__doc__ = 'Display RTEMS message_queue(s) by index(es)' super(rtems_message_queue,self).__init__('rtems mqueue') - def instance(self,obj): + def instance(self, obj): return classic.message_queue(obj) class rtems_timer(rtems_index): @@ -148,7 +191,7 @@ class rtems_timer(rtems_index): self.__doc__ = 'Display RTEMS timer(s) by index(es)' super(rtems_timer, self).__init__('rtems timer') - def instance(self,obj): + def instance(self, obj): return classic.timer(obj) class rtems_partition(rtems_index): @@ -252,3 +295,12 @@ class rtems_wsec(rtems_watchdog_chain): self.__doc__ = 'Display watchdog seconds chain' super(rtems_wsec, self).__init__('rtems wdseconds') +def create(): + return (rtems(), + rtems_object(), + rtems_semaphore(), + rtems_task(), + rtems_message_queue(), + rtems_tod(), + rtems_wdt(), + rtems_wsec()) diff --git a/tools/gdb/python/sparc.py b/tools/gdb/python/sparc.py index 70ef5d3..41b6fec 100644 --- a/tools/gdb/python/sparc.py +++ b/tools/gdb/python/sparc.py @@ -73,7 +73,7 @@ class register: return val - def __init__(self,reg): + def __init__(self, reg): self.reg = reg def global_regs(self): @@ -139,4 +139,4 @@ class register: print '\b\b ]' sr = self.status() - print sr.to_string() \ No newline at end of file + print sr.to_string() diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py index 6116626..0790cc9 100644 --- a/tools/gdb/python/supercore.py +++ b/tools/gdb/python/supercore.py @@ -1,3 +1,32 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # # RTEMS Supercore Objects # diff --git a/tools/gdb/python/supercore_printer.py b/tools/gdb/python/supercore_printer.py index 3ce8110..61241e3 100644 --- a/tools/gdb/python/supercore_printer.py +++ b/tools/gdb/python/supercore_printer.py @@ -1,6 +1,35 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # # RTEMS Supercore pretty printers for GDB # + import objects import itertools import threads @@ -138,4 +167,4 @@ class node: self.node = chains.node(node) def to_string(self): - return "Node: "+str(self.node)+" Next: "+str(self.node.next())+" Prev: "+str(self.node.previous()) \ No newline at end of file + return "Node: "+str(self.node)+" Next: "+str(self.node.next())+" Prev: "+str(self.node.previous()) diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py index 7098481..1719187 100644 --- a/tools/gdb/python/threads.py +++ b/tools/gdb/python/threads.py @@ -1,13 +1,41 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Threads Support -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. # -# $Id$ + +# +# RTEMS Threads Support # import gdb + import chains import objects +import percpu def task_chain(chain): tasks = [] @@ -17,7 +45,7 @@ def task_chain(chain): node.next() return tasks -class state: +class state(): ALL_SET = 0x000fffff READY = 0x00000000 @@ -100,7 +128,7 @@ class state: s = self.masks[m] + ',' return s[:-1] -class wait_info: +class wait_info(): def __init__(self, info): self.info = info @@ -123,11 +151,68 @@ class wait_info: def queue(self): return task_chain(chains.control(self.info['queue'])) -class control: +class registers(): + + def __init__(self, regs): + self.regs = regs + + def names(self): + return [field.name for field in self.regs.type.fields()] + + def get(self, reg): + t = str(self.regs[reg].type) + if t in ['double']: + return float(self.regs[reg]) + return int(self.regs[reg]) + + + def format(self, reg): + t = self.regs[reg].type + if t in ['uint32_t', 'unsigned', 'unsigned long']: + return '%08x (%d)' % (val) + +class control(): + ''' + Thread_Control has the following fields: + Object Objects_Control + RBNode RBTree_Node + current_state States_Control + current_priority Priority_Control + real_priority Priority_Control + resource_count uint32_t + Wait Thread_Wait_information + Timer Watchdog_Control + receive_packet MP_packet_Prefix* X + lock_mutex Chain_Control X + Resource_node Resource_Node X + is_global bool X + is_preemptible bool + Scheduler Thread_Scheduler_control + rtems_ada_self void* X + cpu_time_budget uint32_t + budget_algorithm Thread_CPU_budget_algorithms + budget_callout Thread_CPU_budget_algorithm_callout + cpu_time_used Thread_CPU_usage_t + Start Thread_Start_information + Post_switch_actions Thread_Action_control + Registers Context_Control + fp_context Context_Control_fp* X + libc_reent struct _reent* + API_Extensions void*[THREAD_API_LAST + 1] + task_variables rtems_task_variable_t* X + Key_Chain Chain_Control + Life Thread_Life_control + extensions void*[RTEMS_ZERO_LENGTH_ARRAY] + + where 'X' means the field is condition and may no exist. + ''' def __init__(self, ctrl): - self.ctrl = ctrl + self.reference = ctrl + self.ctrl = ctrl.dereference() self.object = objects.control(ctrl['Object']) + self._executing = percpu.thread_active(self.reference) + self._heir = percpu.thread_heir(self.reference) def id(self): return self.object.id() @@ -138,6 +223,12 @@ class control: val = '*' return val + def executing(self): + return self._executing + + def heir(self): + return self._heir + def current_state(self): return state(self.ctrl['current_state']).to_string() @@ -147,6 +238,15 @@ class control: def real_priority(self): return self.ctrl['real_priority'] + def resource_count(self): + return self.ctrl['resource_count'] + + def cpu_time_budget(self): + return self.ctrl['cpu_time_budget'] + + def cpu_time_used(self): + return self.ctrl['cpu_time_used'] + def preemptible(self): return self.ctrl['is_preemptible'] @@ -156,11 +256,14 @@ class control: def wait_info(self): return wait_info(self.ctrl['Wait']) + def registers(self): + return registers(self.ctrl['Registers']) + def brief(self): return "'%s' (c:%d, r:%d)" % \ (self.name(), self.current_priority(), self.real_priority()) -class queue: +class queue(): """Manage the Thread_queue_Control.""" priority_headers = 4 @@ -186,6 +289,3 @@ class queue: t.extend(task_chain(chains.control( \ self.que['Queues']['Priority'][ph]))) return t - - - diff --git a/tools/gdb/python/watchdog.py b/tools/gdb/python/watchdog.py index 71a1816..dfa57a0 100644 --- a/tools/gdb/python/watchdog.py +++ b/tools/gdb/python/watchdog.py @@ -1,8 +1,34 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Watchdog Support -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. # -# $Id$ +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# RTEMS Watchdog Support # import gdb @@ -63,4 +89,4 @@ class control: return val def show(self): - print self.to_string() \ No newline at end of file + print self.to_string() diff --git a/tools/gdb/python/wscript b/tools/gdb/python/wscript index 22d44e8..a7f428c 100644 --- a/tools/gdb/python/wscript +++ b/tools/gdb/python/wscript @@ -6,18 +6,22 @@ def configure(conf): conf.load('python') def build(bld): - bld.install_files('${PREFIX}/share/gdb/python/rtems', - ['chains.py', - 'classic.py', - 'classic_printer.py', - 'heaps.py', - 'helper.py', - 'main.py', - 'objects.py', - 'pretty.py', - 'rtems.py', - 'sparc.py', - 'supercore.py', - 'supercore_printer.py', - 'threads.py', - 'watchdog.py']) + source = ['__init__.py', + 'chains.py', + 'classic.py', + 'classic_printer.py', + 'configuration.py', + 'heaps.py', + 'helper.py', + 'main.py', + 'objects.py', + 'percpu.py', + 'pretty.py', + 'rtems.py', + 'sparc.py', + 'supercore.py', + 'supercore_printer.py', + 'threads.py', + 'watchdog.py'] + bld(features = 'py', source = source, install_path = None) + bld.install_files('${PREFIX}/share/gdb/python/rtems', source) From sebh at rtems.org Tue Aug 26 08:12:57 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 26 Aug 2014 03:12:57 -0500 Subject: [rtems commit] rtems: Add more clock tick functions Message-ID: <20140826081257.3B8A2700810@git.rtems.org> Module: rtems Branch: master Commit: 96ec8ee80a18502c2159497e821df3fcd0dc7411 Changeset: http://git.rtems.org/rtems/commit/?id=96ec8ee80a18502c2159497e821df3fcd0dc7411 Author: Sebastian Huber Date: Fri Aug 22 17:09:36 2014 +0200 rtems: Add more clock tick functions Add rtems_clock_tick_later(), rtems_clock_tick_later_usec() and rtems_clock_tick_before(). --- cpukit/rtems/include/rtems/rtems/clock.h | 71 ++++++++++++++++++++ doc/user/clock.t | 104 ++++++++++++++++++++++++++++++ testsuites/sptests/sp37/init.c | 55 ++++++++++++++++ testsuites/sptests/sp37/sp37.doc | 5 ++ testsuites/sptests/sp37/system.h | 4 + 5 files changed, 239 insertions(+), 0 deletions(-) diff --git a/cpukit/rtems/include/rtems/rtems/clock.h b/cpukit/rtems/include/rtems/rtems/clock.h index ff71665..7595f5e 100644 --- a/cpukit/rtems/include/rtems/rtems/clock.h +++ b/cpukit/rtems/include/rtems/rtems/clock.h @@ -34,6 +34,7 @@ #include #include #include +#include #include /* struct timeval */ @@ -160,6 +161,76 @@ RTEMS_INLINE_ROUTINE rtems_interval rtems_clock_get_ticks_since_boot(void) } /** + * @brief Returns the ticks counter value delta ticks in the future. + * + * @param[in] delta The ticks delta value. + * + * @return The tick counter value delta ticks in the future. + */ +RTEMS_INLINE_ROUTINE rtems_interval rtems_clock_tick_later( + rtems_interval delta +) +{ + return _Watchdog_Ticks_since_boot + delta; +} + +/** + * @brief Returns the ticks counter value at least delta microseconds in the + * future. + * + * @param[in] delta_in_usec The delta value in microseconds. + * + * @return The tick counter value at least delta microseconds in the future. + */ +RTEMS_INLINE_ROUTINE rtems_interval rtems_clock_tick_later_usec( + rtems_interval delta_in_usec +) +{ + rtems_interval us_per_tick = rtems_configuration_get_microseconds_per_tick(); + + /* + * Add one additional tick, since we don't know the time to the clock next + * tick. + */ + return _Watchdog_Ticks_since_boot + + (delta_in_usec + us_per_tick - 1) / us_per_tick + 1; +} + +/** + * @brief Returns true if the current ticks counter value indicates a time + * before the time specified by the tick value and false otherwise. + * + * @param[in] tick The tick value. + * + * This can be used to write busy loops with a timeout. + * + * @code + * status busy( void ) + * { + * rtems_interval timeout = rtems_clock_tick_later_usec( 10000 ); + * + * do { + * if ( ok() ) { + * return success; + * } + * } while ( rtems_clock_tick_before( timeout ) ); + * + * return timeout; + * } + * @endcode + * + * @retval true The current ticks counter value indicates a time before the + * time specified by the tick value. + * @retval false Otherwise. + */ +RTEMS_INLINE_ROUTINE bool rtems_clock_tick_before( + rtems_interval tick +) +{ + return (int32_t) ( tick - _Watchdog_Ticks_since_boot ) > 0; +} + +/** * @brief Obtain Ticks Per Seconds * * This routine implements the rtems_clock_get_ticks_per_second diff --git a/doc/user/clock.t b/doc/user/clock.t index 921d1cb..1e821ad 100644 --- a/doc/user/clock.t +++ b/doc/user/clock.t @@ -21,6 +21,9 @@ the clock manager are: @item @code{@value{DIRPREFIX}clock_get_seconds_since_epoch} - Get seconds since epoch @item @code{@value{DIRPREFIX}clock_get_ticks_per_second} - Get ticks per second @item @code{@value{DIRPREFIX}clock_get_ticks_since_boot} - Get current ticks counter value + at item @code{@value{DIRPREFIX}clock_tick_later} - Get tick value in the future + at item @code{@value{DIRPREFIX}clock_tick_later_usec} - Get tick value in the future in microseconds + at item @code{@value{DIRPREFIX}clock_tick_before} - Is tick value is before a point in time @item @code{@value{DIRPREFIX}clock_get_uptime} - Get time since boot @item @code{@value{DIRPREFIX}clock_get_uptime_timeval} - Get time since boot in timeval format @item @code{@value{DIRPREFIX}clock_get_uptime_seconds} - Get seconds since boot @@ -617,6 +620,107 @@ This directive will not cause the running task to be preempted. @c @c @page + at subsection CLOCK_TICK_LATER - Get tick value in the future + + at subheading CALLING SEQUENCE: + + at ifset is-C + at findex rtems_clock_tick_later + at example +rtems_interval rtems_clock_tick_later( + rtems_interval delta +); + at end example + at end ifset + + at subheading DESCRIPTION: + +Returns the ticks counter value delta ticks in the future. + + at subheading NOTES: + +This directive is callable from an ISR. + +This directive will not cause the running task to be preempted. + + at c + at c + at c + at page + at subsection CLOCK_TICK_LATER_USEC - Get tick value in the future in microseconds + + at subheading CALLING SEQUENCE: + + at ifset is-C + at findex rtems_clock_tick_later_usec + at example +rtems_interval rtems_clock_tick_later_usec( + rtems_interval delta_in_usec +); + at end example + at end ifset + + at subheading DESCRIPTION: + +Returns the ticks counter value at least delta microseconds in the future. + + at subheading NOTES: + +This directive is callable from an ISR. + +This directive will not cause the running task to be preempted. + + at c + at c + at c + at page + at subsection CLOCK_TICK_BEFORE - Is tick value is before a point in time + + at subheading CALLING SEQUENCE: + + at ifset is-C + at findex rtems_clock_tick_before + at example +rtems_interval rtems_clock_tick_before( + rtems_interval tick +); + at end example + at end ifset + + at subheading DESCRIPTION: + +Returns true if the current ticks counter value indicates a time before the +time specified by the tick value and false otherwise. + + at subheading NOTES: + +This directive is callable from an ISR. + +This directive will not cause the running task to be preempted. + + at subheading EXAMPLE: + + at example + at group +status busy( void ) +@{ + rtems_interval timeout = rtems_clock_tick_later_usec( 10000 ); + + do @{ + if ( ok() ) @{ + return success; + @} + @} while ( rtems_clock_tick_before( timeout ) ); + + return timeout; +@} + at end group + at end example + + at c + at c + at c + at page @subsection CLOCK_GET_UPTIME - Get the time since boot @cindex clock get uptime diff --git a/testsuites/sptests/sp37/init.c b/testsuites/sptests/sp37/init.c index be0bd32..60ae01b 100644 --- a/testsuites/sptests/sp37/init.c +++ b/testsuites/sptests/sp37/init.c @@ -230,6 +230,59 @@ static void test_interrupt_locks( void ) rtems_interrupt_lock_destroy( &initialized ); } +static void test_clock_tick_functions( void ) +{ + rtems_interrupt_level level; + Watchdog_Interval saved_ticks; + + _Thread_Disable_dispatch(); + rtems_interrupt_disable( level ); + + saved_ticks = _Watchdog_Ticks_since_boot; + + _Watchdog_Ticks_since_boot = 0xdeadbeef; + rtems_test_assert( rtems_clock_get_ticks_since_boot() == 0xdeadbeef ); + + rtems_test_assert( rtems_clock_tick_later( 0 ) == 0xdeadbeef ); + rtems_test_assert( rtems_clock_tick_later( 0x8160311e ) == 0x600df00d ); + + _Watchdog_Ticks_since_boot = 0; + rtems_test_assert( rtems_clock_tick_later_usec( 0 ) == 1 ); + rtems_test_assert( rtems_clock_tick_later_usec( 1 ) == 2 ); + rtems_test_assert( rtems_clock_tick_later_usec( US_PER_TICK ) == 2 ); + rtems_test_assert( rtems_clock_tick_later_usec( US_PER_TICK + 1 ) == 3 ); + + _Watchdog_Ticks_since_boot = 0; + rtems_test_assert( !rtems_clock_tick_before( 0xffffffff ) ); + rtems_test_assert( !rtems_clock_tick_before( 0 ) ); + rtems_test_assert( rtems_clock_tick_before( 1 ) ); + + _Watchdog_Ticks_since_boot = 1; + rtems_test_assert( !rtems_clock_tick_before( 0 ) ); + rtems_test_assert( !rtems_clock_tick_before( 1 ) ); + rtems_test_assert( rtems_clock_tick_before( 2 ) ); + + _Watchdog_Ticks_since_boot = 0x7fffffff; + rtems_test_assert( !rtems_clock_tick_before( 0x7ffffffe ) ); + rtems_test_assert( !rtems_clock_tick_before( 0x7fffffff ) ); + rtems_test_assert( rtems_clock_tick_before( 0x80000000 ) ); + + _Watchdog_Ticks_since_boot = 0x80000000; + rtems_test_assert( !rtems_clock_tick_before( 0x7fffffff ) ); + rtems_test_assert( !rtems_clock_tick_before( 0x80000000 ) ); + rtems_test_assert( rtems_clock_tick_before( 0x80000001 ) ); + + _Watchdog_Ticks_since_boot = 0xffffffff; + rtems_test_assert( !rtems_clock_tick_before( 0xfffffffe ) ); + rtems_test_assert( !rtems_clock_tick_before( 0xffffffff ) ); + rtems_test_assert( rtems_clock_tick_before( 0 ) ); + + _Watchdog_Ticks_since_boot = saved_ticks; + + rtems_interrupt_enable( level ); + _Thread_Enable_dispatch(); +} + void test_interrupt_inline(void) { rtems_interrupt_level level; @@ -413,6 +466,8 @@ rtems_task Init( directive_failed( status, "rtems_clock_tick" ); puts( "clock_tick from task level" ); + test_clock_tick_functions(); + /* * Now do a dispatch directly out of a clock tick that is * called from a task. We need to create a task that will diff --git a/testsuites/sptests/sp37/sp37.doc b/testsuites/sptests/sp37/sp37.doc index 9e814f2..b98faa1 100644 --- a/testsuites/sptests/sp37/sp37.doc +++ b/testsuites/sptests/sp37/sp37.doc @@ -13,6 +13,9 @@ test set name: sp37 directives: rtems_clock_tick + rtems_clock_tick_later() + rtems_clock_tick_later_usec() + rtems_clock_tick_before() rtems_interrupt_disable (inline/body) rtems_interrupt_enable (inline/body) rtems_interrupt_flash (inline/body) @@ -24,6 +27,8 @@ concepts: + Ensure that rtems_clock_tick operates properly when invoked from a task rather than an ISR. ++ Ensure that clock tick counter functions work properly. + + Ensure that the interrupt disable, enable, and flash directives operate as expected. diff --git a/testsuites/sptests/sp37/system.h b/testsuites/sptests/sp37/system.h index 43bef81..6bb47ec 100644 --- a/testsuites/sptests/sp37/system.h +++ b/testsuites/sptests/sp37/system.h @@ -15,6 +15,8 @@ #include +#define US_PER_TICK 10000 + /* functions */ rtems_task Init( @@ -28,6 +30,8 @@ rtems_task Init( #define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION +#define CONFIGURE_MICROSECONDS_PER_TICK US_PER_TICK + #define CONFIGURE_RTEMS_INIT_TASKS_TABLE #define CONFIGURE_INIT_TASK_PRIORITY 2 #define CONFIGURE_INIT_TASK_INITIAL_MODES RTEMS_PREEMPT From joel at rtems.org Tue Aug 26 20:21:45 2014 From: joel at rtems.org (Joel Sherrill) Date: Tue, 26 Aug 2014 15:21:45 -0500 Subject: [rtems-testing commit] sim-scripts: Add new or1ksim OpenRISC simulator script. Message-ID: <20140826202145.CDC0E700810@git.rtems.org> Module: rtems-testing Branch: master Commit: 4813bac6d2c39bd4a73e0dc47aa08979bd603c2a Changeset: http://git.rtems.org/rtems-testing/commit/?id=4813bac6d2c39bd4a73e0dc47aa08979bd603c2a Author: Hesham ALMatary Date: Tue Aug 26 12:59:47 2014 -0500 sim-scripts: Add new or1ksim OpenRISC simulator script. --- sim-scripts/Makefile | 5 +- sim-scripts/or1ksim.in | 155 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 159 insertions(+), 1 deletions(-) diff --git a/sim-scripts/Makefile b/sim-scripts/Makefile index 9d9baaf..e45feae 100644 --- a/sim-scripts/Makefile +++ b/sim-scripts/Makefile @@ -1,6 +1,6 @@ INSTALL_DIR=../bin GDBSIM_SCRIPTS=bf537Stamp ezkit533 gdbarmsim h8sim jmr3904 lm32_evr \ - m32csim m32rsim psim sis simsh v850sim + m32csim m32rsim or1ksim psim sis simsh v850sim SKYEYE_SCRIPTS=ant5206 bf537Stamp-skyeye csb337 csb350 csb360 edb7312 \ ezkit533-skyeye gumstix rtl22xx smdk2410 leon2-skyeye @@ -130,6 +130,9 @@ m32csim m32csim-gdb: gdb-sim-run.in gdb-sim.in m32csim.in m32rsim m32rsim-gdb: gdb-sim-run.in gdb-sim.in m32rsim.in ./mkrun yes M32R m32r m32rsim +or1ksim or1ksim-gdb: or1ksim.in + ./mkrun yes OR1K or1k or1ksim + psim psim-gdb: gdb-sim-run.in gdb-sim.in psim.in ./mkrun yes PowerPC powerpc psim diff --git a/sim-scripts/or1ksim.in b/sim-scripts/or1ksim.in new file mode 100644 index 0000000..b71e0f6 --- /dev/null +++ b/sim-scripts/or1ksim.in @@ -0,0 +1,155 @@ +# +# or1k/or1ksim Support +# +bspSupportsGDBServerMode="yes" +runBSP=or32-elf-sim +bspTreeFile=sim.cfg + +runARGS() +{ + echo "-f ${bspTreeFile} ${1}" +} + +checkBSPFaults() +{ + return 0 +} + +bspLimit() +{ + testname=$1 + case ${testname} in + *stackchk*)limit=5 ;; + *fatal*) limit=1 ;; + *minimum*) limit=1 ;; + *psxtime*) limit=180 ;; + *) limit=60 ;; + esac + echo ${limit} +} + +bspGeneratesGDBCommands="yes" + +gdbServerARGS() +{ + echo "-c ${bspTreeFile}" +} + +bspGenerateGDBCommands() +{ +cat < Module: rtems Branch: master Commit: 2cd68a8bf626e94d906a97c337935e93094cd8f5 Changeset: http://git.rtems.org/rtems/commit/?id=2cd68a8bf626e94d906a97c337935e93094cd8f5 Author: Hesham ALMatary Date: Tue Aug 26 14:42:47 2014 -0500 Add or1ksim (sim.cfg) configuration file and edit README. OpenRISC/or1ksim BSP: The new sim.cfg file configures or1ksim emulator with HW capabilities that the current RTEMS/or1ksim BSP supports. README: HOWTO run the or1ksim simulator. --- c/src/lib/libbsp/or1k/or1ksim/README | 20 ++++++- c/src/lib/libbsp/or1k/or1ksim/sim.cfg | 104 +++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/or1k/or1ksim/README b/c/src/lib/libbsp/or1k/or1ksim/README index 43b4703..9ce5709 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/README +++ b/c/src/lib/libbsp/or1k/or1ksim/README @@ -14,4 +14,22 @@ Configuration file "sim.cfg" should be provided for complex board configurations at the current directory (which you run or1ksim from) or at ~/.or1k/ -sim -f sim.cfg hello.exe +The current sim.cfg file that configures or1ksim emulator to RTEMS/or1ksim BSP +is at the same directory as this README. You can also use or1ksim script from +rtems-tools/sim-scripts. + +From command line type: + +sim -f sim.cfg $PATH_TO_RTEMS_EXE + +or (if you use a stable or1ksim release) + +or32-elf-sim -f sim.cfg $PATH_TO_RTEMS_EXE + +from sim-scripts: + +or1ksim $PATH_TO_RTEMS_EXE + +and then attach GDB to or1ksim from another terminal by running + +or1ksim-gdb $PATH_TO_RTEMS_EXE diff --git a/c/src/lib/libbsp/or1k/or1ksim/sim.cfg b/c/src/lib/libbsp/or1k/or1ksim/sim.cfg new file mode 100644 index 0000000..061f61a --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/sim.cfg @@ -0,0 +1,104 @@ +section memory + name = "RAM" + random_seed = 12345 + type = random + ce = 0 + mc = 0 + baseaddr = 0x00000000 + size = 0x08000000 + delayr = 1 + delayw = 2 +end + +section immu + enabled = 0 + nsets = 64 + nways = 1 + pagesize = 8192 + hitdelay = 0 + missdelay = 0 +end + +section dmmu + enabled = 0 + nsets = 64 + nways = 1 + pagesize = 8192 + hitdelay = 0 + missdelay = 0 +end +section mc + enabled = 0 + baseaddr = 0x90000000 + POC = 0x0000000a /* 32 bit SSRAM */ + index = 0 +end + +section ic + enabled = 0 + nsets = 256 + nways = 1 + blocksize = 16 + hitdelay = 20 + missdelay = 20 +end + +section dc + enabled = 0 + nsets = 256 + nways = 1 + blocksize = 16 + load_hitdelay = 0 + load_missdelay = 0 + store_hitdelay = 0 + store_missdelay = 0 +end + +section pic + enabled = 1 + edge_trigger = 1 +end + +section sim + verbose = 1 + debug = 0 + profile = 0 + history = 0 + clkcycle = 10ns /* 100MHz clock */ +end + +section VAPI + enabled = 1 + server_port = 50000 + log_enabled = 1 + vapi_log_file = "vapi.log" +end + +section cpu + ver = 0x12 + cfg = 0x00 + rev = 0x0001 + superscalar = 0 + hazards = 0 + dependstats = 0 + sbuf_len = 100 +end + +section debug + enabled = 1 + rsp_enabled = 1 + rsp_port = 50001 +end + +section uart + enabled = 1 + baseaddr = 0x90000000 + #channel = "xterm" + channel = "file:uart0.rx,uart0.tx" + irq = 2 + 16550 = 1 +end + +section pm + enabled = 1 +end From chrisj at rtems.org Wed Aug 27 09:56:37 2014 From: chrisj at rtems.org (Chris Johns) Date: Wed, 27 Aug 2014 04:56:37 -0500 Subject: [rtems commit] arm/lm3s3749: Add tests that do not fit. Message-ID: <20140827095637.B08FD70080E@git.rtems.org> Module: rtems Branch: master Commit: 614a0889b664a9309c3a966e5f0f494d4b94b62f Changeset: http://git.rtems.org/rtems/commit/?id=614a0889b664a9309c3a966e5f0f494d4b94b62f Author: Chris Johns Date: Wed Aug 27 20:04:26 2014 +1000 arm/lm3s3749: Add tests that do not fit. You need --enable-c++ for the c++ tests. --- .../lm3s69xx/make/custom/lm3s3749-testsuite.tcfg | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749-testsuite.tcfg b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749-testsuite.tcfg index 6925cd3..5d20dda 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749-testsuite.tcfg @@ -5,6 +5,7 @@ # capture +iostream ftp01 fileio flashdisk01 @@ -30,5 +31,7 @@ mrfs_fsrdwr mrfs_fssymlink mrfs_fstime pppd +rtems++ +sptls02 syscall01 utf8proc01 From sebh at rtems.org Wed Aug 27 11:58:05 2014 From: sebh at rtems.org (Sebastian Huber) Date: Wed, 27 Aug 2014 06:58:05 -0500 Subject: [rtems commit] rtems: SMP fix for timer server Message-ID: <20140827115806.0DF1D70080E@git.rtems.org> Module: rtems Branch: master Commit: 34db8ec9322f8c9ae6d416c94f6d66fd236184cb Changeset: http://git.rtems.org/rtems/commit/?id=34db8ec9322f8c9ae6d416c94f6d66fd236184cb Author: Sebastian Huber Date: Wed Aug 27 14:06:10 2014 +0200 rtems: SMP fix for timer server --- cpukit/rtems/src/timerserver.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/cpukit/rtems/src/timerserver.c b/cpukit/rtems/src/timerserver.c index 7523ebc..ad32172 100644 --- a/cpukit/rtems/src/timerserver.c +++ b/cpukit/rtems/src/timerserver.c @@ -513,7 +513,9 @@ rtems_status_code rtems_timer_initiate_server( _Objects_Build_name('T','I','M','E'), /* "TIME" */ _priority, /* create with priority 1 since 0 is illegal */ stack_size, /* let user specify stack size */ - RTEMS_NO_PREEMPT, /* no preempt is like an interrupt */ + rtems_configuration_is_smp_enabled() ? + RTEMS_DEFAULT_MODES : /* no preempt is not supported for SMP */ + RTEMS_NO_PREEMPT, /* no preempt is like an interrupt */ /* user may want floating point but we need */ /* system task specified for 0 priority */ attribute_set | RTEMS_SYSTEM_TASK, From sebh at rtems.org Wed Aug 27 13:10:34 2014 From: sebh at rtems.org (Sebastian Huber) Date: Wed, 27 Aug 2014 08:10:34 -0500 Subject: [rtems-libbsd commit] Update due to rbtree API changes Message-ID: <20140827131034.2473970080E@git.rtems.org> Module: rtems-libbsd Branch: master Commit: 8e2e9b3e655f130aa7dd8151a1ce0cabe59cbdf3 Changeset: http://git.rtems.org/rtems-libbsd/commit/?id=8e2e9b3e655f130aa7dd8151a1ce0cabe59cbdf3 Author: Sebastian Huber Date: Wed Aug 27 15:00:09 2014 +0200 Update due to rbtree API changes --- rtemsbsd/rtems/rtems-bsd-chunk.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/rtemsbsd/rtems/rtems-bsd-chunk.c b/rtemsbsd/rtems/rtems-bsd-chunk.c index 5c9c6eb..c10c220 100644 --- a/rtemsbsd/rtems/rtems-bsd-chunk.c +++ b/rtemsbsd/rtems/rtems-bsd-chunk.c @@ -47,7 +47,7 @@ #define chunk_of_node(n) ((rtems_bsd_chunk_info *) n) -static int +static rtems_rbtree_compare_result chunk_compare(const rtems_rbtree_node *a, const rtems_rbtree_node *b) { const rtems_bsd_chunk_info *left = chunk_of_node(a); @@ -71,7 +71,7 @@ rtems_bsd_chunk_init(rtems_bsd_chunk_control *self, uintptr_t info_size, self->info_size = info_size; self->info_ctor = info_ctor; self->info_dtor = info_dtor; - rtems_rbtree_initialize_empty(&self->chunks, chunk_compare, true); + rtems_rbtree_initialize_empty(&self->chunks); } void * @@ -90,7 +90,7 @@ rtems_bsd_chunk_alloc(rtems_bsd_chunk_control *self, uintptr_t chunk_size) (*self->info_ctor)(self, info); _RTEMS_Lock_allocator(); - rtems_rbtree_insert(&self->chunks, &info->node); + rtems_rbtree_insert(&self->chunks, &info->node, chunk_compare, true); _RTEMS_Unlock_allocator(); } @@ -122,7 +122,7 @@ rtems_bsd_chunk_get_info(rtems_bsd_chunk_control *self, }; return chunk_of_node(rtems_rbtree_find(&self->chunks, - &find_me.node)); + &find_me.node, chunk_compare, true)); } void * From joel at rtems.org Wed Aug 27 15:55:46 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 27 Aug 2014 10:55:46 -0500 Subject: [rtems commit] lpc40xx_ea_rom_int-testsuite.tcfg: New file Message-ID: <20140827155546.4210270080E@git.rtems.org> Module: rtems Branch: master Commit: 7d3a3456303ab21a9453ac4ee2f04ba6eac60bab Changeset: http://git.rtems.org/rtems/commit/?id=7d3a3456303ab21a9453ac4ee2f04ba6eac60bab Author: Joel Sherrill Date: Tue Aug 26 13:53:27 2014 -0500 lpc40xx_ea_rom_int-testsuite.tcfg: New file --- .../make/custom/lpc40xx_ea_rom_int-testsuite.tcfg | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int-testsuite.tcfg new file mode 100644 index 0000000..b8b9bbe --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int-testsuite.tcfg @@ -0,0 +1,7 @@ +# +# lpc40xx_ea_rom_int RTEMS Test Database. +# +# Format is one line per test that is _NOT_ built. +# + +fsdosfsname01 From joel at rtems.org Wed Aug 27 15:55:46 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 27 Aug 2014 10:55:46 -0500 Subject: [rtems commit] nds/Makefile.am: Rework to avoid creating ltos of .rel files Message-ID: <20140827155546.2C997700810@git.rtems.org> Module: rtems Branch: master Commit: 6e60140daf1c7e4a39dcd17b0240eb812ead2f77 Changeset: http://git.rtems.org/rtems/commit/?id=6e60140daf1c7e4a39dcd17b0240eb812ead2f77 Author: Joel Sherrill Date: Wed Aug 27 11:00:07 2014 -0500 nds/Makefile.am: Rework to avoid creating ltos of .rel files This was necessary to enable all tests to link. --- c/src/lib/libbsp/arm/nds/Makefile.am | 106 +++++++++++----------------------- 1 files changed, 35 insertions(+), 71 deletions(-) diff --git a/c/src/lib/libbsp/arm/nds/Makefile.am b/c/src/lib/libbsp/arm/nds/Makefile.am index 76bab01..c8d8811 100644 --- a/c/src/lib/libbsp/arm/nds/Makefile.am +++ b/c/src/lib/libbsp/arm/nds/Makefile.am @@ -30,72 +30,43 @@ libbsp_a_SOURCES = include_ndsdir = $(includedir)/nds include_nds_HEADERS = touchscreen/touchscreen.h sound/sound.h -noinst_PROGRAMS += startup.rel -startup_rel_SOURCES = ../../shared/bsplibc.c ../../shared/bsppost.c \ - startup/bspstart.c ../../shared/bspclean.c startup/bspreset.c \ - ../../shared/bspgetworkarea.c ../../shared/bsppredriverhook.c \ - ../../shared/bsppretaskinghook.c ../../shared/bootcard.c +libbsp_a_CPPFLAGS = -DARM9 +libbsp_a_CPPFLAGS += -I$(srcdir)/../../shared/include +libbsp_a_CPPFLAGS += -I$(srcdir)/include +libbsp_a_CPPFLAGS += -I$(srcdir)/libnds/include +libbsp_a_CPPFLAGS += -I$(srcdir)/libfat/source/disc_io +libbsp_a_SOURCES += ../../shared/bsplibc.c +libbsp_a_SOURCES += ../../shared/bsppost.c +libbsp_a_SOURCES += startup/bspstart.c +libbsp_a_SOURCES += ../../shared/bspclean.c +libbsp_a_SOURCES += startup/bspreset.c +libbsp_a_SOURCES += ../../shared/bspgetworkarea.c +libbsp_a_SOURCES += ../../shared/bsppredriverhook.c +libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c +libbsp_a_SOURCES += ../../shared/bootcard.c libbsp_a_SOURCES += ../../shared/cpucounterread.c libbsp_a_SOURCES += ../../shared/cpucounterdiff.c -startup_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += gnatsupp.rel -gnatsupp_rel_SOURCES = ../../shared/gnatinstallhandler.c -gnatsupp_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -gnatsupp_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += clock.rel -clock_rel_SOURCES = clock/clock.c -clock_rel_SOURCES += ../../shared/clockdrv_shell.h -clock_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += rtc.rel -rtc_rel_SOURCES = rtc/rtc.c ../../shared/tod.c -rtc_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -rtc_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += console.rel -console_rel_SOURCES = console/console.c -console_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -I$(srcdir)/include -console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += fb.rel -fb_rel_SOURCES = fb/fb.c -fb_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -fb_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += touchscreen.rel -touchscreen_rel_SOURCES = touchscreen/touchscreen.c touchscreen/parser.c \ - touchscreen/reco.c -touchscreen_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -touchscreen_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += timer.rel -timer_rel_SOURCES = timer/timer.c -timer_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += sound.rel -sound_rel_SOURCES = sound/sound.c -sound_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -sound_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += block.rel -block_rel_SOURCES = block/block.c -block_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -DNDS -I$(srcdir)/libfat/source/disc_io -block_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += irq.rel -irq_rel_SOURCES = irq/irq.c -irq_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) +libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c +libbsp_a_SOURCES += clock/clock.c +libbsp_a_SOURCES += ../../shared/clockdrv_shell.h +libbsp_a_SOURCES += rtc/rtc.c +libbsp_a_SOURCES += ../../shared/tod.c +libbsp_a_SOURCES += console/console.c +libbsp_a_SOURCES += fb/fb.c +libbsp_a_SOURCES += touchscreen/touchscreen.c +libbsp_a_SOURCES += touchscreen/parser.c +libbsp_a_SOURCES += touchscreen/reco.c +libbsp_a_SOURCES += timer/timer.c +libbsp_a_SOURCES += sound/sound.c +libbsp_a_SOURCES += block/block.c +libbsp_a_SOURCES += irq/irq.c +# Cache +libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c +libbsp_a_SOURCES += ../../shared/include/cache_.h if HAS_NETWORKING noinst_PROGRAMS += wifi.rel -wifi_rel_SOURCES = wifi/wifi.c \ - wifi/compat.c +wifi_rel_SOURCES = wifi/wifi.c wifi/compat.c wifi_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/dswifi/include -I$(srcdir)/libnds/include -I$(srcdir)/dswifi/include -D_KERNEL -D__BSD_VISIBLE wifi_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif @@ -144,8 +115,8 @@ libnds9_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) if HAS_NETWORKING # dswifi, ARM9 side noinst_PROGRAMS += dswifi9.rel -dswifi9_rel_SOURCES = dswifi/arm9/source/wifi_arm9.c \ - dswifi/common/source/spinlock.S +dswifi9_rel_SOURCES = dswifi/arm9/source/wifi_arm9.c +dswifi9_rel_SOURCES += dswifi/common/source/spinlock.S dswifi9_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/dswifi/include -I$(srcdir)/libnds/include -I$(srcdir)/dswifi/common/source -I$(srcdir)/wifi -D_KERNEL dswifi9_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif @@ -255,14 +226,7 @@ coproc.bin: coproc/coproc.S coproc/coproc.c libnds7.rel endif project_lib_DATA += coproc.bin -# Cache -libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c -libbsp_a_SOURCES += ../../shared/include/cache_.h -libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include - -libbsp_a_LIBADD = clock.rel console.rel gnatsupp.rel startup.rel irq.rel \ - timer.rel libnds9.rel rtc.rel fb.rel touchscreen.rel sound.rel \ - block.rel libdldi.rel +libbsp_a_LIBADD = libnds9.rel libdldi.rel if HAS_NETWORKING libbsp_a_LIBADD += wifi.rel dswifi9.rel From joel at rtems.org Wed Aug 27 17:41:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 27 Aug 2014 12:41:54 -0500 Subject: [rtems commit] virtex5/.../bsp.h: Add BSP_Convert_decrementer() macro required by MPC6xx timer driver Message-ID: <20140827174155.0759370080E@git.rtems.org> Module: rtems Branch: master Commit: bfa2b8c39ee19006e75d5ea3890fdda3eec4f9b7 Changeset: http://git.rtems.org/rtems/commit/?id=bfa2b8c39ee19006e75d5ea3890fdda3eec4f9b7 Author: Joel Sherrill Date: Wed Aug 27 12:50:36 2014 -0500 virtex5/.../bsp.h: Add BSP_Convert_decrementer() macro required by MPC6xx timer driver --- c/src/lib/libbsp/powerpc/virtex5/include/bsp.h | 27 +++++++++++++++++++++-- 1 files changed, 24 insertions(+), 3 deletions(-) diff --git a/c/src/lib/libbsp/powerpc/virtex5/include/bsp.h b/c/src/lib/libbsp/powerpc/virtex5/include/bsp.h index 2e21129..8558faa 100644 --- a/c/src/lib/libbsp/powerpc/virtex5/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/virtex5/include/bsp.h @@ -1,7 +1,9 @@ -/* bsp.h +/* @file * * This include file contains all GEN405 board IO definitions. - * + */ + +/* * derived from helas403/include/bsp.h: * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp * Author: Thomas Doerfler @@ -67,7 +69,26 @@ extern "C" { /* miscellaneous stuff assumed to exist */ extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ -extern rtems_configuration_table BSP_Configuration; /* owned by BSP */ +/* + * Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * Processor Clock Frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +/* + * Macro used by shared MPC6xx timer driver + */ +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + + #endif /* ASM */ void BSP_ask_for_reset(void); From chrisj at rtems.org Thu Aug 28 00:54:02 2014 From: chrisj at rtems.org (Chris Johns) Date: Wed, 27 Aug 2014 19:54:02 -0500 Subject: [rtems commit] preinstall: Regenerated files differ from the repo. Message-ID: <20140828005403.4B659700810@git.rtems.org> Module: rtems Branch: master Commit: 5826a1b284450778be4b73276560a48ccd0cd9a7 Changeset: http://git.rtems.org/rtems/commit/?id=5826a1b284450778be4b73276560a48ccd0cd9a7 Author: Chris Johns Date: Thu Aug 28 10:08:00 2014 +1000 preinstall: Regenerated files differ from the repo. --- .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 12 ++++++------ c/src/lib/libbsp/or1k/or1ksim/preinstall.am | 13 +++++++------ c/src/lib/libbsp/or1k/preinstall.am | 1 + c/src/lib/libcpu/or1k/preinstall.am | 7 ++++--- 4 files changed, 18 insertions(+), 15 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 768c01d..5b6b9fd 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) +CLEANFILES = $(TMPINSTALL_FILES) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am index cbdf3df..2569864 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am +++ b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) +CLEANFILES = $(TMPINSTALL_FILES) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @@ -117,3 +117,4 @@ TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds $(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base + diff --git a/c/src/lib/libbsp/or1k/preinstall.am b/c/src/lib/libbsp/or1k/preinstall.am index 1143c2e..dba6cc4 100644 --- a/c/src/lib/libbsp/or1k/preinstall.am +++ b/c/src/lib/libbsp/or1k/preinstall.am @@ -4,3 +4,4 @@ if AMPOLISH3 $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif + diff --git a/c/src/lib/libcpu/or1k/preinstall.am b/c/src/lib/libcpu/or1k/preinstall.am index 9670596..ee9d0da 100644 --- a/c/src/lib/libcpu/or1k/preinstall.am +++ b/c/src/lib/libcpu/or1k/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) @@ -21,3 +21,4 @@ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) $(PROJECT_INCLUDE)/libcpu/cache.h: ../shared/include/cache.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache.h + From chrisj at rtems.org Thu Aug 28 04:25:49 2014 From: chrisj at rtems.org (Chris Johns) Date: Wed, 27 Aug 2014 23:25:49 -0500 Subject: [rtems commit] arm: Add tests which fail to build with C++ enabled. Message-ID: <20140828042549.D503C70080E@git.rtems.org> Module: rtems Branch: master Commit: d04cb1242d0b359acd9c7f976dd8b6472e5da101 Changeset: http://git.rtems.org/rtems/commit/?id=d04cb1242d0b359acd9c7f976dd8b6472e5da101 Author: Chris Johns Date: Thu Aug 28 14:34:10 2014 +1000 arm: Add tests which fail to build with C++ enabled. --- .../lm3s69xx/make/custom/lm3s6965-testsuite.tcfg | 2 ++ .../lm3s69xx/make/custom/lm4f120-testsuite.tcfg | 4 ++++ .../make/custom/lpc1768_mbed-testsuite.tcfg | 2 ++ .../custom/lpc1768_mbed_ahb_ram-testsuite.tcfg | 2 ++ .../arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg | 4 ++++ .../make/custom/lpc23xx_tli800-testsuite.tcfg | 4 ++++ .../make/custom/lpc32xx_mzx_stage_1-testsuite.tcfg | 2 ++ .../arm/rtl22xx/make/custom/rtl22xx-testsuite.tcfg | 2 ++ .../stm32f4/make/custom/stm32f105rc-testsuite.tcfg | 2 ++ 9 files changed, 24 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965-testsuite.tcfg b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965-testsuite.tcfg index 77395c7..7e1706e 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965-testsuite.tcfg @@ -5,6 +5,7 @@ # fileio +iostream flashdisk01 fsdosfsname01 ftp01 @@ -19,3 +20,4 @@ mghttpd01 monitor02 utf8proc01 pppd +rtems++ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm4f120-testsuite.tcfg b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm4f120-testsuite.tcfg index d7ec311..b4b9365 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm4f120-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm4f120-testsuite.tcfg @@ -5,6 +5,8 @@ # fileio +cdtest +iostream flashdisk01 fsdosfsname01 ftp01 @@ -22,4 +24,6 @@ sp16 sp25 sp48 spstkalloc02 +sptls02 +rtems++ utf8proc01 diff --git a/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed-testsuite.tcfg index 910bf59..2a7d71b 100644 --- a/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed-testsuite.tcfg @@ -17,3 +17,5 @@ jffs2_fssymlink jffs2_fstime pppd mghttpd01 +iostream +rtems++ diff --git a/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed_ahb_ram-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed_ahb_ram-testsuite.tcfg index 659276b..748b271 100644 --- a/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed_ahb_ram-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed_ahb_ram-testsuite.tcfg @@ -17,3 +17,5 @@ mghttpd01 pppd spstkalloc02 utf8proc01 +iostream +rtems++ diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg index 47bd346..4d7f178 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg @@ -5,11 +5,13 @@ # capture +cdtest fileio flashdisk01 fsdosfsname01 fsrfsbitmap01 ftp01 +iostream jffs2_fserror jffs2_fslink jffs2_fspatheval @@ -30,6 +32,8 @@ mrfs_fsrdwr mrfs_fssymlink mrfs_fstime pppd +rtems++ spstkalloc02 +sptls02 syscall01 utf8proc01 diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc23xx_tli800-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc23xx_tli800-testsuite.tcfg index 4b47039..a678ca2 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc23xx_tli800-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc23xx_tli800-testsuite.tcfg @@ -5,12 +5,14 @@ # capture +cdtest fileio flashdisk01 fsdosfsformat01 fsdosfsname01 fsrfsbitmap01 ftp01 +iostream jffs2_fserror jffs2_fslink jffs2_fspatheval @@ -33,6 +35,8 @@ mrfs_fstime mdosfs_fsrdwr paranoia pppd +rtems++ +sptls02 spstkalloc02 syscall01 utf8proc01 diff --git a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_stage_1-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_stage_1-testsuite.tcfg index 9228d0e..68cfc64 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_stage_1-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_stage_1-testsuite.tcfg @@ -7,6 +7,7 @@ fileio ftp01 fsdosfsname01 +iostream jffs2_fserror jffs2_fslink jffs2_fspatheval @@ -17,4 +18,5 @@ jffs2_fstime mghttpd01 monitor02 pppd +rtems++ utf8proc01 diff --git a/c/src/lib/libbsp/arm/rtl22xx/make/custom/rtl22xx-testsuite.tcfg b/c/src/lib/libbsp/arm/rtl22xx/make/custom/rtl22xx-testsuite.tcfg index 3992b31..d23a630 100644 --- a/c/src/lib/libbsp/arm/rtl22xx/make/custom/rtl22xx-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/rtl22xx/make/custom/rtl22xx-testsuite.tcfg @@ -5,4 +5,6 @@ # fsdosfsname01 +iostream +rtems++ utf8proc01 diff --git a/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f105rc-testsuite.tcfg b/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f105rc-testsuite.tcfg index 89fdf29..be079fb 100644 --- a/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f105rc-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f105rc-testsuite.tcfg @@ -8,6 +8,7 @@ fileio flashdisk01 fsdosfsname01 ftp01 +iostream jffs2_fserror jffs2_fslink jffs2_fspatheval @@ -18,4 +19,5 @@ jffs2_fstime mghttpd01 monitor02 pppd +rtems++ utf8proc01 From joel at rtems.org Thu Aug 28 13:36:52 2014 From: joel at rtems.org (Joel Sherrill) Date: Thu, 28 Aug 2014 08:36:52 -0500 Subject: [rtems commit] Regenerate all preinstall.am files. Message-ID: <20140828133652.753BF700810@git.rtems.org> Module: rtems Branch: master Commit: b597c0d60ce789c3f3708108c7a5abd75eecfbdf Changeset: http://git.rtems.org/rtems/commit/?id=b597c0d60ce789c3f3708108c7a5abd75eecfbdf Author: Joel Sherrill Date: Thu Aug 28 08:44:52 2014 -0500 Regenerate all preinstall.am files. Apparently, at some point automake output changed and these were not updated. --- .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/csb336/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/csb337/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/edb7312/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/gdbarmsim/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/gp32/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/gumstix/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/lm3s69xx/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/lpc24xx/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/lpc32xx/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/nds/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/raspberrypi/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/stm32f4/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/tms570/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am | 14 +++++++------- c/src/lib/libbsp/bfin/TLL6527M/preinstall.am | 6 +++--- c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am | 14 +++++++------- c/src/lib/libbsp/bfin/eZKit533/preinstall.am | 12 ++++++------ c/src/lib/libbsp/lm32/lm32_evr/preinstall.am | 6 +++--- c/src/lib/libbsp/lm32/milkymist/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m32r/m32rsim/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/av5282/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/csb360/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/gen68302/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/gen68340/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/gen68360/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/genmcf548x/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/idp/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mcf52235/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mcf5235/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/mcf5329/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mrm332/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mvme136/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mvme147/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mvme147s/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mvme162/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/mvme167/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/ods68302/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/uC5282/preinstall.am | 14 +++++++------- c/src/lib/libbsp/mips/csb350/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/genmongoosev/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/malta/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/rbtx4938/preinstall.am | 12 ++++++------ c/src/lib/libbsp/moxie/moxiesim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/nios2/nios2_iss/preinstall.am | 6 +++--- c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am | 6 +++--- c/src/lib/libbsp/or1k/or1ksim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/beatnik/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/ep1a/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/gen5200/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/gen83xx/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/haleakala/preinstall.am | 14 +++++++------- c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am | 12 ++++++------ .../libbsp/powerpc/motorola_powerpc/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/mpc8260ads/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/psim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/qemuppc/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/qoriq/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/score603e/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/ss555/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/t32mppc/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/virtex/preinstall.am | 14 +++++++------- c/src/lib/libbsp/powerpc/virtex4/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/virtex5/preinstall.am | 14 +++++++------- c/src/lib/libbsp/sh/gensh1/preinstall.am | 10 +++++----- c/src/lib/libbsp/sh/gensh2/preinstall.am | 10 +++++----- c/src/lib/libbsp/sh/gensh4/preinstall.am | 6 +++--- c/src/lib/libbsp/sh/shsim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/sparc/erc32/preinstall.am | 12 ++++++------ c/src/lib/libbsp/sparc/leon2/preinstall.am | 12 ++++++------ c/src/lib/libbsp/sparc/leon3/preinstall.am | 6 +++--- c/src/lib/libbsp/sparc64/usiii/preinstall.am | 6 +++--- c/src/lib/libcpu/arm/preinstall.am | 6 +++--- c/src/lib/libcpu/bfin/preinstall.am | 6 +++--- c/src/lib/libcpu/lm32/preinstall.am | 6 +++--- c/src/lib/libcpu/mips/preinstall.am | 6 +++--- c/src/lib/libcpu/powerpc/preinstall.am | 6 +++--- c/src/lib/libcpu/sparc64/preinstall.am | 6 +++--- c/src/librtems++/preinstall.am | 12 ++++++------ cpukit/ftpd/preinstall.am | 6 +++--- cpukit/mghttpd/preinstall.am | 12 ++++++------ cpukit/posix/preinstall.am | 6 +++--- cpukit/preinstall.am | 6 +++--- cpukit/score/cpu/bfin/preinstall.am | 6 +++--- cpukit/score/cpu/h8300/preinstall.am | 6 +++--- cpukit/score/cpu/i386/preinstall.am | 6 +++--- cpukit/score/cpu/m32r/preinstall.am | 6 +++--- cpukit/score/cpu/mips/preinstall.am | 6 +++--- cpukit/score/cpu/powerpc/preinstall.am | 6 +++--- cpukit/score/cpu/sparc64/preinstall.am | 6 +++--- cpukit/score/preinstall.am | 6 +++--- cpukit/telnetd/preinstall.am | 12 ++++++------ cpukit/zlib/preinstall.am | 6 +++--- 95 files changed, 464 insertions(+), 464 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 5b6b9fd..2627812 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/csb336/preinstall.am b/c/src/lib/libbsp/arm/csb336/preinstall.am index 389ac9a..9fdcef7 100644 --- a/c/src/lib/libbsp/arm/csb336/preinstall.am +++ b/c/src/lib/libbsp/arm/csb336/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/csb337/preinstall.am b/c/src/lib/libbsp/arm/csb337/preinstall.am index f067f39..33eaa98 100644 --- a/c/src/lib/libbsp/arm/csb337/preinstall.am +++ b/c/src/lib/libbsp/arm/csb337/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/edb7312/preinstall.am b/c/src/lib/libbsp/arm/edb7312/preinstall.am index 59bd50a..7b0639f 100644 --- a/c/src/lib/libbsp/arm/edb7312/preinstall.am +++ b/c/src/lib/libbsp/arm/edb7312/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am b/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am index 049f288..53ad826 100644 --- a/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am +++ b/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/gp32/preinstall.am b/c/src/lib/libbsp/arm/gp32/preinstall.am index e2bd7e9..1d72ddf 100644 --- a/c/src/lib/libbsp/arm/gp32/preinstall.am +++ b/c/src/lib/libbsp/arm/gp32/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/gumstix/preinstall.am b/c/src/lib/libbsp/arm/gumstix/preinstall.am index dea7ee9..2188049 100644 --- a/c/src/lib/libbsp/arm/gumstix/preinstall.am +++ b/c/src/lib/libbsp/arm/gumstix/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am b/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am index db476c2..eb4b176 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am index 3bf67a6..0e65c58 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am index 79dfb0e..6ba42de 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/nds/preinstall.am b/c/src/lib/libbsp/arm/nds/preinstall.am index e0555de..5ae1d49 100644 --- a/c/src/lib/libbsp/arm/nds/preinstall.am +++ b/c/src/lib/libbsp/arm/nds/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/raspberrypi/preinstall.am b/c/src/lib/libbsp/arm/raspberrypi/preinstall.am index d754fa7..398581a 100644 --- a/c/src/lib/libbsp/arm/raspberrypi/preinstall.am +++ b/c/src/lib/libbsp/arm/raspberrypi/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am b/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am index 0f38c23..5f72122 100644 --- a/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am +++ b/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/stm32f4/preinstall.am b/c/src/lib/libbsp/arm/stm32f4/preinstall.am index a75e3d0..a081a88 100644 --- a/c/src/lib/libbsp/arm/stm32f4/preinstall.am +++ b/c/src/lib/libbsp/arm/stm32f4/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am b/c/src/lib/libbsp/arm/tms570/preinstall.am index d7ac628..f88c7fd 100644 --- a/c/src/lib/libbsp/arm/tms570/preinstall.am +++ b/c/src/lib/libbsp/arm/tms570/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am index f846d75..c079c07 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am b/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am index 557599a..525f222 100644 --- a/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am +++ b/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am b/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am index bdd3a3e..0142ef7 100644 --- a/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am +++ b/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/bfin/eZKit533/preinstall.am b/c/src/lib/libbsp/bfin/eZKit533/preinstall.am index 557599a..e25c8d7 100644 --- a/c/src/lib/libbsp/bfin/eZKit533/preinstall.am +++ b/c/src/lib/libbsp/bfin/eZKit533/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am b/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am index a95af39..981d677 100644 --- a/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am +++ b/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/lm32/milkymist/preinstall.am b/c/src/lib/libbsp/lm32/milkymist/preinstall.am index c3217ef..0ee384d 100644 --- a/c/src/lib/libbsp/lm32/milkymist/preinstall.am +++ b/c/src/lib/libbsp/lm32/milkymist/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m32r/m32rsim/preinstall.am b/c/src/lib/libbsp/m32r/m32rsim/preinstall.am index 73323b5..67ceb2b 100644 --- a/c/src/lib/libbsp/m32r/m32rsim/preinstall.am +++ b/c/src/lib/libbsp/m32r/m32rsim/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/av5282/preinstall.am b/c/src/lib/libbsp/m68k/av5282/preinstall.am index 73323b5..e3970ec 100644 --- a/c/src/lib/libbsp/m68k/av5282/preinstall.am +++ b/c/src/lib/libbsp/m68k/av5282/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/csb360/preinstall.am b/c/src/lib/libbsp/m68k/csb360/preinstall.am index ed79155..1c64e4f 100644 --- a/c/src/lib/libbsp/m68k/csb360/preinstall.am +++ b/c/src/lib/libbsp/m68k/csb360/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/gen68302/preinstall.am b/c/src/lib/libbsp/m68k/gen68302/preinstall.am index 540e452..a63094d 100644 --- a/c/src/lib/libbsp/m68k/gen68302/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68302/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/gen68340/preinstall.am b/c/src/lib/libbsp/m68k/gen68340/preinstall.am index 0c891ea..298545c 100644 --- a/c/src/lib/libbsp/m68k/gen68340/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68340/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/gen68360/preinstall.am b/c/src/lib/libbsp/m68k/gen68360/preinstall.am index 24d5ce9..0a6c6d6 100644 --- a/c/src/lib/libbsp/m68k/gen68360/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68360/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am b/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am index 31ce6bc..331f0b5 100644 --- a/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am +++ b/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/idp/preinstall.am b/c/src/lib/libbsp/m68k/idp/preinstall.am index 1bcb5b6..73bd6bd 100644 --- a/c/src/lib/libbsp/m68k/idp/preinstall.am +++ b/c/src/lib/libbsp/m68k/idp/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mcf52235/preinstall.am b/c/src/lib/libbsp/m68k/mcf52235/preinstall.am index 73323b5..67ceb2b 100644 --- a/c/src/lib/libbsp/m68k/mcf52235/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf52235/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/mcf5235/preinstall.am b/c/src/lib/libbsp/m68k/mcf5235/preinstall.am index 916e8d1..321a130 100644 --- a/c/src/lib/libbsp/m68k/mcf5235/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf5235/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mcf5329/preinstall.am b/c/src/lib/libbsp/m68k/mcf5329/preinstall.am index aaadccc..24be79a 100644 --- a/c/src/lib/libbsp/m68k/mcf5329/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf5329/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mrm332/preinstall.am b/c/src/lib/libbsp/m68k/mrm332/preinstall.am index 4ab583c..e8ddde2 100644 --- a/c/src/lib/libbsp/m68k/mrm332/preinstall.am +++ b/c/src/lib/libbsp/m68k/mrm332/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mvme136/preinstall.am b/c/src/lib/libbsp/m68k/mvme136/preinstall.am index ed79155..312b0f4 100644 --- a/c/src/lib/libbsp/m68k/mvme136/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme136/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mvme147/preinstall.am b/c/src/lib/libbsp/m68k/mvme147/preinstall.am index ed79155..312b0f4 100644 --- a/c/src/lib/libbsp/m68k/mvme147/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme147/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mvme147s/preinstall.am b/c/src/lib/libbsp/m68k/mvme147s/preinstall.am index ed79155..312b0f4 100644 --- a/c/src/lib/libbsp/m68k/mvme147s/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme147s/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mvme162/preinstall.am b/c/src/lib/libbsp/m68k/mvme162/preinstall.am index 528c115..59198f3 100644 --- a/c/src/lib/libbsp/m68k/mvme162/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme162/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mvme167/preinstall.am b/c/src/lib/libbsp/m68k/mvme167/preinstall.am index fd59d14..ea1d67d 100644 --- a/c/src/lib/libbsp/m68k/mvme167/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme167/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/ods68302/preinstall.am b/c/src/lib/libbsp/m68k/ods68302/preinstall.am index f95a843..7f0436f 100644 --- a/c/src/lib/libbsp/m68k/ods68302/preinstall.am +++ b/c/src/lib/libbsp/m68k/ods68302/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/uC5282/preinstall.am b/c/src/lib/libbsp/m68k/uC5282/preinstall.am index 73323b5..e3970ec 100644 --- a/c/src/lib/libbsp/m68k/uC5282/preinstall.am +++ b/c/src/lib/libbsp/m68k/uC5282/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/csb350/preinstall.am b/c/src/lib/libbsp/mips/csb350/preinstall.am index 244a228..d05c802 100644 --- a/c/src/lib/libbsp/mips/csb350/preinstall.am +++ b/c/src/lib/libbsp/mips/csb350/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/genmongoosev/preinstall.am b/c/src/lib/libbsp/mips/genmongoosev/preinstall.am index b2e4615..a6505c0 100644 --- a/c/src/lib/libbsp/mips/genmongoosev/preinstall.am +++ b/c/src/lib/libbsp/mips/genmongoosev/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/malta/preinstall.am b/c/src/lib/libbsp/mips/malta/preinstall.am index 8d22a8c..091e11b 100644 --- a/c/src/lib/libbsp/mips/malta/preinstall.am +++ b/c/src/lib/libbsp/mips/malta/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/rbtx4938/preinstall.am b/c/src/lib/libbsp/mips/rbtx4938/preinstall.am index b2d7806..11efecd 100644 --- a/c/src/lib/libbsp/mips/rbtx4938/preinstall.am +++ b/c/src/lib/libbsp/mips/rbtx4938/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/moxie/moxiesim/preinstall.am b/c/src/lib/libbsp/moxie/moxiesim/preinstall.am index bdd3a3e..347e43d 100644 --- a/c/src/lib/libbsp/moxie/moxiesim/preinstall.am +++ b/c/src/lib/libbsp/moxie/moxiesim/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am b/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am index 5e40708..87f904e 100644 --- a/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am +++ b/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am b/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am index 72d079a..a6a238d 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am +++ b/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am index 2569864..a83e053 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am +++ b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/beatnik/preinstall.am b/c/src/lib/libbsp/powerpc/beatnik/preinstall.am index f2dbe5f..10efa55 100644 --- a/c/src/lib/libbsp/powerpc/beatnik/preinstall.am +++ b/c/src/lib/libbsp/powerpc/beatnik/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/ep1a/preinstall.am b/c/src/lib/libbsp/powerpc/ep1a/preinstall.am index 3680071..88a9e13 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/preinstall.am +++ b/c/src/lib/libbsp/powerpc/ep1a/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/gen5200/preinstall.am b/c/src/lib/libbsp/powerpc/gen5200/preinstall.am index 6720cd2..9f5d146 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/preinstall.am +++ b/c/src/lib/libbsp/powerpc/gen5200/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am index 8fe05dc..ab9dd65 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am +++ b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/haleakala/preinstall.am b/c/src/lib/libbsp/powerpc/haleakala/preinstall.am index fc36cf9..8f70554 100644 --- a/c/src/lib/libbsp/powerpc/haleakala/preinstall.am +++ b/c/src/lib/libbsp/powerpc/haleakala/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am b/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am index 047971f..43ca5a9 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/preinstall.am b/c/src/lib/libbsp/powerpc/motorola_powerpc/preinstall.am index 248ed37..86585eb 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/preinstall.am +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am b/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am index 50714c3..aa78beb 100644 --- a/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/preinstall.am b/c/src/lib/libbsp/powerpc/mpc8260ads/preinstall.am index 82ab792..071a7e3 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/psim/preinstall.am b/c/src/lib/libbsp/powerpc/psim/preinstall.am index 044618b..ecf4a2b 100644 --- a/c/src/lib/libbsp/powerpc/psim/preinstall.am +++ b/c/src/lib/libbsp/powerpc/psim/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am b/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am index 0a0653a..4fa463d 100644 --- a/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am +++ b/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/qoriq/preinstall.am b/c/src/lib/libbsp/powerpc/qoriq/preinstall.am index 34d6cab..8adee61 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/preinstall.am +++ b/c/src/lib/libbsp/powerpc/qoriq/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/score603e/preinstall.am b/c/src/lib/libbsp/powerpc/score603e/preinstall.am index 4d2f767..036f227 100644 --- a/c/src/lib/libbsp/powerpc/score603e/preinstall.am +++ b/c/src/lib/libbsp/powerpc/score603e/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/ss555/preinstall.am b/c/src/lib/libbsp/powerpc/ss555/preinstall.am index a21da1f..6d7cb01 100644 --- a/c/src/lib/libbsp/powerpc/ss555/preinstall.am +++ b/c/src/lib/libbsp/powerpc/ss555/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am b/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am index 2d73712..d3bec9c 100644 --- a/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am +++ b/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/virtex/preinstall.am b/c/src/lib/libbsp/powerpc/virtex/preinstall.am index 07c6ff9..e8b4481 100644 --- a/c/src/lib/libbsp/powerpc/virtex/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/virtex4/preinstall.am b/c/src/lib/libbsp/powerpc/virtex4/preinstall.am index e441f38..f507474 100644 --- a/c/src/lib/libbsp/powerpc/virtex4/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex4/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/virtex5/preinstall.am b/c/src/lib/libbsp/powerpc/virtex5/preinstall.am index e441f38..b0155fc 100644 --- a/c/src/lib/libbsp/powerpc/virtex5/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex5/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sh/gensh1/preinstall.am b/c/src/lib/libbsp/sh/gensh1/preinstall.am index 639852c..0334fd7 100644 --- a/c/src/lib/libbsp/sh/gensh1/preinstall.am +++ b/c/src/lib/libbsp/sh/gensh1/preinstall.am @@ -8,16 +8,16 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/sh/gensh2/preinstall.am b/c/src/lib/libbsp/sh/gensh2/preinstall.am index 7d4c5ec..b44511c 100644 --- a/c/src/lib/libbsp/sh/gensh2/preinstall.am +++ b/c/src/lib/libbsp/sh/gensh2/preinstall.am @@ -8,16 +8,16 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/sh/gensh4/preinstall.am b/c/src/lib/libbsp/sh/gensh4/preinstall.am index 3821249..b7d09e5 100644 --- a/c/src/lib/libbsp/sh/gensh4/preinstall.am +++ b/c/src/lib/libbsp/sh/gensh4/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/sh/shsim/preinstall.am b/c/src/lib/libbsp/sh/shsim/preinstall.am index 9e08790..202e051 100644 --- a/c/src/lib/libbsp/sh/shsim/preinstall.am +++ b/c/src/lib/libbsp/sh/shsim/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sparc/erc32/preinstall.am b/c/src/lib/libbsp/sparc/erc32/preinstall.am index 71ef19e..7bae1e1 100644 --- a/c/src/lib/libbsp/sparc/erc32/preinstall.am +++ b/c/src/lib/libbsp/sparc/erc32/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sparc/leon2/preinstall.am b/c/src/lib/libbsp/sparc/leon2/preinstall.am index 006bb70..a3bcae5 100644 --- a/c/src/lib/libbsp/sparc/leon2/preinstall.am +++ b/c/src/lib/libbsp/sparc/leon2/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sparc/leon3/preinstall.am b/c/src/lib/libbsp/sparc/leon3/preinstall.am index 210558e..443400d 100644 --- a/c/src/lib/libbsp/sparc/leon3/preinstall.am +++ b/c/src/lib/libbsp/sparc/leon3/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/sparc64/usiii/preinstall.am b/c/src/lib/libbsp/sparc64/usiii/preinstall.am index 73f10f9..2122b19 100644 --- a/c/src/lib/libbsp/sparc64/usiii/preinstall.am +++ b/c/src/lib/libbsp/sparc64/usiii/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libcpu/arm/preinstall.am b/c/src/lib/libcpu/arm/preinstall.am index 751a085..c756d19 100644 --- a/c/src/lib/libcpu/arm/preinstall.am +++ b/c/src/lib/libcpu/arm/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/bfin/preinstall.am b/c/src/lib/libcpu/bfin/preinstall.am index a8b2fa9..36f6ca9 100644 --- a/c/src/lib/libcpu/bfin/preinstall.am +++ b/c/src/lib/libcpu/bfin/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/lm32/preinstall.am b/c/src/lib/libcpu/lm32/preinstall.am index 0516c2c..9667d9c 100644 --- a/c/src/lib/libcpu/lm32/preinstall.am +++ b/c/src/lib/libcpu/lm32/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + if shared $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu diff --git a/c/src/lib/libcpu/mips/preinstall.am b/c/src/lib/libcpu/mips/preinstall.am index 4a83d60..0f5a379 100644 --- a/c/src/lib/libcpu/mips/preinstall.am +++ b/c/src/lib/libcpu/mips/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) diff --git a/c/src/lib/libcpu/powerpc/preinstall.am b/c/src/lib/libcpu/powerpc/preinstall.am index 129855e..33d79d9 100644 --- a/c/src/lib/libcpu/powerpc/preinstall.am +++ b/c/src/lib/libcpu/powerpc/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/sparc64/preinstall.am b/c/src/lib/libcpu/sparc64/preinstall.am index 83b9153..ab9d46e 100644 --- a/c/src/lib/libcpu/sparc64/preinstall.am +++ b/c/src/lib/libcpu/sparc64/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + if shared $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu diff --git a/c/src/librtems++/preinstall.am b/c/src/librtems++/preinstall.am index 256004c..55d3cbf 100644 --- a/c/src/librtems++/preinstall.am +++ b/c/src/librtems++/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/ftpd/preinstall.am b/cpukit/ftpd/preinstall.am index 85ae87d..abeefb3 100644 --- a/cpukit/ftpd/preinstall.am +++ b/cpukit/ftpd/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/cpukit/mghttpd/preinstall.am b/cpukit/mghttpd/preinstall.am index 305a914..b63c988 100644 --- a/cpukit/mghttpd/preinstall.am +++ b/cpukit/mghttpd/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/posix/preinstall.am b/cpukit/posix/preinstall.am index 6e3f2a2..beb6d58 100644 --- a/cpukit/posix/preinstall.am +++ b/cpukit/posix/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/preinstall.am b/cpukit/preinstall.am index 70923f0..b2f88a9 100644 --- a/cpukit/preinstall.am +++ b/cpukit/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/score/cpu/bfin/preinstall.am b/cpukit/score/cpu/bfin/preinstall.am index a16a047..c5f501c 100644 --- a/cpukit/score/cpu/bfin/preinstall.am +++ b/cpukit/score/cpu/bfin/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/h8300/preinstall.am b/cpukit/score/cpu/h8300/preinstall.am index f3c1681..0f89b1c 100644 --- a/cpukit/score/cpu/h8300/preinstall.am +++ b/cpukit/score/cpu/h8300/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/i386/preinstall.am b/cpukit/score/cpu/i386/preinstall.am index 060176b..2d29558 100644 --- a/cpukit/score/cpu/i386/preinstall.am +++ b/cpukit/score/cpu/i386/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/m32r/preinstall.am b/cpukit/score/cpu/m32r/preinstall.am index 3d76b74..044514a 100644 --- a/cpukit/score/cpu/m32r/preinstall.am +++ b/cpukit/score/cpu/m32r/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/score/cpu/mips/preinstall.am b/cpukit/score/cpu/mips/preinstall.am index 2385f8c..bca004a 100644 --- a/cpukit/score/cpu/mips/preinstall.am +++ b/cpukit/score/cpu/mips/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/powerpc/preinstall.am b/cpukit/score/cpu/powerpc/preinstall.am index 3293498..ccc4cbe 100644 --- a/cpukit/score/cpu/powerpc/preinstall.am +++ b/cpukit/score/cpu/powerpc/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/sparc64/preinstall.am b/cpukit/score/cpu/sparc64/preinstall.am index 00af891..3f53e73 100644 --- a/cpukit/score/cpu/sparc64/preinstall.am +++ b/cpukit/score/cpu/sparc64/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/preinstall.am b/cpukit/score/preinstall.am index 891c21e..a1e4583 100644 --- a/cpukit/score/preinstall.am +++ b/cpukit/score/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/telnetd/preinstall.am b/cpukit/telnetd/preinstall.am index 68bf81f..9acb287 100644 --- a/cpukit/telnetd/preinstall.am +++ b/cpukit/telnetd/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/zlib/preinstall.am b/cpukit/zlib/preinstall.am index ea2f248..27b3248 100644 --- a/cpukit/zlib/preinstall.am +++ b/cpukit/zlib/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = From chrisj at rtems.org Fri Aug 29 01:43:10 2014 From: chrisj at rtems.org (Chris Johns) Date: Thu, 28 Aug 2014 20:43:10 -0500 Subject: [rtems-source-builder commit] Fix bug of uncompressing zip files. Message-ID: <20140829014310.89820700852@git.rtems.org> Module: rtems-source-builder Branch: master Commit: e7a6292cb590ec5629abaa94e17a38bd6a368ad1 Changeset: http://git.rtems.org/rtems-source-builder/commit/?id=e7a6292cb590ec5629abaa94e17a38bd6a368ad1 Author: Hesham ALMatary Date: Thu Aug 28 19:14:05 2014 +0200 Fix bug of uncompressing zip files. This patch uses __unzip macro for uncompressing zip files instead of the wrong __zip macro which is not defined in defaults.mc file. --- source-builder/sb/download.py | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/source-builder/sb/download.py b/source-builder/sb/download.py index fbf9ce0..fdc834a 100644 --- a/source-builder/sb/download.py +++ b/source-builder/sb/download.py @@ -110,7 +110,7 @@ def _http_parser(source, config, opts): source['compressed'] = '%{__bzip2} -dc' elif esl[-1:][0] == 'zip': source['compressed-type'] = 'zip' - source['compressed'] = '%{__zip} -u' + source['compressed'] = '%{__unzip} -u' elif esl[-1:][0] == 'xz': source['compressed-type'] = 'xz' source['compressed'] = '%{__xz} -dc' From chrisj at rtems.org Fri Aug 29 01:43:10 2014 From: chrisj at rtems.org (Chris Johns) Date: Thu, 28 Aug 2014 20:43:10 -0500 Subject: [rtems-source-builder commit] Add support for building bare-metal or1ksim. Message-ID: <20140829014310.C7F6970064D@git.rtems.org> Module: rtems-source-builder Branch: master Commit: 183626a1d4c88bd5e2a829154b1db72642240729 Changeset: http://git.rtems.org/rtems-source-builder/commit/?id=183626a1d4c88bd5e2a829154b1db72642240729 Author: Hesham ALMatary Date: Thu Aug 28 19:14:34 2014 +0200 Add support for building bare-metal or1ksim. This patch adds support to enable RSB to build or1ksim emulator (the main OpenRISC 1000 simulator) from latest or1ksim github repo. --- bare/config/devel/or1ksim-1.1.0.cfg | 16 +++++++++ bare/config/devel/or1ksim.bset | 7 ++++ source-builder/config/or1ksim-1-1.cfg | 57 +++++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+), 0 deletions(-) diff --git a/bare/config/devel/or1ksim-1.1.0.cfg b/bare/config/devel/or1ksim-1.1.0.cfg new file mode 100644 index 0000000..bfd1a44 --- /dev/null +++ b/bare/config/devel/or1ksim-1.1.0.cfg @@ -0,0 +1,16 @@ +# +# or1ksim emulator 1.1.0 +# + +%if %{release} == %{nil} +%define release 1 +%endif + +%include %{_configdir}/base.cfg + +%define or1ksim_version 1.1.0 + +# +# The or1ksim build instructions. We use 1.x.x Release 1. +# +%include %{_configdir}/or1ksim-1-1.cfg diff --git a/bare/config/devel/or1ksim.bset b/bare/config/devel/or1ksim.bset new file mode 100644 index 0000000..2941553 --- /dev/null +++ b/bare/config/devel/or1ksim.bset @@ -0,0 +1,7 @@ +# +# Build set for or1ksim emulator +# + +%define release 1 + +devel/or1ksim-1.1.0 diff --git a/source-builder/config/or1ksim-1-1.cfg b/source-builder/config/or1ksim-1-1.cfg new file mode 100644 index 0000000..30dfe13 --- /dev/null +++ b/source-builder/config/or1ksim-1-1.cfg @@ -0,0 +1,57 @@ +# +# or1ksim 1.x.x Version 1. +# +# This configuration file configure's, make's and install's or1ksim. +# + +%if %{release} == %{nil} +%define release 1 +%endif + +Name: or1ksim-1.1.0 +Summary: or1ksim-github +Version: %{or1ksim_version} +Release: %{release} +URL: https://github.com/openrisc/or1ksim +BuildRoot: %{_tmppath}/%{name}-root-%(%{__id_u} -n) + +# +# Source +# +%source set or1ksim https://github.com/openrisc/or1ksim/archive/or1k-master.zip + +# +# Prepare the source code. +# +%prep + build_top=$(pwd) + + %source setup or1ksim -q -n or1ksim-or1k-master + + cd ${build_top} + +%build + build_top=$(pwd) + + cd or1ksim-or1k-master/ + + ../or1ksim-or1k-master/configure \ + --target=or1k-elf \ + --prefix=%{_prefix} \ + CFLAGS="-O0 -DINLINE=static -DNO_SOFTFLOAT_UNUSED" + + + %{__make} %{?_smp_mflags} all$ + + + cd ${build_top} + +%install + build_top=$(pwd) + + rm -rf $SB_BUILD_ROOT + + cd or1ksim-or1k-master + %{__make} DESTDIR=$SB_BUILD_ROOT PREFIX=%{_prefix} install + + cd ${build_top} From joel at rtems.org Fri Aug 29 18:24:58 2014 From: joel at rtems.org (Joel Sherrill) Date: Fri, 29 Aug 2014 13:24:58 -0500 Subject: [examples-v2 commit] example-v2 patch for RPi B+ (led) Message-ID: <20140829182459.3811C70025E@git.rtems.org> Module: examples-v2 Branch: master Commit: 944b4f1f73e8f173fd9c3efaaf79a4b542375106 Changeset: http://git.rtems.org/examples-v2/commit/?id=944b4f1f73e8f173fd9c3efaaf79a4b542375106 Author: Pierre Ficheux Date: Fri Aug 29 08:16:23 2014 -0500 example-v2 patch for RPi B+ (led) Hi, Here is the patch for "example-v2" project to support Raspberry Pi B+ as led number is now 47 instead of 16 on RPi B. regards -- Pierre FICHEUX -/- CTO OW/OWI, France -\- pierre.ficheux at openwide.fr http://ingenierie.openwide.fr http://www.linuxembedded.fr I would love to change the world, but they won't give me the source code >From e4d8edfb8650207641bc8e2716cf15ce958ede0f Mon Sep 17 00:00:00 2001 From: Pierre FICHEUX Date: Fri, 29 Aug 2014 15:11:41 +0200 Subject: [PATCH] Added led blink support for RPi B+ --- led/led.h | 16 ++++++++++++---- 1 files changed, 12 insertions(+), 4 deletions(-) diff --git a/led/led.h b/led/led.h index 152b76a..3fee684 100644 --- a/led/led.h +++ b/led/led.h @@ -67,10 +67,18 @@ uint8_t MPC8313_LED_Count; #define OUT_GPIO(g) *(gpio+((g)/10)) |= (1<<(((g)%10)*3)) #define GPIO_SET *(gpio+7) // sets bits which are 1 ignores bits which are 0 #define GPIO_CLR *(gpio+10) // clears bits which are 1 ignores bits which are 0 - -#define LED_INIT() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; OUT_GPIO(16);} while(0) -#define LED_ON() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_CLR = 1 << 16;} while(0) -#define LED_OFF() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_SET = 1 << 16;} while(0) +// For GPIO# >= 32 (RPi B+) +#define GPIO_SET_EXT *(gpio+8) // sets bits which are 1 ignores bits which are 0 +#define GPIO_CLR_EXT *(gpio+11) // clears bits which are 1 ignores bits which are 0 + +// RPi B +//#define LED_INIT() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; OUT_GPIO(16);} while(0) +//#define LED_ON() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_CLR = 1 << 16;} while(0) +//#define LED_OFF() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_SET = 1 << 16;} while(0) +// RPi B+ => led 47 +#define LED_INIT() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; OUT_GPIO(47);} while(0) +#define LED_ON() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_CLR_EXT = 1 << (47 % 32);} while(0) +#define LED_OFF() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_SET_EXT = 1 << (47 % 32);} while(0) #else /* default case is to print */ From joel at rtems.org Fri Aug 29 18:24:58 2014 From: joel at rtems.org (Joel Sherrill) Date: Fri, 29 Aug 2014 13:24:58 -0500 Subject: [examples-v2 commit] Miscellaneous clean up and warning removal Message-ID: <20140829182458.DD57E70080E@git.rtems.org> Module: examples-v2 Branch: master Commit: 61d2a1f2e8ddb992f98e80cd503879226730eeec Changeset: http://git.rtems.org/examples-v2/commit/?id=61d2a1f2e8ddb992f98e80cd503879226730eeec Author: Joel Sherrill Date: Fri Aug 29 13:17:40 2014 -0500 Miscellaneous clean up and warning removal --- cxx/cxx_throw/init.cc | 6 ++++++ hello/hello_world_c/test.c | 7 +++++-- hello/wscript | 1 + led/event_server/init.c | 13 ++++++------- led/msg_server/init.c | 33 +++++++++++++++------------------ led/ratemon1/init.c | 7 +++---- led/ratemon2/init.c | 19 ++++++++----------- led/timeout_event/init.c | 14 ++++++++------ led/timer/init.c | 22 ++++++---------------- led/timer_server/init.c | 25 +++++++------------------ ticker/ticker/init.c | 36 +++++++++++++++--------------------- 11 files changed, 80 insertions(+), 103 deletions(-) diff --git a/cxx/cxx_throw/init.cc b/cxx/cxx_throw/init.cc index 041a73f..b001015 100644 --- a/cxx/cxx_throw/init.cc +++ b/cxx/cxx_throw/init.cc @@ -164,6 +164,12 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE #define CONFIGURE_MAXIMUM_TASKS 1 +/* + * GCC C++ support requires Classic Semaphores but this could change to + * POSIX mutexes at some point in the future. When that happens, this will + * need to change. + */ +#define CONFIGURE_MAXIMUM_SEMAPHORES 1 #define CONFIGURE_INIT diff --git a/hello/hello_world_c/test.c b/hello/hello_world_c/test.c index 67ca6b1..04a55fe 100644 --- a/hello/hello_world_c/test.c +++ b/hello/hello_world_c/test.c @@ -1,8 +1,8 @@ /* - * Simple test program -- simplified version of sample test hello. + * Classic API Hello World */ -#include +#include #include #include @@ -18,9 +18,12 @@ rtems_task Init( /* configuration information */ +#include + /* NOTICE: the clock driver is explicitly disabled */ #define CONFIGURE_APPLICATION_DOES_NOT_NEED_CLOCK_DRIVER #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER +#define CONFIGURE_USE_DEVFS_AS_BASE_FILESYSTEM #define CONFIGURE_RTEMS_INIT_TASKS_TABLE #define CONFIGURE_MAXIMUM_TASKS 1 diff --git a/hello/wscript b/hello/wscript index ca09158..d03283e 100644 --- a/hello/wscript +++ b/hello/wscript @@ -7,6 +7,7 @@ import rtems_waf.rtems as rtems def build(bld): bld.recurse('hello_world_c') + bld.recurse('main') if rtems.check_posix(bld): bld.recurse('posix_hello_world') bld.recurse('both_hello') diff --git a/led/event_server/init.c b/led/event_server/init.c index 5aa82df..90b0360 100644 --- a/led/event_server/init.c +++ b/led/event_server/init.c @@ -17,12 +17,11 @@ rtems_task Test_task( rtems_task_argument unused ) { - rtems_event_set events; - rtems_status_code status; + rtems_event_set events; for ( ; ; ) { events = 0; - status = rtems_event_receive( + (void) rtems_event_receive( (RTEMS_EVENT_1 | RTEMS_EVENT_2), RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, @@ -55,12 +54,12 @@ rtems_task Init( task_name = rtems_build_name( 'T', 'A', '1', ' ' ); - status = rtems_task_create( + (void) rtems_task_create( task_name, 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_MODES, RTEMS_DEFAULT_ATTRIBUTES, &task_id ); - status = rtems_task_start( task_id, Test_task, 1 ); + (void) rtems_task_start( task_id, Test_task, 1 ); for (count=0; ; count++) { @@ -69,10 +68,10 @@ rtems_task Init( if ( status != RTEMS_SUCCESSFUL ) fputs( "send did not work\n", stderr ); - status = rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); + (void) rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ diff --git a/led/msg_server/init.c b/led/msg_server/init.c index 5389d93..4974dea 100644 --- a/led/msg_server/init.c +++ b/led/msg_server/init.c @@ -20,11 +20,10 @@ rtems_task Test_task( { uint32_t count; size_t received; - rtems_status_code status; for ( ; ; ) { count = 0xFFFFFFFF; - status = rtems_message_queue_receive( + (void) rtems_message_queue_receive( Queue_id, (void *) &count, &received, @@ -44,16 +43,15 @@ rtems_task Init( rtems_task_argument argument ) { - uint32_t count = 0; - rtems_status_code status; + uint32_t count; rtems_id task_id; - rtems_name task_name; + rtems_status_code status; puts( "\n\n*** LED BLINKER -- message receive server ***" ); LED_INIT(); - status = rtems_message_queue_create( + (void) rtems_message_queue_create( rtems_build_name( 'Q', '1', ' ', ' ' ), 1, sizeof(uint32_t), @@ -61,14 +59,16 @@ rtems_task Init( &Queue_id ); - task_name = rtems_build_name( 'T', 'A', '1', ' ' ); - - status = rtems_task_create( - task_name, 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_MODES, - RTEMS_DEFAULT_ATTRIBUTES, &task_id + (void) rtems_task_create( + rtems_build_name( 'T', 'A', '1', ' ' ), + 1, + RTEMS_MINIMUM_STACK_SIZE, + RTEMS_DEFAULT_MODES, + RTEMS_DEFAULT_ATTRIBUTES, + &task_id ); - status = rtems_task_start( task_id, Test_task, 1 ); + (void) rtems_task_start( task_id, Test_task, 1 ); for (count=0; ; count++) { @@ -77,16 +77,14 @@ rtems_task Init( if ( status != RTEMS_SUCCESSFUL ) fputs( "send did not work\n", stderr ); - status = rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); + (void) rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ -#define CONFIGURE_INIT - #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER @@ -95,8 +93,7 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE -#define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE) - +#define CONFIGURE_INIT #include /**************** END OF CONFIGURATION INFORMATION ****************/ diff --git a/led/ratemon1/init.c b/led/ratemon1/init.c index 13d977c..4e587f4 100644 --- a/led/ratemon1/init.c +++ b/led/ratemon1/init.c @@ -16,7 +16,6 @@ rtems_task Init( rtems_task_argument argument ) { - rtems_status_code status; rtems_id period_id; rtems_interval ticks; uint32_t count; @@ -25,7 +24,7 @@ rtems_task Init( LED_INIT(); - status = rtems_rate_monotonic_create( + (void) rtems_rate_monotonic_create( rtems_build_name( 'P', 'E', 'R', '1' ), &period_id ); @@ -33,14 +32,14 @@ rtems_task Init( ticks = rtems_clock_get_ticks_per_second(); for (count=0; ; count++) { - status = rtems_rate_monotonic_period( period_id, ticks ); + (void) rtems_rate_monotonic_period( period_id, ticks ); if ( (count % 2) == 0 ) LED_OFF(); else LED_ON(); } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ diff --git a/led/ratemon2/init.c b/led/ratemon2/init.c index c27150b..33aa542 100644 --- a/led/ratemon2/init.c +++ b/led/ratemon2/init.c @@ -16,7 +16,6 @@ rtems_task Init( rtems_task_argument argument ) { - rtems_status_code status; rtems_id period_id1; rtems_id period_id2; rtems_interval ticks; @@ -25,39 +24,38 @@ rtems_task Init( LED_INIT(); - status = rtems_rate_monotonic_create( + (void) rtems_rate_monotonic_create( rtems_build_name( 'P', 'E', 'R', '1' ), &period_id1 ); - status = rtems_rate_monotonic_create( + (void) rtems_rate_monotonic_create( rtems_build_name( 'P', 'E', 'R', '2' ), &period_id2 ); ticks = rtems_clock_get_ticks_per_second(); - status = rtems_rate_monotonic_period( period_id1, 2 * ticks ); + (void) rtems_rate_monotonic_period( period_id1, 2 * ticks ); LED_OFF(); (void) rtems_task_wake_after( ticks ); - status = rtems_rate_monotonic_period( period_id2, 2 * ticks ); + (void) rtems_rate_monotonic_period( period_id2, 2 * ticks ); LED_ON(); while (1) { - status = rtems_rate_monotonic_period( period_id1, 2 * ticks ); + (void) rtems_rate_monotonic_period( period_id1, 2 * ticks ); LED_OFF(); - status = rtems_rate_monotonic_period( period_id2, 2 * ticks ); + (void) rtems_rate_monotonic_period( period_id2, 2 * ticks ); LED_ON(); } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ -#define CONFIGURE_INIT #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER @@ -66,8 +64,7 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE -#define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE) - +#define CONFIGURE_INIT #include /**************** END OF CONFIGURATION INFORMATION ****************/ diff --git a/led/timeout_event/init.c b/led/timeout_event/init.c index b7c35f7..b9e2c77 100644 --- a/led/timeout_event/init.c +++ b/led/timeout_event/init.c @@ -27,8 +27,12 @@ rtems_task Init( for (count=0; ; count++) { - status = rtems_event_receive( RTEMS_EVENT_1, - RTEMS_DEFAULT_OPTIONS, rtems_clock_get_ticks_per_second(), &events ); + status = rtems_event_receive( + RTEMS_EVENT_1, + RTEMS_DEFAULT_OPTIONS, + rtems_clock_get_ticks_per_second(), + &events + ); if ( status != RTEMS_TIMEOUT ) fputs( "receive did not timeout\n", stderr ); @@ -39,12 +43,11 @@ rtems_task Init( } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ -#define CONFIGURE_INIT #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER @@ -52,8 +55,7 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE -#define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE) - +#define CONFIGURE_INIT #include /**************** END OF CONFIGURATION INFORMATION ****************/ diff --git a/led/timer/init.c b/led/timer/init.c index cc44dae..70364ad 100644 --- a/led/timer/init.c +++ b/led/timer/init.c @@ -37,15 +37,13 @@ void LED_Change_Routine( void ) { rtems_timer_service_routine Timer_Routine( rtems_id id, void *ignored ) { - rtems_status_code status; - if ( id == Timer1 ) led_value = 1; else led_value = 2; led_do_print = 1; - status = rtems_timer_fire_after( + (void) rtems_timer_fire_after( id, 2 * rtems_clock_get_ticks_per_second(), Timer_Routine, @@ -57,34 +55,28 @@ rtems_task Init( rtems_task_argument argument ) { - rtems_status_code status; - puts( "\n\n*** LED BLINKER -- timer ***" ); LED_INIT(); - status = rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '1' ), &Timer1); - if ( status != RTEMS_SUCCESSFUL ) - fputs( "Timer1 create failed\n", stderr ); + (void) rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '1' ), &Timer1); - status = rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '2' ), &Timer2); - if ( status != RTEMS_SUCCESSFUL ) - fputs( "Timer2 create failed\n", stderr ); + (void) rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '2' ), &Timer2); Timer_Routine(Timer1, NULL); LED_Change_Routine(); - status = rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); + (void) rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); Timer_Routine(Timer2, NULL); LED_Change_Routine(); while (1) { - status = rtems_task_wake_after( 10 ); + (void) rtems_task_wake_after( 10 ); LED_Change_Routine(); } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } @@ -98,8 +90,6 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE -#define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE) - #define CONFIGURE_INIT #include /**************** END OF CONFIGURATION INFORMATION ****************/ diff --git a/led/timer_server/init.c b/led/timer_server/init.c index 29d63af..69ec0cb 100644 --- a/led/timer_server/init.c +++ b/led/timer_server/init.c @@ -17,14 +17,12 @@ rtems_id Timer2; rtems_timer_service_routine Timer_Routine( rtems_id id, void *ignored ) { - rtems_status_code status; - if ( id == Timer1 ) LED_OFF(); else LED_ON(); - status = rtems_timer_server_fire_after( + (void) rtems_timer_server_fire_after( id, 2 * rtems_clock_get_ticks_per_second(), Timer_Routine, @@ -36,36 +34,27 @@ rtems_task Init( rtems_task_argument argument ) { - rtems_status_code status; - puts( "\n\n*** LED BLINKER -- timer_server ***" ); LED_INIT(); - status = rtems_timer_initiate_server( + (void) rtems_timer_initiate_server( 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_ATTRIBUTES ); - if ( status != RTEMS_SUCCESSFUL ) - fputs( "timer create server failed\n", stderr ); - - status = rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '1' ), &Timer1); - if ( status != RTEMS_SUCCESSFUL ) - fputs( "Timer1 create failed\n", stderr ); + (void) rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '1' ), &Timer1); - status = rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '2' ), &Timer2); - if ( status != RTEMS_SUCCESSFUL ) - fputs( "Timer2 create failed\n", stderr ); + (void) rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '2' ), &Timer2); Timer_Routine(Timer1, NULL); - status = rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); + (void) rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); Timer_Routine(Timer2, NULL); - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } @@ -79,7 +68,7 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE -#define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE) +#define CONFIGURE_EXTRA_TASK_STACKS (RTEMS_MINIMUM_STACK_SIZE) #define CONFIGURE_INIT #include diff --git a/ticker/ticker/init.c b/ticker/ticker/init.c index 4d3d129..4d86cf6 100644 --- a/ticker/ticker/init.c +++ b/ticker/ticker/init.c @@ -18,27 +18,23 @@ rtems_id Task_id[ 4 ]; /* array of task ids */ rtems_name Task_name[ 4 ]; /* array of task names */ rtems_task Test_task( - rtems_task_argument unused + rtems_task_argument task_index ) { - rtems_id tid; rtems_time_of_day time; - uint32_t task_index; - rtems_status_code status; + rtems_interval ticks; + + ticks = task_index * 5 * rtems_clock_get_ticks_per_second(); - status = rtems_task_ident( RTEMS_SELF, RTEMS_SEARCH_ALL_NODES, &tid ); - task_index = task_number( tid ); for ( ; ; ) { - status = rtems_clock_get_tod( &time ); + (void) rtems_clock_get_tod( &time ); if ( time.second >= 35 ) { puts( "*** END OF CLOCK TICK TEST ***" ); exit( 0 ); } put_name( Task_name[ task_index ], FALSE ); print_time( " - rtems_clock_get_tod - ", &time, "\n" ); - status = rtems_task_wake_after( - task_index * 5 * rtems_clock_get_ticks_per_second() - ); + (void) rtems_task_wake_after( ticks ); } } @@ -46,7 +42,6 @@ rtems_task Init( rtems_task_argument argument ) { - rtems_status_code status; rtems_time_of_day time; puts( "\n\n*** CLOCK TICK TEST ***" ); @@ -59,36 +54,34 @@ rtems_task Init( time.second = 0; time.ticks = 0; - status = rtems_clock_set( &time ); + (void) rtems_clock_set( &time ); Task_name[ 1 ] = rtems_build_name( 'T', 'A', '1', ' ' ); Task_name[ 2 ] = rtems_build_name( 'T', 'A', '2', ' ' ); Task_name[ 3 ] = rtems_build_name( 'T', 'A', '3', ' ' ); - status = rtems_task_create( + (void) rtems_task_create( Task_name[ 1 ], 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_MODES, RTEMS_DEFAULT_ATTRIBUTES, &Task_id[ 1 ] ); - status = rtems_task_create( + (void) rtems_task_create( Task_name[ 2 ], 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_MODES, RTEMS_DEFAULT_ATTRIBUTES, &Task_id[ 2 ] ); - status = rtems_task_create( + (void) rtems_task_create( Task_name[ 3 ], 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_MODES, RTEMS_DEFAULT_ATTRIBUTES, &Task_id[ 3 ] ); - status = rtems_task_start( Task_id[ 1 ], Test_task, 1 ); - status = rtems_task_start( Task_id[ 2 ], Test_task, 2 ); - status = rtems_task_start( Task_id[ 3 ], Test_task, 3 ); + (void) rtems_task_start( Task_id[ 1 ], Test_task, 1 ); + (void) rtems_task_start( Task_id[ 2 ], Test_task, 2 ); + (void) rtems_task_start( Task_id[ 3 ], Test_task, 3 ); - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ -#define CONFIGURE_INIT - #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER @@ -99,6 +92,7 @@ rtems_task Init( #define CONFIGURE_EXTRA_TASK_STACKS (4 * RTEMS_MINIMUM_STACK_SIZE) +#define CONFIGURE_INIT #include /**************** END OF CONFIGURATION INFORMATION ****************/ From chrisj at rtems.org Sat Aug 30 22:37:22 2014 From: chrisj at rtems.org (Chris Johns) Date: Sat, 30 Aug 2014 17:37:22 -0500 Subject: [rtems commit] bootstrap: Sort the various hash keys used in generating preinstall.am. Message-ID: <20140830223723.5D7777006A2@git.rtems.org> Module: rtems Branch: master Commit: 93d0ddd41b6eec7e250eaad1f799cab6cdfb27f8 Changeset: http://git.rtems.org/rtems/commit/?id=93d0ddd41b6eec7e250eaad1f799cab6cdfb27f8 Author: Chris Johns Date: Fri Aug 29 11:39:29 2014 +1000 bootstrap: Sort the various hash keys used in generating preinstall.am. Something must have changed in perl to change the way the keys are ordered by default. --- ampolish3 | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/ampolish3 b/ampolish3 index 69bbf7b..aaa9757 100755 --- a/ampolish3 +++ b/ampolish3 @@ -9,7 +9,7 @@ # # Usage: ampolish3 Makefile.am > preinstall.am # -# Reads a Makefile.am from stdin and writes corresponding +# Reads a Makefile.am from stdin and writes corresponding # pre/tmpinstall rules to stdout. sub replace($); @@ -85,7 +85,7 @@ foreach my $l ( @buffer1 ) { push @buffer2, "$l"; $dirmap{"\$\($1\)"} = replace($2); } elsif ( $l =~ /^\s*noinst_(.*)\s*[\+]?\=(.*)$/o ) - { + { #ignore: noinst_* are not relevant here. } elsif ( $l =~ /^\s*(nodist_|dist_|)(project_|)([a-zA-Z0-9_]+)_(HEADERS|LIBRARIES|DATA|SCRIPTS|PROGRAMS)\s*([\+]?\=)\s*(.*)/o ) { @@ -217,7 +217,7 @@ $output .= "\$(srcdir)/preinstall.am: Makefile.am\n"; $output .= "\t\$(AMPOLISH3) \$(srcdir)/Makefile.am > \$(srcdir)/preinstall.am\n"; $output .= "endif\n\n"; -foreach my $k ( keys %seen ) +foreach my $k ( sort keys %seen ) { if ( $k =~ /PREINSTALL_FILES/o ) { $output .= "all-am: \$(PREINSTALL_FILES)\n\n"; @@ -258,7 +258,7 @@ exit 0; sub replace($) { my ($v) = @_; - foreach my $i ( keys %dirmap ) + foreach my $i ( sort keys %dirmap ) { $v =~ s/\Q$i/$dirmap{$i}/g; } From chrisj at rtems.org Sat Aug 30 22:37:22 2014 From: chrisj at rtems.org (Chris Johns) Date: Sat, 30 Aug 2014 17:37:22 -0500 Subject: [rtems commit] Regenerate all preinstall.am files. Message-ID: <20140830223723.1EBE87006F7@git.rtems.org> Module: rtems Branch: master Commit: 59990cc9752c892dffed6ac0e074d3876c2f663f Changeset: http://git.rtems.org/rtems/commit/?id=59990cc9752c892dffed6ac0e074d3876c2f663f Author: Chris Johns Date: Fri Aug 29 12:48:01 2014 +1000 Regenerate all preinstall.am files. With this patch the preinstall.am files are in a set order and not dependent on now perl implements a hash. --- .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/csb336/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/csb337/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/edb7312/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/gba/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/gdbarmsim/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/gumstix/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/lpc176x/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/lpc24xx/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/lpc32xx/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/rtl22xx/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/smdk2410/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/stm32f4/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/tms570/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am | 6 +++--- c/src/lib/libbsp/avr/avrtest/preinstall.am | 12 ++++++------ c/src/lib/libbsp/bfin/TLL6527M/preinstall.am | 12 ++++++------ c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am | 6 +++--- c/src/lib/libbsp/bfin/eZKit533/preinstall.am | 6 +++--- c/src/lib/libbsp/h8300/h8sim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/i386/pc386/preinstall.am | 10 +++++----- c/src/lib/libbsp/lm32/lm32_evr/preinstall.am | 12 ++++++------ c/src/lib/libbsp/lm32/milkymist/preinstall.am | 6 +++--- c/src/lib/libbsp/m32c/m32cbsp/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m32r/m32rsim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/av5282/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/csb360/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/gen68302/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/gen68340/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/gen68360/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/genmcf548x/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/idp/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mcf5206elite/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/mcf52235/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/mcf5225x/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/mcf5329/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mrm332/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mvme136/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mvme147/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mvme147s/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mvme162/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mvme167/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/ods68302/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/sim68000/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/uC5282/preinstall.am | 6 +++--- c/src/lib/libbsp/mips/genmongoosev/preinstall.am | 6 +++--- c/src/lib/libbsp/mips/hurricane/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/jmr3904/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/malta/preinstall.am | 6 +++--- c/src/lib/libbsp/mips/rbtx4925/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/rbtx4938/preinstall.am | 6 +++--- c/src/lib/libbsp/nios2/nios2_iss/preinstall.am | 14 +++++++------- c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/beatnik/preinstall.am | 10 +++++----- c/src/lib/libbsp/powerpc/gen5200/preinstall.am | 14 +++++++------- c/src/lib/libbsp/powerpc/gen83xx/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/haleakala/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/mvme3100/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/mvme5500/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/psim/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/qemuppc/preinstall.am | 14 +++++++------- c/src/lib/libbsp/powerpc/qoriq/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/score603e/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/ss555/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/t32mppc/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/tqm8xx/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/virtex/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/virtex4/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/virtex5/preinstall.am | 6 +++--- c/src/lib/libbsp/sh/gensh4/preinstall.am | 12 ++++++------ c/src/lib/libbsp/sh/shsim/preinstall.am | 6 +++--- c/src/lib/libbsp/sparc/erc32/preinstall.am | 6 +++--- c/src/lib/libbsp/sparc/leon3/preinstall.am | 14 +++++++------- c/src/lib/libbsp/sparc64/niagara/preinstall.am | 12 ++++++------ c/src/lib/libbsp/sparc64/usiii/preinstall.am | 12 ++++++------ c/src/lib/libbsp/v850/gdbv850sim/preinstall.am | 12 ++++++------ c/src/lib/libcpu/arm/preinstall.am | 6 +++--- c/src/lib/libcpu/bfin/preinstall.am | 6 +++--- c/src/lib/libcpu/lm32/preinstall.am | 6 +++--- c/src/lib/libcpu/mips/preinstall.am | 6 +++--- c/src/lib/libcpu/powerpc/preinstall.am | 6 +++--- c/src/lib/libcpu/sparc64/preinstall.am | 6 +++--- c/src/libchip/preinstall.am | 12 ++++++------ c/src/librtems++/preinstall.am | 6 +++--- cpukit/ftpd/preinstall.am | 6 +++--- cpukit/libfs/src/nfsclient/preinstall.am | 12 ++++++------ cpukit/posix/preinstall.am | 6 +++--- cpukit/pppd/preinstall.am | 12 ++++++------ cpukit/preinstall.am | 6 +++--- cpukit/sapi/preinstall.am | 12 ++++++------ cpukit/score/cpu/bfin/preinstall.am | 6 +++--- cpukit/score/cpu/h8300/preinstall.am | 6 +++--- cpukit/score/cpu/i386/preinstall.am | 6 +++--- cpukit/score/cpu/m32r/preinstall.am | 6 +++--- cpukit/score/cpu/mips/preinstall.am | 6 +++--- cpukit/score/cpu/powerpc/preinstall.am | 6 +++--- cpukit/score/cpu/sparc64/preinstall.am | 6 +++--- cpukit/score/preinstall.am | 6 +++--- cpukit/zlib/preinstall.am | 10 +++++----- 101 files changed, 447 insertions(+), 447 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 2627812..a3e897c 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/csb336/preinstall.am b/c/src/lib/libbsp/arm/csb336/preinstall.am index 9fdcef7..8d27fcc 100644 --- a/c/src/lib/libbsp/arm/csb336/preinstall.am +++ b/c/src/lib/libbsp/arm/csb336/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/csb337/preinstall.am b/c/src/lib/libbsp/arm/csb337/preinstall.am index 33eaa98..1330f04 100644 --- a/c/src/lib/libbsp/arm/csb337/preinstall.am +++ b/c/src/lib/libbsp/arm/csb337/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/arm/edb7312/preinstall.am b/c/src/lib/libbsp/arm/edb7312/preinstall.am index 7b0639f..911f461 100644 --- a/c/src/lib/libbsp/arm/edb7312/preinstall.am +++ b/c/src/lib/libbsp/arm/edb7312/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/gba/preinstall.am b/c/src/lib/libbsp/arm/gba/preinstall.am index 460ba1a..78c7b89 100644 --- a/c/src/lib/libbsp/arm/gba/preinstall.am +++ b/c/src/lib/libbsp/arm/gba/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am b/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am index 53ad826..de1cec0 100644 --- a/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am +++ b/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/gumstix/preinstall.am b/c/src/lib/libbsp/arm/gumstix/preinstall.am index 2188049..f08e6a8 100644 --- a/c/src/lib/libbsp/arm/gumstix/preinstall.am +++ b/c/src/lib/libbsp/arm/gumstix/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/lpc176x/preinstall.am b/c/src/lib/libbsp/arm/lpc176x/preinstall.am index cea255b..17a27c3 100644 --- a/c/src/lib/libbsp/arm/lpc176x/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc176x/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am index 0e65c58..4c5e993 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am index 6ba42de..73120d4 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am b/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am index 5f72122..36f9c5e 100644 --- a/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am +++ b/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/rtl22xx/preinstall.am b/c/src/lib/libbsp/arm/rtl22xx/preinstall.am index d721095..6529f3c 100644 --- a/c/src/lib/libbsp/arm/rtl22xx/preinstall.am +++ b/c/src/lib/libbsp/arm/rtl22xx/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/smdk2410/preinstall.am b/c/src/lib/libbsp/arm/smdk2410/preinstall.am index 2de69b2..01d4e66 100644 --- a/c/src/lib/libbsp/arm/smdk2410/preinstall.am +++ b/c/src/lib/libbsp/arm/smdk2410/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/stm32f4/preinstall.am b/c/src/lib/libbsp/arm/stm32f4/preinstall.am index a081a88..6b342d1 100644 --- a/c/src/lib/libbsp/arm/stm32f4/preinstall.am +++ b/c/src/lib/libbsp/arm/stm32f4/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am b/c/src/lib/libbsp/arm/tms570/preinstall.am index f88c7fd..d9a0bd9 100644 --- a/c/src/lib/libbsp/arm/tms570/preinstall.am +++ b/c/src/lib/libbsp/arm/tms570/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am index c079c07..f5367b6 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/avr/avrtest/preinstall.am b/c/src/lib/libbsp/avr/avrtest/preinstall.am index bdd3a3e..347e43d 100644 --- a/c/src/lib/libbsp/avr/avrtest/preinstall.am +++ b/c/src/lib/libbsp/avr/avrtest/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am b/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am index 525f222..3091c71 100644 --- a/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am +++ b/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am b/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am index 0142ef7..347e43d 100644 --- a/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am +++ b/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/bfin/eZKit533/preinstall.am b/c/src/lib/libbsp/bfin/eZKit533/preinstall.am index e25c8d7..3091c71 100644 --- a/c/src/lib/libbsp/bfin/eZKit533/preinstall.am +++ b/c/src/lib/libbsp/bfin/eZKit533/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/h8300/h8sim/preinstall.am b/c/src/lib/libbsp/h8300/h8sim/preinstall.am index bdd3a3e..347e43d 100644 --- a/c/src/lib/libbsp/h8300/h8sim/preinstall.am +++ b/c/src/lib/libbsp/h8300/h8sim/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/i386/pc386/preinstall.am b/c/src/lib/libbsp/i386/pc386/preinstall.am index 5b592f4..182f564 100644 --- a/c/src/lib/libbsp/i386/pc386/preinstall.am +++ b/c/src/lib/libbsp/i386/pc386/preinstall.am @@ -8,16 +8,16 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am b/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am index 981d677..5191609 100644 --- a/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am +++ b/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/lm32/milkymist/preinstall.am b/c/src/lib/libbsp/lm32/milkymist/preinstall.am index 0ee384d..e3d6f7e 100644 --- a/c/src/lib/libbsp/lm32/milkymist/preinstall.am +++ b/c/src/lib/libbsp/lm32/milkymist/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/m32c/m32cbsp/preinstall.am b/c/src/lib/libbsp/m32c/m32cbsp/preinstall.am index bdd3a3e..347e43d 100644 --- a/c/src/lib/libbsp/m32c/m32cbsp/preinstall.am +++ b/c/src/lib/libbsp/m32c/m32cbsp/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m32r/m32rsim/preinstall.am b/c/src/lib/libbsp/m32r/m32rsim/preinstall.am index 67ceb2b..5092254 100644 --- a/c/src/lib/libbsp/m32r/m32rsim/preinstall.am +++ b/c/src/lib/libbsp/m32r/m32rsim/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/av5282/preinstall.am b/c/src/lib/libbsp/m68k/av5282/preinstall.am index e3970ec..5092254 100644 --- a/c/src/lib/libbsp/m68k/av5282/preinstall.am +++ b/c/src/lib/libbsp/m68k/av5282/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/csb360/preinstall.am b/c/src/lib/libbsp/m68k/csb360/preinstall.am index 1c64e4f..647b809 100644 --- a/c/src/lib/libbsp/m68k/csb360/preinstall.am +++ b/c/src/lib/libbsp/m68k/csb360/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/gen68302/preinstall.am b/c/src/lib/libbsp/m68k/gen68302/preinstall.am index a63094d..9d1687e 100644 --- a/c/src/lib/libbsp/m68k/gen68302/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68302/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/gen68340/preinstall.am b/c/src/lib/libbsp/m68k/gen68340/preinstall.am index 298545c..b56f659 100644 --- a/c/src/lib/libbsp/m68k/gen68340/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68340/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/gen68360/preinstall.am b/c/src/lib/libbsp/m68k/gen68360/preinstall.am index 0a6c6d6..6f2e69f 100644 --- a/c/src/lib/libbsp/m68k/gen68360/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68360/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am b/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am index 331f0b5..505a3ad 100644 --- a/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am +++ b/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/idp/preinstall.am b/c/src/lib/libbsp/m68k/idp/preinstall.am index 73bd6bd..0a548ff 100644 --- a/c/src/lib/libbsp/m68k/idp/preinstall.am +++ b/c/src/lib/libbsp/m68k/idp/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mcf5206elite/preinstall.am b/c/src/lib/libbsp/m68k/mcf5206elite/preinstall.am index 5454d9d..5ccfba8 100644 --- a/c/src/lib/libbsp/m68k/mcf5206elite/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf5206elite/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mcf52235/preinstall.am b/c/src/lib/libbsp/m68k/mcf52235/preinstall.am index 67ceb2b..5092254 100644 --- a/c/src/lib/libbsp/m68k/mcf52235/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf52235/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mcf5225x/preinstall.am b/c/src/lib/libbsp/m68k/mcf5225x/preinstall.am index 73323b5..5092254 100644 --- a/c/src/lib/libbsp/m68k/mcf5225x/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf5225x/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mcf5329/preinstall.am b/c/src/lib/libbsp/m68k/mcf5329/preinstall.am index 24be79a..db2b32c 100644 --- a/c/src/lib/libbsp/m68k/mcf5329/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf5329/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mrm332/preinstall.am b/c/src/lib/libbsp/m68k/mrm332/preinstall.am index e8ddde2..aadebf7 100644 --- a/c/src/lib/libbsp/m68k/mrm332/preinstall.am +++ b/c/src/lib/libbsp/m68k/mrm332/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mvme136/preinstall.am b/c/src/lib/libbsp/m68k/mvme136/preinstall.am index 312b0f4..647b809 100644 --- a/c/src/lib/libbsp/m68k/mvme136/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme136/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mvme147/preinstall.am b/c/src/lib/libbsp/m68k/mvme147/preinstall.am index 312b0f4..647b809 100644 --- a/c/src/lib/libbsp/m68k/mvme147/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme147/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mvme147s/preinstall.am b/c/src/lib/libbsp/m68k/mvme147s/preinstall.am index 312b0f4..647b809 100644 --- a/c/src/lib/libbsp/m68k/mvme147s/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme147s/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mvme162/preinstall.am b/c/src/lib/libbsp/m68k/mvme162/preinstall.am index 59198f3..309fa5c 100644 --- a/c/src/lib/libbsp/m68k/mvme162/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme162/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/mvme167/preinstall.am b/c/src/lib/libbsp/m68k/mvme167/preinstall.am index ea1d67d..4681b20 100644 --- a/c/src/lib/libbsp/m68k/mvme167/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme167/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/ods68302/preinstall.am b/c/src/lib/libbsp/m68k/ods68302/preinstall.am index 7f0436f..7640e08 100644 --- a/c/src/lib/libbsp/m68k/ods68302/preinstall.am +++ b/c/src/lib/libbsp/m68k/ods68302/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/sim68000/preinstall.am b/c/src/lib/libbsp/m68k/sim68000/preinstall.am index bdd3a3e..347e43d 100644 --- a/c/src/lib/libbsp/m68k/sim68000/preinstall.am +++ b/c/src/lib/libbsp/m68k/sim68000/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/uC5282/preinstall.am b/c/src/lib/libbsp/m68k/uC5282/preinstall.am index e3970ec..5092254 100644 --- a/c/src/lib/libbsp/m68k/uC5282/preinstall.am +++ b/c/src/lib/libbsp/m68k/uC5282/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/mips/genmongoosev/preinstall.am b/c/src/lib/libbsp/mips/genmongoosev/preinstall.am index a6505c0..f11c87a 100644 --- a/c/src/lib/libbsp/mips/genmongoosev/preinstall.am +++ b/c/src/lib/libbsp/mips/genmongoosev/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/mips/hurricane/preinstall.am b/c/src/lib/libbsp/mips/hurricane/preinstall.am index ae6cd49..7755bef 100644 --- a/c/src/lib/libbsp/mips/hurricane/preinstall.am +++ b/c/src/lib/libbsp/mips/hurricane/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/jmr3904/preinstall.am b/c/src/lib/libbsp/mips/jmr3904/preinstall.am index 244a228..d05c802 100644 --- a/c/src/lib/libbsp/mips/jmr3904/preinstall.am +++ b/c/src/lib/libbsp/mips/jmr3904/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/malta/preinstall.am b/c/src/lib/libbsp/mips/malta/preinstall.am index 091e11b..fc103c5 100644 --- a/c/src/lib/libbsp/mips/malta/preinstall.am +++ b/c/src/lib/libbsp/mips/malta/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/mips/rbtx4925/preinstall.am b/c/src/lib/libbsp/mips/rbtx4925/preinstall.am index b2d7806..de464aa 100644 --- a/c/src/lib/libbsp/mips/rbtx4925/preinstall.am +++ b/c/src/lib/libbsp/mips/rbtx4925/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/rbtx4938/preinstall.am b/c/src/lib/libbsp/mips/rbtx4938/preinstall.am index 11efecd..de464aa 100644 --- a/c/src/lib/libbsp/mips/rbtx4938/preinstall.am +++ b/c/src/lib/libbsp/mips/rbtx4938/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am b/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am index 87f904e..eaeeefe 100644 --- a/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am +++ b/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am b/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am index a6a238d..72d079a 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am +++ b/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/beatnik/preinstall.am b/c/src/lib/libbsp/powerpc/beatnik/preinstall.am index 10efa55..b3093ab 100644 --- a/c/src/lib/libbsp/powerpc/beatnik/preinstall.am +++ b/c/src/lib/libbsp/powerpc/beatnik/preinstall.am @@ -5,11 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) @@ -18,6 +13,11 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/gen5200/preinstall.am b/c/src/lib/libbsp/powerpc/gen5200/preinstall.am index 9f5d146..75a41ea 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/preinstall.am +++ b/c/src/lib/libbsp/powerpc/gen5200/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am index ab9dd65..8b06af2 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am +++ b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/haleakala/preinstall.am b/c/src/lib/libbsp/powerpc/haleakala/preinstall.am index 8f70554..0e65b26 100644 --- a/c/src/lib/libbsp/powerpc/haleakala/preinstall.am +++ b/c/src/lib/libbsp/powerpc/haleakala/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am b/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am index aa78beb..dd192b0 100644 --- a/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am b/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am index 6edf483..5865adf 100644 --- a/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am b/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am index a4017e8..796f977 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/psim/preinstall.am b/c/src/lib/libbsp/powerpc/psim/preinstall.am index ecf4a2b..9a133c4 100644 --- a/c/src/lib/libbsp/powerpc/psim/preinstall.am +++ b/c/src/lib/libbsp/powerpc/psim/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am b/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am index 4fa463d..e5e2ab2 100644 --- a/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am +++ b/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/qoriq/preinstall.am b/c/src/lib/libbsp/powerpc/qoriq/preinstall.am index 8adee61..0843a7a 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/preinstall.am +++ b/c/src/lib/libbsp/powerpc/qoriq/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/score603e/preinstall.am b/c/src/lib/libbsp/powerpc/score603e/preinstall.am index 036f227..2756fa1 100644 --- a/c/src/lib/libbsp/powerpc/score603e/preinstall.am +++ b/c/src/lib/libbsp/powerpc/score603e/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/ss555/preinstall.am b/c/src/lib/libbsp/powerpc/ss555/preinstall.am index 6d7cb01..5eb0a1e 100644 --- a/c/src/lib/libbsp/powerpc/ss555/preinstall.am +++ b/c/src/lib/libbsp/powerpc/ss555/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am b/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am index d3bec9c..8a404f8 100644 --- a/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am +++ b/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/preinstall.am b/c/src/lib/libbsp/powerpc/tqm8xx/preinstall.am index 7960684..cfe6ebd 100644 --- a/c/src/lib/libbsp/powerpc/tqm8xx/preinstall.am +++ b/c/src/lib/libbsp/powerpc/tqm8xx/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/virtex/preinstall.am b/c/src/lib/libbsp/powerpc/virtex/preinstall.am index e8b4481..ed98676 100644 --- a/c/src/lib/libbsp/powerpc/virtex/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/virtex4/preinstall.am b/c/src/lib/libbsp/powerpc/virtex4/preinstall.am index f507474..f7a73c4 100644 --- a/c/src/lib/libbsp/powerpc/virtex4/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex4/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/virtex5/preinstall.am b/c/src/lib/libbsp/powerpc/virtex5/preinstall.am index b0155fc..f7a73c4 100644 --- a/c/src/lib/libbsp/powerpc/virtex5/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex5/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/sh/gensh4/preinstall.am b/c/src/lib/libbsp/sh/gensh4/preinstall.am index b7d09e5..8dd0653 100644 --- a/c/src/lib/libbsp/sh/gensh4/preinstall.am +++ b/c/src/lib/libbsp/sh/gensh4/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sh/shsim/preinstall.am b/c/src/lib/libbsp/sh/shsim/preinstall.am index 202e051..fa84c38 100644 --- a/c/src/lib/libbsp/sh/shsim/preinstall.am +++ b/c/src/lib/libbsp/sh/shsim/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/sparc/erc32/preinstall.am b/c/src/lib/libbsp/sparc/erc32/preinstall.am index 7bae1e1..00e9487 100644 --- a/c/src/lib/libbsp/sparc/erc32/preinstall.am +++ b/c/src/lib/libbsp/sparc/erc32/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/sparc/leon3/preinstall.am b/c/src/lib/libbsp/sparc/leon3/preinstall.am index 443400d..d7b28e4 100644 --- a/c/src/lib/libbsp/sparc/leon3/preinstall.am +++ b/c/src/lib/libbsp/sparc/leon3/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sparc64/niagara/preinstall.am b/c/src/lib/libbsp/sparc64/niagara/preinstall.am index 722ccdd..7725e49 100644 --- a/c/src/lib/libbsp/sparc64/niagara/preinstall.am +++ b/c/src/lib/libbsp/sparc64/niagara/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sparc64/usiii/preinstall.am b/c/src/lib/libbsp/sparc64/usiii/preinstall.am index 2122b19..3546fc4 100644 --- a/c/src/lib/libbsp/sparc64/usiii/preinstall.am +++ b/c/src/lib/libbsp/sparc64/usiii/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/v850/gdbv850sim/preinstall.am b/c/src/lib/libbsp/v850/gdbv850sim/preinstall.am index 1fc9abe..38d42ac 100644 --- a/c/src/lib/libbsp/v850/gdbv850sim/preinstall.am +++ b/c/src/lib/libbsp/v850/gdbv850sim/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libcpu/arm/preinstall.am b/c/src/lib/libcpu/arm/preinstall.am index c756d19..751a085 100644 --- a/c/src/lib/libcpu/arm/preinstall.am +++ b/c/src/lib/libcpu/arm/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/bfin/preinstall.am b/c/src/lib/libcpu/bfin/preinstall.am index 36f6ca9..a8b2fa9 100644 --- a/c/src/lib/libcpu/bfin/preinstall.am +++ b/c/src/lib/libcpu/bfin/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/lm32/preinstall.am b/c/src/lib/libcpu/lm32/preinstall.am index 9667d9c..0516c2c 100644 --- a/c/src/lib/libcpu/lm32/preinstall.am +++ b/c/src/lib/libcpu/lm32/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - if shared $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu diff --git a/c/src/lib/libcpu/mips/preinstall.am b/c/src/lib/libcpu/mips/preinstall.am index 0f5a379..4a83d60 100644 --- a/c/src/lib/libcpu/mips/preinstall.am +++ b/c/src/lib/libcpu/mips/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) diff --git a/c/src/lib/libcpu/powerpc/preinstall.am b/c/src/lib/libcpu/powerpc/preinstall.am index 33d79d9..129855e 100644 --- a/c/src/lib/libcpu/powerpc/preinstall.am +++ b/c/src/lib/libcpu/powerpc/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/sparc64/preinstall.am b/c/src/lib/libcpu/sparc64/preinstall.am index ab9d46e..83b9153 100644 --- a/c/src/lib/libcpu/sparc64/preinstall.am +++ b/c/src/lib/libcpu/sparc64/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - if shared $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu diff --git a/c/src/libchip/preinstall.am b/c/src/libchip/preinstall.am index 452818f..2f95e6c 100644 --- a/c/src/libchip/preinstall.am +++ b/c/src/libchip/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/librtems++/preinstall.am b/c/src/librtems++/preinstall.am index 55d3cbf..2111689 100644 --- a/c/src/librtems++/preinstall.am +++ b/c/src/librtems++/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/cpukit/ftpd/preinstall.am b/cpukit/ftpd/preinstall.am index abeefb3..85ae87d 100644 --- a/cpukit/ftpd/preinstall.am +++ b/cpukit/ftpd/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/cpukit/libfs/src/nfsclient/preinstall.am b/cpukit/libfs/src/nfsclient/preinstall.am index c65f7f7..593fc03 100644 --- a/cpukit/libfs/src/nfsclient/preinstall.am +++ b/cpukit/libfs/src/nfsclient/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/posix/preinstall.am b/cpukit/posix/preinstall.am index beb6d58..6e3f2a2 100644 --- a/cpukit/posix/preinstall.am +++ b/cpukit/posix/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/pppd/preinstall.am b/cpukit/pppd/preinstall.am index 9479a04..19f4bc1 100644 --- a/cpukit/pppd/preinstall.am +++ b/cpukit/pppd/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/preinstall.am b/cpukit/preinstall.am index b2f88a9..70923f0 100644 --- a/cpukit/preinstall.am +++ b/cpukit/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/sapi/preinstall.am b/cpukit/sapi/preinstall.am index 57c5b97..40eafdd 100644 --- a/cpukit/sapi/preinstall.am +++ b/cpukit/sapi/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/score/cpu/bfin/preinstall.am b/cpukit/score/cpu/bfin/preinstall.am index c5f501c..a16a047 100644 --- a/cpukit/score/cpu/bfin/preinstall.am +++ b/cpukit/score/cpu/bfin/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/h8300/preinstall.am b/cpukit/score/cpu/h8300/preinstall.am index 0f89b1c..f3c1681 100644 --- a/cpukit/score/cpu/h8300/preinstall.am +++ b/cpukit/score/cpu/h8300/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/i386/preinstall.am b/cpukit/score/cpu/i386/preinstall.am index 2d29558..060176b 100644 --- a/cpukit/score/cpu/i386/preinstall.am +++ b/cpukit/score/cpu/i386/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/m32r/preinstall.am b/cpukit/score/cpu/m32r/preinstall.am index 044514a..3d76b74 100644 --- a/cpukit/score/cpu/m32r/preinstall.am +++ b/cpukit/score/cpu/m32r/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/score/cpu/mips/preinstall.am b/cpukit/score/cpu/mips/preinstall.am index bca004a..2385f8c 100644 --- a/cpukit/score/cpu/mips/preinstall.am +++ b/cpukit/score/cpu/mips/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/powerpc/preinstall.am b/cpukit/score/cpu/powerpc/preinstall.am index ccc4cbe..3293498 100644 --- a/cpukit/score/cpu/powerpc/preinstall.am +++ b/cpukit/score/cpu/powerpc/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/sparc64/preinstall.am b/cpukit/score/cpu/sparc64/preinstall.am index 3f53e73..00af891 100644 --- a/cpukit/score/cpu/sparc64/preinstall.am +++ b/cpukit/score/cpu/sparc64/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/preinstall.am b/cpukit/score/preinstall.am index a1e4583..891c21e 100644 --- a/cpukit/score/preinstall.am +++ b/cpukit/score/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/zlib/preinstall.am b/cpukit/zlib/preinstall.am index 27b3248..7eb8f7b 100644 --- a/cpukit/zlib/preinstall.am +++ b/cpukit/zlib/preinstall.am @@ -5,11 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) @@ -18,6 +13,11 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) From chrisj at rtems.org Sat Aug 30 22:58:52 2014 From: chrisj at rtems.org (Chris Johns) Date: Sat, 30 Aug 2014 17:58:52 -0500 Subject: [rtems-source-builder commit] sb: Add support for the standard git protocols for the %source command. Message-ID: <20140830225852.B8B4E7006A2@git.rtems.org> Module: rtems-source-builder Branch: master Commit: d790668e390357c4c5fca82704806b9453151a42 Changeset: http://git.rtems.org/rtems-source-builder/commit/?id=d790668e390357c4c5fca82704806b9453151a42 Author: Chris Johns Date: Fri Aug 29 13:14:14 2014 +1000 sb: Add support for the standard git protocols for the %source command. The source selector 'git://' now supports a protocol option that lets you set the specific protocol git is to use to access a remote repository. --- doc/source-builder.txt | 6 ++++++ source-builder/sb/download.py | 26 ++++++++++++++++++++++++-- source-builder/sb/git.py | 5 ++++- 3 files changed, 34 insertions(+), 3 deletions(-) diff --git a/doc/source-builder.txt b/doc/source-builder.txt index 3f80503..1d9a474 100644 --- a/doc/source-builder.txt +++ b/doc/source-builder.txt @@ -1413,6 +1413,8 @@ the repository via the URL by appending options and arguments to the GIT path. The options are delimited by `?` and option arguments are delimited from the options with `=`. The options are: +`protocol`:: Use a specific protocol. The supported values are _ssh_, _git_, +_http_, _https_, _ftp_, _ftps_, _rsync_, and _none_. `branch`:: Checkout the specified branch. `pull`:: Perform a pull to update the repository. `fetch`:: Perform a fetch to get any remote updates. @@ -1428,6 +1430,10 @@ a hard reset. You can select specific branches and apply patches. The repository is cleaned up before each build to avoid various version control errors that can arise. +The protocol option lets you set a specific protocol. The 'git://' prefix used +by the RSB to select a git repository can be removed using _none_ or replaced +with one of the standard git protcols. + CVS ^^^ diff --git a/source-builder/sb/download.py b/source-builder/sb/download.py index fdc834a..dc1def6 100644 --- a/source-builder/sb/download.py +++ b/source-builder/sb/download.py @@ -201,7 +201,7 @@ def parse_url(url, pathkey, config, opts): source['url'] = url colon = url.find(':') if url[colon + 1:colon + 3] != '//': - raise error.general('malforned URL: %s' % (url)) + raise error.general('malforned URL (no protocol prefix): %s' % (url)) source['path'] = url[:colon + 3] + path.dirname(url[colon + 3:]) source['file'] = path.basename(url) source['name'], source['ext'] = path.splitext(source['file']) @@ -310,9 +310,27 @@ def _http_downloader(url, local, config, opts): return not failed def _git_downloader(url, local, config, opts): + repo = git.repo(local, opts, config.macros) rlp = os.path.relpath(path.host(local)) us = url.split('?') - repo = git.repo(local, opts, config.macros) + # + # Handle the various git protocols. + # + # remove 'git' from 'git://xxxx/xxxx?protocol=...' + # + url_base = us[0][len('git'):] + for a in us[1:]: + _as = a.split('=') + if _as[0] == 'protocol': + if len(_as) != 2: + raise error.general('invalid git protocol option: %s' % (_as)) + if _as[1] == 'none': + # remove the rest of the protocol header leaving nothing. + us[0] = url_base[len('://'):] + else: + if _as[1] not in ['ssh', 'git', 'http', 'https', 'ftp', 'ftps', 'rsync']: + raise error.general('unknown git protocol: %s' % (_as[1])) + us[0] = _as[1] + url_base if not repo.valid(): log.notice('git: clone: %s -> %s' % (us[0], rlp)) if not opts.dry_run(): @@ -350,6 +368,10 @@ def _git_downloader(url, local, config, opts): log.notice('git: reset: %s' % (us[0])) if not opts.dry_run(): repo.reset(arg) + elif _as[0] == 'protocol': + pass + else: + raise error.general('invalid git option: %s' % (_as)) return True def _cvs_downloader(url, local, config, opts): diff --git a/source-builder/sb/git.py b/source-builder/sb/git.py index 093c443..d115845 100644 --- a/source-builder/sb/git.py +++ b/source-builder/sb/git.py @@ -57,7 +57,10 @@ class repo: self.macros = opts.defaults else: self.macros = macros - self.git = self.macros.expand('%{__git}') + if self.macros is None: + self.git = 'git' + else: + self.git = self.macros.expand('%{__git}') def git_version(self): ec, output = self._run(['--version'], True) From sebh at rtems.org Mon Aug 11 06:11:34 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 11 Aug 2014 06:11:34 -0000 Subject: [rtems commit] bsp/altera-cyclone-v: Add a simple I2C driver. Message-ID: <20140811060245.A39DE70084A@git.rtems.org> Module: rtems Branch: master Commit: 3f9cd87d76740db4efdd28d3112a3cc8dce3dfc4 Changeset: http://git.rtems.org/rtems/commit/?id=3f9cd87d76740db4efdd28d3112a3cc8dce3dfc4 Author: Christian Mauderer Date: Mon Jul 14 16:33:52 2014 +0200 bsp/altera-cyclone-v: Add a simple I2C driver. --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 7 + c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac | 8 + .../libbsp/arm/altera-cyclone-v/hwlib/README.txt | 41 +- .../arm/altera-cyclone-v/hwlib/include/alt_i2c.h | 2024 +++++++ .../altera-cyclone-v/hwlib/include/socal/alt_i2c.h | 5940 ++++++++++++++++++++ .../arm/altera-cyclone-v/hwlib/src/hwmgr/alt_i2c.c | 2004 +++++++ .../arm/altera-cyclone-v/i2c/i2cdrv-config.c | 24 + .../arm/altera-cyclone-v/i2c/i2cdrv-config.h | 37 + c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv.c | 215 + .../libbsp/arm/altera-cyclone-v/include/i2cdrv.h | 76 + .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 20 +- 11 files changed, 10389 insertions(+), 7 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index e92e728..01b0272 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -56,6 +56,7 @@ include_bsp_HEADERS += hwlib/include/alt_clock_group.h include_bsp_HEADERS += hwlib/include/alt_clock_manager.h include_bsp_HEADERS += hwlib/include/alt_generalpurpose_io.h include_bsp_HEADERS += hwlib/include/alt_hwlibs_ver.h +include_bsp_HEADERS += hwlib/include/alt_i2c.h include_bsp_HEADERS += hwlib/include/alt_interrupt_common.h include_bsp_HEADERS += hwlib/include/alt_mpu_registers.h include_bsp_HEADERS += hwlib/include/alt_reset_manager.h @@ -125,6 +126,7 @@ CFLAGS += -Wno-missing-prototypes libbsp_a_SOURCES += hwlib/src/hwmgr/alt_address_space.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_clock_manager.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_generalpurpose_io.c +libbsp_a_SOURCES += hwlib/src/hwmgr/alt_i2c.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_reset_manager.c #The following Altera hwlib source files have been left out because so far #they are not required: @@ -193,6 +195,11 @@ libbsp_a_SOURCES += console/console-config.c libbsp_a_SOURCES += ../../shared/clockdrv_shell.h libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c +# I2C +libbsp_a_SOURCES += i2c/i2cdrv.c +libbsp_a_SOURCES += i2c/i2cdrv-config.c +include_bsp_HEADERS += include/i2cdrv.h + # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac b/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac index 561a192..bad9a2a 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac @@ -46,6 +46,14 @@ RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_UART_1],[configuration for UART 1]) RTEMS_BSPOPTS_SET([CYCLONE_V_UART_BAUD],[*],[115200U]) RTEMS_BSPOPTS_HELP([CYCLONE_V_UART_BAUD],[baud for UARTs]) +RTEMS_BSPOPTS_SET([CYCLONE_V_NO_I2C],[*],[1]) +RTEMS_BSPOPTS_HELP([CYCLONE_V_NO_I2C], +[Number of configured I2C buses. Note that each bus has to be configured in an +apropriate i2cdrv_config array.]) + +RTEMS_BSPOPTS_SET([CYCLONE_V_I2C0_SPEED],[*],[100000]) +RTEMS_BSPOPTS_HELP([CYCLONE_V_I2C0_SPEED],[speed for I2C0 in HZ]) + RTEMS_CHECK_SMP AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"]) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt index f19d387..154b343 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt @@ -10,4 +10,43 @@ The hwlib directory contains only those files from Alteras hwlib which are required by the BSP (the whole hwlib was considered too big). The directory structure within the hwlib directory is equivalent to Alteras hwlib directory structure. For easy maintenance only whole files have been -left out. \ No newline at end of file +left out. + +Altera provides the hwlib with their SoC Embedded Design Suite (EDS). + +HWLIB Version: +-------------- +The files have been taken from the following hwlib versions: + +|======================================== +| Version | File +| | +| 13.0SP1 | include/alt_address_space.h +| 13.0SP1 | include/alt_clock_group.h +| 13.0SP1 | include/alt_clock_manager.h +| 13.0SP1 | include/alt_generalpurpose_io.h +| 13.0SP1 | include/alt_hwlibs_ver.h +| 13.1 | include/alt_i2c.h +| 13.0SP1 | include/alt_interrupt_common.h +| 13.0SP1 | include/alt_mpu_registers.h +| 13.0SP1 | include/alt_reset_manager.h +| 13.0SP1 | include/hwlib.h +| 13.0SP1 | include/socal/alt_clkmgr.h +| 13.0SP1 | include/socal/alt_gpio.h +| 13.1 | include/socal/alt_i2c.h +| 13.0SP1 | include/socal/alt_l3.h +| 13.0SP1 | include/socal/alt_rstmgr.h +| 13.0SP1 | include/socal/alt_sdr.h +| 13.0SP1 | include/socal/alt_sysmgr.h +| 13.0SP1 | include/socal/alt_uart.h +| 13.0SP1 | include/socal/hps.h +| 13.0SP1 | include/socal/socal.h +| 13.0SP1 | src/hwmgr/alt_address_space.c +| 13.0SP1 | src/hwmgr/alt_clock_manager.c +| 13.0SP1 | src/hwmgr/alt_generalpurpose_io.c +| 13.1 | src/hwmgr/alt_i2c.c +| 13.0SP1 | src/hwmgr/alt_reset_manager.c +|======================================== + +hwlib 13.0SP1 is from SoC EDS 13.0.1.232 +hwlib 13.1 is from SoC EDS 14.0.0.200 diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_i2c.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_i2c.h new file mode 100644 index 0000000..7af55cf --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_i2c.h @@ -0,0 +1,2024 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/*! \file + * Altera - I2C Controller API + */ + +#ifndef __ALT_I2C_H__ +#define __ALT_I2C_H__ + +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "socal/alt_i2c.h" +#include "socal/alt_rstmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C I2C Controller API + * + * This module defines an API for configuring and managing the HPS I2C controllers. + * + * The I2C controller provides support for a communication link between integrated + * circuits on a board. It is a simple two-wire bus which consists of a serial + * data line (SDA) and a serial clock (SCL) for use in applications such as + * temperature sensors and voltage level translators to EEPROMs, A/D and D/A + * converters, CODECs, and many types of microprocessors. + * + * The Hard Processor System (HPS) provides four I2C controllers to enable system + * software to communicate serially with I2C buses. Each I2C controller can + * operate in master or slave mode, and support standard mode of up to 100 + * kilobits per second (Kbps) or fast mode of up to 400 Kbps. These I2C + * controllers are instances of the Synopsys DesignWare APB I2C (DW_apb_i2c) + * controller. + * + * NOTE: Each I2C controller must be programmed to operate in either master or + * slave mode only. Operating as a master and slave simultaneously is not + * supported. + * + * Features of the I2C Controller: + * * Support both 100 KBps and 400 KBps modes + * * One of the following I2C operations: master or slave + * * Support both 7-bit and 10-bit addressing modes + * * Mixed read and write combined-format transactions + * * Bulk transmit mode + * * DMA handshaking interface + * + * For a complete details on the configuration and operation of I2C controller, + * consult the following references: + * * Cyclone V Device Handbook Volume 3: Hard Processor System Technical + * Reference Manual, Chapter 20. I2C Controller (cv_54020-1.2) + * * Synopsys DesignWare DW_apb_i2c Databook DW_apb_i2c, Version 1.15a + * * The I2C-Bus Specification Version 2.1 + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the operational state of I2C by + * transfer operation. + */ +typedef enum ALT_I2C_TRANSFER_TYPE_e +{ + ALT_I2C_TRANSFER_NONE = 0, /*!< No transfer operation */ + ALT_I2C_TRANSFER_START = 1, /*!< Start detect */ + ALT_I2C_TRANSFER_COMPLETE = 2, /*!< All operations done */ + ALT_I2C_TRANSFER_READ = 3, /*!< Read operation is active */ + ALT_I2C_TRANSFER_WRITE = 4, /*!< Write operation is active */ +} +ALT_I2C_TRANSFER_TYPE_t; + + +/* + * A pointer or handle to the I2C controller device instance. The ALT_I2C_DEV_t is + * initialized by a call to alt_i2c_init() and subsequently used by the other I2C + * controller API functions as a reference to a specific device. + * + * \internal + * ALT_I2C_DEV_t may be a struct or reference to an opaque data + * structure. Whatever "internal" type is suited to the needs of the + * implementation. + * \endinternal + */ +typedef struct ALT_I2C_DEV_s +{ + void * location; /*!< HPS address of I2C instance. */ + alt_freq_t clock_freq; /*!< Input clock frequency. */ + uint32_t last_target; /*!< Last issued target address. */ +} +ALT_I2C_DEV_t; + +/*! + * This type enumerates the HPS I2C controller instances. + */ +typedef enum ALT_I2C_CTLR_e +{ + ALT_I2C_I2C0 = (int)ALT_I2C0_OFST, /*!< I2C0 instance. */ + ALT_I2C_I2C1 = (int)ALT_I2C1_OFST, /*!< I2C1 instance. */ + ALT_I2C_I2C2 = (int)ALT_I2C2_OFST, /*!< I2C2 instance. */ + ALT_I2C_I2C3 = (int)ALT_I2C3_OFST, /*!< I2C3 instance. */ +} ALT_I2C_CTLR_t; + +/*! + * This type enumerates the modes that the I2C controller may operate in. + * + * NOTE: Each I2C controller must be programmed to operate in either master or + * slave mode only. Operating as a master and slave simultaneously is not + * supported. + */ +typedef enum ALT_I2C_MODE_e +{ + ALT_I2C_MODE_SLAVE = ALT_I2C_CON_MST_MOD_E_DIS, /*!< Slave Mode */ + ALT_I2C_MODE_MASTER = ALT_I2C_CON_MST_MOD_E_EN /*!< Master Mode */ +} ALT_I2C_MODE_t; + +/*! + * This type enumerates the I2C controller operational speed modes. + * + * The I2C controller can operate in standard mode (with data rates 0 to 100 Kbps) + * or fast mode (with data rates less than or equal to 400 Kbps). Additionally, + * fast mode devices are downward compatible. For instance, fast mode devices can + * communicate with standard mode devices in 0 to 100 Kbps I2C bus + * system. However, standard mode devices are not upward compatible and should not + * be incorporated in a fast-mode I2C bus system as they cannot follow the higher + * transfer rate and therefore unpredictable states would occur. + * + * This setting is relevant only if one is operating the I2C in master mode. + */ +typedef enum ALT_I2C_SPEED_e +{ + ALT_I2C_SPEED_STANDARD = ALT_I2C_CON_SPEED_E_STANDARD, + /*!< Standard mode (0 to 100 Kbps) */ + ALT_I2C_SPEED_FAST = ALT_I2C_CON_SPEED_E_FAST + /*!< Fast mode (<= 400 Kbps) */ +} ALT_I2C_SPEED_t; + +/*! + * This type enumerates the two addressing modes formats supported by the I2C + * controller. + * + * The I2C controller does not support mixed address format - that is, a 7-bit + * address transaction followed by a 10-bit address transaction or vice versa - + * combined format transactions. + */ +typedef enum ALT_I2C_ADDR_MODE_e +{ + ALT_I2C_ADDR_MODE_7_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START7, + /*!< 7-Bit Address Format */ + ALT_I2C_ADDR_MODE_10_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 + /*!< 10-Bit Address Format */ +} ALT_I2C_ADDR_MODE_t; + +/*! + * This type enumerates interrupt status conditions for the I2C controller. + */ +typedef enum ALT_I2C_STATUS_e +{ + ALT_I2C_STATUS_RX_UNDER = 1UL << 0, + /*!< Set if the processor attempts to read the + * receive buffer when it is empty. If the I2C + * controller is disabled, this status keeps + * maintains its state until the master or slave + * state machines go into idle, then this + * interrupt is cleared. + */ + ALT_I2C_STATUS_RX_OVER = 1UL << 1, + /*!< Set if the receive buffer is completely + * filled to capacity and an additional byte is + * received from an external I2C device. The I2C + * controller acknowledges this, but any data + * bytes received after the FIFO is full are + * discarded. If the I2C controller is disabled, + * this status maintains its statue until the + * master or slave state machines go into idle, + * then this interrupt is cleared. + */ + ALT_I2C_STATUS_RX_FULL = 1UL << 2, + /*!< Set when the receive buffer reaches or goes + * above the RX_TL threshold. It is + * automatically cleared by hardware when buffer + * level goes below the threshold. If the I2C + * controller is disabled, the RX FIFO is + * flushed and held in reset; therefore the RX + * FIFO is not full. So this bit is cleared once + * the I2C controller is disabled, regardless of + * the activity that continues. + */ + ALT_I2C_STATUS_TX_OVER = 1UL << 3, + /*!< Set during transmit if the transmit buffer is + * filled to capacity and the processor attempts + * to issue another I2C command. When the I2C + * controller is disabled, this bit maintains + * its state until the master or slave state + * machines go into idle, then this interrupt is + * cleared. + */ + ALT_I2C_STATUS_TX_EMPTY = 1UL << 4, + /*!< This bit is set to 1 when the transmit buffer + * is at or below the configured threshold + * value. It is automatically cleared by + * hardware when the buffer level goes above the + * threshold. When the I2C controller is + * disabled, the TX FIFO is flushed and held in + * reset. The TX FIFO appears as if it has no + * data in it, so this bit is set to 1, provided + * there is activity in the master or slave + * state machines. When there is no longer + * activity, then this bit is set to 0. + * + */ + ALT_I2C_STATUS_RD_REQ = 1UL << 5, + /*!< This bit is set to 1 when I2C is acting as a + * slave and another I2C master is attempting to + * read data from the I2C. The I2C holds the bus + * in a wait state until this interrupt is + * serviced, which means that the slave has been + * addressed by a remote master that is asking + * for data to be transferred. The processor + * must respond to this interrupt and then write + * the requested data. This bit is set to 0 just + * after the processor by calling + * alt_i2c_int_clear() with + * ALT_I2C_STATUS_RD_REQ in the mask.. + */ + ALT_I2C_STATUS_TX_ABORT = 1UL << 6, + /*!< This bit indicates if I2C, as an I2C + * transmitter, is unable to complete the + * intended actions on the contents of the + * transmit FIFO. This situation can occur both + * as an I2C master or an I2C slave, and is + * referred to as a 'transmit abort'. When this + * bit is set to 1, the IC_TX_ABRT_SOURCE + * register indicates the reason why the + * transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX + * FIFO whenever this bit is set. The TX FIFO + * remains in this flushed state until the + * register alt_i2c_int_clear() with + * ALT_I2C_STATUS_TX_ABORT in the mask is + * called. Once this happens, the TX FIFO is + * then ready to accept more data bytes from the + * APB interface. + */ + ALT_I2C_STATUS_RX_DONE = 1UL << 7, + /*!< When the I2C is acting as a + * slave-transmitter, this bit is set to 1 if + * the master does not acknowledge a transmitted + * byte. This occurs on the last byte of the + * transmission, indicating that the + * transmission is done. + */ + ALT_I2C_STATUS_ACTIVITY = 1UL << 8, + /*!< This bit captures I2C activity and stays set + * until it is cleared. There are four ways to + * clear it: + * * Disabling the I2C controller + * * Calling alt_i2c_int_clear() with + * ALT_I2C_STATUS_ACTIVITY in the mask. + * * Calling alt_i2c_int_clear() with + * ALT_I2C_STATUS_ALL in the mask. + * * System reset + * + * Once this bit is set, it stays set unless one + * of the four methods is used to clear it. Even + * if the I2C module is idle, this bit remains + * set until cleared, indicating that there was + * activity on the bus. + */ + ALT_I2C_STATUS_STOP_DET = 1UL << 9, + /*!< Indicates whether a STOP condition has + * occurred on the I2C interface regardless of + * whether I2C is operating in slave or master + * mode. + */ + ALT_I2C_STATUS_START_DET = 1UL << 10, + /*!< Indicates whether a START or RESTART + * condition has occurred on the I2C interface + * regardless of whether I2C is operating in + * slave or master mode. + */ + ALT_I2C_STATUS_INT_CALL = 1UL << 11, + /*!< Set only when a General Call address is + * received and it is acknowledged. It stays set + * until it is cleared either by disabling I2C + * or when alt_i2c_int_clear() with + * ALT_I2C_STATUS_CALL in the mask is + * called. I2C stores the received data in the + * Rx buffer. + */ + ALT_I2C_STATUS_INT_ALL = 0xFFF, + /*!< All Combined and Individual Interrupts. This + * enumeration value can be used to clear, + * disable, and enable the combined interrupt + * and all individual interrupt status + * conditions. As a side effect, when passed to + * alt_i2c_int_clear(), clears the source causes + * (\ref ALT_I2C_TX_ABORT_CAUSE_t) of the + * ALT_I2C_STATUS_TX_ABORT condition. + */ +} ALT_I2C_STATUS_t; + +/*! + * This type enumerates the source causes of a ALT_I2C_STATUS_TX_ABORT condition. + * + * The active ALT_I2C_TX_ABORT_CAUSE_t source conditions are cleared when + * alt_i2c_int_clear() with is called ALT_I2C_STATUS_TX_ABORT in the mask or + * alt_i2c_int_clear() is called with ALT_I2C_STATUS_ALL in the mask. + * + * \internal + * Discuss special handling of abrt_sbyte_norstrt TX_ABRT source required in ???() function. + * \endinternal + */ +typedef enum ALT_I2C_TX_ABORT_CAUSE_e +{ + ALT_I2C_TX_ABORT_CAUSE_7B_ADDR_NOACK = 1UL << 0, + /*!< Master Abort 7 Bit Address - If set (1), + * Master is in 7-bit addressing mode and the + * address sent was not acknowledged by any + * slave. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_10ADDR1_NOACK = 1UL << 1, + /*!< Master Abort 10 Bit Address Byte 1 - If set + * (1), Master is in 10-bit address mode and the + * first 10-bit address byte was not + * acknowledged by any slave. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_10ADDR2_NOACK = 1UL << 2, + /*!< Master Abort 10 Bit Address Byte 2 - If set + * (1), Master is in 10-bit address mode and the + * second address byte of the 10-bit address was + * not acknowledged by any slave + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_TXDATA_NOACK = 1UL << 3, + /*!< Master Abort TX NOACK Bit - If set (1), + * Master has received an acknowledgement for + * the address, but when it sent data byte(s) + * following the address, it did not receive an + * acknowledge from the remote slave(s). This is + * a master-mode only bit. + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_GCALL_NOACK = 1UL << 4, + /*!< Master Abort GC Noack Bit - If set (1), I2C + * controller in master mode sent a General Call + * and no slave on the bus acknowledged the + * General Call. + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_GCALL_RD = 1UL << 5, + /*!< Master Abort GC Read Bit - If set (1), I2C + * controller in master mode sent a General Call + * but the user programmed the byte following + * the General Call to be a read from the bus + * (IC_DATA_CMD[9] is set to 1). + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_HS_ACKDET = 1UL << 6, + /*!< Master HS MC Ack - If set (1), Master is in + * High Speed mode and the High Speed Master + * code was acknowledged (wrong behavior). + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_SBYTE_ACKDET = 1UL << 7, + /*!< Master Abort START Byte - If set (1), Master + * has sent a START Byte and the START Byte was + * acknowledged (wrong behavior). + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_HS_NORSTRT = 1UL << 8, + /*!< Master HS Restart Disabled - If set (1), the + * restart is disabled (IC_RESTART_EN bit + * (IC_CON[5]) = 0) and the user is trying to + * use the master to transfer data in High Speed + * mode. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_SBYTE_NORSTRT = 1UL << 9, + /*!< Master Abort START No Restart - To clear, the + * source of the ABRT_SBYTE_NORSTRT must be + * fixed first; restart must be enabled + * (IC_CON[5]=1), the SPECIAL bit must be + * cleared (IC_TAR[11]), or the GC_OR_START bit + * must be cleared (IC_TAR[10]). Once the source + * of the ABRT_SBYTE_NORSTRT is fixed, then this + * bit can be cleared in the same manner as + * other bits in this register. If the source of + * the ABRT_SBYTE_NORSTRT is not fixed before + * attempting to clear this bit, bit 9 clears + * for one cycle and then gets re-asserted. + * + * If set (1), the restart is disabled + * (IC_RESTART_EN bit (IC_CON[5]) = 0) and the + * user is trying to send a START Byte. + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_10B_RD_NORSTRT = 1UL << 10, + /*!< Master Abort 10 Bit No Restart - If set (1), + * the restart is disabled (IC_RESTART_EN bit + * (IC_CON[5]) = 0) and the master sends a read + * command in 10-bit addressing mode. + * + * Role of I2C: Master Receiver. + */ + ALT_I2C_TX_ABORT_CAUSE_MST_DIS = 1UL << 11, + /*!< Master Operation with Master Disabled - If set + * (1), user tries to initiate a Master + * operation with the Master mode disabled. + * + * Role of I2C: Master or Slave-Receiver. + */ + ALT_I2C_TX_ABORT_CAUSE_ARB_LOST = 1UL << 12, + /*!< Master Abort Arbitration Lost - If set (1), + * master has lost arbitration, or if + * IC_TX_ABRT_SOURCE[14] is also set, then the + * slave transmitter has lost arbitration. Note: + * I2C can be both master and slave at the same + * time. + * + * Role of I2C: Master or Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLVFLUSH_TXFIFO = 1UL << 13, + /*!< Slave Abort Flush TXFIFO - If set (1), Slave + * has received a read command and some data + * exists in the TX FIFO so the slave issues a + * TX_ABRT interrupt to flush old data in TX + * FIFO. + * + * Role of I2C: Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLV_ARBLOST = 1UL << 14, + /*!< Slave Abort Arbitration Lost - If set (1), + * Slave lost the bus while transmitting data to + * a remote master. IC_TX_ABRT_SOURCE[12] is set + * at the same time. + * + * Note: Even though the slave never owns the + * bus, something could go wrong on the + * bus. This is a fail safe check. For instance, + * during a data transmission at the low-to-high + * transition of SCL, if what is on the data bus + * is not what is supposed to be transmitted, + * then DW_apb_i2c no longer own the bus. + * + * Role of I2C: Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLVRD_INTX = 1UL << 15 + /*!< Slave Abort Read TX - If set (1), + * when the processor side responds to a + * slave mode request for data to be transmitted + * to a remote master and user writes a 1 in CMD + * (bit 8) of IC_DATA_CMD register. + * + * Role of I2C: Slave-Transmitter. + */ +} ALT_I2C_TX_ABORT_CAUSE_t; + +/*! + * This type defines a structure for configuration of the SCL high and low counts + * to ensure proper I/O timing with the device interface. + * + * The SCL count values are only relevant if the I2C controller is enabled to as + * an I2C master. The SCL count values are ignored when the I2C controller is + * enabled as an I2C slave. + * + * See: Clock Frequency Configuration section of Chapter 20. I2C + * Controller in the Cyclone V Device Handbook Volume 3: Hard + * Processor System Technical Reference Manual for a complete discussion + * of calculation of the proper SCL clock high and low times. + */ +typedef struct ALT_I2C_MASTER_CONFIG_s +{ + ALT_I2C_ADDR_MODE_t addr_mode; + /*!< The address mode (7 or 10 bit) when + * acting as a master. + */ + bool restart_enable; + /*!< This setting determines whether RESTART + * conditions may be sent when acting as a + * master. When the \e restart_enable is + * false, the I2C controller master is + * incapable of performing the following + * functions: + * * Sending a START BYTE + * * Performing any high-speed mode + * operation + * * Performing direction changes in + * combined format mode + * * Performing a read operation with a + * 10-bit address + */ + ALT_I2C_SPEED_t speed_mode; + /*!< The speed mode of the I2C operation. + */ + uint16_t ss_scl_hcnt; + /*!< The SCL clock high-period count for + * standard speed. + */ + uint16_t ss_scl_lcnt; + /*!< The SCL clock low-period count for + * standard speed. + */ + uint16_t fs_scl_hcnt; + /*!< The SCL clock high-period count for fast + * speed. + */ + uint16_t fs_scl_lcnt; + /*!< The SCL clock low-period count for fast + * speed. + */ + uint8_t fs_spklen; + /*!< The duration, measured in ic_clk cycles, + * of the longest spike that is filtered out + * by the spike suppression logic when the + * component is operating in SS or FS modes. + */ +} ALT_I2C_MASTER_CONFIG_t; + +/*! + * This type defines a structure for configuration of the I2C controller when it + * is operating in slave mode. + */ +typedef struct ALT_I2C_SLAVE_CONFIG_s +{ + ALT_I2C_ADDR_MODE_t addr_mode; /*!< The address mode (7 or 10 bit) when + * acting as a slave. + */ + uint32_t addr; /*!< The slave address to which the I2C + * controller responds when acting as a + * slave. + */ + bool nack_enable; /*!< Enable generation of a NACK. when the + * I2C controller is a + * slave-receiver. If \b true, it can + * only generate a NACK after a data + * byte is received; hence, the data + * transfer is aborted and the data + * received is not pushed onto the + * receive buffer. When \b false, it + * generates NACK/ACK, depending on + * normal criteria. + * * \b true = generate NACK after data + * byte received + * * \b false = generate NACK/ACK normally + */ +} ALT_I2C_SLAVE_CONFIG_t; + +/*! + * Initialize the specified I2C controller instance for use and return a device + * handle referencing it. + * + * \param i2c + * The HPS I2C controller instance to initialize. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Initialization process: + * * Initialize internal driver state + * * Check clock setup (ALT_CLK_L4_SP) + * * Take I2C instance out of reset (System Manager) + * * Disable and clear all interrupts and status conditions + * * Setup and initialize any expected initial I2C controller state + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_init(const ALT_I2C_CTLR_t i2c, ALT_I2C_DEV_t *i2c_dev); + +/*! + * Reset the specified I2C controller instance for use. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Reset process: + * * Disable controller + * * Initialize internal driver state + * * Check clock setup (ALT_CLK_L4_SP) + * * Take I2C instance out of reset (System Manager) + * * Disable and clear all interrupts and status conditions + * * Setup and initialize any expected initial I2C controller state + * * Enable controller + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_reset(ALT_I2C_DEV_t * i2c_dev); + +/*! + * Uninitialize the I2C controller referenced by the \e i2c_dev handle. + * + * This function attempts to gracefully shutdown the I2C controller by waiting for + * any inpcomplete transactions to finish and then putting the I2C controller into + * reset. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_uninit(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Disables the I2C controller. + * + * When the I2C controller is disabled, the following occurs: + * * The TX FIFO and RX FIFO get flushed. + * * The I2C interrupt status conditions remain active until the I2C controller + * goes into IDLE state. + * + * If the controller is transmitting, it stops as well as deletes the contents of + * the transmit buffer after the current transfer is complete. If the module is + * receiving, the controller stops the current transfer at the end of the current + * byte and does not acknowledge the transfer. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE = 0 + * Follow the procedure in section 3.8.3 Disabling DW_apb_i2c of the DW Databook. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_disable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Enables the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_enable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE if the I2C controller is enabled. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_is_enabled(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Gets the current configuration of the I2C controller when operating in master + * mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_I2C_MASTER_CONFIG_t structure for holding + * the returned I2C master mode configuration parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t* cfg); + +/*! + * Sets the configuration of the I2C controller with operational parameters for + * operating in master mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * Pointer to a ALT_I2C_MASTER_CONFIG_t structure holding the desired + * I2C master mode operational parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg); + +/*! + * This is a utility function that returns the speed based on parameters of the + * I2C master configuration. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * A pointer to the master confugurations. + * + * \param speed_in_hz + * [out] Speed (Hz) of the I2C bus currently configured at. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_master_config_speed_get(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg, + uint32_t * speed_in_hz); + +/*! + * This is a utility function that computes parameters for the I2C master + * configuration that best matches the speed requested. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * A pointer to the master confugurations. + * + * \param speed_in_hz + * Speed (Hz) of the I2C bus to configure. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_speed_set(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t * cfg, + uint32_t speed_in_hz); + +/*! + * Definition included for backwards compatibility. + */ +#define alt_i2c_cfg_to_speed(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_get((i2c_dev), (cfg), (speed_in_hz)) + +/*! + * Definition included for backwards compatibility. + */ +#define alt_i2c_speed_to_cfg(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_set((i2c_dev), (cfg), (speed_in_hz)) + +/*! + * Gets the current configuration of the I2C controller when operating in slave + * mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_I2C_SLAVE_CONFIG_t structure for holding + * the returned I2C slave mode configuration parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_SLAVE_CONFIG_t* cfg); + +/*! + * Sets the configuration of the I2C controller with operational parameters for + * operating in slave mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * Pointer to a ALT_I2C_SLAVE_CONFIG_t structure holding the desired + * I2C slave mode operational parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_SLAVE_CONFIG_t* cfg); + +/*! \addtogroup ALT_I2C_SDA_HOLD SDA Hold Time Configuration + * + * The I2C protocol specification requires 300ns of hold time on the SDA signal in + * standard and fast speed modes. Board delays on the SCL and SDA signals can mean + * that the hold-time requirement is met at the I2C master, but not at the I2C + * slave (or vice-versa). Because each system may encounter differing board signal + * delays, the I2C controller provides the capability to adjust of the SDA + * hold-time. + * + * The functions in this section provide software configuration of SDA hold time + * for the I2C controller. + * + * @{ + */ + +/*! + * Gets the currently configured value for the SDA hold time in I2C controller + * clock (\ref ALT_CLK_L4_SP) clock ticks. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param hold_time + * [out] The configured SDA hold time in \ref ALT_CLK_L4_SP clock + * ticks. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_sda_hold_time_get(ALT_I2C_DEV_t *i2c_dev, + uint16_t *hold_time); + +/*! + * Sets the configured value for the SDA hold time in terms of I2C controller + * clock (\ref ALT_CLK_L4_SP) clock ticks. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param hold_time + * The SDA hold time in \ref ALT_CLK_L4_SP clock ticks. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_SDA_HOLD is 16 bits wide. hold_time must be in range 0..65535. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_sda_hold_time_set(ALT_I2C_DEV_t *i2c_dev, + const uint16_t hold_time); + +/*! @} */ + +/*! + * Gets the current operational mode of the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mode + * [out] The current operational mode enabled for the I2C + * controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_op_mode_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MODE_t* mode); + +/*! + * Sets the operational mode of the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mode + * The operational mode to enable for the I2C controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_op_mode_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MODE_t mode); + +/*! + * Returns ALT_E_TRUE if the I2C controller is busy. The I2C controller is busy if + * either the Slave Finite State Machine (FSM) is not in the IDLE state or the + * Master Finite State Machine (FSM) is not in the IDLE state. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.ACTIVITY == 1 + * NOTE: IC_STATUS[0] that is, the ACTIVITY bit is the OR of SLV_ACTIVITY and + * MST_ACTIVITY bits. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_is_busy(ALT_I2C_DEV_t *i2c_dev); + +/*! + * This function reads a single data byte from the receive FIFO. + * + * This function is used to perform low level access to the data bytes + * received by the I2C controller and buffered in the receive FIFO. It + * may be used by master-receivers or slave receivers. + * + * This function does not check for valid data in the receive FIFO + * beforehand and may cause an underflow if improperly used. It is + * meant to be called from a context where preconditions have been + * previously asserted such as in the implementation of the + * alt_i2c_slave_receive() or alt_i2c_master_receive() function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param val + * [out] The single data byte read from the receive FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_read(ALT_I2C_DEV_t *i2c_dev, uint8_t *val); + +/*! + * This function writes a single data byte to the transmit FIFO. + * + * This function is used to perform low level writes of data to the + * transmit FIFO for transmission by the I2C controller. It may be + * used by slave receivers. + * + * This function does not check whether the transmit FIFO is full or + * not beforehand and may cause an overflow if improperly used. It is + * meant to be called from a context where preconditions have been + * previously asserted such as in the implementation of the + * alt_i2c_slave_transmit() function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param val + * The data byte to write to the transmission FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_write(ALT_I2C_DEV_t *i2c_dev, const uint8_t val); + +/*! + * This function acts in the role of a slave-receiver by receiving a single data + * byte from the I2C bus in response to a write command from the master. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is data in the RX FIFO to + * accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * [out] A pointer to a buffer to contain the received data byte. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_receive(ALT_I2C_DEV_t *i2c_dev, + uint8_t *data); + +/*! + * This function acts in the role of a slave-transmitter by transmitting a single + * data byte to the I2C bus in response to a read request from the master. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO to accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * The data byte to transmit. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_transmit(ALT_I2C_DEV_t *i2c_dev, + const uint8_t data); + +/*! + * This function acts in the role of a slave-transmitter by transmitting data in + * bulk to the I2C bus in response to a series of read requests from a master. + * + * In the standard I2C protocol, all transactions are single byte transactions and + * the slave responds to a remote master read request by writing one byte into the + * slave's TX FIFO. When a slave (slave-transmitter) is issued with a read request + * from the remote master (master-receiver), at a minimum there should be at least + * one entry placed into the slave-transmitter's TX FIFO. The I2C controller is + * capable of handling more data in the TX FIFO so that subsequent read requests + * can receive that data without raising an interrupt or software having to poll + * to request more data. This eliminates overhead latencies from being incurred by + * servicing the interrupt or polling for data requests each time had there been a + * restriction of having only one entry placed in the TX FIFO. + * + * If the remote master acknowledges the data sent by the slave-transmitter and + * there is no data in the slave's TX FIFO, the I2C controller raises the read + * request interrupt and waits for data to be written into the TX FIFO before it + * can be sent to the remote master. + * + * If the programmer knows in advance that the master is requesting a packet of \e + * n bytes, then when another master request for data is received, the TX FIFO + * could be written with \e n number bytes and the master receives it as a + * continuous stream of data. For example, the slave continues to send data to the + * master as long as the master is acknowledging the data sent and there is data + * available in the TX FIFO. There is no need to hold the SCL line low or to issue + * READ request again. + * + * If the remote master is to receive \e n bytes from the slave but the programmer + * wrote a number of bytes larger than \e n to the TX FIFO, then when the slave + * finishes sending the requested \e n bytes, it clears the TX FIFO and ignores + * any excess bytes. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO to accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * A pointer to the data buffer to transmit. + * + * \param size + * The size of the data buffer in bytes to place in the TX FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * See: Section Slave-Transfer Operation for Bulk Transfers of the DW + * Databook for details of implementation and error conditions that may occur. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_bulk_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size); + +/*! + * This function returns the current target address. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param target_addr + * [out] The 7 or 10 bit slave target address. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_i2c_master_target_get(ALT_I2C_DEV_t * i2c_dev, uint32_t * target_addr); + +/*! + * This function updates the target slave address for any upcoming I2C bus IO. + * + * This API is not suitlabe for being called in an interrupt context as it + * will wait for the TX FIFO to flush before applying the changes. If the TX + * FIFO is known to be empty and the controller idle, then it can be safely + * called. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param target_addr + * The 7 or 10 bit slave target address. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_i2c_master_target_set(ALT_I2C_DEV_t * i2c_dev, uint32_t target_addr); + +/*! + * This function acts in the role of a master-transmitter by issuing a write + * command and transmitting data to the I2C bus. + * + * This API is not suitable for being called in an interrupt context as it may + * wait for certain controller states before completing. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * A pointer to a data buffer to transmit + * + * \param size + * The size of the data buffer in bytes to place in the TX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function acts in the role of a master-receiver by receiving one or more + * data bytes transmitted from a slave in response to read requests issued from + * this master. + * + * This function causes the master to issue the required number of read requests + * to the slave and read the received data bytes from the Rx FIFO. + * + * The \e issue_restart and \e issue_stop parameters apply to the final read + * request transaction in the \e num_data_entries sequence required to fulfill the + * aggregate receive request. + * + * This API is not suitable for being called in an interrupt context as it may + * wait for certain controller states before completing. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * [out] The data buffer to receive the requested \e size bytes. + * + * \param size + * The size of the data buffer to read from the RX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_receive(ALT_I2C_DEV_t *i2c_dev, + void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function causes the I2C controller master to issue a READ request on the + * bus. This function is typically used during master-receiver transfers. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Write IC_DATA_CMD.CMD = 1 (read request). IC_DATA_CMD.DAT is + * written with "don't care" values as these bits are ignored by the + * I2C controller . + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_issue_read(ALT_I2C_DEV_t *i2c_dev, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function causes the I2C controller master to issue a send byte on the + * bus. This function is typically used during master-transmitter/slave-transmitter + * transfers. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param value + * The data item to be transmitted. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Write IC_DATA_CMD.CMD = 0 (write request). + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_issue_write(ALT_I2C_DEV_t *i2c_dev, + const uint8_t value, + const bool issue_restart, + const bool issue_stop); + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_GEN_CALL General Call + * + * The functions in this group support General Call addresses. + * + * The general call address is for addressing every device connected to the I2C + * bus at the same time. However, if a device does not need any of the data + * supplied within the general call structure, it can ignore this address by not + * issuing an acknowledgment. If a device does require data from a general call + * address, it acknowledges this address and behaves as a slave-receiver. The + * master does not actually know how many devices acknowledged if one or more + * devices respond. The second and following bytes are acknowledged by every + * slave-receiver capable of handling this data. A slave who cannot process one of + * these bytes must ignore it by not-acknowledging. If one or more slaves + * acknowledge, the not-acknowledge will not be seen by the master. + * + * The functions in this group do not provide any general call functional command + * interpretation or implementation (e.g. software reset). + * + * @{ + */ + +/*! + * This function acts in the role of a master-transmitter by issuing a general + * call command to all devices connected to the I2C bus. + * + * The \e issue_restart and \e issue_stop parameters apply to the final write + * transaction in the \e num_data_entries byte transmission sequence. + * + * The I2C controller must be in master mode before calling this function. + * + * The target slave address will be modified by this function. Call + * alt_i2c_master_target_set() to reset the slave target address for + * subsequent IO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * An array of data byte(s) to transmit. + * + * \param num_data_entries + * The number of entries (bytes) in \e data to place in the TX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_general_call(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * Disables the I2C controller from responding to a General Call address. The + * controller will respond with a NACK and no General Call status conditions or + * interrupts are generated. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_disable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Enables the I2C controller to respond with an ACK when it receives a General + * Call address. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_enable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE if the I2C controller is enabled to respond to General Call + * addresses. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_is_enabled(ALT_I2C_DEV_t *i2c_dev); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_INT Interrupt and Status Conditions + * + * The functions in this group provide management for the I2C controller status + * conditions and interrupts. + * + * Each I2C controller has a single combined interrupt output (\b + * ALT_INT_INTERRUPT_I2Cn_IRQ). The following events can generate an + * interrupt: + * * General Call Address Received + * * Start or Restart Condition Occurred + * * Stop Condition Occurred + * * I2C Controller Activity + * * Receive Done + * * Transmit Abort + * * Read Request + * * Transmit Buffer Empty + * * Transmit Overflow + * * Receive Buffer Full + * * Receive Overflow + * * Receive Underflow + * + * These interrupt status conditions may be monitored either by polling their + * status or by configuring interrupt handlers using the HWLIB Interrupt + * Controller API. + * + * Functions to get the current status, enable or disable (i.e. mass or unmask), + * and clear interrupt status conditions for the I2C controller are defined in + * this section. + * + * @{ + */ + +/*! + * Returns the current I2C controller interrupt status conditions. + * + * This function returns the current value of the I2C controller interrupt status + * register value which reflects the current I2C controller status conditions that + * are not disabled (i.e. masked). + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_INTR_STAT + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status); + +/*! + * Returns the I2C controller raw interrupt status conditions irrespective of + * the interrupt status condition enablement state. + * + * This function returns the current value of the I2C controller raw interrupt + * status register value which reflects the current I2C controller status + * conditions regardless of whether they are disabled (i.e. masked) or not. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_INTR_STAT + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_raw_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status); + +/*! + * Clears the specified I2C controller interrupt status conditions identified + * in the mask. + * + * This function clears one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the QSPI interrupt status conditions to clear. \e mask + * is a mask of logically OR'ed \ref ALT_I2C_STATUS_t values that + * designate the status conditions to clear. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_clear(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Disable the specified I2C controller interrupt status conditions identified in + * the mask. + * + * This function disables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of enabling it as a contributor to the \b + * ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. The function + * alt_i2c_int_enable() is used to enable status source conditions. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_I2C_STATUS_t values that designate the status conditions to + * disable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_disable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Enable the specified I2C controller interrupt status conditions identified in + * the mask. + * + * This function enables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of disabling it as a contributor to the \b + * ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. The function + * alt_i2c_int_disable() is used to disable status source conditions. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_I2C_STATUS_t values that designate the status conditions to + * enable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_enable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Gets the cause of I2C transmission abort. A I2C transmission abort indicates + * that the I2C transmitter is unable to complete the intended actions on the + * contents of the transmit FIFO. This situation can occur both as an I2C master + * or an I2C slave, and is referred to as a "transmit abort". + * + * The returned value of this function is the value of the IC_TX_ABRT_SOURCE + * register which indicates the cause why the transmit abort occurred. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cause + * [out] A pointer to a bit mask of the \ref ALT_I2C_TX_ABORT_CAUSE_t + * causes of the transmission abort. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_ABRT_SOURCE + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_abort_cause_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_TX_ABORT_CAUSE_t *cause); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_RX_FIFO RX FIFO Management + * + * The receive FIFO has a configurable threshold value that controls the level of + * entries (or above) that sets the RX_FULL status condition and triggers an + * interrupt. The valid range is 0 - (ALT_I2C_RX_FIFO_NUM_ENTRIES-1), with the + * additional restriction that I2C controller does not allow this value to be set + * to a value larger than the depth of the buffer. If an attempt is made to do + * that, the actual value set will be the maximum depth of the buffer. A value of + * 0 sets the threshold for 1 entry, and a value of (ALT_I2C_RX_FIFO_NUM_ENTRIES-1) + * sets the threshold for ALT_I2C_RX_FIFO_NUM_ENTRIES entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the I2C controller receive FIFO. + */ +#define ALT_I2C_RX_FIFO_NUM_ENTRIES 64 + +/*! + * Returns ALT_E_TRUE when the receive FIFO is empty. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.RFNE == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE when the receive FIFO is completely full. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.RFF == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns the number of valid entries in the receive FIFO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param num_entries + * [out] The number of entries in the receive FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RXFLR.RXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries); + +/*! + * Gets the current receive FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold); + +/*! + * Sets the current receive FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_TX_FIFO TX FIFO Management + * + * The transmit FIFO has a configurable threshold value that controls the level of + * entries (or below) that sets the TX_EMPTY status condition and triggers an + * interrupt. The valid range is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES-1), with the + * additional restriction that I2C controller does not allow this value to be set + * to a value larger than the depth of the buffer. If an attempt is made to do + * that, the actual value set will be the maximum depth of the buffer. A value of + * 0 sets the threshold for 0 entries, and a value of (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) + * sets the threshold for (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the I2C controller transmit FIFO. + */ +#define ALT_I2C_TX_FIFO_NUM_ENTRIES 64 + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is empty. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.TFE == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is completely full. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.TFNF == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns the number of valid entries in the transmit FIFO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param num_entries + * [out] The number of entries in the transmit FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TXFLR.TXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries); + +/*! + * Gets the current transmit FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold); + +/*! + * Sets the current transmit FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_DMA DMA Interface + * + * The DMA interface has a configurable threshold value that controls the + * level of entries that triggers the burst handshaking request used for DMA + * integration. + * + * For the TX threshold, if the number of entries in the TX FIFO is at or + * below the set threshold, a DMA handshaking request will be made. The valid + * range for the TX threshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). + * + * For the RX threshold, if the number of entries in the RX FIFO is above the + * set threshold, a DMA handshaking request will be made. The valid range for + * the RX treshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). + * + * Having a higher threshold can improve the AXI bus utilization at the + * expense of the likelyhoold of overflow / underflow conditions. + * @{ + */ + +/*! + * Gets the current RX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); + +/*! + * Sets the current RX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); + +/*! + * Gets the current TX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); + +/*! + * Sets the current TX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_I2C_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_i2c.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_i2c.h new file mode 100644 index 0000000..b50543a --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_i2c.h @@ -0,0 +1,5940 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_I2C */ + +#ifndef __ALTERA_ALT_I2C_H__ +#define __ALTERA_ALT_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : I2C Module - ALT_I2C + * I2C Module + * + * Registers in the I2C module + * + */ +/* + * Register : Control Register - ic_con + * + * This register can be written only when the I2C is disabled, which corresponds to + * the Bit [0] of the Enable Register being set to 0. Writes at other times have no + * effect. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | Master Enable + * [2:1] | RW | 0x2 | Master Speed Control + * [3] | RW | 0x1 | Slave Address Size + * [4] | RW | 0x1 | Master Address Size + * [5] | RW | 0x1 | Restart Enable + * [6] | RW | 0x1 | Slave Disable + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Enable - master_mode + * + * This bit controls whether the i2c master is enabled. + * + * NOTE: Software should ensure that if this bit is written with '1', then bit 6 + * should also be written with a '1'. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------- + * ALT_I2C_CON_MST_MOD_E_DIS | 0x0 | master disabled + * ALT_I2C_CON_MST_MOD_E_EN | 0x1 | master enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_MST_MOD + * + * master disabled + */ +#define ALT_I2C_CON_MST_MOD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_MST_MOD + * + * master enabled + */ +#define ALT_I2C_CON_MST_MOD_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_MSB 0 +/* The width in bits of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_MST_MOD register field value. */ +#define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CON_MST_MOD register field value. */ +#define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_RESET 0x1 +/* Extracts the ALT_I2C_CON_MST_MOD field value from a register. */ +#define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CON_MST_MOD register field value suitable for setting the register. */ +#define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Master Speed Control - speed + * + * These bits control at which speed the I2C operates, its setting is relevant only + * if one is operating the I2C in master mode. Hardware protects against illegal + * values being programmed by software. This field should be programmed only with + * standard or fast speed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:--------------------------- + * ALT_I2C_CON_SPEED_E_STANDARD | 0x1 | standard mode (100 kbit/s) + * ALT_I2C_CON_SPEED_E_FAST | 0x2 | fast mode (400 kbit/s) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_SPEED + * + * standard mode (100 kbit/s) + */ +#define ALT_I2C_CON_SPEED_E_STANDARD 0x1 +/* + * Enumerated value for register field ALT_I2C_CON_SPEED + * + * fast mode (400 kbit/s) + */ +#define ALT_I2C_CON_SPEED_E_FAST 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_MSB 2 +/* The width in bits of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_WIDTH 2 +/* The mask used to set the ALT_I2C_CON_SPEED register field value. */ +#define ALT_I2C_CON_SPEED_SET_MSK 0x00000006 +/* The mask used to clear the ALT_I2C_CON_SPEED register field value. */ +#define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_RESET 0x2 +/* Extracts the ALT_I2C_CON_SPEED field value from a register. */ +#define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_I2C_CON_SPEED register field value suitable for setting the register. */ +#define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006) + +/* + * Field : Slave Address Size - ic_10bitaddr_slave + * + * When acting as a slave, this bit controls whether the I2C responds to 7- or + * 10-bit addresses. In 7-bit addressing, only the lower 7 bits of the Slave + * Address Register are compared. The I2C responds will only respond to 10-bit + * addressing transfers that match the full 10 bits of the Slave Address register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT | 0x0 | 7-bit addressing + * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT | 0x1 | 10-bit addressing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV + * + * 7-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV + * + * 10-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3 +/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_10BITADDR_SLV field value from a register. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_CON_IC_10BITADDR_SLV register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Master Address Size - ic_10bitaddr_master + * + * This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing + * mode when acting as a master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT | 0x0 | 7-bit addressing + * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT | 0x1 | 10-bit addressing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST + * + * 7-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST + * + * 10-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4 +/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_10BITADDR_MST field value from a register. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_CON_IC_10BITADDR_MST register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Restart Enable - ic_restart_en + * + * Determines whether RESTART conditions may be sent when acting as a master. Some + * older slaves do not support handling RESTART conditions; however, RESTART + * conditions are used in several I2C operations. When RESTART is disabled, the + * master is prohibited from performing the following functions + * + * * Changing direction within a transfer (split), + * + * * Sending a START BYTE, + * + * * High-speed mode operation, + * + * * Combined format transfers in 7-bit addressing modes, + * + * * Read operation with a 10-bit address, + * + * * Sending multiple bytes per transfer, + * + * By replacing RESTART condition followed by a STOP and a subsequent START + * condition, split operations are broken down into multiple I2C transfers. If the + * above operations are performed, it will result in setting bit [6](tx_abort) of + * the Raw Interrupt Status Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------- + * ALT_I2C_CON_IC_RESTART_EN_E_DIS | 0x0 | restart master disable + * ALT_I2C_CON_IC_RESTART_EN_E_EN | 0x1 | restart master enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN + * + * restart master disable + */ +#define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN + * + * restart master enable + */ +#define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_MSB 5 +/* The width in bits of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_RESTART_EN register field value. */ +#define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_CON_IC_RESTART_EN register field value. */ +#define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_RESTART_EN field value from a register. */ +#define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_CON_IC_RESTART_EN register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Slave Disable - ic_slave_disable + * + * This bit controls whether I2C has its slave disabled. The slave will be + * disabled, after reset. + * + * NOTE: Software should ensure that if this bit is written with 0, then bit [0] of + * this register should also be written with a 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------- + * ALT_I2C_CON_IC_SLV_DIS_E_DIS | 0x1 | slave disable + * ALT_I2C_CON_IC_SLV_DIS_E_EN | 0x0 | slave enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS + * + * slave disable + */ +#define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1 +/* + * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS + * + * slave enable + */ +#define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_MSB 6 +/* The width in bits of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_SLV_DIS register field value. */ +#define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_CON_IC_SLV_DIS register field value. */ +#define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_SLV_DIS field value from a register. */ +#define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_CON_IC_SLV_DIS register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CON. + */ +struct ALT_I2C_CON_s +{ + uint32_t master_mode : 1; /* Master Enable */ + uint32_t speed : 2; /* Master Speed Control */ + uint32_t ic_10bitaddr_slave : 1; /* Slave Address Size */ + uint32_t ic_10bitaddr_master : 1; /* Master Address Size */ + uint32_t ic_restart_en : 1; /* Restart Enable */ + uint32_t ic_slave_disable : 1; /* Slave Disable */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CON. */ +typedef volatile struct ALT_I2C_CON_s ALT_I2C_CON_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CON register from the beginning of the component. */ +#define ALT_I2C_CON_OFST 0x0 +/* The address of the ALT_I2C_CON register. */ +#define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST)) + +/* + * Register : Target Address Register - ic_tar + * + * This register can be written to only when the ic_enable register is set to 0. + * This register is 13 bits wide. All bits can be dynamically updated as long as + * any set of the following conditions are true, + * + * (Enable Register bit 0 is set to 0) or (Enable Register bit 0 is set to 1 AND + * (I2C is NOT engaged in any Master [tx, rx] operation [ic_status register + * mst_activity bit 5 is set to 0]) AND (I2C is enabled to operate in Master + * mode[ic_con bit[0] is set to one]) AND (there are NO entries in the TX FIFO + * Register [IC_STATUS bit [2] is set to 1]) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [9:0] | RW | 0x55 | Master Target Address + * [10] | RW | 0x0 | General Call OR Start + * [11] | RW | 0x0 | Special + * [12] | RW | 0x1 | Master Addressing Bit Control + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Target Address - ic_tar + * + * This is the target address for any master transaction. When transmitting a + * General Call, these bits are ignored. To generate a START BYTE, the CPU needs to + * write only once into these bits. If the ic_tar and ic_sar are the same, loopback + * exists but the FIFOs are shared between master and slave, so full loopback is + * not feasible. Only one direction loopback mode is supported (simplex), not + * duplex. A master cannot transmit to itself; it can transmit to only a slave. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_MSB 9 +/* The width in bits of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_WIDTH 10 +/* The mask used to set the ALT_I2C_TAR_IC_TAR register field value. */ +#define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff +/* The mask used to clear the ALT_I2C_TAR_IC_TAR register field value. */ +#define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_RESET 0x55 +/* Extracts the ALT_I2C_TAR_IC_TAR field value from a register. */ +#define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_I2C_TAR_IC_TAR register field value suitable for setting the register. */ +#define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff) + +/* + * Field : General Call OR Start - gc_or_start + * + * If bit 11 (SPECIAL) of this Register is set to 1, then this bit indicates + * whether a General Call or START byte command is to be performed by the I2C or + * General Call Address after issuing a General Call, only writes may be performed. + * Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the Raw + * Interrupt_Status register. The I2C remains in General Call mode until the + * special bit value (bit 11) is cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------- + * ALT_I2C_TAR_GC_OR_START_E_GENCALL | 0x0 | General Call + * ALT_I2C_TAR_GC_OR_START_E_STARTBYTE | 0x1 | START Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_GC_OR_START + * + * General Call + */ +#define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_GC_OR_START + * + * START Byte + */ +#define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_MSB 10 +/* The width in bits of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_GC_OR_START register field value. */ +#define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_TAR_GC_OR_START register field value. */ +#define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_RESET 0x0 +/* Extracts the ALT_I2C_TAR_GC_OR_START field value from a register. */ +#define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_TAR_GC_OR_START register field value suitable for setting the register. */ +#define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Special - special + * + * This bit indicates whether software performs a General Call or START BYTE + * command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:-------------------------------------------- + * ALT_I2C_TAR_SPECIAL_E_GENCALL | 0x0 | Ignore bit 10 gc_or_start and use ic_tar + * : | | normally + * ALT_I2C_TAR_SPECIAL_E_STARTBYTE | 0x1 | Perform special I2C command as specified in + * : | | gc_or_start + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_SPECIAL + * + * Ignore bit 10 gc_or_start and use ic_tar normally + */ +#define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_SPECIAL + * + * Perform special I2C command as specified in gc_or_start + */ +#define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_MSB 11 +/* The width in bits of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_SPECIAL register field value. */ +#define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_TAR_SPECIAL register field value. */ +#define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_RESET 0x0 +/* Extracts the ALT_I2C_TAR_SPECIAL field value from a register. */ +#define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_TAR_SPECIAL register field value suitable for setting the register. */ +#define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Master Addressing Bit Control - ic_10bitaddr_master + * + * This bit controls whether the i2c starts its transfers in 7-bit or 10-bit + * addressing mode when acting as a master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------- + * ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 | 0x0 | Master Address, 7bit + * ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 | 0x1 | Master Address, 10bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST + * + * Master Address, 7bit + */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST + * + * Master Address, 10bit + */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12 +/* The width in bits of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff +/* The reset value of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1 +/* Extracts the ALT_I2C_TAR_IC_10BITADDR_MST field value from a register. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_I2C_TAR_IC_10BITADDR_MST register field value suitable for setting the register. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TAR. + */ +struct ALT_I2C_TAR_s +{ + uint32_t ic_tar : 10; /* Master Target Address */ + uint32_t gc_or_start : 1; /* General Call OR Start */ + uint32_t special : 1; /* Special */ + uint32_t ic_10bitaddr_master : 1; /* Master Addressing Bit Control */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TAR. */ +typedef volatile struct ALT_I2C_TAR_s ALT_I2C_TAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TAR register from the beginning of the component. */ +#define ALT_I2C_TAR_OFST 0x4 +/* The address of the ALT_I2C_TAR register. */ +#define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST)) + +/* + * Register : Slave Address Register - ic_sar + * + * Holds Address of Slave + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [9:0] | RW | 0x55 | Slave Address + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Slave Address - ic_sar + * + * The Slave Address register holds the slave address when the I2C is operating as + * a slave. For 7-bit addressing, only Field Bits [6:0] of the Slave Address + * Register are used. This register can be written only when the I2C interface is + * disabled, which corresponds to field bit 0 of the Enable Register being set to + * 0. Writes at other times have no effect. + * + * Note, the default values cannot be any of the reserved address locations: that + * is, + * + * 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not + * guaranteed if you program the Slave Address Register or Target Address Register + * to a reserved value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_MSB 9 +/* The width in bits of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_WIDTH 10 +/* The mask used to set the ALT_I2C_SAR_IC_SAR register field value. */ +#define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff +/* The mask used to clear the ALT_I2C_SAR_IC_SAR register field value. */ +#define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_RESET 0x55 +/* Extracts the ALT_I2C_SAR_IC_SAR field value from a register. */ +#define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_I2C_SAR_IC_SAR register field value suitable for setting the register. */ +#define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SAR. + */ +struct ALT_I2C_SAR_s +{ + uint32_t ic_sar : 10; /* Slave Address */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SAR. */ +typedef volatile struct ALT_I2C_SAR_s ALT_I2C_SAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SAR register from the beginning of the component. */ +#define ALT_I2C_SAR_OFST 0x8 +/* The address of the ALT_I2C_SAR register. */ +#define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST)) + +/* + * Register : Tx Rx Data and Command Register - ic_data_cmd + * + * This is the register the CPU writes to when filling the TX FIFO. Reading from + * this register returns bytes from RX FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------- + * [7:0] | RW | 0x0 | Tx Rx Data + * [8] | W | 0x0 | Master Read Write Control + * [9] | W | 0x0 | Generate Stop + * [10] | W | 0x0 | Generate Restart + * [31:11] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Tx Rx Data - dat + * + * This Field contains the data to be transmitted or received on the I2C bus. If + * you are writing to these bits and want to perform a read, bits 7:0 (dat) are + * ignored by the I2C. However, when you read from this register, these bits return + * the value of data received on the I2C interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_MSB 7 +/* The width in bits of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_WIDTH 8 +/* The mask used to set the ALT_I2C_DATA_CMD_DAT register field value. */ +#define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_DATA_CMD_DAT register field value. */ +#define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_DAT field value from a register. */ +#define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_DATA_CMD_DAT register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Master Read Write Control - cmd + * + * This bit controls whether a read or a write is performed. This bit does not + * control the direction when the I2C acts as a slave. It controls only the + * direction when it acts as a master. When a command is entered in the TX FIFO, + * this bit distinguishes the write and read commands. In slave-receiver mode, this + * bit is a 'don't care' because writes to this register are not required. In + * slave-transmitter mode, a '0' indicates that the CPU data is to be transmitted. + * When programming this bit, you should remember the following: attempting to + * perform a read operation after a General Call command has been sent results in a + * tx_abrt interrupt (bit 6 of the Raw Intr Status Register), unless bit 11 special + * in the Target Address Register has been cleared. If a '1' is written to this bit + * after receiving a RD_REQ interrupt, then a tx_abrt interrupt occurs. + * + * NOTE: It is possible that while attempting a master I2C read transfer on I2C, a + * RD_REQ interrupt may have occurred simultaneously due to a remote I2C master + * addressing I2C. In this type of scenario, I2C ignores the Data Cmd write, + * generates a tx_abrt interrupt, and waits to service the RD_REQ interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------- + * ALT_I2C_DATA_CMD_CMD_E_RD | 0x1 | Master Read + * ALT_I2C_DATA_CMD_CMD_E_WR | 0x0 | Master Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_CMD + * + * Master Read + */ +#define ALT_I2C_DATA_CMD_CMD_E_RD 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_CMD + * + * Master Write + */ +#define ALT_I2C_DATA_CMD_CMD_E_WR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_MSB 8 +/* The width in bits of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_CMD register field value. */ +#define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_DATA_CMD_CMD register field value. */ +#define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_CMD field value from a register. */ +#define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_DATA_CMD_CMD register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Generate Stop - stop + * + * This bit controls whether a STOP is issued after the byte is sent or received. + * + * 1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is + * empty. If the Tx FIFO is not empty, the master immediately tries to start a new + * transfer by issuing a START and arbitrating for the bus. + * + * 0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO + * is empty. If the Tx FIFO is not empty, the master continues the current transfer + * by sending/receiving data bytes according to the value of the CMD bit. If the Tx + * FIFO is empty, the master holds the SCL line low and stalls the bus until a new + * command is available in the Tx FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------ + * ALT_I2C_DATA_CMD_STOP_E_STOP | 0x1 | Issue Stop + * ALT_I2C_DATA_CMD_STOP_E_NO_STOP | 0x0 | Do Not Issue Stop + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_STOP + * + * Issue Stop + */ +#define ALT_I2C_DATA_CMD_STOP_E_STOP 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_STOP + * + * Do Not Issue Stop + */ +#define ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_MSB 9 +/* The width in bits of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_STOP register field value. */ +#define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_DATA_CMD_STOP register field value. */ +#define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_STOP field value from a register. */ +#define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_DATA_CMD_STOP register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Generate Restart - restart + * + * This bit controls whether a RESTART is issued before the byte is sent or + * received. + * + * 1 = A RESTART is issued before the data is sent/received (according to the value + * of CMD), regardless of whether or not the transfer direction is changing from + * the previous command. + * + * 0 = A RESTART is issued only if the transfer direction is changing from the + * previous command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:---------------------------------- + * ALT_I2C_DATA_CMD_RESTART_E_RESTART | 0x1 | Issue Restart + * ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE | 0x0 | Issue Restart On Direction Change + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART + * + * Issue Restart + */ +#define ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART + * + * Issue Restart On Direction Change + */ +#define ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_MSB 10 +/* The width in bits of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_RESTART register field value. */ +#define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_DATA_CMD_RESTART register field value. */ +#define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_RESTART field value from a register. */ +#define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_DATA_CMD_RESTART register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DATA_CMD. + */ +struct ALT_I2C_DATA_CMD_s +{ + uint32_t dat : 8; /* Tx Rx Data */ + uint32_t cmd : 1; /* Master Read Write Control */ + uint32_t stop : 1; /* Generate Stop */ + uint32_t restart : 1; /* Generate Restart */ + uint32_t : 21; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DATA_CMD. */ +typedef volatile struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DATA_CMD register from the beginning of the component. */ +#define ALT_I2C_DATA_CMD_OFST 0x10 +/* The address of the ALT_I2C_DATA_CMD register. */ +#define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST)) + +/* + * Register : Std Spd Clock SCL HCNT Register - ic_ss_scl_hcnt + * + * This register sets the SCL clock high-period count for standard speed. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [15:0] | RW | 0x190 | Std Spd SCL High Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Std Spd SCL High Period - ic_ss_scl_hcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock high-period count for + * standard speed. This register can be written only when the I2C interface is + * disabled which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect. The minimum valid value is 6; hardware prevents + * values less than this being written, and if attempted results in 6 being set. It + * is readable and writeable. + * + * NOTE: This register must not be programmed to a value higher than 65525, because + * I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter + * reaches a value of IC_SS_SCL_HCNT + 10. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15 +/* The width in bits of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190 +/* Extracts the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT field value from a register. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value suitable for setting the register. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SS_SCL_HCNT. + */ +struct ALT_I2C_SS_SCL_HCNT_s +{ + uint32_t ic_ss_scl_hcnt : 16; /* Std Spd SCL High Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SS_SCL_HCNT. */ +typedef volatile struct ALT_I2C_SS_SCL_HCNT_s ALT_I2C_SS_SCL_HCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SS_SCL_HCNT register from the beginning of the component. */ +#define ALT_I2C_SS_SCL_HCNT_OFST 0x14 +/* The address of the ALT_I2C_SS_SCL_HCNT register. */ +#define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST)) + +/* + * Register : Std Spd Clock SCL LCNT Register - ic_ss_scl_lcnt + * + * This register sets the SCL clock low-period count for standard speed + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [15:0] | RW | 0x1d6 | Std Spd SCL Low Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Std Spd SCL Low Period - ic_ss_scl_lcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock low period count for + * standard speed. This register can be written only when the I2C interface is + * disabled which corresponds to the Enable Register register being set to 0. + * Writes at other times have no effect. The minimum valid value is 8; hardware + * prevents values less than this from being written, and if attempted, results in + * 8 being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15 +/* The width in bits of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6 +/* Extracts the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT field value from a register. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value suitable for setting the register. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SS_SCL_LCNT. + */ +struct ALT_I2C_SS_SCL_LCNT_s +{ + uint32_t ic_ss_scl_lcnt : 16; /* Std Spd SCL Low Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SS_SCL_LCNT. */ +typedef volatile struct ALT_I2C_SS_SCL_LCNT_s ALT_I2C_SS_SCL_LCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SS_SCL_LCNT register from the beginning of the component. */ +#define ALT_I2C_SS_SCL_LCNT_OFST 0x18 +/* The address of the ALT_I2C_SS_SCL_LCNT register. */ +#define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST)) + +/* + * Register : Fast Spd Clock SCL HCNT Register - ic_fs_scl_hcnt + * + * This register sets the SCL clock high-period count for fast speed + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [15:0] | RW | 0x3c | Fast Spd SCL High Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Fast Spd SCL High Period - ic_fs_scl_hcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This register sets the SCL clock high-period count for + * fast speed. It is used in high-speed mode to send the Master Code and START BYTE + * or General CALL. This register goes away and becomes read-only returning 0s if + * in Standard Speed Mode. This register can be written only when the I2C interface + * is disabled, which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect. The minimum valid value is 6; hardware prevents + * values less than this from being written, and if attempted results in 6 being + * set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15 +/* The width in bits of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c +/* Extracts the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT field value from a register. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value suitable for setting the register. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SCL_HCNT. + */ +struct ALT_I2C_FS_SCL_HCNT_s +{ + uint32_t ic_fs_scl_hcnt : 16; /* Fast Spd SCL High Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SCL_HCNT. */ +typedef volatile struct ALT_I2C_FS_SCL_HCNT_s ALT_I2C_FS_SCL_HCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SCL_HCNT register from the beginning of the component. */ +#define ALT_I2C_FS_SCL_HCNT_OFST 0x1c +/* The address of the ALT_I2C_FS_SCL_HCNT register. */ +#define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST)) + +/* + * Register : Fast Spd Clock SCL LCNT Register - ic_fs_scl_lcnt + * + * This register sets the SCL clock low period count + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [15:0] | RW | 0x82 | Fast Spd SCL Low Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Fast Spd SCL Low Period - ic_fs_scl_lcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock low period count for + * fast speed. It is used in high-speed mode to send the Master Code and START BYTE + * or General CALL. This register can be written only when the I2C interface is + * disabled, which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect.The minimum valid value is 8; hardware prevents + * values less than this being written, and if attempted results in 8 being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15 +/* The width in bits of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82 +/* Extracts the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT field value from a register. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value suitable for setting the register. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SCL_LCNT. + */ +struct ALT_I2C_FS_SCL_LCNT_s +{ + uint32_t ic_fs_scl_lcnt : 16; /* Fast Spd SCL Low Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SCL_LCNT. */ +typedef volatile struct ALT_I2C_FS_SCL_LCNT_s ALT_I2C_FS_SCL_LCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SCL_LCNT register from the beginning of the component. */ +#define ALT_I2C_FS_SCL_LCNT_OFST 0x20 +/* The address of the ALT_I2C_FS_SCL_LCNT register. */ +#define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST)) + +/* + * Register : Interrupt Status Register - ic_intr_stat + * + * Each bit in this register has a corresponding mask bit in the Interrupt Mask + * Register. These bits are cleared by reading the matching Interrupt Clear + * Register. The unmasked raw versions of these bits are available in the Raw + * Interrupt Status Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [0] | R | 0x0 | Receiver Under + * [1] | R | 0x0 | Receiver Over + * [2] | R | 0x0 | Receive Full + * [3] | R | 0x0 | Interrupt Transmit Over + * [4] | R | 0x0 | Interrupt Transmit Empty + * [5] | R | 0x0 | Interrupt Read Request + * [6] | R | 0x0 | Interrupt TX Abort + * [7] | R | 0x0 | Interrupt RX Done + * [8] | R | 0x0 | Interrupt R_activity + * [9] | R | 0x0 | Interrupt Stop Detect + * [10] | R | 0x0 | Interrupt Start Detect + * [11] | R | 0x0 | Interrupt General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receiver Under - r_rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the Tx Rx Data and Command Register. If the module is disabled, + * Enable Register is set to 0, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_UNDER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_INTR_STAT_R_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Receiver Over - r_rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled, + * Enable Register bit[0] is set to 0 this bit keeps its level until the master or + * slave state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_OVER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_INTR_STAT_R_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive Full - r_rx_full + * + * Set when the receive buffer reaches or goes above the Receive FIFO Threshold + * Value(rx_tl). It is automatically cleared by hardware when buffer level goes + * below the threshold. If the module is disabled, Bit [0] of the Enable Register + * set to 0, the RX FIFO is flushed and held in reset; therefore the RX FIFO is not + * full. So this bit is cleared once the Enable Register Bit 0 is programmed with a + * 0, regardless of the activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_FULL field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_INTR_STAT_R_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Interrupt Transmit Over - r_tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the Data and Command + * Register. When the module is disabled, this bit keeps its level until the master + * or slave state machines goes into idle, then interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_OVER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_INTR_STAT_R_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Interrupt Transmit Empty - r_tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, this bit is set to 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_EMPTY field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_INTR_STAT_R_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Interrupt Read Request - r_rd_req + * + * This bit is set to 1 when i2c is acting as a slave and another I2C master is + * attempting to read data from I2C. The I2C holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the IC_DATA_CMD register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RD_REQ field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_INTR_STAT_R_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Interrupt TX Abort - r_tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit + * abort'.When this bit is set to 1, the ic_tx_abrt_source register indicates the + * reason why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_ABRT field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_INTR_STAT_R_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Interrupt RX Done - r_rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_DONE field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_INTR_STAT_R_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Interrupt R_activity - r_activity + * + * This bit captures I2C activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the I2C + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * I2C reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the I2C module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_ACTIVITY field value from a register. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_INTR_STAT_R_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Interrupt Stop Detect - r_stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_STOP_DET field value from a register. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_INTR_STAT_R_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Interrupt Start Detect - r_start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_START_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_START_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_START_DET field value from a register. */ +#define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_INTR_STAT_R_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Interrupt General Call - r_gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_GEN_CALL field value from a register. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_INTR_STAT_R_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_INTR_STAT. + */ +struct ALT_I2C_INTR_STAT_s +{ + const uint32_t r_rx_under : 1; /* Receiver Under */ + const uint32_t r_rx_over : 1; /* Receiver Over */ + const uint32_t r_rx_full : 1; /* Receive Full */ + const uint32_t r_tx_over : 1; /* Interrupt Transmit Over */ + const uint32_t r_tx_empty : 1; /* Interrupt Transmit Empty */ + const uint32_t r_rd_req : 1; /* Interrupt Read Request */ + const uint32_t r_tx_abrt : 1; /* Interrupt TX Abort */ + const uint32_t r_rx_done : 1; /* Interrupt RX Done */ + const uint32_t r_activity : 1; /* Interrupt R_activity */ + const uint32_t r_stop_det : 1; /* Interrupt Stop Detect */ + const uint32_t r_start_det : 1; /* Interrupt Start Detect */ + const uint32_t r_gen_call : 1; /* Interrupt General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_INTR_STAT. */ +typedef volatile struct ALT_I2C_INTR_STAT_s ALT_I2C_INTR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_INTR_STAT register from the beginning of the component. */ +#define ALT_I2C_INTR_STAT_OFST 0x2c +/* The address of the ALT_I2C_INTR_STAT register. */ +#define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST)) + +/* + * Register : Interrupt Mask Register - ic_intr_mask + * + * These bits mask their corresponding interrupt status bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------- + * [0] | RW | 0x1 | Mask RX Under + * [1] | RW | 0x1 | RX Buffer Over + * [2] | RW | 0x1 | RX Buffer Full + * [3] | RW | 0x1 | TX Buffer Over + * [4] | RW | 0x1 | TX Buffer Empty + * [5] | RW | 0x1 | Read Request + * [6] | RW | 0x1 | TX Abort + * [7] | RW | 0x1 | RX Done + * [8] | RW | 0x0 | Activity Bit + * [9] | RW | 0x0 | Stop Detect + * [10] | RW | 0x0 | Start Detect + * [11] | RW | 0x1 | General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mask RX Under - m_rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, + * this bit keeps its level until the master or slave state machines go into idle, + * and then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_UNDER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_INTR_MSK_M_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : RX Buffer Over - m_rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled + * ic_enable[0]=0, this bit keeps its level until the master or slave state + * machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_OVER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_INTR_MSK_M_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : RX Buffer Full - m_rx_full + * + * Set when the receive buffer reaches or goes above the RX_TL threshold in the + * ic_rx_tl register. It is automatically cleared by hardware when buffer level + * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is + * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the + * activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_FULL field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_INTR_MSK_M_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : TX Buffer Over - m_tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the ic_data_cmd register. + * When the module is disabled, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_OVER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_INTR_MSK_M_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : TX Buffer Empty - m_tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, then this bit is set to + * 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_EMPTY field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_INTR_MSK_M_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Read Request - m_rd_req + * + * This bit is set to 1 when I2C is acting as a slave and another I2C master is + * attempting to read data from I2C. The I2C holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the ic_data_cmd register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RD_REQ field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_INTR_MSK_M_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : TX Abort - m_tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. + * When this bit is set to 1, the ic_tx_abrt_source register indicates the reason + * why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_ABRT field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_INTR_MSK_M_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : RX Done - m_rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_DONE field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_INTR_MSK_M_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Activity Bit - m_activity + * + * This bit captures i2c activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the i2c + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * System reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the I2C module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_ACTIVITY field value from a register. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_INTR_MSK_M_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Stop Detect - m_stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether i2c is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_STOP_DET field value from a register. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_INTR_MSK_M_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Start Detect - m_start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_START_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_START_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_START_DET field value from a register. */ +#define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_INTR_MSK_M_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : General Call - m_gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_GEN_CALL field value from a register. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_INTR_MSK_M_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_INTR_MSK. + */ +struct ALT_I2C_INTR_MSK_s +{ + uint32_t m_rx_under : 1; /* Mask RX Under */ + uint32_t m_rx_over : 1; /* RX Buffer Over */ + uint32_t m_rx_full : 1; /* RX Buffer Full */ + uint32_t m_tx_over : 1; /* TX Buffer Over */ + uint32_t m_tx_empty : 1; /* TX Buffer Empty */ + uint32_t m_rd_req : 1; /* Read Request */ + uint32_t m_tx_abrt : 1; /* TX Abort */ + uint32_t m_rx_done : 1; /* RX Done */ + uint32_t m_activity : 1; /* Activity Bit */ + uint32_t m_stop_det : 1; /* Stop Detect */ + uint32_t m_start_det : 1; /* Start Detect */ + uint32_t m_gen_call : 1; /* General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_INTR_MSK. */ +typedef volatile struct ALT_I2C_INTR_MSK_s ALT_I2C_INTR_MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_INTR_MSK register from the beginning of the component. */ +#define ALT_I2C_INTR_MSK_OFST 0x30 +/* The address of the ALT_I2C_INTR_MSK register. */ +#define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST)) + +/* + * Register : Raw Interrupt Status Register - ic_raw_intr_stat + * + * Unlike the ic_intr_stat register, these bits are not masked so they always show + * the true status of the I2C. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | R | 0x0 | I2C Raw Interrupt RX Under + * [1] | R | 0x0 | Raw Interrupt RX Over + * [2] | R | 0x0 | Raw Interrupt RX Full + * [3] | R | 0x0 | Raw Interrupt TX Over + * [4] | R | 0x0 | Raw Interrupt TX Empty + * [5] | R | 0x0 | Raw Interrupt Read Request + * [6] | R | 0x0 | Raw Interrupt TX Abort + * [7] | R | 0x0 | Raw Interrupt RX Done + * [8] | R | 0x0 | Raw Interrupt Activity + * [9] | R | 0x0 | Raw Interrupt Stop Detect + * [10] | R | 0x0 | Raw Interrupt Start Detect + * [11] | R | 0x0 | Raw Interrupt General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : I2C Raw Interrupt RX Under - rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, + * this bit keeps its level until the master or slave state machines go into idle, + * then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_UNDER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Raw Interrupt RX Over - rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled + * ic_enable[0]=0), this bit keeps its level until the master or slave state + * machines go into then, this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_OVER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Raw Interrupt RX Full - rx_full + * + * Set when the receive buffer reaches or goes above the RX_TL threshold in the + * ic_rx_tl register. It is automatically cleared by hardware when buffer level + * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is + * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the + * activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_FULL field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Raw Interrupt TX Over - tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the ic_data_cmd register. + * When the module is disabled, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_OVER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Raw Interrupt TX Empty - tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, then this bit is set to + * 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_EMPTY field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Raw Interrupt Read Request - rd_req + * + * This bit is set to 1 when I2C is acting as a slave and another I2C master is + * attempting to read data from I2C. The i2c holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the ic_data_cmd register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RD_REQ field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_RAW_INTR_STAT_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Raw Interrupt TX Abort - tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. + * When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason + * why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_ABRT field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Raw Interrupt RX Done - rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1 if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_DONE field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Raw Interrupt Activity - activity + * + * This bit captures i2c activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the I2C + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * System reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the i2c module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_ACTIVITY field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Raw Interrupt Stop Detect - stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_STOP_DET field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_RAW_INTR_STAT_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Raw Interrupt Start Detect - start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_START_DET field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_RAW_INTR_STAT_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Raw Interrupt General Call - gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_GEN_CALL field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RAW_INTR_STAT. + */ +struct ALT_I2C_RAW_INTR_STAT_s +{ + const uint32_t rx_under : 1; /* I2C Raw Interrupt RX Under */ + const uint32_t rx_over : 1; /* Raw Interrupt RX Over */ + const uint32_t rx_full : 1; /* Raw Interrupt RX Full */ + const uint32_t tx_over : 1; /* Raw Interrupt TX Over */ + const uint32_t tx_empty : 1; /* Raw Interrupt TX Empty */ + const uint32_t rd_req : 1; /* Raw Interrupt Read Request */ + const uint32_t tx_abrt : 1; /* Raw Interrupt TX Abort */ + const uint32_t rx_done : 1; /* Raw Interrupt RX Done */ + const uint32_t activity : 1; /* Raw Interrupt Activity */ + const uint32_t stop_det : 1; /* Raw Interrupt Stop Detect */ + const uint32_t start_det : 1; /* Raw Interrupt Start Detect */ + const uint32_t gen_call : 1; /* Raw Interrupt General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RAW_INTR_STAT. */ +typedef volatile struct ALT_I2C_RAW_INTR_STAT_s ALT_I2C_RAW_INTR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RAW_INTR_STAT register from the beginning of the component. */ +#define ALT_I2C_RAW_INTR_STAT_OFST 0x34 +/* The address of the ALT_I2C_RAW_INTR_STAT register. */ +#define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST)) + +/* + * Register : Receive FIFO Threshold Register - ic_rx_tl + * + * I2C Receive FIFO Threshold Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [7:0] | RW | 0x0 | Receive FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Threshold Level - rx_tl + * + * Controls the level of entries (or above) that triggers the RX_FULL interrupt + * (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the + * additional restriction that hardware does not allow this value to be set to a + * value larger than the depth of the buffer. If an attempt is made to do that, the + * actual value set will be the maximum depth of the buffer. A value of 0 sets the + * threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_MSB 7 +/* The width in bits of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_WIDTH 8 +/* The mask used to set the ALT_I2C_RX_TL_RX_TL register field value. */ +#define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_RX_TL_RX_TL register field value. */ +#define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_RESET 0x0 +/* Extracts the ALT_I2C_RX_TL_RX_TL field value from a register. */ +#define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_RX_TL_RX_TL register field value suitable for setting the register. */ +#define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RX_TL. + */ +struct ALT_I2C_RX_TL_s +{ + uint32_t rx_tl : 8; /* Receive FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RX_TL. */ +typedef volatile struct ALT_I2C_RX_TL_s ALT_I2C_RX_TL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RX_TL register from the beginning of the component. */ +#define ALT_I2C_RX_TL_OFST 0x38 +/* The address of the ALT_I2C_RX_TL register. */ +#define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST)) + +/* + * Register : Transmit FIFO Threshold Level Register - ic_tx_tl + * + * Sets FIFO depth for Interrupt. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [7:0] | RW | 0x0 | Transmit FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Threshold Level - tx_tl + * + * Controls the level of entries (or below) that trigger the TX_EMPTY interrupt + * (bit 4 in ic_raw_intr_stat register). The valid range is 0-255, with the + * additional restriction that it may not be set to value larger than the depth of + * the buffer. If an attempt is made to do that, the actual value set will be the + * maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and + * a value of 255 sets the threshold for 255 entries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_MSB 7 +/* The width in bits of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_WIDTH 8 +/* The mask used to set the ALT_I2C_TX_TL_TX_TL register field value. */ +#define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_TX_TL_TX_TL register field value. */ +#define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_RESET 0x0 +/* Extracts the ALT_I2C_TX_TL_TX_TL field value from a register. */ +#define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_TX_TL_TX_TL register field value suitable for setting the register. */ +#define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TX_TL. + */ +struct ALT_I2C_TX_TL_s +{ + uint32_t tx_tl : 8; /* Transmit FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TX_TL. */ +typedef volatile struct ALT_I2C_TX_TL_s ALT_I2C_TX_TL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TX_TL register from the beginning of the component. */ +#define ALT_I2C_TX_TL_OFST 0x3c +/* The address of the ALT_I2C_TX_TL register. */ +#define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST)) + +/* + * Register : Combined and Individual Interrupt Register - ic_clr_intr + * + * Controls Interrupts + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Combined and Individual Interrupt Bits + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Combined and Individual Interrupt Bits - clr_intr + * + * Read this register to clear the combined interrupt, all individual interrupts, + * and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable + * interrupts but software clearable interrupts. Refer to Bit 9 of the + * ic_tx_abrt_source register for an exception to clearing ic_tx_abrt_source. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0 +/* The width in bits of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0 +/* Extracts the ALT_I2C_CLR_INTR_CLR_INTR field value from a register. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_INTR_CLR_INTR register field value suitable for setting the register. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_INTR. + */ +struct ALT_I2C_CLR_INTR_s +{ + const uint32_t clr_intr : 1; /* Combined and Individual Interrupt Bits */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_INTR. */ +typedef volatile struct ALT_I2C_CLR_INTR_s ALT_I2C_CLR_INTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_INTR register from the beginning of the component. */ +#define ALT_I2C_CLR_INTR_OFST 0x40 +/* The address of the ALT_I2C_CLR_INTR register. */ +#define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST)) + +/* + * Register : Rx Under Interrupt Register - ic_clr_rx_under + * + * Rx Under Interrupt Bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | R | 0x0 | Clear Rx Under Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Rx Under Interrupt Bit - clr_rx_under + * + * Read this register to clear the RX_UNDER interrupt bit 0 of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER field value from a register. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_UNDER. + */ +struct ALT_I2C_CLR_RX_UNDER_s +{ + const uint32_t clr_rx_under : 1; /* Clear Rx Under Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_UNDER. */ +typedef volatile struct ALT_I2C_CLR_RX_UNDER_s ALT_I2C_CLR_RX_UNDER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_UNDER register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_UNDER_OFST 0x44 +/* The address of the ALT_I2C_CLR_RX_UNDER register. */ +#define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST)) + +/* + * Register : RX Over Interrupt Register - ic_clr_rx_over + * + * Clears Rx over Interrupt Bit + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | RX Over Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RX Over Interrupt Bit - clr_rx_over + * + * Read this register to clear the RX_OVER interrupt bit 1 of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER field value from a register. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_OVER. + */ +struct ALT_I2C_CLR_RX_OVER_s +{ + const uint32_t clr_rx_over : 1; /* RX Over Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_OVER. */ +typedef volatile struct ALT_I2C_CLR_RX_OVER_s ALT_I2C_CLR_RX_OVER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_OVER register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_OVER_OFST 0x48 +/* The address of the ALT_I2C_CLR_RX_OVER register. */ +#define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST)) + +/* + * Register : TX Over Interrupt Register - ic_clr_tx_over + * + * Clears Over Interrupts + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | TX Over Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : TX Over Interrupt Bit - clr_tx_over + * + * Read this register to clear the TX_OVER interrupt (bit 3) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER field value from a register. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_TX_OVER. + */ +struct ALT_I2C_CLR_TX_OVER_s +{ + const uint32_t clr_tx_over : 1; /* TX Over Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_TX_OVER. */ +typedef volatile struct ALT_I2C_CLR_TX_OVER_s ALT_I2C_CLR_TX_OVER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_TX_OVER register from the beginning of the component. */ +#define ALT_I2C_CLR_TX_OVER_OFST 0x4c +/* The address of the ALT_I2C_CLR_TX_OVER register. */ +#define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST)) + +/* + * Register : Interrupt Read Request Register - ic_clr_rd_req + * + * Clear RD_REQ Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | R | 0x0 | Interrupt Register Read Request Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Register Read Request Bit - clr_rd_req + * + * Read this register to clear the RD_REQ interrupt (bit 5) of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ field value from a register. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RD_REQ. + */ +struct ALT_I2C_CLR_RD_REQ_s +{ + const uint32_t clr_rd_req : 1; /* Interrupt Register Read Request Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RD_REQ. */ +typedef volatile struct ALT_I2C_CLR_RD_REQ_s ALT_I2C_CLR_RD_REQ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RD_REQ register from the beginning of the component. */ +#define ALT_I2C_CLR_RD_REQ_OFST 0x50 +/* The address of the ALT_I2C_CLR_RD_REQ register. */ +#define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST)) + +/* + * Register : Tx Abort Interrupt Register - ic_clr_tx_abrt + * + * Clear TX_ABRT Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | Tx Abort Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Tx Abort Interrupt Bit - clr_tx_abort + * + * Read this register to clear the TX_ABRT interrupt (bit 6) of the + * ic_raw_intr_stat register, and the ic_tx_abrt_source register. This also + * releases the TX FIFO from the flushed/reset state, allowing more writes to the + * TX FIFO. Refer to Bit 9 of the ic_tx_abrt_source register for an exception to + * clearing ic_tx_abrt_source. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0 +/* The width in bits of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0 +/* Extracts the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT field value from a register. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value suitable for setting the register. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_TX_ABRT. + */ +struct ALT_I2C_CLR_TX_ABRT_s +{ + const uint32_t clr_tx_abort : 1; /* Tx Abort Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_TX_ABRT. */ +typedef volatile struct ALT_I2C_CLR_TX_ABRT_s ALT_I2C_CLR_TX_ABRT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_TX_ABRT register from the beginning of the component. */ +#define ALT_I2C_CLR_TX_ABRT_OFST 0x54 +/* The address of the ALT_I2C_CLR_TX_ABRT register. */ +#define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST)) + +/* + * Register : Rx Done Interrupt Register - ic_clr_rx_done + * + * Clear RX_DONE Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | RX_DONE Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RX_DONE Interrupt Bit - clr_rx_done + * + * Read this register to clear the RX_DONE interrupt (bit 7) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE field value from a register. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_DONE. + */ +struct ALT_I2C_CLR_RX_DONE_s +{ + const uint32_t clr_rx_done : 1; /* RX_DONE Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_DONE. */ +typedef volatile struct ALT_I2C_CLR_RX_DONE_s ALT_I2C_CLR_RX_DONE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_DONE register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_DONE_OFST 0x58 +/* The address of the ALT_I2C_CLR_RX_DONE register. */ +#define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST)) + +/* + * Register : Activity Interrupt Register - ic_clr_activity + * + * Clears ACTIVITY Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | Activity Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Activity Interrupt Bit - clr_activity + * + * Reading this register clears the ACTIVITY interrupt if the I2C is not active + * anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt + * bit continues to be set. It is automatically cleared by hardware if the module + * is disabled and if there is no further activity on the bus. The value read from + * this register to get status of the ACTIVITY interrupt (bit 8) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0 +/* The width in bits of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY field value from a register. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_ACTIVITY. + */ +struct ALT_I2C_CLR_ACTIVITY_s +{ + const uint32_t clr_activity : 1; /* Activity Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_ACTIVITY. */ +typedef volatile struct ALT_I2C_CLR_ACTIVITY_s ALT_I2C_CLR_ACTIVITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_ACTIVITY register from the beginning of the component. */ +#define ALT_I2C_CLR_ACTIVITY_OFST 0x5c +/* The address of the ALT_I2C_CLR_ACTIVITY register. */ +#define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST)) + +/* + * Register : Stop Detect Interrupt Register - ic_clr_stop_det + * + * Clear Interrupts. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [0] | R | 0x0 | Stop Detect Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Stop Detect Interrupt Bit - clr_stop_det + * + * Read this register to clear the clr_stop_det interrupt (bit 9) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0 +/* The width in bits of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET field value from a register. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_STOP_DET. + */ +struct ALT_I2C_CLR_STOP_DET_s +{ + const uint32_t clr_stop_det : 1; /* Stop Detect Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_STOP_DET. */ +typedef volatile struct ALT_I2C_CLR_STOP_DET_s ALT_I2C_CLR_STOP_DET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_STOP_DET register from the beginning of the component. */ +#define ALT_I2C_CLR_STOP_DET_OFST 0x60 +/* The address of the ALT_I2C_CLR_STOP_DET register. */ +#define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST)) + +/* + * Register : Start Detect Interrupt Register - ic_clr_start_det + * + * Clears START_DET Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | R | 0x0 | Start Detect Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Detect Interrupt Bit - clr_start_det + * + * Read this register to clear the start_det interrupt (bit 10) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0 +/* The width in bits of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_CLR_START_DET_CLR_START_DET field value from a register. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_START_DET_CLR_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_START_DET. + */ +struct ALT_I2C_CLR_START_DET_s +{ + const uint32_t clr_start_det : 1; /* Start Detect Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_START_DET. */ +typedef volatile struct ALT_I2C_CLR_START_DET_s ALT_I2C_CLR_START_DET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_START_DET register from the beginning of the component. */ +#define ALT_I2C_CLR_START_DET_OFST 0x64 +/* The address of the ALT_I2C_CLR_START_DET register. */ +#define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST)) + +/* + * Register : GEN CALL Interrupt Register - ic_clr_gen_call + * + * Clear GEN_CALL Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | GEN CALL Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GEN CALL Interrupt Bit - clr_gen_call + * + * Read this register to clear the GEN_CALL interrupt (bit 11) of ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0 +/* The width in bits of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL field value from a register. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_GEN_CALL. + */ +struct ALT_I2C_CLR_GEN_CALL_s +{ + const uint32_t clr_gen_call : 1; /* GEN CALL Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_GEN_CALL. */ +typedef volatile struct ALT_I2C_CLR_GEN_CALL_s ALT_I2C_CLR_GEN_CALL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_GEN_CALL register from the beginning of the component. */ +#define ALT_I2C_CLR_GEN_CALL_OFST 0x68 +/* The address of the ALT_I2C_CLR_GEN_CALL register. */ +#define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST)) + +/* + * Register : Enable Register - ic_enable + * + * Enable and disable i2c operation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Enable Bit + * [1] | RW | 0x0 | TX abort Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable Bit - enable + * + * Controls whether the I2C is enabled. Software can disable I2C while it is + * active. However, it is important that care be taken to ensure that I2C is + * disabled properly. When the I2C is disabled, the following occurs: + * + * The TX FIFO and RX FIFO get flushed. Status bits in the IC_INTR_STAT register + * are still active until I2C goes into IDLE state. If the module is transmitting, + * it stops as well as deletes the contents of the transmit buffer after the + * current transfer is complete. If the module is receiving, the I2C stops the + * current transfer at the end of the current byte and does not acknowledge the + * transfer. The l4_sp_clk synchronizes pclk and ic_clk. The register + * ic_enable_status is added to allow software to determine when the hardware has + * completely shutdown in response to the IC_ENABLE register being set from 1 to 0. + * Only one register is required to be monitored. Procedure for Disabling I2C + * + * 1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling + * period for the highest I2C transfer speed used in the system and supported by + * I2C. For example, if the highest I2C transfer mode is 400 kb/s, then this + * ti2c_poll is 25us. + * + * 2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any + * repeated polling operation exceeds this maximum value, an error is reported. 3. + * Execute a blocking thread/process/function that prevents any further I2C master + * transactions to be started by software, but allows any pending transfers to be + * completed. + * + * 4. The variable POLL_COUNT is initialized to zero. 5. Set IC_ENABLE to 0. + * + * 6. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment + * POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant + * error code. + * + * 7. If IC_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the + * previous step. Otherwise, exit with a relevant success code. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------|:------|:----------------------------------------------- + * ALT_I2C_EN_EN_E_DIS | 0x0 | Disables i2c. TX and RX FIFOs are held in an + * : | | erased state + * ALT_I2C_EN_EN_E_EN | 0x1 | Enables i2c. Software can disable i2c while it + * : | | is active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_EN_EN + * + * Disables i2c. TX and RX FIFOs are held in an erased state + */ +#define ALT_I2C_EN_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_EN_EN + * + * Enables i2c. Software can disable i2c while it is active + */ +#define ALT_I2C_EN_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_MSB 0 +/* The width in bits of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_EN register field value. */ +#define ALT_I2C_EN_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_EN_EN register field value. */ +#define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_RESET 0x0 +/* Extracts the ALT_I2C_EN_EN field value from a register. */ +#define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_EN_EN register field value suitable for setting the register. */ +#define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TX abort Bit - txabort + * + * Write 1 does a TX abort. Self cleared on abort completion + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_MSB 1 +/* The width in bits of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_TXABT register field value. */ +#define ALT_I2C_EN_TXABT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_EN_TXABT register field value. */ +#define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_RESET 0x0 +/* Extracts the ALT_I2C_EN_TXABT field value from a register. */ +#define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_EN_TXABT register field value suitable for setting the register. */ +#define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_EN. + */ +struct ALT_I2C_EN_s +{ + uint32_t enable : 1; /* Enable Bit */ + uint32_t txabort : 1; /* TX abort Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_EN. */ +typedef volatile struct ALT_I2C_EN_s ALT_I2C_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_EN register from the beginning of the component. */ +#define ALT_I2C_EN_OFST 0x6c +/* The address of the ALT_I2C_EN register. */ +#define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST)) + +/* + * Register : Status Register - ic_status + * + * This is a read-only register used to indicate the current transfer status and + * FIFO status. The status register may be read at any time. None of the bits in + * this register request an interrupt.When the I2C is disabled by writing 0 in bit + * 0 of the ic_enable register: + * + * * Bits 1 and 2 are set to 1 + * + * * Bits 3 and 4 are set to 0 + * + * When the master or slave state machines goes to idle + * + * * Bits 5 and 6 are set to 0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | R | 0x0 | Activity Status Bit + * [1] | R | 0x1 | TX FIFO Not Full Bit + * [2] | R | 0x1 | TX FIFO Empty Bit + * [3] | R | 0x0 | RX FIFO Empty Bit + * [4] | R | 0x0 | RX FIFO Full Bit + * [5] | R | 0x0 | Master FSM Activity Status Bit + * [6] | R | 0x0 | Slave FSM Activity Status Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Activity Status Bit - activity + * + * I2C Activity. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_MSB 0 +/* The width in bits of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_ACTIVITY register field value. */ +#define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_STAT_ACTIVITY register field value. */ +#define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_STAT_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TX FIFO Not Full Bit - tfnf + * + * Transmit Fifo Full + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------------------- + * ALT_I2C_STAT_TFNF_E_FULL | 0x0 | Transmit FIFO is full + * ALT_I2C_STAT_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_TFNF + * + * Transmit FIFO is full + */ +#define ALT_I2C_STAT_TFNF_E_FULL 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_TFNF + * + * Transmit FIFO is not full + */ +#define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_MSB 1 +/* The width in bits of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_TFNF register field value. */ +#define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_STAT_TFNF register field value. */ +#define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_RESET 0x1 +/* Extracts the ALT_I2C_STAT_TFNF field value from a register. */ +#define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_STAT_TFNF register field value suitable for setting the register. */ +#define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : TX FIFO Empty Bit - tfe + * + * Transmit FIFO Empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_I2C_STAT_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty + * ALT_I2C_STAT_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_TFE + * + * Transmit FIFO is not empty + */ +#define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_TFE + * + * Transmit FIFO is empty + */ +#define ALT_I2C_STAT_TFE_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_MSB 2 +/* The width in bits of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_TFE register field value. */ +#define ALT_I2C_STAT_TFE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_STAT_TFE register field value. */ +#define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_RESET 0x1 +/* Extracts the ALT_I2C_STAT_TFE field value from a register. */ +#define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_STAT_TFE register field value suitable for setting the register. */ +#define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : RX FIFO Empty Bit - rfne + * + * Receive FIFO Not Empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------- + * ALT_I2C_STAT_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty + * ALT_I2C_STAT_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_RFNE + * + * Receive FIFO is empty + */ +#define ALT_I2C_STAT_RFNE_E_EMPTY 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_RFNE + * + * Receive FIFO is not empty + */ +#define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_MSB 3 +/* The width in bits of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_RFNE register field value. */ +#define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_STAT_RFNE register field value. */ +#define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_RESET 0x0 +/* Extracts the ALT_I2C_STAT_RFNE field value from a register. */ +#define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_STAT_RFNE register field value suitable for setting the register. */ +#define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : RX FIFO Full Bit - rff + * + * Receive FIFO Completely Full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:------------------------- + * ALT_I2C_STAT_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full + * ALT_I2C_STAT_RFF_E_FULL | 0x1 | Receive FIFO is full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_RFF + * + * Receive FIFO is not full + */ +#define ALT_I2C_STAT_RFF_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_RFF + * + * Receive FIFO is full + */ +#define ALT_I2C_STAT_RFF_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_MSB 4 +/* The width in bits of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_RFF register field value. */ +#define ALT_I2C_STAT_RFF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_STAT_RFF register field value. */ +#define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_RESET 0x0 +/* Extracts the ALT_I2C_STAT_RFF field value from a register. */ +#define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_STAT_RFF register field value suitable for setting the register. */ +#define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Master FSM Activity Status Bit - mst_activity + * + * When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is + * set. Note:IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and + * MST_ACTIVITY bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------ + * ALT_I2C_STAT_MST_ACTIVITY_E_IDLE | 0x0 | Master FSM is in IDLE state. Master part of i2c + * : | | is not Active + * ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE | 0x1 | Master FSM is not in IDLE state. Master part of + * : | | i2c is Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY + * + * Master FSM is in IDLE state. Master part of i2c is not Active + */ +#define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY + * + * Master FSM is not in IDLE state. Master part of i2c is Active + */ +#define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_MSB 5 +/* The width in bits of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_MST_ACTIVITY register field value. */ +#define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_STAT_MST_ACTIVITY register field value. */ +#define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_MST_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_STAT_MST_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Slave FSM Activity Status Bit - slv_activity + * + * Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in + * the IDLE state, this bit is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE | 0x0 | Slave FSM is in IDLE state so the Slave part of + * : | | i2c is not Active + * ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE | 0x1 | Slave FSM is not in IDLE state so the Slave part + * : | | of i2c is Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY + * + * Slave FSM is in IDLE state so the Slave part of i2c is not Active + */ +#define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY + * + * Slave FSM is not in IDLE state so the Slave part of i2c is Active + */ +#define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6 +/* The width in bits of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_SLV_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_STAT_SLV_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_STAT. + */ +struct ALT_I2C_STAT_s +{ + const uint32_t activity : 1; /* Activity Status Bit */ + const uint32_t tfnf : 1; /* TX FIFO Not Full Bit */ + const uint32_t tfe : 1; /* TX FIFO Empty Bit */ + const uint32_t rfne : 1; /* RX FIFO Empty Bit */ + const uint32_t rff : 1; /* RX FIFO Full Bit */ + const uint32_t mst_activity : 1; /* Master FSM Activity Status Bit */ + const uint32_t slv_activity : 1; /* Slave FSM Activity Status Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_STAT. */ +typedef volatile struct ALT_I2C_STAT_s ALT_I2C_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_STAT register from the beginning of the component. */ +#define ALT_I2C_STAT_OFST 0x70 +/* The address of the ALT_I2C_STAT register. */ +#define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST)) + +/* + * Register : Transmit FIFO Level Register - ic_txflr + * + * This register contains the number of valid data entries in the transmit FIFO + * buffer. It is cleared whenever: + * + * * The I2C is disabled + * + * * There is a transmit abort that is, TX_ABRT bit is set in the ic_raw_intr_stat + * register. The slave bulk transmit mode is aborted The register increments + * whenever data is placed into the transmit FIFO and decrements when data is + * taken from the transmit FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [6:0] | R | 0x0 | Transmit FIFO Level Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Level Bit - txflr + * + * Transmit FIFO Level.Contains the number of valid data entries in the transmit + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_MSB 6 +/* The width in bits of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_WIDTH 7 +/* The mask used to set the ALT_I2C_TXFLR_TXFLR register field value. */ +#define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_I2C_TXFLR_TXFLR register field value. */ +#define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_RESET 0x0 +/* Extracts the ALT_I2C_TXFLR_TXFLR field value from a register. */ +#define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_I2C_TXFLR_TXFLR register field value suitable for setting the register. */ +#define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TXFLR. + */ +struct ALT_I2C_TXFLR_s +{ + const uint32_t txflr : 7; /* Transmit FIFO Level Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TXFLR. */ +typedef volatile struct ALT_I2C_TXFLR_s ALT_I2C_TXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TXFLR register from the beginning of the component. */ +#define ALT_I2C_TXFLR_OFST 0x74 +/* The address of the ALT_I2C_TXFLR register. */ +#define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST)) + +/* + * Register : Receive FIFO Level Register - ic_rxflr + * + * This register contains the number of valid data entries in the receive FIFO + * buffer. It is cleared whenever: + * + * * The I2C is disabled + * + * * Whenever there is a transmit abort caused by any of the events tracked in + * ic_tx_abrt_source The register increments whenever data is placed into the + * receive FIFO and decrements when data is taken from the receive FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [6:0] | R | 0x0 | Receive FIFO Level Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Level Bit - rxflr + * + * Receive FIFO Level. Contains the number of valid data entries in the receive + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_MSB 6 +/* The width in bits of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_WIDTH 7 +/* The mask used to set the ALT_I2C_RXFLR_RXFLR register field value. */ +#define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_I2C_RXFLR_RXFLR register field value. */ +#define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_RESET 0x0 +/* Extracts the ALT_I2C_RXFLR_RXFLR field value from a register. */ +#define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_I2C_RXFLR_RXFLR register field value suitable for setting the register. */ +#define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RXFLR. + */ +struct ALT_I2C_RXFLR_s +{ + const uint32_t rxflr : 7; /* Receive FIFO Level Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RXFLR. */ +typedef volatile struct ALT_I2C_RXFLR_s ALT_I2C_RXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RXFLR register from the beginning of the component. */ +#define ALT_I2C_RXFLR_OFST 0x78 +/* The address of the ALT_I2C_RXFLR register. */ +#define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST)) + +/* + * Register : SDA Hold Register - ic_sda_hold + * + * This register controls the amount of time delay (in terms of number of l4_sp_clk + * clock periods) introduced in the falling edge of SCL, relative to SDA changing, + * when I2C services a read request in a slave-transmitter operation. The relevant + * I2C requirement is thd:DAT as detailed in the I2C Bus Specification. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------- + * [15:0] | RW | 0x1 | SDA Hold Bit + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDA Hold Bit - ic_sda_hold + * + * Program to a minimum 0f 300ns. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_MSB 15 +/* The width in bits of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_WIDTH 16 +/* The mask used to set the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_RESET 0x1 +/* Extracts the ALT_I2C_SDA_HOLD_IC_SDA_HOLD field value from a register. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value suitable for setting the register. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SDA_HOLD. + */ +struct ALT_I2C_SDA_HOLD_s +{ + uint32_t ic_sda_hold : 16; /* SDA Hold Bit */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SDA_HOLD. */ +typedef volatile struct ALT_I2C_SDA_HOLD_s ALT_I2C_SDA_HOLD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SDA_HOLD register from the beginning of the component. */ +#define ALT_I2C_SDA_HOLD_OFST 0x7c +/* The address of the ALT_I2C_SDA_HOLD register. */ +#define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST)) + +/* + * Register : Transmit Abort Source Register - ic_tx_abrt_source + * + * This register has 16 bits that indicate the source of the TX_ABRT bit. Except + * for Bit 9, this register is cleared whenever the ic_clr_tx_abrt register or the + * ic_clr_intr register is read. To clear Bit 9, the source of the + * abrt_sbyte_norstrt must be fixed first; RESTART must be enabled (ic_con[5]=1), + * the special bit must be cleared (ic_tar[11]), or the gc_or_start bit must be + * cleared (ic_tar[10]). Once the source of the abrt_sbyte_norstrt is fixed, then + * this bit can be cleared in the same manner as other bits in this register. If + * the source of the abrt_sbyte_norstrt is not fixed before attempting to clear + * this bit, Bit 9 clears for one cycle and is then re-asserted. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | Master Abort 7 Bit Address + * [1] | RW | 0x0 | Master Abort 10 Bit Address Byte 1 + * [2] | RW | 0x0 | Master Abort 10 Bit Address Byte 2 + * [3] | RW | 0x0 | Master Abort TX Noack Bit + * [4] | RW | 0x0 | Master Abort GC Noack Bit + * [5] | RW | 0x0 | Master Abort GC Read Bit + * [6] | RW | 0x0 | Master HS MC Ack + * [7] | RW | 0x0 | Master Abort START Byte + * [8] | RW | 0x0 | Master HS Restart Disabled + * [9] | RW | 0x0 | Master Abort START No Restart + * [10] | RW | 0x0 | Master Abort 10 Bit No Restart + * [11] | RW | 0x0 | Master Oper Master Dis + * [12] | RW | 0x0 | Master Abort Arbitration Lost + * [13] | RW | 0x0 | Slave Abort Flush TXFIFO + * [14] | RW | 0x0 | Slave Abort Arbitration Lost + * [15] | RW | 0x0 | Slave Abort Read TX + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Abort 7 Bit Address - abrt_7b_addr_noack + * + * Master is in 7-bit addressing mode and the address sent was not acknowledged by + * any slave. Role of i2c: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Master Abort 10 Bit Address Byte 1 - abrt_10addr1_noack + * + * Master is in 10-bit address mode and the first 10-bit address byte was not + * acknowledged by any slave. Role of i2c: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Master Abort 10 Bit Address Byte 2 - abrt_10addr2_noack + * + * Master is in 10-bit address mode and the second address byte of the 10-bit + * address was not acknowledged by any slave. Role of i2c: Master-Transmitter or + * Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Master Abort TX Noack Bit - abrt_txdata_noack + * + * This is a master-mode only bit. Master has received an acknowledgement for the + * address, but when it sent data byte(s) following the address, it did not receive + * an acknowledge from the remote slave(s). Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Master Abort GC Noack Bit - abrt_gcall_noack + * + * i2c in master mode sent a General Call and no slave on the bus acknowledged the + * General Call. Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Master Abort GC Read Bit - abrt_gcall_read + * + * i2c in master mode sent a General Call but the user programmed the byte + * following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to + * 1). Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Master HS MC Ack - abrt_hs_ackdet + * + * Master is in High Speed mode and the High Speed Master code was acknowledged + * (wrong behavior). Role of i2c: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Master Abort START Byte - abrt_sbyte_ackdet + * + * Master has sent a START Byte and the START Byte was acknowledged (wrong + * behavior). Role of i2c: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Master HS Restart Disabled - abrt_hs_norstrt + * + * The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is + * trying to use the master to transfer data in High Speed mode. Role of i2c: + * Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Master Abort START No Restart - abrt_sbyte_norstrt + * + * To clear Bit 9, the source of then abrt_sbyte_norstrt must be fixed first; + * restart must be enabled (ic_con[5]=1), the SPECIAL bit must be cleared + * (ic_tar[11]), or the GC_OR_START bit must be cleared (ic_tar[10]). Once the + * source of the abrt_sbyte_norstrt is fixed, then this bit can be cleared in the + * same manner as other bits in this register. If the source of the + * abrt_sbyte_norstrt is not fixed before attempting to clear this bit, bit 9 + * clears for one cycle and then gets reasserted. 1: The restart is disabled + * (IC_RESTART_EN bit (ic_con[5]) =0) and the user is trying to send a START Byte. + * Role of I2C: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Master Abort 10 Bit No Restart - abrt_10b_rd_norstrt + * + * The restart is disabled (ic_restart_en bit (ic_con[5]) =0) and the master sends + * a read command in 10-bit addressing mode. Role of I2C: Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Master Oper Master Dis - abrt_master_dis + * + * User tries to initiate a Master operation with the Master mode disabled. Role of + * I2C: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Master Abort Arbitration Lost - arb_lost + * + * Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the + * slave transmitter has lost arbitration. Note: I2C can be both master and slave + * at the same time. Role of i2c: Master-Transmitter or Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ARB_LOST field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Slave Abort Flush TXFIFO - abrt_slvflush_txfifo + * + * Slave has received a read command and some data exists in the TX FIFO so the + * slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Role of I2C: + * Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Slave Abort Arbitration Lost - abrt_slv_arblost + * + * Slave lost the bus while transmitting data to a remote master. + * IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never + * 'owns' the bus, something could go wrong on the bus. This is a fail safe check. + * For instance, during a data transmission at the low-to-high transition of SCL, + * if what is on the data bus is not what is supposed to be transmitted, then i2c + * no longer own the bus. Role of I2C: Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Slave Abort Read TX - abrt_slvrd_intx + * + * When the processor side responds to a slave mode request for data to be + * transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD + * register. Role of I2C: Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TX_ABRT_SRC. + */ +struct ALT_I2C_TX_ABRT_SRC_s +{ + uint32_t abrt_7b_addr_noack : 1; /* Master Abort 7 Bit Address */ + uint32_t abrt_10addr1_noack : 1; /* Master Abort 10 Bit Address Byte 1 */ + uint32_t abrt_10addr2_noack : 1; /* Master Abort 10 Bit Address Byte 2 */ + uint32_t abrt_txdata_noack : 1; /* Master Abort TX Noack Bit */ + uint32_t abrt_gcall_noack : 1; /* Master Abort GC Noack Bit */ + uint32_t abrt_gcall_read : 1; /* Master Abort GC Read Bit */ + uint32_t abrt_hs_ackdet : 1; /* Master HS MC Ack */ + uint32_t abrt_sbyte_ackdet : 1; /* Master Abort START Byte */ + uint32_t abrt_hs_norstrt : 1; /* Master HS Restart Disabled */ + uint32_t abrt_sbyte_norstrt : 1; /* Master Abort START No Restart */ + uint32_t abrt_10b_rd_norstrt : 1; /* Master Abort 10 Bit No Restart */ + uint32_t abrt_master_dis : 1; /* Master Oper Master Dis */ + uint32_t arb_lost : 1; /* Master Abort Arbitration Lost */ + uint32_t abrt_slvflush_txfifo : 1; /* Slave Abort Flush TXFIFO */ + uint32_t abrt_slv_arblost : 1; /* Slave Abort Arbitration Lost */ + uint32_t abrt_slvrd_intx : 1; /* Slave Abort Read TX */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TX_ABRT_SRC. */ +typedef volatile struct ALT_I2C_TX_ABRT_SRC_s ALT_I2C_TX_ABRT_SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TX_ABRT_SRC register from the beginning of the component. */ +#define ALT_I2C_TX_ABRT_SRC_OFST 0x80 +/* The address of the ALT_I2C_TX_ABRT_SRC register. */ +#define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST)) + +/* + * Register : Generate Slave Data NACK - ic_slv_data_nack_only + * + * The register is used to generate a NACK for the data part of a transfer when i2c + * is acting as a slave-receiver. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [0] | RW | 0x0 | Generate Nack Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Generate Nack Bit - nack + * + * This Bit control Nack generation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:-------------------------------------- + * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE | 0x1 | Generate NACK after data byte receive + * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM | 0x0 | Generate NACK/ACK normally + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK + * + * Generate NACK after data byte receive + */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1 +/* + * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK + * + * Generate NACK/ACK normally + */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0 +/* The width in bits of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1 +/* The mask used to set the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0 +/* Extracts the ALT_I2C_SLV_DATA_NACK_ONLY_NACK field value from a register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value suitable for setting the register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. + */ +struct ALT_I2C_SLV_DATA_NACK_ONLY_s +{ + uint32_t nack : 1; /* Generate Nack Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. */ +typedef volatile struct ALT_I2C_SLV_DATA_NACK_ONLY_s ALT_I2C_SLV_DATA_NACK_ONLY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SLV_DATA_NACK_ONLY register from the beginning of the component. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84 +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST)) + +/* + * Register : DMA Control - ic_dma_cr + * + * The register is used to enable the DMA Controller interface operation. There is + * a separate bit for transmit and receive. This can be programmed regardless of + * the state of IC_ENABLE. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | Receive DMA Enable Bit + * [1] | RW | 0x0 | Transmit DMA Enable Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive DMA Enable Bit - rdmae + * + * This bit enables/disables the receive FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------- + * ALT_I2C_DMA_CR_RDMAE_E_DIS | 0x0 | Receive DMA disable + * ALT_I2C_DMA_CR_RDMAE_E_EN | 0x1 | Receive DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE + * + * Receive DMA disable + */ +#define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE + * + * Receive DMA enabled + */ +#define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_MSB 0 +/* The width in bits of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_WIDTH 1 +/* The mask used to set the ALT_I2C_DMA_CR_RDMAE register field value. */ +#define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_DMA_CR_RDMAE register field value. */ +#define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_RESET 0x0 +/* Extracts the ALT_I2C_DMA_CR_RDMAE field value from a register. */ +#define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_DMA_CR_RDMAE register field value suitable for setting the register. */ +#define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit DMA Enable Bit - tdmae + * + * This bit enables/disables the transmit FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------- + * ALT_I2C_DMA_CR_TDMAE_E_DIS | 0x0 | Transmit DMA disable + * ALT_I2C_DMA_CR_TDMAE_E_EN | 0x1 | Transmit DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE + * + * Transmit DMA disable + */ +#define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE + * + * Transmit DMA enabled + */ +#define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_MSB 1 +/* The width in bits of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_WIDTH 1 +/* The mask used to set the ALT_I2C_DMA_CR_TDMAE register field value. */ +#define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_DMA_CR_TDMAE register field value. */ +#define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_RESET 0x0 +/* Extracts the ALT_I2C_DMA_CR_TDMAE field value from a register. */ +#define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_DMA_CR_TDMAE register field value suitable for setting the register. */ +#define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_CR. + */ +struct ALT_I2C_DMA_CR_s +{ + uint32_t rdmae : 1; /* Receive DMA Enable Bit */ + uint32_t tdmae : 1; /* Transmit DMA Enable Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_CR. */ +typedef volatile struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_CR register from the beginning of the component. */ +#define ALT_I2C_DMA_CR_OFST 0x88 +/* The address of the ALT_I2C_DMA_CR register. */ +#define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST)) + +/* + * Register : DMA Transmit Data Level - ic_dma_tdlr + * + * This register supports DMA Transmit Operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [5:0] | RW | 0x0 | DMA Transmit Data Level Bit + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DMA Transmit Data Level Bit - dmatdl + * + * This bit field controls the level at which a DMA request is made by the transmit + * logic. It is equal to the watermark level; that is, the i2c_dma_tx_req signal is + * generated when the number of valid data entries in the transmit FIFO is equal to + * or below this field value, and TDMAE = 1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_MSB 5 +/* The width in bits of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6 +/* The mask used to set the ALT_I2C_DMA_TDLR_DMATDL register field value. */ +#define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f +/* The mask used to clear the ALT_I2C_DMA_TDLR_DMATDL register field value. */ +#define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0 +/* Extracts the ALT_I2C_DMA_TDLR_DMATDL field value from a register. */ +#define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_I2C_DMA_TDLR_DMATDL register field value suitable for setting the register. */ +#define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_TDLR. + */ +struct ALT_I2C_DMA_TDLR_s +{ + uint32_t dmatdl : 6; /* DMA Transmit Data Level Bit */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_TDLR. */ +typedef volatile struct ALT_I2C_DMA_TDLR_s ALT_I2C_DMA_TDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_TDLR register from the beginning of the component. */ +#define ALT_I2C_DMA_TDLR_OFST 0x8c +/* The address of the ALT_I2C_DMA_TDLR register. */ +#define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST)) + +/* + * Register : Receive Data Level - ic_dma_rdlr + * + * DMA Control Signals Interface. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [5:0] | RW | 0x0 | Receive Data Level Bits + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive Data Level Bits - dmardl + * + * This bit field controls the level at which a DMA request is made by the receive + * logic. The watermark level \= DMARDL+1; that is, dma_rx_req is generated when + * the number of valid data entries in the receive FIFO is equal to or more than + * this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then + * dma_rx_req is asserted when or more data entries are present in the receive + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_MSB 5 +/* The width in bits of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6 +/* The mask used to set the ALT_I2C_DMA_RDLR_DMARDL register field value. */ +#define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f +/* The mask used to clear the ALT_I2C_DMA_RDLR_DMARDL register field value. */ +#define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0 +/* Extracts the ALT_I2C_DMA_RDLR_DMARDL field value from a register. */ +#define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_I2C_DMA_RDLR_DMARDL register field value suitable for setting the register. */ +#define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_RDLR. + */ +struct ALT_I2C_DMA_RDLR_s +{ + uint32_t dmardl : 6; /* Receive Data Level Bits */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_RDLR. */ +typedef volatile struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_RDLR register from the beginning of the component. */ +#define ALT_I2C_DMA_RDLR_OFST 0x90 +/* The address of the ALT_I2C_DMA_RDLR register. */ +#define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST)) + +/* + * Register : SDA Setup Register - ic_sda_setup + * + * This register controls the amount of time delay (in terms of number of l4_sp_clk + * clock periods) introduced in the rising edge of SCL relative to SDA changing by + * holding SCL low when I2C services a read request while operating as a slave- + * transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the + * I2C Bus Specification. This register must be programmed with a value equal to or + * greater than 2. + * + * Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * + * (l4_sp_clk)], so if the user requires 10 l4_sp_clk periods of setup time, they + * should program a value of 11. The IC_SDA_SETUP register is only used by the I2C + * when operating as a slave transmitter. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [7:0] | RW | 0x64 | SDA Setup Value + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDA Setup Value - sda_setup + * + * It is recommended that if the required delay is 1000ns, then for an l4_sp_clk + * frequency of 10 MHz, ic_sda_setup should be programmed to a value of 11. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7 +/* The width in bits of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8 +/* The mask used to set the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64 +/* Extracts the ALT_I2C_SDA_SETUP_SDA_SETUP field value from a register. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_SDA_SETUP_SDA_SETUP register field value suitable for setting the register. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SDA_SETUP. + */ +struct ALT_I2C_SDA_SETUP_s +{ + uint32_t sda_setup : 8; /* SDA Setup Value */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SDA_SETUP. */ +typedef volatile struct ALT_I2C_SDA_SETUP_s ALT_I2C_SDA_SETUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SDA_SETUP register from the beginning of the component. */ +#define ALT_I2C_SDA_SETUP_OFST 0x94 +/* The address of the ALT_I2C_SDA_SETUP register. */ +#define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST)) + +/* + * Register : ACK General Call - ic_ack_general_call + * + * The register controls whether i2c responds with a ACK or NACK when it receives + * an I2C General Call address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | ACK General Call Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ACK General Call Bit - ack_gen_call + * + * When an ACK is asserted, (by asserting i2c_out_data) when it receives a General + * call. Otherwise, i2c responds with a NACK (by negating i2c_out_data). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------- + * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK | 0x0 | I2C responds with a NACK + * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK | 0x1 | I2C responds with an ACK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL + * + * I2C responds with a NACK + */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0 +/* + * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL + * + * I2C responds with an ACK + */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0 +/* The width in bits of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1 +/* Extracts the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL field value from a register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_ACK_GENERAL_CALL. + */ +struct ALT_I2C_ACK_GENERAL_CALL_s +{ + uint32_t ack_gen_call : 1; /* ACK General Call Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_ACK_GENERAL_CALL. */ +typedef volatile struct ALT_I2C_ACK_GENERAL_CALL_s ALT_I2C_ACK_GENERAL_CALL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_ACK_GENERAL_CALL register from the beginning of the component. */ +#define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98 +/* The address of the ALT_I2C_ACK_GENERAL_CALL register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST)) + +/* + * Register : Enable Status Register - ic_enable_status + * + * This register is used to report the i2c hardware status when the IC_ENABLE + * register is set from 1 to 0; that is, when i2c is disabled. If IC_ENABLE has + * been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE + * has been set to 0, bits 2:1 are only valid as soon as bit 0 is read as '0'. + * + * Note: When ic_enable has been written with '0' a delay occurs for bit 0 to be + * read as '0' because disabling the i2c depends on I2C bus activities. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | R | 0x0 | Enable Status Bit + * [1] | R | 0x0 | Slave Disabled While Busy Bit + * [2] | R | 0x0 | Slave Received Data Lost Bit + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable Status Bit - ic_en + * + * This bit always reflects the value driven on the output port ic_en. Not used in + * current application. When read as 1, i2c is deemed to be in an enabled state. + * When read as 0, i2c is deemed completely inactive. NOTE: The CPU can safely read + * this bit anytime. When this bit is read as 0, the CPU can safely read + * slv_rx_data_lost (bit 2) and slv_disabled_while_busy (bit 1). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_MSB 0 +/* The width in bits of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_IC_EN register field value. */ +#define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_EN_STAT_IC_EN register field value. */ +#define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_IC_EN field value from a register. */ +#define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_EN_STAT_IC_EN register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Slave Disabled While Busy Bit - slv_disabled_while_busy + * + * This bit indicates if a potential or active Slave operation has been aborted due + * to the setting of the ic_enable register from 1 to 0. This bit is set when the + * CPU writes a 0 to the ic_enable register while: (a) I2C is receiving the address + * byte of the Slave-Transmitter operation from a remote master; OR, (b) address + * and data bytes of the Slave-Receiver operation from a remote master. When read + * as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, + * irrespective of whether the I2C address matches the slave address set in i2c + * (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 + * but has not taken effect. NOTE: If the remote I2C master terminates the transfer + * with a STOP condition before the i2c has a chance to NACK a transfer, and + * IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as + * 0, i2c is deemed to have been disabled when there is master activity, or when + * the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) + * is read as 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1 +/* The width in bits of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY field value from a register. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Slave Received Data Lost Bit - slv_rx_data_lost + * + * This bit indicates if a Slave-Receiver operation has been aborted with at least + * one data byte received from an I2C transfer due to the setting of IC ENABLE from + * 1 to 0. When read as 1, i2c is deemed to have been actively engaged in an + * aborted I2C transfer (with matching address) and the data phase of the I2C + * transfer has been entered, even though a data byte has been responded with a + * NACK. NOTE: If the remote I2C master terminates the transfer with a STOP + * condition before the i2c has a chance to NACK a transfer, and ic_enable has been + * set to 0, then this bit is also set to 1. When read as 0, i2c is deemed to have + * been disabled without being actively involved in the data phase of a Slave- + * Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is + * read as 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2 +/* The width in bits of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST field value from a register. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_EN_STAT. + */ +struct ALT_I2C_EN_STAT_s +{ + const uint32_t ic_en : 1; /* Enable Status Bit */ + const uint32_t slv_disabled_while_busy : 1; /* Slave Disabled While Busy Bit */ + const uint32_t slv_rx_data_lost : 1; /* Slave Received Data Lost Bit */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_EN_STAT. */ +typedef volatile struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_EN_STAT register from the beginning of the component. */ +#define ALT_I2C_EN_STAT_OFST 0x9c +/* The address of the ALT_I2C_EN_STAT register. */ +#define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST)) + +/* + * Register : SS and FS Spike Suppression Limit Register - ic_fs_spklen + * + * This register is used to store the duration, measured in ic_clk cycles, of the + * longest spike that is filtered out by the spike suppression logic when the + * component is operating in SS or FS modes. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [7:0] | RW | 0x2 | Spike Suppression Limit Register + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Spike Suppression Limit Register - spklen + * + * This register must be set before any I2C bus transaction can take place to + * ensure stable operation. This register sets the duration, measured in ic_clk + * cycles, of the longest spike in the SCL or SDA lines that are filtered out by + * the spike suppression logic. This register can be written only when the I2C + * interface is disabled, which corresponds to the IC_ENABLE register being set to + * 0. Writes at other times have no effect. The minimum valid value is 1; hardware + * prevents values less than this being written, and if attempted results in 2 + * being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_MSB 7 +/* The width in bits of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_WIDTH 8 +/* The mask used to set the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_RESET 0x2 +/* Extracts the ALT_I2C_FS_SPKLEN_SPKLEN field value from a register. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_FS_SPKLEN_SPKLEN register field value suitable for setting the register. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SPKLEN. + */ +struct ALT_I2C_FS_SPKLEN_s +{ + uint32_t spklen : 8; /* Spike Suppression Limit Register */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SPKLEN. */ +typedef volatile struct ALT_I2C_FS_SPKLEN_s ALT_I2C_FS_SPKLEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SPKLEN register from the beginning of the component. */ +#define ALT_I2C_FS_SPKLEN_OFST 0xa0 +/* The address of the ALT_I2C_FS_SPKLEN register. */ +#define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST)) + +/* + * Register : Component Parameter Register 1 - ic_comp_param_1 + * + * This is a constant read-only register that contains encoded information about + * the component's parameter settings. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [1:0] | R | 0x2 | APB Data Width Register + * [3:2] | R | 0x2 | Max Speed Mode + * [4] | R | 0x0 | CNT Registers Access + * [5] | R | 0x1 | Intr IO + * [6] | R | 0x1 | Has DMA + * [7] | R | 0x1 | Add Encoded Params + * [15:8] | R | 0x3f | Rx Buffer Depth + * [23:16] | R | 0x3f | Tx Buffer Depth + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB Data Width Register - apb_data_width + * + * Sets the APB Data Width. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH + * + * APB Data Width is 32 Bits + */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2 +/* Extracts the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Max Speed Mode - max_speed_mode + * + * The value of this field determines the maximum i2c bus interface speed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------- + * ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST | 0x2 | Fast Mode (400 kbit/s) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD + * + * Fast Mode (400 kbit/s) + */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2 +/* Extracts the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : CNT Registers Access - hc_count_values + * + * This makes the *CNT registers readable and writable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR | 0x0 | *CNT registers read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES + * + * * CNT registers read/write + */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0 +/* Extracts the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Intr IO - intr_io + * + * All interrupt sources are combined in to a single output. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED | 0x1 | Combined Interrupt Output + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_INTR_IO + * + * Combined Interrupt Output + */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_INTR_IO field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_COMP_PARAM_1_INTR_IO register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Has DMA - has_dma + * + * This configures the inclusion of DMA handshaking interface signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------ + * ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT | 0x1 | Has DMA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HAS_DMA + * + * Has DMA + */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_HAS_DMA field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_COMP_PARAM_1_HAS_DMA register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Add Encoded Params - add_encoded_params + * + * By adding in the encoded parameters, this gives firmware an easy and quick way + * of identifying the DesignWare component within an I/O memory map. Some critical + * design-time options determine how a driver should interact with the peripheral. + * There is a minimal area overhead by including these parameters. Allows a single + * driver to be developed for each component which will be self-configurable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------- + * ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Add Encoded Params + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS + * + * Add Encoded Params + */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Rx Buffer Depth - rx_buffer_depth + * + * Sets Rx FIFO Depth. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------------- + * ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Rx Fifo Depth 64 Entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH + * + * Rx Fifo Depth 64 Entries + */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff +/* The reset value of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f +/* Extracts the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Tx Buffer Depth - tx_buffer_depth + * + * Sets Tx FIFO Depth. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Tx Buffer Depth 64 Entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH + * + * Tx Buffer Depth 64 Entries + */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff +/* The reset value of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f +/* Extracts the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_PARAM_1. + */ +struct ALT_I2C_COMP_PARAM_1_s +{ + const uint32_t apb_data_width : 2; /* APB Data Width Register */ + const uint32_t max_speed_mode : 2; /* Max Speed Mode */ + const uint32_t hc_count_values : 1; /* CNT Registers Access */ + const uint32_t intr_io : 1; /* Intr IO */ + const uint32_t has_dma : 1; /* Has DMA */ + const uint32_t add_encoded_params : 1; /* Add Encoded Params */ + const uint32_t rx_buffer_depth : 8; /* Rx Buffer Depth */ + const uint32_t tx_buffer_depth : 8; /* Tx Buffer Depth */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_PARAM_1. */ +typedef volatile struct ALT_I2C_COMP_PARAM_1_s ALT_I2C_COMP_PARAM_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_PARAM_1 register from the beginning of the component. */ +#define ALT_I2C_COMP_PARAM_1_OFST 0xf4 +/* The address of the ALT_I2C_COMP_PARAM_1 register. */ +#define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST)) + +/* + * Register : Component Version Register - ic_comp_version + * + * Describes the version of the I2C + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------------- + * [31:0] | R | 0x3132302a | Component Parameter Value + * + */ +/* + * Field : Component Parameter Value - ic_comp_version + * + * Specifies I2C release number (encoded as 4 ASCII characters) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:-----------|:-------------- + * ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A | 0x3132302a | Version 1.20a + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_VER_IC_COMP_VER + * + * Version 1.20a + */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A 0x3132302a + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31 +/* The width in bits of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32 +/* The mask used to set the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff +/* The mask used to clear the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000 +/* The reset value of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132302a +/* Extracts the ALT_I2C_COMP_VER_IC_COMP_VER field value from a register. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_I2C_COMP_VER_IC_COMP_VER register field value suitable for setting the register. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_VER. + */ +struct ALT_I2C_COMP_VER_s +{ + const uint32_t ic_comp_version : 32; /* Component Parameter Value */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_VER. */ +typedef volatile struct ALT_I2C_COMP_VER_s ALT_I2C_COMP_VER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_VER register from the beginning of the component. */ +#define ALT_I2C_COMP_VER_OFST 0xf8 +/* The address of the ALT_I2C_COMP_VER register. */ +#define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST)) + +/* + * Register : Component Type Register - ic_comp_type + * + * Describes a unique ASCII value + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | R | 0x44570140 | Component Type Number + * + */ +/* + * Field : Component Type Number - ic_comp_type + * + * Designware Component Type number = 0x44_57_01_40. This assigned unique hex value + * is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit + * unsigned number. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31 +/* The width in bits of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32 +/* The mask used to set the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000 +/* The reset value of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140 +/* Extracts the ALT_I2C_COMP_TYPE_IC_COMP_TYPE field value from a register. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value suitable for setting the register. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_TYPE. + */ +struct ALT_I2C_COMP_TYPE_s +{ + const uint32_t ic_comp_type : 32; /* Component Type Number */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_TYPE. */ +typedef volatile struct ALT_I2C_COMP_TYPE_s ALT_I2C_COMP_TYPE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_TYPE register from the beginning of the component. */ +#define ALT_I2C_COMP_TYPE_OFST 0xfc +/* The address of the ALT_I2C_COMP_TYPE register. */ +#define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_I2C. + */ +struct ALT_I2C_s +{ + volatile ALT_I2C_CON_t ic_con; /* ALT_I2C_CON */ + volatile ALT_I2C_TAR_t ic_tar; /* ALT_I2C_TAR */ + volatile ALT_I2C_SAR_t ic_sar; /* ALT_I2C_SAR */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_I2C_DATA_CMD_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ + volatile ALT_I2C_SS_SCL_HCNT_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ + volatile ALT_I2C_SS_SCL_LCNT_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ + volatile ALT_I2C_FS_SCL_HCNT_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ + volatile ALT_I2C_FS_SCL_LCNT_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ + volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ + volatile ALT_I2C_INTR_STAT_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ + volatile ALT_I2C_INTR_MSK_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ + volatile ALT_I2C_RAW_INTR_STAT_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ + volatile ALT_I2C_RX_TL_t ic_rx_tl; /* ALT_I2C_RX_TL */ + volatile ALT_I2C_TX_TL_t ic_tx_tl; /* ALT_I2C_TX_TL */ + volatile ALT_I2C_CLR_INTR_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ + volatile ALT_I2C_CLR_RX_UNDER_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ + volatile ALT_I2C_CLR_RX_OVER_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ + volatile ALT_I2C_CLR_TX_OVER_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ + volatile ALT_I2C_CLR_RD_REQ_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ + volatile ALT_I2C_CLR_TX_ABRT_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ + volatile ALT_I2C_CLR_RX_DONE_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ + volatile ALT_I2C_CLR_ACTIVITY_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ + volatile ALT_I2C_CLR_STOP_DET_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ + volatile ALT_I2C_CLR_START_DET_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ + volatile ALT_I2C_CLR_GEN_CALL_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ + volatile ALT_I2C_EN_t ic_enable; /* ALT_I2C_EN */ + volatile ALT_I2C_STAT_t ic_status; /* ALT_I2C_STAT */ + volatile ALT_I2C_TXFLR_t ic_txflr; /* ALT_I2C_TXFLR */ + volatile ALT_I2C_RXFLR_t ic_rxflr; /* ALT_I2C_RXFLR */ + volatile ALT_I2C_SDA_HOLD_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ + volatile ALT_I2C_TX_ABRT_SRC_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ + volatile ALT_I2C_SLV_DATA_NACK_ONLY_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ + volatile ALT_I2C_DMA_CR_t ic_dma_cr; /* ALT_I2C_DMA_CR */ + volatile ALT_I2C_DMA_TDLR_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ + volatile ALT_I2C_DMA_RDLR_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ + volatile ALT_I2C_SDA_SETUP_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ + volatile ALT_I2C_ACK_GENERAL_CALL_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ + volatile ALT_I2C_EN_STAT_t ic_enable_status; /* ALT_I2C_EN_STAT */ + volatile ALT_I2C_FS_SPKLEN_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ + volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ + volatile ALT_I2C_COMP_PARAM_1_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ + volatile ALT_I2C_COMP_VER_t ic_comp_version; /* ALT_I2C_COMP_VER */ + volatile ALT_I2C_COMP_TYPE_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ +}; + +/* The typedef declaration for register group ALT_I2C. */ +typedef volatile struct ALT_I2C_s ALT_I2C_t; +/* The struct declaration for the raw register contents of register group ALT_I2C. */ +struct ALT_I2C_raw_s +{ + volatile uint32_t ic_con; /* ALT_I2C_CON */ + volatile uint32_t ic_tar; /* ALT_I2C_TAR */ + volatile uint32_t ic_sar; /* ALT_I2C_SAR */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ + volatile uint32_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ + volatile uint32_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ + volatile uint32_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ + volatile uint32_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ + volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ + volatile uint32_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ + volatile uint32_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ + volatile uint32_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ + volatile uint32_t ic_rx_tl; /* ALT_I2C_RX_TL */ + volatile uint32_t ic_tx_tl; /* ALT_I2C_TX_TL */ + volatile uint32_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ + volatile uint32_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ + volatile uint32_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ + volatile uint32_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ + volatile uint32_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ + volatile uint32_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ + volatile uint32_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ + volatile uint32_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ + volatile uint32_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ + volatile uint32_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ + volatile uint32_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ + volatile uint32_t ic_enable; /* ALT_I2C_EN */ + volatile uint32_t ic_status; /* ALT_I2C_STAT */ + volatile uint32_t ic_txflr; /* ALT_I2C_TXFLR */ + volatile uint32_t ic_rxflr; /* ALT_I2C_RXFLR */ + volatile uint32_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ + volatile uint32_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ + volatile uint32_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ + volatile uint32_t ic_dma_cr; /* ALT_I2C_DMA_CR */ + volatile uint32_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ + volatile uint32_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ + volatile uint32_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ + volatile uint32_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ + volatile uint32_t ic_enable_status; /* ALT_I2C_EN_STAT */ + volatile uint32_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ + volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ + volatile uint32_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ + volatile uint32_t ic_comp_version; /* ALT_I2C_COMP_VER */ + volatile uint32_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_I2C. */ +typedef volatile struct ALT_I2C_raw_s ALT_I2C_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_I2C_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_i2c.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_i2c.c new file mode 100644 index 0000000..1519f4f --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_i2c.c @@ -0,0 +1,2004 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_i2c.h" +#include "alt_reset_manager.h" +#include + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) + +///// + +#define MIN(a, b) ((a) > (b) ? (b) : (a)) + +///// + +// Timeout for reset manager +#define ALT_I2C_RESET_TMO_INIT 8192 +// Timeout for disable device +#define ALT_I2C_MAX_T_POLL_COUNT 8192 +// Timeout for waiting interrupt +#define ALT_I2C_TMO_WAITER 2500000 + +// Min frequency during standard speed +#define ALT_I2C_SS_MIN_SPEED 8000 +// Max frequency during standard speed +#define ALT_I2C_SS_MAX_SPEED 100000 +// Min frequency during fast speed +#define ALT_I2C_FS_MIN_SPEED 100000 +// Max frequency during fast speed +#define ALT_I2C_FS_MAX_SPEED 400000 +// Default spike suppression limit during standard speed +#define ALT_I2C_SS_DEFAULT_SPKLEN 11 +// Default spike suppression limit during fast speed +#define ALT_I2C_FS_DEFAULT_SPKLEN 4 + +// Diff between SCL LCNT and SCL HCNT +#define ALT_I2C_DIFF_LCNT_HCNT 70 + +// Reserved address from 0x00 to 0x07 +#define ALT_I2C_SLV_RESERVE_ADDR_S_1 0x00 +#define ALT_I2C_SLV_RESERVE_ADDR_F_1 0x07 +// Reserved address from 0x78 to 0x7F +#define ALT_I2C_SLV_RESERVE_ADDR_S_2 0x78 +#define ALT_I2C_SLV_RESERVE_ADDR_F_2 0x7F + +static ALT_STATUS_CODE alt_i2c_is_enabled_helper(ALT_I2C_DEV_t * i2c_dev); + +// +// Check whether i2c space is correct. +// +static ALT_STATUS_CODE alt_i2c_checking(ALT_I2C_DEV_t * i2c_dev) +{ + if ( (i2c_dev->location != (void *)ALT_I2C_I2C0) + && (i2c_dev->location != (void *)ALT_I2C_I2C1) + && (i2c_dev->location != (void *)ALT_I2C_I2C2) + && (i2c_dev->location != (void *)ALT_I2C_I2C3)) + { + // Incorrect device + return ALT_E_FALSE; + } + + // Reset i2c module + return ALT_E_TRUE; +} + +static ALT_STATUS_CODE alt_i2c_rstmgr_set(ALT_I2C_DEV_t * i2c_dev) +{ + uint32_t rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + + // Assert the appropriate I2C module reset signal via the Reset Manager Peripheral Reset register. + switch ((ALT_I2C_CTLR_t)i2c_dev->location) + { + case ALT_I2C_I2C0: + rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + break; + case ALT_I2C_I2C1: + rst_mask = ALT_RSTMGR_PERMODRST_I2C1_SET_MSK; + break; + case ALT_I2C_I2C2: + rst_mask = ALT_RSTMGR_PERMODRST_I2C2_SET_MSK; + break; + case ALT_I2C_I2C3: + rst_mask = ALT_RSTMGR_PERMODRST_I2C3_SET_MSK; + break; + default: + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + return ALT_E_SUCCESS; +} + +// +// Reset i2c module by reset manager +// +static ALT_STATUS_CODE alt_i2c_rstmgr_strobe(ALT_I2C_DEV_t * i2c_dev) +{ + uint32_t rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + + // Assert the appropriate I2C module reset signal via the Reset Manager Peripheral Reset register. + switch ((ALT_I2C_CTLR_t)i2c_dev->location) + { + case ALT_I2C_I2C0: + rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + break; + case ALT_I2C_I2C1: + rst_mask = ALT_RSTMGR_PERMODRST_I2C1_SET_MSK; + break; + case ALT_I2C_I2C2: + rst_mask = ALT_RSTMGR_PERMODRST_I2C2_SET_MSK; + break; + case ALT_I2C_I2C3: + rst_mask = ALT_RSTMGR_PERMODRST_I2C3_SET_MSK; + break; + default: + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + volatile uint32_t timeout = ALT_I2C_RESET_TMO_INIT; + + // Wait while i2c modure is reseting + while (--timeout) + ; + + // Deassert the appropriate I2C module reset signal via the Reset Manager Peripheral Reset register. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + return ALT_E_SUCCESS; +} + +// +// Initialize the specified I2C controller instance for use and return a device +// handle referencing it. +// +ALT_STATUS_CODE alt_i2c_init(const ALT_I2C_CTLR_t i2c, + ALT_I2C_DEV_t * i2c_dev) +{ + // Save i2c start address to the instance + i2c_dev->location = (void *)i2c; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_clk_is_enabled(ALT_CLK_L4_SP) != ALT_E_TRUE) + { + return ALT_E_BAD_CLK; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_clk_freq_get(ALT_CLK_L4_SP, &i2c_dev->clock_freq); + } + + // Reset i2c module + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_reset(i2c_dev); + } + + return status; +} + +// +// Reset i2c module +// +ALT_STATUS_CODE alt_i2c_reset(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + // Reset i2c module by reset manager + alt_i2c_rstmgr_strobe(i2c_dev); + + // Set optimal parameters for all i2c devices on the bus + ALT_I2C_MASTER_CONFIG_t cfg; + cfg.addr_mode = ALT_I2C_ADDR_MODE_7_BIT; + cfg.speed_mode = ALT_I2C_SPEED_STANDARD; + cfg.fs_spklen = ALT_I2C_SS_DEFAULT_SPKLEN; + cfg.restart_enable = ALT_E_TRUE; + cfg.ss_scl_lcnt = cfg.fs_scl_lcnt = 0x2FB; + cfg.ss_scl_hcnt = cfg.fs_scl_hcnt = 0x341; + + alt_i2c_master_config_set(i2c_dev, &cfg); + + // Active master mode + alt_i2c_op_mode_set(i2c_dev, ALT_I2C_MODE_MASTER); + + // Reset the last target address cache. + i2c_dev->last_target = 0xffffffff; + + // Clear interrupts mask and clear interrupt status. + // Interrupts are unmasked by default. + alt_i2c_int_disable(i2c_dev, ALT_I2C_STATUS_INT_ALL); + alt_i2c_int_clear(i2c_dev, ALT_I2C_STATUS_INT_ALL); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Uninitialize the I2C controller referenced by the i2c_dev handle. +// +ALT_STATUS_CODE alt_i2c_uninit(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Disable i2c controller + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_disable(i2c_dev); + } + + // Reset i2c module by reset manager + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_rstmgr_set(i2c_dev); + } + + return status; +} + +// +// Enables the I2C controller. +// +ALT_STATUS_CODE alt_i2c_enable(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // Enable DMA by default. + alt_write_word(ALT_I2C_DMA_CR_ADDR(i2c_dev->location), + ALT_I2C_DMA_CR_TDMAE_SET_MSK | ALT_I2C_DMA_CR_RDMAE_SET_MSK); + + alt_setbits_word(ALT_I2C_EN_ADDR(i2c_dev->location), ALT_I2C_EN_EN_SET_MSK); + + return ALT_E_SUCCESS; +} + +// +// Disables the I2C controller +// +ALT_STATUS_CODE alt_i2c_disable(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // If i2c controller is enabled, return with sucess + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_SUCCESS; + } + + // Else clear enable bit of i2c_enable register + alt_clrbits_word(ALT_I2C_EN_ADDR(i2c_dev->location), ALT_I2C_EN_EN_SET_MSK); + + uint32_t timeout = ALT_I2C_MAX_T_POLL_COUNT; + + // Wait to complete all transfer operations or timeout + while (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE) + { + // If controller still are active, return timeout error + if (--timeout == 0) + { + return ALT_E_TMO; + } + } + + // Clear interrupt status + alt_i2c_int_clear(i2c_dev, ALT_I2C_STATUS_INT_ALL); + + return ALT_E_SUCCESS; +} + +// +// Check whether i2c controller is enable +// +static ALT_STATUS_CODE alt_i2c_is_enabled_helper(ALT_I2C_DEV_t * i2c_dev) +{ + if (ALT_I2C_EN_STAT_IC_EN_GET(alt_read_word(ALT_I2C_EN_STAT_ADDR(i2c_dev->location)))) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +ALT_STATUS_CODE alt_i2c_is_enabled(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + return alt_i2c_is_enabled_helper(i2c_dev); +} + +// +// Get config parameters from appropriate registers for master mode. +// +ALT_STATUS_CODE alt_i2c_master_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t cfg_register = alt_read_word(ALT_I2C_CON_ADDR(i2c_dev->location)); + uint32_t tar_register = alt_read_word(ALT_I2C_TAR_ADDR(i2c_dev->location)); + uint32_t spkl_register = alt_read_word(ALT_I2C_FS_SPKLEN_ADDR(i2c_dev->location)); + + cfg->speed_mode = (ALT_I2C_SPEED_t)ALT_I2C_CON_SPEED_GET(cfg_register); + cfg->fs_spklen = ALT_I2C_FS_SPKLEN_SPKLEN_GET(spkl_register); + cfg->restart_enable = ALT_I2C_CON_IC_RESTART_EN_GET(cfg_register); + cfg->addr_mode = (ALT_I2C_ADDR_MODE_t)ALT_I2C_TAR_IC_10BITADDR_MST_GET(tar_register); + + cfg->ss_scl_lcnt = alt_read_word(ALT_I2C_SS_SCL_LCNT_ADDR(i2c_dev->location)); + cfg->ss_scl_hcnt = alt_read_word(ALT_I2C_SS_SCL_HCNT_ADDR(i2c_dev->location)); + cfg->fs_scl_lcnt = alt_read_word(ALT_I2C_FS_SCL_LCNT_ADDR(i2c_dev->location)); + cfg->fs_scl_hcnt = alt_read_word(ALT_I2C_FS_SCL_HCNT_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +// +// Set config parameters to appropriate registers for master mode. +// +ALT_STATUS_CODE alt_i2c_master_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->speed_mode != ALT_I2C_SPEED_STANDARD) + && (cfg->speed_mode != ALT_I2C_SPEED_FAST)) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->addr_mode != ALT_I2C_ADDR_MODE_7_BIT) + && (cfg->addr_mode != ALT_I2C_ADDR_MODE_10_BIT)) + { + return ALT_E_ARG_RANGE; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + // Set config parameters to appropriate registers + + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_SPEED_SET_MSK | ALT_I2C_CON_IC_RESTART_EN_SET_MSK, + ALT_I2C_CON_SPEED_SET(cfg->speed_mode) | ALT_I2C_CON_IC_RESTART_EN_SET(cfg->restart_enable)); + + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK, + ALT_I2C_TAR_IC_10BITADDR_MST_SET(cfg->addr_mode)); + + alt_replbits_word(ALT_I2C_FS_SPKLEN_ADDR(i2c_dev->location), + ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK, + ALT_I2C_FS_SPKLEN_SPKLEN_SET(cfg->fs_spklen)); + + alt_replbits_word(ALT_I2C_SS_SCL_LCNT_ADDR(i2c_dev->location), + ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK, + ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(cfg->ss_scl_lcnt)); + alt_replbits_word(ALT_I2C_SS_SCL_HCNT_ADDR(i2c_dev->location), + ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK, + ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(cfg->ss_scl_hcnt)); + alt_replbits_word(ALT_I2C_FS_SCL_LCNT_ADDR(i2c_dev->location), + ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK, + ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(cfg->fs_scl_lcnt)); + alt_replbits_word(ALT_I2C_FS_SCL_HCNT_ADDR(i2c_dev->location), + ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK, + ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(cfg->fs_scl_hcnt)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Return bus speed by configuration of i2c controller for master mode. +// +ALT_STATUS_CODE alt_i2c_master_config_speed_get(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t * cfg, + uint32_t * speed_in_hz) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t scl_lcnt = (cfg->speed_mode == ALT_I2C_SPEED_STANDARD) ? cfg->ss_scl_lcnt : cfg->fs_scl_lcnt; + + if (scl_lcnt == 0) + { + return ALT_E_BAD_ARG; + } + + *speed_in_hz = i2c_dev->clock_freq / (scl_lcnt << 1); + + return ALT_E_SUCCESS; +} + +// +// Fill struct with configuration of i2c controller for master mode by bus speed +// +ALT_STATUS_CODE alt_i2c_master_config_speed_set(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t * cfg, + uint32_t speed_in_hz) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // If speed is not standard or fast return range error + if ((speed_in_hz > ALT_I2C_FS_MAX_SPEED) || (speed_in_hz < ALT_I2C_SS_MIN_SPEED)) + { + return ALT_E_ARG_RANGE; + } + + if (speed_in_hz > ALT_I2C_FS_MIN_SPEED) + { + cfg->speed_mode = ALT_I2C_SPEED_FAST; + cfg->fs_spklen = ALT_I2C_FS_DEFAULT_SPKLEN; + } + else + { + cfg->speed_mode = ALT_I2C_SPEED_STANDARD; + cfg->fs_spklen = ALT_I2C_SS_DEFAULT_SPKLEN; + } + + // = / 2 * + uint32_t scl_lcnt = i2c_dev->clock_freq / (speed_in_hz << 1); + + cfg->ss_scl_lcnt = cfg->fs_scl_lcnt = scl_lcnt; + // hcount = + 70 + cfg->ss_scl_hcnt = cfg->fs_scl_hcnt = scl_lcnt - ALT_I2C_DIFF_LCNT_HCNT; + + // lcount = / 2 * + + return ALT_E_SUCCESS; +} + +// +// Get config parameters from appropriate registers for slave mode. +// +ALT_STATUS_CODE alt_i2c_slave_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_SLAVE_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t cfg_register = alt_read_word(ALT_I2C_CON_ADDR(i2c_dev->location)); + uint32_t sar_register = alt_read_word(ALT_I2C_SAR_ADDR(i2c_dev->location)); + uint32_t nack_register = alt_read_word(ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(i2c_dev->location)); + + cfg->addr_mode = (ALT_I2C_ADDR_MODE_t)ALT_I2C_CON_IC_10BITADDR_SLV_GET(cfg_register); + cfg->addr = ALT_I2C_SAR_IC_SAR_GET(sar_register); + cfg->nack_enable = ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(nack_register); + + return ALT_E_SUCCESS; +} + +// +// Set config parameters to appropriate registers for slave mode. +// +ALT_STATUS_CODE alt_i2c_slave_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_SLAVE_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->addr_mode != ALT_I2C_ADDR_MODE_7_BIT) + && (cfg->addr_mode != ALT_I2C_ADDR_MODE_10_BIT)) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->addr > ALT_I2C_SAR_IC_SAR_SET_MSK) + || (cfg->addr < ALT_I2C_SLV_RESERVE_ADDR_F_1) + || ((cfg->addr > ALT_I2C_SLV_RESERVE_ADDR_S_2) && (cfg->addr < ALT_I2C_SLV_RESERVE_ADDR_F_2)) + ) + { + return ALT_E_ARG_RANGE; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK, + ALT_I2C_CON_IC_10BITADDR_SLV_SET(cfg->addr_mode)); + + alt_replbits_word(ALT_I2C_SAR_ADDR(i2c_dev->location), + ALT_I2C_SAR_IC_SAR_SET_MSK, + ALT_I2C_SAR_IC_SAR_SET(cfg->addr)); + alt_replbits_word(ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(i2c_dev->location), + ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK, + ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(cfg->nack_enable)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Get hold time (use during slave mode) +// +ALT_STATUS_CODE alt_i2c_sda_hold_time_get(ALT_I2C_DEV_t *i2c_dev, + uint16_t *hold_time) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t sda_register = alt_read_word(ALT_I2C_SDA_HOLD_ADDR(i2c_dev->location)); + *hold_time = ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(sda_register); + + return ALT_E_SUCCESS; +} + +// +// Set hold time (use during slave mode) +// +ALT_STATUS_CODE alt_i2c_sda_hold_time_set(ALT_I2C_DEV_t *i2c_dev, + const uint16_t hold_time) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_SDA_HOLD_ADDR(i2c_dev->location), + ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK, + ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(hold_time)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Gets the current operational mode of the I2C controller. +// +ALT_STATUS_CODE alt_i2c_op_mode_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MODE_t* mode) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t cfg_register = alt_read_word(ALT_I2C_CON_ADDR(i2c_dev->location)); + uint32_t mst_mod_stat = ALT_I2C_CON_MST_MOD_GET(cfg_register); + uint32_t slv_mod_stat = ALT_I2C_CON_IC_SLV_DIS_GET(cfg_register); + + // Return error if master and slave modes enable or disable at the same time + if ( (mst_mod_stat == ALT_I2C_CON_MST_MOD_E_EN && slv_mod_stat == ALT_I2C_CON_IC_SLV_DIS_E_EN) + || (mst_mod_stat == ALT_I2C_CON_MST_MOD_E_DIS && slv_mod_stat == ALT_I2C_CON_IC_SLV_DIS_E_DIS)) + { + return ALT_E_ERROR; + } + + *mode = (ALT_I2C_MODE_t)mst_mod_stat; + + return ALT_E_SUCCESS; +} + +// +// Sets the operational mode of the I2C controller. +// +ALT_STATUS_CODE alt_i2c_op_mode_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MODE_t mode) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( (mode != ALT_I2C_MODE_MASTER) + && (mode != ALT_I2C_MODE_SLAVE)) + { + return ALT_E_ARG_RANGE; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + if (mode == ALT_I2C_MODE_MASTER) + { + // Enable master, disable slave + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_IC_SLV_DIS_SET_MSK | ALT_I2C_CON_MST_MOD_SET_MSK, + ALT_I2C_CON_IC_SLV_DIS_SET(ALT_I2C_CON_IC_SLV_DIS_E_DIS) | ALT_I2C_CON_MST_MOD_SET(ALT_I2C_CON_MST_MOD_E_EN)); + } + else if (mode == ALT_I2C_MODE_SLAVE) + { + // Enable slave, disable master + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_IC_SLV_DIS_SET_MSK | ALT_I2C_CON_MST_MOD_SET_MSK, + ALT_I2C_CON_IC_SLV_DIS_SET(ALT_I2C_CON_IC_SLV_DIS_E_EN) | ALT_I2C_CON_MST_MOD_SET(ALT_I2C_CON_MST_MOD_E_DIS)); + } + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Returns ALT_E_TRUE if the I2C controller is busy +// +ALT_STATUS_CODE alt_i2c_is_busy(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( ALT_I2C_STAT_ACTIVITY_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location)))) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// This function reads a single data byte from the receive FIFO. +// +ALT_STATUS_CODE alt_i2c_read(ALT_I2C_DEV_t *i2c_dev, uint8_t *value) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + *value = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + + return ALT_E_SUCCESS; +} + +// +// This function writes a single data byte to the transmit FIFO. +// +ALT_STATUS_CODE alt_i2c_write(ALT_I2C_DEV_t *i2c_dev, const uint8_t value) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(value)); + + return ALT_E_SUCCESS; +} + +// +// This function acts in the role of a slave-receiver by receiving a single data +// byte from the I2C bus in response to a write command from the master. +// +ALT_STATUS_CODE alt_i2c_slave_receive(ALT_I2C_DEV_t * i2c_dev, + uint8_t * data) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + // alt_i2c_read(). + *data = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + + return ALT_E_SUCCESS; +} + +// +// This function acts in the role of a slave-transmitter by transmitting a single +// data byte to the I2C bus in response to a read request from the master. +// +ALT_STATUS_CODE alt_i2c_slave_transmit(ALT_I2C_DEV_t *i2c_dev, + const uint8_t data) +{ + // Send bulk of data with one value + return alt_i2c_slave_bulk_transmit(i2c_dev, &data, 1); +} + +// +// This function acts in the role of a slave-transmitter by transmitting data in +// bulk to the I2C bus in response to a series of read requests from a master. +// +ALT_STATUS_CODE alt_i2c_slave_bulk_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + const char * buffer = data; + for (size_t i = 0; i < size; ++i) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(*buffer) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + + ++buffer; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_master_target_get(ALT_I2C_DEV_t * i2c_dev, uint32_t * target_addr) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *target_addr = i2c_dev->last_target; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_master_target_set(ALT_I2C_DEV_t * i2c_dev, uint32_t target_addr) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Wait until the TX FIFO flushes. This is needed because TAR can only be + // updated under specific conditions. + + if (target_addr != i2c_dev->last_target) + { + uint32_t timeout = 10000; + + while (alt_i2c_tx_fifo_is_empty(i2c_dev) == ALT_E_FALSE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + + // Update target address + if (status == ALT_E_SUCCESS) + { + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_IC_TAR_SET_MSK, + ALT_I2C_TAR_IC_TAR_SET(target_addr)); + + i2c_dev->last_target = target_addr; + } + } + + return status; +} + +// +// Write bulk of data or read requests to tx fifo +// +static ALT_STATUS_CODE alt_i2c_master_transmit_helper(ALT_I2C_DEV_t * i2c_dev, + const uint8_t * buffer, + size_t size, + bool issue_restart, + bool issue_stop) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the rested size is 1, the restart and stop may need to be sent in the + // same frame. + if (size == 1) + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_issue_write(i2c_dev, + *buffer, + issue_restart, + issue_stop); + + ++buffer; + --size; + } + } + else + { + // First byte + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_issue_write(i2c_dev, + *buffer, + issue_restart, + false); + + ++buffer; + --size; + } + + ///// + + // Middle byte(s) + + if (status == ALT_E_SUCCESS) + { + uint32_t timeout = size * 10000; + + while (size > 1) + { + uint32_t level = 0; + status = alt_i2c_tx_fifo_level_get(i2c_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t space = ALT_I2C_TX_FIFO_NUM_ENTRIES - level; + if (space == 0) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + + continue; + } + + // Subtract 1 because the last byte may need to issue_stop + space = MIN(space, size - 1); + + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(*buffer) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + + ++buffer; + } + + size -= space; + } + } + + ///// + + // Last byte + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_issue_write(i2c_dev, + *buffer, + false, + issue_stop); + + ++buffer; + --size; + } + } + + return status; +} + +// +// This function acts in the role of a master-transmitter by issuing a write +// command and transmitting data to the I2C bus. +// +ALT_STATUS_CODE alt_i2c_master_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_transmit_helper(i2c_dev, + data, + size, + issue_restart, + issue_stop); + } + + // Need reset for set i2c bus in idle state + if (status == ALT_E_TMO) + { + alt_i2c_reset(i2c_dev); + } + + return status; +} + +ALT_STATUS_CODE alt_i2c_master_receive_helper(ALT_I2C_DEV_t *i2c_dev, + uint8_t * buffer, + size_t size, + bool issue_restart, + bool issue_stop) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t issue_left = size; + uint32_t data_left = size; + + uint32_t timeout = size * 10000; + + // Wait for space in the TX FIFO to send the first read request. + // This is needed because the issue restart need to be set. + + if (issue_restart == true) + { + if (status == ALT_E_SUCCESS) + { + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + } + + // Now send the first request. + + if (status == ALT_E_SUCCESS) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + --issue_left; + } + } + + // For the rest of the data ... + + while (data_left > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + // Top up the TX FIFO with read issues + // Special consideration must be made for the last read issue, as it may be necessary to "issue_stop". + + if (issue_left > 0) + { + uint32_t level = 0; + status = alt_i2c_tx_fifo_level_get(i2c_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t space = ALT_I2C_TX_FIFO_NUM_ENTRIES - level; + + if (issue_left == 1) + { + if (space > 0) + { + space = 1; + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + } + } + else + { + // Send up to issue_left - 1, as the last issue has special considerations. + space = MIN(issue_left - 1, space); + + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + } + } + + issue_left -= space; + } + + // Read out the resulting received data as they come in. + + if (data_left > 0) + { + uint32_t level = 0; + status = alt_i2c_rx_fifo_level_get(i2c_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + if (level == 0) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + + level = MIN(data_left, level); + + for (uint32_t i = 0; i < level; ++i) + { + // alt_i2c_read(i2c_dev, &value); + *buffer = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + ++buffer; + } + + data_left -= level; + } + } + + + return status; +} + +// +// This function acts in the role of a master-receiver by receiving one or more +// data bytes transmitted from a slave in response to read requests issued from +// this master. +// +ALT_STATUS_CODE alt_i2c_master_receive(ALT_I2C_DEV_t *i2c_dev, + void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // This I2C controller requires that a read issue be performed for each byte requested. + // Read issue takes space in the TX FIFO, which may asynchronously handling a previous request. + + if (size == 1) + { + uint32_t timeout = 10000; + + // Wait for space in the TX FIFO to send the read request. + + if (status == ALT_E_SUCCESS) + { + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + } + + // Issue the read request in the TX FIFO. + + if (status == ALT_E_SUCCESS) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + } + + // Wait for data to become available in the RX FIFO. + + if (status == ALT_E_SUCCESS) + { + while (alt_i2c_rx_fifo_is_empty(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + } + + // Read the RX FIFO. + + if (status == ALT_E_SUCCESS) + { + uint8_t * buffer = data; + *buffer = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + } + } + else if (size <= 64) + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + data, + size, + issue_restart, + issue_stop); + } + } + else + { + uint8_t * buffer = data; + size_t size_left = size; + + // Send the first ALT_I2C_RX_FIFO_NUM_ENTRIES items + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + buffer, + ALT_I2C_RX_FIFO_NUM_ENTRIES, + issue_restart, + false); + } + + buffer += ALT_I2C_RX_FIFO_NUM_ENTRIES; + size_left -= ALT_I2C_RX_FIFO_NUM_ENTRIES; + + while (size_left > 0) + { + if (size_left > ALT_I2C_RX_FIFO_NUM_ENTRIES) + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + buffer, + ALT_I2C_RX_FIFO_NUM_ENTRIES, + false, + false); + } + + buffer += ALT_I2C_RX_FIFO_NUM_ENTRIES; + size_left -= ALT_I2C_RX_FIFO_NUM_ENTRIES; + } + else + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + buffer, + size_left, + false, + issue_stop); + } + + size_left = 0; + } + + if (status != ALT_E_SUCCESS) + { + break; + } + } + } + + // Need reset for set i2c bus in idle state + if (status == ALT_E_TMO) + { + alt_i2c_reset(i2c_dev); + } + + return status; +} + +// +// This function causes the I2C controller master to send data to the bus. +// +ALT_STATUS_CODE alt_i2c_issue_write(ALT_I2C_DEV_t *i2c_dev, + const uint8_t value, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + // Wait until there is a FIFO spot + uint32_t timeout = 10000; + + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + return ALT_E_TMO; + } + } + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(value) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + return ALT_E_SUCCESS; +} + +// +// This function causes the I2C controller master to issue a READ request on the bus. +// +ALT_STATUS_CODE alt_i2c_issue_read(ALT_I2C_DEV_t *i2c_dev, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + // Wait until there is a FIFO spot + uint32_t timeout = 10000; + + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + return ALT_E_TMO; + } + } + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + return ALT_E_SUCCESS; +} + +// +// This function acts in the role of a master-transmitter by issuing a general +// call command to all devices connected to the I2C bus. +// +ALT_STATUS_CODE alt_i2c_master_general_call(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_target_set(i2c_dev, 0); + } + + // General call is a transmit in master mode (target address are not used during it) + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_transmit(i2c_dev, data, size, issue_restart, issue_stop); + } + + return status; +} + +///// + +ALT_STATUS_CODE alt_i2c_general_call_ack_disable(ALT_I2C_DEV_t *i2c_dev) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_SPECIAL_SET_MSK | ALT_I2C_TAR_GC_OR_START_SET_MSK, + ALT_I2C_TAR_SPECIAL_SET(ALT_I2C_TAR_SPECIAL_E_STARTBYTE) | ALT_I2C_TAR_GC_OR_START_SET(ALT_I2C_TAR_GC_OR_START_E_STARTBYTE)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Enables the I2C controller to respond with an ACK when it receives a General +// Call address. +// +ALT_STATUS_CODE alt_i2c_general_call_ack_enable(ALT_I2C_DEV_t *i2c_dev) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_SPECIAL_SET_MSK | ALT_I2C_TAR_GC_OR_START_SET_MSK, + ALT_I2C_TAR_SPECIAL_SET(ALT_I2C_TAR_SPECIAL_E_GENCALL) | ALT_I2C_TAR_GC_OR_START_SET(ALT_I2C_TAR_GC_OR_START_E_GENCALL)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Returns ALT_E_TRUE if the I2C controller is enabled to respond to General Call +// addresses. +// +ALT_STATUS_CODE alt_i2c_general_call_ack_is_enabled(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t tar_register = alt_read_word(ALT_I2C_TAR_ADDR(i2c_dev->location)); + + if ( (ALT_I2C_TAR_SPECIAL_GET(tar_register) == ALT_I2C_TAR_SPECIAL_E_GENCALL) + && (ALT_I2C_TAR_GC_OR_START_GET(tar_register) == ALT_I2C_TAR_GC_OR_START_E_GENCALL) + ) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns the current I2C controller interrupt status conditions. +// +ALT_STATUS_CODE alt_i2c_int_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *status = alt_read_word(ALT_I2C_INTR_STAT_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +// +// Returns the I2C controller raw interrupt status conditions irrespective of +// the interrupt status condition enablement state. +// +ALT_STATUS_CODE alt_i2c_int_raw_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *status = alt_read_word(ALT_I2C_RAW_INTR_STAT_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +// +// Clears the specified I2C controller interrupt status conditions identified +// in the mask. +// +ALT_STATUS_CODE alt_i2c_int_clear(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (mask == ALT_I2C_STATUS_INT_ALL) + { + alt_read_word(ALT_I2C_CLR_INTR_ADDR(i2c_dev->location)); + return ALT_E_SUCCESS; + } + + // For different status clear different register + + if (mask & ALT_I2C_STATUS_RX_UNDER) + { + alt_read_word(ALT_I2C_CLR_RX_UNDER_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_RX_OVER) + { + alt_read_word(ALT_I2C_CLR_RX_OVER_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_TX_OVER) + { + alt_read_word(ALT_I2C_CLR_TX_OVER_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_RD_REQ) + { + alt_read_word(ALT_I2C_CLR_RD_REQ_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_TX_ABORT) + { + alt_read_word(ALT_I2C_CLR_TX_ABRT_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_RX_DONE) + { + alt_read_word(ALT_I2C_CLR_RX_DONE_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_ACTIVITY) + { + alt_read_word(ALT_I2C_CLR_ACTIVITY_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_STOP_DET) + { + alt_read_word(ALT_I2C_CLR_STOP_DET_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_START_DET) + { + alt_read_word(ALT_I2C_CLR_START_DET_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_INT_CALL) + { + alt_read_word(ALT_I2C_CLR_GEN_CALL_ADDR(i2c_dev->location)); + } + + return ALT_E_SUCCESS; +} + +// +// Disable the specified I2C controller interrupt status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_i2c_int_disable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + alt_clrbits_word(ALT_I2C_INTR_MSK_ADDR(i2c_dev->location), mask); + + return ALT_E_SUCCESS; +} + +// +// Enable the specified I2C controller interrupt status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_i2c_int_enable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_I2C_INTR_MSK_ADDR(i2c_dev->location), mask); + + return ALT_E_SUCCESS; +} + +///// + +// +// Gets the cause of I2C transmission abort. +// +ALT_STATUS_CODE alt_i2c_tx_abort_cause_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_TX_ABORT_CAUSE_t *cause) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *cause = (ALT_I2C_TX_ABORT_CAUSE_t)alt_read_word(ALT_I2C_TX_ABRT_SRC_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +///// + +// +// Returns ALT_E_TRUE when the receive FIFO is empty. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_RFNE_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_RFNE_E_EMPTY) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns ALT_E_TRUE when the receive FIFO is completely full. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_RFF_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_RFF_E_FULL) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns the number of valid entries in the receive FIFO. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *num_entries = ALT_I2C_RXFLR_RXFLR_GET(alt_read_word(ALT_I2C_RXFLR_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Gets the current receive FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_RX_TL_RX_TL_GET(alt_read_word(ALT_I2C_RX_TL_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Sets the current receive FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_RX_TL_ADDR(i2c_dev->location), + ALT_I2C_RX_TL_RX_TL_SET_MSK, + ALT_I2C_RX_TL_RX_TL_SET(threshold)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Returns ALT_E_TRUE when the transmit FIFO is empty. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_TFE_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_TFE_E_EMPTY) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns ALT_E_TRUE when the transmit FIFO is completely full. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_TFNF_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_TFNF_E_FULL) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns the number of valid entries in the transmit FIFO. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *num_entries = ALT_I2C_TXFLR_TXFLR_GET(alt_read_word(ALT_I2C_TXFLR_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Sets the current transmit FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_TX_TL_TX_TL_GET(alt_read_word(ALT_I2C_TX_TL_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Sets the current transmit FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_TX_TL_ADDR(i2c_dev->location), + ALT_I2C_TX_TL_TX_TL_SET_MSK, + ALT_I2C_TX_TL_TX_TL_SET(threshold)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +///// + +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_DMA_RDLR_DMARDL_GET(alt_read_word(ALT_I2C_DMA_RDLR_ADDR(i2c_dev->location))); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (threshold > ALT_I2C_DMA_RDLR_DMARDL_SET_MSK) + { + return ALT_E_ARG_RANGE; + } + + alt_write_word(ALT_I2C_DMA_RDLR_ADDR(i2c_dev->location), threshold); + return ALT_E_SUCCESS; + +} + +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_DMA_TDLR_DMATDL_GET(alt_read_word(ALT_I2C_DMA_TDLR_ADDR(i2c_dev->location))); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (threshold > ALT_I2C_DMA_TDLR_DMATDL_SET_MSK) + { + return ALT_E_ARG_RANGE; + } + + alt_write_word(ALT_I2C_DMA_TDLR_ADDR(i2c_dev->location), threshold); + return ALT_E_SUCCESS; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.c b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.c new file mode 100644 index 0000000..3c29b61 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include "i2cdrv-config.h" + +const i2cdrv_configuration i2cdrv_config[CYCLONE_V_NO_I2C] = { + { + .controller = ALT_I2C_I2C0, + .device_name = "/dev/i2c0", + .speed = CYCLONE_V_I2C0_SPEED, + } +}; diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.h b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.h new file mode 100644 index 0000000..6509747 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef XXX_H +#define XXX_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + ALT_I2C_CTLR_t controller; + char *device_name; + uint32_t speed; +} i2cdrv_configuration; + +extern const i2cdrv_configuration i2cdrv_config[]; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XXX_H */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv.c b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv.c new file mode 100644 index 0000000..3ea2355 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv.c @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include +#include "i2cdrv-config.h" + +typedef struct { + ALT_I2C_DEV_t i2c_dev; + rtems_id mutex; +} i2cdrv_entry; + +i2cdrv_entry i2cdrv_table[CYCLONE_V_NO_I2C]; + +static ALT_I2C_DEV_t *get_device(i2cdrv_entry *e) +{ + return &e->i2c_dev; +} + +static rtems_status_code init_i2c_module( + i2cdrv_entry *e, + const i2cdrv_configuration *cfg +) +{ + ALT_STATUS_CODE asc = ALT_E_SUCCESS; + ALT_I2C_CTLR_t controller = cfg->controller; + ALT_I2C_DEV_t *dev = get_device(e); + ALT_I2C_MASTER_CONFIG_t i2c_cfg = { + .addr_mode = ALT_I2C_ADDR_MODE_7_BIT, + .restart_enable = false, + }; + + asc = alt_i2c_init(controller, dev); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + asc = alt_i2c_op_mode_set(dev, ALT_I2C_MODE_MASTER); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + asc = alt_i2c_master_config_speed_set(dev, &i2c_cfg, cfg->speed); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + asc = alt_i2c_master_config_set(dev, &i2c_cfg); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + asc = alt_i2c_enable(dev); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver i2cdrv_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + for ( size_t i = 0; i < CYCLONE_V_NO_I2C; ++i ) { + i2cdrv_entry *e = &i2cdrv_table[i]; + const i2cdrv_configuration *cfg = &i2cdrv_config[i]; + + sc = rtems_io_register_name(cfg->device_name, major, i); + assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_semaphore_create( + rtems_build_name ('I', '2', 'C', '0' + i), + 0, + RTEMS_BINARY_SEMAPHORE | RTEMS_PRIORITY | RTEMS_INHERIT_PRIORITY, + 0, + &e->mutex + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = init_i2c_module(e, cfg); + if ( sc != RTEMS_SUCCESSFUL ) { + /* I2C is not usable at this point. Releasing the mutex would allow the + * usage which could lead to undefined behaviour. */ + return sc; + } + + sc = rtems_semaphore_release(e->mutex); + assert(sc == RTEMS_SUCCESSFUL); + } + + return sc; +} + +rtems_device_driver i2cdrv_open( + rtems_device_major_number major, + rtems_device_major_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + i2cdrv_entry *e = &i2cdrv_table[minor]; + + sc = rtems_semaphore_obtain(e->mutex, RTEMS_WAIT, RTEMS_NO_TIMEOUT); + return sc; +} + +rtems_device_driver i2cdrv_close( + rtems_device_major_number major, + rtems_device_major_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + i2cdrv_entry *e = &i2cdrv_table[minor]; + + sc = rtems_semaphore_release(e->mutex); + return sc; +} + +rtems_device_driver i2cdrv_read( + rtems_device_major_number major, + rtems_device_major_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + i2cdrv_entry *e = &i2cdrv_table[minor]; + rtems_libio_rw_args_t *rw = arg; + ALT_I2C_DEV_t *dev = get_device(e); + ALT_STATUS_CODE asc = ALT_E_SUCCESS; + + asc = alt_i2c_master_receive(dev, rw->buffer, rw->count, true, true); + if ( asc == ALT_E_SUCCESS ) { + rw->bytes_moved = rw->count; + } else { + sc = RTEMS_IO_ERROR; + } + + return sc; +} + +rtems_device_driver i2cdrv_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + i2cdrv_entry *e = &i2cdrv_table[minor]; + rtems_libio_rw_args_t *rw = arg; + ALT_I2C_DEV_t *dev = get_device(e); + ALT_STATUS_CODE asc = ALT_E_SUCCESS; + + asc = alt_i2c_master_transmit(dev, rw->buffer, rw->count, true, true); + if ( asc == ALT_E_SUCCESS ) { + rw->bytes_moved = rw->count; + } else { + sc = RTEMS_IO_ERROR; + } + + return sc; +} + +static rtems_status_code ioctl_set_slave_address( + i2cdrv_entry *e, + rtems_libio_ioctl_args_t *args +) +{ + ALT_I2C_DEV_t *dev = get_device(e); + ALT_STATUS_CODE asc = ALT_E_SUCCESS; + uint32_t address = (uint32_t) args->buffer; + + asc = alt_i2c_master_target_set(dev, address); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver i2cdrv_ioctl( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + i2cdrv_entry *e = &i2cdrv_table[minor]; + rtems_libio_ioctl_args_t *args = arg; + + switch (args->command) { + case I2C_IOC_SET_SLAVE_ADDRESS: + sc = ioctl_set_slave_address(e, args); + break; + default: + sc = RTEMS_INVALID_NUMBER; + break; + } + + return sc; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/include/i2cdrv.h b/c/src/lib/libbsp/arm/altera-cyclone-v/include/i2cdrv.h new file mode 100644 index 0000000..9a4411d --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/include/i2cdrv.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef I2CDRV_H +#define I2CDRV_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +rtems_device_driver i2cdrv_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_ioctl( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define I2C_DRIVER_TABLE_ENTRY \ + { \ + i2cdrv_initialize, \ + i2cdrv_open, \ + i2cdrv_close, \ + i2cdrv_read, \ + i2cdrv_write, \ + i2cdrv_ioctl \ + } + +#define I2C_IOC_SET_SLAVE_ADDRESS 1 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* I2CDRV_H */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 8873d31..c13ef6a 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @@ -163,6 +163,10 @@ $(PROJECT_INCLUDE)/bsp/alt_hwlibs_ver.h: hwlib/include/alt_hwlibs_ver.h $(PROJEC $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_hwlibs_ver.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_hwlibs_ver.h +$(PROJECT_INCLUDE)/bsp/alt_i2c.h: hwlib/include/alt_i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_i2c.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_i2c.h + $(PROJECT_INCLUDE)/bsp/alt_interrupt_common.h: hwlib/include/alt_interrupt_common.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_interrupt_common.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_interrupt_common.h @@ -243,3 +247,7 @@ $(PROJECT_LIB)/linkcmds.altcycv_devkit_smp: startup/linkcmds.altcycv_devkit_smp $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.altcycv_devkit_smp TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.altcycv_devkit_smp +$(PROJECT_INCLUDE)/bsp/i2cdrv.h: include/i2cdrv.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/i2cdrv.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/i2cdrv.h + From joel.sherrill at oarcorp.com Mon Aug 25 15:34:49 2014 From: joel.sherrill at oarcorp.com (Joel Sherrill) Date: Mon, 25 Aug 2014 15:34:49 -0000 Subject: [rtems commit] score: Add missing define to cache manager In-Reply-To: <20140825065014.F3D3C70080E@git.rtems.org> References: <20140825065014.F3D3C70080E@git.rtems.org> Message-ID: <53FB5797.9080208@oarcorp.com> Do we want these methods provided with empty implementations on targets without CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS? We have always aimed for a consistent API. This propagates the use of a conditional into drivers and other code. --joel On 8/25/2014 1:50 AM, Sebastian Huber wrote: > Module: rtems > Branch: master > Commit: e7a42a0cfbafc2311888780b086010aef6556311 > Changeset: http://git.rtems.org/rtems/commit/?id=e7a42a0cfbafc2311888780b086010aef6556311 > > Author: Daniel Cederman > Date: Mon Aug 25 08:48:17 2014 +0200 > > score: Add missing define to cache manager > > --- > > c/src/lib/libcpu/shared/src/cache_manager.c | 2 ++ > 1 files changed, 2 insertions(+), 0 deletions(-) > > diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c > index 7dd408f..7ff1166 100644 > --- a/c/src/lib/libcpu/shared/src/cache_manager.c > +++ b/c/src/lib/libcpu/shared/src/cache_manager.c > @@ -435,6 +435,7 @@ rtems_cache_disable_data( void ) > * and then perform the invalidations. > */ > > +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) > #if !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) > static void > _invalidate_multiple_instruction_lines_no_range_functions( > @@ -462,6 +463,7 @@ _invalidate_multiple_instruction_lines_no_range_functions( > } > } > #endif > +#endif > > void > rtems_cache_invalidate_multiple_instruction_lines( > > _______________________________________________ > vc mailing list > vc at rtems.org > http://lists.rtems.org/mailman/listinfo/vc -- Joel Sherrill, Ph.D. Director of Research & Development joel.sherrill at OARcorp.com On-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available (256) 722-9985 From sebh at rtems.org Tue Aug 26 15:12:22 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 26 Aug 2014 15:12:22 -0000 Subject: [rtems commit] bsp/altera-cyclone-v: Add DMA support hwlib files Message-ID: <20140826150327.B0CF6700683@git.rtems.org> Module: rtems Branch: master Commit: 76386c1047ea15a05965adcab371bba2147831ba Changeset: http://git.rtems.org/rtems/commit/?id=76386c1047ea15a05965adcab371bba2147831ba Author: Sebastian Huber Date: Tue Aug 26 16:00:44 2014 +0200 bsp/altera-cyclone-v: Add DMA support hwlib files --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 21 +- .../hwlib/include/alt_16550_uart.h | 1555 +++++ .../arm/altera-cyclone-v/hwlib/include/alt_cache.h | 964 ++++ .../arm/altera-cyclone-v/hwlib/include/alt_dma.h | 1007 ++++ .../hwlib/include/alt_dma_common.h | 162 + .../hwlib/include/alt_dma_program.h | 951 ++++ .../arm/altera-cyclone-v/hwlib/include/alt_qspi.h | 1535 +++++ .../hwlib/include/alt_qspi_private.h | 167 + .../hwlib/include/socal/alt_dmanonsecure.h | 144 + .../hwlib/include/socal/alt_dmasecure.h | 144 + .../hwlib/include/socal/alt_qspi.h | 5951 ++++++++++++++++++++ .../hwlib/include/socal/alt_qspidata.h | 52 + .../hwlib/src/hwmgr/alt_16550_uart.c | 1179 ++++ .../arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma.c | 3749 ++++++++++++ .../hwlib/src/hwmgr/alt_dma_program.c | 1064 ++++ .../altera-cyclone-v/hwlib/src/hwmgr/alt_qspi.c | 2619 +++++++++ .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 40 + 17 files changed, 21297 insertions(+), 7 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index a581dee..aad1db1 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -51,23 +51,25 @@ include_bsp_HEADERS += include/irq.h include_bsp_HEADERS += include/nocache-heap.h # Altera hwlib +include_bsp_HEADERS += hwlib/include/alt_16550_uart.h include_bsp_HEADERS += hwlib/include/alt_address_space.h +include_bsp_HEADERS += hwlib/include/alt_cache.h include_bsp_HEADERS += hwlib/include/alt_clock_group.h include_bsp_HEADERS += hwlib/include/alt_clock_manager.h +include_bsp_HEADERS += hwlib/include/alt_dma_common.h +include_bsp_HEADERS += hwlib/include/alt_dma.h +include_bsp_HEADERS += hwlib/include/alt_dma_program.h include_bsp_HEADERS += hwlib/include/alt_generalpurpose_io.h include_bsp_HEADERS += hwlib/include/alt_hwlibs_ver.h include_bsp_HEADERS += hwlib/include/alt_i2c.h include_bsp_HEADERS += hwlib/include/alt_interrupt_common.h include_bsp_HEADERS += hwlib/include/alt_mpu_registers.h +include_bsp_HEADERS += hwlib/include/alt_qspi_private.h include_bsp_HEADERS += hwlib/include/alt_reset_manager.h include_bsp_HEADERS += hwlib/include/hwlib.h #The following Altera hwlib header files have been left out because so far #they are not required: -#include_bsp_HEADERS += hwlib/include/alt_16550_uart.h #include_bsp_HEADERS += hwlib/include/alt_bridge_manager.h -#include_bsp_HEADERS += hwlib/include/alt_dma_common.h -#include_bsp_HEADERS += hwlib/include/alt_dma_program.h -#include_bsp_HEADERS += hwlib/include/alt_dma.h #include_bsp_HEADERS += hwlib/include/alt_fpga_manager.h #include_bsp_HEADERS += hwlib/include/alt_globaltmr.h #include_bsp_HEADERS += hwlib/include/alt_system_manager.h @@ -79,9 +81,13 @@ include_bsp_HEADERS += hwlib/include/hwlib.h # Some of the headers from hwlib need the files from socal. Install them. include_bsp_socal_HEADERS += hwlib/include/socal/alt_acpidmap.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_clkmgr.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_dmanonsecure.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_dmasecure.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_gpio.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_i2c.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_l3.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_qspidata.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_qspi.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_rstmgr.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_sdr.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_sysmgr.h @@ -124,17 +130,18 @@ libbsp_a_CPPFLAGS += -std=gnu99 CFLAGS += -Wno-missing-prototypes # hwlib from Altera +libbsp_a_SOURCES += hwlib/src/hwmgr/alt_16550_uart.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_address_space.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_clock_manager.c +libbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma.c +libbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma_program.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_generalpurpose_io.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_i2c.c +libbsp_a_SOURCES += hwlib/src/hwmgr/alt_qspi.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_reset_manager.c #The following Altera hwlib source files have been left out because so far #they are not required: -#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_16550_uart.c #libbsp_a_SOURCES += hwlib/src/hwmgr/alt_bridge_manager.c -#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma_program.c -#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma.c #libbsp_a_SOURCES += hwlib/src/hwmgr/alt_fpga_manager.c #libbsp_a_SOURCES += hwlib/src/hwmgr/alt_globaltmr.c #libbsp_a_SOURCES += hwlib/src/hwmgr/alt_system_manager.c diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h new file mode 100644 index 0000000..bca6f63 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h @@ -0,0 +1,1555 @@ +/* + * Altera - SoC UART Manager + */ + +/***************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ALT_16550_UART_H__ +#define __ALT_16550_UART_H__ + +#include "hwlib.h" +#include "alt_clock_manager.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup UART UART Driver API + * + * This module defines the Universal Asynchronous Receiver/Transmitter (UART) + * API for accessing and using the UART resources. The API allows for general + * control of a 16550 compatible UART controller. + * + * This implementation can control the following UARTs: + * * SoCFPGA On-board UARTs + * * Altera 16550 Compatible Soft IP UART + * + * The following reference materials were used in the design of this API: + * * Synopsys® DesignWare DW_apb_uart Databook v3.10a + * + * @{ + */ + +/*! + * \addtogroup UART_BASIC UART Basic + * + * This group of APIs provides basic access to the UART to initialize, + * uninitialize, read, write, and reset the UART. + * + * @{ + */ + +/*! + * This type definition enumerates the list of UARTs available on the system. + */ +typedef enum ALT_16550_DEVICE_e +{ + /*! + * This option selects UART0 in the SoC FPGA. + */ + ALT_16550_DEVICE_SOCFPGA_UART0 = 0, + + /*! + * This option selects UART1 in the SoC FPGA. + */ + ALT_16550_DEVICE_SOCFPGA_UART1 = 1, + + /*! + * This option selects an Altera 16550 Compatible soft IP UART. The memory + * location of the device must be provided as part of the initialization. + */ + ALT_16550_DEVICE_ALTERA_16550_UART = 0x100 +} +ALT_16550_DEVICE_t; + +/*! + * This structure is used to represent a handle to a specific UART on the + * system. The internal members are undocumented and should be not altered + * outside of this API. + */ +typedef struct ALT_16550_HANDLE_s +{ + ALT_16550_DEVICE_t device; + void * location; + alt_freq_t clock_freq; + uint32_t data; + uint32_t fcr; +} +ALT_16550_HANDLE_t; + +/*! + * Performs the initialization steps needed by the UART. This should be the + * first API call made when accessing a particular UART + * + * The default UART setting is 8 databits, no parity, 1 stopbit, and 57600 + * baud. + * + * For the SoCFPGA UARTs, The ALT_CLK_L4_SP clock needs to be setup before + * initialization. + * + * \param device + * The UART device identifier. + * + * \param location + * The memory of the location for the given UART. For SoCFPGA + * UARTs, this parameter is ignored. + * + * \param clock_freq + * The clock frequency of the serial clock for the given UART. + * For SoCFPGA UARTs, this paramter is ignored. + * + * \param handle + * [out] A pointer to a handle that will represent the UART. This + * handle should subsequently be used when calling other UART + * APIs. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device identifier is invalid. + * \retval ALT_E_BAD_CLK The required clock is not yet setup. + */ +ALT_STATUS_CODE alt_16550_init(ALT_16550_DEVICE_t device, + void * location, + alt_freq_t clock_freq, + ALT_16550_HANDLE_t * handle); + +/*! + * Performs the uninitialization steps for the UART. This should be the last + * API call made to cleanup the UART. + * + * After calling this function, the handle will need to be initialized again + * before being used by calling alt_16550_init(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_uninit(ALT_16550_HANDLE_t * handle); + +/*! + * Resets the UART to the default configuration. The UART will be reset and + * reinitialized. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_reset(ALT_16550_HANDLE_t * handle); + +/*! + * Starts the UART after all configuration has been completed. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Stops the UART. While UART configuration can be done while enabled, it is + * not recommended. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads a single character from the UART receiver buffer. This API should + * only be used when FIFOs are disabled. + * + * \param handle + * The UART device handle. + * + * \param item + * [out] Pointer to an output parameter that contains the in + * receiver buffer of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_read(ALT_16550_HANDLE_t * handle, + char * item); + +/*! + * Writes a single character to the UART transmitter buffer. This API should + * only be used when FIFOs are disabled. + * + * \param handle + * The UART device handle. + * + * \param item + * The character to write to the transmitter buffer of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_write(ALT_16550_HANDLE_t * handle, + char item); + +/*! + * @} + */ + +/*! + * \addtogroup UART_FIFO UART FIFO Interface + * + * This group of APIs provides access, configuration, and control of the UART + * FIFO. The FIFO allows the UART to buffer received data and data to be + * transmitted. + * + * @{ + */ + +/*! + * This type definition enumerates the receiver FIFO level conditions that + * will trigger the receiver FIFO to issue a receiver FIFO full event. + */ +typedef enum ALT_16550_FIFO_TRIGGER_RX_e +{ + /*! + * 1 or more character(s) in the receiver FIFO will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_RX_ANY = 0, + + /*! + * 25% or higher capacity usage in the receiver FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL = 1, + + /*! + * 50% or higher capacity usage in the receiver FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_HALF_FULL = 2, + + /*! + * 2 characters less than the receiver FIFO capacity will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL = 3 +} +ALT_16550_FIFO_TRIGGER_RX_t; + +/*! + * This type definition enumerates the transmitter FIFO level conditions that + * will trigger the transmitter FIFO to issue a transmitter FIFO empty event. + */ +typedef enum ALT_16550_FIFO_TRIGGER_TX_e +{ + /*! + * Transmitter FIFO being completely empty will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_TX_EMPTY = 0, + + /*! + * 2 or less character(s) in the transmitter FIFO will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY = 1, + + /*! + * 25% or less capacity usage in the transmitter FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL = 2, + + /*! + * 50% or less capacity usage in the transmitter FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_TX_HALF_FULL = 3 +} +ALT_16550_FIFO_TRIGGER_TX_t; + +/*! + * Enables FIFO on the UART. This will enable both the receiver FIFO and + * transmitter FIFO. Both FIFOs will be cleared. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Disables FIFOs on the UART. This will disable both the receiver FIFO and + * transmitter FIFO. Any data left in the FIFOs will be lost. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the given buffer from the receiver FIFO in the UART. + * + * The available characters in the FIFO can be determined by a few ways. Users + * can determine the number of items by calling alt_16550_fifo_level_get_rx(). + * + * Another way is by using the RX trigger and RX interrupt. First determine the + * RX FIFO size by calling alt_16550_fifo_size_get_rx(). Then set the desired + * trigger level by calling alt_16550_fifo_trigger_set_rx(). Calculate the + * triggering point by applying trigger description on the FIFO size. Enable RX + * interrupts by calling alt_16550_int_enable_rx(). When the RX interrupt fires + * due to the ALT_16550_INT_STATUS_RX_DATA condition, the calculated triggering + * point value can be used to determine the RX FIFO level. If the interrupt + * fires due to the ALT_16550_INT_STATUS_RX_TIMEOUT, the RX FIFO can be + * completely emptied by repeatedly polling the Line Status + * ALT_16550_LINE_STATUS_DR condition by calling alt_16550_line_status_get(). + * These steps are necessary if the UART does not implement FIFO level query + * functionality. As of 13.0sp1, this applies to the Altera 16550 Compatible + * Soft UART. + * + * Reading more data than that which is available can result in invalid data + * appearing like valid data. + * + * The FIFO must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param buffer + * [out] Pointer to a buffer where the specified count of + * characters from the receiver FIFO will be copied to. + * + * \param count + * The count of characters from the receiver FIFO to be copied. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_read(ALT_16550_HANDLE_t * handle, + char * buffer, + size_t count); + +/*! + * Writes the given buffer to the transmitter FIFO in the UART. + * + * The available space in the FIFO can be determined by a few ways. Users can + * determine the number of items by calculating the FIFO capacity minus the + * FIFO level. This can be done by calling alt_16550_fifo_size_get_tx() and + * alt_16550_fifo_level_get_tx() respectively. + * + * Another way is by using the TX trigger and TX interrupt. First determine the + * TX FIFO size by calling alt_16550_fifo_size_get_tx(). The set the desired + * trigger level by calling alt_16550_fifo_trigger_set_tx(). Calculate the + * triggering point by applying the trigger description on the FIFO size. + * Enable TX interrupts by calling alt_16550_int_enable_tx(). When the TX + * interrupt fires, calculate the empty entries in the FIFO by subtracting the + * TX FIFO size and the calculated value. These steps are necessary if the UART + * does not implement FIFO level query functionality. As of 13.0sp1, this + * applies to the Altera 16550 Compatible Soft UART. + * + * Writing more data that there is space can result in data lost due to + * overflowing. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param buffer + * Pointer to a buffer from where the specified count of + * characters will be copied to the transmitter FIFO. + * + * \param count + * The count of characters from the given buffer to be copied. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_write(ALT_16550_HANDLE_t * handle, + const char * buffer, + size_t count); + +/*! + * Clears the contents of the receiver FIFO. Any characters which were + * previously contained in that FIFO will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Clears the contents of the transmitter FIFO. Any characters which were + * previously contained in that FIFO will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Clears the contents of the receiver and transmitter FIFO. Any characters + * which were previously contained on those FIFOs will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_all(ALT_16550_HANDLE_t * handle); + +/*! + * Queries the size of the receiver FIFO. + * + * \param handle + * The UART device handle. + * + * \param size + * [out] Pointer to an output parameter that contains the size of + * the receiver FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_size_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * size); + +/*! + * Queries the size of the transmitter FIFO. + * + * \param handle + * The UART device handle. + * + * \param size + * [out] Pointer to an output parameter that contains the size of + * the transmitter FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_size_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * size); + +/*! + * Queries the current level of the receiver FIFO. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * For the Altera 16550 Compatible UART, it may not be possible to read the + * FIFO level and this function may always report 0. For more information on + * interacting with the FIFO in this situation, see documentation for + * alt_16550_fifo_read(). + * + * \param handle + * The UART device handle. + * + * \param level + * [out] Pointer to an output parameter that contains the level + * or number of characters in the receiver FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_level_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * level); + +/*! + * Queries the current level of the transmitter FIFO. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * For the Altera 16550 Compatible UART, it may not be possible to read the + * FIFO level and this function may always report 0. For more information on + * interacting with the FIFO in this situation, see documentation for + * alt_16550_fifo_write(). + * + * \param handle + * The UART device handle. + * + * \param level + * [out] Pointer to an output parameter that contains the level + * or number of characters in the transmitter FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_level_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * level); + +/*! + * Sets the receiver FIFO level which will trigger the receiver FIFO to issue + * receiver FIFO full event. For the list of available receiver FIFO trigger + * levels, see the documentation for ALT_16550_FIFO_TRIGGER_RX_t. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param trigger + * The level of the receiver FIFO which is needed to trigger a + * receiver FIFO full event. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_trigger_set_rx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_RX_t trigger); + +/*! + * Sets the transmitter FIFO level which will trigger the transmitter FIFO to + * transmitter FIFO empty event. For the list of available transmitter FIFO + * trigger levels, see the documentation for ALT_16550_FIFO_TRIGGER_TX_t. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param trigger + * The level of the transmitter FIFO which is needed to trigger a + * transmitter FIFO empty event. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_trigger_set_tx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_TX_t trigger); + +/*! + * @} + */ + +/*! + * \addtogroup UART_BAUD UART Baudrate Interface + * + * This group of APIs allows for the configuration of the UART's baudrate + * generation related functions. + * + * The UART baudrate is determined by dividing the ALT_CLK_L4_SP clock with + * the configured divisor. + * + * @{ + */ + +/*! + * This enumeration lists out the common baudrates used with modem and serial + * ports. Not every baudrate is available for the UART due to the limits of + * the serial clock frequency and divisor value. + */ +typedef enum ALT_16550_BAUDRATE_e +{ + ALT_16550_BAUDRATE_50 = 50, /*!< 50 bps baudrate. */ + ALT_16550_BAUDRATE_75 = 75, /*!< 75 bps baudrate. */ + ALT_16550_BAUDRATE_150 = 150, /*!< 150 bps baudrate. */ + ALT_16550_BAUDRATE_300 = 300, /*!< 300 bps baudrate. */ + ALT_16550_BAUDRATE_600 = 600, /*!< 600 bps baudrate. */ + ALT_16550_BAUDRATE_900 = 900, /*!< 900 bps baudrate. */ + ALT_16550_BAUDRATE_1200 = 1200, /*!< 1200 bps baudrate. */ + ALT_16550_BAUDRATE_1800 = 1800, /*!< 1800 bps baudrate. */ + ALT_16550_BAUDRATE_2400 = 2400, /*!< 2400 bps baudrate. */ + ALT_16550_BAUDRATE_3600 = 3600, /*!< 3600 bps baudrate. */ + ALT_16550_BAUDRATE_4800 = 4800, /*!< 4800 bps baudrate. */ + ALT_16550_BAUDRATE_7200 = 7200, /*!< 7200 bps baudrate. */ + ALT_16550_BAUDRATE_9600 = 9600, /*!< 9600 bps baudrate. */ + ALT_16550_BAUDRATE_14400 = 14400, /*!< 14400 bps baudrate. */ + ALT_16550_BAUDRATE_19200 = 19200, /*!< 19200 bps baudrate. */ + ALT_16550_BAUDRATE_28800 = 28800, /*!< 28800 bps baudrate. */ + ALT_16550_BAUDRATE_38400 = 38400, /*!< 38400 bps baudrate. */ + ALT_16550_BAUDRATE_57600 = 57600, /*!< 57600 bps baudrate. */ + ALT_16550_BAUDRATE_115200 = 115200 /*!< 115200 bps baudrate. */ +} +ALT_16550_BAUDRATE_t; + +/*! + * Gets the baudrate for the UART. + * + * This is done by calculating the baudrate from the divisor and the serial + * clock. The reported baudrate may not correspond exactly to the request + * baudrate. + * + * \param handle + * The UART device handle. + * + * \param baudrate + * [out] Pointer to an output paramter that contains the current + * baudrate of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_baudrate_get(ALT_16550_HANDLE_t * handle, + uint32_t * baudrate); + +/*! + * Sets the baudrate for the UART. This change will take effect when the UART + * moves from disabled to enabled. + * + * This is done by calculating the correct divisor using the request baudrate + * and the known serial clock. + * + * \param handle + * The UART device handle. + * + * \param baudrate + * The requested baudrate for the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + * \retval ALT_E_ARG_RANGE The given baudrate is not possible due to + * limitations of the baudrate divisor and/or + * serial clock. + */ +ALT_STATUS_CODE alt_16550_baudrate_set(ALT_16550_HANDLE_t * handle, + uint32_t baudrate); + +/*! + * Gets the baudrate divisor for the UART. + * + * The baudrate is determined by the following formula: + * * Baudrate = (serial clock frequency) / (16 * divisor) + * + * \param handle + * The UART device handle. + * + * \param divisor + * [out] Pointer to an output parameter that contains the current + * divisor used for baudrate generation. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_divisor_get(ALT_16550_HANDLE_t * handle, + uint32_t * divisor); + +/*! + * Sets the baudrate divisor for the UART. This change will take effect when + * the UART moves from disabled to enabled. + * + * The baudrate is determined by the following formula: + * * Baudrate = (serial clock frequency) / (16 * divisor) + * + * \param handle + * The UART device handle. + * + * \param divisor + * The specified divisor value to use for baudrate generation. + * Valid values are 1 - 65535. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART identifier is invalid or the + * specified divisor is not supported by the + * UART. + */ +ALT_STATUS_CODE alt_16550_divisor_set(ALT_16550_HANDLE_t * handle, + uint32_t divisor); + +/*! + * @} + */ + +/*! + * \addtogroup UART_INT UART Interrupt Interface + * + * This group of APIs provides access, configuration, and control of the + * UART interrupts. + * + * @{ + */ + +/*! + * This type definition enumerates the different interrupt conditions that can + * be generated by the UART controller. + * + * Interrupts are listed in highest to lowest priority order. + */ +typedef enum ALT_16550_INT_STATUS_e +{ + /*! + * This interrupt signals that a overrun, parity, or framing error + * occurred, or a break event occured. The interrupt is cleared by reading + * the line status by calling alt_16550_line_status_get() or by disabling + * line status interrupts by calling alt_16550_int_disable_line(). + */ + ALT_16550_INT_STATUS_LINE = 0x6, + + /*! + * This interrupt signals that some data is available to be read from the + * UART. The definition of some depends on whether FIFOs are enabled or + * not. + * + * If FIFOs are disabled, this interrupt signals that the receiver + * contains data. In this case, the interrupt is cleared by reading the + * data from the UART by calling alt_16550_read(). + * + * If FIFOs are enabled, this interrupt signals that the receiver FIFO + * level is above the receiver trigger level specified. In this case, the + * interrupt is cleared by reading a sufficiently large buffer from the + * receiver FIFO such that the FIFO is filled below the receiver trigger + * level specified by calling alt_16550_fifo_read() or by adjusting the + * receiver trigger level appropriately by calling + * alt_16550_fifo_trigger_set_rx(). + * + * In either case, this interrupt can also be cleared by disabling + * receiver interrupts by calling alt_16550_int_disable_rx(). + */ + ALT_16550_INT_STATUS_RX_DATA = 0x4, + + /*! + * This interrupt signals that data is available in the receiver FIFO and + * that there has been no activity with the receiver FIFO for the last 4 + * character frames. In essence, the receiver FIFO has temporarily settled + * thus it may be a good time to empty the receiver FIFO. This interrupt + * is only available if FIFOs are enabled. The interrupt is cleared by + * reading from the receiver FIFO by calling alt_16550_fifo_read() or by + * disabling receiver interrupts by calling alt_16550_int_disable_rx(). + */ + ALT_16550_INT_STATUS_RX_TIMEOUT = 0xC, + + /*! + * This interrupt signals that the transmitter is idling. The definition + * of idling depends on whether FIFOs are enabled or not. + * + * If FIFOs are disabled, this interrupt signals that the transmitter + * shift register is empty. In this case, the interrupt is cleared by + * writing data to the UART by calling alt_16550_write(). + * + * If FIFO are enabled, this interrupt signals that the transmitter FIFO + * level is below the transmitter trigger level specified. In this case, + * the interrupt is cleared by writing a sufficiently large buffer to the + * transmitter FIFO such that the FIFO is filled above the transmitter + * trigger level specified by calling alt_16550_fifo_write() or by + * adjusting the transmitter trigger level appropriately by calling + * alt_16550_fifo_trigger_set_tx(). + * + * In either case, this interrupt can also be cleared by disabling + * transmitter interrupts by calling alt_16550_int_disable_tx(). + */ + ALT_16550_INT_STATUS_TX_IDLE = 0x2, + + /*! + * Modem status interrupt pending. The interrupt is cleared by reading the + * modem status by calling alt_16550_modem_status_get() or by disabling + * modem status interrupts by calling alt_16550_int_disable_modem(). + */ + ALT_16550_INT_STATUS_MODEM = 0x0, + + /*! + * No interrupts pending. + */ + ALT_16550_INT_STATUS_NONE = 0x1 +} +ALT_16550_INT_STATUS_t; + +/*! + * Enables the receiver FIFO to generate interrupts. Enabling this interrupt + * allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_RX_DATA + * * ALT_16550_INT_STATUS_RX_TIMEOUT + * + * This interrupt is disabled by default. + * + * The FIFOs must also be enabled for this interrupt to actually be generated. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the receiver FIFO from generating interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the transmitter FIFO to generate interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_TX_IDLE + * + * This interrupt is disabled by default. + * + * The FIFOs must also be enabled for this interrupt to actually be generated. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the transmitter FIFO from generating interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the receiver to generate line status interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_LINE + * + * This interrupt is disabled by default. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_line(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the receiver from generating line status interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_line(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the UART to generate modem status interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_MODEM + * + * This interrupt is disabled by default. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_modem(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the UART from generate modem status interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_modem(ALT_16550_HANDLE_t * handle); + +/*! + * Disables all interrupts on the UART. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_all(ALT_16550_HANDLE_t * handle); + +/*! + * Queries the interrupt status of the UART. This returns the highest priority + * interrupt pending. The appropriate interrupts must be enabled for them be + * generated in the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * interrupt status of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_status_get(ALT_16550_HANDLE_t * handle, + ALT_16550_INT_STATUS_t * status); + +/*! + * @} + */ + +/*! + * \addtogroup UART_MODEM UART Modem Interface + * + * This group of APIs provides access, configuration, and control of the UART + * Modem interface. + * + * @{ + */ + +/*! + * This type definition enumerates the set of UART modem status conditions as + * register mask values. + */ +typedef enum ALT_16550_MODEM_STATUS_e +{ + /*! + * Data Carrier Detect. This status indicates that the carrier has been + * detected by the modem. It corresponds to an inverted dcd_n input. DCD + * is unasserted when dcd_n is logic 1 and asserted when dcd_n is logic 0. + */ + ALT_16550_MODEM_STATUS_DCD = 1 << 7, + + /*! + * Ring Indicator. This status indicates that the telephone ringing signal + * has been redeived by the modem. It corresponds to an inverted ri_n + * input. RI is unasserted when ri_n is logic 1 and asserted when ri_n is + * logic 0. + */ + ALT_16550_MODEM_STATUS_RI = 1 << 6, + + /*! + * Data Set Ready. This status indicates that the modem is ready to + * establish communications with the UART. It corresponds to an inverted + * dsr_n input. DSR is unasserted when dsr_n is logic 1 and asserted when + * dsr_n is logic 0. + */ + ALT_16550_MODEM_STATUS_DSR = 1 << 5, + + /*! + * Clear To Send. This status indicates the current state of the modem + * cts_n line. It corresponds to an inverted cts_n input. CTS is + * unasserted when cts_n is logic 1 and asserted when cts_n is logic 0. + */ + ALT_16550_MODEM_STATUS_CTS = 1 << 4, + + /*! + * Delta Data Carrier Detect. This status condition indicates that the + * Data Carrier Detect has changed since the last time the modem status + * was read. Reading the modem status clears this status. For more + * information about the Data Carrier Detect status, see + * ALT_16550_MODEM_STATUS_DCD. + */ + ALT_16550_MODEM_STATUS_DDCD = 1 << 3, + + /*! + * Trailing Edge of Ring Indicator. This status indicates that the Ring + * Indicator has changed from asserted to unasserted. Reading the modem + * status will clear this status. For more information about the Ring + * Indicator status, reference ALT_16550_MODEM_STATUS_RI. + */ + ALT_16550_MODEM_STATUS_TERI = 1 << 2, + + /*! + * Delta Data Set Ready. This status condition indicates that the Data Set + * Ready has changed since the last time the modem status was read. + * Reading the modem status will clear this status. For more information + * about the Data Set Ready status, see ALT_16550_MODEM_STATUS_DSR. + */ + ALT_16550_MODEM_STATUS_DDSR = 1 << 1, + + /*! + * Delta Clear To Send. This status condition indicates that the Clear To + * Send has changed since the last time the modem status was read. Reading + * the modem status will clear this status. For more information about the + * Clear To Send status, see ALT_16550_MODEM_STATUS_CTS. + */ + ALT_16550_MODEM_STATUS_DCTS = 1 << 0 +} +ALT_16550_MODEM_STATUS_t; + +/*! + * Enables automatic flow control in the UART modem. When in this mode, the + * rts_n is gated with the threshold trigger condition of the receiver FIFO. + * + * The Altera 16550 Compatible Soft IP UART may not have this option enabled. + * + * The FIFOs must be enabled for flow control to be used. + * + * The recommended bring up for flow control is as follows: + * * Enable automatic flow control by calling alt_16550_flowcontrol_enable(). + * This will allow both the receiver FIFO and user RTS to control the rts_n + * output. Because the user RTS is not enabled, the rts_n will be inactive + * high. + * * Enable RTS by calling alt_16550_modem_enable_rts(). This will give the + * receiver FIFO to have full control of the rts_n output. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_flowcontrol_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Disables automatic flow control in the UART modem. + * + * The recommended bring down for flow control is as follows: + * * Disable RTS by calling alt_16550_modem_disable_rts(). This will disable + * generation of the rts_n ouput. + * * Disable automatic flow control by calling + * alt_16550_flowcontrol_disable(). + * + * The receiver FIFO will still be active after these steps. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_flowcontrol_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Puts the UART in loopback mode. This is used for diagnostic and test + * purposes. + * + * The SoCFPGA UARTs does not support automatic flow control when in loopback + * mode. + * + * The Altera 16550 Compatible Soft IP UART implements this in 13.0sp1 and + * later. Setting this has no effect with 13.0. + * + * When in this mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are + * disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) + * are held inactive high externally and internally looped back to the inputs. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_loopback_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Takes the UART out of loopback mode. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_loopback_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the OUT1 output. OUT1 is inverted then driven out to out1_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_out1(ALT_16550_HANDLE_t * handle); + +/*! + * Unasserts the OUT1 output. OUT1 is inverted then driven out to out1_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_out1(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the OUT2 output. OUT2 is inverted then driven out to out2_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_out2(ALT_16550_HANDLE_t * handle); + +/*! + * Unasserts the OUT2 output. OUT2 is inverted then driven out to out2_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_out2(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the RTS (Request To Send) output. RTS is inverted then driven out + * to rts_n. RTS is used to inform the modem that the UART is ready to receive + * data. + * + * There are special considerations when the UART is in automatic flow control + * mode. See alt_16550_flowcontrol_enable() for more information. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_rts(ALT_16550_HANDLE_t * handle); + +/*! + * Deaserts the RTS (Request To Send) output. RTS is inverted then driven out + * to rts_n. + * + * There are special considerations when the UART is in automatic flow control + * mode. See alt_16550_flowcontrol_enable() for more information. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_rts(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the DTR (Data Terminal Ready) output. DTR is inverted then driven + * out to dtr_n. DTR is used to inform the modem that UART is ready to + * establish communications. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_dtr(ALT_16550_HANDLE_t * handle); + +/*! + * Deasserts the DTR (Data Terminal Ready) output. DTR is inverted then driven + * out to dtr_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_dtr(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the modem status from the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * modem status of the UART as a register mask. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status); + +/*! + * @} + */ + +/*! + * \addtogroup UART_LINE UART Line Interface + * + * This group of APIs provides access, configuration, and control of the UART + * Line interface. + * + * @{ + */ + +/*! + * This type definition enumerates the supported databits per frame. + */ +typedef enum ALT_16550_DATABITS_e +{ + /*! + * This option selects 5 databits per frame. + */ + ALT_16550_DATABITS_5 = 0, + + /*! + * This option selects 6 databits per frame. + */ + ALT_16550_DATABITS_6 = 1, + + /*! + * This option selects 7 databits per frame. + */ + ALT_16550_DATABITS_7 = 2, + + /*! + * This option selects 8 databits per frame. + */ + ALT_16550_DATABITS_8 = 3 +} +ALT_16550_DATABITS_t; + +/*! + * This type definition enumerates the supported stopbits per frame. + */ +typedef enum ALT_16550_STOPBITS_e +{ + /*! + * This options specifies 1 stopbit per frame. + */ + ALT_16550_STOPBITS_1 = 0, + + /*! + * This options specifies 2 stopbits per frame. If the frame is + * configured with 5 databits, 1.5 stopbits is used instead. + */ + ALT_16550_STOPBITS_2 = 1 +} +ALT_16550_STOPBITS_t; + +/*! + * This type definition enumerates the possible parity to use per frame. + */ +typedef enum ALT_16550_PARITY_e +{ + /*! + * This option disables the parity error detection bit in the data frame. + */ + ALT_16550_PARITY_DISABLE = 0, + + /*! + * This option enables the odd parity error detection bit in the data + * frame. + */ + ALT_16550_PARITY_ODD = 1, + + /*! + * This option enables the even parity error detection bit in the data + * frame. + */ + ALT_16550_PARITY_EVEN = 2 +} +ALT_16550_PARITY_t; + +/*! + * This type definition enumerates the set of UART line status conditions as + * register mask values. + */ +typedef enum ALT_16550_LINE_STATUS_e +{ + /*! + * Receiver FIFO Error. This status indicates that one or more parity + * error, framing error, or break indication exists in the receiver FIFO. + * It is only set when FIFO is enabled. This status cleared when line + * status is read, the character with the issue is at the top of the FIFO, + * and when no other issues exist in the FIFO. + */ + ALT_16550_LINE_STATUS_RFE = 1 << 7, + + /*! + * Transmitter EMpTy (Empty). This status indicates that transmitter shift + * register is empty. If FIFOs are enabled, the status is set when the + * transmitter FIFO is also empty. This status is cleared when the + * transmitter shift registers is loaded by writing to the UART + * transmitter buffer or transmitter FIFO if FIFOs are enabled. This is + * done by calling alt_16550_write() and alt_16550_fifo_write() + * respectively. + */ + ALT_16550_LINE_STATUS_TEMT = 1 << 6, + + /*! + * Transmitter Holding Register Empty. This status indicates that the + * transmitter will run out of data soon. The definition of soon depends + * on whether the FIFOs are enabled. + * + * If FIFOs are disabled, this status indicates that the transmitter will + * run out of data to send after the current transmit shift register + * completes. In this case, this status is cleared when the data is + * written to the UART. This can be done by calling alt_16550_write(). + * + * If FIFOs are enabled, this status indicates that the transmitter FIFO + * level is below the transmitter trigger level specified. In this case, + * this status is cleared by writing a sufficiently large buffer to the + * transmitter FIFO such that the FIFO is filled above the transmitter + * trigger level specified by calling alt_16550_fifo_write() or by + * adjusting the transmitter trigger level appropriately by calling + * alt_16550_fifo_trigger_set_tx(). + * + * \internal + * The implementation of the UART driver always ensures that IER[7] is + * set. This means that the UART always has Programmable THRE (Transmitter + * Holding Register Empty) Interrupt Mode Enable (PTIME) enabled. + * \endinternal + */ + ALT_16550_LINE_STATUS_THRE = 1 << 5, + + /*! + * Break Interrupt. This status indicates that a break interrupt sequence + * is detected in the incoming serial data. This happens when the the data + * is 0 for longer than a frame would normally be transmitted. The break + * interrupt status is cleared by reading the line status by calling + * alt_16550_line_status_get(). + * + * If FIFOs are enabled, this status will be set when the character with + * the break interrupt status is at the top of the receiver FIFO. + */ + ALT_16550_LINE_STATUS_BI = 1 << 4, + + /*! + * Framing Error. This status indicates that a framing error occurred in + * the receiver. This happens when the receiver detects a missing or + * incorrect number of stopbit(s). + * + * If FIFOs are enabled, this status will be set when the character with + * the framing error is at the top of the FIFO. When a framing error + * occurs, the UART attempts to resynchronize with the transmitting UART. + * This status is also set if break interrupt occurred. + */ + ALT_16550_LINE_STATUS_FE = 1 << 3, + + /*! + * Parity Error. This status indicates that a parity error occurred in the + * receiver. + * + * If FIFOs are enabled, this status will be set when the character with + * the parity error is at the top of the receiver FIFO. This status is + * also set if a break interrupt occurred. + */ + ALT_16550_LINE_STATUS_PE = 1 << 2, + + /*! + * Overrun Error. This status indicates that an overrun occurred in the + * receiver. + * + * If FIFOs are disabled, the arriving character will overwrite the + * existing character in the receiver. Any previously existing + * character(s) will be lost. + * + * If FIFOs are disabled, the arriving character will be discarded. The + * buffer will continue to contain the preexisting characters. + */ + ALT_16550_LINE_STATUS_OE = 1 << 1, + + /*! + * Data Ready. This status indicates that the receiver or receiver FIFO + * contains at least one character. + */ + ALT_16550_LINE_STATUS_DR = 1 << 0 +} +ALT_16550_LINE_STATUS_t; + +/*! + * Sets the configuration for a given character frame. + * + * \param handle + * The UART device handle. + * + * \param databits + * The number of databits for each character frame. + * + * \param parity + * The parity to use for each character frame. + * + * \param stopbits + * The number of stopbits for each character frame. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_config_set(ALT_16550_HANDLE_t * handle, + ALT_16550_DATABITS_t databits, + ALT_16550_PARITY_t parity, + ALT_16550_STOPBITS_t stopbits); + +/*! + * Starts transmitting a break condition by transmitting a logic 0 state + * longer than a frame would normally be transmitted. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_break_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Stops transmitting a break condition. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_break_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the line status from the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * line status of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_16550_UART_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_cache.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_cache.h new file mode 100644 index 0000000..8d088ab --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_cache.h @@ -0,0 +1,964 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_CACHE_H__ +#define __ALT_CACHE_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup CACHE_MGR Cache Management API + * + * This module defines the cache management API for enabling and disabling L1 + * data cache, L1 instruction cache, L1 dynamic branch prediction caches, L1 + * TLB cache, and L2 cache in the SoC. As well, many it allows users to perform + * cache maintenance operations on these caches. This includes the following + * operations: + * * Invalidate: Marks the cache line as being invalid, freeing up the space + * to cache other data. All APIs which enable caches invalidates the memory + * before being enabling the cache. + * * Clean: If the cache line is dirty, it synchronizes the cache line data + * with the upper level memory system and marks that line as clean. All APIs + * which disable caches cleans the memory before disabling the cache. + * * Purge: A term used in this API as a short form for clean and invalidate. + * This operation cleans and invalidates a cache line in that order, as a + * single command to the cache controller. + * + * The following reference materials were used in the design of this API: + * * ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition + * * Cortex™-A9 Technical Reference Manual + * * Cortex™-A9 MPCore Technical Reference Manual + * * CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference + * Manual + * + * @{ + */ + +/*! + * \addtogroup CACHE_SYS System Level Cache Management API + * + * This API group provides cache maintenance operations which affects multiple + * cache levels. + * + * The enable and disable functions enables and disables all caches in the + * system respectively. For caches shared by the CPU core(s), particularly the + * L2 cache, once that cache is enabled or disabled it will not be invalidated + * or cleaned again respectively. This allows the safe system-wide enable and + * disable to be used in single-core and multi-core scenarios. + * + * For cache maintenance operations, this API implements the procedures + * outlined in the L2C-310 Technical Reference Manual, section 3.3.10, + * subsection "System cache maintenance considerations". This allows for a + * convenient way to invalidate, clean, or clean and invalidate cache data from + * the L1 to L2 to L3 while avoiding any potential race conditions in + * mutli-core or multi-master scenarios. It assumes that the L1 and L2 cache is + * set in "non-exclusive" mode. This means a segment of data can reside in both + * the L1 and L2 simultaneously. This is the default mode for caches in the + * system. + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * @{ + */ + +/*! + * Enables support for a non-flat virtual memory. A flat virtual memory is + * where every virtual address matches exactly to the physical address, making + * the virtual to physical translation trivial. Adding support for non-flat + * adds some overhead for the VA to PA translation and error detection. + * + * To enable non-flat virtual memory support, defined + * ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY=1 in your Makefile when compiling + * HWLibs. + */ +#ifndef ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY +#define ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY (0) +#endif + +/*! + * This is the system wide cache line size, given in bytes. + */ +#define ALT_CACHE_LINE_SIZE 32 + +/*! + * Enables all caches and features which improve reliability and speed on all + * cache controllers visible to the current CPU core. This includes parity + * error detection. Cache controllers visible to multiple CPU cores, for + * example the L2, will first be checked to be disabled before being enabled. + * All necessary cache maintenance operations will be done automatically. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_system_enable(void); + +/*! + * Disables all cache controllers visible to the current CPU core. Cache + * controllers visible to multiple CPU cores, for example the L2, will first + * be checked to be enabled before being disabled. All necessary cache + * maintenance operations will be done automatically. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_system_disable(void); + +/*! + * Invalidates the specified contents of all cache levels visible to the + * current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L2 invalidate address(es) + * -# L2 cache sync + * -# L1 invalidate address(es) + * -# DSB instruction + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_invalidate(void * vaddress, size_t length); + +/*! + * Cleans the specified contents of all cache levels visible to the current + * CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L1 clean address(es) + * -# DSB instruction + * -# L2 clean address(es) + * -# L2 cache sync + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_clean(void * vaddress, size_t length); + +/*! + * Cleans and invalidates the specified contents of all cache levels visible + * to the current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L1 clean address(es) + * -# DSB instruction + * -# L2 clean and invalidate address(es) + * -# L2 cache sync + * -# L1 invalidate address(es) + * -# DSB instruction + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_purge(void * vaddress, size_t length); + +/*! + * @} + */ + +/*! + * \addtogroup CACHE_L1 L1 Cache Management API + * + * This API group provides functions to interact with various components of the + * L1 cache on the SoCFPGA. This includes the following cache components: + * * Instruction Cache + * * Data Cache + * * Parity error detection + * * Dynamic branch prediction + * * Data prefetching + * + * The API within this group only affects the L1 cache on the current CPU. To + * interact the L1 cache on another CPU, the API must be called from that other + * CPU. + * + * With respect to bring-up, the L1 and L2 cache controller setups are fully + * independent. The L2 can be setup at any time, before or after the L1 is setup. + * \internal + * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". + * \endinternal + * + * @{ + */ + +/*! + * Enables all L1 caches and features on the current CPU core. This includes + * the instruction cache, data cache, parity error detection, branch target + * address cache, global history buffer, and data prefetching. All necessary + * maintenance tasks will be taken care of. + * + * This function should not be mixed with other L1 cache related functions + * which enable or disable caches individually. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_enable_all(void); + +/*! + * Disables all L1 caches and features on the current CPU core. This includes + * the instruction cache, data cache, parity error detection, branch target + * address cache, global history buffer, and data prefetching. All necessary + * maintenance tasks will be taken care of. + * + * This function should not be mixed with other L1 cache related functions + * which enable or disable caches individually. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_disable_all(void); + +/*! + * Enables the L1 instruction cache on the current CPU core. If the cache is + * already enabled, nothing is done. Otherwise the instruction cache is first + * invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_enable(void); + +/*! + * Disables the L1 instruction cache on the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_disable(void); + +/*! + * Returns \b true when the L1 instruction cache is enabled and \b false when + * it is disabled on the current CPU core. + * + * \retval true The L1 instruction cache is enabled. + * \retval false The L1 instruction cache is disabled. + */ +bool alt_cache_l1_instruction_is_enabled(void); + +/*! + * Invalidates the contents of the L1 instruction cache on the current CPU + * core. + * + * Normally this is done automatically as part of + * alt_cache_l1_instruction_enable(), but in certain circumstances it may be + * necessary to invalidate it manually. An example of this situation is when + * the address space is remapped and the processor executes instructions from + * the new memory area. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_invalidate(void); + +/*! + * Enables the L1 data cache on the current CPU core. + * + * If the cache is already enabled nothing is done. Otherwise the data cache is + * first invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_enable(void); + +/*! + * Disables the L1 data cache on the current CPU core. + * + * If the cache is already disabled nothing is done. Otherwise the data cache + * is first cleaned before being disabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_disable(void); + +/*! + * Returns \b true when the L1 data cache is enabled and \b false when it is + * disabled on the current CPU core. + * + * \retval true The L1 data cache is enabled. + * \retval false The L1 data cache is disabled. + */ +bool alt_cache_l1_data_is_enabled(void); + +/*! + * Invalidates the specified contents of the L1 data cache on the current CPU + * core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param vaddress + * The virtual address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_invalidate(void * vaddress, size_t length); + +/*! + * Invalidates the entire contents of the L1 data cache on the current CPU + * core. + * + * Normally this is done automatically as part of alt_cache_l1_data_enable(), + * but in certain circumstances it may be necessary to invalidate it manually. + * An example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_invalidate_all(void); + +/*! + * Cleans the specified contents of the L1 data cache on the current CPU core + * for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param vaddress + * The virtual address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_clean(void * vaddress, size_t length); + +/*! + * Cleans the entire L1 data cache for the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_clean_all(void); + +/*! + * Cleans and invalidates the specified contents of the L1 data cache on the + * current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * Normally this is done automatically as part of alt_cache_l1_data_disable(), + * but in certain circumstances it may be necessary to purged it manually. + * An example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + * + * \param vaddress + * The virtual address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_purge(void * vaddress, size_t length); + +/*! + * Cleans and invalidates the entire L1 data cache for the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_purge_all(void); + +/*! + * Enables the parity error detection feature in the L1 caches on the current + * CPU core. + * + * Ideally parity should be enabled before any L1 caches are enabled. If the + * instruction, data, and / or dynamic branch predictor caches are already + * enabled, they will first be cleaned (if needed) and disabled before parity + * is enabled in hardware. Afterwards, the affected caches will be invalidated + * and enabled. + * + * Parity and TLB interaction deserves special attention. The TLB is considered + * to be a L1 cache but is enabled when the MMU, which is grouped in another + * API, is enabled. Due to the system-wide influence of the MMU, it cannot be + * disabled and enabled with impunity as the other L1 caches, which are + * designed to operate as transparently as possible. Thus parity error + * detection must be enabled before the L1 TLB cache, and by extension the MMU, + * is enabled. + * + * For a parity error to be reported, the appropriate CPU PARITYFAIL interrupt + * for the current CPU core must be enabled using the interrupt controller API. + * For CPU0, ALT_INT_INTERRUPT_CPU0_PARITYFAIL is asserted if any parity error + * is detected while the other PARITYFAIL interrupts are for parity errors in a + * specific memory. Refer to the interrupt controller API for more details + * about programming the interrupt controller. + * + * In the event of a parity error is detected, the appropriate CPU parity + * interrupt will be raised. CPU parity interrupts are all edge triggered and + * are cleared by acknowledging them in the interrupt controller API. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_parity_enable(void); + +/*! + * Disables parity error detection in the L1 caches. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_parity_disable(void); + +/*! + * Returns \b true when parity error detection is enabled and \b false when it + * is disabled on the current CPU core. + * + * \retval true Parity error detection for L1 caches is + * enabled. + * \retval false Parity error detection for L1 caches is + * disabled. + */ +bool alt_cache_l1_parity_is_enabled(void); + +/*! + * Enables the dynamic branch predictor features on the current CPU core. + * + * This operation enables both the Branch Target Address Cache (BTAC) and + * the Global History Buffer (GHB). Affected caches are automatically + * invalidated before use. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_enable(void); + +/*! + * Disables the dynamic branch predictor features on the current CPU core. + * + * This operation disables both the Branch Target Address Cache (BTAC) and + * the Global History Buffer (GHB). + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_disable(void); + +/*! + * Returns \b true when both the dynamic predictor features are enabled and + * \b false when they are disabled on the current CPU core. + * + * \retval true The L1 branch predictor caches are all enabled. + * \retval false Some or all L1 branch predictor caches are + * disabled. + */ +bool alt_cache_l1_branch_is_enabled(void); + +/*! + * Invalidates the dynamic branch predictor feature caches on the current CPU + * core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_invalidate(void); + +/*! + * Enables the L1 cache data prefetch feature on the current CPU core. + * + * This allows data to be prefetched into the data cache before it is to be + * used. For example in a loop the current iteration may want to preload the + * data which will be used in the next teration. This is done by using the PLD + * instructions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_prefetch_enable(void); + +/*! + * Disables the L1 cache data prefetch feature on the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_prefetch_disable(void); + +/*! + * Returns \b true if the L1 cache data prefetch feature is enabled and + * \b false if it is disabled on the current CPU core. + * + * \retval true The L1 data cache prefetch feature is enabled. + * \retval false The L1 data cache prefetch feature is disabled. + */ +bool alt_cache_l1_prefetch_is_enabled(void); + +/*! + * @} + */ + +/*! + * \addtogroup CACHE_L2 L2 Cache Management API + * + * This API group provides functions to interact with various features of the + * L2 cache on the SoCFPGA. This includes the following features: + * * L2 cache + * * Parity error detection + * * Data prefetching + * * Interrupt Management + * + * \internal + * Additional features that may be implemented in the future: + * * Lockdown + * * Event counter + * \endinternal + * + * The API within this group affects the L2 cache which is visible to all CPUs + * on the system. + * + * With respect to bring-up, the L1 and L2 cache controller setups are fully + * independent. The L2 can be setup at any time, before or after the L1 is setup. + * \internal + * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". + * \endinternal + * + * @{ + */ + +/*! + * Initializes the L2 cache controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_cache_l2_init(void); + +/*! + * Uninitializes the L2 cache controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_cache_l2_uninit(void); + +/*! + * Enables the L2 cache features for data and instruction prefetching. + * + * Prefetching can be enabled or disabled while the L2 cache is enabled. + * \internal + * Source: Use the Prefetch Control Register. + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_prefetch_enable(void); + +/*! + * Disables the L2 cache features for data and instruction prefetching. + * + * Prefetching can be enabled or disabled while the L2 cache is enabled. + * \internal + * Source: Use the Prefetch Control Register. + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_prefetch_disable(void); + +/*! + * Returns \b true if either L2 cache data or instruction prefetch features are + * enabled and \b false if no prefetching features are enabled. + * + * \retval true The L2 data and instruction prefetch features + * are enabled. + * \retval false Some L2 data and instruction prefetch features + * are disabled. + */ +bool alt_cache_l2_prefetch_is_enabled(void); + +/*! + * Enables parity error detection in the L2 cache. + * + * Ideally parity should be enabled before the L2 cache is enabled. If the + * cache is already enabled, it will first be cleaned and disabled before + * parity is enabled in hardware. Afterwards, the cache will be invalidated and + * enabled. + * + * For a parity error to be reported, the ALT_CACHE_L2_INTERRUPT_PARRD and / or + * ALT_CACHE_L2_INTERRUPT_PARRT interrupt condition(s) must be enabled. This is + * done by calling alt_cache_l2_int_enable(). As well, the L2 cache interrupt + * must be enabled using the interrupt controller API. Refer to the interrupt + * controller API for more details about programming the interrupt controller. + * + * In the event of a parity error is detected, the appropriate L2 cache parity + * interrupt will be raised. To clear the parity interrupt(s), the appropriate + * L2 cache parity interrupt must be cleared by calling + * alt_cache_l2_int_status_clear(). + * + * For ECC support, refer to the ECC related API documentation for more + * information. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_parity_enable(void); + +/*! + * Disables parity error detection in the L2 cache. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_parity_disable(void); + +/*! + * Returns \b true when parity error detection is enabled and \b false when it + * is disabled. + * + * \retval true The L2 cache parity error detection feature is + * enabled. + * \retval false The L2 cache parity error detection feature is + * disabled. + */ +bool alt_cache_l2_parity_is_enabled(void); + +/*! + * Enables the L2 cache. + * + * If the L2 cache is already enabled, nothing is done. Otherwise the entire + * contents of the cache is first invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_enable(void); + +/*! + * Disables the L2 cache. + * + * If the L2 cache is already disabled, nothing is done. Otherwise the entire + * contents of the cache is first cleaned before being disabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_disable(void); + +/*! + * Returns \b true when the L2 cache is enabled and \b false when it is + * disabled. + * + * \retval true The L2 cache is enabled. + * \retval false The L2 cache is disabled. + */ +bool alt_cache_l2_is_enabled(void); + +/*! + * Flushes the L2 cache controller hardware buffers. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_sync(void); + +/*! + * Invalidates the specified contents of the L2 cache for the given memory + * segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_invalidate(void * paddress, size_t length); + +/*! + * Invalidates th entire contents of the L2 cache. + * + * Normally this is done automatically as part of alt_cache_l2_enable(), but + * in certain circumstances it may be necessary to invalidate it manually. An + * example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_invalidate_all(void); + +/*! + * Cleans the specified contents of the L2 cache for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_clean(void * paddress, size_t length); + +/*! + * Cleans the entire L2 cache. All L2 cache controller interrupts will be + * temporarily disabled while the clean operation is in progress and restored + * once the it is finished. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_clean_all(void); + +/*! + * Cleans and invalidates the specified contents of the L2 cache for the + * given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l2_purge(void * paddress, size_t length); + +/*! + * Cleans and invalidates the entire L2 cache. All L2 cache controller + * interrupts will be temporarily disabled while the clean and invalidate + * operation is in progress and restored once the it is finished. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_purge_all(void); + +/*! + * This type definition enumerates all the interrupt conditions that can be + * generated by the L2 cache controller as register mask values. + */ +enum ALT_CACHE_L2_INTERRUPT_e +{ + /*! Decode error received on the master ports from L3. */ + ALT_CACHE_L2_INTERRUPT_DECERR = 1 << 8, + + /*! Slave error received on the master ports from L3. */ + ALT_CACHE_L2_INTERRUPT_SLVERR = 1 << 7, + + /*! Error on the L2 data RAM read. */ + ALT_CACHE_L2_INTERRUPT_ERRRD = 1 << 6, + + /*! Error on the L2 tag RAM read. */ + ALT_CACHE_L2_INTERRUPT_ERRRT = 1 << 5, + + /*! Error on the L2 data RAM write. */ + ALT_CACHE_L2_INTERRUPT_ERRWD = 1 << 4, + + /*! Error on the L2 tag RAM write. */ + ALT_CACHE_L2_INTERRUPT_ERRWT = 1 << 3, + + /*! Parity error on the L2 data RAM read. */ + ALT_CACHE_L2_INTERRUPT_PARRD = 1 << 2, + + /*! Parity error on the L2 tag RAM read. */ + ALT_CACHE_L2_INTERRUPT_PARRT = 1 << 1, + + /*! Event counter overflow or increment. */ + ALT_CACHE_L2_INTERRUPT_ECNTR = 1 << 0 +}; +typedef enum ALT_CACHE_L2_INTERRUPT_e ALT_CACHE_L2_INTERRUPT_t; + +/*! + * Enables the L2 cache controller interrupts for the specified set of + * condition(s). + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_enable(uint32_t interrupt); + +/*! + * Disables the L2 cache controller interrupts for the specified set of + * condition(s). + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_disable(uint32_t interrupt); + +/*! + * Gets the condition(s) causing the L2 cache controller to interrupt as a + * register mask. + * + * \returns A register mask of the currently asserted and enabled + * conditions resulting in an interrupt being generated. + */ +uint32_t alt_cache_l2_int_status_get(void); + +/*! + * Clears the specified conditon(s) causing the L2 cache controller to + * interrupt as a mask. Condition(s) specified which are not causing an + * interrupt or condition(s) specified which are not enabled are ignored. + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_status_clear(uint32_t interrupt); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_CACHE_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h new file mode 100644 index 0000000..6be93fb --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h @@ -0,0 +1,1007 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_DMA_H__ +#define __ALT_DMA_H__ + +#include "hwlib.h" +#include "alt_dma_common.h" +#include "alt_dma_program.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_DMA DMA Controller API + * + * This module defines the API for configuration and use of the general purpose + * DMA controller for the SoC. The DMA controller is an instance of the ARM + * Corelink DMA Controller (DMA-330). + * + * References: + * * ARM DDI 0424C, CoreLink DMA Controller DMA-330 Technical Reference + * Manual. + * * ARM DAI 0239A, Application Note 239 Example Programs for the CoreLink + * DMA Controller DMA-330. + * * Altera, Cyclone V Device Handbook Volume 3: Hard Processor System + * Technical Reference Manual, DMA Controller. + * + * @{ + */ + +/*! + * \addtogroup ALT_DMA_COMPILE DMA API Compile Options + * + * This API provides control over the compile time inclusion of selected + * modules. This can allow for a smaller resulting binary. + * + * @{ + */ + +#ifndef ALT_DMA_PERIPH_PROVISION_16550_SUPPORT +#define ALT_DMA_PERIPH_PROVISION_16550_SUPPORT (1) +#endif + +#ifndef ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT +#define ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT (1) +#endif + +/*! + * @} + */ + +/*! + * \addtogroup ALT_DMA_CSR DMA API for Configuration, Control, and Status + * + * This API provides functions for configuration, control, and status queries + * of the DMA controller. + * + * @{ + */ + +/*! + * This type definition enumerates the operational states that the DMA manager + * may have. + */ +typedef enum ALT_DMA_MANAGER_STATE_e +{ + ALT_DMA_MANAGER_STATE_STOPPED = 0, /*!< Stopped */ + ALT_DMA_MANAGER_STATE_EXECUTING = 1, /*!< Executing */ + ALT_DMA_MANAGER_STATE_CACHE_MISS = 2, /*!< Cache Miss */ + ALT_DMA_MANAGER_STATE_UPDATING_PC = 3, /*!< Updating PC */ + ALT_DMA_MANAGER_STATE_WFE = 4, /*!< Waiting for Event */ + ALT_DMA_MANAGER_STATE_FAULTING = 15 /*!< Faulting */ +} +ALT_DMA_MANAGER_STATE_t; + +/*! + * This type definition enumerates the operational states that a DMA channel + * may have. + */ +typedef enum ALT_DMA_CHANNEL_STATE_e +{ + ALT_DMA_CHANNEL_STATE_STOPPED = 0, /*!< Stopped */ + ALT_DMA_CHANNEL_STATE_EXECUTING = 1, /*!< Executing */ + ALT_DMA_CHANNEL_STATE_CACHE_MISS = 2, /*!< Cache Miss */ + ALT_DMA_CHANNEL_STATE_UPDATING_PC = 3, /*!< Updating PC */ + ALT_DMA_CHANNEL_STATE_WFE = 4, /*!< Waiting for Event */ + ALT_DMA_CHANNEL_STATE_AT_BARRIER = 5, /*!< At Barrier */ + ALT_DMA_CHANNEL_STATE_WFP = 7, /*!< Waiting for Peripheral */ + ALT_DMA_CHANNEL_STATE_KILLING = 8, /*!< Killing */ + ALT_DMA_CHANNEL_STATE_COMPLETING = 9, /*!< Completing */ + ALT_DMA_CHANNEL_STATE_FAULTING_COMPLETING = 14, /*!< Faulting Completing */ + ALT_DMA_CHANNEL_STATE_FAULTING = 15 /*!< Faulting */ +} +ALT_DMA_CHANNEL_STATE_t; + +/*! + * This type definition enumerates the possible fault status that the DMA + * manager can have as a register mask. + */ +typedef enum ALT_DMA_MANAGER_FAULT_e +{ + /*! + * The DMA manager abort occured because of an instruction issued through + * the debug interface. + */ + ALT_DMA_MANAGER_FAULT_DBG_INSTR = (int32_t)(1UL << 30), + + /*! + * The DMA manager instruction fetch AXI bus response was not OKAY. + */ + ALT_DMA_MANAGER_FAULT_INSTR_FETCH_ERR = (int32_t)(1UL << 16), + + /*! + * The DMA manager attempted to execute DMAWFE or DMASEV with + * inappropriate security permissions. + */ + ALT_DMA_MANAGER_FAULT_MGR_EVNT_ERR = (int32_t)(1UL << 5), + + /*! + * The DMA manager attempted to execute DMAGO with inappropriate security + * permissions. + */ + ALT_DMA_MANAGER_FAULT_DMAGO_ERR = (int32_t)(1UL << 4), + + /*! + * The DMA manager attempted to execute an instruction operand that was + * not valid for the DMA configuration. + */ + ALT_DMA_MANAGER_FAULT_OPERAND_INVALID = (int32_t)(1UL << 1), + + /*! + * The DMA manager attempted to execute an undefined instruction. + */ + ALT_DMA_MANAGER_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0) +} +ALT_DMA_MANAGER_FAULT_t; + +/*! + * This type definition enumerates the possible fault status that a channel + * may have as a register mask. + */ +typedef enum ALT_DMA_CHANNEL_FAULT_e +{ + /*! + * The DMA channel has locked up due to resource starvation. + */ + ALT_DMA_CHANNEL_FAULT_LOCKUP_ERR = (int32_t)(1UL << 31), + + /*! + * The DMA channel abort occured because of an instruction issued through + * the debug interface. + */ + ALT_DMA_CHANNEL_FAULT_DBG_INSTR = (int32_t)(1UL << 30), + + /*! + * The DMA channel data read AXI bus reponse was not OKAY. + */ + ALT_DMA_CHANNEL_FAULT_DATA_READ_ERR = (int32_t)(1UL << 18), + + /*! + * The DMA channel data write AXI bus response was not OKAY. + */ + ALT_DMA_CHANNEL_FAULT_DATA_WRITE_ERR = (int32_t)(1UL << 17), + + /*! + * The DMA channel instruction fetch AXI bus response was not OKAY. + */ + ALT_DMA_CHANNEL_FAULT_INSTR_FETCH_ERR = (int32_t)(1UL << 16), + + /*! + * The DMA channel MFIFO did not have the data for the DMAST instruction. + */ + ALT_DMA_CHANNEL_FAULT_ST_DATA_UNAVAILABLE = (int32_t)(1UL << 13), + + /*! + * The DMA channel MFIFO is too small to hold the DMALD instruction data, + * or too small to servic the DMAST instruction request. + */ + ALT_DMA_CHANNEL_FAULT_MFIFO_ERR = (int32_t)(1UL << 12), + + /*! + * The DMA channel in non-secure state attempted to perform a secure read + * or write. + */ + ALT_DMA_CHANNEL_FAULT_CH_RDWR_ERR = (int32_t)(1UL << 7), + + /*! + * The DMA channel in non-secure state attempted to execute the DMAWFP, + * DMALDP, DMASTP, or DMAFLUSHP instruction involving a secure peripheral. + */ + ALT_DMA_CHANNEL_FAULT_CH_PERIPH_ERR = (int32_t)(1UL << 6), + + /*! + * The DMA channel in non-secure state attempted to execute the DMAWFE or + * DMASEV instruction for a secure event or secure interrupt (if + * applicable). + */ + ALT_DMA_CHANNEL_FAULT_CH_EVNT_ERR = (int32_t)(1UL << 5), + + /*! + * The DMA channel attempted to execute an instruction operand that was + * not valid for the DMA configuration. + */ + ALT_DMA_CHANNEL_FAULT_OPERAND_INVALID = (int32_t)(1UL << 1), + + /*! + * The DMA channel attempted to execute an undefined instruction. + */ + ALT_DMA_CHANNEL_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0) +} +ALT_DMA_CHANNEL_FAULT_t; + +/*! + * This type definition enumerates the possible DMA event-interrupt behavior + * option selections when a DMASEV instruction is executed. + */ +typedef enum ALT_DMA_EVENT_SELECT_e +{ + /*! + * If the DMA controller executes DMASEV for the event-interrupt resource + * then the DMA sends the event to all of the channel threads. + */ + ALT_DMA_EVENT_SELECT_SEND_EVT, + + /*! + * If the DMA controller executes DMASEV for the event-interrupt resource + * then the DMA sets the \b irq[N] HIGH. + */ + ALT_DMA_EVENT_SELECT_SIG_IRQ +} +ALT_DMA_EVENT_SELECT_t; + +/*! + * This type enumerates the DMA peripheral interface MUX selection options + * available. + */ +typedef enum ALT_DMA_PERIPH_MUX_e +{ + /*! + * Accept the reset default MUX selection + */ + ALT_DMA_PERIPH_MUX_DEFAULT = 0, + + /*! + * Select FPGA as the peripheral interface + */ + ALT_DMA_PERIPH_MUX_FPGA = 1, + + /*! + * Select CAN as the peripheral interface + */ + ALT_DMA_PERIPH_MUX_CAN = 2 +} +ALT_DMA_PERIPH_MUX_t; + +/*! + * This type defines the structure used to specify the configuration of the + * security states and peripheral interface MUX selections for the DMA + * controller. + */ +typedef struct ALT_DMA_CFG_s +{ + /*! + * DMA Manager security state configuration. + */ + ALT_DMA_SECURITY_t manager_sec; + + /*! + * DMA interrupt output security state configurations. Security state + * configurations are 0-based index-aligned with the enumeration values + * ALT_DMA_EVENT_0 through ALT_DMA_EVENT_7 of the ALT_DMA_EVENT_t type. + */ + ALT_DMA_SECURITY_t irq_sec[8]; + + /*! + * Peripheral request interface security state configurations. Security + * state configurations are 0-based index-aligned with the enumeration + * values of the ALT_DMA_PERIPH_t type. + */ + ALT_DMA_SECURITY_t periph_sec[32]; + + /*! + * DMA Peripheral Register Interface MUX Selections. MUX selections are + * 0-based index-aligned with the enumeration values + * ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 through + * ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 of the ALT_DMA_PERIPH_t type. + */ + ALT_DMA_PERIPH_MUX_t periph_mux[4]; +} +ALT_DMA_CFG_t; + +/*! + * Initialize the DMA controller. + * + * Initializes the DMA controller by setting the necessary control values to + * establish the security state and MUXed peripheral request interface selection + * configurations before taking the DMA controller out of reset. + * + * After the DMA is initialized, the following conditions hold true: + * * All DMA channel threads are in the Stopped state. + * * All DMA channel threads are available for allocation. + * * DMA Manager thread is waiting for an instruction from either APB + * interface. + * * The security state configurations of the DMA Manager, interrupt outputs, + * and peripheral request interfaces are established and immutable until the + * DMA is reset. + * * The MUXed peripheral request interface selection configurations are + * established and immutable until the DMA is reset. + * + * \param dma_cfg + * A pointer to a ALT_DMA_CFG_t structure containing the desired + * DMA controller security state and peripheral request interface + * MUX selections. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_init(const ALT_DMA_CFG_t * dma_cfg); + +/*! + * Uninitializes the DMA controller. + * + * Uninitializes the DMA controller by killing any running channel threads and + * putting the DMA controller into reset. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_uninit(void); + +/*! + * Allocate a DMA channel resource for use. + * + * \param channel + * A DMA controller channel. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_channel_alloc(ALT_DMA_CHANNEL_t channel); + +/*! + * Allocate a free DMA channel resource for use if there are any. + * + * \param allocated + * [out] A pointer to an output parameter that will contain the + * channel allocated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. An unallocated channel + * may not be available at the time of the API + * call. + */ +ALT_STATUS_CODE alt_dma_channel_alloc_any(ALT_DMA_CHANNEL_t * allocated); + +/*! + * Free a DMA channel resource for reuse. + * + * \param channel + * The DMA controller channel resource to free. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. The channel may not be in + * the STOPPED state. + */ +ALT_STATUS_CODE alt_dma_channel_free(ALT_DMA_CHANNEL_t channel); + +/*! + * Start execution of a DMA microcode program on the specified DMA channel + * thread resource. + * + * \param channel + * The DMA channel thread used to execute the microcode program. + * + * \param pgm + * The DMA microcode program. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_channel_exec(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * pgm); + +/*! + * Kill (abort) execution of any microcode program executing on the specified + * DMA channel thread resource. + * + * Terminates the channel thread of execution by issuing a DMAKILL instruction + * using the DMA APB slave interface. + * + * \param channel + * The DMA channel thread to abort any executing microcode program + * on. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO Timeout waiting for the channel to change into + * KILLING or STOPPED state. + */ +ALT_STATUS_CODE alt_dma_channel_kill(ALT_DMA_CHANNEL_t channel); + +/*! + * Returns the current register value for the given DMA channel. + * + * \param channel + * The DMA channel thread to abort any executing microcode program + * on. + * + * \param reg + * Register to get the value for. + * + * \param val + * [out] The current value of the requested register. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The specified channel or register is invalid. + */ +ALT_STATUS_CODE alt_dma_channel_reg_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_REG_t reg, uint32_t * val); + +/*! + * Signals the occurrence of an event or interrupt, using the specified event + * number. + * + * Causes the CPU to issue a DMASEV instruction using the DMA APB slave + * interface. + * + * The Interrupt Enable Register (INTEN) register is used to control if each + * event-interrupt resource is either an event or an interrupt. The INTEN + * register sets the event-interrupt resource to function as an: + * * Event - The DMAC generates an event for the specified event-interrupt + * resource. When the DMAC executes a DMAWFE instruction for the + * same event-interrupt resource then it clears the event. + * * Interrupt - The DMAC sets the \b IRQ[N] signal high, where + * \e evt_num is the number of the specified event + * resource. The interrupt must be cleared after being handled. + * + * When the configured to generate an event, this function may be used to + * restart one or more waiting DMA channels (i.e. having executed a DMAWFE + * instruction). + * + * See the following sections from the \e ARM DDI 0424C, CoreLink DMA Controller + * DMA-330 Technical Reference Manual for implementation details and use cases: + * * 2.5.1, Issuing Instructions to the DMAC using a Slave Interface + * * 2.7, Using Events and Interrupts + * + * \param evt_num + * A DMA event-interrupt resource. Allowable event values may be + * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 but ALT_DMA_EVENT_ABORT is + * not. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given event number is invalid. + */ +ALT_STATUS_CODE alt_dma_send_event(ALT_DMA_EVENT_t evt_num); + +/*! + * Returns the current operational state of the DMA manager thread. + * + * \param state + * [out] Pointer to an output parameter to contain the DMA + * channel thread state. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_manager_state_get(ALT_DMA_MANAGER_STATE_t * state); + +/*! + * Returns the current operational state of the specified DMA channel thread. + * + * \param channel + * The DMA channel thread to return the operational state of. + * + * \param state + * [out] Pointer to an output parameter to contain the DMA + * channel thread state. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_channel_state_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_CHANNEL_STATE_t * state); + +/*! + * Return the current fault status of the DMA manager thread. + * + * \param fault + * [out] Pointer to an output parameter to contain the DMA + * manager fault status. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_manager_fault_status_get(ALT_DMA_MANAGER_FAULT_t * fault); + +/*! + * Return the current fault status of the specified DMA channel thread. + * + * \param channel + * The DMA channel thread to return the fault status of. + * + * \param fault + * [out] Pointer to an output parameter to contain the DMA + * channel fault status. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_channel_fault_status_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_CHANNEL_FAULT_t * fault); + +/*! + * Select whether the DMA controller sends the specific event to all channel + * threads or signals an interrupt using the corressponding \b irq when a DMASEV + * instruction is executed for the specified event-interrupt resource number. + * + * \param evt_num + * The event-interrupt resource number. Valid values are + * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. + * + * \param opt + * The desired behavior selection for \e evt_num when a DMASEV is + * executed. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given selection identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_event_int_select(ALT_DMA_EVENT_t evt_num, + ALT_DMA_EVENT_SELECT_t opt); + +/*! + * Returns the status of the specified event-interrupt resource. + * + * Returns ALT_E_TRUE if event is active or \b irq[N] is HIGH and returns + * ALT_E_FALSE if event is inactive or \b irq[N] is LOW. + * + * \param evt_num + * The event-interrupt resource number. Valid values are + * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. + * + * \retval ALT_E_TRUE Event is active or \b irq[N] is HIGH. + * \retval ALT_E_FALSE Event is inactive or \b irq[N] is LOW. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given event identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_event_int_status_get_raw(ALT_DMA_EVENT_t evt_num); + +/*! + * Returns the status of the specified interrupt resource. + * + * Returns ALT_E_TRUE if interrupt is active and therfore \b irq[N] is HIGH and + * returns ALT_E_FALSE if interrupt is inactive and therfore \b irq[N] is LOW. + * + * \param irq_num + * The interrupt resource number. Valid values are + * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. + * + * \retval ALT_E_TRUE Event is active or \b irq[N] is HIGH. + * \retval ALT_E_FALSE Event is inactive or \b irq[N] is LOW. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given event identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_int_status_get(ALT_DMA_EVENT_t irq_num); + +/*! + * Clear the active (HIGH) status of the specified interrupt resource. + * + * If the specified interrupt is HIGH, then sets \b irq[N] to LOW if the + * event-interrupt resource is configured (see: alt_dma_event_int_enable()) + * to signal an interrupt. Otherwise, the status of \b irq[N] does not change. + * + * \param irq_num + * The interrupt resource number. Valid values are + * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given event identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_int_clear(ALT_DMA_EVENT_t irq_num); + +/*! + * @} + */ + +/*! + * \addtogroup ALT_DMA_STD_OPS DMA API for Standard Operations + * + * The functions in this group provide common DMA operations for common bulk + * data transfers between: + * * Memory to Memory + * * Zero to Memory + * * Memory to Peripheral + * * Peripheral to Memory + * + * All DMA operations are asynchronous. The following are the ways to receive + * notification of a DMA transfer complete operation: + * * Use alt_dma_channel_state_get() and poll for the + * ALT_DMA_CHANNEL_STATE_STOPPED status. + * * In conjunction with the interrupt API, use DMA events to signal an + * interrupt. The event first must be configured to signal an interrupt + * using alt_dma_event_int_select(). Configure the DMA program to send an + * event. + * * Construct a custom program which waits for a particular event number by + * assemblying a DMAWFE using alt_dma_program_DMAWFE(). Then run the custom + * program on a different channel. The custom program will wait until the + * DMA program sends the event. Configure the DMA program to send an event. + * + * Cache related maintenance on the source and/or destinatino buffer are not + * handled the DMA API and are the responsibility of the programmer. This is + * because the DMA API does not have visibility into the current configuration + * of the MMU or know about any special considerations regarding the source + * and/or destination memory. The following are some example scenarios and + * cache maintenance related precautions that may need to be taken: + * * alt_dma_memory_to_memory(): Source buffer should be cleaned or purged, + * destination buffer should be invalidated. + * * alt_dma_zero_to_memory(): Destination buffer should be invalidated. + * * alt_dma_memory_to_register(): Source buffer should be cleaned or purged. + * * alt_dma_register_to_memory(): Destination buffer should be invalidated. + * * alt_dma_memory_to_periph(): Source buffer should be cleaned or purged. + * * alt_dma_periph_to_memory(): Destination buffer should be invalidated. + * + * @{ + */ + +/*! + * Uses the DMA engine to asynchronously copy the specified memory from the + * given source address to the given destination address. + * + * Overlapping memory regions are not supported. + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param dest + * The destination memory address to copy to. + * + * \param src + * The source memory address to copy from. + * + * \param size + * The size of the transfer in bytes. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel or event identifier (if + * used) is invalid, or the memory regions + * specified are overlapping. + */ +ALT_STATUS_CODE alt_dma_memory_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dest, + const void * src, + size_t size, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * Uses the DMA engine to asynchronously zero out the specified memory buffer. + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param buf + * The buffer memory address to zero out. + * + * \param size + * The size of the buffer in bytes. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel or event identifier (if + * used) is invalid. + */ +ALT_STATUS_CODE alt_dma_zero_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * buf, + size_t size, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * Uses the DMA engine to asynchronously transfer the contents of a memory + * buffer to a keyhole register. + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param dst_reg + * The address of the register to write buffer to. + * + * \param src_buf + * The address of the memory buffer for the data. + * + * \param count + * The number of transfers to make. + * + * \param register_width_bits + * The width of the register to transfer to in bits. Valid values + * are 8, 16, 32, and 64. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel, event identifier (if used), + * or register width are invalid, or if the + * destination register or source buffer is + * unaligned to the register width. + */ +ALT_STATUS_CODE alt_dma_memory_to_register(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst_reg, + const void * src_buf, + size_t count, + uint32_t register_width_bits, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * Uses the DMA engine to asynchronously transfer the contents of a keyhole + * register to a memory buffer. + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param dst_buf + * The address of the memory buffer to copy to. + * + * \param src_reg + * The address of the keyhole register to read from. + * + * \param count + * The number of transfers to make. + * + * \param register_width_bits + * The width of the register to transfer to in bits. Valid values + * are 8, 16, 32, and 64. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel, event identifier (if used), + * or register width are invalid, or if the + * destination buffer or source register is + * unaligned to the register width. + */ +ALT_STATUS_CODE alt_dma_register_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst_buf, + const void * src_reg, + size_t count, + uint32_t register_width_bits, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * Uses the DMA engine to asynchronously copy memory from the given source + * address to the specified peripheral. Because different peripheral has + * different characteristics, individual peripherals need to be explicitly + * supported. + * + * The following lists the peripheral IDs supported by this API: + * * ALT_DMA_PERIPH_QSPI_FLASH_TX + * * ALT_DMA_PERIPH_UART0_TX + * * ALT_DMA_PERIPH_UART1_TX + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param dest + * The destination peripheral to copy memory to. + * + * \param src + * The source memory address to copy from. + * + * \param size + * The size of the transfer in bytes. + * + * \param periph_info + * A pointer to a peripheral specific data structure. The + * following list shows what data structure should be used for + * peripherals: + * * ALT_DMA_PERIPH_QSPI_FLASH_TX: This parameter is ignored. + * * ALT_DMA_PERIPH_UART0_TX: Use a pointer to the + * ALT_16550_HANDLE_t used to interact with that UART. + * * ALT_DMA_PERIPH_UART1_TX: Use a pointer to the + * ALT_16550_HANDLE_t used to interact with that UART. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel, peripheral, or event + * identifier (if used) is invalid. + * + * \internal + * Priority peripheral IDs to be supported: + * * ALT_DMA_PERIPH_FPGA_0 + * * ALT_DMA_PERIPH_FPGA_1 + * * ALT_DMA_PERIPH_FPGA_2 + * * ALT_DMA_PERIPH_FPGA_3 + * * ALT_DMA_PERIPH_FPGA_4 + * * ALT_DMA_PERIPH_FPGA_5 + * * ALT_DMA_PERIPH_FPGA_6 + * * ALT_DMA_PERIPH_FPGA_7 + * * ALT_DMA_PERIPH_I2C0_TX + * * ALT_DMA_PERIPH_I2C1_TX + * * ALT_DMA_PERIPH_I2C2_TX + * * ALT_DMA_PERIPH_I2C3_TX + * * ALT_DMA_PERIPH_SPI0_MASTER_TX + * * ALT_DMA_PERIPH_SPI0_SLAVE_TX + * * ALT_DMA_PERIPH_SPI1_MASTER_TX + * * ALT_DMA_PERIPH_SPI1_SLAVE_TX + * \endinternal + */ +ALT_STATUS_CODE alt_dma_memory_to_periph(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t dest, + const void * src, + size_t size, + void * periph_info, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * Uses the DMA engine to copy memory from the specified peripheral to the + * given destination address. Because different peripheral has different + * characteristics, individual peripherals need to be explicitly supported. + * + * The following lists the peripheral IDs supported by this API: + * * ALT_DMA_PERIPH_QSPI_FLASH_RX + * * ALT_DMA_PERIPH_UART0_RX + * * ALT_DMA_PERIPH_UART1_RX + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param dest + * The destination memory address to copy to. + * + * \param src + * The source peripheral to copy memory from. + * + * \param size + * The size of the transfer in bytes. + * + * \param periph_info + * A pointer to a peripheral specific data structure. The + * following list shows what data structure should be used for + * peripherals: + * * ALT_DMA_PERIPH_QSPI_FLASH_RX: This parameter is ignored. + * * ALT_DMA_PERIPH_UART0_RX: Use a pointer to the + * ALT_16550_HANDLE_t used to interact with that UART. + * * ALT_DMA_PERIPH_UART1_RX: Use a pointer to the + * ALT_16550_HANDLE_t used to interact with that UART. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel, peripheral, or event + * identifier (if used) is invalid. +* + * \internal + * Priority peripheral IDs to be supported: + * * ALT_DMA_PERIPH_FPGA_0 + * * ALT_DMA_PERIPH_FPGA_1 + * * ALT_DMA_PERIPH_FPGA_2 + * * ALT_DMA_PERIPH_FPGA_3 + * * ALT_DMA_PERIPH_FPGA_4 + * * ALT_DMA_PERIPH_FPGA_5 + * * ALT_DMA_PERIPH_FPGA_6 + * * ALT_DMA_PERIPH_FPGA_7 + * * ALT_DMA_PERIPH_I2C0_RX + * * ALT_DMA_PERIPH_I2C1_RX + * * ALT_DMA_PERIPH_I2C2_RX + * * ALT_DMA_PERIPH_I2C3_RX + * * ALT_DMA_PERIPH_SPI0_MASTER_RX + * * ALT_DMA_PERIPH_SPI0_SLAVE_RX + * * ALT_DMA_PERIPH_SPI1_MASTER_RX + * * ALT_DMA_PERIPH_SPI1_SLAVE_RX + * \endinternal + */ +ALT_STATUS_CODE alt_dma_periph_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dest, + ALT_DMA_PERIPH_t src, + size_t size, + void * periph_info, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h new file mode 100644 index 0000000..e82bc1a --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h @@ -0,0 +1,162 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_DMA_COMMON_H__ +#define __ALT_DMA_COMMON_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions + * + * This module contains the common definitions for the DMA controller related + * APIs. + * + * @{ + */ + +/*! + * This type definition enumerates the DMA controller channel threads. + */ +typedef enum ALT_DMA_CHANNEL_e +{ + ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */ + ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */ + ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */ + ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */ + ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */ + ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */ + ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */ + ALT_DMA_CHANNEL_7 = 7 /*!< DMA Channel Thread 7 */ +} +ALT_DMA_CHANNEL_t; + +/*! + * This type definition enumerates the SoC system peripherals implementing the + * required request interface that enables direct DMA transfers to/from the + * device. + * + * FPGA soft IP interface to the DMA are required to comply with the Synopsys + * protocol. + * + * Request interface numbers 4 through 7 are multiplexed between the CAN + * controllers and soft logic implemented in the FPGA fabric. The selection + * between the CAN controller and FPGA interfaces is determined at DMA + * initialization. + */ +typedef enum ALT_DMA_PERIPH_e +{ + ALT_DMA_PERIPH_FPGA_0 = 0, /*!< FPGA soft IP interface 0 */ + ALT_DMA_PERIPH_FPGA_1 = 1, /*!< FPGA soft IP interface 1 */ + ALT_DMA_PERIPH_FPGA_2 = 2, /*!< FPGA soft IP interface 2 */ + ALT_DMA_PERIPH_FPGA_3 = 3, /*!< FPGA soft IP interface 3 */ + + ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4, /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */ + ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5, /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */ + ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6, /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */ + ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7, /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */ + + ALT_DMA_PERIPH_FPGA_4 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */ + ALT_DMA_PERIPH_FPGA_5 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */ + ALT_DMA_PERIPH_FPGA_6 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */ + ALT_DMA_PERIPH_FPGA_7 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */ + + ALT_DMA_PERIPH_CAN0_IF1 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */ + ALT_DMA_PERIPH_CAN0_IF2 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */ + ALT_DMA_PERIPH_CAN1_IF1 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */ + ALT_DMA_PERIPH_CAN1_IF2 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */ + + ALT_DMA_PERIPH_I2C0_TX = 8, /*!< I2C 0 TX */ + ALT_DMA_PERIPH_I2C0_RX = 9, /*!< I2C 0 RX */ + ALT_DMA_PERIPH_I2C1_TX = 10, /*!< I2C 1 TX */ + ALT_DMA_PERIPH_I2C1_RX = 11, /*!< I2C 1 RX */ + ALT_DMA_PERIPH_I2C2_TX = 12, /*!< I2C 2 TX */ + ALT_DMA_PERIPH_I2C2_RX = 13, /*!< I2C 2 RX */ + ALT_DMA_PERIPH_I2C3_TX = 14, /*!< I2C 3 TX */ + ALT_DMA_PERIPH_I2C3_RX = 15, /*!< I2C 3 RX */ + ALT_DMA_PERIPH_SPI0_MASTER_TX = 16, /*!< SPI 0 Master TX */ + ALT_DMA_PERIPH_SPI0_MASTER_RX = 17, /*!< SPI 0 Master RX */ + ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18, /*!< SPI 0 Slave TX */ + ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19, /*!< SPI 0 Slave RX */ + ALT_DMA_PERIPH_SPI1_MASTER_TX = 20, /*!< SPI 1 Master TX */ + ALT_DMA_PERIPH_SPI1_MASTER_RX = 21, /*!< SPI 1 Master RX */ + ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22, /*!< SPI 1 Slave TX */ + ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23, /*!< SPI 1 Slave RX */ + ALT_DMA_PERIPH_QSPI_FLASH_TX = 24, /*!< QSPI Flash TX */ + ALT_DMA_PERIPH_QSPI_FLASH_RX = 25, /*!< QSPI Flash RX */ + ALT_DMA_PERIPH_STM = 26, /*!< System Trace Macrocell */ + ALT_DMA_PERIPH_RESERVED = 27, /*!< Reserved */ + ALT_DMA_PERIPH_UART0_TX = 28, /*!< UART 0 TX */ + ALT_DMA_PERIPH_UART0_RX = 29, /*!< UART 0 RX */ + ALT_DMA_PERIPH_UART1_TX = 30, /*!< UART 1 TX */ + ALT_DMA_PERIPH_UART1_RX = 31 /*!< UART 1 RX */ +} +ALT_DMA_PERIPH_t; + +/*! + * This type enumerates the DMA security state options available. + */ +typedef enum ALT_DMA_SECURITY_e +{ + ALT_DMA_SECURITY_DEFAULT = 0, /*!< Use the default security value (e.g. reset default) */ + ALT_DMA_SECURITY_SECURE = 1, /*!< Secure */ + ALT_DMA_SECURITY_NONSECURE = 2 /*!< Non-secure */ +} +ALT_DMA_SECURITY_t; + +/*! + * This type definition enumerates the DMA event-interrupt resources. + */ +typedef enum ALT_DMA_EVENT_e +{ + ALT_DMA_EVENT_0 = 0, /*!< DMA Event 0 */ + ALT_DMA_EVENT_1 = 1, /*!< DMA Event 1 */ + ALT_DMA_EVENT_2 = 2, /*!< DMA Event 2 */ + ALT_DMA_EVENT_3 = 3, /*!< DMA Event 3 */ + ALT_DMA_EVENT_4 = 4, /*!< DMA Event 4 */ + ALT_DMA_EVENT_5 = 5, /*!< DMA Event 5 */ + ALT_DMA_EVENT_6 = 6, /*!< DMA Event 6 */ + ALT_DMA_EVENT_7 = 7, /*!< DMA Event 7 */ + ALT_DMA_EVENT_ABORT = 8 /*!< DMA Abort Event */ +} +ALT_DMA_EVENT_t; + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_COMMON_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h new file mode 100644 index 0000000..5fa876f --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h @@ -0,0 +1,951 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_DMA_PROGRAM_H__ +#define __ALT_DMA_PROGRAM_H__ + +#include "hwlib.h" +#include "alt_dma_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_DMA_PRG DMA Controller Programming API + * + * This API provides functions for dynamically defining and assembling microcode + * programs for execution on the DMA controller. + * + * The microcode program assembly API provides users with the ability to develop + * highly optimized and tailored algorithms for data transfer between SoC FPGA + * IP blocks and/or system memory. + * + * The same microcode program assembly facilities are also used to implement the + * functions found in the HWLIB Common DMA Operations functional API. + * + * An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA + * microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated + * from used specified system memory. Once a microcode program has been + * assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA + * channel thread. The microcode program may be rerun on any DMA channel thread + * whenever required as long as the integrity of the ALT_DMA_PROGRAM_t + * containing the program is maintained. + * + * @{ + */ + +/*! + * This preprocessor declares the DMA channel thread microcode instruction + * cache line width in bytes. It is recommended that the program buffers be + * sized to a multiple of the cache line size. This will allow for the most + * efficient microcode speed and space utilization. + */ +#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32) + +/*! + * This preprocessor declares the DMA channel thread microcode instruction + * cache line count. Thus the total size of the cache is the cache line size + * multipled by the cache line count. Programs larger than the cache size risk + * having a cache miss while executing. + */ +#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16) + +/*! + * This preprocessor definition determines the size of the program buffer + * within the ALT_DMA_PROGRAM_t structure. This size should provide adequate + * size for most DMA microcode programs. If calls within this API are + * reporting out of memory response codes, consider increasing the provisioned + * program buffersize. + * + * To specify another DMA microcode program buffer size, redefine the macro + * below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in + * your Makefile. It is recommended that the size be a multiple of the + * microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for + * more information. The largest supported buffer size is 65536 bytes. + */ +#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE +#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT) +#endif + +/*! + * This type defines the structure used to assemble and contain a microcode + * program which can be executed by the DMA controller. The internal members + * are undocumented and should not be altered outside of this API. + */ +typedef struct ALT_DMA_PROGRAM_s +{ + uint32_t flag; + + uint16_t buffer_start; + uint16_t code_size; + + uint16_t loop0; + uint16_t loop1; + + uint16_t sar; + uint16_t dar; + + /* + * Add a little extra space so that regardless of where this structure + * sits in memory, a suitable start address can be aligned to the cache + * line stride while providing the requested buffer space. + */ + uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE + + ALT_DMA_PROGRAM_CACHE_LINE_SIZE]; +} +ALT_DMA_PROGRAM_t; + +/*! + * This type definition enumerates the DMA controller register names for use in + * microcode program definition. + */ +typedef enum ALT_DMA_PROGRAM_REG_e +{ + /*! Source Address Register */ + ALT_DMA_PROGRAM_REG_SAR = 0x0, + + /*! Destination Address Register */ + ALT_DMA_PROGRAM_REG_DAR = 0x2, + + /*! Channel Control Register */ + ALT_DMA_PROGRAM_REG_CCR = 0x1 +} +ALT_DMA_PROGRAM_REG_t; + +/*! + * This type definition enumerates the instruction modifier options available + * for use with selected DMA microcode instructions. + * + * The enumerations values are context dependent upon the instruction being + * modified. + * + * For the DMALD[S|B], DMALDP\, DMAST[S|B], and + * DMASTP\ microcode instructions, the enumeration + * ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the S option modifier + * while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the B + * option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies + * that no modifier is present for instructions where use of [S|B] is + * optional. + * + * For the DMAWFP microcode instruction, the enumerations + * ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or + * ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding + * options \. + */ +typedef enum ALT_DMA_PROGRAM_INST_MOD_e +{ + /*! + * This DMA instruction modifier specifies that no special modifier is + * added to the instruction. + */ + ALT_DMA_PROGRAM_INST_MOD_NONE, + + /*! + * Depending on the DMA microcode instruction modified, this modifier + * specifies S case for a [S|B] or a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_SINGLE, + + /*! + * Depending on the DMA microcode instruction modified, this modifier + * specifies B case for a [S|B] or a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_BURST, + + /*! + * This DMA instruction modifier specifies a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_PERIPH +} +ALT_DMA_PROGRAM_INST_MOD_t; + +/*! + * This function initializes a system memory buffer for use as a DMA microcode + * program buffer. This should be the first API call made on the program + * buffer type. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function verifies that the DMA microcode program buffer is no longer + * in use and performs any needed uninitialization steps. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function clears the existing DMA microcode program in the given + * program buffer. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function validate that the given DMA microcode program buffer contains + * a well formed program. If caches are enabled, the program buffer contents + * will be cleaned to RAM. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The given program is well formed. + * \retval ALT_E_ERROR The given program is not well formed. + * \retval ALT_E_TMO The cache operation timed out. + */ +ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function reports the number bytes incremented for the register + * specified. The purpose is to determine the progress of an ongoing DMA + * transfer. + * + * It is implemented by calculating the difference of the programmed SAR or DAR + * with the current channel SAR or DAR register value. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \param channel + * The channel that the program is running on. + * + * \param reg + * Register to change the value for. Valid for only + * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. + * + * \param current + * The current snapshot value of the register read from the DMA + * channel. + * + * \param progress + * [out] A pointer to a memory location that will be used to store + * the number of bytes transfered. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + * \retval ALT_E_BAD_ARG The specified channel is invalid, the specified + * register is invalid, or the DMAMOV for the + * specified register has not yet been assembled + * in the current program buffer. + */ +ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, + uint32_t current, uint32_t * progress); + +/*! + * This function updates a pre-existing DMAMOV value affecting the SAR or DAR + * registers. This allows for pre-assembled programs that can be used on + * different source and destination addresses. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \param reg + * Register to change the value for. Valid for only + * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. + * + * \param val + * The value to update to. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + * \retval ALT_E_BAD_ARG The specified register is invalid or the DMAMOV + * for the specified register has not yet been + * assembled in the current program buffer. + */ +ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, uint32_t val); + +/*! + */ + +/*! + * Assembles a DMAADDH (Add Halfword) instruction into the microcode program + * buffer. This instruction uses 3 bytes of buffer space. + * + * \param pgm + * The DMA program buffer to contain the assembled instruction. + * + * \param addr_reg + * The channel address register (ALT_DMA_PROGRAM_REG_DAR or + * ALT_DMA_PROGRAM_REG_SAR) to add the value to. + * + * \param val + * The 16-bit unsigned value to add to the channel address + * register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAADDH , <16-bit immediate> +ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); + +/*! + * Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode + * program buffer. This instruction uses 3 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param addr_reg + * The channel address register (ALT_DMA_PROGRAM_REG_DAR or + * ALT_DMA_PROGRAM_REG_SAR) to add the value to. + * + * \param val + * The 16-bit unsigned value to add to the channel address + * register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAADNH , <16-bit immediate> +ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); + +/*! + * Assembles a DMAEND (End) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAEND +ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode + * program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param periph + * The peripheral to flush. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid peripheral specified. + */ +// Assembler Syntax: DMAFLUSHP +ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMAGO (Go) instruction into the microcode program buffer. This + * instruction uses 6 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param channel + * The stopped channel to act upon. + * + * \param val + * The value to write to the channel program counter register. + * + * \param sec + * The security state for the operation. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel or security specified. + */ +// Assembler Syntax: DMAGO , <32-bit_immediate> [, ns] +ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_CHANNEL_t channel, uint32_t val, + ALT_DMA_SECURITY_t sec); + +/*! + * Assembles a DMAKILL (Kill) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAKILL +ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMALD (Load) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. + */ +// Assembler Syntax: DMALD[S|B] +ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMALDP (Load and notify Peripheral) instruction into the + * microcode program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \param periph + * The peripheral to notify. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral + * specified. + */ +// Assembler Syntax: DMALDP +ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMALP (Loop) instruction into the microcode program buffer. + * This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param iterations + * The number of iterations to run for. Valid values are 1 - 256. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid iterations specified. + * \retval ALT_E_BAD_OPERATION All loop registers are in use. + */ +// Assembler Syntax: DMALP [|] +ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm, + uint32_t iterations); + +/*! + * Assembles a DMALPEND (Loop End) instruction into the microcode program + * buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the loop terminator. Only + * ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE + * and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. + * \retval ALT_E_ARG_RANGE Loop size is too large to be supported. + * \retval ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to + * the program buffer before adding this + * DMALPEND instruction. + */ +// Assembler Syntax: DMALPEND[S|B] +ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMALPFE (Loop Forever) instruction into the microcode program + * buffer. No instruction is added to the buffer but a previous DMALPEND to + * create an infinite loop. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMALPFE +ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAMOV (Move) instruction into the microcode program buffer. + * This instruction uses 6 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param chan_reg + * The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR, + * ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy + * the value to. + * + * \param val + * The value to write to the specified register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAMOV , <32-bit_immediate> +ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val); + +/*! + * Assembles a DMANOP (No Operation) instruction into the microcode program + * buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMANOP +ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMARMB (Read Memory Barrier) instruction into the microcode + * program buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMARMB +ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMASEV (Send Event) instruction into the microcode program + * buffer. This instruction uses 2 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param evt + * The event to send. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid event specified. + */ +// Assembler Syntax: DMASEV +ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt); + +/*! + * Assembles a DMAST (Store) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAST[S|B] +ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMASTP (Store and notify Peripheral) instruction into the + * microcode program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \param periph + * The peripheral to notify. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral + * specified. + */ +// Assembler Syntax: DMASTP +ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMASTZ (Store Zero) instruction into the microcode program + * buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMASTZ +ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAWFE (Wait For Event) instruction into the microcode program + * buffer. This instruction uses 2 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param evt + * The event to wait for. + * + * \param invalid + * If invalid is set to true, the instruction will be configured + * to invalidate the instruction cache for the current DMA + * thread. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid event specified. + */ +// Assembler Syntax: DMAWFE [, invalid] +ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt, bool invalid); + +/*! + * Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode + * program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param periph + * The peripheral to wait on. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE, + * ALT_DMA_PROGRAM_INST_MOD_BURST, or + * ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid peripheral or instruction modifier + * specified. + */ +// Assembler Syntax: DMAWFP , +ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode + * program buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAWMB +ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm); + +/*! + * \addtogroup DMA_CCR Support for DMAMOV CCR + * + * The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the + * dynamic microcode programming of the assembler directive: +\verbatim + +DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA] + [SP] [SC] + [DB<1-16>] [DS<8|16|32|64|128>] [DA] + [DP] [DC] + [ES<8|16|32|64|128>] + +\endverbatim +* with a DMAMOV instruction (see: alt_dma_program_DMAMOV()). +* +* For example the assembler directive: +\verbatim +DMAMOV CCR SB1 SS32 DB1 DS32 +\endverbatim +* would be dynamically programmed with the following API call: +\verbatim +alt_dma_program_DMAMOV( pgm, + ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES8 + ) + ); +\endverbatim +* +* Each CCR option category should be specified regardless of whether it +* specifies a custom value or the normal default value (i.e. an +* ALT_DMA_CCR_OPT_*_DEFAULT. +* +* @{ +*/ + +/* + * Source Address {Fixed,Incrementing} + */ +/*! Source Address Fixed address burst. */ +#define ALT_DMA_CCR_OPT_SAF (0 << 0) +/*! Source Address Incrementing address burst. */ +#define ALT_DMA_CCR_OPT_SAI (1 << 0) +/*! Source Address Default value. */ +#define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI + +/* + * Source burst Size (in bits) + */ +/*! Source burst Size of 8 bits. */ +#define ALT_DMA_CCR_OPT_SS8 (0 << 1) +/*! Source burst Size of 16 bits. */ +#define ALT_DMA_CCR_OPT_SS16 (1 << 1) +/*! Source burst Size of 32 bits. */ +#define ALT_DMA_CCR_OPT_SS32 (2 << 1) +/*! Source burst Size of 64 bits. */ +#define ALT_DMA_CCR_OPT_SS64 (3 << 1) +/*! Source burst Size of 128 bits. */ +#define ALT_DMA_CCR_OPT_SS128 (4 << 1) +/*! Source burst Size default bits. */ +#define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8 + +/* + * Source burst Length (in transfer(s)) + */ +/*! Source Burst length of 1 transfer. */ +#define ALT_DMA_CCR_OPT_SB1 (0x0 << 4) +/*! Source Burst length of 2 transfers. */ +#define ALT_DMA_CCR_OPT_SB2 (0x1 << 4) +/*! Source Burst length of 3 transfers. */ +#define ALT_DMA_CCR_OPT_SB3 (0x2 << 4) +/*! Source Burst length of 4 transfers. */ +#define ALT_DMA_CCR_OPT_SB4 (0x3 << 4) +/*! Source Burst length of 5 transfers. */ +#define ALT_DMA_CCR_OPT_SB5 (0x4 << 4) +/*! Source Burst length of 6 transfers. */ +#define ALT_DMA_CCR_OPT_SB6 (0x5 << 4) +/*! Source Burst length of 7 transfers. */ +#define ALT_DMA_CCR_OPT_SB7 (0x6 << 4) +/*! Source Burst length of 8 transfers. */ +#define ALT_DMA_CCR_OPT_SB8 (0x7 << 4) +/*! Source Burst length of 9 transfers. */ +#define ALT_DMA_CCR_OPT_SB9 (0x8 << 4) +/*! Source Burst length of 10 transfers. */ +#define ALT_DMA_CCR_OPT_SB10 (0x9 << 4) +/*! Source Burst length of 11 transfers. */ +#define ALT_DMA_CCR_OPT_SB11 (0xa << 4) +/*! Source Burst length of 12 transfers. */ +#define ALT_DMA_CCR_OPT_SB12 (0xb << 4) +/*! Source Burst length of 13 transfers. */ +#define ALT_DMA_CCR_OPT_SB13 (0xc << 4) +/*! Source Burst length of 14 transfers. */ +#define ALT_DMA_CCR_OPT_SB14 (0xd << 4) +/*! Source Burst length of 15 transfers. */ +#define ALT_DMA_CCR_OPT_SB15 (0xe << 4) +/*! Source Burst length of 16 transfers. */ +#define ALT_DMA_CCR_OPT_SB16 (0xf << 4) +/*! Source Burst length default transfers. */ +#define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1 + +/* + * Source Protection + */ +/*! Source Protection bits for AXI bus ARPROT[2:0]. */ +#define ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8) +/*! Source Protection bits default value. */ +#define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0) + +/* + * Source cache + */ +/*! Source Cache bits for AXI bus ARCACHE[2:0]. */ +#define ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11) +/*! Source Cache bits default value. */ +#define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0) + +/* + * Destination Address {Fixed,Incrementing} + */ +/*! Destination Address Fixed address burst. */ +#define ALT_DMA_CCR_OPT_DAF (0 << 14) +/*! Destination Address Incrementing address burst. */ +#define ALT_DMA_CCR_OPT_DAI (1 << 14) +/*! Destination Address Default value. */ +#define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI + +/* + * Destination burst Size (in bits) + */ +/*! Destination burst Size of 8 bits. */ +#define ALT_DMA_CCR_OPT_DS8 (0 << 15) +/*! Destination burst Size of 16 bits. */ +#define ALT_DMA_CCR_OPT_DS16 (1 << 15) +/*! Destination burst Size of 32 bits. */ +#define ALT_DMA_CCR_OPT_DS32 (2 << 15) +/*! Destination burst Size of 64 bits. */ +#define ALT_DMA_CCR_OPT_DS64 (3 << 15) +/*! Destination burst Size of 128 bits. */ +#define ALT_DMA_CCR_OPT_DS128 (4 << 15) +/*! Destination burst Size default bits. */ +#define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8 + +/* + * Destination Burst length (in transfer(s)) + */ +/*! Destination Burst length of 1 transfer. */ +#define ALT_DMA_CCR_OPT_DB1 (0x0 << 18) +/*! Destination Burst length of 2 transfers. */ +#define ALT_DMA_CCR_OPT_DB2 (0x1 << 18) +/*! Destination Burst length of 3 transfers. */ +#define ALT_DMA_CCR_OPT_DB3 (0x2 << 18) +/*! Destination Burst length of 4 transfers. */ +#define ALT_DMA_CCR_OPT_DB4 (0x3 << 18) +/*! Destination Burst length of 5 transfers. */ +#define ALT_DMA_CCR_OPT_DB5 (0x4 << 18) +/*! Destination Burst length of 6 transfers. */ +#define ALT_DMA_CCR_OPT_DB6 (0x5 << 18) +/*! Destination Burst length of 7 transfers. */ +#define ALT_DMA_CCR_OPT_DB7 (0x6 << 18) +/*! Destination Burst length of 8 transfers. */ +#define ALT_DMA_CCR_OPT_DB8 (0x7 << 18) +/*! Destination Burst length of 9 transfers. */ +#define ALT_DMA_CCR_OPT_DB9 (0x8 << 18) +/*! Destination Burst length of 10 transfers. */ +#define ALT_DMA_CCR_OPT_DB10 (0x9 << 18) +/*! Destination Burst length of 11 transfers. */ +#define ALT_DMA_CCR_OPT_DB11 (0xa << 18) +/*! Destination Burst length of 12 transfers. */ +#define ALT_DMA_CCR_OPT_DB12 (0xb << 18) +/*! Destination Burst length of 13 transfers. */ +#define ALT_DMA_CCR_OPT_DB13 (0xc << 18) +/*! Destination Burst length of 14 transfers. */ +#define ALT_DMA_CCR_OPT_DB14 (0xd << 18) +/*! Destination Burst length of 15 transfers. */ +#define ALT_DMA_CCR_OPT_DB15 (0xe << 18) +/*! Destination Burst length of 16 transfers. */ +#define ALT_DMA_CCR_OPT_DB16 (0xf << 18) +/*! Destination Burst length default transfers. */ +#define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1 + +/* + * Destination Protection + */ +/*! Destination Protection bits for AXI bus AWPROT[2:0]. */ +#define ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22) +/*! Destination Protection bits default value. */ +#define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0) + +/* + * Destination Cache + */ +/*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */ +#define ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25) +/*! Destination Cache bits default value. */ +#define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0) + +/* + * Endian Swap size (in bits) + */ +/*! Endian Swap: No swap, 8-bit data. */ +#define ALT_DMA_CCR_OPT_ES8 (0 << 28) +/*! Endian Swap: Swap bytes within 16-bit data. */ +#define ALT_DMA_CCR_OPT_ES16 (1 << 28) +/*! Endian Swap: Swap bytes within 32-bit data. */ +#define ALT_DMA_CCR_OPT_ES32 (2 << 28) +/*! Endian Swap: Swap bytes within 64-bit data. */ +#define ALT_DMA_CCR_OPT_ES64 (3 << 28) +/*! Endian Swap: Swap bytes within 128-bit data. */ +#define ALT_DMA_CCR_OPT_ES128 (4 << 28) +/*! Endian Swap: Default byte swap. */ +#define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8 + +/*! Default CCR register options for a DMAMOV CCR assembler directive. */ +#define ALT_DMA_CCR_OPT_DEFAULT \ + (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \ + ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \ + ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \ + ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \ + ALT_DMA_CCR_OPT_ES8) + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_PROGRAM_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi.h new file mode 100644 index 0000000..d09ccf2 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi.h @@ -0,0 +1,1535 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/****************************************************************************** +* +* !!!! Customer Be Aware, Exception!!! +* +* 1. Qspi Direct Access Mode is not working! +* +* This is because the qspi flash memory installed on our DevKit board, Micro +* part N25Q00xx, 8 Gb, is not completely compatible with our embedded Synopsis +* QSPI controller IP. Therefore there is no viable direct access code offered +* in the lib. All the memory rea/write functionality is offered with indirect +* access only. +* +* Should you install a different flash memory part in your custom board, and +* wondering wether direct access mode works, please contact with us. +* +******************************************************************************/ + +/*! \file + * Altera - QSPI Flash Controller Module + */ + +#ifndef __ALT_QSPI_H__ +#define __ALT_QSPI_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI QSPI Flash Controller Module + * + * This module defines a low level driver API for the hardware processor system + * (HPS) quad serial peripheral interface (QSPI) flash controller for access to + * serial NOR flash devices. The quad SPI flash controller supports standard SPI + * flash devices as well as high-performance dual and quad SPI flash + * devices. + * + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_CSR General Control and Status Functions + * + * The declarations and functions in this group provide general purpose control + * and status functions for the QSPI Flash Controller. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Initialize the QSPI flash controller for use. + * + * \internal + * Implementation Notes: + * * The QSPI Controller has been designed to wake up in a state that is + * suitable for performing basic reads and writes using the direct access + * controller. + * * Bring out of reset + * * QSPI reference clock validation + * * See Programmer's Guide, Configuring the QSPI Controller for use after + * reset, in QSPI_FLASH_CTRL for full initialization details. + * \endinternal + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_init(void); + +/******************************************************************************/ +/*! + * Uninitialize the QSPI flash controller. + * + * Uninitialize the QSPI flash controller by cancelling any indirect transfers + * in progress and putting the QSPI controller into reset. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_uninit(void); + +/******************************************************************************/ +/*! + * Disable the QSPI Controller. + * + * Disable the QSPI once the current transfer of the data word (FF_W) is + * complete. All output enables are inactive and all pins are set to input + * mode. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_disable(void); + +/******************************************************************************/ +/*! + * Enable the QSPI Controller. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_enable(void); + +/******************************************************************************/ +/*! + * This type definition enumerates the interrupt status conditions for the QSPI + * controller. + * + * The enumerations serve as masks for the QSPI controller events that can be + * set when the designated conditions occur and the corresponding event is + * enabled. When any of these event source conditions are true, the \b + * ALT_INT_INTERRUPT_QSPI_IRQ interrupt output is asserted high. + * + * Interrupt sources are cleared when software calls alt_qspi_int_clear(). The + * interrupt sources are individually maskable using alt_qspi_int_disable() and + * alt_qspi_int_enable(). + */ +typedef enum ALT_QSPI_INT_STATUS_e +{ + /*! + * Mode fail M - indicates the voltage on pin n_ss_in is inconsistent with + * the SPI mode. Set = 1 if n_ss_in is low in master mode (multi-master + * contention). These conditions will clear the spi_enable bit and disable + * the SPI. + * * 0 = no mode fault has been detected. + * * 1 = a mode fault has occurred. + */ + ALT_QSPI_INT_STATUS_MODE_FAIL = (0x1 << 0), + + /*! + * Underflow Detected. + * * 0 = no underflow has been detected. + * * 1 = underflow is detected and an attempt to transfer data is made + * when the small TX FIFO is empty. This may occur when AHB write + * data is being supplied too slowly to keep up with the requested + * write operation. + */ + ALT_QSPI_INT_STATUS_UFL = (0x1 << 1), + + /*! + * Controller has completed last triggered indirect operation. + */ + ALT_QSPI_INT_STATUS_IDAC_OP_COMPLETE = (0x1 << 2), + + /*! + * Indirect operation was requested but could not be accepted. Two indirect + * operations already in storage. + */ + ALT_QSPI_INT_STATUS_IDAC_OP_REJECT = (0x1 << 3), + + /*! + * Write to protected area was attempted and rejected. + */ + ALT_QSPI_INT_STATUS_WR_PROT_VIOL = (0x1 << 4), + + /*! + * Illegal AHB Access Detected. AHB write wrapping bursts and the use of + * SPLIT/RETRY accesses will cause this interrupt to trigger. + */ + ALT_QSPI_INT_STATUS_ILL_AHB_ACCESS = (0x1 << 5), + + /*! + * Indirect Transfer Watermark Level Breached. + */ + ALT_QSPI_INT_STATUS_IDAC_WTRMK_TRIG = (0x1 << 6), + + /*! + * Receive Overflow. This should only occur in Legacy SPI mode. + * + * Set if an attempt is made to push the RX FIFO when it is full. This bit + * is reset only by a system reset and cleared only when this register is + * read. If a new push to the RX FIFO occurs coincident with a register read + * this flag will remain set. + * * 0 = no overflow has been detected. + * * 1 = an overflow has occurred. + */ + ALT_QSPI_INT_STATUS_RX_OVF = (0x1 << 7), + + /*! + * Small TX FIFO not full (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO has >= THRESHOLD entries. + * * 1 = FIFO has < THRESHOLD entries. + */ + ALT_QSPI_INT_STATUS_TX_FIFO_NOT_FULL = (0x1 << 8), + + /*! + * Small TX FIFO full (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO is not full. + * * 1 = FIFO is full. + */ + ALT_QSPI_INT_STATUS_TX_FIFO_FULL = (0x1 << 9), + + /*! + * Small RX FIFO not empty (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO has < RX THRESHOLD entries. + * * 1 = FIFO has >= THRESHOLD entries. + */ + ALT_QSPI_INT_STATUS_RX_FIFO_NOT_EMPTY = (0x1 << 10), + + /*! + * Small RX FIFO full (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO is not full. + * * 1 = FIFO is full. + */ + ALT_QSPI_INT_STATUS_RX_FIFO_FULL = (0x1 << 11), + + /*! + * Indirect Read partition of SRAM is full and unable to immediately + * complete indirect operation. + */ + ALT_QSPI_INT_STATUS_IDAC_RD_FULL = (0x1 << 12) + +} ALT_QSPI_INT_STATUS_t; + +/******************************************************************************/ +/*! + * Returns the QSPI controller interrupt status register value. + * + * This function returns the current value of the QSPI controller interrupt + * status register value which reflects the current QSPI controller status + * conditions. + * + * \returns The current value of the QSPI controller interrupt status + * register value which reflects the current QSPI controller status + * conditions as defined by the \ref ALT_QSPI_INT_STATUS_t mask. + * If the corresponding bit is set then the condition is asserted. + */ +uint32_t alt_qspi_int_status_get(void); + +/******************************************************************************/ +/*! + * Clears the specified QSPI controller interrupt status conditions identified + * in the mask. + * + * This function clears one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. + * + * \param mask + * Specifies the QSPI interrupt status conditions to clear. \e + * mask is a mask of logically OR'ed \ref ALT_QSPI_INT_STATUS_t + * values that designate the status conditions to clear. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_int_clear(const uint32_t mask); + +/******************************************************************************/ +/*! + * Disable the specified QSPI controller interrupt status conditions identified + * in the mask. + * + * This function disables one or more of the status conditions as contributors + * to the \b ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of enabling it as a contributor to the \b + * ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. The function + * alt_qspi_int_enable() is used to enable status source conditions. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed + * \ref ALT_QSPI_INT_STATUS_t values that designate the status + * conditions to disable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_int_disable(const uint32_t mask); + +/******************************************************************************/ +/*! + * Enable the specified QSPI controller interrupt status conditions identified + * in the mask. + * + * This function enables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of disabling it as a contributor to the \b + * ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. The function + * alt_qspi_int_disable() is used to disable status source conditions. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed + * \ref ALT_QSPI_INT_STATUS_t values that designate the status + * conditions to enable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_int_enable(const uint32_t mask); + +/******************************************************************************/ +/*! + * Returns true the serial interface and QSPI pipeline is IDLE. + * + * \returns Returns true the serial interface and QSPI pipeline is IDLE. + */ +bool alt_qspi_is_idle(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_GP_BLKIO General Purpose Block I/O + * + * The functions in this group provide general purpose block read and + * write flash functions. + * + * \internal + * These functions use Indirect Read/Write transfers to read and write block + * data to the flash device. An outline of the operational flow for these + * operations can be found in: + * //depot/soc/hhp_sw/baremetal_fw/drivers/qspi/qspi.c + * + * The general flow for an indirect block read is to call + * qspi_configure_mode_indirect_read_start() to initiate the read transfer from + * the flash device into the SRAM buffer and follow with a call to either + * qpsi_write_sram_fifo_poll() or qspi_read_sram_fifo_irq() to copy the data + * from SRAM into the user's buffer. + * + * The general flow for an indirect block write is to call + * qspi_configure_mode_indirect_write_start() to initiate the write transfer + * from the SRAM buffer to the flash device and follow with a call to either + * qpsi_write_sram_fifo_poll() or qspi_write_sram_fifo_irq() to fill the SRAM + * buffer with the user's data as space becomes available. + * \endinternal + * + * @{ + */ + +/******************************************************************************/ +/*! + * Read a block of data from the specified flash address. + * + * Reads a block of \e n data bytes from the flash \e src address into the user + * supplied \e dest buffer. The memory address, flash address, and size must be + * word aligned. + * + * \param dest + * The address of a caller supplied destination buffer large enough + * to contain the requested block of flash data. + * + * \param src + * The flash device address to start reading data from. + * + * \param size + * The requested number of data bytes to read from the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_read(void * dest, uint32_t src, size_t size); + +/******************************************************************************/ +/*! + * Write a block of data to the specified flash address. + * + * Writes a block of \e n data bytes to the flash \e dest address from the + * designated \e src buffer. The applicable destination flash address range + * should have been erased prior to calling this function. The flash address, + * memory address, and size must be word aligned. + * + * \param dest + * The destination flash address to begin writing data to. + * + * \param src + * The source address to start writing data from. + * + * \param size + * The requested number of data bytes to write to the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_write(uint32_t dest, const void * src, size_t size); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_DEV_CFG Flash Device Configuration + * + * The declarations and functions in this group are used to configure the QSPI + * controller interface to external flash devices. + * + * The following steps describe how to initialize and configure the + * QSPI controller to operate with a flash device. + * + * * Wait until any pending QSPI operations have completed. + * * Disable the QSPI controller using alt_qspi_disable(). + * * Configure the device for optimal read transaction performance using + * alt_qspi_device_read_config_set(). + * * Configure the device for optimal write transaction performance using + * alt_qspi_device_write_config_set(). + * * Enable (alt_qspi_mode_bit_disable()) or disable + * (alt_qspi_mode_bit_disable()) the mode bits per the device + * requirements. If mode bits are enabled, then configure the mode + * bit values using alt_qspi_mode_bit_config_set(). + * * Configure the device size and write protection information using + * alt_qspi_device_size_config_set(). + * * Configure the QSPI device delay and timing settings using + * alt_qspi_device_write_config_set(). + * * Configure the baud divisor setting to define the required clock frequency + * to the device using alt_qspi_baud_rate_div_set(). + * * Enable the QSPI controller using alt_qspi_enable(). + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type enumerates the operational modes the QSPI controller can be + * configured for. It may apply to instruction, address, and/or data width + * interactions between the QSPI controller and the flash device. + */ +typedef enum ALT_QSPI_MODE_e +{ + ALT_QSPI_MODE_SINGLE = 0, /*!< Use Standard Single SPI (SIO-SPI) mode (bits + * always transferred into the device on DQ0 + * only). Supported by all SPI flash devices. + */ + ALT_QSPI_MODE_DUAL = 1, /*!< Use Dual SPI (DIO-SPI) SPI mode where bits are + * transferred on DQ0 and DQ1. + */ + ALT_QSPI_MODE_QUAD = 2 /*!< Use Dual SPI (QIO-SPI) SPI mode where bits are + * transferred on DQ0, DQ1, DQ3, and DQ3. + */ +} ALT_QSPI_MODE_t; + +/******************************************************************************/ +/*! + * This type enumerates the mode configurations available for driving the + * ss_n[3:0] device chip selects. The chip selects may be controlled as either + * in a '1 of 4' or '4 to 16 decode' mode. + */ +typedef enum ALT_QSPI_CS_MODE_e +{ + ALT_QSPI_CS_MODE_SINGLE_SELECT = 0, /*!< Select 1 of 4 chip select ss_n[3:0] + */ + ALT_QSPI_CS_MODE_DECODE = 1 /*!< Select external 4 to 16 decode of + * ss_n[3:0]. + */ +} ALT_QSPI_CS_MODE_t; + +/******************************************************************************/ +/*! + * This type enumerates the QSPI controller master baud rate divisor selections. + */ +typedef enum ALT_QSPI_BAUD_DIV_e +{ + ALT_QSPI_BAUD_DIV_2 = 0x0, /*!< Divide by 2 */ + ALT_QSPI_BAUD_DIV_4 = 0x1, /*!< Divide by 4 */ + ALT_QSPI_BAUD_DIV_6 = 0x2, /*!< Divide by 6 */ + ALT_QSPI_BAUD_DIV_8 = 0x3, /*!< Divide by 8 */ + ALT_QSPI_BAUD_DIV_10 = 0x4, /*!< Divide by 10 */ + ALT_QSPI_BAUD_DIV_12 = 0x5, /*!< Divide by 12 */ + ALT_QSPI_BAUD_DIV_14 = 0x6, /*!< Divide by 14 */ + ALT_QSPI_BAUD_DIV_16 = 0x7, /*!< Divide by 16 */ + ALT_QSPI_BAUD_DIV_18 = 0x8, /*!< Divide by 18 */ + ALT_QSPI_BAUD_DIV_20 = 0x9, /*!< Divide by 20 */ + ALT_QSPI_BAUD_DIV_22 = 0xA, /*!< Divide by 22 */ + ALT_QSPI_BAUD_DIV_24 = 0xB, /*!< Divide by 24 */ + ALT_QSPI_BAUD_DIV_26 = 0xC, /*!< Divide by 26 */ + ALT_QSPI_BAUD_DIV_28 = 0xD, /*!< Divide by 28 */ + ALT_QSPI_BAUD_DIV_30 = 0xE, /*!< Divide by 30 */ + ALT_QSPI_BAUD_DIV_32 = 0xF /*!< Divide by 32 */ +} ALT_QSPI_BAUD_DIV_t; + +/******************************************************************************/ +/*! + * Device Size Configuration + * + * This type defines the structure used to specify flash device size and write + * protect regions. + */ +typedef struct ALT_QSPI_DEV_SIZE_CONFIG_s +{ + uint32_t block_size; /*!< Number of bytes per device block. The + * number is specified as a power of 2. + * That is 0 = 1 byte, 1 = 2 bytes, ... + * 16 = 65535 bytes, etc. + */ + uint32_t page_size; /*!< Number of bytes per device page. This + * is required by the controller for + * performing flash writes up to and + * across page boundaries. + */ + uint32_t addr_size; /*!< Number of bytes used for the flash + * address. The value is \e n + 1 + * based. That is 0 = 1 byte, 1 = 2 bytes, + * 2 = 3 bytes, 3 = 4 bytes. + */ + uint32_t lower_wrprot_block; /*!< The block number that defines the lower + * block in the range of blocks that is + * protected from writing. This field + * is ignored it write protection is + * disabled. + */ + uint32_t upper_wrprot_block; /*!< The block number that defines the upper + * block in the range of blocks that is + * protected from writing. This field + * is ignored it write protection is + * disabled. + */ + bool wrprot_enable; /*!< The write region enable value. A value + * of \b true enables write protection + * on the region specified by the + * \e lower_wrprot_block and + * \e upper_wrprot_block range. + */ +} ALT_QSPI_DEV_SIZE_CONFIG_t; + +/******************************************************************************/ +/*! + * This type enumerates the QSPI clock phase activity options outside the SPI + * word. + */ +typedef enum ALT_QSPI_CLK_PHASE_e +{ + ALT_QSPI_CLK_PHASE_ACTIVE = 0, /*!< The SPI clock is active outside the + * word + */ + ALT_QSPI_CLK_PHASE_INACTIVE = 1 /*!< The SPI clock is inactive outside the + * word + */ +} ALT_QSPI_CLK_PHASE_t; + +/******************************************************************************/ +/*! + * This type enumerates the QSPI clock polarity options outside the SPI word. + */ +typedef enum ALT_QSPI_CLK_POLARITY_e +{ + ALT_QSPI_CLK_POLARITY_LOW = 0, /*!< SPI clock is quiescent low outside the + * word. + */ + ALT_QSPI_CLK_POLARITY_HIGH = 1 /*!< SPI clock is quiescent high outside the + * word. + */ +} ALT_QSPI_CLK_POLARITY_t; + +/******************************************************************************/ +/*! + * QSPI Controller Timing Configuration + * + * This type defines the structure used to configure timing paramaters used by + * the QSPI controller to communicate with a target flash device. + * + * All timing values are defined in cycles of the SPI master ref clock. + */ +typedef struct ALT_QSPI_TIMING_CONFIG_s +{ + ALT_QSPI_CLK_PHASE_t clk_phase; /*!< Selects whether the clock is in an + * active or inactive phase outside the + * SPI word. + */ + + ALT_QSPI_CLK_POLARITY_t clk_pol; /*!< Selects whether the clock is quiescent + * low or high outside the SPI word. + */ + + uint32_t cs_da; /*!< Chip Select De-Assert. Added delay in + * master reference clocks for the length + * that the master mode chip select + * outputs are de-asserted between + * transactions. If CSDA = \e X, then the + * chip select de-assert time will be: 1 + * sclk_out + 1 ref_clk + \e X ref_clks. + */ + uint32_t cs_dads; /*!< Chip Select De-Assert Different + * Slaves. Delay in master reference + * clocks between one chip select being + * de-activated and the activation of + * another. This is used to ensure a quiet + * period between the selection of two + * different slaves. CSDADS is only + * relevant when switching between 2 + * different external flash devices. If + * CSDADS = \e X, then the delay will be: + * 1 sclk_out + 3 ref_clks + \e X + * ref_clks. + */ + uint32_t cs_eot; /*!< Chip Select End Of Transfer. Delay in + * master reference clocks between last + * bit of current transaction and + * de-asserting the device chip select + * (n_ss_out). By default (when CSEOT=0), + * the chip select will be de-asserted on + * the last falling edge of sclk_out at + * the completion of the current + * transaction. If CSEOT = \e X, then chip + * selected will de-assert \e X ref_clks + * after the last falling edge of + * sclk_out. + */ + uint32_t cs_sot; /*!< Chip Select Start Of Transfer. Delay in + * master reference clocks between setting + * n_ss_out low and first bit transfer. By + * default (CSSOT=0), chip select will be + * asserted half a SCLK period before the + * first rising edge of sclk_out. If CSSOT + * = \e X, chip select will be asserted + * half an sclk_out period before the + * first rising edge of sclk_out + \e X + * ref_clks. + */ + + uint32_t rd_datacap; /*!< The additional number of read data + * capture cycles (ref_clk) that should be + * applied to the internal read data + * capture circuit. The large + * clock-to-out delay of the flash memory + * together with trace delays as well as + * other device delays may impose a + * maximum flash clock frequency which is + * less than the flash memory device + * itself can operate at. To compensate, + * software should set this register to a + * value that guarantees robust data + * captures. + */ +} ALT_QSPI_TIMING_CONFIG_t; + +/******************************************************************************/ +/*! + * Device Instruction Configuration + * + * This type defines a structure for specifying the optimal instruction set + * configuration to use with a target flash device. + */ +typedef struct ALT_QSPI_DEV_INST_CONFIG_s +{ + uint32_t op_code; /*!< The read or write op code to use + * for the device transaction. + */ + ALT_QSPI_MODE_t inst_type; /*!< Instruction mode type for the + * controller to use with the + * device. The instruction type + * applies to all instructions + * (reads and writes) issued from + * either the Direct Access + * Controller or the Indirect + * Acces Controller. + */ + ALT_QSPI_MODE_t addr_xfer_type; /*!< Address transfer mode type. The + * value of this field is ignored + * if the \e inst_type data member + * is set to anything other than + * ALT_QSPI_MODE_SINGLE. In that + * case, the addr_xfer_type + * assumes the same mode as the \e + * inst_type. + */ + ALT_QSPI_MODE_t data_xfer_type; /*!< Data transfer mode type. The + * value of this field is ignored + * if the \e inst_type data member + * is set to anything other than + * ALT_QSPI_MODE_SINGLE. In that + * case, the data_xfer_type + * assumes the same mode as the \e + * inst_type. + */ + uint32_t dummy_cycles; /*!< Number of dummy clock cycles + * required by device for a read + * or write instruction. + */ + +} ALT_QSPI_DEV_INST_CONFIG_t; + +/******************************************************************************/ +/*! + * Get the current value of the QSPI master baud rate divisor. + * + * \returns The value of the QSPI master baud rate divisor. + */ +ALT_QSPI_BAUD_DIV_t alt_qspi_baud_rate_div_get(void); + +/******************************************************************************/ +/*! + * Set the current value of the QSPI master baud rate divisor. + * + * Sets the value of the QSPI master baud rate divisor. + * + * \param baud_rate_div + * The master baud rate divisor. Valid range includes + * even values 2 to 32. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_baud_rate_div_set(const ALT_QSPI_BAUD_DIV_t baud_rate_div); + +/******************************************************************************/ +/*! + * Get the current QSPI device peripheral chip select output and decode function + * configuration values. + * + * \param cs + * [out] The chip select line output values. + * + * \param cs_mode + * [out] The decode mode to use for the chip selects. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_chip_select_config_get(uint32_t* cs, ALT_QSPI_CS_MODE_t* cs_mode); + +/******************************************************************************/ +/*! + * Set the QSPI device peripheral chip select outputs and decode function + * configuration. + * + * The chip select lines output values operate according to the selected chip + * select decode mode. If \e cs_mode is ALT_QSPI_CS_MODE_SINGLE_SELECT then + * cs[3:0] are output thus: + * + * cs[3:0] | n_ss_out[3:0] + * :---------|:---------------------------- + * xxx0 | 1110 + * xx01 | 1101 + * x011 | 1011 + * 0111 | 0111 + * 1111 | 1111 (no peripheral selected) + * + * Otherwise if \e cs_mode is ALT_QSPI_CS_MODE_DECODE then cs[3:0] directly + * drives n_ss_out[3:0]. + * + * \param cs + * The chip select line output values. + * + * \param cs_mode + * The decode mode to use for the chip selects. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_chip_select_config_set(const uint32_t cs, + const ALT_QSPI_CS_MODE_t cs_mode); + +/******************************************************************************/ +/*! + * Disable the mode bits from being sent after the address bytes. + * + * Prevent the mode bits defined in the Mode Bit Configuration register from + * being sent following the address bytes. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_mode_bit_disable(void); + +/******************************************************************************/ +/*! + * Enable the mode bits to be sent after the address bytes. + * + * Ensure the mode bits defined in the Mode Bit Configuration register to + * be sent following the address bytes. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_mode_bit_enable(void); + +/******************************************************************************/ +/*! + * Get the current value of the Mode Bit Configuration register. + * + * \returns The 8 bit value that is sent to the device following the address + * bytes when the mode bit is enabled (see: alt_qspi_mode_bit_enable()) + */ +uint32_t alt_qspi_mode_bit_config_get(void); + +/******************************************************************************/ +/*! + * Set the value of the Mode Bit Configuration register. + * + * Set the value of the 8 bits that are sent to the device following the address + * bytes when the mode bit is enabled (see: alt_qspi_mode_bit_enable()) + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param mode_bits + * The 8 bit value sent to the device following the address bytes. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_mode_bit_config_set(const uint32_t mode_bits); + +/******************************************************************************/ +/*! + * Get the current flash device size and write protection configuration. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_DEV_SIZE_CONFIG_t structure to + * contain the returned flash device size and write protection + * configuration. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_size_config_get(ALT_QSPI_DEV_SIZE_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the flash device size and write protection configuration. + * + * \param cfg + * Pointer to a ALT_QSPI_DEV_SIZE_CONFIG_t structure containing the + * flash device size and write protection configuration. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_size_config_set(const ALT_QSPI_DEV_SIZE_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Get the current QSPI device read instruction configuration. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure to + * contain the returned QSPI controller instruction configuration + * used when performing read transactions with the device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_read_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the QSPI device read instruction configuration. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param cfg + * Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure specifying the + * desired op code, transfer widths, and dummy cycles for the QSPI + * controller to use when performing read transactions with the + * device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_read_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Get the current QSPI device write instruction configuration. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure to + * contain the returned QSPI controller instruction configuration + * used when performing write transactions with the device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_write_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the QSPI device write instruction configuration. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param cfg + * Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure specifying the + * desired op code, transfer widths, and dummy cycles for the QSPI + * controller to use when performing write transactions with the + * device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_write_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Get the QSPI device delay and timing configuration parameters. + * + * This function returns the settings of the chip select delay and timing + * configurations. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_TIMING_CONFIG_t structure to return + * the device timing and delay settings. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_timing_config_get(ALT_QSPI_TIMING_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the QSPI device delay and timing configuration parameters. + * + * This function allows the user to configure how the chip select is driven + * after each flash access. This is required as each device may have different + * timing requirements. As the serial clock frequency is increased, these + * timing parameters become more important and can be adjusted to meet the + * requirements of a specific flash device. All timings are defined in cycles + * of the SPI master ref clock. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param cfg + * Pointer to a ALT_QSPI_TIMING_CONFIG_t structure specifying the + * desired timing and delay settings. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_timing_config_set(const ALT_QSPI_TIMING_CONFIG_t * cfg); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_DAC Direct Access Mode + * + * In direct access mode, an access to the AHB data slave triggers a read or + * write command to the flash memory. To use the direct access mode, enable the + * direct access controller with the alt_qspi_direct_enable() function. An + * external master, for example a processor, triggers the direct access + * controller with a read or write operation to the AHB data slave + * interface. The data slave exposes a 1MB window into the flash device. You can + * remap this window to any 1MB location within the flash device address range. + * + * To remap the AHB data slave to access other 1MB regions of the flash device, + * enable address remapping by calling alt_qspi_ahb_address_remap_enable(). All + * incoming data slave accesses remap to the offset specified in the remap + * address register which is configured by alt_qspi_ahb_remap_address_set(). + * + * The 20 LSBs of incoming addresses are used for accessing the 1MB region and + * the higher bits are ignored. + * + * The quad SPI controller does not issue any error status for accesses that lie + * outside the connected flash memory space. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Disable the QSPI Direct Access Controller. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_direct_disable(void); + +/******************************************************************************/ +/*! + * Enable the QSPI Direct Access Controller. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_direct_enable(void); + +/******************************************************************************/ +/*! + * Get the current AHB address remap value. + * + * Returns the current value of the AHB remap address register. + * + * \returns The value used to remap an incoming AHB address to a + * different address used by the flash device. + */ +uint32_t alt_qspi_ahb_remap_address_get(void); + +/******************************************************************************/ +/*! + * Set the AHB address remap value. + * + * Sets the value of the AHB remap address register. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param ahb_remap_addr + * The value used to remap an incoming AHB address to a different + * address used by the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_ahb_remap_address_set(const uint32_t ahb_remap_addr); + +/******************************************************************************/ +/*! + * Disable AHB address remapping. + * + * Disables remapping of incoming AHB addresses so they are sent unmodified to + * the flash device. The incoming AHB address maps directly to the address + * serially sent to the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_ahb_address_remap_disable(void); + +/******************************************************************************/ +/*! + * Enable AHB address remapping. + * + * Enables remapping of incoming AHB addresses so they are modified to + * \ + \e N, where \e N is the configured remap address value. + * + * See: alt_qspi_ahb_remap_address_set(). + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_ahb_address_remap_enable(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_INDAC Indirect Access Mode + * + * In indirect access mode, flash data is temporarily buffered in the QSPI + * controller's SRAM. Software controls and triggers indirect accesses through + * the APB register slave interface. The controller transfers data through the + * AHB data slave interface. + * + * An indirect read operation reads data from the flash memory, places the data + * into the SRAM, and transfers the data to an external master through the AHB + * data slave interface. + * + * An indirect write operation programs data from the SRAM to the flash memory. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Starts an indirect read transfer. + * + * Initiates an indirect read transfer of the requested number of bytes from the + * designated flash address. + * + * After calling this function, flash data may be read from the QSPI SRAM buffer + * as it becomes available via one of the following methods: + * * Directly from the AHB data slave interface at the configured AHB trigger + * address. If the requested data is not immediately available in the SRAM + * buffer then AHB wait states will be applied until the data has been read + * from flash into the SRAM buffer. Alternatively, data may be read from the + * AHB data slave as the SRAM is filled. The availability of data in the SRAM + * buffer may be determined by an SRAM watermark interrupt notification or by + * polling the SRAM fill level. + * * Configuring and enabling the QSPI DMA peripheral controller. + * + * The following is a list of restrictions: + * * flash_addr must be word aligned. + * * num_bytes must be word aligned. + * * The transfer must not cross the 3-byte addressing boundary. This + * restriction may be device specific and may be lifted in the future. + * + * \param flash_addr + * The flash source address to read data from. + * + * \param num_bytes + * The number of bytes to read from the flash source address. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_start(const uint32_t flash_addr, + const size_t num_bytes); + +/******************************************************************************/ +/*! + * Finish the indirect read operation that was completed or canceled. This + * function should be called before another indirect read is started. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_finish(void); + +/******************************************************************************/ +/*! + * Cancel all indirect read transfers in progress. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_cancel(void); + +/******************************************************************************/ +/*! + * Get the current indirect read SRAM fill level value. + * + * Returns the SRAM fill level for the indirect read partition in units of SRAM + * words (4 bytes). + * + * \returns The SRAM fill level for the indirect read partition in units of + * SRAM words (4 bytes). + */ +uint32_t alt_qspi_indirect_read_fill_level(void); + +/******************************************************************************/ +/*! + * Get the current indirect read watermark value. + * + * The watermark value (in bytes) represents the minimum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level passes + * the watermark, an interrupt source is also generated. This can be disabled by + * writing a value of all zeroes. + * + * \returns The current indirect read watermark value. + */ +uint32_t alt_qspi_indirect_read_watermark_get(void); + +/******************************************************************************/ +/*! + * Set the indirect read watermark value. + * + * The watermark value (in bytes) represents the minimum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level passes + * the watermark, an interrupt source is also generated. This can be disabled by + * writing a value of all zeroes. The watermark can only be set when no indirect + * read is in progress. + * + * \param watermark + * The watermark value (in bytes). + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_watermark_set(const uint32_t watermark); + +/******************************************************************************/ +/*! + * Returns true when an indirect read has completed otherwise false. + * + * \internal + * Returns Indirect Read Transfer Control Register bit 5 "Indirect Completion Status". + * \endinternal + * + * \returns Returns true when an indirect read has completed otherwise false. + */ +bool alt_qspi_indirect_read_is_complete(void); + +/******************************************************************************/ +/*! + * Starts an indirect write transfer. + * + * Initiates an indirect write transfer of the requested number of bytes to the + * designated flash address. + * + * After calling this function, flash data may be written to the QSPI SRAM + * buffer there is space via one of the following methods: + * * Directly from the AHB data slave interface at the configured AHB trigger + * address. If the requested space is not immediately available in the SRAM + * buffer then AHB wait states will be applied until the space becomes + * available. Alternatively, the data may be written to the AHB data slave + * as the SRAM is drained. The space in the SRAM buffer may be determined by + * an SRAM watermark interrupt notification or by polling the SRAM fill + * level and subtracting that value from the SRAM space devoted to writes. + * * Configuring and enabling the QSPI DMA peripheral controller. + * + * The following is a list of restrictions: + * * flash_addr must be word aligned. + * * num_bytes must be word aligned. + * * num_bytes must be 256 or below. This is due to a device specific + * limitation and may be lifted in the future. + * * The transfer must not cross the page (256 byte) addressing boundary. This + * restriction may be device specific and may be lifted in the future. + * + * \param flash_addr + * The flash destination address to write data to. + * + * \param num_bytes + * The number of bytes to write to the flash. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_start(const uint32_t flash_addr, + const size_t num_bytes); + +/******************************************************************************/ +/*! + * Finish the indirect write operation that was completed or canceled. This + * function should be called before another indirect write is started. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_finish(void); + +/******************************************************************************/ +/*! + * Cancel all indirect write transfers in progress. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_cancel(void); + +/******************************************************************************/ +/*! + * Get the current indirect write SRAM fill level value. + * + * Returns the SRAM fill level for the indirect write partition in units of SRAM + * words (4 bytes). + * + * \returns The SRAM fill level for the indirect write partition in units of + * SRAM words (4 bytes). + */ +uint32_t alt_qspi_indirect_write_fill_level(void); + +/******************************************************************************/ +/*! + * Get the current indirect write watermark value. + * + * The watermark value (in bytes) represents the maximum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level falls + * below the watermark, an interrupt is also generated. This can be disabled by + * writing a value of all ones. + * + * \returns The current indirect write watermark value. + */ +uint32_t alt_qspi_indirect_write_watermark_get(void); + +/******************************************************************************/ +/*! + * Set the indirect write watermark value. + * + * The watermark value (in bytes) represents the maximum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level falls + * below the watermark, an interrupt is also generated. This can be disabled by + * writing a value of all ones. The watermark can only be set when no indirect + * write is in progress. + * + * \param watermark + * The watermark value (in bytes). + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_watermark_set(const uint32_t watermark); + +/******************************************************************************/ +/*! + * Returns true when an indirect write has completed otherwise false. + * + * \internal + * Returns Indirect Write Transfer Control Register bit 5 "Indirect Completion + * Status". + * \endinternal + * + * \returns Returns true when an indirect write has completed otherwise + * false. + */ +bool alt_qspi_indirect_write_is_complete(void); + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_CFG_SRAM SRAM Partition + * + * The SRAM local memory buffer is a 128 by 32-bit (512 total bytes) memory. The + * SRAM has two partitions, with the lower partition reserved for indirect read + * operations and the upper partition for indirect write operations. The size of + * the partitions is specified in the SRAM partition register, based on 32-bit + * word sizes. For example, to specify four bytes of storage, write the value 1. + * The value written to the indirect read partition size field ( addr ) defines + * the number of entries reserved for indirect read operations. For example, write + * the value 32 (0x20) to partition the 128-entry SRAM to 32 entries (25%) for + * read usage and 96 entries (75%) for write usage. + * + * The functions in this section provide accces to configure the SRAM read + * partition allocation. + * + * @{ + */ + +/*! + * The size of the onboard SRAM in bytes. + */ +#define ALT_QSPI_SRAM_FIFO_SIZE (512) + +/* + * The size of the onboard SRAM in entries. Each entry is word (32-bit) sized. + */ +#define ALT_QSPI_SRAM_FIFO_ENTRY_COUNT (512 / sizeof(uint32_t)) + +/******************************************************************************/ +/*! + * Get the entry count (words) of the indirect read partition in the QSPI + * controller SRAM. + * + * There is an additional word of read memory not in the SRAM but used to + * buffer the SRAM and the AHB. As such, the total on board memory buffer for + * indirect read is 1 more than the value reported by this function. + * + * \returns The count of 32-bit words of the indirect read partition in the + * QSPI controller SRAM. + * + * \internal + * The documentation states that the number of locations allocated to indirect + * read = SRAM_PARTITION_REG + 1. Cadence clarified that the +1 comes from an + * additional register slice for read's, implemented in FLOPs, which was done + * to avoid connection the SRAM directly to the AHB interface. This was done + * for performance / timing reasons. The +1 will not be included in the return + * value but documented as an additional entry. + * \endinternal + */ +uint32_t alt_qspi_sram_partition_get(void); + +/******************************************************************************/ +/*! + * Set the entry count (words) of the indirect read partition in the QSPI + * controller SRAM. + * + * Note: It is recommended that setting SRAM partition to 0 or 127 should be + * avoided although it is not prohibited. + * + * \param read_part_size + * The count of 32-bit words to allocate to the indirect read + * partition in the QSPI controller SRAM. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_sram_partition_set(const uint32_t read_part_size); + +/*! @} */ + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_ERASE Flash Erase + * + * The functions in this group are used to erase selected portions of a flash + * device. + * @{ + */ + +/******************************************************************************/ +/*! + * This function erases the designated flash device subsector. + * + * This function erases the flash device subsector containing the designated + * flash address. Any address within the subsector is valid. + * + * \param addr + * A flash address contained within the the subsector to be erased. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_erase_subsector(const uint32_t addr); + +/******************************************************************************/ +/*! + * This function erases the designated flash device sector. + * + * This function erases the flash device sector containing the designated flash + * address. Any address within the sector is valid. + * + * \param addr + * A flash address contained within the the sector to be erased. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_erase_sector(const uint32_t addr); + +/******************************************************************************/ +/*! + * This function erases the entire flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_erase_chip(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_DMA DMA Peripheral Interface + * + * The DMA peripheral request controller is only used for the indirect mode of + * operation where data is temporarily stored in the SRAM. The QSPI flash + * controller uses the DMA peripheral request interface to trigger the external + * DMA into performing data transfers between memory and the QSPI + * controller. + * + * There are two DMA peripheral request interfaces, one for indirect reads and + * one for indirect writes. The DMA peripheral request controller can issue two + * types of DMA requests, single or burst, to the external DMA. The number of + * bytes for each single or burst request is specified using the + * alt_qspi_dma_config_set(). The DMA peripheral request controller splits the + * total amount of data to be transferred into a number of DMA burst and single + * requests by dividing the total number of bytes by the number of bytes + * specified in the burst request, and then dividing the remainder by the number + * of bytes in a single request. + * + * When programming the DMA controller, the burst request size must match the + * burst request size set in the quad SPI controller to avoid quickly reaching + * an overflow or underflow condition. + * @{ + */ + +/******************************************************************************/ +/*! + * Disable the QSPI DMA peripheral interface. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_disable(void); + +/******************************************************************************/ +/*! + * Enable the QSPI DMA peripheral interface. + * + * Enable the QSPI DMA handshaking logic. When enabled the QSPI will trigger DMA + * transfer requests via the DMA peripheral interface. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_enable(void); + +/******************************************************************************/ +/*! + * Get the current DMA peripheral configuration. + * + * This function returns the QSPI DMA peripheral interface single and burst type + * transfer size configurations. + * + * \param single_type_sz + * [out] The number of bytes for each DMA single type + * request. Value must be a power of 2 between 1 and 32728. + * + * \param burst_type_sz + * [out] The number of bytes for each DMA burst type request. Value + * must be a power of 2 between 1 and 32728. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_config_get(uint32_t * single_type_sz, + uint32_t * burst_type_sz); + +/******************************************************************************/ +/*! + * Set the DMA peripheral configuration. + * + * This function configures the QSPI DMA peripheral interface single and burst + * type transfer sizes. The DMA configruation should be setup while the + * controller is idle. Because all transfers are required to be word aligned, + * the smallest DMA request is 4 bytes. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param single_type_sz + * The number of bytes for each DMA single type request. Value must + * be a power of 2 between 4 and 32768. + * + * \param burst_type_sz + * The number of bytes for each DMA burst type request. Value must + * be a power of 2 between 4 and 32768. Bursts must be equal or + * larger than single requests. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_config_set(const uint32_t single_type_sz, + const uint32_t burst_type_sz); + + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_QSPI_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi_private.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi_private.h new file mode 100644 index 0000000..21fd3a9 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi_private.h @@ -0,0 +1,167 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! \file + * Altera - QSPI Flash Controller Module + */ + +#ifndef __ALT_QSPI_PRIVATE_H__ +#define __ALT_QSPI_PRIVATE_H__ + +#include "socal/socal.h" + +// +// This section provisions support for various flash devices. +// + +#define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1 + +///// + +#define ALT_QSPI_PAGE_ADDR_MSK 0xFFFFFF00 +#define ALT_QSPI_PAGE_SIZE 0x00000100 // 256 B +#define ALT_QSPI_SUBSECTOR_ADDR_MSK 0xFFFFF000 +#define ALT_QSPI_SUBSECTOR_SIZE 0x00001000 // 4096 B +#define ALT_QSPI_SECTOR_ADDR_MSK 0xFFFF0000 +#define ALT_QSPI_SECTOR_SIZE 0x00010000 // 64 KiB +#define ALT_QSPI_BANK_ADDR_MSK 0xFF000000 +#define ALT_QSPI_BANK_SIZE 0x01000000 // 16 MiB + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +#define ALT_QSPI_N25Q_DIE_ADDR_MSK 0xFE000000 +#define ALT_QSPI_N25Q_DIE_SIZE 0x02000000 // 32 MiB +#endif + +///// + +// Default delay timing (in ns) for N25Q. +// These values are from the N25Q handbook. The timing correctness is difficult +// to test because the test setup does not feature mutliple chips. +#define ALT_QSPI_TSHSL_NS_DEF (50) +#define ALT_QSPI_TSD2D_NS_DEF (0) +#define ALT_QSPI_TCHSH_NS_DEF (4) +#define ALT_QSPI_TSLCH_NS_DEF (4) + +/* +// Default delay timing (in ns) +#define ALT_QSPI_TSHSL_NS_DEF (200) +#define ALT_QSPI_TSD2D_NS_DEF (255) +#define ALT_QSPI_TCHSH_NS_DEF (20) +#define ALT_QSPI_TSLCH_NS_DEF (20) +*/ + +// Flash commands +#define ALT_QSPI_STIG_OPCODE_READ (0x03) +#define ALT_QSPI_STIG_OPCODE_4BYTE_READ (0x13) +#define ALT_QSPI_STIG_OPCODE_FASTREAD (0x0B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO (0xBB) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO (0xEB) +#define ALT_QSPI_STIG_OPCODE_PP (0x02) +#define ALT_QSPI_STIG_OPCODE_DUAL_PP (0xA2) +#define ALT_QSPI_STIG_OPCODE_QUAD_PP (0x32) +#define ALT_QSPI_STIG_OPCODE_RDID (0x9F) +#define ALT_QSPI_STIG_OPCODE_WREN (0x06) +#define ALT_QSPI_STIG_OPCODE_WRDIS (0x04) +#define ALT_QSPI_STIG_OPCODE_RDSR (0x05) +#define ALT_QSPI_STIG_OPCODE_WRSR (0x01) +#define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE (0x20) +#define ALT_QSPI_STIG_OPCODE_SEC_ERASE (0xD8) +#define ALT_QSPI_STIG_OPCODE_BULK_ERASE (0xC7) +#define ALT_QSPI_STIG_OPCODE_DIE_ERASE (0xC4) +#define ALT_QSPI_STIG_OPCODE_CHIP_ERASE (0x60) +#define ALT_QSPI_STIG_OPCODE_RD_EXT_REG (0xC8) +#define ALT_QSPI_STIG_OPCODE_WR_EXT_REG (0xC5) +#define ALT_QSPI_STIG_OPCODE_RD_STAT_REG (0x05) +#define ALT_QSPI_STIG_OPCODE_WR_STAT_REG (0x01) +#define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE (0xB7) +#define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE (0xE9) + +// Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts. +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +#define ALT_QSPI_STIG_OPCODE_RESET_EN (0x66) +#define ALT_QSPI_STIG_OPCODE_RESET_MEM (0x99) +#define ALT_QSPI_STIG_OPCODE_RDFLGSR (0x70) +#define ALT_QSPI_STIG_OPCODE_CLRFLGSR (0x50) +#define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM (0x5A) +#endif + +// Spansion commands +// #define OPCODE_ECRM (0xFF) // Exit continuous read mode + +#define QSPI_READ_CLK_MHZ (50) +#define QSPI_FASTREAD_CLK_MHZ (100) + +// Manufacturer ID +#define ALT_QSPI_STIG_RDID_JEDECID_MICRON (0x20) +#define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX (0x20) // Same as Micron +#define ALT_QSPI_STIG_RDID_JEDECID_SPANSION (0xEF) +#define ALT_QSPI_STIG_RDID_JEDECID_WINBOND (0xEF) // Same as Spansion +#define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC (0xC2) +#define ALT_QSPI_STIG_RDID_JEDECID_ATMEL (0x1F) + +#define ALT_QSPI_STIG_RDID_JEDECID_GET(value) ((value >> 0) & 0xff) +#define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff) + +#define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value) ((value >> 5) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value) ((value >> 4) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value) ((value >> 1) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value) ((value >> 0) & 0x1) + +#define ALT_QSPI_STIG_SR_BUSY_GET(value) ((value >> 0) & 0x1) + +///// + +#define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff) + +ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size); + +ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy, + uint32_t num_bytes, uint32_t * output, + uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy, + uint32_t num_bytes, const uint32_t * input, + uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy, + uint32_t address, + uint32_t timeout); + +ALT_STATUS_CODE alt_qspi_device_wren(void); +ALT_STATUS_CODE alt_qspi_device_wrdis(void); +ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid); +ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param); +ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank); + +#endif // __ALT_PRIVATE_QSPI_H__ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmanonsecure.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmanonsecure.h new file mode 100644 index 0000000..1425708 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmanonsecure.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_DMANONSECURE */ + +#ifndef __ALTERA_ALT_DMANONSECURE_H__ +#define __ALTERA_ALT_DMANONSECURE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : nonsecure DMA Module Address Space - ALT_DMANONSECURE + * nonsecure DMA Module Address Space + * + * Address space allocated to the nonsecure DMA. For detailed information about the + * use of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click + * here[/url] to access the ARM documentation for the DMA-330. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_MSB 31 +/* The width in bits of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_DMANONSECURE_REG_FLD register field value. */ +#define ALT_DMANONSECURE_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_DMANONSECURE_REG_FLD register field value. */ +#define ALT_DMANONSECURE_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_DMANONSECURE_REG_FLD register field is UNKNOWN. */ +#define ALT_DMANONSECURE_REG_FLD_RESET 0x0 +/* Extracts the ALT_DMANONSECURE_REG_FLD field value from a register. */ +#define ALT_DMANONSECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_DMANONSECURE_REG_FLD register field value suitable for setting the register. */ +#define ALT_DMANONSECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_DMANONSECURE_REG. + */ +struct ALT_DMANONSECURE_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_DMANONSECURE_REG. */ +typedef volatile struct ALT_DMANONSECURE_REG_s ALT_DMANONSECURE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_DMANONSECURE_REG register from the beginning of the component. */ +#define ALT_DMANONSECURE_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_DMANONSECURE. + */ +struct ALT_DMANONSECURE_s +{ + volatile ALT_DMANONSECURE_REG_t reg; /* ALT_DMANONSECURE_REG */ +}; + +/* The typedef declaration for register group ALT_DMANONSECURE. */ +typedef volatile struct ALT_DMANONSECURE_s ALT_DMANONSECURE_t; +/* The struct declaration for the raw register contents of register group ALT_DMANONSECURE. */ +struct ALT_DMANONSECURE_raw_s +{ + volatile uint32_t reg; /* ALT_DMANONSECURE_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_DMANONSECURE. */ +typedef volatile struct ALT_DMANONSECURE_raw_s ALT_DMANONSECURE_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_DMANONSECURE_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmasecure.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmasecure.h new file mode 100644 index 0000000..5941433 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmasecure.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_DMASECURE */ + +#ifndef __ALTERA_ALT_DMASECURE_H__ +#define __ALTERA_ALT_DMASECURE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : secure DMA Module Address Space - ALT_DMASECURE + * secure DMA Module Address Space + * + * Address space allocated to the secure DMA. For detailed information about the + * use of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click + * here[/url] to access the ARM documentation for the DMA-330. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_MSB 31 +/* The width in bits of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_DMASECURE_REG_FLD register field value. */ +#define ALT_DMASECURE_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_DMASECURE_REG_FLD register field value. */ +#define ALT_DMASECURE_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_DMASECURE_REG_FLD register field is UNKNOWN. */ +#define ALT_DMASECURE_REG_FLD_RESET 0x0 +/* Extracts the ALT_DMASECURE_REG_FLD field value from a register. */ +#define ALT_DMASECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_DMASECURE_REG_FLD register field value suitable for setting the register. */ +#define ALT_DMASECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_DMASECURE_REG. + */ +struct ALT_DMASECURE_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_DMASECURE_REG. */ +typedef volatile struct ALT_DMASECURE_REG_s ALT_DMASECURE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_DMASECURE_REG register from the beginning of the component. */ +#define ALT_DMASECURE_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_DMASECURE. + */ +struct ALT_DMASECURE_s +{ + volatile ALT_DMASECURE_REG_t reg; /* ALT_DMASECURE_REG */ +}; + +/* The typedef declaration for register group ALT_DMASECURE. */ +typedef volatile struct ALT_DMASECURE_s ALT_DMASECURE_t; +/* The struct declaration for the raw register contents of register group ALT_DMASECURE. */ +struct ALT_DMASECURE_raw_s +{ + volatile uint32_t reg; /* ALT_DMASECURE_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_DMASECURE. */ +typedef volatile struct ALT_DMASECURE_raw_s ALT_DMASECURE_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_DMASECURE_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspi.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspi.h new file mode 100644 index 0000000..cbec31b --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspi.h @@ -0,0 +1,5951 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_QSPI */ + +#ifndef __ALTERA_ALT_QSPI_H__ +#define __ALTERA_ALT_QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : QSPI Flash Controller Module Registers - ALT_QSPI + * QSPI Flash Controller Module Registers + * + * Registers in the QSPI Flash Controller module accessible via its APB slave + * + */ +/* + * Register : QSPI Configuration Register - cfg + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------- + * [0] | RW | 0x0 | QSPI Enable + * [1] | RW | 0x0 | Clock Polarity + * [2] | RW | 0x0 | Select Clock Phase + * [6:3] | ??? | 0x0 | *UNDEFINED* + * [7] | RW | 0x0 | Enable Direct Access Controller + * [8] | RW | 0x0 | Legacy IP Mode Enable + * [9] | RW | 0x0 | Peripheral select decode + * [13:10] | RW | 0x0 | Peripheral Chip Select Lines + * [14] | RW | 0x0 | Write Protect Flash Pin + * [15] | RW | 0x0 | Enable DMA Peripheral Interface + * [16] | RW | 0x0 | Enable AHB Address Re-mapping + * [17] | RW | 0x0 | Enter XIP Mode on next READ + * [18] | RW | 0x0 | Enter XIP Mode Immediately + * [22:19] | RW | 0xf | Master Mode Baud Rate Divisor + * [30:23] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x0 | Serial interface and QSPI pipeline is IDLE + * + */ +/* + * Field : QSPI Enable - en + * + * If this bit is disabled, the QSPI will finish the current transfer of the data + * word (FF_W) and stop sending. When Enabled, and qspi_n_mo_en = 0, all output + * enables are inactive and all pins are set to input mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------|:------|:----------------- + * ALT_QSPI_CFG_EN_E_DIS | 0x0 | Disable the QSPI + * ALT_QSPI_CFG_EN_E_EN | 0x1 | Enable the QSPI + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_EN + * + * Disable the QSPI + */ +#define ALT_QSPI_CFG_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_EN + * + * Enable the QSPI + */ +#define ALT_QSPI_CFG_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_MSB 0 +/* The width in bits of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_EN register field value. */ +#define ALT_QSPI_CFG_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_CFG_EN register field value. */ +#define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_EN field value from a register. */ +#define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Clock Polarity - selclkpol + * + * Controls spiclk modes of operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------- + * ALT_QSPI_CFG_SELCLKPOL_E_LOW | 0x1 | SPI clock is quiescent low + * ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0 | SPI clock is quiescent high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL + * + * SPI clock is quiescent low + */ +#define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL + * + * SPI clock is quiescent high + */ +#define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_MSB 1 +/* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */ +#define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */ +#define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */ +#define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Select Clock Phase - selclkphase + * + * Selects whether the clock is in an active or inactive phase outside the SPI + * word. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:--------------------------- + * ALT_QSPI_CFG_SELCLKPHASE_E_ACT | 0x0 | SPI clock is quiescent low + * ALT_QSPI_CFG_SELCLKPHASE_E_INACT | 0x1 | Clock Inactive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE + * + * SPI clock is quiescent low + */ +#define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE + * + * Clock Inactive + */ +#define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_MSB 2 +/* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */ +#define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */ +#define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */ +#define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Enable Direct Access Controller - endiracc + * + * If disabled, the Direct Access Controller becomes inactive once the current + * transfer of the data word (FF_W) is complete. When the Direct Access Controller + * and Indirect Access Controller are both disabled, all AHB requests are completed + * with an error response. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_QSPI_CFG_ENDIRACC_E_DIS | 0x0 | Disable Direct Access Ctrl + * ALT_QSPI_CFG_ENDIRACC_E_EN | 0x1 | Enable Direct Access Ctrl + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC + * + * Disable Direct Access Ctrl + */ +#define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC + * + * Enable Direct Access Ctrl + */ +#define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_MSB 7 +/* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */ +#define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */ +#define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */ +#define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Legacy IP Mode Enable - enlegacyip + * + * This bit can select the Direct Access Controller/Indirect Access Controller or + * legacy mode.If legacy mode is selected, any write to the controller via the AHB + * interface is serialized and sent to the FLASH device. Any valid AHB read will + * pop the internal RX-FIFO, retrieving data that was forwarded by the external + * FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and + * controlled via the HSIZE input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------------------------------- + * ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD | 0x1 | Legacy Mode + * ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD | 0x0 | Use Direct/Indirect Access Controller + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP + * + * Legacy Mode + */ +#define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP + * + * Use Direct/Indirect Access Controller + */ +#define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_MSB 8 +/* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */ +#define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */ +#define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */ +#define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Peripheral select decode - perseldec + * + * Select between '1 of 4 selects' or 'external 4-to-16 decode'. The + * qspi_n_ss_out[3:0] output signals are controlled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------- + * ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1 | Select external 4-to-16 decode + * ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 | 0x0 | Selects 1 of 4 qspi_n_ss_out[3:0] + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC + * + * Select external 4-to-16 decode + */ +#define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC + * + * Selects 1 of 4 qspi_n_ss_out[3:0] + */ +#define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_MSB 9 +/* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */ +#define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */ +#define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */ +#define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Peripheral Chip Select Lines - percslines + * + * Peripheral chip select line output decode type. As per perseldec, if perseldec = + * 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The + * asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0] + * require an external 4 to 16 decoder. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_MSB 13 +/* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_WIDTH 4 +/* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */ +#define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00 +/* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */ +#define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff +/* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */ +#define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10) +/* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00) + +/* + * Field : Write Protect Flash Pin - wp + * + * This bit controls the write protect pin of the flash devices. The signal + * qspi_mo2_wpn needs to be resynchronized to the generated memory clock as + * necessary. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------- + * ALT_QSPI_CFG_WP_E_WRPROTON | 0x1 | Enable Write Protect + * ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0 | Disable Write Protect + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_WP + * + * Enable Write Protect + */ +#define ALT_QSPI_CFG_WP_E_WRPROTON 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_WP + * + * Disable Write Protect + */ +#define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_MSB 14 +/* The width in bits of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_WP register field value. */ +#define ALT_QSPI_CFG_WP_SET_MSK 0x00004000 +/* The mask used to clear the ALT_QSPI_CFG_WP register field value. */ +#define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff +/* The reset value of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_WP field value from a register. */ +#define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Enable DMA Peripheral Interface - endma + * + * Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer + * requests via the DMA peripheral interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------- + * ALT_QSPI_CFG_ENDMA_E_EN | 0x1 | Enable DMA Mode + * ALT_QSPI_CFG_ENDMA_E_DIS | 0x0 | Disable DMA Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDMA + * + * Enable DMA Mode + */ +#define ALT_QSPI_CFG_ENDMA_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDMA + * + * Disable DMA Mode + */ +#define ALT_QSPI_CFG_ENDMA_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_MSB 15 +/* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */ +#define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000 +/* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */ +#define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff +/* The reset value of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */ +#define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Enable AHB Address Re-mapping - enahbremap + * + * (Direct Access Mode Only) When enabled, the incoming AHB address will be adapted + * and sent to the FLASH device as (address + N), where N is the value stored in + * the remap address register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------- + * ALT_QSPI_CFG_ENAHBREMAP_E_EN | 0x1 | Enable AHB Re-mapping + * ALT_QSPI_CFG_ENAHBREMAP_E_DIS | 0x0 | Disable AHB Re-mapping + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP + * + * Enable AHB Re-mapping + */ +#define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP + * + * Disable AHB Re-mapping + */ +#define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_MSB 16 +/* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */ +#define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000 +/* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */ +#define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff +/* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */ +#define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Enter XIP Mode on next READ - enterxipnextrd + * + * If XIP is enabled, then setting to disabled will cause the controller to exit + * XIP mode on the next READ instruction. If XIP is disabled, then setting to + * enabled will inform the controller that the device is ready to enter XIP on the + * next READ instruction. The controller will therefore send the appropriate + * command sequence, including mode bits to cause the device to enter XIP mode. Use + * this register after the controller has ensured the FLASH device has been + * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit + * should be set to 0. This will take effect in the attached device only AFTER the + * next READ instruction is executed. Software should therefore ensure that at + * least one READ instruction is requested after resetting this bit before it can + * be sure XIP mode in the device is exited. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------- + * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN | 0x1 | Enter XIP Mode on next READ instruction + * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS | 0x0 | Exit XIP Mode on next READ instruction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD + * + * Enter XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD + * + * Exit XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17 +/* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000 +/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff +/* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Enter XIP Mode Immediately - enterxipimm + * + * If XIP is enabled, then setting to disabled will cause the controller to exit + * XIP mode on the next READ instruction. If XIP is disabled, then setting enable + * will operate the device in XIP mode immediately. Use this register when the + * external device wakes up in XIP mode (as per the contents of its non- volatile + * configuration register). The controller will assume the next READ instruction + * will be passed to the device as an XIP instruction, and therefore will not + * require the READ opcode to be transferred. Note: To exit XIP mode, this bit + * should be set to 0. This will take effect in the attached device only after the + * next READ instruction is executed. Software therefore should ensure that at + * least one READ instruction is requested after resetting this bit in order to be + * sure that XIP mode is exited. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:--------------------------------------- + * ALT_QSPI_CFG_ENTERXIPIMM_E_EN | 0x1 | Enter XIP Mode immediately + * ALT_QSPI_CFG_ENTERXIPIMM_E_DIS | 0x0 | Exit XIP Mode on next READ instruction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM + * + * Enter XIP Mode immediately + */ +#define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM + * + * Exit XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18 +/* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000 +/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff +/* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Master Mode Baud Rate Divisor - bauddiv + * + * SPI baud rate = ref_clk / (2 * baud_rate_divisor) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_QSPI_CFG_BAUDDIV_E_BAUD2 | 0x0 | Baud Rate Div/2 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD4 | 0x1 | Baud Rate Div/4 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD6 | 0x2 | Baud Rate Div/6 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD8 | 0x3 | Baud Rate Div/8 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4 | Baud Rate Div/10 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5 | Baud Rate Div/12 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6 | Baud Rate Div/14 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7 | Baud Rate Div/16 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8 | Baud Rate Div/18 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9 | Baud Rate Div/20 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa | Baud Rate Div/22 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb | Baud Rate Div/24 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc | Baud Rate Div/26 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd | Baud Rate Div/28 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe | Baud Rate Div/30 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf | Baud Rate Div/32 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/2 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/4 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/6 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/8 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/10 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/12 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/14 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/16 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/18 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/20 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/22 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/24 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/26 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/28 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/30 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/32 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_MSB 22 +/* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_WIDTH 4 +/* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */ +#define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000 +/* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */ +#define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff +/* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_RESET 0xf +/* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */ +#define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19) +/* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000) + +/* + * Field : Serial interface and QSPI pipeline is IDLE - idle + * + * This is a STATUS read-only bit. Note this is a retimed signal, so there will be + * some inherent delay on the generation of this status signal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------- + * ALT_QSPI_CFG_IDLE_E_SET | 0x1 | Idle Mode + * ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0 | Non-Idle Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_IDLE + * + * Idle Mode + */ +#define ALT_QSPI_CFG_IDLE_E_SET 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_IDLE + * + * Non-Idle Mode + */ +#define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_MSB 31 +/* The width in bits of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */ +#define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */ +#define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */ +#define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_CFG. + */ +struct ALT_QSPI_CFG_s +{ + uint32_t en : 1; /* QSPI Enable */ + uint32_t selclkpol : 1; /* Clock Polarity */ + uint32_t selclkphase : 1; /* Select Clock Phase */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t endiracc : 1; /* Enable Direct Access Controller */ + uint32_t enlegacyip : 1; /* Legacy IP Mode Enable */ + uint32_t perseldec : 1; /* Peripheral select decode */ + uint32_t percslines : 4; /* Peripheral Chip Select Lines */ + uint32_t wp : 1; /* Write Protect Flash Pin */ + uint32_t endma : 1; /* Enable DMA Peripheral Interface */ + uint32_t enahbremap : 1; /* Enable AHB Address Re-mapping */ + uint32_t enterxipnextrd : 1; /* Enter XIP Mode on next READ */ + uint32_t enterxipimm : 1; /* Enter XIP Mode Immediately */ + uint32_t bauddiv : 4; /* Master Mode Baud Rate Divisor */ + uint32_t : 8; /* *UNDEFINED* */ + const uint32_t idle : 1; /* Serial interface and QSPI pipeline is IDLE */ +}; + +/* The typedef declaration for register ALT_QSPI_CFG. */ +typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */ +#define ALT_QSPI_CFG_OFST 0x0 + +/* + * Register : Device Read Instruction Register - devrd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [7:0] | RW | 0x3 | Read Opcode in non-XIP mode + * [9:8] | RW | 0x0 | Instruction Transfer Width + * [11:10] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | Address Transfer Width + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [17:16] | RW | 0x0 | Data Transfer Width + * [19:18] | ??? | 0x0 | *UNDEFINED* + * [20] | RW | 0x0 | Mode Bit Enable + * [23:21] | ??? | 0x0 | *UNDEFINED* + * [28:24] | RW | 0x0 | Dummy Read Clock Cycles + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Read Opcode in non-XIP mode - rdopcode + * + * Read Opcode to use when not in XIP mode + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_QSPI_DEVRD_RDOPCODE_E_RD | 0x3 | Read Opcode in Non-XIP mode + * ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD | 0xb | Fast Read in Non-XIP mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE + * + * Read Opcode in Non-XIP mode + */ +#define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE + * + * Fast Read in Non-XIP mode + */ +#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_MSB 7 +/* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */ +#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */ +#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3 +/* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */ +#define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Instruction Transfer Width - instwidth + * + * Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions + * sent to SPI flash device (not just read instructions). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0 | Instruction transferred on DQ0. Supported by all + * : | | SPI flash devices. + * ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL | 0x1 | Instruction transferred on DQ0 and DQ1. + * : | | Supported by all SPI flash devices that support + * : | | the Dual SP (DIO-SPI) Protocol. + * ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD | 0x2 | Instruction transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by all SPI flash devices that + * : | | support the Quad SP (QIO-SPI) Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0. Supported by all SPI flash devices. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that + * support the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash + * devices that support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9 +/* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300 +/* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff +/* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : Address Transfer Width - addrwidth + * + * Sets read address transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0 | Read address transferred on DQ0. Supported by + * : | | all SPI flash devices + * ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by some SPI flash devices that + * : | | support the Extended SPI Protocol and by all SPI + * : | | flash devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices + * that support the Extended SPI Protocol and by all SPI flash devices that support + * the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13 +/* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000 +/* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff +/* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Data Transfer Width - datawidth + * + * Sets read data transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0 | Read data transferred on DQ0. Supported by all + * : | | SPI flash devices + * ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported + * : | | by some SPI flash devices that support the + * : | | Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that + * support the Extended SPI Protocol and by all SPI flash devices that support the + * Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17 +/* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Mode Bit Enable - enmodebits + * + * If this bit is set, the mode bits as defined in the Mode Bit Configuration + * register are sent following the address bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------- + * ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER | 0x0 | No Order + * ALT_QSPI_DEVRD_ENMODBITS_E_ORDER | 0x1 | Mode Bits follow address bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS + * + * No Order + */ +#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS + * + * Mode Bits follow address bytes + */ +#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_MSB 20 +/* The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1 +/* The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value. */ +#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000 +/* The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value. */ +#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff +/* The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register. */ +#define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Dummy Read Clock Cycles - dummyrdclks + * + * Number of dummy clock cycles required by device for read instruction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28 +/* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000 +/* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff +/* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24) +/* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVRD. + */ +struct ALT_QSPI_DEVRD_s +{ + uint32_t rdopcode : 8; /* Read Opcode in non-XIP mode */ + uint32_t instwidth : 2; /* Instruction Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t addrwidth : 2; /* Address Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t datawidth : 2; /* Data Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t enmodebits : 1; /* Mode Bit Enable */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t dummyrdclks : 5; /* Dummy Read Clock Cycles */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVRD. */ +typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */ +#define ALT_QSPI_DEVRD_OFST 0x4 + +/* + * Register : Device Write Instruction Register - devwr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [7:0] | RW | 0x2 | Write Opcode + * [11:8] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | Address Transfer Width + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [17:16] | RW | 0x0 | Data Transfer Width + * [23:18] | ??? | 0x0 | *UNDEFINED* + * [28:24] | RW | 0x0 | Dummy Write Clock Cycles + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write Opcode - wropcode + * + * Write Opcode + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_MSB 7 +/* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */ +#define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */ +#define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2 +/* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */ +#define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Address Transfer Width - addrwidth + * + * Sets write address transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0 | Write address transferred on DQ0. Supported by + * : | | all SPI flash devices + * ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by some SPI flash devices that + * : | | support the Extended SPI Protocol and by all SPI + * : | | flash devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Write address transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices + * that support the Extended SPI Protocol and by all SPI flash devices that support + * the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13 +/* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000 +/* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff +/* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Data Transfer Width - datawidth + * + * Sets write data transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0 | Write data transferred on DQ0. Supported by all + * : | | SPI flash devices + * ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported + * : | | by some SPI flash devices that support the + * : | | Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Write data transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that + * support the Extended SPI Protocol and by all SPI flash devices that support the + * Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17 +/* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Dummy Write Clock Cycles - dummywrclks + * + * Number of dummy clock cycles required by device for write instruction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28 +/* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000 +/* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff +/* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24) +/* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVWR. + */ +struct ALT_QSPI_DEVWR_s +{ + uint32_t wropcode : 8; /* Write Opcode */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t addrwidth : 2; /* Address Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t datawidth : 2; /* Data Transfer Width */ + uint32_t : 6; /* *UNDEFINED* */ + uint32_t dummywrclks : 5; /* Dummy Write Clock Cycles */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVWR. */ +typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */ +#define ALT_QSPI_DEVWR_OFST 0x8 + +/* + * Register : QSPI Device Delay Register - delay + * + * This register is used to introduce relative delays into the generation of the + * master output signals. All timings are defined in cycles of the qspi_clk. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------- + * [7:0] | RW | 0x0 | Clock Delay with qspi_n_ss_out + * [15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit + * [23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation + * [31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert + * + */ +/* + * Field : Clock Delay with qspi_n_ss_out - init + * + * Delay in master reference clocks between setting qspi_n_ss_out low and first bit + * transfer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_MSB 7 +/* The width in bits of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */ +#define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */ +#define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */ +#define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Clock Delay for Last Transaction Bit - after + * + * Delay in master reference clocks between last bit of current transaction and + * deasserting the device chip select (qspi_n_ss_out). By default, the chip select + * will be deasserted on the cycle following the completion of the current + * transaction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_MSB 15 +/* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */ +#define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */ +#define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff +/* The reset value of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */ +#define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Clock Delay for Chip Select Deactivation - btwn + * + * Delay in master reference clocks between one chip select being de-activated and + * the activation of another. This is used to ensure a quiet period between the + * selection of two different slaves and requires the transmit FIFO to be empty. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_MSB 23 +/* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */ +#define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */ +#define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff +/* The reset value of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */ +#define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000) + +/* + * Field : Clock Delay for Chip Select Deassert - nss + * + * Delay in master reference clocks for the length that the master mode chip select + * outputs are de-asserted between transactions. The minimum delay is always + * qspi_sck_out period to ensure the chip select is never re-asserted within an + * qspi_sck_out period. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_MSB 31 +/* The width in bits of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */ +#define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000 +/* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */ +#define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff +/* The reset value of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */ +#define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DELAY. + */ +struct ALT_QSPI_DELAY_s +{ + uint32_t init : 8; /* Clock Delay with qspi_n_ss_out */ + uint32_t after : 8; /* Clock Delay for Last Transaction Bit */ + uint32_t btwn : 8; /* Clock Delay for Chip Select Deactivation */ + uint32_t nss : 8; /* Clock Delay for Chip Select Deassert */ +}; + +/* The typedef declaration for register ALT_QSPI_DELAY. */ +typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */ +#define ALT_QSPI_DELAY_OFST 0xc + +/* + * Register : Read Data Capture Register - rddatacap + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | RW | 0x1 | Bypass + * [4:1] | RW | 0x0 | Read Delay + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bypass - byp + * + * Controls bypass of the adapted loopback clock circuit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------ + * ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x0 | No Bypass + * ALT_QSPI_RDDATACAP_BYP_E_BYPASS | 0x1 | Bypass loopback clock circuit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP + * + * No Bypass + */ +#define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0 +/* + * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP + * + * Bypass loopback clock circuit + */ +#define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_MSB 0 +/* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_WIDTH 1 +/* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */ +#define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */ +#define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_RESET 0x1 +/* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */ +#define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */ +#define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Read Delay - delay + * + * Delay the read data capturing logic by the programmed number of qspi_clk cycles + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_MSB 4 +/* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4 +/* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */ +#define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e +/* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */ +#define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1 +/* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0 +/* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */ +#define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1) +/* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */ +#define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_RDDATACAP. + */ +struct ALT_QSPI_RDDATACAP_s +{ + uint32_t byp : 1; /* Bypass */ + uint32_t delay : 4; /* Read Delay */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_RDDATACAP. */ +typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */ +#define ALT_QSPI_RDDATACAP_OFST 0x10 + +/* + * Register : Device Size Register - devsz + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [3:0] | RW | 0x2 | Number of address Bytes + * [15:4] | RW | 0x100 | Number of Bytes per Device Page + * [20:16] | RW | 0x10 | Number of Bytes per Block + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Number of address Bytes - numaddrbytes + * + * Number of address bytes. A value of 0 indicates 1 byte. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3 +/* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2 +/* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Number of Bytes per Device Page - bytesperdevicepage + * + * Number of bytes per device page. This is required by the controller for + * performing FLASH writes up to and across page boundaries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15 +/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12 +/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0 +/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f +/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100 +/* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4) +/* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0) + +/* + * Field : Number of Bytes per Block - bytespersubsector + * + * Number of bytes per Block. This is required by the controller for performing the + * write protection logic. The number of bytes per block must be a power of 2 + * number. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20 +/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000 +/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff +/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10 +/* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16) +/* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVSZ. + */ +struct ALT_QSPI_DEVSZ_s +{ + uint32_t numaddrbytes : 4; /* Number of address Bytes */ + uint32_t bytesperdevicepage : 12; /* Number of Bytes per Device Page */ + uint32_t bytespersubsector : 5; /* Number of Bytes per Block */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVSZ. */ +typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */ +#define ALT_QSPI_DEVSZ_OFST 0x14 + +/* + * Register : SRAM Partition Register - srampart + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [6:0] | RW | 0x40 | Indirect Read Partition Size + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Indirect Read Partition Size - addr + * + * Defines the size of the indirect read partition in the SRAM, in units of SRAM + * locations. By default, half of the SRAM is reserved for indirect read operations + * and half for indirect write operations. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_MSB 6 +/* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_WIDTH 7 +/* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */ +#define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */ +#define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_RESET 0x40 +/* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */ +#define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_SRAMPART. + */ +struct ALT_QSPI_SRAMPART_s +{ + uint32_t addr : 7; /* Indirect Read Partition Size */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_SRAMPART. */ +typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */ +#define ALT_QSPI_SRAMPART_OFST 0x18 + +/* + * Register : Indirect AHB Address Trigger Register - indaddrtrig + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Trigger Address + * + */ +/* + * Field : Trigger Address - addr + * + * This is the base address that will be used by the AHB controller. When the + * incoming AHB read access address matches a range of addresses from this trigger + * address to the trigger address + 15, then the AHB request will be completed by + * fetching data from the Indirect Controllers SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDADDRTRIG. + */ +struct ALT_QSPI_INDADDRTRIG_s +{ + uint32_t addr : 32; /* Trigger Address */ +}; + +/* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */ +typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */ +#define ALT_QSPI_INDADDRTRIG_OFST 0x1c + +/* + * Register : DMA Peripheral Register - dmaper + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [3:0] | RW | 0x0 | Number of Single Bytes + * [7:4] | ??? | 0x0 | *UNDEFINED* + * [11:8] | RW | 0x0 | Number of Burst Bytes + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Number of Single Bytes - numsglreqbytes + * + * Number of bytes in a single type request on the DMA peripheral request. A + * programmed value of 0 represents a single byte. This should be setup before + * starting the indirect read or write operation. The actual number of bytes used + * is 2**(value in this register) which will simplify implementation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3 +/* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Number of Burst Bytes - numburstreqbytes + * + * Number of bytes in a burst type request on the DMA peripheral request. A + * programmed value of 0 represents a single byte. This should be setup before + * starting the indirect read or write operation. The actual number of bytes used + * is 2**(value in this register) which will simplify implementation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11 +/* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00 +/* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff +/* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8) +/* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DMAPER. + */ +struct ALT_QSPI_DMAPER_s +{ + uint32_t numsglreqbytes : 4; /* Number of Single Bytes */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t numburstreqbytes : 4; /* Number of Burst Bytes */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DMAPER. */ +typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */ +#define ALT_QSPI_DMAPER_OFST 0x20 + +/* + * Register : Remap Address Register - remapaddr + * + * This register is used to remap an incoming AHB address to a different address + * used by the FLASH device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | RW | 0x0 | Remap Address Offset + * + */ +/* + * Field : Remap Address Offset - value + * + * This offset is added to the incoming AHB address to determine the address used + * by the FLASH device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */ +#define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */ +#define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */ +#define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_REMAPADDR. + */ +struct ALT_QSPI_REMAPADDR_s +{ + uint32_t value : 32; /* Remap Address Offset */ +}; + +/* The typedef declaration for register ALT_QSPI_REMAPADDR. */ +typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */ +#define ALT_QSPI_REMAPADDR_OFST 0x24 + +/* + * Register : Mode Bit Register - modebit + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Mode + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mode - mode + * + * These are the 8 mode bits that are sent to the device following the address + * bytes if mode bit transmission has been enabled. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_MSB 7 +/* The width in bits of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_WIDTH 8 +/* The mask used to set the ALT_QSPI_MODBIT_MOD register field value. */ +#define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_MODBIT_MOD register field value. */ +#define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_RESET 0x0 +/* Extracts the ALT_QSPI_MODBIT_MOD field value from a register. */ +#define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_MODBIT_MOD register field value suitable for setting the register. */ +#define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_MODBIT. + */ +struct ALT_QSPI_MODBIT_s +{ + uint32_t mode : 8; /* Mode */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_MODBIT. */ +typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_MODBIT register from the beginning of the component. */ +#define ALT_QSPI_MODBIT_OFST 0x28 + +/* + * Register : SRAM Fill Register - sramfill + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------------------------- + * [15:0] | R | 0x0 | SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS + * [31:16] | R | 0x0 | SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS + * + */ +/* + * Field : SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS - indrdpart + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15 +/* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16 +/* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000 +/* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0 +/* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS - indwrpart + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31 +/* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16 +/* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff +/* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0 +/* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_SRAMFILL. + */ +struct ALT_QSPI_SRAMFILL_s +{ + const uint32_t indrdpart : 16; /* SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS */ + const uint32_t indwrpart : 16; /* SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS */ +}; + +/* The typedef declaration for register ALT_QSPI_SRAMFILL. */ +typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */ +#define ALT_QSPI_SRAMFILL_OFST 0x2c + +/* + * Register : TX Threshold Register - txthresh + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x1 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Defines the level at which the transmit FIFO not full interrupt is generated + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_MSB 3 +/* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4 +/* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1 +/* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */ +#define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_TXTHRESH. + */ +struct ALT_QSPI_TXTHRESH_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_TXTHRESH. */ +typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */ +#define ALT_QSPI_TXTHRESH_OFST 0x30 + +/* + * Register : RX Threshold Register - rxthresh + * + * Device Instruction Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x1 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Defines the level at which the receive FIFO not empty interrupt is generated + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_MSB 3 +/* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4 +/* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1 +/* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */ +#define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_RXTHRESH. + */ +struct ALT_QSPI_RXTHRESH_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_RXTHRESH. */ +typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */ +#define ALT_QSPI_RXTHRESH_OFST 0x34 + +/* + * Register : Interrupt Status Register - irqstat + * + * The status fields in this register are set when the described event occurs and + * the interrupt is enabled in the mask register. When any of these bit fields are + * set, the interrupt output is asserted high. The fields are each cleared by + * writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when + * legacy SPI mode is active. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Underflow Detected + * [2] | RW | 0x0 | Indirect Operation Complete + * [3] | RW | 0x0 | Indirect Read Reject + * [4] | RW | 0x0 | Protected Area Write Attempt + * [5] | RW | 0x0 | Illegal AHB Access Detected + * [6] | RW | 0x0 | Transfer Watermark Reached + * [7] | RW | 0x0 | Receive Overflow + * [8] | RW | 0x1 | Transmit FIFO Compared to Threshold + * [9] | RW | 0x0 | Transmit FIFO Full + * [10] | RW | 0x0 | Receive FIFO Compared to Threshold + * [11] | RW | 0x0 | Receive FIFO Full + * [12] | RW | 0x0 | Indirect Read Partition overflow + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Underflow Detected - underflowdet + * + * An underflow is detected when an attempt to transfer data is made when the + * transmit FIFO is empty. This may occur when the AHB write data is being supplied + * too slowly to keep up with the requested write operation. This bit is reset only + * by a system reset and cleared only when the register is read. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW | 0x1 | Underflow + * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0 | No Underflow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET + * + * Underflow + */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET + * + * No Underflow + */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1 +/* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Operation Complete - indopdone + * + * Controller has completed last triggered indirect operation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP | 0x1 | Completed Indirect Operation + * ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0 | No Indirect Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE + * + * Completed Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE + * + * No Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Indirect Read Reject - indrdreject + * + * Indirect operation was requested but could not be accepted. Two indirect + * operations already in storage. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ | 0x1 | Indirect Operation Requested + * ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0 | No Indirect Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT + * + * Indirect Operation Requested + */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT + * + * No Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Protected Area Write Attempt - protwrattempt + * + * Write to protected area was attempted and rejected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------- + * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT | 0x1 | Write Attempt to protected area + * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT | 0x0 | No Write Attempt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT + * + * Write Attempt to protected area + */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT + * + * No Write Attempt + */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4 +/* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Illegal AHB Access Detected - illegalacc + * + * Illegal AHB access has been detected. AHB wrapping bursts and the use of + * SPLIT/RETRY accesses will cause this error interrupt to trigger. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB | 0x1 | Illegal AHB attempt + * ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0 | No Illegal AHB attempt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC + * + * Illegal AHB attempt + */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC + * + * No Illegal AHB attempt + */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5 +/* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transfer Watermark Reached - indxfrlvl + * + * Indirect Transfer Watermark Level Reached + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL | 0x1 | Water level reached + * ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0 | No water level reached + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL + * + * Water level reached + */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL + * + * No water level reached + */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Overflow - rxover + * + * This should only occur in Legacy SPI mode. Set if an attempt is made to push the + * RX FIFO when it is full. This bit is reset only by a system reset and cleared + * only when this register is read. If a new push to the RX FIFO occurs coincident + * with a register read this flag will remain set. 0 : no overflow has been + * detected. 1 : an overflow has occurred. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER | 0x1 | Receive Overflow + * ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0 | No Receive Overflow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER + * + * Receive Overflow + */ +#define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER + * + * No Receive Overflow + */ +#define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_MSB 7 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */ +#define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */ +#define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit FIFO Compared to Threshold - txthreshcmp + * + * Indicates the number of entries in the transmit FIFO with respect to the + * threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0 | FIFO has > TXTHRESH entries + * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1 | FIFO has <= TXTHRESH entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP + * + * FIFO has > TXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP + * + * FIFO has <= TXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8 +/* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1 +/* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Transmit FIFO Full - txfull + * + * Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy + * mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0 | Transmit FIFO Not Full + * ALT_QSPI_IRQSTAT_TXFULL_E_FULL | 0x1 | Transmit FIFO Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL + * + * Transmit FIFO Not Full + */ +#define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL + * + * Transmit FIFO Full + */ +#define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_MSB 9 +/* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive FIFO Compared to Threshold - rxthreshcmp + * + * Indicates the number of entries in the receive FIFO with respect to the + * threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0 | FIFO has <= RXTHRESH entries + * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1 | FIFO has > RXTHRESH entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP + * + * FIFO has <= RXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP + * + * FIFO has > RXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Receive FIFO Full - rxfull + * + * Indicates that the receive FIFO is full or not. Only relevant in SPI legacy + * mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------- + * ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0 | Receive FIFO Not Full + * ALT_QSPI_IRQSTAT_RXFULL_E_FULL | 0x1 | Receive FIFO Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL + * + * Receive FIFO Not Full + */ +#define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL + * + * Receive FIFO Full + */ +#define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_MSB 11 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Indirect Read Partition overflow - indsramfull + * + * Indirect Read Partition of SRAM is full and unable to immediately complete + * indirect operation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------- + * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL | 0x1 | SRAM is full + * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0 | SRAM is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL + * + * SRAM is full + */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL + * + * SRAM is not full + */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff +/* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_IRQSTAT. + */ +struct ALT_QSPI_IRQSTAT_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t underflowdet : 1; /* Underflow Detected */ + uint32_t indopdone : 1; /* Indirect Operation Complete */ + uint32_t indrdreject : 1; /* Indirect Read Reject */ + uint32_t protwrattempt : 1; /* Protected Area Write Attempt */ + uint32_t illegalacc : 1; /* Illegal AHB Access Detected */ + uint32_t indxfrlvl : 1; /* Transfer Watermark Reached */ + uint32_t rxover : 1; /* Receive Overflow */ + uint32_t txthreshcmp : 1; /* Transmit FIFO Compared to Threshold */ + uint32_t txfull : 1; /* Transmit FIFO Full */ + uint32_t rxthreshcmp : 1; /* Receive FIFO Compared to Threshold */ + uint32_t rxfull : 1; /* Receive FIFO Full */ + uint32_t indsramfull : 1; /* Indirect Read Partition overflow */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_IRQSTAT. */ +typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */ +#define ALT_QSPI_IRQSTAT_OFST 0x40 + +/* + * Register : Interrupt Mask - irqmask + * + * If disabled, the interrupt for the corresponding interrupt status register bit + * is disabled. If enabled, the interrupt for the corresponding interrupt status + * register bit is enabled. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Underflow Detected Mask + * [2] | RW | 0x0 | Mask + * [3] | RW | 0x0 | Indirect Read Reject Mask + * [4] | RW | 0x0 | Protected Area Write Attempt Mask + * [5] | RW | 0x0 | Illegal Access Detected Mask + * [6] | RW | 0x0 | Transfer Watermark Breach Mask + * [7] | RW | 0x0 | Receive Overflow Mask + * [8] | RW | 0x0 | Transmit FIFO Threshold Compare Mask + * [9] | RW | 0x0 | Transmit FIFO Full Mask + * [10] | RW | 0x0 | Receive FIFO Threshold Compare Mask + * [11] | RW | 0x0 | Receive FIFO full Mask + * [12] | RW | 0x0 | Indirect Read Partition overflow mask + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Underflow Detected Mask - underflowdet + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1 +/* The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Mask - indopdone + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDOPDONE_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDOPDONE_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2 +/* The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Indirect Read Reject Mask - indrdreject + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDRDREJECT_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3 +/* The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Protected Area Write Attempt Mask - protwrattempt + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4 +/* The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Illegal Access Detected Mask - illegalacc + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_ILLEGALACC_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5 +/* The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transfer Watermark Breach Mask - indxfrlvl + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDXFRLVL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6 +/* The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Overflow Mask - rxover + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXOVER_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXOVER_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_MSB 7 +/* The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value. */ +#define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value. */ +#define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register. */ +#define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit FIFO Threshold Compare Mask - txthreshcmp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8 +/* The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Transmit FIFO Full Mask - txfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_TXFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_TXFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_MSB 9 +/* The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value. */ +#define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value. */ +#define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive FIFO Threshold Compare Mask - rxthreshcmp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10 +/* The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Receive FIFO full Mask - rxfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_MSB 11 +/* The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value. */ +#define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value. */ +#define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Indirect Read Partition overflow mask - indsramfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDSRAMFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12 +/* The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff +/* The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_IRQMSK. + */ +struct ALT_QSPI_IRQMSK_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t underflowdet : 1; /* Underflow Detected Mask */ + uint32_t indopdone : 1; /* Mask */ + uint32_t indrdreject : 1; /* Indirect Read Reject Mask */ + uint32_t protwrattempt : 1; /* Protected Area Write Attempt Mask */ + uint32_t illegalacc : 1; /* Illegal Access Detected Mask */ + uint32_t indxfrlvl : 1; /* Transfer Watermark Breach Mask */ + uint32_t rxover : 1; /* Receive Overflow Mask */ + uint32_t txthreshcmp : 1; /* Transmit FIFO Threshold Compare Mask */ + uint32_t txfull : 1; /* Transmit FIFO Full Mask */ + uint32_t rxthreshcmp : 1; /* Receive FIFO Threshold Compare Mask */ + uint32_t rxfull : 1; /* Receive FIFO full Mask */ + uint32_t indsramfull : 1; /* Indirect Read Partition overflow mask */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_IRQMSK. */ +typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component. */ +#define ALT_QSPI_IRQMSK_OFST 0x44 + +/* + * Register : Lower Write Protection Register - lowwrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | RW | 0x0 | Block Number + * + */ +/* + * Field : Block Number - subsector + * + * The block number that defines the lower block in the range of blocks that is to + * be locked from writing. The definition of a block in terms of number of bytes is + * programmable via the Device Size Configuration register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31 +/* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32 +/* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0 +/* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_LOWWRPROT. + */ +struct ALT_QSPI_LOWWRPROT_s +{ + uint32_t subsector : 32; /* Block Number */ +}; + +/* The typedef declaration for register ALT_QSPI_LOWWRPROT. */ +typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */ +#define ALT_QSPI_LOWWRPROT_OFST 0x50 + +/* + * Register : Upper Write Protection Register - uppwrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | RW | 0x0 | Block Number + * + */ +/* + * Field : Block Number - subsector + * + * The block number that defines the upper block in the range of blocks that is to + * be locked from writing. The definition of a block in terms of number of bytes is + * programmable via the Device Size Configuration register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31 +/* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32 +/* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0 +/* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_UPPWRPROT. + */ +struct ALT_QSPI_UPPWRPROT_s +{ + uint32_t subsector : 32; /* Block Number */ +}; + +/* The typedef declaration for register ALT_QSPI_UPPWRPROT. */ +typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */ +#define ALT_QSPI_UPPWRPROT_OFST 0x54 + +/* + * Register : Write Protection Register - wrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | RW | 0x0 | Write Protection Inversion Bit + * [1] | RW | 0x0 | Write Protection Enable Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write Protection Inversion Bit - inv + * + * When enabled, the protection region defined in the lower and upper write + * protection registers is inverted meaning it is the region that the system is + * permitted to write to. When disabled, the protection region defined in the lower + * and upper write protection registers is the region that the system is not + * permitted to write to. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------- + * ALT_QSPI_WRPROT_INV_E_EN | 0x1 | Write Region allowed + * ALT_QSPI_WRPROT_INV_E_DIS | 0x0 | Write Region not allowed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_WRPROT_INV + * + * Write Region allowed + */ +#define ALT_QSPI_WRPROT_INV_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_WRPROT_INV + * + * Write Region not allowed + */ +#define ALT_QSPI_WRPROT_INV_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_MSB 0 +/* The width in bits of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_WIDTH 1 +/* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */ +#define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */ +#define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_RESET 0x0 +/* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */ +#define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */ +#define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Write Protection Enable Bit - en + * + * When enabled, any AHB write access with an address within the protection region + * defined in the lower and upper write protection registers is rejected. An AHB + * error response is generated and an interrupt source triggered. When disabled, + * the protection region is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:--------------------------- + * ALT_QSPI_WRPROT_EN_E_EN | 0x1 | AHB Write Access rejected + * ALT_QSPI_WRPROT_EN_E_DIS | 0x0 | Protection Region Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_WRPROT_EN + * + * AHB Write Access rejected + */ +#define ALT_QSPI_WRPROT_EN_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_WRPROT_EN + * + * Protection Region Disabled + */ +#define ALT_QSPI_WRPROT_EN_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_MSB 1 +/* The width in bits of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_WIDTH 1 +/* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */ +#define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */ +#define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_RESET 0x0 +/* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */ +#define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */ +#define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_WRPROT. + */ +struct ALT_QSPI_WRPROT_s +{ + uint32_t inv : 1; /* Write Protection Inversion Bit */ + uint32_t en : 1; /* Write Protection Enable Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_WRPROT. */ +typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */ +#define ALT_QSPI_WRPROT_OFST 0x58 + +/* + * Register : Indirect Read Transfer Register - indrd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------------- + * [0] | RW | 0x0 | Start Indirect Read + * [1] | RW | 0x0 | Cancel Indirect Read + * [2] | R | Unknown | Indirect Read Status + * [3] | RW | Unknown | SRAM Full + * [4] | R | Unknown | Queued Indirect Read Operations + * [5] | RW | Unknown | Indirect Completion Status + * [7:6] | R | Unknown | Completed Indirect Operations + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Indirect Read - start + * + * When this bit is enabled, it will trigger an indirect read operation. The + * assumption is that the indirect start address and the indirect number of bytes + * register is setup before triggering the indirect read operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------- + * ALT_QSPI_INDRD_START_E_END | 0x1 | Trigger Indirect Read + * ALT_QSPI_INDRD_START_E_DISD | 0x0 | No Indirect Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_START + * + * Trigger Indirect Read + */ +#define ALT_QSPI_INDRD_START_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_START + * + * No Indirect Read + */ +#define ALT_QSPI_INDRD_START_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_MSB 0 +/* The width in bits of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_START register field value. */ +#define ALT_QSPI_INDRD_START_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_INDRD_START register field value. */ +#define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_START field value from a register. */ +#define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Cancel Indirect Read - cancel + * + * This bit will cancel all ongoing indirect read operations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_QSPI_INDRD_CANCEL_E_CANCEL | 0x1 | Cancel Indirect Read + * ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0 | Do Not Cancel Indirect Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_CANCEL + * + * Cancel Indirect Read + */ +#define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_CANCEL + * + * Do Not Cancel Indirect Read + */ +#define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_MSB 1 +/* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */ +#define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */ +#define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */ +#define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Read Status - rd_status + * + * Indirect read operation in progress (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------ + * ALT_QSPI_INDRD_RD_STAT_E_RDOP | 0x1 | Read Operation in progress + * ALT_QSPI_INDRD_RD_STAT_E_NOACTION | 0x0 | No read operation in progress + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT + * + * Read Operation in progress + */ +#define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT + * + * No read operation in progress + */ +#define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_MSB 2 +/* The width in bits of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value. */ +#define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value. */ +#define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_INDRD_RD_STAT register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_RD_STAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register. */ +#define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SRAM Full - sram_full + * + * SRAM full and unable to immediately complete an indirect operation. Write a 1 to + * this field to clear it. ; indirect operation (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------- + * ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1 | Sram Full- Cant complete operation + * ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0 | SRram Not Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL + * + * Sram Full- Cant complete operation + */ +#define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL + * + * SRram Not Full + */ +#define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_MSB 3 +/* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */ +#define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */ +#define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */ +#define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Queued Indirect Read Operations - rd_queued + * + * Two indirect read operations have been queued + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1 | Queued Indirect Read + * ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION | 0x0 | No Queued Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED + * + * Queued Indirect Read + */ +#define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED + * + * No Queued Read + */ +#define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_MSB 4 +/* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */ +#define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */ +#define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */ +#define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Indirect Completion Status - ind_ops_done_status + * + * This field is set to 1 when an indirect operation has completed. Write a 1 to + * this field to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------- + * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP | 0x1 | Indirect Op Complete operation + * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION | 0x0 | Indirect Op Not Complete + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT + * + * Indirect Op Complete operation + */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT + * + * Indirect Op Not Complete + */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5 +/* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Completed Indirect Operations - num_ind_ops_done + * + * This field contains the number of indirect operations which have been completed. + * This is used in conjunction with the indirect completion status field (bit 5). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7 +/* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2 +/* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f +/* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRD. + */ +struct ALT_QSPI_INDRD_s +{ + uint32_t start : 1; /* Start Indirect Read */ + uint32_t cancel : 1; /* Cancel Indirect Read */ + const uint32_t rd_status : 1; /* Indirect Read Status */ + uint32_t sram_full : 1; /* SRAM Full */ + const uint32_t rd_queued : 1; /* Queued Indirect Read Operations */ + uint32_t ind_ops_done_status : 1; /* Indirect Completion Status */ + const uint32_t num_ind_ops_done : 2; /* Completed Indirect Operations */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRD. */ +typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */ +#define ALT_QSPI_INDRD_OFST 0x60 + +/* + * Register : Indirect Read Transfer Watermark Register - indrdwater + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Watermark Value + * + */ +/* + * Field : Watermark Value - level + * + * This represents the minimum fill level of the SRAM before a DMA peripheral + * access is permitted. When the SRAM fill level passes the watermark, an interrupt + * is also generated. This field can be disabled by writing a value of all zeroes. + * The units of this register are BYTES + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */ +#define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */ +#define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */ +#define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDWATER. + */ +struct ALT_QSPI_INDRDWATER_s +{ + uint32_t level : 32; /* Watermark Value */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDWATER. */ +typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */ +#define ALT_QSPI_INDRDWATER_OFST 0x64 + +/* + * Register : Indirect Read Transfer Start Address Register - indrdstaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [31:0] | RW | 0x0 | Start Address of Indirect Access + * + */ +/* + * Field : Start Address of Indirect Access - addr + * + * This is the start address from which the indirect access will commence its READ + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDSTADDR. + */ +struct ALT_QSPI_INDRDSTADDR_s +{ + uint32_t addr : 32; /* Start Address of Indirect Access */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */ +typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */ +#define ALT_QSPI_INDRDSTADDR_OFST 0x68 + +/* + * Register : Indirect Read Transfer Number Bytes Register - indrdcnt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | RW | 0x0 | Indirect Count + * + */ +/* + * Field : Indirect Count - value + * + * This is the number of bytes that the indirect access will consume. This can be + * bigger than the configured size of SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */ +#define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */ +#define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */ +#define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDCNT. + */ +struct ALT_QSPI_INDRDCNT_s +{ + uint32_t value : 32; /* Indirect Count */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDCNT. */ +typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */ +#define ALT_QSPI_INDRDCNT_OFST 0x6c + +/* + * Register : Indirect Write Transfer Register - indwr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------------- + * [0] | RW | 0x0 | Start Indirect Write + * [1] | RW | 0x0 | Cancel Indirect Write + * [2] | R | Unknown | Indirect Write Status + * [3] | R | 0x0 | Reserved + * [4] | R | Unknown | Queued Indirect Write Operations + * [5] | RW | Unknown | Indirect Completion Status + * [7:6] | R | Unknown | Completed Indirect Operations + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Indirect Write - start + * + * Writing a 1 to this bit will trigger an indirect write operation. The assumption + * is that the indirect start address and the indirect number of bytes register is + * setup before triggering the indirect write operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------------- + * ALT_QSPI_INDWR_START_E_END | 0x1 | Trigger indirect write operation + * ALT_QSPI_INDWR_START_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_START + * + * Trigger indirect write operation + */ +#define ALT_QSPI_INDWR_START_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_START + * + * No Action + */ +#define ALT_QSPI_INDWR_START_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_MSB 0 +/* The width in bits of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_START register field value. */ +#define ALT_QSPI_INDWR_START_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_INDWR_START register field value. */ +#define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_START field value from a register. */ +#define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Cancel Indirect Write - cancel + * + * Writing a 1 to this bit will cancel all ongoing indirect write operations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1 | Cancel Indirect write operation + * ALT_QSPI_INDWR_CANCEL_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_CANCEL + * + * Cancel Indirect write operation + */ +#define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_CANCEL + * + * No Action + */ +#define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_MSB 1 +/* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */ +#define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */ +#define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */ +#define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Write Status - rdstat + * + * Indirect write operation in progress (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------- + * ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1 | Indirect write operation + * ALT_QSPI_INDWR_RDSTAT_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT + * + * Indirect write operation + */ +#define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT + * + * No Action + */ +#define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_MSB 2 +/* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */ +#define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */ +#define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_INDWR_RDSTAT register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_RDSTAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */ +#define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Reserved - sramfull + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_MSB 3 +/* The width in bits of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_SRAMFULL register field value. */ +#define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_INDWR_SRAMFULL register field value. */ +#define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_SRAMFULL field value from a register. */ +#define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_INDWR_SRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Queued Indirect Write Operations - rdqueued + * + * Two indirect write operations have been queued + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_INDWR_RDQUEUED_E_INDWROP | 0x1 | Two Indirect write operation + * ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED + * + * Two Indirect write operation + */ +#define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED + * + * No Action + */ +#define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_MSB 4 +/* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */ +#define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */ +#define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */ +#define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Indirect Completion Status - inddone + * + * This field is set to 1 when an indirect operation has completed. Write a 1 to + * this field to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1 | Indirect operation completed + * ALT_QSPI_INDWR_INDDONE_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_INDDONE + * + * Indirect operation completed + */ +#define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_INDDONE + * + * No Action + */ +#define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_MSB 5 +/* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */ +#define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */ +#define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_INDWR_INDDONE register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_INDDONE_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */ +#define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Completed Indirect Operations - indcnt + * + * This field contains the count of indirect operations which have been completed. + * This is used in conjunction with the indirect completion status field (bit 5). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_MSB 7 +/* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_WIDTH 2 +/* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */ +#define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */ +#define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f +/* The reset value of the ALT_QSPI_INDWR_INDCNT register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_INDCNT_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */ +#define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWR. + */ +struct ALT_QSPI_INDWR_s +{ + uint32_t start : 1; /* Start Indirect Write */ + uint32_t cancel : 1; /* Cancel Indirect Write */ + const uint32_t rdstat : 1; /* Indirect Write Status */ + const uint32_t sramfull : 1; /* Reserved */ + const uint32_t rdqueued : 1; /* Queued Indirect Write Operations */ + uint32_t inddone : 1; /* Indirect Completion Status */ + const uint32_t indcnt : 2; /* Completed Indirect Operations */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWR. */ +typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */ +#define ALT_QSPI_INDWR_OFST 0x70 + +/* + * Register : Indirect Write Transfer Watermark Register - indwrwater + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------- + * [31:0] | RW | 0xffffffff | Watermark Value + * + */ +/* + * Field : Watermark Value - level + * + * This represents the maximum fill level of the SRAM before a DMA peripheral + * access is permitted. When the SRAM fill level falls below the watermark, an + * interrupt is also generated. This field can be disabled by writing a value of + * all ones. The units of this register are bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */ +#define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */ +#define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff +/* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */ +#define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRWATER. + */ +struct ALT_QSPI_INDWRWATER_s +{ + uint32_t level : 32; /* Watermark Value */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRWATER. */ +typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */ +#define ALT_QSPI_INDWRWATER_OFST 0x74 + +/* + * Register : Indirect Write Transfer Start Address Register - indwrstaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [31:0] | RW | 0x0 | Start of Indirect Access + * + */ +/* + * Field : Start of Indirect Access - addr + * + * This is the start address from which the indirect access will commence its write + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRSTADDR. + */ +struct ALT_QSPI_INDWRSTADDR_s +{ + uint32_t addr : 32; /* Start of Indirect Access */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */ +typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */ +#define ALT_QSPI_INDWRSTADDR_OFST 0x78 + +/* + * Register : Indirect Write Transfer Count Register - indwrcnt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [31:0] | RW | 0x0 | Indirect Number of Bytes + * + */ +/* + * Field : Indirect Number of Bytes - value + * + * This is the number of bytes that the indirect access will consume. This can be + * bigger than the configured size of SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */ +#define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */ +#define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */ +#define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRCNT. + */ +struct ALT_QSPI_INDWRCNT_s +{ + uint32_t value : 32; /* Indirect Number of Bytes */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRCNT. */ +typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */ +#define ALT_QSPI_INDWRCNT_OFST 0x7c + +/* + * Register : Flash Command Register - flashcmd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Execute Command + * [1] | R | 0x0 | Command Execution Status + * [6:2] | ??? | 0x0 | *UNDEFINED* + * [11:7] | RW | 0x0 | Number of Dummy Bytes + * [14:12] | RW | 0x0 | Number of Write Data Bytes + * [15] | RW | 0x0 | Write Data Enable + * [17:16] | RW | 0x0 | Number of Address Bytes + * [18] | RW | 0x0 | Mode Bit Enable + * [19] | RW | 0x0 | Command Address Enable + * [22:20] | RW | 0x0 | Number of Read Data Bytes + * [23] | RW | 0x0 | Read Data Enable + * [31:24] | RW | 0x0 | Command Opcode + * + */ +/* + * Field : Execute Command - execcmd + * + * Execute the command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE | 0x1 | Execute Command + * ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD + * + * Execute Command + */ +#define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0 +/* The width in bits of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_EXECCMD field value from a register. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_FLSHCMD_EXECCMD register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Command Execution Status - cmdexecstat + * + * Command execution in progress. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------- + * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1 | Command Execution Status + * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT + * + * Command Execution Status + */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1 +/* The width in bits of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_CMDEXECSTAT field value from a register. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Number of Dummy Bytes - numdummybytes + * + * Set to the number of dummy bytes required This should be setup before triggering + * the command via the execute field of this register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f +/* The reset value of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7) +/* Produces a ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80) + +/* + * Field : Number of Write Data Bytes - numwrdatabytes + * + * Up to 8 Data bytes may be written using this command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0 | Write 1 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1 | Write 2 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2 | Write 3 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3 | Write 4 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4 | Write 5 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5 | Write 6 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6 | Write 7 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7 | Write 8 Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 1 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 2 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 3 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 4 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 5 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 6 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 7 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 8 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMWRDATABYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12) +/* Produces a ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000) + +/* + * Field : Write Data Enable - enwrdata + * + * Set to 1 if the command specified in the command opcode field requires write + * data bytes to be sent to the device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------- + * ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES | 0x1 | Command requires write data bytes + * ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA + * + * Command requires write data bytes + */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff +/* The reset value of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENWRDATA field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_QSPI_FLSHCMD_ENWRDATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Number of Address Bytes - numaddrbytes + * + * Set to the number of address bytes required (the address itself is programmed in + * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the + * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address + * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------- + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0 | Write 1 Address Byte + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1 | Write 2 Address Bytes + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2 | Write 3 Address Bytes + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3 | Write 4 Address Bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 1 Address Byte + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 2 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 3 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 4 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMADDRBYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Mode Bit Enable - enmodebit + * + * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration + * register are sent following the address bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------- + * ALT_QSPI_FLSHCMD_ENMODBIT_E_END | 0x1 | Mode Bit follows address bytes + * ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT + * + * Mode Bit follows address bytes + */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENMODBIT field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_QSPI_FLSHCMD_ENMODBIT register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Command Address Enable - encmdaddr + * + * If enabled, the command specified in bits 31:24 requires an address. This should + * be setup before triggering the command via writing a 1 to the execute field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:--------------------------------------- + * ALT_QSPI_FLSHCMD_ENCMDADDR_E_END | 0x1 | Command in bits 31:24 requires address + * ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR + * + * Command in bits 31:24 requires address + */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENCMDADDR field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_QSPI_FLSHCMD_ENCMDADDR register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Number of Read Data Bytes - numrddatabytes + * + * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for + * 8 bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0 | Read 1 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1 | Read 2 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2 | Read 3 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3 | Read 4 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4 | Read 5 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5 | Read 6 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6 | Read 7 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7 | Read 8 Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 1 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 2 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 3 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 4 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 5 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 6 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 7 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 8 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMRDDATABYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20) +/* Produces a ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000) + +/* + * Field : Read Data Enable - enrddata + * + * If enabled, the command specified in the command opcode field (bits 31:24) + * requires read data bytes to be received from the device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------- + * ALT_QSPI_FLSHCMD_ENRDDATA_E_EN | 0x1 | Command Requires read data + * ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA + * + * Command Requires read data + */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENRDDATA field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_QSPI_FLSHCMD_ENRDDATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Command Opcode - cmdopcode + * + * The command opcode field should be setup before triggering the command. For + * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of + * this register launches the command. NOTE : Using this approach to issue commands + * to the device will make use of the instruction type of the device instruction + * configuration register. If this field is set to 2'b00, then the command opcode, + * command address, command dummy bytes and command data will all be transferred in + * a serial fashion. If this field is set to 2'b01, then the command opcode, + * command address, command dummy bytes and command data will all be transferred in + * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command + * opcode, command address, command dummy bytes and command data will all be + * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff +/* The reset value of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_CMDOPCODE field value from a register. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_QSPI_FLSHCMD_CMDOPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMD. + */ +struct ALT_QSPI_FLSHCMD_s +{ + uint32_t execcmd : 1; /* Execute Command */ + const uint32_t cmdexecstat : 1; /* Command Execution Status */ + uint32_t : 5; /* *UNDEFINED* */ + uint32_t numdummybytes : 5; /* Number of Dummy Bytes */ + uint32_t numwrdatabytes : 3; /* Number of Write Data Bytes */ + uint32_t enwrdata : 1; /* Write Data Enable */ + uint32_t numaddrbytes : 2; /* Number of Address Bytes */ + uint32_t enmodebit : 1; /* Mode Bit Enable */ + uint32_t encmdaddr : 1; /* Command Address Enable */ + uint32_t numrddatabytes : 3; /* Number of Read Data Bytes */ + uint32_t enrddata : 1; /* Read Data Enable */ + uint32_t cmdopcode : 8; /* Command Opcode */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMD. */ +typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMD register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMD_OFST 0x90 + +/* + * Register : Flash Command Address Registers - flashcmdaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Command Address + * + */ +/* + * Field : Command Address - addr + * + * This should be setup before triggering the command with execute field (bit 0) of + * the Flash Command Control register. It is the address used by the command + * specified in the opcode field (bits 31:24) of the Flash Command Control + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDADDR_ADDR field value from a register. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDADDR. + */ +struct ALT_QSPI_FLSHCMDADDR_s +{ + uint32_t addr : 32; /* Command Address */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDADDR. */ +typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDADDR register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDADDR_OFST 0x94 + +/* + * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [31:0] | RW | 0x0 | Command Read Data (Lower byte) + * + */ +/* + * Field : Command Read Data (Lower byte) - data + * + * This is the data that is returned by the flash device for any status or + * configuration read operation carried out by triggering the event in the control + * register. The register will be valid when the polling bit in the control + * register is low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDRDDATALO_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDRDDATALO_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDRDDATALO. + */ +struct ALT_QSPI_FLSHCMDRDDATALO_s +{ + uint32_t data : 32; /* Command Read Data (Lower byte) */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATALO. */ +typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDRDDATALO register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0 + +/* + * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup + * + * Device Instruction Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [31:0] | RW | 0x0 | Command Read Data (Upper byte) + * + */ +/* + * Field : Command Read Data (Upper byte) - data + * + * This is the data that is returned by the FLASH device for any status or + * configuration read operation carried out by triggering the event in the control + * register. The register will be valid when the polling bit in the control + * register is low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDRDDATAUP_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDRDDATAUP. + */ +struct ALT_QSPI_FLSHCMDRDDATAUP_s +{ + uint32_t data : 32; /* Command Read Data (Upper byte) */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATAUP. */ +typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDRDDATAUP register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4 + +/* + * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | Command Write Data Lower Byte + * + */ +/* + * Field : Command Write Data Lower Byte - data + * + * This is the command write data lower byte. This should be setup before + * triggering the command with execute field (bit 0) of the Flash Command Control + * register. It is the data that is to be written to the flash for any status or + * configuration write operation carried out by triggering the event in the Flash + * Command Control register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDWRDATALO_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDWRDATALO_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDWRDATALO. + */ +struct ALT_QSPI_FLSHCMDWRDATALO_s +{ + uint32_t data : 32; /* Command Write Data Lower Byte */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATALO. */ +typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDWRDATALO register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8 + +/* + * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | ALT_QSPI_FLSHCMDWRDATAUP_DATA + * + */ +/* + * Field : data + * + * This is the command write data upper byte. This should be setup before + * triggering the command with execute field (bit 0) of the Flash Command Control + * register. It is the data that is to be written to the flash for any status or + * configuration write operation carried out by triggering the event in the Flash + * Command Control register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDWRDATAUP_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDWRDATAUP. + */ +struct ALT_QSPI_FLSHCMDWRDATAUP_s +{ + uint32_t data : 32; /* ALT_QSPI_FLSHCMDWRDATAUP_DATA */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATAUP. */ +typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDWRDATAUP register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac + +/* + * Register : Module ID Register - moduleid + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------- + * [24:0] | R | 0x1001 | Module ID number + * [31:25] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Module ID number - value + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_MSB 24 +/* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_WIDTH 25 +/* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */ +#define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff +/* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */ +#define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000 +/* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_RESET 0x1001 +/* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */ +#define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0) +/* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_MODULEID. + */ +struct ALT_QSPI_MODULEID_s +{ + const uint32_t value : 25; /* Module ID number */ + uint32_t : 7; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_MODULEID. */ +typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */ +#define ALT_QSPI_MODULEID_OFST 0xfc + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_QSPI. + */ +struct ALT_QSPI_s +{ + volatile ALT_QSPI_CFG_t cfg; /* ALT_QSPI_CFG */ + volatile ALT_QSPI_DEVRD_t devrd; /* ALT_QSPI_DEVRD */ + volatile ALT_QSPI_DEVWR_t devwr; /* ALT_QSPI_DEVWR */ + volatile ALT_QSPI_DELAY_t delay; /* ALT_QSPI_DELAY */ + volatile ALT_QSPI_RDDATACAP_t rddatacap; /* ALT_QSPI_RDDATACAP */ + volatile ALT_QSPI_DEVSZ_t devsz; /* ALT_QSPI_DEVSZ */ + volatile ALT_QSPI_SRAMPART_t srampart; /* ALT_QSPI_SRAMPART */ + volatile ALT_QSPI_INDADDRTRIG_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ + volatile ALT_QSPI_DMAPER_t dmaper; /* ALT_QSPI_DMAPER */ + volatile ALT_QSPI_REMAPADDR_t remapaddr; /* ALT_QSPI_REMAPADDR */ + volatile ALT_QSPI_MODBIT_t modebit; /* ALT_QSPI_MODBIT */ + volatile ALT_QSPI_SRAMFILL_t sramfill; /* ALT_QSPI_SRAMFILL */ + volatile ALT_QSPI_TXTHRESH_t txthresh; /* ALT_QSPI_TXTHRESH */ + volatile ALT_QSPI_RXTHRESH_t rxthresh; /* ALT_QSPI_RXTHRESH */ + volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_IRQSTAT_t irqstat; /* ALT_QSPI_IRQSTAT */ + volatile ALT_QSPI_IRQMSK_t irqmask; /* ALT_QSPI_IRQMSK */ + volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_LOWWRPROT_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ + volatile ALT_QSPI_UPPWRPROT_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ + volatile ALT_QSPI_WRPROT_t wrprot; /* ALT_QSPI_WRPROT */ + volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ + volatile ALT_QSPI_INDRD_t indrd; /* ALT_QSPI_INDRD */ + volatile ALT_QSPI_INDRDWATER_t indrdwater; /* ALT_QSPI_INDRDWATER */ + volatile ALT_QSPI_INDRDSTADDR_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ + volatile ALT_QSPI_INDRDCNT_t indrdcnt; /* ALT_QSPI_INDRDCNT */ + volatile ALT_QSPI_INDWR_t indwr; /* ALT_QSPI_INDWR */ + volatile ALT_QSPI_INDWRWATER_t indwrwater; /* ALT_QSPI_INDWRWATER */ + volatile ALT_QSPI_INDWRSTADDR_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ + volatile ALT_QSPI_INDWRCNT_t indwrcnt; /* ALT_QSPI_INDWRCNT */ + volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ + volatile ALT_QSPI_FLSHCMD_t flashcmd; /* ALT_QSPI_FLSHCMD */ + volatile ALT_QSPI_FLSHCMDADDR_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ + volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ + volatile ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ + volatile ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ + volatile ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ + volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ + volatile ALT_QSPI_MODULEID_t moduleid; /* ALT_QSPI_MODULEID */ +}; + +/* The typedef declaration for register group ALT_QSPI. */ +typedef volatile struct ALT_QSPI_s ALT_QSPI_t; +/* The struct declaration for the raw register contents of register group ALT_QSPI. */ +struct ALT_QSPI_raw_s +{ + volatile uint32_t cfg; /* ALT_QSPI_CFG */ + volatile uint32_t devrd; /* ALT_QSPI_DEVRD */ + volatile uint32_t devwr; /* ALT_QSPI_DEVWR */ + volatile uint32_t delay; /* ALT_QSPI_DELAY */ + volatile uint32_t rddatacap; /* ALT_QSPI_RDDATACAP */ + volatile uint32_t devsz; /* ALT_QSPI_DEVSZ */ + volatile uint32_t srampart; /* ALT_QSPI_SRAMPART */ + volatile uint32_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ + volatile uint32_t dmaper; /* ALT_QSPI_DMAPER */ + volatile uint32_t remapaddr; /* ALT_QSPI_REMAPADDR */ + volatile uint32_t modebit; /* ALT_QSPI_MODBIT */ + volatile uint32_t sramfill; /* ALT_QSPI_SRAMFILL */ + volatile uint32_t txthresh; /* ALT_QSPI_TXTHRESH */ + volatile uint32_t rxthresh; /* ALT_QSPI_RXTHRESH */ + volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ + volatile uint32_t irqstat; /* ALT_QSPI_IRQSTAT */ + volatile uint32_t irqmask; /* ALT_QSPI_IRQMSK */ + volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ + volatile uint32_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ + volatile uint32_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ + volatile uint32_t wrprot; /* ALT_QSPI_WRPROT */ + volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ + volatile uint32_t indrd; /* ALT_QSPI_INDRD */ + volatile uint32_t indrdwater; /* ALT_QSPI_INDRDWATER */ + volatile uint32_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ + volatile uint32_t indrdcnt; /* ALT_QSPI_INDRDCNT */ + volatile uint32_t indwr; /* ALT_QSPI_INDWR */ + volatile uint32_t indwrwater; /* ALT_QSPI_INDWRWATER */ + volatile uint32_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ + volatile uint32_t indwrcnt; /* ALT_QSPI_INDWRCNT */ + volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ + volatile uint32_t flashcmd; /* ALT_QSPI_FLSHCMD */ + volatile uint32_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ + volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ + volatile uint32_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ + volatile uint32_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ + volatile uint32_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ + volatile uint32_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ + volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ + volatile uint32_t moduleid; /* ALT_QSPI_MODULEID */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_QSPI. */ +typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_QSPI_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspidata.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspidata.h new file mode 100644 index 0000000..19383ee --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspidata.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_QSPIDATA */ + +#ifndef __ALTERA_ALT_QSPIDATA_H__ +#define __ALTERA_ALT_QSPIDATA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : QSPI Flash Module Data (AHB Slave) - ALT_QSPIDATA + * QSPI Flash Module Data (AHB Slave) + * + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_QSPIDATA_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_16550_uart.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_16550_uart.c new file mode 100644 index 0000000..a5dfc5f --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_16550_uart.c @@ -0,0 +1,1179 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_16550_uart.h" +#include "alt_clock_manager.h" +#include "socal/alt_rstmgr.h" +#include "socal/alt_uart.h" +#include "socal/hps.h" +#include "socal/socal.h" + +///// + +#define ALT_16550_HANDLE_DATA_UART_ENABLED_MSK (1UL << 31) +#define ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(value) (value & 0xffff) + +#define ALT_ALTERA_16550_CPR_OFST (0xF4) +#define ALT_ALTERA_16550_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ALTERA_16550_CPR_OFST)) +#define ALT_ALTERA_16550_CPR_FIFO_MODE_GET(value) (((value) >> 16) & 0xff) +#define ALT_ALTERA_16550_CPR_AFCE_MODE_SET_MSK (1 << 4) + +///// + +// Remove these macros as part of case:123835. +#define ALT_UART_IER_DLH_VALUE_SET(value) ((value) & 0xff) +#define ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK + +///// + +// +// Helper function which resets the UART and if requested, initializes the UART +// to the default settings. Currently the default settings are: +// - 8 databits +// - no parity +// - 1 stopbit +// - 57600 baudrate +// The reset routines depends on the hardware implementation of the UART. +// + +// This helper is needed because the regular alt_read_word(src) essentially +// resolves to "*(volatile uint32_t *)src". As there is no assignment, this +// could potentially be optimized away. With the helper, the actual register +// read should occur and be returned (and subsequently discarded). +static inline uint32_t alt_read_word_helper(const void * addr) +{ + return alt_read_word(addr); +} + +// +// Helper function write the divisor in hardware. +// +static ALT_STATUS_CODE alt_16550_write_divisor_helper(ALT_16550_HANDLE_t * handle, + uint32_t divisor) +{ + // Validate the divisor parameter. + if (divisor > 0xffff) + { + // This should never happen as it is verified in divisor_set. + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set LCR::DLAB (Line Control Register :: Divisor Latch Access Bit) + alt_setbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_DLAB_SET_MSK); + + // Write DLL (Divisor Latch Low). + alt_write_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location), ALT_UART_RBR_THR_DLL_VALUE_SET(divisor)); + + // Write DLH (Divisor Latch High). + alt_write_word(ALT_UART_IER_DLH_ADDR(handle->location), ALT_UART_IER_DLH_VALUE_SET(divisor >> 8)); + + // Clear LCR::DLAB (Line Control Register :: Divisor Latch Access Bit) + alt_clrbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_DLAB_SET_MSK); + + break; + + default: + return ALT_E_ERROR; + } + + // Update the enabled state in the handle data. + if (divisor != 0) + { + handle->data |= ALT_16550_HANDLE_DATA_UART_ENABLED_MSK; + } + else + { + handle->data &= ~ALT_16550_HANDLE_DATA_UART_ENABLED_MSK; + } + + return ALT_E_SUCCESS; +} + +// +// Helper function to reset the UART. +// +static ALT_STATUS_CODE alt_16550_reset_helper(ALT_16550_HANDLE_t * handle, bool enable_init) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::UR (Shadow Reset Register :: UART Reset) + alt_write_word(ALT_UART_SRR_ADDR(handle->location), ALT_UART_SRR_UR_SET_MSK); + + // Read the MSR to work around case:119085. + alt_read_word_helper(ALT_UART_MSR_ADDR(handle->location)); + break; + + case ALT_16550_DEVICE_ALTERA_16550_UART: + alt_16550_write_divisor_helper(handle, 0); // Disable UART + alt_16550_int_disable_all(handle); // Disable interrupts + alt_16550_fifo_disable(handle); // Disable FIFOs + alt_write_word(ALT_UART_MCR_ADDR(handle->location), 0); // 0 -> MCR (AFCE, LP, OUT2, OUT1, RTS, DTR) + break; + + default: + return ALT_E_ERROR; + } + + // If we are initializing (as opposed to just uninitializing) + if (enable_init) + { + ALT_STATUS_CODE status; + + // Set bit IER::PTIME (Interrupt Enable Register :: Programmable THRE Mode Enable) + alt_setbits_word(ALT_UART_IER_DLH_ADDR(handle->location), ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK); + + // Set the line configuration to use 8-N-1. + status = alt_16550_line_config_set(handle, ALT_16550_DATABITS_8, + ALT_16550_PARITY_DISABLE, + ALT_16550_STOPBITS_1); + if (status != ALT_E_SUCCESS) + { + return status; + } + + uint32_t divisor = ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data); + if (divisor == 0) + { + // Set the default baudrate to 57600. + status = alt_16550_baudrate_set(handle, ALT_16550_BAUDRATE_57600); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_init(ALT_16550_DEVICE_t device, + void * location, + alt_freq_t clock_freq, + ALT_16550_HANDLE_t * handle) +{ + handle->device = device; + handle->data = 0; + handle->fcr = 0; + + switch (device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // The ALT_CLK_L4_SP is required for all SoCFPGA UARTs. Check that it's enabled. + if (alt_clk_is_enabled(ALT_CLK_L4_SP) != ALT_E_TRUE) + { + return ALT_E_BAD_CLK; + } + else + { + ALT_STATUS_CODE status; + status = alt_clk_freq_get(ALT_CLK_L4_SP, &handle->clock_freq); + if (status != ALT_E_SUCCESS) + { + return status; + } + + if (device == ALT_16550_DEVICE_SOCFPGA_UART0) + { + handle->location = ALT_UART0_ADDR; + + // Bring UART0 out of reset. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART0_SET_MSK); + } + else // device == ALT_16550_DEVICE_SOCFPGA_UART1 + { + handle->location = ALT_UART1_ADDR; + + // Bring UART1 out of reset. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART1_SET_MSK); + } + + // Verify the UCR (UART Component Version) + uint32_t ucr = alt_read_word(ALT_UART_UCV_ADDR(handle->location)); + if (ucr != ALT_UART_UCV_UART_COMPONENT_VER_RESET) + { + return ALT_E_ERROR; + } + } + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + handle->location = location; + handle->clock_freq = clock_freq; + break; + default: + return ALT_E_BAD_ARG; + } + + return alt_16550_reset_helper(handle, true); +} + +ALT_STATUS_CODE alt_16550_uninit(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART0_SET_MSK); + return ALT_E_SUCCESS; + case ALT_16550_DEVICE_SOCFPGA_UART1: + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART1_SET_MSK); + return ALT_E_SUCCESS; + case ALT_16550_DEVICE_ALTERA_16550_UART: + default: + return alt_16550_reset_helper(handle, false); + } +} + +ALT_STATUS_CODE alt_16550_reset(ALT_16550_HANDLE_t * handle) +{ + return alt_16550_reset_helper(handle, true); +} + +ALT_STATUS_CODE alt_16550_enable(ALT_16550_HANDLE_t * handle) +{ + // Write the divisor cached in the handle data to the divisor registers. + // This will effectively enable the UART. + return alt_16550_write_divisor_helper(handle, + ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data)); +} + +ALT_STATUS_CODE alt_16550_disable(ALT_16550_HANDLE_t * handle) +{ + // Write 0 to the divisor the divisor registers. This will effectively + // disable the UART. + return alt_16550_write_divisor_helper(handle, 0); +} + +ALT_STATUS_CODE alt_16550_read(ALT_16550_HANDLE_t * handle, + char * item) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is disabled + if (handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the RBR (Receive Buffer Register) into *item. + *item = ALT_UART_RBR_THR_DLL_VALUE_GET(alt_read_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location))); + break; + default: + return ALT_E_ERROR; + } + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_write(ALT_16550_HANDLE_t * handle, + char item) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is disabled + if (handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write the buffer into the THR (Transmit Holding Register) + alt_write_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location), item); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_16550_fifo_enable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set FCR::FIFOE (FIFO Control Register :: FIFO Enable) bit. + handle->fcr |= ALT_UART_FCR_FIFOE_SET_MSK; + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + // No need to reset / clear the FIFOs. This is done automatically when + // FCR::FIFOE is changed. + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_disable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear FCR::FIFOE (FIFO Control Register :: FIFO Enable) bit. + handle->fcr &= ~ALT_UART_FCR_FIFOE_SET_MSK; + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_read(ALT_16550_HANDLE_t * handle, + char * buffer, + size_t count) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the RBR (Receive Buffer Register) into the buffer + for (size_t i = 0; i < count; ++i) + { + buffer[i] = ALT_UART_RBR_THR_DLL_VALUE_GET(alt_read_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location))); + } + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_write(ALT_16550_HANDLE_t * handle, + const char * buffer, + size_t count) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write the buffer into the THR (Transmit Holding Register) + for (size_t i = 0; i < count; ++i) + { + alt_write_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location), buffer[i]); + } + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_clear_rx(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::RFR (Shadow Reset Register :: Receiver FIFO Reset) bit. + alt_write_word(ALT_UART_SRR_ADDR(handle->location), ALT_UART_SRR_RFR_SET_MSK); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write FCR::RFIFOR (FIFO Control Register :: Receiver FIFO Reset) bit. + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr | ALT_UART_FCR_RFIFOR_SET_MSK); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_clear_tx(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::XFR (Shadow Reset Register :: Xmitter FIFO Reset) bit. + alt_write_word(ALT_UART_SRR_ADDR(handle->location), ALT_UART_SRR_XFR_SET_MSK); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write FCR::XFIFOR (FIFO Control Register :: Xmitter FIFO Reset) bit. + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr | ALT_UART_FCR_XFIFOR_SET_MSK); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_clear_all(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::(RFR | XFR) + // (Shadow Reset Register :: (Receiver FIFO Reset | Xmitter FIFO Reset)) bits. + alt_write_word(ALT_UART_SRR_ADDR(handle->location), + ALT_UART_SRR_RFR_SET_MSK | ALT_UART_SRR_XFR_SET_MSK); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write FCR::(RFIFOR |XFIFOR) + // (FIFO Control Register :: (Receiver FIFO Reset | Xmitter FIFO Reset)) bits. + alt_write_word(ALT_UART_FCR_ADDR(handle->location), + handle->fcr | ALT_UART_FCR_RFIFOR_SET_MSK | ALT_UART_FCR_XFIFOR_SET_MSK); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_size_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * size) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read the CPR::FIFO_Mod (Component Parameter Register :: FIFO Mode). + // The FIFO size is 16x this value. + *size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Altera 16550 Compatible Soft UARTs have a configurable size and is + // stored in the CPR::FIFO_Mode (Component Parameter Register :: FIFO Depth). + *size = ALT_ALTERA_16550_CPR_FIFO_MODE_GET(alt_read_word(ALT_ALTERA_16550_CPR_ADDR(handle->location))) << 4; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_size_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * size) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read the CPR::FIFO_Mod (Component Parameter Register :: FIFO Mode). + // The FIFO size is 16x this value. + *size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Altera 16550 Compatible Soft UARTs have a configurable size and is + // stored in the CPR::FIFO_Mode (Component Parameter Register :: FIFO Depth). + // The FIFO size is 16x this value. + *size = ALT_ALTERA_16550_CPR_FIFO_MODE_GET(alt_read_word(ALT_ALTERA_16550_CPR_ADDR(handle->location))) << 4; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_level_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * level) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read RFL (Receive FIFO Level). + *level = alt_read_word(ALT_UART_RFL_ADDR(handle->location)); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // RFL not implemented. Return 0. + *level = 0; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_level_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * level) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read TFL (Transmit FIFO Level). + *level = alt_read_word(ALT_UART_TFL_ADDR(handle->location)); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // TFL not implemented. Return 0. + *level = 0; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_trigger_set_rx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_RX_t trigger) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + // Verify triggering parameter + switch (trigger) + { + case ALT_16550_FIFO_TRIGGER_RX_ANY: + case ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL: + case ALT_16550_FIFO_TRIGGER_RX_HALF_FULL: + case ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Update FCR::RT (FIFO Control Register :: Receiver Trigger) + handle->fcr &= ~ALT_UART_FCR_RT_SET_MSK; + handle->fcr |= ALT_UART_FCR_RT_SET(trigger); + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_trigger_set_tx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_TX_t trigger) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + // Verify triggering parameter + switch (trigger) + { + case ALT_16550_FIFO_TRIGGER_TX_EMPTY: + case ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY: + case ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL: + case ALT_16550_FIFO_TRIGGER_TX_HALF_FULL: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Update FCR::TET (FIFO Control Register :: Transmit Empty Trigger) + handle->fcr &= ~ALT_UART_FCR_TET_SET_MSK; + handle->fcr |= ALT_UART_FCR_TET_SET(trigger); + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_16550_baudrate_get(ALT_16550_HANDLE_t * handle, + uint32_t * baudrate) +{ + // Query the divisor cached in the handle data + uint32_t divisor = ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data); + + // The divisor should never be zero. It is set to allow for a baud of 57600 + // on initialization and a valid value is checked at + // alt_16550_divisor_set(). We do not check for users altering the data in + // the handle structure. + + // Formula for calculating the baudrate: + // baudrate = clock / (16 * divisor) + + *baudrate = (handle->clock_freq >> 4) / divisor; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_baudrate_set(ALT_16550_HANDLE_t * handle, + uint32_t baudrate) +{ + if (baudrate == 0) + { + return ALT_E_ARG_RANGE; + } + + // Formula for calculating the divisor: + // baudrate = clock / (16 * divisor) + // => baudrate * 16 * divisor = clock + // => divisor = clock / (baudrate * 16) + // => divisor = (clock / 16) / baudrate + + // Add half of the denominator to address rounding errors. + uint32_t divisor = ((handle->clock_freq + (8 * baudrate)) / (16 * baudrate)); + + // Check for divisor range is in alt_16550_divisor_set(). + return alt_16550_divisor_set(handle, divisor); +} + +ALT_STATUS_CODE alt_16550_divisor_get(ALT_16550_HANDLE_t * handle, + uint32_t * divisor) +{ + // Just read the divisor portion of the handle data. + *divisor = ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_divisor_set(ALT_16550_HANDLE_t * handle, + uint32_t divisor) +{ + // Verify divisor value is in range. + if ((divisor > 0xffff) || (divisor == 0)) + { + return ALT_E_ARG_RANGE; + } + + // Set the divisor portion of the handle data. + handle->data &= ~(0xffff); + handle->data |= divisor; + + // Even if the UART is enabled, don't do anything. It is documented that + // the change will take effect when the UART move to the enabled state. + + return ALT_E_SUCCESS; +} + +///// + +static ALT_STATUS_CODE alt_16550_ier_mask_set_helper(ALT_16550_HANDLE_t * handle, uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set bit in IER (Interrupt Enable Register) + alt_setbits_word(ALT_UART_IER_DLH_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +static ALT_STATUS_CODE alt_16550_ier_mask_clr_helper(ALT_16550_HANDLE_t * handle, uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear bit in IER (Interrupt Enable Register) + alt_clrbits_word(ALT_UART_IER_DLH_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_int_enable_rx(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::ERBFI (Interrupt Enable Register :: Enable Receive Buffer Full Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_rx(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::ERBFI (Interrupt Enable Register :: Enable Receive Buffer Full Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_enable_tx(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::ETBEI (Interrupt Enable Register :: Enable Transmit Buffer Empty Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_tx(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::ETBEI (Interrupt Enable Register :: Enable Transmit Buffer Empty Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_enable_line(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::ELSI (Interrupt Enable Register :: Enable Line Status Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_line(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::ELSI (Interrupt Enable Register :: Enable Line Status Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_enable_modem(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::EDSSI (Interrupt Enable Register :: Enable Modem Status Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_modem(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::EDSSI (Interrupt Enable Register :: Enable Modem Status Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_all(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::(ERBFI | ETBEI | ELSI | EDSSI) + // (Interrupt Enable Register :: (Enable Receive Buffer Full Interrupt | + // Enable Transmit Buffer Empty Interrupt | + // Enable Line Status Interrupt | + // Enable Modem Status Interrupt)) bits + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK | + ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK | + ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK | + ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_status_get(ALT_16550_HANDLE_t * handle, + ALT_16550_INT_STATUS_t * status) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read IIR::IID (Interrupt Identity Register :: Interrupt ID) + *status = (ALT_16550_INT_STATUS_t) ALT_UART_IIR_ID_GET(alt_read_word(ALT_UART_IIR_ADDR(handle->location))); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_16550_line_config_set(ALT_16550_HANDLE_t * handle, + ALT_16550_DATABITS_t databits, + ALT_16550_PARITY_t parity, + ALT_16550_STOPBITS_t stopbits) +{ + // Validate the databits parameter. + switch (databits) + { + case ALT_16550_DATABITS_5: + case ALT_16550_DATABITS_6: + case ALT_16550_DATABITS_7: + case ALT_16550_DATABITS_8: + break; + default: + return ALT_E_ERROR; + } + + // Validate the parity parameter. + switch (parity) + { + case ALT_16550_PARITY_DISABLE: + case ALT_16550_PARITY_ODD: + case ALT_16550_PARITY_EVEN: + break; + default: + return ALT_E_ERROR; + } + + // Validate the stopbits parameter. + switch (stopbits) + { + case ALT_16550_STOPBITS_1: + case ALT_16550_STOPBITS_2: + break; + default: + return ALT_E_ERROR; + } + + // LCR (Line Control Register) cache. + uint32_t lcr = 0; + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + + // Configure the number of databits + lcr |= ALT_UART_LCR_DLS_SET(databits); + + // Configure the number of stopbits + lcr |= ALT_UART_LCR_STOP_SET(stopbits); + + // Configure the parity + if (parity != ALT_16550_PARITY_DISABLE) + { + // Enable parity in LCR + lcr |= ALT_UART_LCR_PEN_SET_MSK; + + if (parity == ALT_16550_PARITY_EVEN) + { + // Enable even parity in LCR; otherwise it's odd parity. + lcr |= ALT_UART_LCR_EPS_SET_MSK; + } + } + + // Update LCR (Line Control Register) + alt_replbits_word(ALT_UART_LCR_ADDR(handle->location), + ALT_UART_LCR_DLS_SET_MSK + | ALT_UART_LCR_STOP_SET_MSK + | ALT_UART_LCR_PEN_SET_MSK + | ALT_UART_LCR_EPS_SET_MSK, + lcr); + + break; + + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_line_break_enable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set the LCR::Break (Line Control Register :: Break) bit. + alt_setbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_BREAK_SET_MSK); + break; + + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_line_break_disable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear the LCR::Break (Line Control Register :: Break) bit. + alt_clrbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_BREAK_SET_MSK); + break; + + default: + return ALT_E_ERROR; + } + + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_line_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the LSR (Line Status Register). + *status = alt_read_word(ALT_UART_LSR_ADDR(handle->location)); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +static ALT_STATUS_CODE alt_16550_mcr_mask_set_helper(ALT_16550_HANDLE_t * handle, + uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set the bit in MCR (Modem Control Register). + alt_setbits_word(ALT_UART_MCR_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +static ALT_STATUS_CODE alt_16550_mcr_mask_clr_helper(ALT_16550_HANDLE_t * handle, uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear the bit in MCR (Modem Control Register). + alt_clrbits_word(ALT_UART_MCR_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_flowcontrol_enable(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + // For the Altera 16550 Compatible Soft UART, check that Hardware Flowcontrol is enabled. + if (handle->device == ALT_16550_DEVICE_ALTERA_16550_UART) + { + // Read the CPR::AFCE_Mode (Component Parameter Register :: Auto Flow Control mode) bit. + uint32_t cpr = alt_read_word(ALT_ALTERA_16550_CPR_ADDR(handle->location)); + if (!(ALT_ALTERA_16550_CPR_AFCE_MODE_SET_MSK & cpr)) + { + return ALT_E_ERROR; + } + } + + // Set MCR::AFCE (Modem Control Register :: Automatic FlowControl Enable) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_AFCE_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_flowcontrol_disable(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::AFCE (Modem Control Register :: Automatic FlowControl Enable) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_AFCE_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_loopback_enable(ALT_16550_HANDLE_t * handle) +{ + // Loopback is not implemented in the Altera 16550 Compatible Soft UART. + if (handle->device == ALT_16550_DEVICE_ALTERA_16550_UART) + { + return ALT_E_ERROR; + } + + // Set MCR::Loopback (Modem Control Register :: Loopback) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_LOOPBACK_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_loopback_disable(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::Loopback (Modem Control Register :: Loopback) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_LOOPBACK_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_out1(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::Out1 (Modem Control Register :: Out1) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_OUT1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_out1(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::Out1 (Modem Control Register :: Out1) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_OUT1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_out2(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::Out2 (Modem Control Register :: Out2) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_OUT2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_out2(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::Out2 (Modem Control Register :: Out2) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_OUT2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_rts(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::RTS (Modem Control Register :: Request To Send) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_RTS_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_rts(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::RTS (Modem Control Register :: Request To Send) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_RTS_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_dtr(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::DTR (Modem Control Register :: Data Terminal Ready) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_DTR_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_dtr(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::DTR (Modem Control Register :: Data Terminal Ready) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_DTR_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the MSR (Modem Status Register). + *status = alt_read_word(ALT_UART_MSR_ADDR(handle->location)); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma.c new file mode 100644 index 0000000..2bdc519 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma.c @@ -0,0 +1,3749 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include +#include "alt_dma.h" +#include "socal/socal.h" +#include "socal/hps.h" +#include "socal/alt_rstmgr.h" +#include "socal/alt_sysmgr.h" + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT +#include "alt_16550_uart.h" +#include "socal/alt_uart.h" +#endif + +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT +#include "socal/alt_qspi.h" +#endif + +///// + +#ifndef MIN +#define MIN(a, b) ((a) > (b) ? (b) : (a)) +#endif // MIN + +#ifndef ARRAY_COUNT +#define ARRAY_COUNT(array) (sizeof(array) / sizeof(array[0])) +#endif + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) + +///// + +// +// SoCAL stand in for DMA Controller registers +// +// The base can be one of the following: +// - ALT_DMANONSECURE_ADDR +// - ALT_DMASECURE_ADDR +// +// Macros which have a channel parameter does no validation. +// + +// DMA Manager Status Register +#define ALT_DMA_DSR_OFST 0x0 +#define ALT_DMA_DSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DSR_OFST)) +#define ALT_DMA_DSR_DMASTATUS_SET_MSK 0x0000000f +#define ALT_DMA_DSR_DMASTATUS_GET(value) ((value) & 0x0000000f) + +// DMA Program Counter Register +#define ALT_DMA_DPC_OFST 0x4 +#define ALT_DMA_DPC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DPC_OFST)) + +// Interrupt Enable Register +#define ALT_DMA_INTEN_OFST 0x20 +#define ALT_DMA_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTEN_OFST)) + +// Event-Interrupt Raw Status Register +#define ALT_DMA_INT_EVENT_RIS_OFST 0x24 +#define ALT_DMA_INT_EVENT_RIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INT_EVENT_RIS_OFST)) + +// Interrupt Status Register +#define ALT_DMA_INTMIS_OFST 0x28 +#define ALT_DMA_INTMIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTMIS_OFST)) + +// Interrupt Clear Register +#define ALT_DMA_INTCLR_OFST 0x2c +#define ALT_DMA_INTCLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTCLR_OFST)) + +// Fault Status DMA Manager Register +#define ALT_DMA_FSRD_OFST 0x30 +#define ALT_DMA_FSRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRD_OFST)) + +// Fault Status DMA Channel Register +#define ALT_DMA_FSRC_OFST 0x34 +#define ALT_DMA_FSRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRC_OFST)) + +// Fault Type DMA Manager Register +#define ALT_DMA_FTRD_OFST 0x38 +#define ALT_DMA_FTRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRD_OFST)) + +// Fault Type DMA Channel Registers +#define ALT_DMA_FTRx_OFST(channel) (0x40 + 0x4 * (channel)) +#define ALT_DMA_FTRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FTRx_OFST(channel))) + +// Channel Status Registers +#define ALT_DMA_CSRx_OFST(channel) (0x100 + 0x8 * (channel)) +#define ALT_DMA_CSRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CSRx_OFST(channel))) +#define ALT_DMA_CSRx_CHANNELSTATUS_SET_MSK 0x0000000f +#define ALT_DMA_CSRx_CHANNELSTATUS_GET(value) ((value) & 0x0000000f) + +// Channel Program Counter Registers +#define ALT_DMA_CPCx_OFST(channel) (0x104 + 0x8 * (channel)) +#define ALT_DMA_CPCx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CPCx_OFST(channel))) + +// Source Address Registers +#define ALT_DMA_SARx_OFST(channel) (0x400 + 0x20 * (channel)) +#define ALT_DMA_SARx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_SARx_OFST(channel))) + +// Destination Address Registers +#define ALT_DMA_DARx_OFST(channel) (0x404 + 0x20 * (channel)) +#define ALT_DMA_DARx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DARx_OFST(channel))) + +// Channel Control Registers +#define ALT_DMA_CCRx_OFST(channel) (0x408 + 0x20 * (channel)) +#define ALT_DMA_CCRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CCRx_OFST(channel))) + +// Loop Counter 0 Registers +#define ALT_DMA_LC0_x_OFST(channel) (0x40c + 0x20 * (channel)) +#define ALT_DMA_LC0_x_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_LC0_x_OFST(channel))) + +// Loop Counter 1 Registers +#define ALT_DMA_LC1_x_OFST(channel) (0x410 + 0x20 * (channel)) +#define ALT_DMA_LC1_x_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_LC1_x_OFST(channel))) + +// Debug Status Register +#define ALT_DMA_DBGSTATUS_OFST 0xd00 +#define ALT_DMA_DBGSTATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGSTATUS_OFST)) + +// Debug Command Register +#define ALT_DMA_DBGCMD_OFST 0xd04 +#define ALT_DMA_DBGCMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGCMD_OFST)) + +// Debug Instruction-0 Register +#define ALT_DMA_DBGINST0_OFST 0xd08 +#define ALT_DMA_DBGINST0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGINST0_OFST)) +#define ALT_DMA_DBGINST0_CHANNELNUMBER_SET(value) (((value) & 0x7) << 8) +#define ALT_DMA_DBGINST0_DEBUGTHREAD_SET(value) ((value) & 0x1) +#define ALT_DMA_DBGINST0_DEBUGTHREAD_E_MANAGER 0 +#define ALT_DMA_DBGINST0_DEBUGTHREAD_E_CHANNEL 1 +#define ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(value) (((value) & 0xff) << 16) +#define ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(value) (((value) & 0xff) << 24) + +// Debug Instruction-1 Register +#define ALT_DMA_DBGINST1_OFST 0xd0c +#define ALT_DMA_DBGINST1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGINST1_OFST)) + +// Configuration Registers 0 - 4 +#define ALT_DMA_CR0_OFST 0xe00 +#define ALT_DMA_CR1_OFST 0xe04 +#define ALT_DMA_CR2_OFST 0xe08 +#define ALT_DMA_CR3_OFST 0xe0c +#define ALT_DMA_CR4_OFST 0xe10 +#define ALT_DMA_CR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR0_OFST)) +#define ALT_DMA_CR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR1_OFST)) +#define ALT_DMA_CR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR2_OFST)) +#define ALT_DMA_CR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR3_OFST)) +#define ALT_DMA_CR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR4_OFST)) + +// DMA Configuration Register +#define ALT_DMA_CRD_OFST 0xe14 +#define ALT_DMA_CRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CRD_OFST)) + +// Watchdog Register +#define ALT_DMA_WD_OFST 0xe80 +#define ALT_DMA_WD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_WD_OFST)) + +///// + +// +// Internal Data structures +// + +// This flag marks the channel as being allocated. +#define ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED (1 << 0) + +typedef struct ALT_DMA_CHANNEL_INFO_s +{ + uint8_t flag; +} +ALT_DMA_CHANNEL_INFO_t; + +static ALT_DMA_CHANNEL_INFO_t channel_info_array[8]; + +///// + +ALT_STATUS_CODE alt_dma_init(const ALT_DMA_CFG_t * dma_cfg) +{ + // Initialize the channel information array + for (int i = 0; i < 8; ++i) + { + channel_info_array[i].flag = 0; + } + + // Update the System Manager DMA configuration items + + uint32_t dmactrl = 0; + + // Handle FPGA / CAN muxing + for (int i = 0; i < 4; ++i) + { + // The default is FPGA. + switch (dma_cfg->periph_mux[i]) + { + case ALT_DMA_PERIPH_MUX_DEFAULT: + case ALT_DMA_PERIPH_MUX_FPGA: + break; + case ALT_DMA_PERIPH_MUX_CAN: + dmactrl |= (ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK << i); + break; + default: + return ALT_E_ERROR; + } + } + + // Handle Manager security + // Default is Secure state. + switch (dma_cfg->manager_sec) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + break; + case ALT_DMA_SECURITY_NONSECURE: + dmactrl |= ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK; + break; + default: + return ALT_E_ERROR; + } + + // Handle IRQ security + for (int i = 0; i < ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH; ++i) + { + // Default is Secure state. + switch (dma_cfg->irq_sec[i]) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + break; + case ALT_DMA_SECURITY_NONSECURE: + dmactrl |= (1 << (i + ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB)); + break; + default: + return ALT_E_ERROR; + } + } + + alt_write_word(ALT_SYSMGR_DMA_CTL_ADDR, dmactrl); + + // Update the System Manager DMA peripheral security items + + uint32_t dmapersecurity = 0; + + for (int i = 0; i < 32; ++i) + { + // Default is Secure state. + switch (dma_cfg->periph_sec[i]) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + break; + case ALT_DMA_SECURITY_NONSECURE: + dmapersecurity |= (1 << i); + break; + default: + return ALT_E_ERROR; + } + } + + alt_write_word(ALT_SYSMGR_DMA_PERSECURITY_ADDR, dmapersecurity); + + // Take DMA out of reset. + + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_DMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_uninit(void) +{ + // DMAKILL all channel and free all allocated channels. + for (int i = 0; i < 8; ++i) + { + if (channel_info_array[i].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED) + { + alt_dma_channel_kill((ALT_DMA_CHANNEL_t)i); + alt_dma_channel_free((ALT_DMA_CHANNEL_t)i); + } + } + + // Put DMA into reset. + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_DMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_alloc(ALT_DMA_CHANNEL_t channel) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is unallocated + + if (channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED) + { + return ALT_E_ERROR; + } + + // Mark channel as allocated + + channel_info_array[channel].flag |= ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_alloc_any(ALT_DMA_CHANNEL_t * allocated) +{ + // Sweep channel array for unallocated channel + + for (int i = 0; i < 8; ++i) + { + if (!(channel_info_array[i].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + // Allocate that free channel. + + ALT_STATUS_CODE status = alt_dma_channel_alloc((ALT_DMA_CHANNEL_t)i); + if (status == ALT_E_SUCCESS) + { + *allocated = (ALT_DMA_CHANNEL_t)i; + } + return status; + } + } + + // No free channels found. + + return ALT_E_ERROR; +} + +ALT_STATUS_CODE alt_dma_channel_free(ALT_DMA_CHANNEL_t channel) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is allocated + + if (!(channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + return ALT_E_ERROR; + } + + // Verify channel is stopped + + ALT_DMA_CHANNEL_STATE_t state; + ALT_STATUS_CODE status = alt_dma_channel_state_get(channel, &state); + if (status != ALT_E_SUCCESS) + { + return status; + } + if (state != ALT_DMA_CHANNEL_STATE_STOPPED) + { + return ALT_E_ERROR; + } + + // Mark channel as unallocated. + + channel_info_array[channel].flag &= ~ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_exec(ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_t * pgm) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is allocated + + if (!(channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + return ALT_E_ERROR; + } + + // Verify channel is stopped + + ALT_DMA_CHANNEL_STATE_t state; + ALT_STATUS_CODE status = alt_dma_channel_state_get(channel, &state); + if (status != ALT_E_SUCCESS) + { + return status; + } + if (state != ALT_DMA_CHANNEL_STATE_STOPPED) + { + return ALT_E_ERROR; + } + + // Validate the program + + if (alt_dma_program_validate(pgm) != ALT_E_SUCCESS) + { + return ALT_E_ERROR; + } + + // + // Execute the program + // + + // Get the start address + + uint32_t start = (uint32_t) &pgm->program[pgm->buffer_start]; + + dprintf("DMA[exec]: pgm->program = %p.\n", pgm->program); + dprintf("DMA[exec]: start = %p.\n", (void *)start); + + // Configure DBGINST0 and DBGINST1 to execute DMAGO targetting the requested channel. + + // For information on APB Interface, see PL330, section 2.5.1. + // For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21. + // For information on DMAGO, see PL330, section 4.3.5. + + alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR), + ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0xa0) | + ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(channel)); + + alt_write_word(ALT_DMA_DBGINST1_ADDR(ALT_DMASECURE_ADDR), start); + + // Execute the instruction held in DBGINST{0,1} + + // For information on DBGCMD, see PL330, section 3.3.19. + + alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_kill(ALT_DMA_CHANNEL_t channel) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is allocated + + if (!(channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + return ALT_E_ERROR; + } + + // NOTE: Don't worry about the current channel state. Just issue DMAKILL + // instruction. The channel state cannot move from from Stopped back to + // Killing. + + // Configure DBGINST0 to execute DMAKILL on the requested channel thread. + // DMAKILL is short enough not to use DBGINST1 register. + + // For information on APB Interface, see PL330, section 2.5.1. + // For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21. + // For information on DMAKILL, see PL330, section 4.3.6. + + alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR), + ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0x1) | + ALT_DMA_DBGINST0_CHANNELNUMBER_SET(channel) | + ALT_DMA_DBGINST0_DEBUGTHREAD_SET(ALT_DMA_DBGINST0_DEBUGTHREAD_E_CHANNEL)); + + // Execute the instruction held in DBGINST0 + + // For information on DBGCMD, see PL330, section 3.3.19. + + alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0); + + // Wait for channel to move to KILLING or STOPPED state. Do not wait for + // the STOPPED only. If the AXI transaction hangs permanently, it can be + // waiting indefinately. + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + ALT_DMA_CHANNEL_STATE_t current; + uint32_t i = 20000; + + while (--i) + { + status = alt_dma_channel_state_get(channel, ¤t); + if (status != ALT_E_SUCCESS) + { + break; + } + if ( (current == ALT_DMA_CHANNEL_STATE_KILLING) + || (current == ALT_DMA_CHANNEL_STATE_STOPPED)) + { + break; + } + } + + if (i == 0) + { + status = ALT_E_TMO; + } + + return status; +} + +ALT_STATUS_CODE alt_dma_channel_reg_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_REG_t reg, uint32_t * val) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on SAR, see PL330, section 3.3.13. + // For information on DAR, see PL330, section 3.3.14. + // For information on CCR, see PL330, section 3.3.15. + + switch (reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + *val = alt_read_word(ALT_DMA_SARx_ADDR(ALT_DMASECURE_ADDR, channel)); + break; + case ALT_DMA_PROGRAM_REG_DAR: + *val = alt_read_word(ALT_DMA_DARx_ADDR(ALT_DMASECURE_ADDR, channel)); + break; + case ALT_DMA_PROGRAM_REG_CCR: + *val = alt_read_word(ALT_DMA_CCRx_ADDR(ALT_DMASECURE_ADDR, channel)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_send_event(ALT_DMA_EVENT_t evt_num) +{ + // Validate evt_num + + switch (evt_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // Issue the DMASEV on the DMA manager thread. + // DMASEV is short enough not to use DBGINST1 register. + + // For information on APB Interface, see PL330, section 2.5.1. + // For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21. + // For information on DMASEV, see PL330, section 4.3.15. + + alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR), + ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0x34) | // opcode for DMASEV + ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(evt_num << 3) | + ALT_DMA_DBGINST0_DEBUGTHREAD_SET(ALT_DMA_DBGINST0_DEBUGTHREAD_E_MANAGER) + ); + + // Execute the instruction held in DBGINST0 + + // For information on DBGCMD, see PL330, section 3.3.19. + + alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_manager_state_get(ALT_DMA_MANAGER_STATE_t * state) +{ + // For information on DSR, see PL330, section 3.3.1. + + uint32_t raw_state = alt_read_word(ALT_DMA_DSR_ADDR(ALT_DMASECURE_ADDR)); + + *state = (ALT_DMA_MANAGER_STATE_t)ALT_DMA_DSR_DMASTATUS_GET(raw_state); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_state_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_CHANNEL_STATE_t * state) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on CSR, see PL330, section 3.3.11. + + uint32_t raw_state = alt_read_word(ALT_DMA_CSRx_ADDR(ALT_DMASECURE_ADDR, channel)); + + *state = (ALT_DMA_CHANNEL_STATE_t)ALT_DMA_CSRx_CHANNELSTATUS_GET(raw_state); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_manager_fault_status_get(ALT_DMA_MANAGER_FAULT_t * fault) +{ + // For information on FTRD, see PL330, section 3.3.9. + + *fault = (ALT_DMA_MANAGER_FAULT_t)alt_read_word(ALT_DMA_FTRD_ADDR(ALT_DMASECURE_ADDR)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_fault_status_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_CHANNEL_FAULT_t * fault) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on FTR, see PL330, section 3.3.10. + + *fault = (ALT_DMA_CHANNEL_FAULT_t)alt_read_word(ALT_DMA_FTRx_ADDR(ALT_DMASECURE_ADDR, channel)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_event_int_select(ALT_DMA_EVENT_t evt_num, + ALT_DMA_EVENT_SELECT_t opt) +{ + // Validate evt_num + switch (evt_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INTEN, see PL330, section 3.3.3. + + switch (opt) + { + case ALT_DMA_EVENT_SELECT_SEND_EVT: + alt_clrbits_word(ALT_DMA_INTEN_ADDR(ALT_DMASECURE_ADDR), 1 << evt_num); + break; + case ALT_DMA_EVENT_SELECT_SIG_IRQ: + alt_setbits_word(ALT_DMA_INTEN_ADDR(ALT_DMASECURE_ADDR), 1 << evt_num); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_event_int_status_get_raw(ALT_DMA_EVENT_t evt_num) +{ + // Validate evt_num + switch (evt_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INT_EVENT_RIS, see PL330, section 3.3.4. + + uint32_t status_raw = alt_read_word(ALT_DMA_INT_EVENT_RIS_ADDR(ALT_DMASECURE_ADDR)); + + if (status_raw & (1 << evt_num)) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +ALT_STATUS_CODE alt_dma_int_status_get(ALT_DMA_EVENT_t irq_num) +{ + // Validate evt_num + switch (irq_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INTMIS, see PL330, section 3.3.5. + + uint32_t int_status = alt_read_word(ALT_DMA_INTMIS_ADDR(ALT_DMASECURE_ADDR)); + + if (int_status & (1 << irq_num)) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +ALT_STATUS_CODE alt_dma_int_clear(ALT_DMA_EVENT_t irq_num) +{ + // Validate evt_num + switch (irq_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INTCLR, see PL330, section 3.3.6. + + alt_write_word(ALT_DMA_INTCLR_ADDR(ALT_DMASECURE_ADDR), 1 << irq_num); + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_dma_memory_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst, + const void * src, + size_t size, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the size is zero, and no event is requested, just return success. + if ((size == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (size != 0) + { + uintptr_t udst = (uintptr_t)dst; + uintptr_t usrc = (uintptr_t)src; + + dprintf("DMA[M->M]: dst = %p.\n", dst); + dprintf("DMA[M->M]: src = %p.\n", src); + dprintf("DMA[M->M]: size = 0x%x.\n", size); + + // Detect if memory regions overshoots the address space. + + if (udst + size - 1 < udst) + { + return ALT_E_BAD_ARG; + } + if (usrc + size - 1 < usrc) + { + return ALT_E_BAD_ARG; + } + + // Detect if memory regions overlaps. + + if (udst > usrc) + { + if (usrc + size - 1 > udst) + { + return ALT_E_BAD_ARG; + } + } + else + { + if (udst + size - 1 > usrc) + { + return ALT_E_BAD_ARG; + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, usrc); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, udst); + } + + size_t sizeleft = size; + + // + // The algorithm uses the strategy described in PL330 B.3.1. + // It is extended for 2-byte and 1-byte unaligned cases. + // + + // First see how many byte(s) we need to transfer to get src to be 8 byte aligned + if (usrc & 0x7) + { + uint32_t aligncount = MIN(8 - (usrc & 0x7), sizeleft); + sizeleft -= aligncount; + + dprintf("DMA[M->M]: Total pre-alignment 1-byte burst size tranfer(s): %lu.\n", aligncount); + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SBx (Source burst length of [aligncount] transfers) + // - DBx (Destination burst length of [aligncount] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ((aligncount - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((aligncount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + // This is the number of 8-byte bursts + uint32_t burstcount = sizeleft >> 3; + + bool correction = (burstcount != 0); + + // Update the size left to transfer + sizeleft &= 0x7; + + dprintf("DMA[M->M]: Total Main 8-byte burst size transfer(s): %lu.\n", burstcount); + dprintf("DMA[M->M]: Total Main 1-byte burst size transfer(s): %u.\n", sizeleft); + + // Determine how many 16 length bursts can be done + + if (burstcount >> 4) + { + uint32_t length16burstcount = burstcount >> 4; + burstcount &= 0xf; + + dprintf("DMA[M->M]: Number of 16 burst length 8-byte transfer(s): %lu.\n", length16burstcount); + dprintf("DMA[M->M]: Number of remaining 8-byte transfer(s): %lu.\n", burstcount); + + // Program in the following parameters: + // - SS64 (Source burst size of 8-byte) + // - DS64 (Destination burst size of 8-byte) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SS64 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (length16burstcount > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(length16burstcount, 256); + length16burstcount -= loopcount; + + dprintf("DMA[M->M]: Looping %lux 16 burst length 8-byte transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [burstcount] 8-byte transfer(s) + // remaining. [burstcount] should be less than 16. + + // Do one more burst with a SB / DB of length [burstcount]. + + if (burstcount) + { + // Program in the following parameters: + // - SS64 (Source burst size of 8-byte) + // - DS64 (Destination burst size of 8-byte) + // - SBx (Source burst length of [burstlength] transfers) + // - DBx (Destination burst length of [burstlength] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ((burstcount - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SS64 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((burstcount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + // This is where the last DMAMOV CCR and DMAST is done if an + // alignment correction required. + + if ( (correction == true) + && ((usrc & 0x7) != (udst & 0x7)) // If src and dst are mod-8 congruent, no correction is needed. + ) + { + if (status == ALT_E_SUCCESS) + { + // Determine what type of correction. + + // Set the source parameters to match that of the destination + // parameters. This way the SAR is increment in the same fashion as + // DAR. This will allow the non 8-byte transfers to copy correctly. + + uint32_t ccr; + + if ((usrc & 0x3) == (udst & 0x3)) + { + dprintf("DMA[M->M]: Single correction 4-byte burst size tranfer.\n"); + + // Program in the following parameters: + // - SS32 (Source burst size of 4-byte) + // - DS32 (Destination burst size of 4-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - All other options default. + + ccr = ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ); + } + else if ((usrc & 0x1) == (udst & 0x1)) + { + dprintf("DMA[M->M]: Single correction 2-byte burst size tranfer.\n"); + + // Program in the following parameters: + // - SS16 (Source burst size of 2-byte) + // - DS16 (Destination burst size of 2-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - All other options default. + + ccr = ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS16 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS16 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ); + } + else + { + dprintf("DMA[M->M]: Single correction 1-byte burst size tranfer.\n"); + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - All other options default. + + ccr = ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ); + } + + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ccr); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + // At this point, there should be 0 - 7 1-byte transfers remaining. + + if (sizeleft) + { + dprintf("DMA[M->M]: Total post 1-byte burst size tranfer(s): %u.\n", sizeleft); + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SBx (Source burst length of [sizeleft] transfers) + // - DBx (Destination burst length of [sizeleft] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ((sizeleft - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((sizeleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } // if (size != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->M]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_zero_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * buf, + size_t size, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the size is zero, and no event is requested, just return success. + if ((size == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (size != 0) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)buf); + } + + dprintf("DMA[Z->M]: buf = %p.\n", buf); + dprintf("DMA[Z->M]: size = 0x%x.\n", size); + + size_t sizeleft = size; + + // First see how many byte(s) we need to transfer to get dst to be 8 byte aligned. + if ((uint32_t)buf & 0x7) + { + uint32_t aligncount = MIN(8 - ((uint32_t)buf & 0x7), sizeleft); + sizeleft -= aligncount; + + dprintf("DMA[Z->M]: Total pre-alignment 1-byte burst size tranfer(s): %lu.\n", aligncount); + + // Program in the following parameters: + // - DS8 (Destination burst size of 1-byte) + // - DBx (Destination burst length of [aligncount] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((aligncount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + } + + // This is the number of 8-byte bursts left + uint32_t burstcount = sizeleft >> 3; + + // Update the size left to transfer + sizeleft &= 0x7; + + dprintf("DMA[Z->M]: Total Main 8-byte burst size transfer(s): %lu.\n", burstcount); + dprintf("DMA[Z->M]: Total Main 1-byte burst size transfer(s): %u.\n", sizeleft); + + // Determine how many 16 length bursts can be done + if (burstcount >> 4) + { + uint32_t length16burstcount = burstcount >> 4; + burstcount &= 0xf; + + dprintf("DMA[Z->M]: Number of 16 burst length 8-byte transfer(s): %lu.\n", length16burstcount); + dprintf("DMA[Z->M]: Number of remaining 8-byte transfer(s): %lu.\n", burstcount); + + // Program in the following parameters: + // - DS64 (Destination burst size of 8-byte) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (length16burstcount > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(length16burstcount, 256); + length16burstcount -= loopcount; + + dprintf("DMA[Z->M]: Looping %lux 16 burst length 8-byte transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [burstcount] 8-byte transfer(s) + // remaining. [burstcount] should be less than 16. + + // Do one more burst with a SB / DB of length [burstcount]. + + if (burstcount) + { + // Program in the following parameters: + // - DS64 (Destination burst size of 8-byte) + // - DBx (Destination burst length of [burstlength] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((burstcount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + } + + // At this point, there should be 0 - 7 1-byte transfers remaining. + + if (sizeleft) + { + dprintf("DMA[Z->M]: Total post 1-byte burst size tranfer(s): %u.\n", sizeleft); + + // Program in the following parameters: + // - DS8 (Destination burst size of 1-byte) + // - DBx (Destination burst length of [sizeleft] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((sizeleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + } + } // if (size != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[Z->M]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_memory_to_register(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst_reg, + const void * src_buf, + size_t count, + uint32_t register_width_bits, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the count is zero, and no event is requested, just return success. + if ((count == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (count != 0) + { + // Verify valid register_width_bits and construct the CCR SS and DS parameters. + uint32_t ccr_ss_ds_mask = 0; + + if (status == ALT_E_SUCCESS) + { + switch (register_width_bits) + { + case 8: + // Program in the following parameters: + // - SS8 (Source burst size of 8 bits) + // - DS8 (Destination burst size of 8 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_DS8; + break; + case 16: + // Program in the following parameters: + // - SS16 (Source burst size of 16 bits) + // - DS16 (Destination burst size of 16 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS16 | ALT_DMA_CCR_OPT_DS16; + break; + case 32: + // Program in the following parameters: + // - SS32 (Source burst size of 32 bits) + // - DS32 (Destination burst size of 32 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS32 | ALT_DMA_CCR_OPT_DS32; + break; + case 64: + // Program in the following parameters: + // - SS64 (Source burst size of 64 bits) + // - DS64 (Destination burst size of 64 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS64 | ALT_DMA_CCR_OPT_DS64; + break; + default: + status = ALT_E_BAD_ARG; + break; + } + } + + // Verify that the dst_reg and src_buf are aligned to the register width + if (status == ALT_E_SUCCESS) + { + if (((uintptr_t)dst_reg & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else if (((uintptr_t)src_buf & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else + { + dprintf("DMA[M->R]: dst_reg = %p.\n", dst_reg); + dprintf("DMA[M->R]: src_buf = %p.\n", src_buf); + dprintf("DMA[M->R]: count = 0x%x.\n", count); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, (uint32_t)src_buf); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)dst_reg); + } + + // This is the remaining count left to process. + uint32_t countleft = count; + + // See how many 16-length bursts we can use + if (countleft >> 4) + { + // Program in the following parameters: + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - DAF (Destination address fixed) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + uint32_t length16burst = countleft >> 4; + countleft &= 0xf; + + dprintf("DMA[M->R]: Number of 16 burst length transfer(s): %lu.\n", length16burst); + dprintf("DMA[M->R]: Number of remaining transfer(s): %lu.\n", countleft); + + // See how many 256x 16-length bursts we can use + if (length16burst >> 8) + { + uint32_t loop256length16burst = length16burst >> 8; + length16burst &= ((1 << 8) - 1); + + dprintf("DMA[M->R]: Number of 256-looped 16 burst length transfer(s): %lu.\n", loop256length16burst); + dprintf("DMA[M->R]: Number of remaining 16 burst length transfer(s): %lu.\n", length16burst); + + while (loop256length16burst > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(loop256length16burst, 256); + loop256length16burst -= loopcount; + + dprintf("DMA[M->R]: Looping %lux super loop transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // The super loop above ensures that the length16burst is below 256. + if (length16burst > 0) + { + uint32_t loopcount = length16burst; + length16burst = 0; + + dprintf("DMA[M->R]: Looping %lux 16 burst length transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [countleft] transfer(s) remaining. + // [countleft] should be less than 16. + + if (countleft) + { + // Program in the following parameters: + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - DAF (Destination address fixed) + // - SBx (Source burst length of [countleft] transfer(s)) + // - DBx (Destination burst length of [countleft] transfer(s)) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->R]: Tail end %lux transfer(s).\n", countleft); + + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ((countleft - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((countleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (count != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->R]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->R]: DMAEND program.\n"); + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_register_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst_buf, + const void * src_reg, + size_t count, + uint32_t register_width_bits, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the count is zero, and no event is requested, just return success. + if ((count == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (count != 0) + { + // Verify valid register_width_bits and construct the CCR SS and DS parameters. + uint32_t ccr_ss_ds_mask = 0; + + if (status == ALT_E_SUCCESS) + { + switch (register_width_bits) + { + case 8: + // Program in the following parameters: + // - SS8 (Source burst size of 8 bits) + // - DS8 (Destination burst size of 8 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_DS8; + break; + case 16: + // Program in the following parameters: + // - SS16 (Source burst size of 16 bits) + // - DS16 (Destination burst size of 16 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS16 | ALT_DMA_CCR_OPT_DS16; + break; + case 32: + // Program in the following parameters: + // - SS32 (Source burst size of 32 bits) + // - DS32 (Destination burst size of 32 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS32 | ALT_DMA_CCR_OPT_DS32; + break; + case 64: + // Program in the following parameters: + // - SS64 (Source burst size of 64 bits) + // - DS64 (Destination burst size of 64 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS64 | ALT_DMA_CCR_OPT_DS64; + break; + default: + dprintf("DMA[R->M]: Invalid register width.\n"); + status = ALT_E_BAD_ARG; + break; + } + } + + // Verify that the dst_buf and src_reg are aligned to the register width + if (status == ALT_E_SUCCESS) + { + if (((uintptr_t)dst_buf & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else if (((uintptr_t)src_reg & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else + { + dprintf("DMA[R->M]: dst_reg = %p.\n", dst_buf); + dprintf("DMA[R->M]: src_buf = %p.\n", src_reg); + dprintf("DMA[R->M]: count = 0x%x.\n", count); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, (uint32_t)src_reg); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)dst_buf); + } + + // This is the remaining count left to process. + uint32_t countleft = count; + + // See how many 16-length bursts we can use + if (countleft >> 4) + { + uint32_t length16burst = countleft >> 4; + countleft &= 0xf; + + dprintf("DMA[R->M]: Number of 16 burst length transfer(s): %lu.\n", length16burst); + dprintf("DMA[R->M]: Number of remaining transfer(s): %lu.\n", countleft); + + // + // The algorithm uses the strategy described in PL330 B.2.3. + // Not sure if registers will accept burst transfers so read the register in its own transfer. + // + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // See how many 256x 16-length bursts we can do + if (length16burst >> 8) + { + uint32_t loop256length16burst = length16burst >> 8; + length16burst &= ((1 << 8) - 1); + + dprintf("DMA[R->M]: Number of 256-looped 16 burst length transfer(s): %lu.\n", loop256length16burst); + dprintf("DMA[R->M]: Number of remaining 16 burst length transfer(s): %lu.\n", length16burst); + + while (loop256length16burst > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(loop256length16burst, 256); + loop256length16burst -= loopcount; + + dprintf("DMA[R->M]: Looping %lux super loop transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // The super loop above ensures that the length16burst is below 256. + if (length16burst > 0) + { + uint32_t loopcount = length16burst; + length16burst = 0; + + dprintf("DMA[R->M]: Looping %lux 16 burst length transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [countleft] transfer(s) remaining. + // [countleft] should be less than 16. + + if (countleft) + { + dprintf("DMA[R->M]: Tail end %lux transfer(s).\n", countleft); + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - SBx (Source burst length of [countleft] transfer(s)) + // - DBx (Destination burst length of [countleft] transfer(s)) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ((countleft - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((countleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (count != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[R->M]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT +static ALT_STATUS_CODE alt_dma_memory_to_qspi(ALT_DMA_PROGRAM_t * program, + const char * src, + size_t size) +{ + if ((uintptr_t)src & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, + (uint32_t)ALT_QSPIDATA_ADDR); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, + (uint32_t)src); + } + + ///// + + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + uint32_t qspi_single_size_log2 = ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(dmaper); + uint32_t qspi_burst_size_log2 = ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(dmaper); + uint32_t qspi_single_size = 1 << qspi_single_size_log2; + uint32_t qspi_burst_size = 1 << qspi_burst_size_log2; + + dprintf("DMA[M->P][QSPI]: QSPI Single = %lu; Burst = %lu.\n", qspi_single_size, qspi_burst_size); + + // Because single transfers are equal or smaller than burst (and in the + // smaller case, it is always a clean multiple), only the single size + // check is needed for transfer composability. + if (size & (qspi_single_size - 1)) + { + dprintf("DMA[M->P][QSPI]: QSPI DMA size configuration not suitable for transfer request.\n"); + return ALT_E_ERROR; + } + + ///// + + if ((uintptr_t)src & 0x7) + { + // Source address is not 8-byte aligned. Do 1x 32-bit transfer to get it 8-byte aligned. + + dprintf("DMA[M->P][QSPI]: Creating 1x 4-byte aligning transfer.\n"); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAI + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + size -= sizeof(uint32_t); + } + + uint32_t qspi_single_count = 0; + uint32_t qspi_burst_count = size >> qspi_burst_size_log2; + + // Use QSPI burst transfers if: + // - QSPI bursts are larger than QSPI singles [AND] + // - Size is large enough that at least 1 burst will be used. + + if ( (qspi_burst_size_log2 > qspi_single_size_log2) + && (qspi_burst_count != 0) + ) + { + // qspi_burst_count = size >> qspi_burst_size_log2; + qspi_single_count = (size & (qspi_burst_size - 1)) >> qspi_single_size_log2; + + dprintf("DMA[M->P][QSPI][B]: Burst size = %lu bytes, count = %lu.\n", qspi_burst_size, qspi_burst_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t src_size_log2 = MIN(3, qspi_burst_size_log2); + + uint32_t src_length = 0; + uint32_t src_multiple = 0; + + if ((qspi_burst_size >> src_size_log2) <= 16) + { + src_length = qspi_burst_size >> src_size_log2; + src_multiple = 1; + } + else + { + src_length = 16; + src_multiple = (qspi_burst_size >> src_size_log2) >> 4; // divide by 16 + + if (src_multiple == 0) + { + dprintf("DEBUG[QSPI][B]: src_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t dst_length = 1; // dst_length is always 1 because the address is fixed. + uint32_t dst_multiple = qspi_burst_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[M->P][QSPI][B]: dst_size = %u bits, dst_length = %u, dst_multiple = %lu.\n", + 32, 1, dst_multiple); + dprintf("DMA[M->P][QSPI][B]: src_size = %u bits, src_length = %lu, src_multiple = %lu.\n", + (1 << src_size_log2) * 8, src_length, src_multiple); + + ///// + + // Program in the following parameters: + // - SAI (Source address increment) + // - SSx (Source burst size of [1 << src_size_log2]-bytes) + // - SBx (Source burst length of [src_length] transfer(s)) + // - DAF (Destination address fixed) + // - DS32 (Destination burst size of 4-bytes) + // - DB1 (Destination burst length of 1 transfer) + // - All other parameters default + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAI + | (src_size_log2 << 1) // SS + | ((src_length - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // NOTE: We do not do the 256x bursts for M->P case because we only + // write up to 256 B at a time. + + while (qspi_burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_burst_count, 256); + qspi_burst_count -= loopcount; + + dprintf("DMA[M->P][QSPI][B]: Creating %lu burst-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + else + { + qspi_single_count = size >> qspi_single_size_log2; + } + + // Assemble the single portion of the DMA program. + if (qspi_single_count) + { + dprintf("DMA[M->P][QSPI][S]: Single size = %lu bytes, count = %lu.\n", qspi_single_size, qspi_single_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t src_size_log2 = MIN(3, qspi_single_size_log2); + + uint32_t src_length = 0; + uint32_t src_multiple = 0; + + if ((qspi_single_size >> src_size_log2) <= 16) + { + src_length = qspi_single_size >> src_size_log2; + src_multiple = 1; + } + else + { + src_length = 16; + src_multiple = (qspi_single_size >> src_size_log2) >> 4; // divide by 16 + + if (src_multiple == 0) + { + dprintf("DEBUG[QSPI][S]: src_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t dst_length = 1; // dst_length is always 1 becaus the address is fixed. + uint32_t dst_multiple = qspi_single_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[M->P][QSPI][S]: dst_size = %u bits, dst_length = %u, dst_multiple = %lu.\n", + 32, 1, dst_multiple); + dprintf("DMA[M->P][QSPI][S]: src_size = %u bits, src_length = %lu, src_multiple = %lu.\n", + (1 <P case because we only + // write up to 256 B at a time. + + while (qspi_single_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_single_count, 256); + qspi_single_count -= loopcount; + + dprintf("DMA[M->P][QSPI][S]: Creating %lu single-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (qspi_single_count != 0) + + return status; +} + +static ALT_STATUS_CODE alt_dma_qspi_to_memory(ALT_DMA_PROGRAM_t * program, + char * dst, + size_t size) +{ + if ((uintptr_t)dst & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, + (uint32_t)dst); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, + (uint32_t)ALT_QSPIDATA_ADDR); + } + + ///// + + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + uint32_t qspi_single_size_log2 = ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(dmaper); + uint32_t qspi_burst_size_log2 = ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(dmaper); + uint32_t qspi_single_size = 1 << qspi_single_size_log2; + uint32_t qspi_burst_size = 1 << qspi_burst_size_log2; + + dprintf("DMA[P->M][QSPI]: QSPI Single = %lu; Burst = %lu.\n", qspi_single_size, qspi_burst_size); + + // Because single transfers are equal or smaller than burst (and in the + // smaller case, it is always a clean multiple), only the single size + // check is needed for transfer composability. + if (size & (qspi_single_size - 1)) + { + dprintf("DMA[P->M][QSPI]: QSPI DMA size configuration not suitable for transfer request.\n"); + return ALT_E_ERROR; + } + + ///// + + if ((uintptr_t)dst & 0x7) + { + // Destination address is not 8-byte aligned. Do 1x 32-bit transfer to get it 8-byte aligned. + + dprintf("DMA[P->M][QSPI]: Creating 1x 4-byte aligning transfer.\n"); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAI + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + size -= sizeof(uint32_t); + } + + uint32_t qspi_single_count = 0; + uint32_t qspi_burst_count = size >> qspi_burst_size_log2; + + // Use QSPI burst transfers if: + // - QSPI bursts are larger than QSPI singles [AND] + // - Size is large enough that at least 1 burst will be used. + + if ( (qspi_burst_size_log2 > qspi_single_size_log2) + && (qspi_burst_count != 0) + ) + { + // qspi_burst_count = size >> qspi_burst_size_log2; + qspi_single_count = (size & (qspi_burst_size - 1)) >> qspi_single_size_log2; + + dprintf("DMA[P->M][QSPI][B]: Burst size = %lu bytes, count = %lu.\n", qspi_burst_size, qspi_burst_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t dst_size_log2 = MIN(3, qspi_burst_size_log2); + + uint32_t dst_length = 0; + uint32_t dst_multiple = 0; + + if ((qspi_burst_size >> dst_size_log2) <= 16) + { + dst_length = qspi_burst_size >> dst_size_log2; + dst_multiple = 1; + } + else + { + dst_length = 16; + dst_multiple = (qspi_burst_size >> dst_size_log2) >> 4; // divide by 16 + + if (dst_multiple == 0) + { + dprintf("DEBUG[QSPI][B]: dst_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t src_length = 1; // src_length is always 1 because the address is fixed. + uint32_t src_multiple = qspi_burst_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[P->M][QSPI][B]: dst_size = %u bits, dst_length = %lu, dst_multiple = %lu.\n", + (1 << dst_size_log2) * 8, dst_length, dst_multiple); + dprintf("DMA[P->M][QSPI][B]: src_size = %u bits, src_length = %u, src_multiple = %lu.\n", + 32, 1, src_multiple); + + ///// + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SS32 (Source burst size of 4-bytes) + // - SB1 (Source burst length of 1 transfer) + // - DAI (Destination address increment) + // - DSx (Destination burst size of [1 << dst_size_log2]-bytes]) + // - DBx (Destination burst length of [dst_length] transfer(s)) + // - All other parameters default + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAI + | (dst_size_log2 << 15) // DS + | ((dst_length - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // See how many 256x bursts we can construct. This will allow for extremely large requests. + + if (qspi_burst_count >> 8) + { + uint32_t qspi_burst256_count = qspi_burst_count >> 8; + qspi_burst_count &= (1 << 8) - 1; + + while (qspi_burst256_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_burst256_count, 256); + qspi_burst256_count -= loopcount; + + dprintf("DMA[P->M][QSPI][B]: Creating %lu 256x burst-type transfer(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + // Inner loop { + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Outer loop + } + } + + while (qspi_burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_burst_count, 256); + qspi_burst_count -= loopcount; + + dprintf("DMA[P->M][QSPI][B]: Creating %lu burst-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + else + { + qspi_single_count = size >> qspi_single_size_log2; + } + + // Assemble the single portion of the DMA program. + if (qspi_single_count) + { + dprintf("DMA[P->M][QSPI][S]: Single size = %lu bytes, count = %lu.\n", qspi_single_size, qspi_single_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t dst_size_log2 = MIN(3, qspi_single_size_log2); + + uint32_t dst_length = 0; + uint32_t dst_multiple = 0; + + if ((qspi_single_size >> dst_size_log2) <= 16) + { + dst_length = qspi_single_size >> dst_size_log2; + dst_multiple = 1; + } + else + { + dst_length = 16; + dst_multiple = (qspi_single_size >> dst_size_log2) >> 4; // divide by 16 + + if (dst_multiple == 0) + { + dprintf("DEBUG[QSPI][S]: dst_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t src_length = 1; // src_length is always 1 because the address is fixed. + uint32_t src_multiple = qspi_single_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[P->M][QSPI][S]: dst_size = %u bits, dst_length = %lu, dst_multiple = %lu.\n", + (1 << dst_size_log2) * 8, dst_length, dst_multiple); + dprintf("DMA[P->M][QSPI][S]: src_size = %u bits, src_length = %u, src_multiple = %lu.\n", + 32, 1, src_multiple); + + ///// + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SS32 (Source burst size of 4-bytes) + // - SB1 (Source burst length of 1 transfer) + // - DAI (Destination address increment) + // - DSx (Destination burst size of [1 << dst_size_log2]-bytes]) + // - DBx (Destination burst length of [dst_length] transfer(s)) + // - All other parameters default + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAI + | (dst_size_log2 << 15) // DS + | ((dst_length - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // See how many 256x bursts we can construct. This will allow for extremely large requests. + + if (qspi_single_count >> 8) + { + uint32_t qspi_single256_count = qspi_single_count >> 8; + qspi_single_count &= (1 << 8) - 1; + + while (qspi_single256_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_single256_count, 256); + qspi_single256_count -= loopcount; + + dprintf("DMA[P->M][QSPI][S]: Creating %lu 256x single-type transfer(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + // Inner loop { + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Outer loop + } + } + + while (qspi_single_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_single_count, 256); + qspi_single_count -= loopcount; + + dprintf("DMA[P->M][QSPI][S]: Creating %lu single-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (qspi_single_count != 0) + + return status; +} +#endif // ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT +static ALT_STATUS_CODE alt_dma_memory_to_16550_single(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - DAF (Destination address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + uint32_t sizeleft = size; + + while (sizeleft > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(sizeleft, 256); + sizeleft -= loopcount; + + dprintf("DMA[M->P][16550][S]: Creating %lu transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_memory_to_16550_burst(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t burst_size, + size_t burst_count) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - DAF (Source address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(burst_count, 256); + burst_count -= loopcount; + + dprintf("DMA[M->P][16550][B]: Creating outer %lu inner loop(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // Inner loop { + + // Loop [burst_size / 16] times. The burst_size was trimmed to the + // nearest multiple of 16 by the caller. Each burst does 16 transfers + // hence the need for the divide. + + dprintf("DMA[M->P][16550][B]: Creating inner %u transfer(s).\n", burst_size >> 4); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, burst_size >> 4); // divide by 16. + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Outer loop + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_memory_to_16550(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + ALT_16550_HANDLE_t * handle, + const void * src, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, + (uint32_t)ALT_UART_RBR_THR_DLL_ADDR(handle->location)); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, + (uint32_t)src); + } + + // Determine if FIFOs are enabled from the FCR cache + + if (ALT_UART_FCR_FIFOE_GET(handle->fcr) != 0) + { + dprintf("DMA[M->P][16550]: FIFOs enabled.\n"); + + // + // FIFOs are enabled. + // + + uint32_t tx_size; + uint32_t burst_size; + ALT_16550_FIFO_TRIGGER_TX_t trig_tx; + + // Get the TX FIFO Size + // Use the register interface to avoid coupling the 16550 and DMA. + tx_size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + + // Get the TX FIFO Trigger Level from the FCR cache + trig_tx = (ALT_16550_FIFO_TRIGGER_TX_t)ALT_UART_FCR_TET_GET(handle->fcr); + + switch (trig_tx) + { + case ALT_16550_FIFO_TRIGGER_TX_EMPTY: + burst_size = tx_size; + break; + case ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY: + burst_size = tx_size - 2; + break; + case ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL: + burst_size = 3 * (tx_size >> 2); + break; + case ALT_16550_FIFO_TRIGGER_TX_HALF_FULL: + burst_size = tx_size >> 1; + break; + default: + // This case should never happen. + return ALT_E_ERROR; + } + + if (burst_size < 16) + { + // There's no point bursting 1 byte at a time per notify, so just do single transfers. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_single(program, + periph, + size); + } + } + else + { + uint32_t sizeleft = size; + + // Now trip the burst size to a multiple of 16. + // This will optimize the bursting in the fewest possible commands. + dprintf("DMA[M->P][16550]: Untrimmed burst size = %lu.\n", burst_size); + burst_size &= ~0xf; + dprintf("DMA[M->P][16550]: Trimmed burst size = %lu.\n", burst_size); + + // Determine how many burst transfers can be done + uint32_t burst_count = 0; + + burst_count = sizeleft / burst_size; + sizeleft -= burst_count * burst_size; + + if (burst_count == 0) + { + // Do the transfer + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_single(program, + periph, + sizeleft); + } + } + else + { + // Do the burst transfers + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_burst(program, + periph, + burst_size, + burst_count); + } + + // Program the DMA engine to transfer the non-burstable items in single tranfers + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_single(program, + periph, + sizeleft); + } + + } // else if (burst_count == 0) + } + } + else + { + dprintf("DMA[M->P][16550]: FIFOs disabled.\n"); + + // + // FIFOs are disabled. + // + + status = alt_dma_memory_to_16550_single(program, + periph, + size); + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_16550_to_memory_single(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - SAF (Source address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + uint32_t sizeleft = size; + + while (sizeleft > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(sizeleft, 256); + sizeleft -= loopcount; + + dprintf("DMA[P->M][16550][S]: Creating %lu transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_16550_to_memory_burst(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t burst_size, + size_t burst_count) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - SAF (Source address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(burst_count, 256); + burst_count -= loopcount; + + dprintf("DMA[P->M][16550][B]: Creating outer %lu inner loop(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // Inner loop { + + // Loop [burst_size / 16] times. The burst_size was trimmed to the + // nearest multiple of 16 by the caller. Each burst does 16 transfers + // hence the need for the divide. + + dprintf("DMA[P->M][16550][B]: Creating inner %u transfer(s).\n", burst_size >> 4); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, burst_size >> 4); // divide by 16. + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Outer loop + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_16550_to_memory(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + ALT_16550_HANDLE_t * handle, + void * dst, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)dst); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, (uint32_t)ALT_UART_RBR_THR_DLL_ADDR(handle->location)); + } + + // Determine if FIFOs are enabled from the FCR cache + + if (ALT_UART_FCR_FIFOE_GET(handle->fcr) != 0) + { + dprintf("DMA[P->M][16550]: FIFOs enabled.\n"); + + // + // FIFOs are enabled. + // + + uint32_t rx_size; + uint32_t burst_size; + ALT_16550_FIFO_TRIGGER_RX_t trig_rx; + + // Get the RX FIFO Size + // Use the register interface to avoid coupling the 16550 and DMA. + rx_size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + + // Get the RX FIFO Trigger Level from the FCR cache + trig_rx = (ALT_16550_FIFO_TRIGGER_RX_t)ALT_UART_FCR_RT_GET(handle->fcr); + + switch (trig_rx) + { + case ALT_16550_FIFO_TRIGGER_RX_ANY: + burst_size = 1; + break; + case ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL: + burst_size = rx_size >> 2; // divide by 4 + break; + case ALT_16550_FIFO_TRIGGER_RX_HALF_FULL: + burst_size = rx_size >> 1; // divide by 2 + break; + case ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL: + burst_size = rx_size - 2; + break; + default: + // This case should never happen. + return ALT_E_ERROR; + } + + if (burst_size < 16) + { + // There's no point bursting 1 byte at a time per notify, so just do single transfers. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_single(program, + periph, + size); + } + } + else + { + uint32_t sizeleft = size; + + // Now trim the burst size to a multiple of 16. + // This will optimize the bursting in the fewest possible commands. + dprintf("DMA[P->M][16550]: Untrimmed burst size = %lu.\n", burst_size); + burst_size &= ~0xf; + dprintf("DMA[P->M][16550]: Trimmed burst size = %lu.\n", burst_size); + + // Determine how many burst transfers can be done + uint32_t burst_count = 0; + + burst_count = sizeleft / burst_size; + sizeleft -= burst_count * burst_size; + + if (burst_count == 0) + { + // Do the transfer. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_single(program, + periph, + sizeleft); + } + } + else + { + // Do the burst transfers + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_burst(program, + periph, + burst_size, + burst_count); + } + + // Program the DMA engine to transfer the non-burstable items in single transfers. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_single(program, + periph, + sizeleft); + } + + } // if (burst_count == 0) + } + } + else + { + dprintf("DMA[P->M][16550]: FIFOs disabled.\n"); + + // + // FIFOs are disabled. + // + + status = alt_dma_16550_to_memory_single(program, + periph, + size); + } + + return status; +} +#endif // ALT_DMA_PERIPH_PROVISION_16550_SUPPORT + +ALT_STATUS_CODE alt_dma_memory_to_periph(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t dstp, + const void * src, + size_t size, + void * periph_info, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if ((size == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->P]: Init Program.\n"); + status = alt_dma_program_init(program); + } + + if ((status == ALT_E_SUCCESS) && (size != 0)) + { + switch (dstp) + { +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT + case ALT_DMA_PERIPH_QSPI_FLASH_TX: + status = alt_dma_memory_to_qspi(program, src, size); + break; +#endif + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT + case ALT_DMA_PERIPH_UART0_TX: + case ALT_DMA_PERIPH_UART1_TX: + status = alt_dma_memory_to_16550(program, dstp, + (ALT_16550_HANDLE_t *)periph_info, src, size); + break; +#endif + + case ALT_DMA_PERIPH_FPGA_0: + case ALT_DMA_PERIPH_FPGA_1: + case ALT_DMA_PERIPH_FPGA_2: + case ALT_DMA_PERIPH_FPGA_3: + case ALT_DMA_PERIPH_FPGA_4: + case ALT_DMA_PERIPH_FPGA_5: + case ALT_DMA_PERIPH_FPGA_6: + case ALT_DMA_PERIPH_FPGA_7: + case ALT_DMA_PERIPH_I2C0_TX: + case ALT_DMA_PERIPH_I2C1_TX: + case ALT_DMA_PERIPH_I2C2_TX: + case ALT_DMA_PERIPH_I2C3_TX: + case ALT_DMA_PERIPH_SPI0_MASTER_TX: + case ALT_DMA_PERIPH_SPI0_SLAVE_TX: + case ALT_DMA_PERIPH_SPI1_MASTER_TX: + case ALT_DMA_PERIPH_SPI1_SLAVE_TX: + + default: + status = ALT_E_BAD_ARG; + break; + } + } + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->P]: Adding event.\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_periph_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst, + ALT_DMA_PERIPH_t srcp, + size_t size, + void * periph_info, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if ((size == 0) && (send_evt == false)) + { + return ALT_E_SUCCESS; + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[P->M]: Init Program.\n"); + status = alt_dma_program_init(program); + } + + if ((status == ALT_E_SUCCESS) && (size != 0)) + { + switch (srcp) + { +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT + case ALT_DMA_PERIPH_QSPI_FLASH_RX: + status = alt_dma_qspi_to_memory(program, dst, size); + break; +#endif + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT + case ALT_DMA_PERIPH_UART0_RX: + case ALT_DMA_PERIPH_UART1_RX: + status = alt_dma_16550_to_memory(program, srcp, + (ALT_16550_HANDLE_t *)periph_info, dst, size); + break; +#endif + + case ALT_DMA_PERIPH_FPGA_0: + case ALT_DMA_PERIPH_FPGA_1: + case ALT_DMA_PERIPH_FPGA_2: + case ALT_DMA_PERIPH_FPGA_3: + case ALT_DMA_PERIPH_FPGA_4: + case ALT_DMA_PERIPH_FPGA_5: + case ALT_DMA_PERIPH_FPGA_6: + case ALT_DMA_PERIPH_FPGA_7: + case ALT_DMA_PERIPH_I2C0_RX: + case ALT_DMA_PERIPH_I2C1_RX: + case ALT_DMA_PERIPH_I2C2_RX: + case ALT_DMA_PERIPH_I2C3_RX: + case ALT_DMA_PERIPH_SPI0_MASTER_RX: + case ALT_DMA_PERIPH_SPI0_SLAVE_RX: + case ALT_DMA_PERIPH_SPI1_MASTER_RX: + case ALT_DMA_PERIPH_SPI1_SLAVE_RX: + + default: + status = ALT_E_BAD_ARG; + break; + } + } + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[P->M]: Adding event.\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + + return alt_dma_channel_exec(channel, program); +} + +///// + +static bool alt_dma_is_init(void) +{ + uint32_t permodrst = alt_read_word(ALT_RSTMGR_PERMODRST_ADDR); + + if (permodrst & ALT_RSTMGR_PERMODRST_DMA_SET_MSK) + { + return false; + } + else + { + return true; + } +} + +ALT_STATUS_CODE alt_dma_ecc_start(void * block, size_t size) +{ + if (alt_dma_is_init() == false) + { + return ALT_E_ERROR; + } + + if ((uintptr_t)block & (sizeof(uint64_t) - 1)) + { + return ALT_E_ERROR; + } + + // Verify that all channels are either unallocated or allocated and idle. + + for (int i = 0; i < ARRAY_COUNT(channel_info_array); ++i) + { + if (channel_info_array[i].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED) + { + ALT_DMA_CHANNEL_STATE_t state; + alt_dma_channel_state_get((ALT_DMA_CHANNEL_t)i, &state); + + if (state != ALT_DMA_CHANNEL_STATE_STOPPED) + { + dprintf("DMA[ECC]: Error: Channel %d state is non-stopped (%d).\n", i, (int)state); + return ALT_E_ERROR; + } + } + } + + ///// + + // Enable ECC for DMA RAM + + dprintf("DEBUG[DMA][ECC]: Enable ECC in SysMgr.\n"); + alt_write_word(ALT_SYSMGR_ECC_DMA_ADDR, ALT_SYSMGR_ECC_DMA_EN_SET_MSK); + + // Clear any pending spurious DMA ECC interrupts. + + dprintf("DEBUG[DMA][ECC]: Clear any pending spurious ECC status in SysMgr.\n"); + alt_write_word(ALT_SYSMGR_ECC_DMA_ADDR, + ALT_SYSMGR_ECC_DMA_EN_SET_MSK + | ALT_SYSMGR_ECC_DMA_SERR_SET_MSK + | ALT_SYSMGR_ECC_DMA_DERR_SET_MSK); + + return ALT_E_SUCCESS; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma_program.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma_program.c new file mode 100644 index 0000000..26de4c7 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma_program.c @@ -0,0 +1,1064 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_dma_program.h" +#include "alt_cache.h" +#include + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) + +///// + +// +// The following section describes how the bits are used in the "flag" field: +// + +// [17:16] Which loop registers (LOOP0, LOOP1) are currently being used by a +// partially assembled program. LOOP0 is always used before LOOP1. LOOP1 is +// always ended before LOOP0. +#define ALT_DMA_PROGRAM_FLAG_LOOP0 (1UL << 16) +#define ALT_DMA_PROGRAM_FLAG_LOOP1 (1UL << 17) +#define ALT_DMA_PROGRAM_FLAG_LOOP_ALL (ALT_DMA_PROGRAM_FLAG_LOOP0 | ALT_DMA_PROGRAM_FLAG_LOOP1) + +// [18] Flag that marks LOOP0 as a forever loop. Said another way, LOOP0 is +// being used to execute the DMALPFE directive. +#define ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE (1UL << 18) +// [19] Flag that marks LOOP1 as a forever loop. Said another way, LOOP1 is +// being used to execute the DMALPFE directive. +#define ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE (1UL << 19) + +// [24] Flag that the first SAR has been programmed. The SAR field is valid and +// is the offset from the start of the buffer where SAR is located. +#define ALT_DMA_PROGRAM_FLAG_SAR (1UL << 24) +// [25] Flag that the first DAR has been programmed. The DAR field is valid and +// is the offset from the start of the buffer where DAR is located. +#define ALT_DMA_PROGRAM_FLAG_DAR (1UL << 25) + +// [31] Flag that marks the last assembled instruction as DMAEND. +#define ALT_DMA_PROGRAM_FLAG_ENDED (1UL << 31) + +///// + +ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm) +{ + // Clear the variables that matter. + pgm->flag = 0; + pgm->code_size = 0; + + // Calculate the cache aligned start location of the buffer. + size_t buffer = (size_t)pgm->program; + size_t offset = ((buffer + ALT_DMA_PROGRAM_CACHE_LINE_SIZE - 1) & ~(ALT_DMA_PROGRAM_CACHE_LINE_SIZE - 1)) - buffer; + + // It is safe to cast to uint16_t because the extra offset can only be up to + // (ALT_DMA_PROGRAM_CACHE_LINE_SIZE - 1) or 31, which is within range of the + // uint16_t. + pgm->buffer_start = (uint16_t)offset; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm) +{ + // Clear the variables that matter + pgm->flag = 0; + pgm->code_size = 0; + + return ALT_E_SUCCESS; +} + +__attribute__((weak)) ALT_STATUS_CODE alt_cache_system_clean(void * address, size_t length) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm) +{ + // Verify that at least one instruction is in the buffer + if (pgm->code_size == 0) + { + return ALT_E_ERROR; + } + + // Verify all loops are completed. + if (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + return ALT_E_ERROR; + } + + // Verify last item is DMAEND + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_ENDED)) + { + return ALT_E_ERROR; + } + + // Sync the DMA program to RAM. + void * vaddr = (void *)((uintptr_t)(pgm->program + pgm->buffer_start) & ~(ALT_CACHE_LINE_SIZE - 1)); + size_t length = (pgm->code_size + ALT_CACHE_LINE_SIZE) & ~(ALT_CACHE_LINE_SIZE - 1); + + dprintf("DEBUG[DMAP]: Program (real) @ %p, length = 0x%x.\n", pgm->program + pgm->buffer_start, pgm->code_size); + dprintf("DEBUG[DMAP]: Clean: addr = %p, length = 0x%x.\n", vaddr, length); + + return alt_cache_system_clean(vaddr, length); +} + +ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, + uint32_t current, uint32_t * progress) +{ + // Pointer to where the register is initialized in the program buffer. + uint8_t * buffer = NULL; + + switch (reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_SAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->sar; + break; + + case ALT_DMA_PROGRAM_REG_DAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_DAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->dar; + break; + + default: + return ALT_E_BAD_ARG; + } + + uint32_t initial = + (buffer[3] << 24) | + (buffer[2] << 16) | + (buffer[1] << 8) | + (buffer[0] << 0); + + *progress = current - initial; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, uint32_t val) +{ + uint8_t * buffer = NULL; + + switch (reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_SAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->sar; + break; + + case ALT_DMA_PROGRAM_REG_DAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_DAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->dar; + break; + + default: + return ALT_E_BAD_ARG; + } + + buffer[0] = (uint8_t)((val >> 0) & 0xff); + buffer[1] = (uint8_t)((val >> 8) & 0xff); + buffer[2] = (uint8_t)((val >> 16) & 0xff); + buffer[3] = (uint8_t)((val >> 24) & 0xff); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val) +{ + // For information on DMAADDH, see PL330, section 4.3.1. + + // Check for sufficient space in buffer + if ((pgm->code_size + 3) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid register; construct instruction modifier. + uint8_t ra_mask = 0; + switch (addr_reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + ra_mask = 0x0; + break; + case ALT_DMA_PROGRAM_REG_DAR: + ra_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAADDH + buffer[0] = 0x54 | ra_mask; + buffer[1] = (uint8_t)(val & 0xff); + buffer[2] = (uint8_t)(val >> 8); + + // Update the code size. + pgm->code_size += 3; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val) +{ + // For information on DMAADNH, see PL330, section 4.3.2. + + // Check for sufficient space in buffer + if ((pgm->code_size + 3) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid register; construct instruction modifier. + uint8_t ra_mask = 0; + switch (addr_reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + ra_mask = 0x0; + break; + case ALT_DMA_PROGRAM_REG_DAR: + ra_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAADNH + buffer[0] = 0x5c | ra_mask; + buffer[1] = (uint8_t)(val & 0xff); + buffer[2] = (uint8_t)(val >> 8); + + // Update the code size. + pgm->code_size += 3; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMAEND, see PL330, section 4.3.3. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAEND + buffer[0] = 0x00; + + // Update the code size. + pgm->code_size += 1; + + // Mark program as ended. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_ENDED; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph) +{ + // For information on DMAFLUSHP, see PL330, section 4.3.4. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAFLUSHP + buffer[0] = 0x35; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_CHANNEL_t channel, uint32_t val, + ALT_DMA_SECURITY_t sec) +{ + // For information on DMAGO, see PL330, section 4.3.5. + + // Check for sufficient space in buffer + if ((pgm->code_size + 6) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify security; construct ns mask value + uint8_t ns_mask = 0; + switch (sec) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + ns_mask = 0x0; + break; + case ALT_DMA_SECURITY_NONSECURE: + ns_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAGO + buffer[0] = 0xa0 | ns_mask; + buffer[1] = (uint8_t)channel; + buffer[2] = (uint8_t)((val >> 0) & 0xff); + buffer[3] = (uint8_t)((val >> 8) & 0xff); + buffer[4] = (uint8_t)((val >> 16) & 0xff); + buffer[5] = (uint8_t)((val >> 24) & 0xff); + + // Update the code size. + pgm->code_size += 6; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMAKILL, see PL330, section 4.3.6. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAKILL + buffer[0] = 0x01; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMALD, see PL330, section 4.3.7. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs, x mask value. + uint8_t bsx_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_NONE: + bsx_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsx_mask = 0x1; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsx_mask = 0x3; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALD + buffer[0] = 0x04 | bsx_mask; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph) +{ + // For information on DMALDP, see PL330, section 4.3.8. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs mask value. + uint8_t bs_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bs_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bs_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALDP + buffer[0] = 0x25 | bs_mask; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm, + uint32_t iterations) +{ + // For information on DMALP, see PL330, section 4.3.9. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify iterations in range + if ((iterations == 0) || (iterations > 256)) + { + return ALT_E_BAD_ARG; + } + + // Find suitable LOOPx register to use; construct lc mask value. + uint8_t lc_mask = 0; + switch (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + case 0: // No LOOPx in use. Use LOOP0. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP0; + pgm->loop0 = pgm->code_size + 2; // This is the first instruction after the DMALP + lc_mask = 0x0; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP0: // LOOP0 in use. Use LOOP1. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP1; + pgm->loop1 = pgm->code_size + 2; // This is the first instruction after the DMALP + lc_mask = 0x2; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP_ALL: // All LOOPx in use. Report error. + return ALT_E_BAD_OPERATION; + + default: // Catastrophic error !!! + return ALT_E_ERROR; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALP + buffer[0] = 0x20 | lc_mask; + buffer[1] = (uint8_t)(iterations - 1); + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMALPEND, see PL330, section 4.3.10. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs, x mask value. + uint8_t bsx_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_NONE: + bsx_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsx_mask = 0x1; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsx_mask = 0x3; + break; + default: + return ALT_E_BAD_ARG; + } + + // Determine the loop to end, if it is a forever loop; construct lc mask, nf mask, and backwards jump value. + uint8_t lc_mask = 0; + uint8_t nf_mask = 0; + uint16_t backwards_jump = 0; + switch (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + case ALT_DMA_PROGRAM_FLAG_LOOP0: // LOOP0 in use. End LOOP0. + + backwards_jump = pgm->code_size - pgm->loop0; + + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP0; + pgm->loop0 = 0; + + lc_mask = 0x0; + + if (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE) + { + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE; + } + else + { + nf_mask = 0x10; + } + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP_ALL: // All LOOPx in use. End LOOP1. + + backwards_jump = pgm->code_size - pgm->loop1; + + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP1; + pgm->loop1 = 0; + + lc_mask = 0x4; + + if (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE) + { + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE; + } + else + { + nf_mask = 0x10; + } + break; + + case 0: // No LOOPx in use. Report error! + return ALT_E_BAD_OPERATION; + + default: // Catastrophic error !!! + return ALT_E_ERROR; + } + + // Verify that the jump size is suitable + if (backwards_jump > 255) + { + return ALT_E_ARG_RANGE; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALPEND + buffer[0] = 0x28 | nf_mask | lc_mask | bsx_mask; + buffer[1] = (uint8_t)(backwards_jump); + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMALPFE, see PL330, section 4.3.11. + + // Find suitable LOOPx register to use; + switch (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + case 0: // No LOOPx in use. Use LOOP0. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP0; + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE; + pgm->loop0 = pgm->code_size; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP0: // LOOP0 in use. Use LOOP1. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP1; + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE; + pgm->loop1 = pgm->code_size; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP_ALL: // All LOOPx in use. Report error. + return ALT_E_BAD_OPERATION; + + default: // Catastrophic error !!! + return ALT_E_ERROR; + } + + // Nothing to assemble. + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val) +{ + // For information on DMAMOV, see PL330, section 4.3.12. + + // Check for sufficient space in buffer + if ((pgm->code_size + 6) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify channel register; construct rd mask value + uint8_t rd_mask = 0; + switch (chan_reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + rd_mask = 0; + // If SAR has not been set before, mark the location of where SAR is in the buffer. + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_SAR)) + { + pgm->flag |= ALT_DMA_PROGRAM_FLAG_SAR; + pgm->sar = pgm->code_size + 2; + } + break; + + case ALT_DMA_PROGRAM_REG_CCR: + rd_mask = 1; + break; + + case ALT_DMA_PROGRAM_REG_DAR: + rd_mask = 2; + // If DAR has not been set before, mark the location of where DAR is in the buffer. + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_DAR)) + { + pgm->flag |= ALT_DMA_PROGRAM_FLAG_DAR; + pgm->dar = pgm->code_size + 2; + } + break; + + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAMOV + buffer[0] = 0xbc;; + buffer[1] = rd_mask; + buffer[2] = (uint8_t)((val >> 0) & 0xff); + buffer[3] = (uint8_t)((val >> 8) & 0xff); + buffer[4] = (uint8_t)((val >> 16) & 0xff); + buffer[5] = (uint8_t)((val >> 24) & 0xff); + + // Update the code size. + pgm->code_size += 6; + + return ALT_E_SUCCESS; + +} + +ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMANOP, see PL330, section 4.3.13. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMANOP + buffer[0] = 0x18; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMARMB, see PL330, section 4.3.14. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMARMB + buffer[0] = 0x12; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt) +{ + // For information on DMA, see PL330, section 4.3.15. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Validate evt selection + switch (evt) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMASEV + buffer[0] = 0x34; + buffer[1] = (uint8_t)(evt) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMAST, see PL330, section 4.3.16. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs, x mask value. + uint8_t bsx_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_NONE: + bsx_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsx_mask = 0x1; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsx_mask = 0x3; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAST + buffer[0] = 0x08 | bsx_mask; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph) +{ + // For information on DMASTP, see PL330, section 4.3.17. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs mask value. + uint8_t bs_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bs_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bs_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMASTP + buffer[0] = 0x29 | bs_mask; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMASTZ, see PL330, section 4.3.18. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMASTZ + buffer[0] = 0x0c; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt, bool invalid) +{ + // For information on DMAWFE, see PL330, section 4.3.19. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Validate evt selection + switch (evt) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // Construct i mask value + uint8_t i_mask = 0; + if (invalid) + { + i_mask = 0x2; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAWFE + buffer[0] = 0x36; + buffer[1] = ((uint8_t)(evt) << 3) | i_mask; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMAWFP, see PL330, section 4.3.20. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Verify instruction modifier; construct bs, p mask value. + uint8_t bsp_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsp_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsp_mask = 0x2; + break; + case ALT_DMA_PROGRAM_INST_MOD_PERIPH: + bsp_mask = 0x1; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAWFP + buffer[0] = 0x30 | bsp_mask; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMAWMB, see PL330, section 4.3.21. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAWMB + buffer[0] = 0x13; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_qspi.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_qspi.c new file mode 100644 index 0000000..458ef71 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_qspi.c @@ -0,0 +1,2619 @@ +/****************************************************************************** +* +* alt_qspi.c - API for the Altera SoC FPGA QSPI device. +* +******************************************************************************/ + +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include +#include +#include +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "alt_qspi.h" +#include "alt_qspi_private.h" +#include "socal/alt_qspi.h" +#include "socal/alt_rstmgr.h" +#include "socal/alt_sysmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf printf + +///// + +#define MIN(a, b) ((a) > (b) ? (b) : (a)) + +// qspi_clk operating frequency range. +#define ALT_QSPI_CLK_FREQ_MIN ((alt_freq_t)0) +#define ALT_QSPI_CLK_FREQ_MAX ((alt_freq_t)432000000) + +// The set of all valid QSPI controller interrupt status mask values. +#define ALT_QSPI_INT_STATUS_ALL ( \ + ALT_QSPI_INT_STATUS_MODE_FAIL | \ + ALT_QSPI_INT_STATUS_UFL | \ + ALT_QSPI_INT_STATUS_IDAC_OP_COMPLETE | \ + ALT_QSPI_INT_STATUS_IDAC_OP_REJECT | \ + ALT_QSPI_INT_STATUS_WR_PROT_VIOL | \ + ALT_QSPI_INT_STATUS_ILL_AHB_ACCESS | \ + ALT_QSPI_INT_STATUS_IDAC_WTRMK_TRIG | \ + ALT_QSPI_INT_STATUS_RX_OVF | \ + ALT_QSPI_INT_STATUS_TX_FIFO_NOT_FULL | \ + ALT_QSPI_INT_STATUS_TX_FIFO_FULL | \ + ALT_QSPI_INT_STATUS_RX_FIFO_NOT_EMPTY | \ + ALT_QSPI_INT_STATUS_RX_FIFO_FULL | \ + ALT_QSPI_INT_STATUS_IDAC_RD_FULL \ + ) + +static uint32_t qspi_device_size = 0; + +///// + +static ALT_STATUS_CODE alt_qspi_device_status(uint32_t * status) +{ + // Read flag status register through STIG + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_RDSR, 0, 1, status, 10000); +} + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +static ALT_STATUS_CODE alt_qspi_N25Q_device_flag(uint32_t * flagsr) +{ + if (qspi_device_size < 0x4000000) + { + return ALT_E_SUCCESS; + } + + // Read flag status register through STIG + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_RDFLGSR, 0, 1, flagsr, 10000); +} + +// NOTE: This must be called after QSPI has been enabled. Communications with +// the device will not happen until QSPI is enabled. +static inline ALT_STATUS_CODE alt_qspi_N25Q_enable(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Reset the volatile memory on the N25Q + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_RESET_EN, 0, 10000); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_RESET_MEM, 0, 10000); + } + + ///// + + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_DEV_INST_CONFIG_t cfg = + { + .op_code = ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO, + .inst_type = ALT_QSPI_MODE_SINGLE, // RDID does not support QUAD. + .addr_xfer_type = ALT_QSPI_MODE_QUAD, + .data_xfer_type = ALT_QSPI_MODE_QUAD, + .dummy_cycles = 10 + }; + + status = alt_qspi_device_read_config_set(&cfg); + } + +/* + // CASE 157096: Investigate using QUAD for writes. + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_DEV_INST_CONFIG_t cfg = + { + .op_code = ALT_QSPI_STIG_OPCODE_PP, + .inst_type = ALT_QSPI_MODE_SINGLE, + .addr_xfer_type = ALT_QSPI_MODE_QUAD, + .data_xfer_type = ALT_QSPI_MODE_QUAD, + .dummy_cycles = 0 + }; + + status = alt_qspi_device_write_config_set(&cfg); + } +*/ + + return status; +} + +static ALT_STATUS_CODE alt_qspi_N25Q_flag_wait_for_program(uint32_t timeout) +{ + // The flag status register is only available on the 512 Mib and 1 Gib + // (64 MiB and 128 MiB) Micron parts. + if (qspi_device_size < 0x4000000) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t time_out = timeout; + uint32_t stat = 0; + bool infinite = (timeout == ALT_QSPI_TIMEOUT_INFINITE); + + do + { + status = alt_qspi_device_status(&stat); + if (status != ALT_E_SUCCESS) + { + break; + } + if (!ALT_QSPI_STIG_SR_BUSY_GET(stat)) + { + break; + } + } + while (time_out-- || infinite); + + if (time_out == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + uint32_t flagsr = 0; + + do + { + status = alt_qspi_N25Q_device_flag(&flagsr); + if (status != ALT_E_SUCCESS) + { + break; + } + if (ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(flagsr)) + { + break; + } + } + while (timeout-- || infinite); + + if (timeout == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + if (ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(flagsr)) + { + status = ALT_E_ERROR; + } + } + } + return status; +} + +static ALT_STATUS_CODE alt_qspi_N25Q_flag_wait_for_erase(uint32_t timeout) +{ + // The flag status register is only available on the 512 Mib and 1 Gib + // (64 MiB and 128 MiB) Micron parts. + if (qspi_device_size < 0x4000000) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t time_out = timeout; + uint32_t stat = 0; + bool infinite = (timeout == ALT_QSPI_TIMEOUT_INFINITE); + + do + { + status = alt_qspi_device_status(&stat); + if (status != ALT_E_SUCCESS) + { + break; + } + if (!ALT_QSPI_STIG_SR_BUSY_GET(stat)) + { + break; + } + } + while (time_out-- || infinite); + + if (time_out == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + + uint32_t flagsr = 0; + + do + { + status = alt_qspi_N25Q_device_flag(&flagsr); + if (status != ALT_E_SUCCESS) + { + break; + } + if (ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(flagsr)) + { + break; + } + } + while (timeout-- || infinite); + + if (timeout == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + if (ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(flagsr)) + { + status = ALT_E_ERROR; + } + } + } + + return status; +} +#endif + +// +// A helper function which converts a ns interval into a delay interval for a given MHz. +// The +999 is there to round up the result. +// +static inline int alt_qspi_ns_to_multiplier(int ns, int mhz) +{ + return ((ns * mhz) + 999) / 1000; +} + +ALT_STATUS_CODE alt_qspi_init(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + alt_freq_t qspi_clk_freq = 0; + + // Validate QSPI module input clocks. + // - pclk - l4_mp_clk + // - hclk - l4_mp_clk + // - ref_clk - qspi_clk + + // Check and validate the QSPI ref_clk which is connected to the HPS qspi_clk. + if (status == ALT_E_SUCCESS) + { + if (alt_clk_is_enabled(ALT_CLK_QSPI) != ALT_E_TRUE) + { + status = ALT_E_BAD_CLK; + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_clk_freq_get(ALT_CLK_QSPI, &qspi_clk_freq); + if (status == ALT_E_SUCCESS) + { + if (qspi_clk_freq > ALT_QSPI_CLK_FREQ_MAX) + { + return ALT_E_BAD_CLK; + } + } + } + + int qspi_clk_mhz = qspi_clk_freq / 1000000; + + ///// + + // Take QSPI controller out of reset. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_QSPI_SET_MSK); + + ///// + + // Configure the device timing + + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_TIMING_CONFIG_t timing_cfg = + { + .clk_phase = (ALT_QSPI_CLK_PHASE_t)ALT_QSPI_CFG_SELCLKPHASE_RESET, + .clk_pol = (ALT_QSPI_CLK_POLARITY_t)ALT_QSPI_CFG_SELCLKPOL_RESET, + .cs_da = alt_qspi_ns_to_multiplier(ALT_QSPI_TSHSL_NS_DEF, qspi_clk_mhz), + .cs_dads = alt_qspi_ns_to_multiplier(ALT_QSPI_TSD2D_NS_DEF, qspi_clk_mhz), + .cs_eot = alt_qspi_ns_to_multiplier(ALT_QSPI_TCHSH_NS_DEF, qspi_clk_mhz), + .cs_sot = alt_qspi_ns_to_multiplier(ALT_QSPI_TSLCH_NS_DEF, qspi_clk_mhz), + .rd_datacap = 1 + }; + + dprintf("DEBUG[QSPI]: cs_da = %" PRIu32 ".\n", timing_cfg.cs_da); + dprintf("DEBUG[QSPI]: cs_dads = %" PRIu32 ".\n", timing_cfg.cs_dads); + dprintf("DEBUG[QSPI]: cs_eot = %" PRIu32 ".\n", timing_cfg.cs_eot); + dprintf("DEBUG[QSPI]: cs_sot = %" PRIu32 ".\n", timing_cfg.cs_sot); + + status = alt_qspi_timing_config_set(&timing_cfg); + } + + ///// + + // Configure the remap address register, no remap + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_ahb_remap_address_set(0); + } + + // Configure the interrupt mask register, disabled all first + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_int_disable(ALT_QSPI_INT_STATUS_ALL); + } + + // Configure the baud rate divisor + // CASE 157095: Investigate using 108 MHz, and tweaking the rd_datacap param. + + if (status == ALT_E_SUCCESS) + { + uint32_t device_sclk_mhz = 54; + uint32_t div_actual = (qspi_clk_mhz + (device_sclk_mhz - 1)) / device_sclk_mhz; + dprintf("DEBUG[QSPI]: div_actual = %" PRIu32 ".\n", div_actual); + + ALT_QSPI_BAUD_DIV_t div_bits = (ALT_QSPI_BAUD_DIV_t)(((div_actual + 1) / 2) - 1); + status = alt_qspi_baud_rate_div_set(div_bits); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_uninit(void) +{ + // Put QSPI controller into reset. + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_QSPI_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_disable(void) +{ + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_EN_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_enable(void) +{ + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_EN_SET_MSK); + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + ///// + + // Device specific configuration + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_enable(); + } +#endif + + uint32_t rdid = 0; + + // Query device capabilities + // This requires QSPI to be enabled. + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_rdid(&rdid); + } + + if (status == ALT_E_SUCCESS) + { + // NOTE: The size code seems to be a form of BCD (binary coded decimal). + // The first nibble is the 10's digit and the second nibble is the 1's + // digit in the number of bytes. + + // Capacity ID samples: + // 0x15 : 16 Mb => 2 MiB => 1 << 21 ; BCD=15 + // 0x16 : 32 Mb => 4 MiB => 1 << 22 ; BCD=16 + // 0x17 : 64 Mb => 8 MiB => 1 << 23 ; BCD=17 + // 0x18 : 128 Mb => 16 MiB => 1 << 24 ; BCD=18 + // 0x19 : 256 Mb => 32 MiB => 1 << 25 ; BCD=19 + // 0x1a + // 0x1b + // 0x1c + // 0x1d + // 0x1e + // 0x1f + // 0x20 : 512 Mb => 64 MiB => 1 << 26 ; BCD=20 + // 0x21 : 1024 Mb => 128 MiB => 1 << 27 ; BCD=21 + + int cap_code = ALT_QSPI_STIG_RDID_CAPACITYID_GET(rdid); + + if ( ((cap_code >> 4) > 0x9) || ((cap_code & 0xf) > 0x9)) + { + // If a non-valid BCD value is detected at the top or bottom nibble, chances + // are that the chip has a problem. + + dprintf("DEBUG[QSPI]: Invalid CapacityID encountered: 0x%02x.\n", cap_code); + status = ALT_E_ERROR; + } + else + { + int cap_decoded = ((cap_code >> 4) * 10) + (cap_code & 0xf); + + qspi_device_size = 1 << (cap_decoded + 6); + + dprintf("DEBUG[QSPI]: Device size = 0x%" PRIx32 ".\n", qspi_device_size); + } + } + + // Configure the device size and address bytes + + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_DEV_SIZE_CONFIG_t size_cfg = + { + .block_size = ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET, // 0x10 => 2^16 = 64 KiB + .page_size = ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET, // 0x100 => 256 B + .addr_size = ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET, // 0x2 => 3 bytes or 0x00ffffff mask. + .lower_wrprot_block = 0, + .upper_wrprot_block = (qspi_device_size - 1) >> 16, + .wrprot_enable = ALT_QSPI_WRPROT_EN_RESET + }; + + status = alt_qspi_device_size_config_set(&size_cfg); + } + + ///// + + // Configure the DMA parameters + + // This will allow DMA to work well without much intervention by users. + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_dma_config_set(4, 32); + } + + ///// + + return status; +} + +///// + +uint32_t alt_qspi_int_status_get(void) +{ + // Read and return the value of the QSPI controller Interrupt Status + // Register (irqstat). + return alt_read_word(ALT_QSPI_IRQSTAT_ADDR); +} + +ALT_STATUS_CODE alt_qspi_int_clear(const uint32_t mask) +{ + // Check that the [mask] contains valid interrupt status conditions values. + if ((ALT_QSPI_INT_STATUS_ALL & mask) == 0) + { + return ALT_E_BAD_ARG; + } + + // Write 1's to clear the desired interrupt status condition(s). + alt_write_word(ALT_QSPI_IRQSTAT_ADDR, mask); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_int_disable(const uint32_t mask) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Check that the [mask] contains valid interrupt status conditions values. + if ((ALT_QSPI_INT_STATUS_ALL & mask) == 0) + { + return ALT_E_BAD_ARG; + } + + // Write 0's to disable the desired interrupt status condition(s). + alt_clrbits_word(ALT_QSPI_IRQMSK_ADDR, mask); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_int_enable(const uint32_t mask) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Check that the [mask] contains valid interrupt status conditions values. + if ((ALT_QSPI_INT_STATUS_ALL & mask) == 0) + { + return ALT_E_BAD_ARG; + } + + // Write 1's to enable the desired interrupt status condition(s). + alt_setbits_word(ALT_QSPI_IRQMSK_ADDR, mask); + + return ALT_E_SUCCESS; +} + +///// + +bool alt_qspi_is_idle(void) +{ + // If the idle field of the QSPI configuration register is 1 then the serial + // interface and QSPI pipeline is idle. + return ALT_QSPI_CFG_IDLE_GET(alt_read_word(ALT_QSPI_CFG_ADDR)) == 1; +} + +///// + +static ALT_STATUS_CODE alt_qspi_indirect_write_start_bank(uint32_t dst, size_t length); + +static ALT_STATUS_CODE alt_qspi_indirect_page_bound_write_helper(uint32_t dst, const char * src, size_t length) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_write_start_bank(dst, length); + } + + if (status == ALT_E_SUCCESS) + { + uint32_t write_count = 0; + uint32_t write_capacity = ALT_QSPI_SRAM_FIFO_ENTRY_COUNT - alt_qspi_sram_partition_get(); + + while (write_count < length) + { + uint32_t space = write_capacity - alt_qspi_indirect_write_fill_level(); + space = MIN(space, (length - write_count)/ sizeof(uint32_t)); + + const uint32_t * data = (const uint32_t *)(src + write_count); + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_QSPIDATA_ADDR, *data++); + } + + write_count += space * sizeof(uint32_t); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_write_finish(); + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_indirect_subsector_aligned_write_helper(const char * data, uint32_t subsec_addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + for (int i = 0; i < ALT_QSPI_SUBSECTOR_SIZE / ALT_QSPI_PAGE_SIZE; i++) + { + int offset = i * ALT_QSPI_PAGE_SIZE; + + status = alt_qspi_indirect_page_bound_write_helper(subsec_addr + offset, data + offset, ALT_QSPI_PAGE_SIZE); + if (status != ALT_E_SUCCESS) + { + break; + } + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_indirect_read_start_bank(uint32_t src, size_t size); + +// +// This helper function reads a segment of data, which is limited to 1 bank +// (24 bits of addressing). +// +static ALT_STATUS_CODE alt_qspi_read_bank(char * dst, uint32_t src, size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_read_start_bank(src, size); + } + + if (status == ALT_E_SUCCESS) + { + uint32_t read_count = 0; + + while (!alt_qspi_indirect_read_is_complete()) + { + uint32_t level = alt_qspi_indirect_read_fill_level(); +// level = MIN(level, (size - read_count) / sizeof(uint32_t)); + + uint32_t * data = (uint32_t *)(dst + read_count); + for (uint32_t i = 0; i < level; ++i) + { + *data++ = alt_read_word(ALT_QSPIDATA_ADDR); + } + + read_count += level * sizeof(uint32_t); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_read_finish(); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_read(void * dst, uint32_t src, size_t size) +{ + if (src >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (src + size - 1 >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + if ((uintptr_t)dst & 0x3) + { + return ALT_E_ERROR; + } + + if (src & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // + // bank_count : The number of bank(s) affected, including partial banks. + // bank_addr : The aligned address of the first affected bank, including partial bank(s). + // bank_ofst : The offset of the bank to read. Only used when reading the first bank. + // + uint32_t bank_count = ((src + size - 1) >> 24) - (src >> 24) + 1; + uint32_t bank_addr = src & ALT_QSPI_BANK_ADDR_MSK; + uint32_t bank_ofst = src & (ALT_QSPI_BANK_SIZE - 1); + + char * data = (char *)dst; + + uint32_t copy_length = MIN(size, ALT_QSPI_BANK_SIZE - bank_ofst); + + dprintf("DEBUG[QSPI]: read(): bulk: mem_addr = %p; flash_addr = 0x%" PRIx32 ".\n", data, src); + dprintf("DEBUG[QSPI]: read(): bulk: bank_count = 0x%" PRIx32 ", bank_ofst = 0x%" PRIx32 ".\n", bank_count, bank_ofst); + + for (uint32_t i = 0; i < bank_count; ++i) + { + dprintf("DEBUG[QSPI]: read(): bank 0x%" PRIx32 "; copy_length = 0x%" PRIx32 ".\n", bank_addr >> 24, copy_length); + + status = alt_qspi_device_bank_select(bank_addr >> 24); + if (status != ALT_E_SUCCESS) + { + break; + } + + status = alt_qspi_read_bank(dst, bank_ofst, copy_length); + if (status != ALT_E_SUCCESS) + { + break; + } + + bank_addr += ALT_QSPI_BANK_SIZE; + data += copy_length; + size -= copy_length; + + copy_length = MIN(size, ALT_QSPI_BANK_SIZE); + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_write_bank(uint32_t dst, const char * src, size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + ///// + + uint32_t page_ofst = dst & (ALT_QSPI_PAGE_SIZE - 1); + uint32_t write_size = MIN(size, ALT_QSPI_PAGE_SIZE - page_ofst); + + while (size) + { + dprintf("DEBUG[QSPI]: write(): flash dst = 0x%" PRIx32 ", mem src = %p, write size = 0x%" PRIx32 ", size left = 0x%x.\n", dst, src, write_size, size); + + status = alt_qspi_indirect_page_bound_write_helper(dst, src, write_size); + if (status != ALT_E_SUCCESS) + { + break; + } + + dst += write_size; + src += write_size; + size -= write_size; + + write_size = MIN(size, ALT_QSPI_PAGE_SIZE); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_write(uint32_t dst, const void * src, size_t size) +{ + if (dst >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (dst + size - 1 >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + if ((uintptr_t)src & 0x3) + { + return ALT_E_ERROR; + } + + if (dst & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t bank_count = ((dst + size - 1) >> 24) - (dst >> 24) + 1; + uint32_t bank_addr = dst & ALT_QSPI_BANK_ADDR_MSK; + uint32_t bank_ofst = dst & (ALT_QSPI_BANK_SIZE - 1); + + const char * data = src; + + uint32_t copy_length = MIN(size, ALT_QSPI_BANK_SIZE - bank_ofst); + + dprintf("DEBUG[QSPI]: write(): bulk: flash_addr = 0x%" PRIx32 "; mem_addr = %p.\n", dst, data); + dprintf("DEBUG[QSPI]: write(): bulk: bank_count = 0x%" PRIx32 ", bank_ofst = 0x%" PRIx32 ".\n", bank_count, bank_ofst); + + for (uint32_t i = 0; i < bank_count; ++i) + { + dprintf("DEBUG[QSPI]: write(): bank 0x%" PRIx32 "; copy_length = 0x%" PRIx32 ".\n", bank_addr >> 24, copy_length); + + status = alt_qspi_device_bank_select(bank_addr >> 24); + if (status != ALT_E_SUCCESS) + { + break; + } + + status = alt_qspi_write_bank(bank_ofst, data, copy_length); + if (status != ALT_E_SUCCESS) + { + break; + } + + bank_addr += ALT_QSPI_BANK_SIZE; + data += copy_length; + size -= copy_length; + + copy_length = MIN(size, ALT_QSPI_BANK_SIZE); + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_erase_subsector_bank(uint32_t addr); + +static ALT_STATUS_CODE alt_qspi_replace_bank(uint32_t dst, const char * src, size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // + // subsec_count : The total number of affected subsector(s), + // including partial subsector(s). + // subsec_addr : The aligned address of the next affected subsector, + // including partial subsector(s). + // subsec_partial_head : The number of subsector unaligned data to be + // written out at the start of the flash write + // request. This data ends at the end of the subsector + // or earlier depending on the number of data to be + // written. + // subsec_partial_tail : The number of subsector unaligned data to be + // written out at the end of the flash write request. + // This data starts at the start of the subsector. If + // only a single subsector is written (partial or + // full), this value will be zero. + // + + uint32_t subsec_count = ((dst + size - 1) >> 12) - (dst >> 12) + 1; + uint32_t subsec_addr = dst & ALT_QSPI_SUBSECTOR_ADDR_MSK; + + uint32_t subsec_partial_head = MIN(ALT_QSPI_SUBSECTOR_SIZE - (dst & (ALT_QSPI_SUBSECTOR_SIZE - 1)), size) & (ALT_QSPI_SUBSECTOR_SIZE - 1); + uint32_t subsec_partial_tail = (size - subsec_partial_head) & (ALT_QSPI_SUBSECTOR_SIZE - 1); + + dprintf("DEBUG[QSPI]: replace(): report: dst = 0x%" PRIx32 "; size = 0x%x.\n", + dst, size); + dprintf("DEBUG[QSPI]: replace(): report: subsec_count = 0x%" PRIx32 "; subsec_addr = 0x%" PRIx32 ".\n", + subsec_count, subsec_addr); + dprintf("DEBUG[QSPI]: replace(): report: partial_head = 0x%" PRIx32 "; partial_tail = 0x%" PRIx32 ".\n", + subsec_partial_head, subsec_partial_tail); + + // Write the first subsector, partial case. + + if (subsec_partial_head) + { + // The write request is not aligned to a subsector so we must do the + // Read-Modify-Write cycle to preserve the existing data at the head of + // the subsector not affected by the write. + + char subsec_buf[ALT_QSPI_SUBSECTOR_SIZE]; + + uint32_t subsec_ofst = dst & ~ALT_QSPI_SUBSECTOR_ADDR_MSK; + + // - Read the subsector into buffer + // - Erase that subsector + // - Copy in the user data into buffer + // - Write out buffer to subsector + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_read_bank(subsec_buf, subsec_addr, subsec_ofst); + } + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(subsec_addr); + } + if (status == ALT_E_SUCCESS) + { + memcpy(subsec_buf + subsec_ofst, src, subsec_partial_head); + status = alt_qspi_indirect_subsector_aligned_write_helper(subsec_buf, subsec_addr); + } + + // Do some bookkeeping on the user buffer information + src += subsec_partial_head; + size -= subsec_partial_head; + + // Do some bookkeeping on the subsector tracking + subsec_count--; + subsec_addr += ALT_QSPI_SUBSECTOR_SIZE; + + dprintf("DEBUG[QSPI]: replace(): partial head: subsec_ofst = 0x%" PRIx32 "; size left = 0x%x; status = %" PRIi32 ".\n", + subsec_ofst, size, status); + } + + // If there is a partial tail, then take 1 off the subsec_count. This way + // the following loop will write out all the complete subsectors. The tail + // will be written out afterwards. + + if (subsec_partial_tail) + { + subsec_count--; + } + + // Write the aligned subsectors following any partial subsectors. + + for (uint32_t i = 0; i < subsec_count; ++i) + { + // - Erase subsector + // - Write out buffer to subsector + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(subsec_addr); + } + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_subsector_aligned_write_helper(src, subsec_addr); + } + + src += ALT_QSPI_SUBSECTOR_SIZE; + size -= ALT_QSPI_SUBSECTOR_SIZE; + + // Don't modify subsec_count as it's being used by the loop. + subsec_addr += ALT_QSPI_SUBSECTOR_SIZE; + + dprintf("DEBUG[QSPI]: replace(): subsec aligned: size left = 0x%x, status = %" PRIi32 ".\n", + size, status); + } + + // Write the last subsector, partial case. + + if (subsec_partial_tail) + { + // The write request is not aligned to a subsector so we must do the + // Read-Modify-Write cycle to preserve the existing data at the end of + // the subsector not affected by the write. + + char subsec_buf[ALT_QSPI_SUBSECTOR_SIZE]; + + // - Read the subsector into buffer + // - Erase that subsector + // - Copy in the user data into buffer + // - Write out buffer to subsector + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_read_bank(subsec_buf + subsec_partial_tail, + subsec_addr + subsec_partial_tail, + ALT_QSPI_SUBSECTOR_SIZE - subsec_partial_tail); + } + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(subsec_addr); + } + if (status == ALT_E_SUCCESS) + { + memcpy(subsec_buf, src, subsec_partial_tail); + status = alt_qspi_indirect_subsector_aligned_write_helper(subsec_buf, subsec_addr); + } + + src += subsec_partial_tail; + size -= subsec_partial_tail; + + dprintf("DEBUG[QSPI]: replace(): partial tail: size left = 0x%x, status = %" PRIi32 ".\n", + size, status); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size) +{ + if (dst >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (dst + size - 1 >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + if ((uintptr_t)src & 0x3) + { + return ALT_E_ERROR; + } + + if (dst & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t bank_count = ((dst + size - 1) >> 24) - (dst >> 24) + 1; + uint32_t bank_addr = dst & ALT_QSPI_BANK_ADDR_MSK; + uint32_t bank_ofst = dst & (ALT_QSPI_BANK_SIZE - 1); + + const char * data = (const char *)src; + + uint32_t copy_length = MIN(size, ALT_QSPI_BANK_SIZE - bank_ofst); + + dprintf("DEBUG[QSPI]: replace(): bulk: flash_addr = 0x%" PRIx32 "; mem_addr = %p.\n", dst, data); + dprintf("DEBUG[QSPI]: replace(): bulk: bank_count = 0x%" PRIx32 ", bank_ofst = 0x%" PRIx32 ".\n", bank_count, bank_ofst); + + for (uint32_t i = 0; i < bank_count; ++i) + { + dprintf("DEBUG[QSPI]: replace(): bank 0x%" PRIx32 "; copy_length = 0x%" PRIx32 ".\n", bank_addr >> 24, copy_length); + + status = alt_qspi_device_bank_select(bank_addr >> 24); + if (status != ALT_E_SUCCESS) + { + break; + } + + status = alt_qspi_replace_bank(bank_ofst, data, copy_length); + if (status != ALT_E_SUCCESS) + { + break; + } + + bank_addr += ALT_QSPI_BANK_SIZE; + data += copy_length; + size -= copy_length; + + copy_length = MIN(size, ALT_QSPI_BANK_SIZE); + } + + return status; +} + +///// + +ALT_QSPI_BAUD_DIV_t alt_qspi_baud_rate_div_get(void) +{ + uint32_t baud_rate_div = ALT_QSPI_CFG_BAUDDIV_GET(alt_read_word(ALT_QSPI_CFG_ADDR)); + return (ALT_QSPI_BAUD_DIV_t) baud_rate_div; +} + +ALT_STATUS_CODE alt_qspi_baud_rate_div_set(const ALT_QSPI_BAUD_DIV_t baud_rate_div) +{ + if (0xf < (uint32_t)baud_rate_div) + { + // Invalid baud rate divisor value. + return ALT_E_BAD_ARG; + } + + // Set the Master Mode Baud Rate Divisor Field of the QSPI Configuration Register. + alt_replbits_word(ALT_QSPI_CFG_ADDR, + ALT_QSPI_CFG_BAUDDIV_SET_MSK, + ALT_QSPI_CFG_BAUDDIV_SET(baud_rate_div)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_chip_select_config_get(uint32_t* cs, + ALT_QSPI_CS_MODE_t* cs_mode) +{ + uint32_t cfg = alt_read_word(ALT_QSPI_CFG_ADDR); + + *cs = ALT_QSPI_CFG_PERCSLINES_GET(cfg); + *cs_mode = (ALT_QSPI_CS_MODE_t) ALT_QSPI_CFG_PERSELDEC_GET(cfg); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_chip_select_config_set(const uint32_t cs, + const ALT_QSPI_CS_MODE_t cs_mode) +{ + // chip select cs: + // four bit value, bit 0 = cs0, bit 1 = cs1, bit 2 = cs2, bit 3 = cs3 + // since cs is low true, the value of each bit should be zero if enable the cs. + // + // also allows multiple cs line enabled together. + + if (cs > ((1 << ALT_QSPI_CFG_PERCSLINES_WIDTH) - 1)) + { + // [cs] not within possible 4 bit chip select line value range. + return ALT_E_ARG_RANGE; + } + + if ((cs_mode != ALT_QSPI_CS_MODE_SINGLE_SELECT) && (cs_mode != ALT_QSPI_CS_MODE_DECODE)) + { + return ALT_E_INV_OPTION; + } + + // Update the Peripheral Chip Select Lines and Peripheral Select Decode + // Fields of the QSPI Configuration Register value with the chip select + // options. + uint32_t cfg = alt_read_word(ALT_QSPI_CFG_ADDR); + cfg &= ALT_QSPI_CFG_PERCSLINES_CLR_MSK & ALT_QSPI_CFG_PERSELDEC_CLR_MSK; + cfg |= ALT_QSPI_CFG_PERCSLINES_SET(cs) | ALT_QSPI_CFG_PERSELDEC_SET(cs_mode); + alt_write_word(ALT_QSPI_CFG_ADDR, cfg); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_mode_bit_disable(void) +{ + // Clear the Mode Bit Enable Field of the Device Read Instruction Register + // to disable mode bits from being sent after the address bytes. + alt_clrbits_word(ALT_QSPI_DEVRD_ADDR, ALT_QSPI_DEVRD_ENMODBITS_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_mode_bit_enable(void) +{ + // Set the Mode Bit Enable Field of the Device Read Instruction Register + // to enable mode bits to be sent after the address bytes. + alt_setbits_word(ALT_QSPI_DEVRD_ADDR, ALT_QSPI_DEVRD_ENMODBITS_SET_MSK); + + return ALT_E_SUCCESS; +} + +uint32_t alt_qspi_mode_bit_config_get(void) +{ + // Return the 8 bit value from the Mode Field of the Mode Bit Configuration + // Register. + return ALT_QSPI_MODBIT_MOD_GET(alt_read_word(ALT_QSPI_MODBIT_ADDR)); +} + +ALT_STATUS_CODE alt_qspi_mode_bit_config_set(const uint32_t mode_bits) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + if (mode_bits > ((1 << ALT_QSPI_MODBIT_MOD_WIDTH) - 1)) + { + // 'mode_bits' not within possible 8 bit mode value range. + return ALT_E_ARG_RANGE; + } + + // Set the 8 bit value in the Mode Field of the Mode Bit Configuration + // Register. + alt_replbits_word(ALT_QSPI_MODBIT_ADDR, + ALT_QSPI_MODBIT_MOD_SET_MSK, + ALT_QSPI_MODBIT_MOD_SET(mode_bits)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_size_config_get(ALT_QSPI_DEV_SIZE_CONFIG_t * cfg) +{ + // Although not required, it is recommended that the write protect feature + // be enabled prior to enabling the QSPI controller. This will block any AHB + // writes from taking effect. This also means the write protection registers + // (Lower Write Protection, Upper Write Protection, and Write Protection) + // should be setup and the number of bytes per device block in the device + // size configuration register should be setup prior to enabling the QSPI + // controller. + + // Read Device Size Register and get the Number of Bytes per Block, Number + // of Bytes per Device, and Number of Address Bytes Fields. + + uint32_t devsz = alt_read_word(ALT_QSPI_DEVSZ_ADDR); + + cfg->block_size = ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(devsz); + cfg->page_size = ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(devsz); + cfg->addr_size = ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(devsz); + + // Read Lower Write Protection, Upper Write Protection, and Write Protection + // Registers. + + cfg->lower_wrprot_block = ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(alt_read_word(ALT_QSPI_LOWWRPROT_ADDR)); + cfg->upper_wrprot_block = ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(alt_read_word(ALT_QSPI_UPPWRPROT_ADDR)); + cfg->wrprot_enable = ALT_QSPI_WRPROT_EN_GET(alt_read_word(ALT_QSPI_WRPROT_ADDR)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_size_config_set(const ALT_QSPI_DEV_SIZE_CONFIG_t * cfg) +{ + if (cfg->block_size > ((1 << ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + if (cfg->page_size > ((1 << ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + if (cfg->addr_size > ((1 << ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + if (cfg->lower_wrprot_block > cfg->upper_wrprot_block) + { + // Null write protection regions are not allowed. + return ALT_E_ARG_RANGE; + } + + ///// + + uint32_t value = ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(cfg->block_size) | + ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(cfg->page_size) | + ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(cfg->addr_size); + + alt_write_word(ALT_QSPI_DEVSZ_ADDR, value); + + if (cfg->wrprot_enable) + { + alt_write_word(ALT_QSPI_LOWWRPROT_ADDR, cfg->lower_wrprot_block); + alt_write_word(ALT_QSPI_UPPWRPROT_ADDR, cfg->upper_wrprot_block); + } + + // Read Upper Write Protection Register - uppwrprot. + // Set the Write Protection Enable Bit Field of the Write Protection + // Register accordingly. + if (cfg->wrprot_enable) + { + alt_setbits_word(ALT_QSPI_WRPROT_ADDR, ALT_QSPI_WRPROT_EN_SET(1)); + } + else + { + alt_clrbits_word(ALT_QSPI_WRPROT_ADDR, ALT_QSPI_WRPROT_EN_SET(1)); + } + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_read_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + // Read the Device Read Instruction Register - devrd. + uint32_t devrd = alt_read_word(ALT_QSPI_DEVRD_ADDR); + + cfg->op_code = ALT_QSPI_DEVRD_RDOPCODE_GET(devrd); + cfg->inst_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_INSTWIDTH_GET(devrd); + cfg->addr_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_ADDRWIDTH_GET(devrd); + cfg->data_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_DATAWIDTH_GET(devrd); + cfg->dummy_cycles = ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(devrd); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_read_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Validate input + + if (cfg->op_code > ((1 << ALT_QSPI_DEVRD_RDOPCODE_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + switch (cfg->inst_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->addr_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->data_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + if (cfg->dummy_cycles > ((1 << ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + ///// + + // Read the Device Read Instruction Register - devrd. + uint32_t devrd = alt_read_word(ALT_QSPI_DEVRD_ADDR); + + devrd &= ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK & + ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK & + ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK & + ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK & + ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK; + + devrd |= ALT_QSPI_DEVRD_RDOPCODE_SET(cfg->op_code) | + ALT_QSPI_DEVRD_INSTWIDTH_SET(cfg->inst_type) | + ALT_QSPI_DEVRD_ADDRWIDTH_SET(cfg->addr_xfer_type) | + ALT_QSPI_DEVRD_DATAWIDTH_SET(cfg->data_xfer_type) | + ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(cfg->dummy_cycles); + + alt_write_word(ALT_QSPI_DEVRD_ADDR, devrd); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_write_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + // Device Write Instruction Register - devwr. + uint32_t devwr = alt_read_word(ALT_QSPI_DEVWR_ADDR); + + cfg->op_code = ALT_QSPI_DEVWR_WROPCODE_GET(devwr); + // The Instruction Type field in the Device READ Instruction Register only appears + // once and applies to both READ and WRITE opertions. it is not included in the + // Device WRITE Instruction Register. + cfg->inst_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_INSTWIDTH_GET(alt_read_word(ALT_QSPI_DEVRD_ADDR)); + cfg->addr_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVWR_ADDRWIDTH_GET(devwr); + cfg->data_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVWR_DATAWIDTH_GET(devwr); + cfg->dummy_cycles = ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(devwr); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_write_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Validate input + + if (cfg->op_code > ((1 << ALT_QSPI_DEVWR_WROPCODE_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + switch (cfg->inst_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->addr_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->data_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + if (cfg->dummy_cycles > ((1 << ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + ///// + + // Read the Device Write Instruction Register - devwr. + uint32_t devwr = alt_read_word(ALT_QSPI_DEVWR_ADDR); + + devwr &= ALT_QSPI_DEVWR_WROPCODE_CLR_MSK & + ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK & + ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK & + ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK; + + devwr |= ALT_QSPI_DEVWR_WROPCODE_SET(cfg->op_code) | + ALT_QSPI_DEVWR_ADDRWIDTH_SET(cfg->addr_xfer_type) | + ALT_QSPI_DEVWR_DATAWIDTH_SET(cfg->data_xfer_type) | + ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(cfg->dummy_cycles); + + alt_write_word(ALT_QSPI_DEVWR_ADDR, devwr); + + // The Instruction Type field in the Device READ Instruction Register only appears + // once and applies to both READ and WRITE operations - it is not included in the + // Device WRITE Instruction Register. Therefore, modify the Instruction Type + // Field in the Device Read Register. + alt_replbits_word(ALT_QSPI_DEVRD_ADDR, + ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK, + ALT_QSPI_DEVRD_INSTWIDTH_SET((uint32_t) cfg->inst_type)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_timing_config_get(ALT_QSPI_TIMING_CONFIG_t * cfg) +{ + // QSPI Configuration Register - cfg + uint32_t cfgreg = alt_read_word(ALT_QSPI_CFG_ADDR); + cfg->clk_phase = (ALT_QSPI_CLK_PHASE_t) ALT_QSPI_CFG_SELCLKPHASE_GET(cfgreg); + cfg->clk_pol = (ALT_QSPI_CLK_POLARITY_t) ALT_QSPI_CFG_SELCLKPOL_GET(cfgreg); + + // QSPI Device Delay Register + uint32_t delayreg = alt_read_word(ALT_QSPI_DELAY_ADDR); + cfg->cs_sot = ALT_QSPI_DELAY_INIT_GET(delayreg); + cfg->cs_eot = ALT_QSPI_DELAY_AFTER_GET(delayreg); + cfg->cs_dads = ALT_QSPI_DELAY_BTWN_GET(delayreg); + cfg->cs_da = ALT_QSPI_DELAY_NSS_GET(delayreg); + + // Read Data Capture Register + cfg->rd_datacap = ALT_QSPI_RDDATACAP_DELAY_GET(alt_read_word(ALT_QSPI_RDDATACAP_ADDR)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_timing_config_set(const ALT_QSPI_TIMING_CONFIG_t * cfg) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Validate parameter(s) + + switch (cfg->clk_phase) + { + case ALT_QSPI_CLK_PHASE_ACTIVE: + case ALT_QSPI_CLK_PHASE_INACTIVE: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->clk_pol) + { + case ALT_QSPI_CLK_POLARITY_LOW: + case ALT_QSPI_CLK_POLARITY_HIGH: + break; + default: + return ALT_E_BAD_ARG; + } + + if (cfg->cs_da > ((1 << ALT_QSPI_DELAY_NSS_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + if (cfg->cs_dads > ((1 << ALT_QSPI_DELAY_BTWN_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + if (cfg->cs_eot > ((1 << ALT_QSPI_DELAY_AFTER_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + if (cfg->cs_sot > ((1 << ALT_QSPI_DELAY_INIT_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + if (cfg->rd_datacap > ((1 << ALT_QSPI_RDDATACAP_DELAY_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + ///// + + // QSPI Configuration Register - cfg + uint32_t cfgreg = alt_read_word(ALT_QSPI_CFG_ADDR); + cfgreg &= ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK & + ALT_QSPI_CFG_SELCLKPOL_CLR_MSK; + cfgreg |= ALT_QSPI_CFG_SELCLKPHASE_SET(cfg->clk_phase) | + ALT_QSPI_CFG_SELCLKPOL_SET(cfg->clk_pol); + alt_write_word(ALT_QSPI_CFG_ADDR, cfgreg); + + // QSPI Device Delay Register + uint32_t delayreg = ALT_QSPI_DELAY_INIT_SET(cfg->cs_sot) | + ALT_QSPI_DELAY_AFTER_SET(cfg->cs_eot) | + ALT_QSPI_DELAY_BTWN_SET(cfg->cs_dads) | + ALT_QSPI_DELAY_NSS_SET(cfg->cs_da); + alt_write_word(ALT_QSPI_DELAY_ADDR, delayreg); + + // Read Data Capture Register + + alt_write_word(ALT_QSPI_RDDATACAP_ADDR, + ALT_QSPI_RDDATACAP_BYP_SET(1) | + ALT_QSPI_RDDATACAP_DELAY_SET(cfg->rd_datacap)); + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_qspi_direct_disable(void) +{ + // Clear (set to 0) the Enable Direct Access Controller Field of the QSPI + // Configuration Register to disable the Direct Access Controller. + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDIRACC_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_direct_enable(void) +{ + // Set (set to 1) the Enable Direct Access Controller Field of the QSPI + // Configuration Register to enable the Direct Access Controller. + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDIRACC_SET_MSK); + + return ALT_E_SUCCESS; +} + +uint32_t alt_qspi_ahb_remap_address_get(void) +{ + // Read and return the value of the Remap Address Register. + return ALT_QSPI_REMAPADDR_VALUE_GET(alt_read_word(ALT_QSPI_REMAPADDR_ADDR)); +} + +ALT_STATUS_CODE alt_qspi_ahb_remap_address_set(const uint32_t ahb_remap_addr) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Read and return the value of the Remap Address Register. + alt_setbits_word(ALT_QSPI_REMAPADDR_ADDR, ALT_QSPI_REMAPADDR_VALUE_SET(ahb_remap_addr)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_ahb_address_remap_disable(void) +{ + // Clear (set to 0) the Enable AHB Address Remapping Field of the QSPI + // Configuration Register to disable AHB address remapping. + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENAHBREMAP_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_ahb_address_remap_enable(void) +{ + // Set (set to 1) the Enable AHB Address Remapping Field of the QSPI + // Configuration Register to enable AHB address remapping. + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENAHBREMAP_SET_MSK); + + return ALT_E_SUCCESS; +} + +///// + +static ALT_STATUS_CODE alt_qspi_indirect_read_start_bank(uint32_t flash_addr, + size_t num_bytes) +{ + alt_write_word(ALT_QSPI_INDRDSTADDR_ADDR, flash_addr); + alt_write_word(ALT_QSPI_INDRDCNT_ADDR, num_bytes); + alt_write_word(ALT_QSPI_INDRD_ADDR, ALT_QSPI_INDRD_START_SET_MSK | + ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_indirect_read_start(const uint32_t flash_addr, + const size_t num_bytes) +{ + // flash_addr and num_bytes restriction is to prevent possible unaligned + // exceptions. + + if (flash_addr & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes == 0) + { + // Do not report this as a success. If a indirect read was not + // previously completed, it may be cleared already, at which point + // alt_qspi_indirect_read_is_complete() will never report true. + return ALT_E_ERROR; + } + + if (flash_addr > qspi_device_size) + { + return ALT_E_ERROR; + } + + if (flash_addr + num_bytes > qspi_device_size) + { + return ALT_E_ERROR; + } + + // Verify request does not cross bank boundary. + // This limitation is due to the 3-byte addressing limitation. + if ((flash_addr & ALT_QSPI_BANK_ADDR_MSK) != ((flash_addr + num_bytes - 1) & ALT_QSPI_BANK_ADDR_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status; + status = alt_qspi_device_bank_select(flash_addr >> 24); + if (status != ALT_E_SUCCESS) + { + return status; + } + + ///// + + return alt_qspi_indirect_read_start_bank(flash_addr, + num_bytes); + +} + +ALT_STATUS_CODE alt_qspi_indirect_read_finish(void) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_indirect_read_cancel(void) +{ + // An indirect operation may be cancelled at any time by setting Indirect + // Transfer Control Register bit [1]. + alt_write_word(ALT_QSPI_INDRD_ADDR, ALT_QSPI_INDRD_CANCEL_SET_MSK); + + return ALT_E_SUCCESS; +} + +uint32_t alt_qspi_indirect_read_fill_level(void) +{ + // Return the SRAM Fill Level (Indirect Read Partition) Field of the SRAM + // Fill Register to get the SRAM Fill Level for the Indirect Read Partition + // in units of SRAM Words (4 bytes). + return ALT_QSPI_SRAMFILL_INDRDPART_GET(alt_read_word(ALT_QSPI_SRAMFILL_ADDR)); +} + +uint32_t alt_qspi_indirect_read_watermark_get(void) +{ + // Return the Watermark value in the Indirect Read Transfer Watermark Register. + return alt_read_word(ALT_QSPI_INDRDWATER_ADDR); +} + +ALT_STATUS_CODE alt_qspi_indirect_read_watermark_set(const uint32_t watermark) +{ + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + // Set the Watermark value in the Indirect Read Transfer Watermark Register. + alt_write_word(ALT_QSPI_INDRDWATER_ADDR, watermark); + + return ALT_E_SUCCESS; +} + +bool alt_qspi_indirect_read_is_complete(void) +{ + // The value of the Indirect Completion Status Field of the Indirect Read + // Transfer Control Register is set by hardware when an indirect read + // operation has completed. + return (alt_read_word(ALT_QSPI_INDRD_ADDR) & ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK) != 0; +} + +static ALT_STATUS_CODE alt_qspi_indirect_write_start_bank(uint32_t flash_addr, + size_t num_bytes) +{ + alt_write_word(ALT_QSPI_INDWRSTADDR_ADDR, flash_addr); + alt_write_word(ALT_QSPI_INDWRCNT_ADDR, num_bytes); + alt_write_word(ALT_QSPI_INDWR_ADDR, ALT_QSPI_INDWR_START_SET_MSK | + ALT_QSPI_INDWR_INDDONE_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_indirect_write_start(const uint32_t flash_addr, + const size_t num_bytes) +{ + // flash_addr and num_bytes restriction is to prevent possible unaligned + // exceptions. + + if (flash_addr & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes == 0) + { + // Do not report this as a success. If a indirect write was not + // previously completed, it may be cleared already, at which point + // alt_qspi_indirect_write_is_complete() will never report true. + return ALT_E_ERROR; + } + + if (num_bytes > 256) + { + // The Micron part can only write up to 256 bytes at a time. + return ALT_E_ERROR; + } + + if (flash_addr > qspi_device_size) + { + return ALT_E_ERROR; + } + + if (flash_addr + num_bytes > qspi_device_size) + { + return ALT_E_ERROR; + } + +/* + // Verify request does not cross bank boundary. + // This limitation is due to the 3-byte addressing limitation. + if ((flash_addr & ALT_QSPI_BANK_ADDR_MSK) != ((flash_addr + num_bytes - 1) & ALT_QSPI_BANK_ADDR_MSK)) + { + return ALT_E_ERROR; + } +*/ + // Verify request does not cross page boundary. + // This limitation is in place for the Micron part used. + if ((flash_addr & ALT_QSPI_PAGE_ADDR_MSK) != ((flash_addr + num_bytes - 1) & ALT_QSPI_PAGE_ADDR_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + status = alt_qspi_device_bank_select(flash_addr >> 24); + if (status != ALT_E_SUCCESS) + { + return status; + } + + ///// + + return alt_qspi_indirect_write_start_bank(flash_addr, + num_bytes); +} + +ALT_STATUS_CODE alt_qspi_indirect_write_finish(void) +{ +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + return alt_qspi_N25Q_flag_wait_for_program(ALT_QSPI_TIMEOUT_INFINITE); +#else + return ALT_E_SUCCESS; +#endif +} + +ALT_STATUS_CODE alt_qspi_indirect_write_cancel(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_program(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + + if (status == ALT_E_SUCCESS) + { + // An indirect operation may be cancelled at any time by setting Indirect + // Transfer Control Register bit [1]. + alt_write_word(ALT_QSPI_INDWR_ADDR, ALT_QSPI_INDWR_CANCEL_SET_MSK); + } + + return status; +} + +uint32_t alt_qspi_indirect_write_fill_level(void) +{ + // Return the SRAM Fill Level (Indirect Write Partition) Field of the SRAM + // Fill Register to get the SRAM Fill Level for the Indirect Write Partition + // in units of SRAM Words (4 bytes). + return ALT_QSPI_SRAMFILL_INDWRPART_GET(alt_read_word(ALT_QSPI_SRAMFILL_ADDR)); +} + +uint32_t alt_qspi_indirect_write_watermark_get(void) +{ + // Return the Watermark value in the Indirect Write Transfer Watermark Register. + return alt_read_word(ALT_QSPI_INDWRWATER_ADDR); +} + +ALT_STATUS_CODE alt_qspi_indirect_write_watermark_set(const uint32_t watermark) +{ + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + // Set the Watermark value in the Indirect Write Transfer Watermark Register. + alt_write_word(ALT_QSPI_INDWRWATER_ADDR, watermark); + + return ALT_E_SUCCESS; +} + +bool alt_qspi_indirect_write_is_complete(void) +{ + // The value of the Indirect Completion Status Field of the Indirect Write + // Transfer Control Register is set by hardware when an indirect write + // operation has completed. + return (alt_read_word(ALT_QSPI_INDWR_ADDR) & ALT_QSPI_INDWR_INDDONE_SET_MSK) != 0; +} + +///// + +uint32_t alt_qspi_sram_partition_get(void) +{ + // The number of locations allocated to indirect read is equal to the value + // of the SRAM partition register. See the documentation for this function + // regarding the + 1 in the IP documentation. This way the get() and set() + // will be symmetrical. + + return ALT_QSPI_SRAMPART_ADDR_GET(alt_read_word(ALT_QSPI_SRAMPART_ADDR)); +} + +ALT_STATUS_CODE alt_qspi_sram_partition_set(const uint32_t read_part_size) +{ + if (read_part_size > ((1 << ALT_QSPI_SRAMPART_ADDR_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + alt_replbits_word(ALT_QSPI_SRAMPART_ADDR, + ALT_QSPI_SRAMPART_ADDR_SET_MSK, + ALT_QSPI_SRAMPART_ADDR_SET(read_part_size)); + + return ALT_E_SUCCESS; +} + +///// + + +static ALT_STATUS_CODE alt_qspi_erase_subsector_bank(uint32_t addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE, 0, addr, 10000); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + + return status; +} + +ALT_STATUS_CODE alt_qspi_erase_subsector(const uint32_t addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(addr >> 24); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(addr); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_erase_sector(const uint32_t addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(addr >> 24); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_SEC_ERASE, 0, addr, ALT_QSPI_TIMEOUT_INFINITE); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + + return status; +} + +ALT_STATUS_CODE alt_qspi_erase_chip(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (qspi_device_size >= (2 * ALT_QSPI_N25Q_DIE_SIZE)) + { + // NOTE: This path is specifically for 512 Mib and 1 Gib Micron N25Q + // chips only. + + dprintf("DEBUG[QSPI]: erase[chip]: FYI, wait time is ~800s for 128 MiB.\n"); + + uint32_t die_count = qspi_device_size / ALT_QSPI_N25Q_DIE_SIZE; + + for (int i = 0; i < die_count; ++i) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + dprintf("DEBUG[QSPI]: Erase chip: die = %d, total = %" PRIu32 ".\n", i, die_count); + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(i * (ALT_QSPI_N25Q_DIE_SIZE / ALT_QSPI_BANK_SIZE)); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_DIE_ERASE, 0, + i * ALT_QSPI_N25Q_DIE_SIZE, + ALT_QSPI_TIMEOUT_INFINITE); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + } + } + else + { + // NOTE: Untested path. + + dprintf("DEBUG[QSPI]: Bulk erase.\n"); + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(0); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + // If BULK_ERASE is like other ERASE, it needs the address command. + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_BULK_ERASE, 0, + 0, + ALT_QSPI_TIMEOUT_INFINITE); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + } + + return status; +} + +///// + +ALT_STATUS_CODE alt_qspi_dma_disable(void) +{ + // Clear (set to 0) the Enable DMA Peripheral Interface Field of the QSPI + // Configuration Register to disable the DMA peripheral interface. + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_dma_enable(void) +{ + // Set (set to 1) the Enable DMA Peripheral Interface Field of the QSPI + // Configuration Register to enable the DMA peripheral interface. + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_dma_config_get(uint32_t * single_type_sz, + uint32_t * burst_type_sz) +{ + // Get the current value of the DMA Peripheral Register - dmaper + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + + // For both values, a programmed value of 0 represents a single byte. The + // actual number of bytes used is 2 ** (value in this register field). + *single_type_sz = 1 << ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(dmaper); + *burst_type_sz = 1 << ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(dmaper); + + return ALT_E_SUCCESS; +} + +// +// Returns true if [n] is a power of 2 value otherwise returns false. +// +static bool is_pow_2(uint32_t n) +{ + return ((n > 0) && ((n & (n - 1)) == 0)); +} + +// +// Return the log base 2 value of a number that is known to be a power of 2. +// +static uint32_t log2u(uint32_t value) +{ + uint32_t exp = 0; + while ((exp < 32) && (value != (1 << exp))) + { + ++exp; + } + return exp; +} + +ALT_STATUS_CODE alt_qspi_dma_config_set(const uint32_t single_type_sz, + const uint32_t burst_type_sz) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + if (single_type_sz < 4) + { + return ALT_E_ERROR; + } + + if (burst_type_sz < 4) + { + return ALT_E_ERROR; + } + + if (burst_type_sz < single_type_sz) + { + return ALT_E_ERROR; + } + + const uint32_t single_type_sz_max = 1 << ((1 << ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH) - 1); + const uint32_t burst_type_sz_max = 1 << ((1 << ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH) - 1); + + // Both parameter values must be a power of 2 between 1 and 32728. + if ( (single_type_sz > single_type_sz_max) || !is_pow_2(single_type_sz) + || (burst_type_sz > burst_type_sz_max) || !is_pow_2(burst_type_sz) + ) + { + return ALT_E_ARG_RANGE; + } + + // Get the current value of the DMA Peripheral Register - dmaper + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + dmaper &= ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK & + ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK; + dmaper |= ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(log2u(burst_type_sz)) | + ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(log2u(single_type_sz)); + alt_write_word(ALT_QSPI_DMAPER_ADDR, dmaper); + + return ALT_E_SUCCESS; +} + +///// + +// +// Private STIG and device commands +// + +static ALT_STATUS_CODE alt_qspi_stig_cmd_helper(uint32_t reg_value, uint32_t timeout) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + bool infinite = (timeout == ALT_QSPI_TIMEOUT_INFINITE); + + alt_write_word(ALT_QSPI_FLSHCMD_ADDR, reg_value); + alt_write_word(ALT_QSPI_FLSHCMD_ADDR, reg_value | ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE); + + do + { + reg_value = alt_read_word(ALT_QSPI_FLSHCMD_ADDR); + if (!(reg_value & ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK)) + { + break; + } + + } while (timeout-- || infinite); + + if (timeout == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + uint32_t reg = ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + return alt_qspi_stig_cmd_helper(reg, timeout); +} + +ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, + uint32_t dummy, + uint32_t num_bytes, + uint32_t * output, + uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + // STIG read can only return up to 8 bytes. + if ((num_bytes > 8) || (num_bytes == 0)) + { + return ALT_E_BAD_ARG; + } + + uint32_t reg_value = + ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_ENRDDATA_SET(ALT_QSPI_FLSHCMD_ENRDDATA_E_EN) | + ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(num_bytes - 1) | + ALT_QSPI_FLSHCMD_ENCMDADDR_SET(ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD) | + ALT_QSPI_FLSHCMD_ENMODBIT_SET(ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD) | + ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(0) | + ALT_QSPI_FLSHCMD_ENWRDATA_SET(ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION) | + ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(0) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + status = alt_qspi_stig_cmd_helper(reg_value, timeout); + if (status != ALT_E_SUCCESS) + { + return status; + } + + output[0] = alt_read_word(ALT_QSPI_FLSHCMDRDDATALO_ADDR); + + if (num_bytes > 4) + { + output[1] = alt_read_word(ALT_QSPI_FLSHCMDRDDATAUP_ADDR); + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, + uint32_t dummy, + uint32_t num_bytes, + const uint32_t * input, + uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + // STIG can only write up to 8 bytes. + if ((num_bytes > 8) || (num_bytes == 0)) + { + return ALT_E_BAD_ARG; + } + + uint32_t reg_value = + ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_ENRDDATA_SET(ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION) | + ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(0) | + ALT_QSPI_FLSHCMD_ENCMDADDR_SET(ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD) | + ALT_QSPI_FLSHCMD_ENMODBIT_SET(ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD) | + ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(0) | + ALT_QSPI_FLSHCMD_ENWRDATA_SET(ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES) | + ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(num_bytes - 1) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + alt_write_word(ALT_QSPI_FLSHCMDWRDATALO_ADDR, input[0]); + + if (num_bytes > 4) + { + alt_write_word(ALT_QSPI_FLSHCMDWRDATAUP_ADDR, input[1]); + } + + return alt_qspi_stig_cmd_helper(reg_value, timeout); +} + +ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, + uint32_t dummy, + uint32_t address, + uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + uint32_t reg = ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + reg |= ALT_QSPI_FLSHCMD_ENCMDADDR_SET(ALT_QSPI_FLSHCMD_ENCMDADDR_E_END); + reg |= ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3); + + alt_write_word(ALT_QSPI_FLSHCMDADDR_ADDR, address); + + return alt_qspi_stig_cmd_helper(reg, timeout); +} + +///// + +ALT_STATUS_CODE alt_qspi_device_wren(void) +{ + // Write enable through STIG (not required, auto send by controller during write) + return alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_WREN, 0, 10000); +} + +ALT_STATUS_CODE alt_qspi_device_wrdis(void) +{ + // Write disable through STIG (not required, auto send by controller during write) + return alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_WRDIS, 0, 10000); +} + +ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid) +{ + // Read flash device ID through STIG + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_RDID, 0, 4, rdid, 10000); +} + +ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param) +{ + // Read flash discovery parameters through STIG + + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_DISCVR_PARAM, 8, 8, param, 10000); +} + +ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + dprintf("DEBUG[QSPI]: bank_select(): switching to bank 0x%" PRIu32 ".\n", bank); + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_wr_cmd(ALT_QSPI_STIG_OPCODE_WR_EXT_REG, 0, 1, &bank, 10000); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wrdis(); + } + + return status; +} + +///// + +static bool alt_qspi_is_enabled(void) +{ + uint32_t cfg = alt_read_word(ALT_QSPI_CFG_ADDR); + + if (cfg & ALT_QSPI_CFG_EN_SET_MSK) + { + return true; + } + else + { + return false; + } +} + +ALT_STATUS_CODE alt_qspi_ecc_start(void * block, size_t size) +{ + if (size < (ALT_QSPI_PAGE_SIZE * 8)) + { + return ALT_E_ERROR; + } + + if (alt_qspi_is_enabled() == false) + { + return ALT_E_ERROR; + } + + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // 1. Configure SRAM Partition Register to 126 words for read, 2 words for write. + // 2. Enable ECC on QSPI RAM + // 3. Trigger an indirect read transfer that will fill up 126 words in FIFO by + // monitoring read FIFO fill level; Do not read out data through AHB. + // 4. Start AHB read and start indirect write operation to write back to the same + // device location, this will fill up and initilaize the write partition RAM. + // 5. To clear spurious interrupts, reset the QSPI controller. + + // Save the previous partition size + + uint32_t sram_orig = alt_qspi_sram_partition_get(); + dprintf("DEBUG[QSPI][ECC]: Save original SRAM as %" PRIu32 ".\n", sram_orig); + + // Step 1 + + uint32_t sram_fill = (1 << ALT_QSPI_SRAMPART_ADDR_WIDTH) - 2; + alt_qspi_sram_partition_set(sram_fill); + dprintf("DEBUG[QSPI][ECC]: Set new SRAM as %" PRIu32 ".\n", sram_fill); + + // Step 2 + + dprintf("DEBUG[QSPI][ECC]: Enable ECC in SysMgr.\n"); + alt_write_word(ALT_SYSMGR_ECC_QSPI_ADDR, ALT_SYSMGR_ECC_QSPI_EN_SET_MSK); + + // Step 3 + + // Issue a read ~ 2x larger than the read partition. We will read out 1 page, + // which will be used as the buffer to write back to QSPI. This way no data + // actually changes thus no erase will be needed. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Start indirect read PAGE * 8.\n"); + status = alt_qspi_indirect_read_start(0x0, ALT_QSPI_PAGE_SIZE * 8); + } + + // Read out 1 page for the write data + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Reading out 1 page ...\n"); + + uint32_t read_size = 0; + char * buffer = block; + while (read_size < ALT_QSPI_PAGE_SIZE) + { + uint32_t level = alt_qspi_indirect_read_fill_level(); + level = MIN(level, (ALT_QSPI_PAGE_SIZE - read_size) / sizeof(uint32_t)); + + uint32_t * data = (uint32_t *)(&buffer[read_size]); + for (uint32_t i = 0; i < level; ++i) + { + *data = alt_read_word(ALT_QSPIDATA_ADDR); + ++data; + } + + read_size += level * sizeof(uint32_t); + } + + if (read_size != ALT_QSPI_PAGE_SIZE) + { + status = ALT_E_ERROR; + } + } + + // Wait for read FIFO to report it is up to the specified fill level. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Waiting for read fill level ...\n"); + + uint32_t timeout = 10000; + + while (alt_qspi_indirect_read_fill_level() < sram_fill) + { + if (--timeout == 0) + { + dprintf("DEBUG[QSPI][ECC]: Waiting for read fill timeout !!!\n"); + status = ALT_E_TMO; + break; + } + } + } + + // Step 4 + + // Issue a write of 1 page of the same data from 0x0. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Start indirect write PAGE.\n"); + status = alt_qspi_indirect_write_start(0x0, ALT_QSPI_PAGE_SIZE); + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Writing in 1 page ...\n"); + + uint32_t write_size = 0; + char * buffer = block; + + while (write_size < ALT_QSPI_PAGE_SIZE) + { + uint32_t space = 2 - alt_qspi_indirect_write_fill_level(); + if (space == 0) + { + dprintf("DEBUG[QSPI][ECC]: Write FIFO filled at write_size = %" PRIu32 ".\n", write_size); + // Space = 0; which means all 2 positions in the write FIFO is filled, + // meaning it has been initialized with respect to ECC. + break; + } + + space = MIN(space, (ALT_QSPI_PAGE_SIZE - write_size) / sizeof(uint32_t)); + + uint32_t * data = (uint32_t *)(&buffer[write_size]); + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_QSPIDATA_ADDR, *data); + ++data; + } + + write_size += space * sizeof(uint32_t); + } + + if (write_size != ALT_QSPI_PAGE_SIZE) + { + dprintf("DEBUG[QSPI][ECC]: Cancel indirect write.\n"); + status = alt_qspi_indirect_write_cancel(); + } + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Finish indirect write.\n"); + status = alt_qspi_indirect_write_finish(); + } + + // Cancel the indirect read as it has initialized the read FIFO partition. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Cancel indirect read.\n"); + status = alt_qspi_indirect_read_cancel(); + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Finish indirect read.\n"); + status = alt_qspi_indirect_read_finish(); + } + + // Step 5 + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Clear any pending spurious QSPI ECC interrupts.\n"); + + alt_write_word(ALT_SYSMGR_ECC_QSPI_ADDR, + ALT_SYSMGR_ECC_QSPI_EN_SET_MSK + | ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK + | ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK); + } + + ///// + + // Restore original partition + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Restore original SRAM as %" PRIu32 ".\n", sram_orig); + status = alt_qspi_sram_partition_set(sram_orig); + } + + return status; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 4093831..768c01d 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -143,10 +143,18 @@ $(PROJECT_INCLUDE)/bsp/nocache-heap.h: include/nocache-heap.h $(PROJECT_INCLUDE) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/nocache-heap.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/nocache-heap.h +$(PROJECT_INCLUDE)/bsp/alt_16550_uart.h: hwlib/include/alt_16550_uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_16550_uart.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_16550_uart.h + $(PROJECT_INCLUDE)/bsp/alt_address_space.h: hwlib/include/alt_address_space.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_address_space.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_address_space.h +$(PROJECT_INCLUDE)/bsp/alt_cache.h: hwlib/include/alt_cache.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_cache.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_cache.h + $(PROJECT_INCLUDE)/bsp/alt_clock_group.h: hwlib/include/alt_clock_group.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_clock_group.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_clock_group.h @@ -155,6 +163,18 @@ $(PROJECT_INCLUDE)/bsp/alt_clock_manager.h: hwlib/include/alt_clock_manager.h $( $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_clock_manager.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_clock_manager.h +$(PROJECT_INCLUDE)/bsp/alt_dma_common.h: hwlib/include/alt_dma_common.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_dma_common.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_dma_common.h + +$(PROJECT_INCLUDE)/bsp/alt_dma.h: hwlib/include/alt_dma.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_dma.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_dma.h + +$(PROJECT_INCLUDE)/bsp/alt_dma_program.h: hwlib/include/alt_dma_program.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_dma_program.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_dma_program.h + $(PROJECT_INCLUDE)/bsp/alt_generalpurpose_io.h: hwlib/include/alt_generalpurpose_io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_generalpurpose_io.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_generalpurpose_io.h @@ -175,6 +195,10 @@ $(PROJECT_INCLUDE)/bsp/alt_mpu_registers.h: hwlib/include/alt_mpu_registers.h $( $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_mpu_registers.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_mpu_registers.h +$(PROJECT_INCLUDE)/bsp/alt_qspi_private.h: hwlib/include/alt_qspi_private.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_qspi_private.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_qspi_private.h + $(PROJECT_INCLUDE)/bsp/alt_reset_manager.h: hwlib/include/alt_reset_manager.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_reset_manager.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_reset_manager.h @@ -191,6 +215,14 @@ $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h: hwlib/include/socal/alt_clkmgr.h $(PR $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h +$(PROJECT_INCLUDE)/bsp/socal/alt_dmanonsecure.h: hwlib/include/socal/alt_dmanonsecure.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_dmanonsecure.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_dmanonsecure.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_dmasecure.h: hwlib/include/socal/alt_dmasecure.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_dmasecure.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_dmasecure.h + $(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h: hwlib/include/socal/alt_gpio.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h @@ -203,6 +235,14 @@ $(PROJECT_INCLUDE)/bsp/socal/alt_l3.h: hwlib/include/socal/alt_l3.h $(PROJECT_IN $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_l3.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_l3.h +$(PROJECT_INCLUDE)/bsp/socal/alt_qspidata.h: hwlib/include/socal/alt_qspidata.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_qspidata.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_qspidata.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_qspi.h: hwlib/include/socal/alt_qspi.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_qspi.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_qspi.h + $(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h: hwlib/include/socal/alt_rstmgr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h From sebh at rtems.org Tue Aug 26 15:12:23 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 26 Aug 2014 15:12:23 -0000 Subject: [rtems commit] bsp/altera-cyclone-v: Update to hwlib 13.1 Message-ID: <20140826150327.75170700812@git.rtems.org> Module: rtems Branch: master Commit: 9907ddeb5a1e823129ab7aeeeed1ed4f7a60151c Changeset: http://git.rtems.org/rtems/commit/?id=9907ddeb5a1e823129ab7aeeeed1ed4f7a60151c Author: Sebastian Huber Date: Tue Aug 26 16:59:56 2014 +0200 bsp/altera-cyclone-v: Update to hwlib 13.1 This version is distributed with SoC EDS 14.0.0.200. --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 3 +- .../libbsp/arm/altera-cyclone-v/hwlib/README.txt | 35 +- .../hwlib/include/alt_address_space.h | 461 ++- .../hwlib/include/alt_clock_group.h | 143 +- .../hwlib/include/alt_clock_manager.h | 107 +- .../hwlib/include/alt_generalpurpose_io.h | 246 +- .../hwlib/include/alt_hwlibs_ver.h | 16 +- .../hwlib/include/alt_interrupt_common.h | 2 + .../hwlib/include/alt_reset_manager.h | 42 + .../arm/altera-cyclone-v/hwlib/include/hwlib.h | 1 - .../hwlib/include/socal/alt_acpidmap.h | 3569 ++++++++++ .../altera-cyclone-v/hwlib/include/socal/socal.h | 181 +- .../hwlib/src/hwmgr/alt_address_space.c | 393 +- .../hwlib/src/hwmgr/alt_clock_manager.c | 7386 +++++++++++--------- .../hwlib/src/hwmgr/alt_generalpurpose_io.c | 32 + .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 10 +- 16 files changed, 8786 insertions(+), 3841 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index 939ccc7..a581dee 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -77,6 +77,7 @@ include_bsp_HEADERS += hwlib/include/hwlib.h #include_bsp_HEADERS += hwlib/include/alt_interrupt.h # Some of the headers from hwlib need the files from socal. Install them. +include_bsp_socal_HEADERS += hwlib/include/socal/alt_acpidmap.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_clkmgr.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_gpio.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_i2c.h @@ -118,7 +119,7 @@ libbsp_a_CPPFLAGS = libbsp_a_LIBADD = # for the Altera hwlib -libbsp_a_CPPFLAGS += -I ${srcdir}/hwlib/include +libbsp_a_CPPFLAGS += -I${srcdir}/hwlib/include libbsp_a_CPPFLAGS += -std=gnu99 CFLAGS += -Wno-missing-prototypes diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt index 154b343..d0f505d 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt @@ -16,37 +16,4 @@ Altera provides the hwlib with their SoC Embedded Design Suite (EDS). HWLIB Version: -------------- -The files have been taken from the following hwlib versions: - -|======================================== -| Version | File -| | -| 13.0SP1 | include/alt_address_space.h -| 13.0SP1 | include/alt_clock_group.h -| 13.0SP1 | include/alt_clock_manager.h -| 13.0SP1 | include/alt_generalpurpose_io.h -| 13.0SP1 | include/alt_hwlibs_ver.h -| 13.1 | include/alt_i2c.h -| 13.0SP1 | include/alt_interrupt_common.h -| 13.0SP1 | include/alt_mpu_registers.h -| 13.0SP1 | include/alt_reset_manager.h -| 13.0SP1 | include/hwlib.h -| 13.0SP1 | include/socal/alt_clkmgr.h -| 13.0SP1 | include/socal/alt_gpio.h -| 13.1 | include/socal/alt_i2c.h -| 13.0SP1 | include/socal/alt_l3.h -| 13.0SP1 | include/socal/alt_rstmgr.h -| 13.0SP1 | include/socal/alt_sdr.h -| 13.0SP1 | include/socal/alt_sysmgr.h -| 13.0SP1 | include/socal/alt_uart.h -| 13.0SP1 | include/socal/hps.h -| 13.0SP1 | include/socal/socal.h -| 13.0SP1 | src/hwmgr/alt_address_space.c -| 13.0SP1 | src/hwmgr/alt_clock_manager.c -| 13.0SP1 | src/hwmgr/alt_generalpurpose_io.c -| 13.1 | src/hwmgr/alt_i2c.c -| 13.0SP1 | src/hwmgr/alt_reset_manager.c -|======================================== - -hwlib 13.0SP1 is from SoC EDS 13.0.1.232 -hwlib 13.1 is from SoC EDS 14.0.0.200 +All files are from hwlib 13.1 distributed with SoC EDS 14.0.0.200. diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h index b66ccdf..781cc49 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h @@ -32,8 +32,8 @@ * ******************************************************************************/ -#ifndef __ALT_ADDR_SPACE_H__ -#define __ALT_ADDR_SPACE_H__ +#ifndef __ALT_ADDRESS_SPACE_H__ +#define __ALT_ADDRESS_SPACE_H__ #include #include "hwlib.h" @@ -82,7 +82,7 @@ extern "C" #define L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST) // Address Filtering End Register - End Value Mask #define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000 -// Address Filtering End Register - Reset End Address Value (3 GB) +// Address Filtering End Register - Reset End Address Value (3 GiB) #define L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000 #ifndef __ASSEMBLY__ @@ -192,10 +192,10 @@ typedef enum ALT_ADDR_SPACE_MPU_ATTR_e */ typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e { - ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM, /*!< Maps the SDRAM to address 0x0 + ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, /*!< Maps the SDRAM to address 0x0 * for the non-MPU L3 masters. */ - ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM /*!< Maps the On-chip RAM to address + ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address * 0x0 for the non-MPU L3 * masters. Note that the On-chip * RAM is also always mapped to @@ -276,12 +276,12 @@ ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, * * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest * 64KB of the boot region are accessible because the size of the Boot ROM and - * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MB) to - * 0xC0000000 (3GB) access SDRAM and addresses in the range 0xC0000000 (3GB) to - * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MB of SDRAM is not + * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MiB) to + * 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to + * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not * accessible to the MPU unless address 0 is remapped to SDRAM after reset. * - * This function remaps the addresses between 0x0 to 0x100000 (1MB) to access + * This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access * SDRAM. * * \internal @@ -332,13 +332,13 @@ ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void); * \param addr_filt_start * [out] An output parameter variable for the address filtering * start address for the range of physical addresses redirected to - * the SDRAM AXI master port. The value returned is always a 1 MB + * the SDRAM AXI master port. The value returned is always a 1 MiB * aligned address. * * \param addr_filt_end * [out] An output parameter variable for the address filtering * end address for the range of physical addresses redirected to - * the SDRAM AXI master port. The value returned is always a 1 MB + * the SDRAM AXI master port. The value returned is always a 1 MiB * aligned address. * * \retval ALT_E_SUCCESS The operation was successful. @@ -353,7 +353,7 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start, /*! * Set the L2 cache address filtering configuration settings. * - * Address filtering start and end values must be 1 MB aligned. + * Address filtering start and end values must be 1 MiB aligned. * * \param addr_filt_start * The address filtering start address for the range of physical @@ -380,6 +380,441 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, /*! @} */ +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping + * + * This API provides management of the ACP ID Mapper that enables data coherent + * access to the MPU address space by external masters. The set of external + * masters include L3 master peripherals and FPGA soft IP. + * + * The Accelerator Coherency Port (ACP) allows peripherals - including FPGA + * based soft IP - to maintain data coherency with the Cortex-A9 MPCore + * processors and the Snoop Control Unit (SCU). + * + * The ACP supports up to six masters. However, soft IP implemented in the FPGA + * fabric can have a larger number of masters that need to access the ACP. The + * ACP ID Mapper expands the number of masters able to access the ACP. The ACP + * ID Mapper is situated between the interconnect and the ACP of the MPU + * subsystem. It has the following characteristics: + * * Support for up to six concurrent ID mappings. + * * 1 GiB coherent window into 4 GiB MPU address space + * * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU) + * and L2 cache. + * + * The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller + * Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input + * identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output + * identifiers) required by the ACP slave port. + * + * The ACP ID Mapper supports the two ID mapping modes: + * * Dynamic Mapping - In this mode an input ID is automatically mapped to an + * available output ID. The dynamic mode is more flexible because the hardware + * handles the mapping. The hardware mapping allows an output ID to be used + * for more than one input ID. Output IDs are assigned to input IDs on a + * first-come, first-served basis. + * * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs + * to output IDs. + * + * Out of the total of eight ACP output ID values, only six are available to the + * ACP ID Mapper for remapping. The first two output IDs (0 and 1) are + * dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the + * last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6 + * support fixed and dynamic modes of operation while output ID 7 supports + * dynamic mode only. + * + * The following table summarizes the usage of the 3-bit ouput ID values by the + * ACP ID Mapper and their settings at reset. + * + * Output ID | Usage | Reset State + * :-----------|:--------------------------------------------------|:------------ + * 0 | Reserved for Cortex-A9 cores. | - + * 1 | Reserved for Cortex-A9 cores. | - + * 2 | Assigned to Debug Access Port (DAP) input ID at | Fixed + * : | reset. After reset, can be reconfigured to either | DAP Master + * : | fixed or dynamic. |: + * 3 | Configurable fixed or dynamic mode. | Dynamic + * 4 | Configurable fixed or dynamic mode. | Dynamic + * 5 | Configurable fixed or dynamic mode. | Dynamic + * 6 | Configurable fixed or dynamic mode. | Dynamic + * 7 | Dynamic mode only. | Dynamic + * + * Where Output ID is the ACP ID Mapper output value that goes to the ACP. + * + * Additionally, for masters unable to drive the AXI user sideband signals of + * incoming transactions, the ACP ID Mapper allows control of the AXI user + * sideband signal values. Not all masters drive these signals, so the ACP ID + * Mapper makes it possible to drive the 5-bit user sideband signal with either + * a default value (in dynamic mode) or specific values (in fixed mode). + * + * The ACP ID Mapper can also control which 1 GiB coherent window into memory is + * accessed by masters of the L3 interconnect. Each fixed mapping can be + * assigned a different user sideband signal and memory window to allow specific + * settings for different masters. All dynamic mappings share a common user + * sideband signal and memory window setting. One important exception, however, + * is that the ACP ID mapper always allows user sideband signals from the + * FPGA-to-HPS bridge to pass through to the ACP regardless of the configured + * user sideband value associated with the ID. + * + * The ACP ID Mapper has a 1 GiB address window into the MPU address space, which + * is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows + * transactions to be routed to different 1 GiB-sized memory views, called pages, + * in both dynamic and fixed modes. + * + * See: Chapter 6: Cortex-A9 Microprocessor Unit Subsystem in + * Volume 3: Hard Processor System Technical Reference Manual of the + * Arria V or Cyclone V Device Handbook for a complete discussion of + * the operation and restrictions on the ACP and the ACP ID Mapper. + * + * @{ + */ + +/******************************************************************************/ +/*! + * \name External Master ID Macros + * + * These macros define the HPS external master identifiers that are 12-bit input + * IDs to the ACP ID Mapper. Some of the masters have a range of identifier + * values assigned to them and are distinguished by taking a (var)\ + * argument. + * @{ + */ + +/*! Bit mask for the relevant 12 bits of an external master ID */ +#define ALT_ACP_ID_MAP_MASTER_ID_MASK 0xfff + +/*! Master ID for L2M0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var) (0x00000002 | (0x000007f8 & (var))) +/*! Master ID for DMA */ +#define ALT_ACP_ID_MAP_MASTER_ID_DMA(var) (0x00000001 | (0x00000078 & (var))) +/*! Master ID for EMAC0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var) (0x00000801 | (0x00000878 & (var))) +/*! Master ID for EMAC1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var) (0x00000802 | (0x00000878 & (var))) +/*! Master ID for USB0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB0 0x00000803 +/*! Master ID for USB1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB1 0x00000806 +/*! Master ID for NAND controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_NAND(var) (0x00000804 | (0x00000ff8 & (var))) +/*! Master ID for Embedded Trace Router (ETR) */ +#define ALT_ACP_ID_MAP_MASTER_ID_TMC 0x00000800 +/*! Master ID for Debug Access Port (DAP) */ +#define ALT_ACP_ID_MAP_MASTER_ID_DAP 0x00000004 +/*! Master ID for SD/MMC controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_SDMMC 0x00000805 +/*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */ +#define ALT_ACP_ID_MAP_MASTER_ID_F2H(var) (0x00000000 | (0x000007f8 & (var))) +/*! @} */ + +/******************************************************************************/ +/*! + * This type defines the enumerations 3-bit output ids to ACP ID mapper. + */ +typedef enum ALT_ACP_ID_OUTPUT_ID_e +{ + ALT_ACP_ID_OUT_FIXED_ID_2 = 2, /*!< Assigned to the input ID of the DAP at reset. + * After reset, can be either fixed or dynamic, + * programmed by software. + */ + ALT_ACP_ID_OUT_DYNAM_ID_3 = 3, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_4 = 4, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_5 = 5, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_6 = 6, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_7 = 7 /*!< Dynamic mapping only */ +} ALT_ACP_ID_OUTPUT_ID_t; + +/*! + * This type defines the enumerations used to specify the 1 GiB page view of the + * MPU address space used by an ACP ID mapping configuration. + */ +typedef enum ALT_ACP_ID_MAP_PAGE_e +{ + ALT_ACP_ID_MAP_PAGE_0 = 0, /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_1 = 1, /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_2 = 2, /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */ + ALT_ACP_ID_MAP_PAGE_3 = 3 /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */ +} ALT_ACP_ID_MAP_PAGE_t; + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for read transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating read transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates read + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for write transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating write transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates write + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e awuser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for read + * transactions. The \e output_id value is available for dynamic assignment to + * external master read transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_read_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for write + * transactions. The \e output_id value is available for dynamic assignment to + * external master write transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_write_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the page and user read sideband signal options that are applied to + * all read transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e aruser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure the page and user write sideband signal options that are applied to + * all write transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e awuser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Return the current read transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param aruser + * [out] The 5-bit AXI ARUSER read user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* aruser); + +/******************************************************************************/ +/*! + * Return the current write transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param awuser + * [out] The 5-bit AXI AWUSER write user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* awuser); + +/*! @} */ + /*! @} */ #endif /* __ASSEMBLY__ */ @@ -387,4 +822,4 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, #ifdef __cplusplus } #endif /* __cplusplus */ -#endif /* __ALT_ADDR_SPACE_H__ */ +#endif /* __ALT_ADDRESS_SPACE_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h index a5e8c92..a43608e 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h @@ -1,37 +1,39 @@ -/*! \file - * Contains the definition of an opaque data structure that contains raw - * configuration information for a clock group. - */ - /****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! + * \file + * + * Contains the definition of an opaque data structure that contains raw + * configuration information for a clock group. + */ #ifndef __ALT_CLK_GRP_H__ #define __ALT_CLK_GRP_H__ @@ -44,48 +46,65 @@ extern "C" { #endif /* __cplusplus */ - -/*! This type definition enumerates the clock groups -*/ +/*! + * This type definition enumerates the clock groups + */ typedef enum ALT_CLK_GRP_e { - ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ + ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ - ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ + ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ - ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ + ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ } ALT_CLK_GRP_t; - - -/*! This type definition defines an opaque data structure for holding the - * configuration settings for a complete clock group. +/*! + * This type definition defines an opaque data structure for holding the + * configuration settings for a complete clock group. */ typedef struct ALT_CLK_GROUP_RAW_CFG_s { - uint32_t verid; /*!< SoC FPGA version identifier. This field - * encapsulates the silicon identifier and - * version information associated with this - * clock group configuration. It is used to - * assert that this clock group configuration - * is valid for this device. - */ - uint32_t siliid2; /*!< Reserved register - reserved for future - * device IDs or capability flags/ - */ - ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator */ - - - /*! This union holds the raw register values for configuration of the set of - * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator - * identifies the valid clock group union data member. + uint32_t verid; /*!< SoC FPGA version identifier. This field + * encapsulates the silicon identifier and + * version information associated with this + * clock group configuration. It is used to + * assert that this clock group configuration + * is valid for this device. */ + + uint32_t siliid2; /*!< Reserved register - reserved for future + * device IDs or capability flags. */ + + ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */ + + /*! + * This union holds the register values for configuration of the set of + * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator + * identifies the valid clock group union data member. */ union ALT_CLK_GROUP_RAW_CFG_u { - ALT_CLKMGR_MAINPLL_t mainpllgrp; /*!< Raw clock group configuration for Main PLL group */ - ALT_CLKMGR_PERPLL_t perpllgrp; /*!< Raw clock group configuration for Peripheral PLL group */ - ALT_CLKMGR_SDRPLL_t sdrpllgrp; /*!< Raw clock group configuration for SDRAM PLL group */ + /*! Clock group configuration for Main PLL group. */ + union + { + ALT_CLKMGR_MAINPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */ + } mainpllgrp; + + /*! Clock group configuration for Peripheral PLL group. */ + union + { + ALT_CLKMGR_PERPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */ + } perpllgrp; + + /*! Clock group configuration for SDRAM PLL group. */ + union + { + ALT_CLKMGR_SDRPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */ + } sdrpllgrp; + } clkgrp; } ALT_CLK_GROUP_RAW_CFG_t; diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h index 7cf0e12..d6d9654 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h @@ -6,20 +6,20 @@ /****************************************************************************** * * Copyright 2013 Altera Corporation. All Rights Reserved. -* +* * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* +* * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* +* * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* +* * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. -* +* * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO @@ -30,7 +30,7 @@ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. -* +* ******************************************************************************/ #ifndef __ALT_CLK_MGR_H__ @@ -82,7 +82,7 @@ typedef enum ALT_CLK_e /*!< \b OSC_CLK_2_HPS * External Oscillator input: * * Input Pin - * * Optional clock source to SDRAM PLL + * * Optional clock source to SDRAM PLL * and Peripheral PLL if selected * * Typically used for Ethernet * reference clock @@ -132,7 +132,7 @@ typedef enum ALT_CLK_e * * Input Pin */ - + /* PLLs */ ALT_CLK_MAIN_PLL, /*!< \b main_pll_ref_clkin @@ -142,7 +142,7 @@ typedef enum ALT_CLK_e */ ALT_CLK_PERIPHERAL_PLL, - /*!< \b periph_pll_ref_clkin + /*!< \b periph_pll_ref_clkin * Peripheral PLL input reference * clock, used to designate the * Peripheral PLL in PLL clock @@ -236,7 +236,7 @@ typedef enum ALT_CLK_e ALT_CLK_L4_SP, /*!< \b l4_sp_clk - * Clock for L4 slave peripherals (SP) bus + * Clock for L4 slave peripherals (SP) bus */ ALT_CLK_DBG_BASE, @@ -279,14 +279,14 @@ typedef enum ALT_CLK_e */ ALT_CLK_MAIN_NAND_SDMMC, - /*!< \b main_nand_sdmmc_clk + /*!< \b main_nand_sdmmc_clk * Main PLL C4 Output. Input clock to * flash controller clocks block. * * Alias for \e ALT_CLK_MAIN_PLL_C4 */ ALT_CLK_CFG, - /*!< \b cfg_clk + /*!< \b cfg_clk * FPGA manager configuration clock. */ @@ -295,7 +295,7 @@ typedef enum ALT_CLK_e * Clock to FPGA fabric */ - + /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */ ALT_CLK_PERIPHERAL_PLL_C0, /*!< \b Peripheral PLL C0 Output */ @@ -556,7 +556,7 @@ typedef enum ALT_CLK_PLL_LOCK_STATUS_e * assertion conditions. * * \param lock_stat_mask - * Specifies the PLL lock status conditions to clear. \e lock_stat_mask + * Specifies the PLL lock status conditions to clear. \e lock_stat_mask * is a mask of logically OR'ed \ref ALT_CLK_PLL_LOCK_STATUS_t * values designating the PLL lock conditions to clear. * @@ -588,12 +588,12 @@ uint32_t alt_clk_lock_status_get(void); * * \retval ALT_E_TRUE The specified PLL is currently locked. * \retval ALT_E_FALSE The specified PLL is currently not locked. - * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock + * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock * value. * \internal * NOTE: This function uses the * * \b hps::clkmgr::inter::mainplllocked - * * \b hps::clkmgr::inter::perplllocked, + * * \b hps::clkmgr::inter::perplllocked, * * \b hps::clkmgr::inter::sdrplllocked * * bits to determine if the PLL is locked or not. @@ -612,30 +612,30 @@ ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll); * request from the reset manager sets the safe mode bit in the clock manager * control register. No other control register bits are affected by the safe * mode request from the reset manager. - * + * * While in safe mode, clock manager register settings which control clock * behavior are not changed. However, the output of the registers which control * the clock manager state are forced to the safe mode values such that the * following conditions occur: * * All PLLs are bypassed to the \b osc1_clk clock, including their counters. * * Clock dividers select their default reset values. - * * The flash controllers source clock selections are set to the peripheral + * * The flash controllers source clock selections are set to the peripheral * PLL. * * All clocks are enabled. * * Safe mode is optionally applied to debug clocks. - * + * * A write by software is the only way to clear the safe mode bit. All registers * and clocks need to be configured correctly and all software-managed clocks * need to be gated off before clearing safe mode. Software can then gate clocks * on as required. - * + * * On cold reset, all clocks are put in safe mode. - * + * * On warm reset, safe mode is optionally and independently applied to debug * clocks and normal (i.e.non-debug) clocks based on clock manager register * settings. The default response for warm reset is to put all clocks in safe * mode. - * + * * The APIs in this group provide control of the Clock Manager safe mode warm * reset response behavior. * @{ @@ -651,12 +651,12 @@ typedef enum ALT_CLK_SAFE_DOMAIN_e /*! * This enumeration literal specifies the normal safe mode domain. The * normal domain consists of all clocks except debug clocks. - */ + */ ALT_CLK_DOMAIN_NORMAL, /*! * This enumeration literal specifies the debug safe mode domain. The debug * domain consists of all debug clocks. - */ + */ ALT_CLK_DOMAIN_DEBUG } ALT_CLK_SAFE_DOMAIN_t; @@ -703,7 +703,7 @@ bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain); * * In summary, the PLL bypass controls permit: * * Each PLL to be individually bypassed. - * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs + * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs * reference clock input source reference clock selection. * * Isolation of a the PLL VCO frequency registers (multiplier and divider), phase shift registers (negative phase) , and post scale counters. @@ -720,7 +720,7 @@ bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL clock + * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL clock * value. */ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll); @@ -751,7 +751,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, /*! * Return whether the specified PLL is in bypass or not. * - * \internal + * \internal * This function must also test the \b clkmgr.ctrl.safemode bit in * addition to the PLLs bypass bit to tell whether the bypass mode is * effect or not. @@ -762,7 +762,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, * * \retval ALT_E_TRUE The PLL is in bypass mode. * \retval ALT_E_FALSE The PLL is not in bypass mode. - * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock + * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock * value. */ ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll); @@ -824,7 +824,7 @@ ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock + * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock * value. */ ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk); @@ -839,7 +839,7 @@ ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock + * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock * value. */ ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk); @@ -853,7 +853,7 @@ ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk); * * \retval ALT_E_TRUE The clock is enabled. * \retval ALT_E_FALSE The clock is not enabled. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock + * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock * value. */ ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk); @@ -912,12 +912,12 @@ ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk); * Get the input reference clock source selection value for the specified clock * or PLL. * - * NOTE: This function returns a clock value even though \e clk may specify a - * clock that does not have a selectable input reference clock source. In - * this case, the clock value returned is the static clock source for the + * NOTE: This function returns a clock value even though \e clk may specify a + * clock that does not have a selectable input reference clock source. In + * this case, the clock value returned is the static clock source for the * specified clock. For example calling alt_clk_source_get() with \e clk * set to \ref ALT_CLK_MAIN_PLL will return \ref ALT_CLK_OSC1. - * + * * \param clk * The clock or PLL to retrieve the input reference clock source * selection value for. @@ -939,14 +939,14 @@ ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a clock that - * does not have a selectable input reference + * \retval ALT_E_BAD_ARG The \e clk argument designates a clock that + * does not have a selectable input reference * clock source. - * \retval ALT_E_INV_OPTION The \e ref_clk argument designates a clock that - * is an invalid reference clock source for the + * \retval ALT_E_INV_OPTION The \e ref_clk argument designates a clock that + * is an invalid reference clock source for the * specified clock. */ -ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, +ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk); /*! @} */ @@ -981,7 +981,7 @@ ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG A bad argument value was passed. Either the \e clk - * argument is bad or not a valid external clock + * argument is bad or not a valid external clock * source * \retval ALT_E_ARG_RANGE The frequency value violates the range constraints * for the specified clock. @@ -1018,17 +1018,17 @@ alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk); typedef struct ALT_CLK_PLL_CFG_s { ALT_CLK_t ref_clk; /*!< PLL Reference Clock Source */ - uint32_t mult; /*!< VCO Frequency Configuration - + uint32_t mult; /*!< VCO Frequency Configuration - * Multiplier (M) value, range 1 to 4096 */ - uint32_t div; /*!< VCO Frequency Configuration - + uint32_t div; /*!< VCO Frequency Configuration - * Divider (N) value, range 1 to 64 */ uint32_t cntrs[6]; /*!< Post-Scale Counters (C0 - C5) - * range 1 to 512 */ uint32_t pshift[6]; /*!< Phase Shift - 1/8 (45 degrees) of - * negative phase shift per increment, + * negative phase shift per increment, * range 0 to 4096 */ } ALT_CLK_PLL_CFG_t; @@ -1262,7 +1262,7 @@ ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, * The following interrupt request (IRQ) signals are sourced from the Clock * Manager: * - * * \b clkmgr_IRQ - Clock Manager lock status interrupt output. The PLL lock + * * \b clkmgr_IRQ - Clock Manager lock status interrupt output. The PLL lock * status interrupt is the logical \e OR of six interrupt * sources defining the loss or achievement of lock status for * each PLL. The six PLL lock status conditions are: @@ -1275,7 +1275,7 @@ ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, * * They are enumeratated by the type \ref ALT_CLK_PLL_LOCK_STATUS_t. * - * Each PLL lock condition may be individually disabled/enabled + * Each PLL lock condition may be individually disabled/enabled * as a contributor to the determination of the \b clkmgr_IRQ * assertion status. * @@ -1283,7 +1283,7 @@ ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, * the PLL lock conditions causing the \b clkmgr_IRQ * assertion. * - * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the + * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the * MPU to "wake up" after a transition of the Main PLL into * or out of bypass mode has been safely achieved. The need * for the "wake up" notification is because the PLL clocks @@ -1368,14 +1368,14 @@ ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask); * * A known good clock group configuration may be generated by one of the * following methods: - * - * * As static design information generated by an ACDS clock configuration tool + * + * * As static design information generated by an ACDS clock configuration tool * and passed to embedded software for dynamic loading. - * + * * * By calling alt_clk_group_cfg_raw_get() at run-time from an SoC FPGA that has * programmatically established a known good clock group configuration using * the clock manager API configuration functions. - * + * * @{ */ @@ -1407,7 +1407,7 @@ ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, * * This function is used to safely set the configuration state of a clock * group from a raw clock group configuration specification. The raw clock - * group configuration specification may be a configuration previously + * group configuration specification may be a configuration previously * captured with alt_clk_group_cfg_raw_get() or a group clock configuration * generated by an external utility. * @@ -1422,10 +1422,13 @@ ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, */ ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg); +ALT_STATUS_CODE alt_clk_clkmgr_init(void); + /*! @} */ /*! @} */ #ifdef __cplusplus } + #endif /* __cplusplus */ #endif /* __ALT_CLK_MGR_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h index d8a38f5..0a7abae 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h @@ -5,20 +5,20 @@ /****************************************************************************** * * Copyright 2013 Altera Corporation. All Rights Reserved. -* +* * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* +* * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* +* * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* +* * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. -* +* * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO @@ -29,7 +29,7 @@ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. -* +* ******************************************************************************/ #ifndef __ALT_GPIO_H__ @@ -57,8 +57,8 @@ extern "C" { /******************************************************************************/ /*! \addtogroup ALT_GPIO_API The General Purpose Input/Output Manager API * - * This module defines the General Purpose Input/Output Manager API for - * accessing, configuring, and controlling the General Purpose Input/Output + * This module defines the General Purpose Input/Output Manager API for + * accessing, configuring, and controlling the General Purpose Input/Output * Manager resources. These include both the general-purpose GPIO signals and * the input-only GPI signals that are shared with the DDR interface.\n \n * The GPIO API presents two views or perspectives of the GPIO signals. The first @@ -100,7 +100,7 @@ extern "C" { */ /******************************************************************************/ /*! - * This type definition enumerates the data direction (input or output) of + * This type definition enumerates the data direction (input or output) of * the GPIO signals. */ @@ -114,7 +114,7 @@ typedef enum ALT_GPIO_PIN_DIR_e /******************************************************************************/ /*! - * This type definition enumerates the type of interrupt source + * This type definition enumerates the type of interrupt source * (level-triggered or edge-triggered) of the GPIO signals. */ @@ -128,7 +128,7 @@ typedef enum ALT_GPIO_PIN_TYPE_e /******************************************************************************/ /*! - * This type definition enumerates the polarity of the interrupt sources + * This type definition enumerates the polarity of the interrupt sources * (falling-edge or rising-edge for edge-triggered interrupts, active-low or * active-high for level-triggered interrupts) of the GPIO signals. */ @@ -193,7 +193,7 @@ typedef enum ALT_GPIO_PIN_DATA_e /******************************************************************************/ /*! - * This type definition enumerates the GPIO ports that the GPIO manager + * This type definition enumerates the GPIO ports that the GPIO manager * handles. */ @@ -208,7 +208,7 @@ typedef enum ALT_GPIO_PORT_e * \b Port \b B - 29-bit GPIO port B. */ ALT_GPIO_PORTB, - + /*! * \b Port \b C - 29-bit GPIO port C. \n 13 bits are used for GPIO signals, * 14 bits are used for GPI-only signals that are shared @@ -224,12 +224,12 @@ typedef enum ALT_GPIO_PORT_e ALT_GPIO_PORT_UNKNOWN } ALT_GPIO_PORT_t; - + /******************************************************************************/ /*! * This type definition enumerates the individual bits within the GPIO ports - * used by the GPIO manager. The bit-ordering must match the hardware - * bit-ordering. Since the ordering and packing of bitfields is not + * used by the GPIO manager. The bit-ordering must match the hardware + * bit-ordering. Since the ordering and packing of bitfields is not * standardized in C/C++, the following are defined as masks. \n * For example, to set bits 3 and 4 of GPIO port B outputs (assuming the bits * had previously been set to outputs), the user could use the syntax: \par @@ -310,20 +310,38 @@ typedef enum ALT_GPIO_PORTBIT_e /******************************************************************************/ /*! - * Sets the specified GPIO data bits to use the data direction(s) + * Initialize the GPIO modules before use + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_init(void); + +/******************************************************************************/ +/*! + * Uninitialize the GPIO modules & return to reset state + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_uninit(void); + +/******************************************************************************/ +/*! + * Sets the specified GPIO data bits to use the data direction(s) * specified. * * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this - * operation to. Other bits (where mask bits equal zero) are + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * configure all data direction bits of the port. * \param config * The data-directions of the bits to be set in this operation. - * Individual bits are: \n \b 0 - Use as an input (default). \n + * Individual bits are: \n \b 0 - Use as an input (default). \n * \b 1 - Use as an output. * * \retval ALT_E_SUCCESS The operation was successful. @@ -335,18 +353,18 @@ ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Returns the data direction configuration of selected bits of the + * Returns the data direction configuration of selected bits of the * specified GPIO module. * * \param gpio_pid * The GPIO port identifier. * \param mask * The group of bits (where mask bits equal one) to read and - * return. Other bits (where mask bits equal zero) are returned + * return. Other bits (where mask bits equal zero) are returned * as zero. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * return all data direction bits of the port. * - * \retval uint32_t \n Individual bits are: \n \b 0 - The signal is + * \retval uint32_t \n Individual bits are: \n \b 0 - The signal is * configured as an input. * \n \b 1 - The signal is configured as an output. * @@ -367,7 +385,7 @@ uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid, * operation to. Other bits (mask bits equal zero) are * not changed. * \param val - * The 32-bit word to write to the GPIO outputs. Only the 29 LSBs + * The 32-bit word to write to the GPIO outputs. Only the 29 LSBs * are used. Setting the three MSBs causes an error. * * \retval ALT_E_SUCCESS The operation was successful. @@ -387,8 +405,8 @@ ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all data bits of * the port. * @@ -408,21 +426,21 @@ uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask); */ /******************************************************************************/ /*! - * Sets edge-triggered or level-triggered interrupt configuration for the + * Sets edge-triggered or level-triggered interrupt configuration for the * specified signals of the specified GPIO module. * * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this + * The group of bits (where mask bits equal one) to apply this * operation to. Other bits (where mask bits equal zero) are * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * configure all interrupt type bits of the port. * \param config - * The interrupt configuration to write. Individual bits - * are: \n \b 0 - Set the - * interrupt for this bit to be level-sensitive (default). \n \b + * The interrupt configuration to write. Individual bits + * are: \n \b 0 - Set the + * interrupt for this bit to be level-sensitive (default). \n \b * 1 - Set the interrupt for this bit to be edge-sensitive. * * \retval ALT_E_SUCCESS The operation was successful. @@ -434,20 +452,20 @@ ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Returns the interrupt configuration (edge-triggered or level-triggered) for - * the specified bits of the specified GPIO module. + * Returns the interrupt configuration (edge-triggered or level-triggered) for + * the specified bits of the specified GPIO module. * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all configuration * bits of the port. * \retval uint32_t - * The current interrupt source configuration. Individual bits - * are: \n \b 0 - The interrupt for this bit is set to be - * level-sensitive. \n \b 1 - + * The current interrupt source configuration. Individual bits + * are: \n \b 0 - The interrupt for this bit is set to be + * level-sensitive. \n \b 1 - * The interrupt for this bit is set to be edge-sensitive. * */ @@ -463,12 +481,12 @@ uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this + * The group of bits (where mask bits equal one) to apply this * operation to. Other bits (where mask bits equal zero) are * not changed. * \param config - * The interrupt polarity configuration to set. Individual bits - * are: \n \b 0 - Set the interrupt polarity for this bit to + * The interrupt polarity configuration to set. Individual bits + * are: \n \b 0 - Set the interrupt polarity for this bit to * active-low or falling-edge mode (default). \n \b 1 - Set the * interrupt polarity for this bit to active-high or rising-edge mode. * @@ -481,21 +499,21 @@ ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Returns the active-high or active-low polarity configuration for the + * Returns the active-high or active-low polarity configuration for the * possible interrupt sources of the specified GPIO module. * * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all the * configuration bits of the port. - * + * * \retval uint32_t - * The current polarity configuration. Individual bits are: \n - * \b 0 = The interrupt polarity for this bit is set to + * The current polarity configuration. Individual bits are: \n + * \b 0 = The interrupt polarity for this bit is set to * active-low or falling-edge mode. \n \b 1 = The interrupt * polarity for this bit is set to active-high or rising-edge mode. * @@ -512,7 +530,7 @@ uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid, */ /******************************************************************************/ /*! - * Sets the debounce configuration for input signals of the specified GPIO + * Sets the debounce configuration for input signals of the specified GPIO * module. If debounce is selected, metastability flip-flops are inserted to * debounce signals presented to the GPIO inputs. A signal must be steady for * two periods of the gpio_db_clk clock before it is considered valid. The @@ -521,13 +539,13 @@ uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this + * The group of bits (where mask bits equal one) to apply this * operation to. Other bits (where mask bits equal zero) are * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * configure the debounce setting for all bits of the port. * \param config * The debounce configuration to set. Individual bits are: \n - * \b 0 - Debounce is not selected for this signal (default). \n + * \b 0 - Debounce is not selected for this signal (default). \n * \b 1 - Debounce is selected for this signal. * * \retval ALT_E_SUCCESS The operation was successful. @@ -546,14 +564,14 @@ ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all debounce * configuration bits of the port. - * + * * \retval uint32_t - * The current debounce configuration.Individual bits are: \n - * \b 0 - Debounce is not selected for this signal. \n \b 1 - + * The current debounce configuration.Individual bits are: \n + * \b 0 - Debounce is not selected for this signal. \n \b 1 - * Debounce is selected for this signal. * */ @@ -562,8 +580,8 @@ uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Sets the synchronization configuration for the signals of the specified - * GPIO register. This allows for synchronizing level-sensitive interrupts to + * Sets the synchronization configuration for the signals of the specified + * GPIO register. This allows for synchronizing level-sensitive interrupts to * an internal clock signal. This is a port-wide option that controls all * level-sensitive interrupt signals of that GPIO port. * @@ -572,7 +590,7 @@ uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid, * \param config * \n \b Any \b non-zero \b value - Synchronize to internal clock signal. * \n \b Zero - Do not synchronize to internal clock signal. - * + * * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. @@ -584,8 +602,8 @@ ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! * - * Returns the synchronization configuration for the signals of the - * specified GPIO register. This allows for synchronizing level-sensitive + * Returns the synchronization configuration for the signals of the + * specified GPIO register. This allows for synchronizing level-sensitive * interrupts to the internal clock signal. This is a port-wide option that * controls all level-sensitive interrupt signals of that GPIO port. * @@ -605,7 +623,7 @@ ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid); /*! * Configures a group of GPIO signals with identical setup parameters. Allows * for configuring all parameters of a given port at one time. - * + * * \param gpio_pid * The GPIO port identifier. * \param mask @@ -621,11 +639,11 @@ ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid); * Debounce signals or not. * \param data * Set the data output to this value. - * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid, uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, @@ -699,11 +717,11 @@ uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid); * \param gpio_pid * The GPIO port identifier. * \param mask - * Which bits to change among the port \n \b 0 = + * Which bits to change among the port \n \b 0 = * Do not change this bit. \n \b 1 = Allow this bit to change. * \param val - * The interrupt mask to write. Individual bits are: \n \b 0 = - * Do not mask the interrupt for this bit (default). \n \b 1 = + * The interrupt mask to write. Individual bits are: \n \b 0 = + * Do not mask the interrupt for this bit (default). \n \b 1 = * Mask the interrupt for this bit. * * \retval ALT_E_SUCCESS The operation was successful. @@ -720,10 +738,10 @@ ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid, * * \param gpio_pid * The GPIO port identifier. - * + * * \retval uint32_t - * The interrupt mask that was read. Individual bits are: \n - * \b 0 = The interrupt for this bit is not masked. \n \b 1 = The + * The interrupt mask that was read. Individual bits are: \n + * \b 0 = The interrupt for this bit is not masked. \n \b 1 = The * interrupt for this bit is masked. * */ @@ -731,16 +749,16 @@ uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid); /******************************************************************************/ /*! - * Returns the interrupt pending status of all signals of the specified GPIO + * Returns the interrupt pending status of all signals of the specified GPIO * register. * * * \param gpio_pid * The GPIO port identifier. - + * \retval uint32_t - * The current interrupt pending status. Individual bits are: \n - * \b 0 - The interrupt for this bit is not pending. \n \b 1 - + * The current interrupt pending status. Individual bits are: \n + * \b 0 - The interrupt for this bit is not pending. \n \b 1 - * The interrupt for this bit is pending. * */ @@ -748,15 +766,15 @@ uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid); /******************************************************************************/ /*! - * Clear the interrupt pending status of selected signals of the + * Clear the interrupt pending status of selected signals of the * specified GPIO register. * * * \param gpio_pid * The GPIO port identifier. * \param clrmask - * The interrupt bits to clear. Individual bits are: \n \b 0 - - * The interrupt for this bit will not be changed. \n \b 1 - + * The interrupt bits to clear. Individual bits are: \n \b 0 - + * The interrupt for this bit will not be changed. \n \b 1 - * The interrupt for this bit will be cleared. * * \retval ALT_E_SUCCESS The operation was successful. @@ -1029,7 +1047,7 @@ typedef struct ALT_GPIO_PIN_RECORD_s /******************************************************************************/ /*! * Configures all parameters for one bit (signal) of the GPIO ports. - * + * * \param signal_num * The GPIO port signal index. * \param dir @@ -1043,7 +1061,7 @@ typedef struct ALT_GPIO_PIN_RECORD_s * \param data * If the GPIO signal is set to be an output, set it to * this value - * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. @@ -1056,78 +1074,78 @@ ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num, /******************************************************************************/ /*! * Returns the configuration parameters of a given GPIO bit. - * + * * \param signal_num * The GPIO port signal index. * \param config * Pointer to a single GPIO_CONFIG_RECORD_s configuration record. * The fields of this configuration record are filled in - * by the function. - * + * by the function. + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num, ALT_GPIO_CONFIG_RECORD_t *config); /******************************************************************************/ /*! - * Configures a list of GPIO bits. The GPIO bits do not have to be - * configured the same, as was the case for the mask version of this function, + * Configures a list of GPIO bits. The GPIO bits do not have to be + * configured the same, as was the case for the mask version of this function, * alt_gpio_port_config(). Each bit may be configured differently and bits may * be listed in any order. - * + * * \param config_array * Pointer to an array of GPIO_CONFIG_RECORD_s configuration * records. These definitions contain all the parameters - * needed to set up the listed pins. All or - * any subset of the GPIO signals can be configured. Signals do - * not have to be listed in numerical order or be unique. If a - * signal number is listed multiple times, the last configuration + * needed to set up the listed pins. All or + * any subset of the GPIO signals can be configured. Signals do + * not have to be listed in numerical order or be unique. If a + * signal number is listed multiple times, the last configuration * listed is used. \n Configuration terminates either when \b len * signals have been configured or if the next signal number index * in the array is equal to \b ALT_END_OF_GPIO_SIGNALS (-1). - * + * * \param len - * Length of array to configure. - * + * Length of array to configure. + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array, uint32_t len); /******************************************************************************/ /*! - * Returns a list of the pin signal indices and the associated configuration + * Returns a list of the pin signal indices and the associated configuration * settings (data direction, interrupt type, polarity, and debounce) of that * list of signals. - * + * * \param config_array * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration * records. Only the signal indices in the first field of each * configuration record need be filled in. This function will * fill in all the other fields of the configuration record, * returning all configuration parameters in the array. - * Signals do not have to be listed in numerical order or be - * unique. If a signal number is listed multiple times, the + * Signals do not have to be listed in numerical order or be + * unique. If a signal number is listed multiple times, the * configuration record will contain multiple entries for * that signal. \n Configuration reading terminates either when * \b len signal configurations have been read or if the next * signal number index in the array is equal to * \b ALT_END_OF_GPIO_SIGNALS (-1). * \param len - * Length of configuration array to read and return. - * - * + * Length of configuration array to read and return. + * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len); @@ -1140,30 +1158,30 @@ ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array * alt_gpio_group_config_get() is this version follows a separate list of * signal indices instead of having the signal list provided in the first * field of the configuration records in the array. - * + * * \param pinid_array * Pointer to a list of signal index numbers. These indices * are copied to the first field of each configuration record * in the returned array. * \param config_array * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration - * records. This function will fill in the fields of the - * configuration record, returning all configuration parameters - * in the array. Signals do not have to be listed in numerical - * order or be unique. If a signal number is listed multiple - * times, the configuration record array will contain multiple + * records. This function will fill in the fields of the + * configuration record, returning all configuration parameters + * in the array. Signals do not have to be listed in numerical + * order or be unique. If a signal number is listed multiple + * times, the configuration record array will contain multiple * identical entries for that signal. \n Configuration reading * terminates either when \b len signal configurations have been * read or if the next signal number index in the array is equal * to \b ALT_END_OF_GPIO_SIGNALS (-1). * \param len - * Length of configuration array to read. - * - * + * Length of configuration array to read. + * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - * + * */ ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array, ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len); @@ -1218,10 +1236,10 @@ ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num); /******************************************************************************/ /*! - * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and - * signal mask. If passed a bitmask composed of more than one signal, the + * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and + * signal mask. If passed a bitmask composed of more than one signal, the * signal number of the lowest bit in the bitmask presented is returned. - * + * */ ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid, uint32_t bitmask); diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h index 57f0f0d..7596d50 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h @@ -36,17 +36,21 @@ * ***********************************************************************/ -/* This is the major revision of the Altera ACDS Release */ +/* This is the major revision of the Altera ACDS Release */ #define ALTERA_ACDS_MAJOR_REV 13 -/* This is the minor revision of the Altera ACDS Release */ -#define ALTERA_ACDS_MINOR_REV 0 +/* This is the minor revision of the Altera ACDS Release */ +#define ALTERA_ACDS_MINOR_REV 1 -/* This is an internal HwLibs revision control code. */ -/* End-users should NOT depend upon the value of this field */ +/* This is an internal HwLibs revision/feature control code. */ +/* End-users should NOT depend upon the value of this field */ #define ALTERA_HWLIBS_REV 0 /* This is a text string containing the current release and service pack IDs */ -#define ALTERA_ACDS_REV_STR "13.0SP1" +#define ALTERA_ACDS_REV_STR "13.1" + +/* This is a text string containing the current SoC EDS ID */ +#define ALTERA_SOCEDS_REV_STR "Altera SoC Embedded Design Suite v13.1" + #endif /* __ALT_HWLIBS_VER_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h index db1e6dd..004fd31 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h @@ -343,6 +343,8 @@ typedef enum ALT_INT_INTERRUPT_e ALT_INT_INTERRUPT_SPI3_IRQ = 189, /*!< * Interrupts sourced from the SPI Controllers 0 - 3. + * SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1. + * SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1. * * All interrupts in this group are level triggered. */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h index 7b0da34..d719e3f 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h @@ -239,6 +239,48 @@ ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay, bool fpga_handshake, bool etr_stall); +#if 0 +/*! \addtogroup RST_MGR_MPU + * + * This functional group provides reset control for the Cortex-A9 MPU module. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_PERIPH + * + * This functional group provides inidividual reset control for the HPS + * peripheral modules. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_BRG + * + * This functional group provides inidividual reset control for the bridge + * interfaces between the HPS and FPGA. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_MISC + * + * This functional group provides inidividual reset control for miscellaneous + * HPS modules. + * + * @{ + */ + +/*! @} */ + +#endif + /*! @} */ /*! @} */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h index 7a3bbfd..aba7e87 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h @@ -91,7 +91,6 @@ typedef int32_t ALT_STATUS_CODE; /*! The buffer does not contain enough free space for the operation. */ #define ALT_E_BUF_OVF (-20) - /*! * Indicates a FALSE condition. */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h new file mode 100644 index 0000000..3a6bf0f --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h @@ -0,0 +1,3569 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_ACPIDMAP */ + +#ifndef __ALTERA_ALT_ACPIDMAP_H__ +#define __ALTERA_ALT_ACPIDMAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : ACP ID Mapper Registers - ALT_ACPIDMAP + * ACP ID Mapper Registers + * + * Registers in the ACP ID Mapper module + * + */ +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 2 - vid2rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | ARUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : ARUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD. + */ +struct ALT_ACPIDMAP_VID2RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_s ALT_ACPIDMAP_VID2RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_OFST 0x0 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 2 - vid2wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | AWUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : AWUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR. + */ +struct ALT_ACPIDMAP_VID2WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_s ALT_ACPIDMAP_VID2WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_OFST 0x4 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 3 - vid3rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD. + */ +struct ALT_ACPIDMAP_VID3RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_s ALT_ACPIDMAP_VID3RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_OFST 0x8 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 3 - vid3wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR. + */ +struct ALT_ACPIDMAP_VID3WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_s ALT_ACPIDMAP_VID3WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_OFST 0xc + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 4 - vid4rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD. + */ +struct ALT_ACPIDMAP_VID4RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_s ALT_ACPIDMAP_VID4RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_OFST 0x10 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 4 - vid4wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR. + */ +struct ALT_ACPIDMAP_VID4WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_s ALT_ACPIDMAP_VID4WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_OFST 0x14 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 5 - vid5rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD. + */ +struct ALT_ACPIDMAP_VID5RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_s ALT_ACPIDMAP_VID5RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_OFST 0x18 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 5 - vid5wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR. + */ +struct ALT_ACPIDMAP_VID5WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_s ALT_ACPIDMAP_VID5WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_OFST 0x1c + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 6 - vid6rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD. + */ +struct ALT_ACPIDMAP_VID6RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_s ALT_ACPIDMAP_VID6RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_OFST 0x20 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 6 - vid6wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR. + */ +struct ALT_ACPIDMAP_VID6WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_s ALT_ACPIDMAP_VID6WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_OFST 0x24 + +/* + * Register : Read AXI Master Mapping Register for Dynamic Virtual ID Remap - dynrd + * + * The Read AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD. + */ +struct ALT_ACPIDMAP_DYNRD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_s ALT_ACPIDMAP_DYNRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_OFST 0x28 + +/* + * Register : Write AXI Master Mapping Register for Dynamic Virtual ID Remap - dynwr + * + * The Write AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR. + */ +struct ALT_ACPIDMAP_DYNWR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_s ALT_ACPIDMAP_DYNWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_OFST 0x2c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | ARUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : ARUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD_S. + */ +struct ALT_ACPIDMAP_VID2RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_S_s ALT_ACPIDMAP_VID2RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_S_OFST 0x30 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | AWUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : AWUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR_S. + */ +struct ALT_ACPIDMAP_VID2WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_S_s ALT_ACPIDMAP_VID2WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_S_OFST 0x34 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD_S. + */ +struct ALT_ACPIDMAP_VID3RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_S_s ALT_ACPIDMAP_VID3RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_S_OFST 0x38 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR_S. + */ +struct ALT_ACPIDMAP_VID3WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_S_s ALT_ACPIDMAP_VID3WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_S_OFST 0x3c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD_S. + */ +struct ALT_ACPIDMAP_VID4RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_S_s ALT_ACPIDMAP_VID4RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_S_OFST 0x40 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR_S. + */ +struct ALT_ACPIDMAP_VID4WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_S_s ALT_ACPIDMAP_VID4WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_S_OFST 0x44 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD_S. + */ +struct ALT_ACPIDMAP_VID5RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_S_s ALT_ACPIDMAP_VID5RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_S_OFST 0x48 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR_S. + */ +struct ALT_ACPIDMAP_VID5WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_S_s ALT_ACPIDMAP_VID5WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_S_OFST 0x4c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD_S. + */ +struct ALT_ACPIDMAP_VID6RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_S_s ALT_ACPIDMAP_VID6RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_S_OFST 0x50 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR_S. + */ +struct ALT_ACPIDMAP_VID6WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_S_s ALT_ACPIDMAP_VID6WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_S_OFST 0x54 + +/* + * Register : Read AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynrd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD_S. + */ +struct ALT_ACPIDMAP_DYNRD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_S_s ALT_ACPIDMAP_DYNRD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_S_OFST 0x58 + +/* + * Register : Write AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynwr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR_S. + */ +struct ALT_ACPIDMAP_DYNWR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_S_s ALT_ACPIDMAP_DYNWR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_S_OFST 0x5c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_ACPIDMAP. + */ +struct ALT_ACPIDMAP_s +{ + volatile ALT_ACPIDMAP_VID2RD_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile ALT_ACPIDMAP_VID2WR_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile ALT_ACPIDMAP_VID3RD_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile ALT_ACPIDMAP_VID3WR_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile ALT_ACPIDMAP_VID4RD_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile ALT_ACPIDMAP_VID4WR_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile ALT_ACPIDMAP_VID5RD_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile ALT_ACPIDMAP_VID5WR_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile ALT_ACPIDMAP_VID6RD_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile ALT_ACPIDMAP_VID6WR_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile ALT_ACPIDMAP_DYNRD_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile ALT_ACPIDMAP_DYNWR_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile ALT_ACPIDMAP_VID2RD_S_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile ALT_ACPIDMAP_VID2WR_S_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile ALT_ACPIDMAP_VID3RD_S_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile ALT_ACPIDMAP_VID3WR_S_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile ALT_ACPIDMAP_VID4RD_S_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile ALT_ACPIDMAP_VID4WR_S_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile ALT_ACPIDMAP_VID5RD_S_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile ALT_ACPIDMAP_VID5WR_S_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile ALT_ACPIDMAP_VID6RD_S_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile ALT_ACPIDMAP_VID6WR_S_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile ALT_ACPIDMAP_DYNRD_S_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile ALT_ACPIDMAP_DYNWR_S_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_s ALT_ACPIDMAP_t; +/* The struct declaration for the raw register contents of register group ALT_ACPIDMAP. */ +struct ALT_ACPIDMAP_raw_s +{ + volatile uint32_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile uint32_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile uint32_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile uint32_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile uint32_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile uint32_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile uint32_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile uint32_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile uint32_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile uint32_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile uint32_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile uint32_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile uint32_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile uint32_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile uint32_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile uint32_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile uint32_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile uint32_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile uint32_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile uint32_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile uint32_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile uint32_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile uint32_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile uint32_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_raw_s ALT_ACPIDMAP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_ACPIDMAP_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h index b0375e5..f6090cd 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h @@ -1,39 +1,50 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + /*! \file Altera - ALT_SOCAL */ #ifndef __ALTERA_SOCAL_H__ #define __ALTERA_SOCAL_H__ -#include +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#include +#include +#include +#else /* __cplusplus */ +#include +#include +#include +#endif /* __cplusplus */ +#endif /* __ASSEMBLY__ */ #ifdef __cplusplus extern "C" @@ -61,7 +72,6 @@ extern "C" #define ALT_CAST(type, ptr) ((type) (ptr)) #endif /* __ASSEMBLY__ */ - /*! * \addtogroup ALT_SOCAL_UTIL_RW_FUNC SoCAL Memory Read/Write Utilities * @@ -239,117 +249,8 @@ extern "C" */ #define alt_replbits_dword(dest, msk, src) (alt_write_dword(dest,(alt_read_dword(dest) & ~(msk)) | ((src) & (msk)))) - - /*! @} */ -/*! - * \addtogroup ALT_SOCAL_TYPE_IND_FUNC SoCAL Indirect (pointer-based) Utilities - * - * This section implements two other useful forms of the alt_write_*() macros above that - * are preferable to use in some situations. These use an intermediate pointer (defined - * in the containing compile unit) to move data in an indirect manner. These compile to very - * tight ARM code, equivalent to the above versions. - * - * @{ - */ - -/*! Write the 8 bit byte to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to byte data - * \param src - 8 bit data value to write to memory - */ -#define alt_indwrite_byte(dest, tmptr, src) {(tmptr)=ALT_CAST(uint8_t*,(dest));(*ALT_CAST(volatile uint8_t*,(tmptr))=(src));} - -/*! Write the 8 bit byte to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to byte data - * \param src - Read destination pointer address - */ -#define alt_indread_byte(dest, tmptr, src) {(tmptr)=ALT_CAST(uint8_t*,(src));(*ALT_CAST(volatile uint8_t*,(dest))=*(tmptr));} - -/*! Write the 16 bit halfword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to halfword data - * \param src - 16 bit data value to write to memory - */ -#define alt_indwrite_hword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint16_t*,(dest));(*ALT_CAST(volatile uint16_t*,(tmptr))=(src));} - -/*! Write the 16 bit halfword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to halfword data - * \param src - Read destination pointer address - */ -#define alt_indread_hword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint16_t*,(src));(*ALT_CAST(volatile uint16_t*,(dest))=*(tmptr));} - -/*! Write the 32 bit word to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to word data - * \param src - 32 bit data value to write to memory - */ -#define alt_indwrite_word(dest, tmptr, src) {(tmptr)=ALT_CAST(uint32_t*,(dest));(*ALT_CAST(volatile uint32_t*,(tmptr))=(src));} - -/*! Write the 32 bit word to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to word data - * \param src - Read destination pointer address - */ -#define alt_indread_word(dest, tmptr, src) {(tmptr)=ALT_CAST(uint32_t*,(src));(*ALT_CAST(volatile uint32_t*,(dest))=*(tmptr));} - -/*! Write the 64 bit dword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to double-word data - * \param src - 64 bit data value to write to memory - */ -#define alt_indwrite_dword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint64_t*,(dest));(*ALT_CAST(volatile uint64_t*,(tmptr))=(src));} - -/*! Write the 64 bit dword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to double-word data - * \param src - Read destination pointer address - */ -#define alt_indread_dword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint64_t*,(src));(*ALT_CAST(volatile uint64_t*,(dest))=*(tmptr));} - - -/*! @} */ - -/*! - * \addtogroup ALT_SOCAL_CMPL_ASRT_FUNC SoCAL Compile Assert Utilities - * - * This section implements an assert-type functionality in the compiler rather than in the - * debug run-time code. Additional macros can be built on the basic structure and defined - * to test various conditions and throw a compile-time error if necessary. - * - * @{ - */ - -/*! alt_cat_compile_assert_text() concatenates text. - * \param txta - The first text fragment to be joined - * \param txtb - The second text fragment to be joined - */ -#define alt_cat_compile_assert_text(txta, txtb) txta##txtb - -/*! alt_form_compile_assert_line() is the basis of other functions that check various - * conditions and possibly throw a compile-time error in response, giving an - * assert equivalent that operates at compile time rather than at run-time. - * \param test - Any valid boolean expression - * \param file - The filename where this expression is located (ASCII string) - * \param line - The line number where this expression is located - */ -#define alt_form_compile_assert_line(test, file, line) \ -typedef char alt_cat_compile_assert_text(assertion_at_##file##_line_, line)[2*!!(test)-1] - -/*! alt_check_struct_size() throws a compile-time error if the structure size (a) is - * larger than the size of the reference (b). \n - * alt_check_struct_size() works with groups of bitfields up to much larger - * structure sizes. - * \param a - Structure to be evaluated - * \param b - Reference size - */ -#define alt_check_struct_size(a, b) RTEMS_STATIC_ASSERT((sizeof(a) <= sizeof(b)), Invalid_stuct_size) - - -/*! @} */ /*! @} */ #ifdef __cplusplus diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c index 43d7576..93b7f88 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c @@ -1,45 +1,49 @@ - /****************************************************************************** -* -* alt_address_space.c - API for the Altera SoC FPGA address space. -* -******************************************************************************/ + * + * alt_address_space.c - API for the Altera SoC FPGA address space. + * + ******************************************************************************/ /****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ #include #include "alt_address_space.h" #include "socal/alt_l3.h" #include "socal/socal.h" +#include "socal/alt_acpidmap.h" +#include "hwlib.h" + +#define ALT_ACP_ID_MAX_INPUT_ID 7 +#define ALT_ACP_ID_MAX_OUTPUT_ID 4096 /******************************************************************************/ ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, @@ -154,7 +158,7 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, { // Address filtering start and end values must be 1 MB aligned. if ( (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK) - || (addr_filt_end & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK) ) + || (addr_filt_end & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK) ) { return ALT_E_ARG_RANGE; } @@ -181,4 +185,325 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, } /******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser) +{ + if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + alt_write_word(ALT_ACPIDMAP_VID2RD_ADDR, + ALT_ACPIDMAP_VID2RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID2RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID2RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID2RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + alt_write_word(ALT_ACPIDMAP_VID3RD_ADDR, + ALT_ACPIDMAP_VID3RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID3RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID3RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID3RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + alt_write_word(ALT_ACPIDMAP_VID4RD_ADDR, + ALT_ACPIDMAP_VID4RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID4RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID4RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID4RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + alt_write_word(ALT_ACPIDMAP_VID5RD_ADDR, + ALT_ACPIDMAP_VID5RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID5RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID5RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID5RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + alt_write_word(ALT_ACPIDMAP_VID6RD_ADDR, + ALT_ACPIDMAP_VID6RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID6RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID6RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID6RD_FORCE_SET(1UL)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser) +{ + if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + alt_write_word(ALT_ACPIDMAP_VID2WR_ADDR, + ALT_ACPIDMAP_VID2WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID2WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID2WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID2WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + alt_write_word(ALT_ACPIDMAP_VID3WR_ADDR, + ALT_ACPIDMAP_VID3WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID3WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID3WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID3WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + alt_write_word(ALT_ACPIDMAP_VID4WR_ADDR, + ALT_ACPIDMAP_VID4WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID4WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID4WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID4WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + alt_write_word(ALT_ACPIDMAP_VID5WR_ADDR, + ALT_ACPIDMAP_VID5WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID5WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID5WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID5WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + alt_write_word(ALT_ACPIDMAP_VID6WR_ADDR, + ALT_ACPIDMAP_VID6WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID6WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID6WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID6WR_FORCE_SET(1UL) + ); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + uint32_t aruser, page; + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + aruser = ALT_ACPIDMAP_VID2RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR)); + page = ALT_ACPIDMAP_VID2RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + aruser = ALT_ACPIDMAP_VID3RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR)); + page = ALT_ACPIDMAP_VID3RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + aruser = ALT_ACPIDMAP_VID4RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR)); + page = ALT_ACPIDMAP_VID4RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + aruser = ALT_ACPIDMAP_VID5RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR)); + page = ALT_ACPIDMAP_VID5RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + aruser = ALT_ACPIDMAP_VID6RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR)); + page = ALT_ACPIDMAP_VID6RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR, + ALT_ACPIDMAP_DYNRD_PAGE_SET(page) + | ALT_ACPIDMAP_DYNRD_USER_SET(aruser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + uint32_t awuser, page; + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR)); + page = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR)); + page = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR)); + page = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR)); + page = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR)); + page = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR, + ALT_ACPIDMAP_DYNWR_PAGE_SET(page) + | ALT_ACPIDMAP_DYNWR_USER_SET(awuser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser) +{ + alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR, + ALT_ACPIDMAP_DYNRD_PAGE_SET(page) + | ALT_ACPIDMAP_DYNRD_USER_SET(aruser)); + return ALT_E_SUCCESS; +} + /******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser) +{ + alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR, + ALT_ACPIDMAP_DYNWR_PAGE_SET(page) + | ALT_ACPIDMAP_DYNWR_USER_SET(awuser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, + bool * fixed, + uint32_t * input_id, + ALT_ACP_ID_MAP_PAGE_t * page, + uint32_t * aruser) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + *aruser = ALT_ACPIDMAP_VID2RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID2RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID2RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + *aruser = ALT_ACPIDMAP_VID3RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID3RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID3RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + *aruser = ALT_ACPIDMAP_VID4RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID4RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID4RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + *aruser = ALT_ACPIDMAP_VID5RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID5RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID5RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + *aruser = ALT_ACPIDMAP_VID6RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID6RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID6RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_7: + *aruser = ALT_ACPIDMAP_DYNRD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNRD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, + bool * fixed, + uint32_t * input_id, + ALT_ACP_ID_MAP_PAGE_t * page, + uint32_t * awuser) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + *awuser = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + *awuser = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + *awuser = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + *awuser = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + *awuser = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_7: + *awuser = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c index c731ad3..1291243 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c @@ -1,46 +1,44 @@ /****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - - -#include -#include -#include -#include -#include - -#include "socal/hps.h" -#include "socal/socal.h" -#include "socal/alt_sysmgr.h" -#include "hwlib.h" -#include "alt_clock_manager.h" -#include "alt_mpu_registers.h" + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include +#include +#include +#include + +#include "socal/hps.h" +#include "socal/socal.h" +#include "socal/alt_sysmgr.h" +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "alt_mpu_registers.h" #define UINT12_MAX (4096) @@ -77,10 +75,13 @@ typedef struct ALT_EXT_CLK_PARAMBLOK_s /* contains the current activity state of the clock, 1=active, 0=inactive. */ /* Values taken from Section 2.3 and Section 2.7.1 of the HHP HPS-Clocking */ /* NPP specification. */ -static ALT_EXT_CLK_PARAMBLOK_t alt_ext_clk_paramblok = {{25000000, 10000000, 50000000, 0, 1}, - {25000000, 10000000, 50000000, 0, 1}, - {0, 10000000, 50000000, 0, 1}, - {0, 10000000, 50000000, 0, 1}}; +static ALT_EXT_CLK_PARAMBLOK_t alt_ext_clk_paramblok = +{ + { 25000000, 10000000, 50000000, 0, 1 }, + { 25000000, 10000000, 50000000, 0, 1 }, + { 0, 10000000, 50000000, 0, 1 }, + { 0, 10000000, 50000000, 0, 1 } +}; /* PLL frequency limits */ @@ -104,12 +105,15 @@ typedef struct ALT_PLL_CLK_PARAMBLOK_s #define ALT_ORIGINAL_GUARDBAND_VAL 20 #define ALT_GUARDBAND_LIMIT 20 -static ALT_PLL_CLK_PARAMBLOK_t alt_pll_clk_paramblok = {{0, 320000000, 1200000000, ALT_ORIGINAL_GUARDBAND_VAL, 0}, - {0, 320000000, 900000000, ALT_ORIGINAL_GUARDBAND_VAL, 0}, - {0, 320000000, 800000000, ALT_ORIGINAL_GUARDBAND_VAL, 0}, - {0, 320000000, 1600000000, ALT_ORIGINAL_GUARDBAND_VAL, 1}, - {0, 320000000, 1250000000, ALT_ORIGINAL_GUARDBAND_VAL, 1}, - {0, 320000000, 1066000000, ALT_ORIGINAL_GUARDBAND_VAL, 1}}; +static ALT_PLL_CLK_PARAMBLOK_t alt_pll_clk_paramblok = +{ + { 0, 320000000, 1200000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 900000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 800000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 1600000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 }, + { 0, 320000000, 1250000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 }, + { 0, 320000000, 1066000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 } +}; /* PLL counter frequency limits */ @@ -133,25 +137,69 @@ typedef struct ALT_PLL_CNTR_FREQMAX_s alt_freq_t SDRAMPLL_C5; // SDRAM PLL Counter 5 parameter block } ALT_PLL_CNTR_FREQMAX_t; +// +// The following pll max frequency array statically defined must be recalculated each time +// when powering up, by calling alt_clk_clkmgr_init() +// +// for 14.1 uboot preloader, the following values are calculated dynamically. +// +// Arrial 5 +// alt_pll_cntr_maxfreq.MainPLL_C0 = 1050000000 +// alt_pll_cntr_maxfreq.MainPLL_C1 = 350000000 +// alt_pll_cntr_maxfreq.MainPLL_C2 = 262500000 +// alt_pll_cntr_maxfreq.MainPLL_C3 = 350000000 +// alt_pll_cntr_maxfreq.MainPLL_C4 = 2050781 +// alt_pll_cntr_maxfreq.MainPLL_C5 = 116666666 +// alt_pll_cntr_maxfreq.PeriphPLL_C0 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C1 = 250000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C2 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C3 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C4 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C5 = 1953125 +// alt_pll_cntr_maxfreq.SDRAMPLL_C0 = 533333333 +// alt_pll_cntr_maxfreq.SDRAMPLL_C1 = 1066666666 +// alt_pll_cntr_maxfreq.SDRAMPLL_C2 = 533333333 +// alt_pll_cntr_maxfreq.SDRAMPLL_C5 = 177777777 + +// Cyclone V +// alt_pll_cntr_maxfreq.MainPLL_C0 = 925000000 +// alt_pll_cntr_maxfreq.MainPLL_C1 = 370000000 +// alt_pll_cntr_maxfreq.MainPLL_C2 = 462500000 +// alt_pll_cntr_maxfreq.MainPLL_C3 = 370000000 +// alt_pll_cntr_maxfreq.MainPLL_C4 = 3613281 +// alt_pll_cntr_maxfreq.MainPLL_C5 = 123333333 +// alt_pll_cntr_maxfreq.PeriphPLL_C0 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C1 = 250000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C2 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C3 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C4 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C5 = 1953125 +// alt_pll_cntr_maxfreq.SDRAMPLL_C0 = 400000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C1 = 800000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C2 = 400000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C5 = 133333333 /* Initializes the PLL Counter output maximum frequency block */ -static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = {800000000, /* Main PLL Outputs */ - 400000000, - 400000000, - 432000000, - 250000000, - 125000000, - 250000000, /* Peripheral PLL Outputs */ - 250000000, - 432000000, - 250000000, - 200000000, - 100000000, /* SDRAM PLL Outputs */ - 533000000, - 1066000000, - 533000000, - 200000000 }; +static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = +{ + 800000000, /* Main PLL Outputs */ + 400000000, + 400000000, + 432000000, + 250000000, + 125000000, + 250000000, /* Peripheral PLL Outputs */ + 250000000, + 432000000, + 250000000, + 200000000, + 100000000, /* SDRAM PLL Outputs */ + 533000000, + 1066000000, + 533000000, + 200000000 +}; @@ -181,6 +229,18 @@ static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = {800000000, /* Main PLL & ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK) +// Undocumented register which determines clock dividers for main PLL C0, C1, and C2. These should be considered RO. +#define ALT_CLKMGR_ALTERA_OFST 0xe0 +#define ALT_CLKMGR_ALTERA_MPUCLK_OFST 0x0 +#define ALT_CLKMGR_ALTERA_MAINCLK_OFST 0x4 +#define ALT_CLKMGR_ALTERA_DBGATCLK_OFST 0x8 +#define ALT_CLKMGR_ALTERA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_ALTERA_OFST)) +#define ALT_CLKMGR_ALTERA_MPUCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_MPUCLK_OFST)) +#define ALT_CLKMGR_ALTERA_MAINCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_MAINCLK_OFST)) +#define ALT_CLKMGR_ALTERA_DBGATCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_DBGATCLK_OFST)) +#define ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +#define ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +#define ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Utility functions ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ @@ -199,7 +259,7 @@ static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = {800000000, /* Main PLL /* minimum osc1 clock cycle delay. */ /****************************************************************************************/ -static void inline alt_clk_mgr_wait(void* reg, uint32_t cnt) +inline static void alt_clk_mgr_wait(void* reg, uint32_t cnt) { for (; cnt ; cnt--) { @@ -207,7 +267,6 @@ static void inline alt_clk_mgr_wait(void* reg, uint32_t cnt) } } - /* Wait time constants */ /* These values came from Section 4.9.4 of the HHP HPS-Clocking NPP document */ #define ALT_SW_MANAGED_CLK_WAIT_CTRDIV 30 /* 30 or more MPU clock cycles */ @@ -224,8 +283,7 @@ static void inline alt_clk_mgr_wait(void* reg, uint32_t cnt) // how many loops to wait for the SDRAM clock to come around // to zero and allow for writing a new divisor ratio to it - -static ALT_STATUS_CODE alt_clk_plls_settle_wait(void) +ALT_STATUS_CODE alt_clk_plls_settle_wait(void) { int32_t i = ALT_BYPASS_TIMEOUT_CNT; bool nofini; @@ -238,26 +296,30 @@ static ALT_STATUS_CODE alt_clk_plls_settle_wait(void) return (i > 0) ? ALT_E_SUCCESS : ALT_E_ERROR; } - - -static ALT_STATUS_CODE alt_clk_pll_lock_wait(ALT_CLK_t pll, uint32_t cnt) +static ALT_STATUS_CODE alt_clk_pll_lock_wait(ALT_CLK_t pll, uint32_t timeout) { - ALT_STATUS_CODE ret = ALT_E_ERROR; - uint32_t temp; - uint32_t mask = 0; + uint32_t locked_mask = 0; + + if (pll == ALT_CLK_MAIN_PLL) { locked_mask = ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK; } + else if (pll == ALT_CLK_PERIPHERAL_PLL) { locked_mask = ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK; } + else if (pll == ALT_CLK_SDRAM_PLL) { locked_mask = ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK; } + else + { + return ALT_E_BAD_ARG; + } - if (pll == ALT_CLK_MAIN_PLL) { mask = ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK; } - else if (pll == ALT_CLK_PERIPHERAL_PLL) { mask = ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK; } - else if (pll == ALT_CLK_SDRAM_PLL) { mask = ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK; } - else { return ret; } do { - temp = alt_read_word(ALT_CLKMGR_INTER_ADDR); - } while (!(temp & mask) && --cnt); - if (cnt > 0) { ret = ALT_E_SUCCESS; } - return ret; -} + uint32_t int_status = alt_read_word(ALT_CLKMGR_INTER_ADDR); + if (int_status & locked_mask) + { + return ALT_E_SUCCESS; + } + + } while (timeout--); + return ALT_E_TMO; +} /* Useful utility macro for checking if two values */ /* are within a certain percentage of each other */ @@ -321,25 +383,23 @@ static void alt_clk_pllcounter_write(void* vcoaddr, void* stataddr, void* cntrad /* conditions. */ /****************************************************************************************/ - ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) +ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) { - ALT_STATUS_CODE ret; - - if (lock_stat_mask & (ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK - & ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK - & ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK - & ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK - & ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK - & ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK)) + if (lock_stat_mask & ( ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK + & ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK + & ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK) + ) { - ret = ALT_E_BAD_ARG; + return ALT_E_BAD_ARG; } else { alt_setbits_word(ALT_CLKMGR_INTER_ADDR, lock_stat_mask); - ret = ALT_E_SUCCESS; + return ALT_E_SUCCESS; } - return ret; } @@ -349,15 +409,15 @@ static void alt_clk_pllcounter_write(void* vcoaddr, void* stataddr, void* cntrad uint32_t alt_clk_lock_status_get(void) { - return alt_read_word(ALT_CLKMGR_INTER_ADDR) & (ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK - | ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK - | ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK - | ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK - | ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK - | ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK - | ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK - | ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK - | ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK ); + return alt_read_word(ALT_CLKMGR_INTER_ADDR) & ( ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK + | ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK ); } @@ -368,24 +428,24 @@ uint32_t alt_clk_lock_status_get(void) ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; if (pll == ALT_CLK_MAIN_PLL) { - ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK) + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_PERIPHERAL_PLL) { - ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK) + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_SDRAM_PLL) { - ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK) + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK) ? ALT_E_TRUE : ALT_E_FALSE; } - return ret; + return status; } @@ -396,7 +456,7 @@ ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll) ALT_STATUS_CODE alt_clk_safe_mode_clear(void) { - ALT_STATUS_CODE ret = ALT_E_ERROR; + ALT_STATUS_CODE status = ALT_E_ERROR; #if ALT_PREVENT_GLITCH_EXSAFE uint32_t temp; @@ -407,7 +467,7 @@ ALT_STATUS_CODE alt_clk_safe_mode_clear(void) alt_setbits_word(ALT_CLKMGR_CTL_ADDR, ALT_CLKMGR_CTL_SAFEMOD_SET_MSK); // clear safe mode bit - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); alt_replbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK, temp); @@ -416,10 +476,10 @@ ALT_STATUS_CODE alt_clk_safe_mode_clear(void) #else alt_setbits_word(ALT_CLKMGR_CTL_ADDR, ALT_CLKMGR_CTL_SAFEMOD_SET_MSK); // clear safe mode bit - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #endif - return ret; + return status; } @@ -463,12 +523,12 @@ bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain) ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + uint32_t temp; #if ALT_PREVENT_GLITCH_BYP - uint32_t temp1; - bool restore_0 = false; - bool restore_1 = false; + uint32_t temp1; + bool restore_0 = false; + bool restore_1 = false; #endif // this function should only be called after the selected PLL is locked @@ -479,20 +539,20 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) #if ALT_PREVENT_GLITCH_BYP // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) { - restore_0 = true; + restore_0 = true; } if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) { - restore_1 = true; + restore_1 = true; } temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } #endif @@ -507,7 +567,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) // remove bypass alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #if ALT_PREVENT_GLITCH_BYP if (restore_0 || restore_1) @@ -551,7 +611,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) // remove bypass - don't think that there's any need to touch the bypass clock source alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_PERPLL_SET_MSK); - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #if ALT_PREVENT_GLITCH_BYP if (restore_0 || restore_1) @@ -575,12 +635,15 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) // remove bypass - don't think that there's any need to touch the bypass clock source alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK); - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); } } - else { ret = ALT_E_ERROR; } + else + { + status = ALT_E_ERROR; + } - return ret; + return status; } @@ -590,12 +653,12 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + uint32_t temp; #ifdef ALT_PREVENT_GLITCH_BYP - uint32_t temp1; - bool restore_0 = false; - bool restore_1 = false; + uint32_t temp1; + bool restore_0 = false; + bool restore_1 = false; #endif if (pll == ALT_CLK_MAIN_PLL) @@ -605,59 +668,61 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) #ifdef ALT_PREVENT_GLITCH_BYP // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) { - restore_0 = true; + restore_0 = true; } if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) { - restore_1 = true; + restore_1 = true; } temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } alt_setbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); // no input mux select on main PLL - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); // wait before reenabling the L4MP and L4SP clocks if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } #else alt_setbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); // no input mux select on main PLL - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #endif - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_BAD_ARG; } - else { ret = ALT_E_BAD_ARG; } } - else if (pll == ALT_CLK_PERIPHERAL_PLL) { #ifdef ALT_PREVENT_GLITCH_BYP // if L4MP or L4SP source is set to Peripheral PLL C1, gate it off before changing // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK)) { - restore_0 = true; + restore_0 = true; } if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK)) { - restore_1 = true; + restore_1 = true; } temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } temp = alt_read_word(ALT_CLKMGR_BYPASS_ADDR) & @@ -678,7 +743,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK : ALT_CLKMGR_BYPASS_PERPLL_SET_MSK; // set bypass bit and optionally the source select bit #endif - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; } else if (pll == ALT_CLK_SDRAM_PLL) @@ -689,9 +754,9 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK : ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK; // set bypass bit and optionally the source select bit alt_write_word(ALT_CLKMGR_BYPASS_ADDR, temp); - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; } - return ret; + return status; } @@ -706,27 +771,27 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; if (pll == ALT_CLK_MAIN_PLL) { - ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) || ALT_CLKMGR_BYPASS_MAINPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_PERIPHERAL_PLL) { - ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) || ALT_CLKMGR_BYPASS_PERPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_SDRAM_PLL) { - ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) || ALT_CLKMGR_BYPASS_SDRPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) ? ALT_E_TRUE : ALT_E_FALSE; } - return ret; + return status; } @@ -734,9 +799,9 @@ ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll) /* alt_clk_pll_source_get() returns the current input of the specified PLL. */ /****************************************************************************************/ -static ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) +ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) { - ALT_CLK_t ret = ALT_CLK_UNKNOWN; + ALT_CLK_t ret = ALT_CLK_UNKNOWN; uint32_t temp; @@ -777,962 +842,920 @@ static ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) { ret = ALT_CLK_F2H_SDRAM_REF; } - } + } return ret; } - -/****************************************************************************************/ -/* alt_clk_clock_disable() disables the specified clock. Once the clock is disabled, */ -/* its clock signal does not propagate to its clocked elements. */ -/****************************************************************************************/ - +// +// alt_clk_clock_disable() disables the specified clock. Once the clock is disabled, +// its clock signal does not propagate to its clocked elements. +// ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_SUCCESS; switch (clk) { - /* For PLLs, put them in bypass mode */ - case (ALT_CLK_MAIN_PLL): - case (ALT_CLK_PERIPHERAL_PLL): - case (ALT_CLK_SDRAM_PLL): - ret = alt_clk_pll_bypass_enable(clk, false); - break; - - /* Clocks that originate at the Main PLL */ - case (ALT_CLK_L4_MAIN): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L3_MP): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_MP): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_SP): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_AT): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TRACE): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TIMER): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CFG): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER0): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - /* Clocks that originate at the Peripheral PLL */ - case (ALT_CLK_EMAC0): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_EMAC1): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_USB_MP): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SPI_M): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN0): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN1): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_GPIO_DB): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER1): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SDMMC): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND_X): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - // gate nand_clk off before nand_x_clk - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - ret = ALT_E_SUCCESS; + // For PLLs, put them in bypass mode. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = alt_clk_pll_bypass_enable(clk, false); break; - case (ALT_CLK_QSPI): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - /* Clocks that originate at the SDRAM PLL */ - case (ALT_CLK_DDR_DQS): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DDR_2X_DQS): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - case (ALT_CLK_DDR_DQ): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); + break; + case ALT_CLK_L3_MP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); + break; + case ALT_CLK_L4_MP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + break; + case ALT_CLK_L4_SP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + break; + case ALT_CLK_DBG_AT: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); + break; + case ALT_CLK_DBG: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); + break; + case ALT_CLK_DBG_TRACE: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); + break; + case ALT_CLK_DBG_TIMER: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); + break; + case ALT_CLK_CFG: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER0: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); + break; - case (ALT_CLK_H2F_USER2): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); + break; + case ALT_CLK_EMAC1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); + break; + case ALT_CLK_USB_MP: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); + break; + case ALT_CLK_SPI_M: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); + break; + case ALT_CLK_CAN0: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); + break; + case ALT_CLK_CAN1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); + break; + case ALT_CLK_GPIO_DB: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); + break; + case ALT_CLK_SDMMC: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + break; + case ALT_CLK_NAND_X: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_clk off before nand_x_clk. + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + break; + case ALT_CLK_NAND: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + break; + case ALT_CLK_QSPI: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + break; - default: - break; + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_2X_DQS: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_DQ: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER2: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); + break; + default: + status = ALT_E_BAD_ARG; + break; } - return ret; -} - -/****************************************************************************************/ -/* alt_clk_clock_enable() enables the specified clock. Once the clock is enabled, its */ -/* clock signal propagates to its elements. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_clock_enable() enables the specified clock. Once the clock is enabled, its +// clock signal propagates to its elements. +// ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_SUCCESS; switch (clk) { - /* For PLLs, take them out of bypass mode */ - case (ALT_CLK_MAIN_PLL): - case (ALT_CLK_PERIPHERAL_PLL): - case (ALT_CLK_SDRAM_PLL): - ret = alt_clk_pll_bypass_disable(clk); - break; - - - /* Clocks that originate at the Main PLL */ - case (ALT_CLK_L4_MAIN): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L3_MP): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_MP): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_SP): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_AT): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TRACE): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TIMER): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CFG): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER0): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - /* Clocks that originate at the Peripheral PLL */ - case (ALT_CLK_EMAC0): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_EMAC1): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_USB_MP): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SPI_M): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN0): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN1): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_GPIO_DB): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER1): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SDMMC): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND_X): - // implementation detail - should ALK_CLK_NAND be gated off here before enabling ALT_CLK_NAND_X? - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - // implementation detail - should this wait be enforced here? - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND): - // enabling ALT_CLK_NAND always implies enabling ALT_CLK_NAND_X first - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - // gate nand_x_clk on at least 8 MCU clocks before nand_clk - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_QSPI): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // For PLLs, take them out of bypass mode. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = alt_clk_pll_bypass_disable(clk); + break; - /* Clocks that originate at the SDRAM PLL */ - case (ALT_CLK_DDR_DQS): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); + break; + case ALT_CLK_L3_MP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); + break; + case ALT_CLK_L4_MP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + break; + case ALT_CLK_L4_SP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + break; + case ALT_CLK_DBG_AT: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); + break; + case ALT_CLK_DBG: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); + break; + case ALT_CLK_DBG_TRACE: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); + break; + case ALT_CLK_DBG_TIMER: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); + break; + case ALT_CLK_CFG: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER0: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); + break; - case (ALT_CLK_DDR_2X_DQS): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); + break; + case ALT_CLK_EMAC1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); + break; + case ALT_CLK_USB_MP: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); + break; + case ALT_CLK_SPI_M: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); + break; + case ALT_CLK_CAN0: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); + break; + case ALT_CLK_CAN1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); + break; + case ALT_CLK_GPIO_DB: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); + break; + case ALT_CLK_SDMMC: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + break; + case ALT_CLK_NAND_X: + // implementation detail - should ALK_CLK_NAND be gated off here before enabling ALT_CLK_NAND_X? + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + // implementation detail - should this wait be enforced here? + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + break; + case ALT_CLK_NAND: + // enabling ALT_CLK_NAND always implies enabling ALT_CLK_NAND_X first + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_x_clk on at least 8 MCU clocks before nand_clk + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + break; + case ALT_CLK_QSPI: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + break; - case (ALT_CLK_DDR_DQ): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_2X_DQS: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_DQ: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER2: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); + break; - case (ALT_CLK_H2F_USER2): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + default: + status = ALT_E_BAD_ARG; + break; + } - default: break; - } - return ret; + return status; } - -/****************************************************************************************/ -/* alt_clk_is_enabled() returns whether the specified clock is enabled or not. */ -/****************************************************************************************/ - +// +// alt_clk_is_enabled() returns whether the specified clock is enabled or not. +// ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - - switch (clk) // this should be more than enough cases to cause - { // the compiler to use a jump table implementation + ALT_STATUS_CODE status = ALT_E_BAD_ARG; - /* For PLLs, this function checks if the PLL is bypassed or not */ - case (ALT_CLK_MAIN_PLL): - case (ALT_CLK_PERIPHERAL_PLL): - case (ALT_CLK_SDRAM_PLL): - ret = (alt_clk_pll_is_bypassed(clk) != ALT_E_TRUE); - break; + switch (clk) + { + // For PLLs, this function checks if the PLL is bypassed or not. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = (alt_clk_pll_is_bypassed(clk) != ALT_E_TRUE); + break; - /* These clocks are not gated, so must return a ALT_E_BAD_ARG type error */ - case (ALT_CLK_MAIN_PLL_C0): - case (ALT_CLK_MAIN_PLL_C1): - case (ALT_CLK_MAIN_PLL_C2): - case (ALT_CLK_MAIN_PLL_C3): - case (ALT_CLK_MAIN_PLL_C4): - case (ALT_CLK_MAIN_PLL_C5): - case (ALT_CLK_MPU): - case (ALT_CLK_MPU_L2_RAM): - case (ALT_CLK_MPU_PERIPH): - case (ALT_CLK_L3_MAIN): - case (ALT_CLK_L3_SP): - case (ALT_CLK_DBG_BASE): - case (ALT_CLK_MAIN_QSPI): - case (ALT_CLK_MAIN_NAND_SDMMC): - case (ALT_CLK_PERIPHERAL_PLL_C0): - case (ALT_CLK_PERIPHERAL_PLL_C1): - case (ALT_CLK_PERIPHERAL_PLL_C2): - case (ALT_CLK_PERIPHERAL_PLL_C3): - case (ALT_CLK_PERIPHERAL_PLL_C4): - case (ALT_CLK_PERIPHERAL_PLL_C5): - case (ALT_CLK_SDRAM_PLL_C0): - case (ALT_CLK_SDRAM_PLL_C1): - case (ALT_CLK_SDRAM_PLL_C2): - case (ALT_CLK_SDRAM_PLL_C5): - ret = ALT_E_BAD_ARG; - break; + // These clocks are not gated, so must return a ALT_E_BAD_ARG type error. + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_MPU: + case ALT_CLK_MPU_L2_RAM: + case ALT_CLK_MPU_PERIPH: + case ALT_CLK_L3_MAIN: + case ALT_CLK_L3_SP: + case ALT_CLK_DBG_BASE: + case ALT_CLK_MAIN_QSPI: + case ALT_CLK_MAIN_NAND_SDMMC: + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_SDRAM_PLL_C5: + status = ALT_E_BAD_ARG; + break; - /* Clocks that originate at the Main PLL */ - case (ALT_CLK_L4_MAIN): - ret = (ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_L3_MP): - ret = (ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_L4_MP): - ret = (ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_L4_SP): - ret = (ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG_AT): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG_TRACE): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG_TIMER): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_CFG): - ret = (ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_H2F_USER0): - ret = (ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + status = (ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L3_MP: + status = (ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L4_MP: + status = (ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L4_SP: + status = (ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_AT: + status = (ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG: + status = (ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_TRACE: + status = (ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_TIMER: + status = (ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CFG: + status = (ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER0: + status = (ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - /* Clocks that originate at the Peripheral PLL */ - case (ALT_CLK_EMAC0): - ret = (ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_EMAC1): - ret = (ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_USB_MP): - ret = (ALT_CLKMGR_PERPLL_EN_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_SPI_M): - ret = (ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_CAN0): - ret = (ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_CAN1): - ret = (ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_GPIO_DB): - ret = (ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_H2F_USER1): - ret = (ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + status = (ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_EMAC1: + status = (ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_USB_MP: + status = (ALT_CLKMGR_PERPLL_EN_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_SPI_M: + status = (ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CAN0: + status = (ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CAN1: + status = (ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_GPIO_DB: + status = (ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER1: + status = (ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - /* Clocks that may originate at the Main PLL, the Peripheral PLL, or the FPGA */ - case (ALT_CLK_SDMMC): - ret = (ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_NAND_X): - ret = (ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_NAND): - ret = (ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_QSPI): - ret = (ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that may originate at the Main PLL, the Peripheral PLL, or the FPGA. + case ALT_CLK_SDMMC: + status = (ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_NAND_X: + status = (ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_NAND: + status = (ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_QSPI: + status = (ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - /* Clocks that originate at the SDRAM PLL */ - case (ALT_CLK_DDR_DQS): - ret = (ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DDR_2X_DQS): - ret = (ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DDR_DQ): - ret = (ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_H2F_USER2): - ret = (ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + status = (ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DDR_2X_DQS: + status = (ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DDR_DQ: + status = (ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER2: + status = (ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - default: - break; + default: + status = ALT_E_BAD_ARG; + break; } - return ret; -} - -/****************************************************************************************/ -/* alt_clk_source_get() gets the input reference clock source selection value for the */ -/* specified clock or PLL. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_source_get() gets the input reference clock source selection value for the +// specified clock or PLL. +// ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk) { - ALT_CLK_t ret = ALT_CLK_UNKNOWN; - uint32_t temp; + ALT_CLK_t ret = ALT_CLK_UNKNOWN; + uint32_t temp; switch (clk) { - /* Potential external clock sources */ - case ALT_CLK_IN_PIN_OSC1: - case ALT_CLK_IN_PIN_OSC2: - case ALT_CLK_F2H_PERIPH_REF: - case ALT_CLK_F2H_SDRAM_REF: - case ALT_CLK_IN_PIN_JTAG: - case ALT_CLK_IN_PIN_ULPI0: - case ALT_CLK_IN_PIN_ULPI1: - case ALT_CLK_IN_PIN_EMAC0_RX: - case ALT_CLK_IN_PIN_EMAC1_RX: - ret = clk; - break; // these clock entities are their own source - - /* Phase-Locked Loops */ - case ALT_CLK_MAIN_PLL: - case ALT_CLK_OSC1: - ret = ALT_CLK_IN_PIN_OSC1; - break; - case ALT_CLK_PERIPHERAL_PLL: - ret = alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL); - break; - case ALT_CLK_SDRAM_PLL: - ret = alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL); - break; + // Potential external clock sources. + // these clock entities are their own source + case ALT_CLK_IN_PIN_OSC1: + case ALT_CLK_IN_PIN_OSC2: + case ALT_CLK_F2H_PERIPH_REF: + case ALT_CLK_F2H_SDRAM_REF: + case ALT_CLK_IN_PIN_JTAG: + case ALT_CLK_IN_PIN_ULPI0: + case ALT_CLK_IN_PIN_ULPI1: + case ALT_CLK_IN_PIN_EMAC0_RX: + case ALT_CLK_IN_PIN_EMAC1_RX: + ret = clk; + break; - /* Main Clock Group */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_MAIN_PLL_C3: - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_PLL_C5: - // check bypass, return either osc1 or PLL ID - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL; - break; + // Phase-Locked Loops. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_OSC1: + ret = ALT_CLK_IN_PIN_OSC1; + break; + case ALT_CLK_PERIPHERAL_PLL: + ret = alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL); + break; + case ALT_CLK_SDRAM_PLL: + ret = alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL); + break; + + // Main Clock Group. + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + // check bypass, return either osc1 or PLL ID + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL; + break; + + case ALT_CLK_MPU_PERIPH: + case ALT_CLK_MPU_L2_RAM: + case ALT_CLK_MPU: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C0; + break; + + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + case ALT_CLK_L3_MP: + case ALT_CLK_L3_SP: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + break; - case ALT_CLK_MPU_PERIPH: - case ALT_CLK_MPU_L2_RAM: - case ALT_CLK_MPU: + case ALT_CLK_L4_MP: + // read the state of the L4_mp source bit + if ((ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) + == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C0; - break; + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + } + else + { + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + } + break; - case ALT_CLK_L4_MAIN: - case ALT_CLK_L3_MAIN: - case ALT_CLK_L3_MP: - case ALT_CLK_L3_SP: + case ALT_CLK_L4_SP: + // read the state of the source bit + if ((ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) + == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; - break; + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + } + else + { + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + } + break; - case ALT_CLK_L4_MP: - // read the state of the L4_mp source bit - if ((ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) - == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; - } - else - { - // if the clock comes from periph_base_clk - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; - } - break; + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_AT: + case ALT_CLK_DBG_TRACE: + case ALT_CLK_DBG_TIMER: + case ALT_CLK_DBG: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C2; + break; + case ALT_CLK_MAIN_QSPI: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C3; + break; + case ALT_CLK_MAIN_NAND_SDMMC: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C4; + break; + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C5; + break; - case ALT_CLK_L4_SP: - // read the state of the source bit - if ((ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) - == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; - } - else - { - // if the clock comes from periph_base_clk - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; - } - break; + // Peripherals Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL; + break; - case ALT_CLK_DBG_BASE: - case ALT_CLK_DBG_AT: - case ALT_CLK_DBG_TRACE: - case ALT_CLK_DBG_TIMER: - case ALT_CLK_DBG: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C2; - break; - case ALT_CLK_MAIN_QSPI: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C3; - break; - case ALT_CLK_MAIN_NAND_SDMMC: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C4; - break; - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C5; - break; + case ALT_CLK_EMAC0: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C0; + break; - /* Peripherals Clock Group */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_PERIPHERAL_PLL_C2: - case ALT_CLK_PERIPHERAL_PLL_C3: - case ALT_CLK_PERIPHERAL_PLL_C4: - case ALT_CLK_PERIPHERAL_PLL_C5: - // if the clock comes from periph_base_clk - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL; - break; + case ALT_CLK_EMAC1: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C1; + break; - case ALT_CLK_EMAC0: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C0; - break; + case ALT_CLK_USB_MP: + case ALT_CLK_SPI_M: + case ALT_CLK_CAN0: + case ALT_CLK_CAN1: + case ALT_CLK_GPIO_DB: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + break; - case ALT_CLK_EMAC1: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C1; - break; + case ALT_CLK_H2F_USER1: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C5; + break; - case ALT_CLK_USB_MP: - case ALT_CLK_SPI_M: - case ALT_CLK_CAN0: - case ALT_CLK_CAN1: - case ALT_CLK_GPIO_DB: + case ALT_CLK_SDMMC: + temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; - break; + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; + } + break; - case ALT_CLK_H2F_USER1: + case ALT_CLK_NAND_X: + case ALT_CLK_NAND: + temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C5; - break; - - case ALT_CLK_SDMMC: - temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) - { - ret = ALT_CLK_F2H_PERIPH_REF; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; - } - break; + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; + } + break; - case ALT_CLK_NAND_X: - case ALT_CLK_NAND: - temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) - { - ret = ALT_CLK_F2H_PERIPH_REF; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; - } - break; + case ALT_CLK_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C3; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C2; + } + break; - case ALT_CLK_QSPI: - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) - { - ret = ALT_CLK_F2H_PERIPH_REF; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C3; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C2; - } - break; + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_SDRAM_PLL_C3: + case ALT_CLK_SDRAM_PLL_C4: + case ALT_CLK_SDRAM_PLL_C5: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL; + break; + case ALT_CLK_DDR_DQS: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C0; + break; + case ALT_CLK_DDR_2X_DQS: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C1; + break; + case ALT_CLK_DDR_DQ: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C2; + break; + case ALT_CLK_H2F_USER2: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C5; + break; - /* SDRAM Clock Group */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_SDRAM_PLL_C3: - case ALT_CLK_SDRAM_PLL_C4: - case ALT_CLK_SDRAM_PLL_C5: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL; - break; - case ALT_CLK_DDR_DQS: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C0; - break; - case ALT_CLK_DDR_2X_DQS: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C1; - break; - case ALT_CLK_DDR_DQ: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C2; - break; - case ALT_CLK_H2F_USER2: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C5; - break; + // Clock Output Pins + case ALT_CLK_OUT_PIN_EMAC0_TX: + case ALT_CLK_OUT_PIN_EMAC1_TX: + case ALT_CLK_OUT_PIN_SDMMC: + case ALT_CLK_OUT_PIN_I2C0_SCL: + case ALT_CLK_OUT_PIN_I2C1_SCL: + case ALT_CLK_OUT_PIN_I2C2_SCL: + case ALT_CLK_OUT_PIN_I2C3_SCL: + case ALT_CLK_OUT_PIN_SPIM0: + case ALT_CLK_OUT_PIN_SPIM1: + case ALT_CLK_OUT_PIN_QSPI: + ret = ALT_CLK_UNKNOWN; + break; - /* Clock Output Pins */ - case ALT_CLK_OUT_PIN_EMAC0_TX: - case ALT_CLK_OUT_PIN_EMAC1_TX: - case ALT_CLK_OUT_PIN_SDMMC: - case ALT_CLK_OUT_PIN_I2C0_SCL: - case ALT_CLK_OUT_PIN_I2C1_SCL: - case ALT_CLK_OUT_PIN_I2C2_SCL: - case ALT_CLK_OUT_PIN_I2C3_SCL: - case ALT_CLK_OUT_PIN_SPIM0: - case ALT_CLK_OUT_PIN_SPIM1: - case ALT_CLK_OUT_PIN_QSPI: - ret = ALT_CLK_UNKNOWN; - break; + default: + ret = ALT_CLK_UNKNOWN; + break; + } - default: - break; - } /* end big switch/case construct */ return ret; } - -/****************************************************************************************/ -/* alt_clk_source_set() sets the specified clock's input reference clock source */ -/* selection to the specified input. It does not handle gating the specified clock */ -/* off and back on, those are covered in other functions in this API, but it does */ -/* verify that the clock is off before changing the divider or PLL. Note that the PLL */ -/* must have regained phase-lock before being the bypass is disabled. */ -/****************************************************************************************/ - -ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk) +// +// alt_clk_source_set() sets the specified clock's input reference clock source +// selection to the specified input. It does not handle gating the specified clock +// off and back on, those are covered in other functions in this API, but it does +// verify that the clock is off before changing the divider or PLL. Note that the PLL +// must have regained phase-lock before being the bypass is disabled. +// +ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; if (ALT_CLK_MAIN_PLL == clk) { - if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) { ret = ALT_E_SUCCESS; } + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) + { + // ret = ALT_E_SUCCESS; + } + else + { + status = ALT_E_BAD_ARG; + } } else if (ALT_CLK_PERIPHERAL_PLL == clk) { - // the PLL must be bypassed before getting here - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + // the PLL must be bypassed before getting here + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); temp &= ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK; + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) { temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1); alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_IN_PIN_OSC2) { temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2); alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF); alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - else if ( ALT_CLK_SDRAM_PLL == clk) + else if (ALT_CLK_SDRAM_PLL == clk) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); temp &= ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK; + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) { temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1); alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_IN_PIN_OSC2) { temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2); alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_F2H_SDRAM_REF) { temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF); alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - else if ( ALT_CLK_L4_MP == clk) { - // clock is gated off + // clock is gated off if (ref_clk == ALT_CLK_MAIN_PLL_C1) { alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4) { alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - else if ( ALT_CLK_L4_SP == clk) { if (ref_clk == ALT_CLK_MAIN_PLL_C1) { alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4) { alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - - else if ( ALT_CLK_SDMMC == clk) + else if (ALT_CLK_SDMMC == clk) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); temp &= ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK; + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC)) { temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3) { temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - - else if (( ALT_CLK_NAND_X == clk) || ( ALT_CLK_NAND == clk)) + else if ((ALT_CLK_NAND_X == clk) || ( ALT_CLK_NAND == clk)) { temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); temp &= ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK; + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC)) { temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3) { temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - - else if ( ALT_CLK_QSPI == clk) + else if (ALT_CLK_QSPI == clk) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); temp &= ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK; + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if ((ref_clk == ALT_CLK_MAIN_PLL_C3) || (ref_clk == ALT_CLK_MAIN_QSPI)) { temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C2) { temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - return ret; -} - - -/****************************************************************************************/ -/* alt_clk_ext_clk_freq_set() specifies the frequency of the external clock source as */ -/* a measure of Hz. This value is stored in a static array and used for calculations. */ -/* The supplied frequency should be within the Fmin and Fmax values allowed for the */ -/* external clock source. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_ext_clk_freq_set() specifies the frequency of the external clock source as +// a measure of Hz. This value is stored in a static array and used for calculations. +// The supplied frequency should be within the Fmin and Fmax values allowed for the +// external clock source. +// ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk, alt_freq_t freq) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1)) // two names for one input { if ((freq >= alt_ext_clk_paramblok.clkosc1.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc1.freqmax)) { alt_ext_clk_paramblok.clkosc1.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - else if (clk == ALT_CLK_IN_PIN_OSC2) // the other clock input pin { if ((freq >= alt_ext_clk_paramblok.clkosc2.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc2.freqmax)) { alt_ext_clk_paramblok.clkosc2.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - else if (clk == ALT_CLK_F2H_PERIPH_REF) // clock from the FPGA { if ((freq >= alt_ext_clk_paramblok.periph.freqmin) && (freq <= alt_ext_clk_paramblok.periph.freqmax)) { alt_ext_clk_paramblok.periph.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - else if (clk == ALT_CLK_F2H_SDRAM_REF) // clock from the FPGA SDRAM { if ((freq >= alt_ext_clk_paramblok.sdram.freqmin) && (freq <= alt_ext_clk_paramblok.sdram.freqmax)) { alt_ext_clk_paramblok.sdram.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - return ret; -} - + else + { + status = ALT_E_BAD_ARG; + } -/****************************************************************************************/ -/* alt_clk_ext_clk_freq_get returns the frequency of the external clock source as */ -/* a measure of Hz. This value is stored in a static array. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_ext_clk_freq_get returns the frequency of the external clock source as +// a measure of Hz. This value is stored in a static array. +// alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk) { - uint32_t ret = 0; + uint32_t ret = 0; if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1)) // two names for one input { @@ -1754,323 +1777,341 @@ alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk) } -/****************************************************************************************/ -/* alt_clk_pll_cfg_get() returns the current PLL configuration. */ -/****************************************************************************************/ +// +// alt_clk_pll_cfg_get() returns the current PLL configuration. +// +ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll, ALT_CLK_PLL_CFG_t * pll_cfg) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // return value + uint32_t temp; // temp variable + + if (pll_cfg == NULL) + { + ret = ALT_E_BAD_ARG; + return ret; + } + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; + pll_cfg->mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + pll_cfg->div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); -ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll, ALT_CLK_PLL_CFG_t* pll_cfg) -{ - ALT_STATUS_CODE ret = ALT_E_ERROR; // return value - uint32_t temp; // temp variable - - if (pll_cfg != NULL) - { - if (pll == ALT_CLK_MAIN_PLL) - { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; - pll_cfg->mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); - pll_cfg->div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); - - // Get the C0-C5 divider values: - pll_cfg->cntrs[0] = ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)); - // C0 - mpu_clk - - pll_cfg->cntrs[1] = ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)); - // C1 - main_clk - - pll_cfg->cntrs[2] = ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)); - // C2 - dbg_base_clk - - pll_cfg->cntrs[3] = ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR)); - // C3 - main_qspi_clk - - pll_cfg->cntrs[4] = ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR)); - // C4 - main_nand_sdmmc_clk - - pll_cfg->cntrs[5] = ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR)); - // C5 - cfg_s2f_user0_clk aka cfg_h2f_user0_clk - - // The Main PLL C0-C5 outputs have no phase shift capabilities : - pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = - pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; - ret = ALT_E_SUCCESS; - } - else if (pll == ALT_CLK_PERIPHERAL_PLL) - { - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); - if (temp <= 2) - { - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { - pll_cfg->ref_clk = ALT_CLK_F2H_PERIPH_REF; - } - - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - pll_cfg->mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); - pll_cfg->div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - - // Get the C0-C5 divider values: - pll_cfg->cntrs[0] = ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR)); - // C0 - emac0_clk - - pll_cfg->cntrs[1] = ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR)); - // C1 - emac1_clk - - pll_cfg->cntrs[2] = ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR)); - // C2 - periph_qspi_clk - - pll_cfg->cntrs[3] = ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR)); - // C3 - periph_nand_sdmmc_clk - - pll_cfg->cntrs[4] = ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR)); - // C4 - periph_base_clk - - pll_cfg->cntrs[5] = ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR)); - // C5 - s2f_user1_clk - - // The Peripheral PLL C0-C5 outputs have no phase shift capabilities : - pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = - pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; - ret = ALT_E_SUCCESS; - } - } - else if (pll == ALT_CLK_SDRAM_PLL) - { - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - if (temp <= 2) - { - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { - pll_cfg->ref_clk = ALT_CLK_F2H_SDRAM_REF; - } - - pll_cfg->mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - pll_cfg->div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - - // Get the C0-C5 divider values: - pll_cfg->cntrs[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); - pll_cfg->pshift[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); - // C0 - ddr_dqs_clk - - pll_cfg->cntrs[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); - pll_cfg->pshift[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); - // C1 - ddr_2x_dqs_clk - - pll_cfg->cntrs[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); - pll_cfg->pshift[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); - // C2 - ddr_dq_clk - - pll_cfg->cntrs[3] = pll_cfg->cntrs[4] = pll_cfg->pshift[3] = pll_cfg->pshift[4] = 0; - // C3 & C4 outputs don't exist on the SDRAM PLL - - pll_cfg->cntrs[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); - pll_cfg->pshift[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); - // C5 - s2f_user2_clk or h2f_user2_clk - - ret = ALT_E_SUCCESS; - } - } - } - return ret; -} + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)); + // C0 - mpu_clk + pll_cfg->cntrs[1] = ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)); + // C1 - main_clk -/****************************************************************************************/ -/* alt_clk_pll_cfg_set() sets the PLL configuration using the configuration parameters */ -/* specified in pll_cfg. */ -/****************************************************************************************/ + pll_cfg->cntrs[2] = ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)); + // C2 - dbg_base_clk -ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll, const ALT_CLK_PLL_CFG_t* pll_cfg) -{ - ALT_STATUS_CODE ret = ALT_E_ERROR; - uint32_t temp; + pll_cfg->cntrs[3] = ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR)); + // C3 - main_qspi_clk + + pll_cfg->cntrs[4] = ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR)); + // C4 - main_nand_sdmmc_clk - if (pll_cfg != NULL) + pll_cfg->cntrs[5] = ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR)); + // C5 - cfg_s2f_user0_clk aka cfg_h2f_user0_clk + + // The Main PLL C0-C5 outputs have no phase shift capabilities : + pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = + pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) { - if (alt_clk_pll_is_bypassed(pll) == ALT_E_TRUE) // safe to write the PLL registers? + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + if (temp <= 2) { - if (pll == ALT_CLK_MAIN_PLL) + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) { - temp = (ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK) - & alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - temp |= ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(pll_cfg->mult) | - ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(pll_cfg->div); - alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp); - alt_write_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, pll_cfg->cntrs[0]); - alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, pll_cfg->cntrs[1]); - alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, pll_cfg->cntrs[2]); - alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, pll_cfg->cntrs[3]); - alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, pll_cfg->cntrs[4]); - alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, pll_cfg->cntrs[5]); - ret = ALT_E_SUCCESS; + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; } - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) { - temp = ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK - & ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK; - temp &= alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - temp |= ALT_CLKMGR_PERPLL_VCO_NUMER_SET(pll_cfg->mult) - | ALT_CLKMGR_PERPLL_VCO_DENOM_SET(pll_cfg->div); - if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) - { - temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1); - } - else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) - { - temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2); - } - else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) - { - temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF); - } - else { return ret; } - - alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, pll_cfg->cntrs[0]); - alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, pll_cfg->cntrs[1]); - alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, pll_cfg->cntrs[2]); - alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, pll_cfg->cntrs[3]); - alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, pll_cfg->cntrs[4]); - alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, pll_cfg->cntrs[5]); - ret = ALT_E_SUCCESS; + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; } - else if (pll == ALT_CLK_SDRAM_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) { - // write the SDRAM PLL VCO Counter ----------------------------- - temp = ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK - & ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK; // make a mask - temp &= alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - temp |= ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(pll_cfg->mult) - | ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(pll_cfg->div) - | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK; - // setting this bit aligns the output phase of the counters and prevents - // glitches and too-short clock periods when restarting. - // this bit is cleared at the end of this routine - - if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) - { - temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1); - } - else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) - { - temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2); - } - else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) - { - temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF); - } - else { return ret; } - alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); + pll_cfg->ref_clk = ALT_CLK_F2H_PERIPH_REF; + } - // write the SDRAM PLL C0 Divide Counter ----------------------------- - temp = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(pll_cfg->cntrs[0]) - | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(pll_cfg->pshift[0]); + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + pll_cfg->mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + pll_cfg->div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR)); + // C0 - emac0_clk - // write the SDRAM PLL C1 Divide Counter ----------------------------- - if (ret == ALT_E_SUCCESS) - { - temp = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(pll_cfg->cntrs[1]) - | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(pll_cfg->pshift[1]); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB); - } + pll_cfg->cntrs[1] = ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR)); + // C1 - emac1_clk - // write the SDRAM PLL C2 Divide Counter ----------------------------- - if (ret == ALT_E_SUCCESS) - { - temp = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(pll_cfg->cntrs[2]) - | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(pll_cfg->pshift[2]); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB); - } + pll_cfg->cntrs[2] = ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR)); + // C2 - periph_qspi_clk - // write the SDRAM PLL C5 Divide Counter ----------------------------- - if (ret == ALT_E_SUCCESS) - { - temp = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(pll_cfg->cntrs[2]) - | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(pll_cfg->pshift[2]); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB); - } + pll_cfg->cntrs[3] = ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR)); + // C3 - periph_nand_sdmmc_clk - if (ret == ALT_E_SUCCESS) - { - alt_clrbits_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK); - // allow the phase multiplexer and output counter to leave reset - } + pll_cfg->cntrs[4] = ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR)); + // C4 - periph_base_clk + + pll_cfg->cntrs[5] = ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR)); + // C5 - s2f_user1_clk + + // The Peripheral PLL C0-C5 outputs have no phase shift capabilities : + pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = + pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; + ret = ALT_E_SUCCESS; + } + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + if (temp <= 2) + { + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + pll_cfg->ref_clk = ALT_CLK_F2H_SDRAM_REF; + } + + pll_cfg->mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + pll_cfg->div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); + pll_cfg->pshift[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); + // C0 - ddr_dqs_clk + + pll_cfg->cntrs[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); + pll_cfg->pshift[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); + // C1 - ddr_2x_dqs_clk + + pll_cfg->cntrs[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); + pll_cfg->pshift[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); + // C2 - ddr_dq_clk + + pll_cfg->cntrs[3] = pll_cfg->cntrs[4] = pll_cfg->pshift[3] = pll_cfg->pshift[4] = 0; + // C3 & C4 outputs don't exist on the SDRAM PLL + + pll_cfg->cntrs[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); + pll_cfg->pshift[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); + // C5 - s2f_user2_clk or h2f_user2_clk + + ret = ALT_E_SUCCESS; } } + return ret; } -/****************************************************************************************/ -/* alt_clk_pll_vco_cfg_get() returns the current PLL VCO frequency configuration. */ -/****************************************************************************************/ - -ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll, uint32_t* mult, uint32_t* div) +// +// alt_clk_pll_cfg_set() sets the PLL configuration using the configuration parameters +// specified in pll_cfg. +// +ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll, const ALT_CLK_PLL_CFG_t * pll_cfg) { - ALT_STATUS_CODE ret = ALT_E_ERROR; - uint32_t temp; + if (pll_cfg == NULL) + { + return ALT_E_BAD_ARG; + } - if ((mult != NULL) && (div != NULL)) + if (alt_clk_pll_is_bypassed(pll) != ALT_E_TRUE) // safe to write the PLL registers? { - if (pll == ALT_CLK_MAIN_PLL) + return ALT_E_ERROR; + } + + ALT_STATUS_CODE ret = ALT_E_ERROR; + uint32_t temp; + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = (ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK) + & alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + temp |= ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(pll_cfg->mult) | + ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(pll_cfg->div); + + alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp); + alt_write_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR, pll_cfg->cntrs[0]); + alt_write_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR, pll_cfg->cntrs[1]); + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, pll_cfg->cntrs[2]); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, pll_cfg->cntrs[3]); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, pll_cfg->cntrs[4]); + alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, pll_cfg->cntrs[5]); + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK + & ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK; + temp &= alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + temp |= ALT_CLKMGR_PERPLL_VCO_NUMER_SET(pll_cfg->mult) + | ALT_CLKMGR_PERPLL_VCO_DENOM_SET(pll_cfg->div); + + if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - *mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp) + 1; - *div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp) + 1; - ret = ALT_E_SUCCESS; + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1); } - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - *mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp) + 1; - *div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp) + 1; - ret = ALT_E_SUCCESS; + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2); } - else if (pll == ALT_CLK_SDRAM_PLL) + else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - *mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp) + 1; - *div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp) + 1; - ret = ALT_E_SUCCESS; + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF); + } + else + { + return ret; + } + + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, pll_cfg->cntrs[0]); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, pll_cfg->cntrs[1]); + alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, pll_cfg->cntrs[2]); + alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, pll_cfg->cntrs[3]); + alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, pll_cfg->cntrs[4]); + alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, pll_cfg->cntrs[5]); + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + // write the SDRAM PLL VCO Counter ----------------------------- + temp = ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK + & ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK; // make a mask + temp &= alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + temp |= ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(pll_cfg->mult) + | ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(pll_cfg->div) + | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK; + // setting this bit aligns the output phase of the counters and prevents + // glitches and too-short clock periods when restarting. + // this bit is cleared at the end of this routine + + if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1); + } + else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2); + } + else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF); + } + else + { + return ret; + } + + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); + + // write the SDRAM PLL C0 Divide Counter ----------------------------- + temp = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(pll_cfg->cntrs[0]) + | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(pll_cfg->pshift[0]); + + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); + + // write the SDRAM PLL C1 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(pll_cfg->cntrs[1]) + | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(pll_cfg->pshift[1]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB); + } + + // write the SDRAM PLL C2 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(pll_cfg->cntrs[2]) + | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(pll_cfg->pshift[2]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB); + } + + // write the SDRAM PLL C5 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(pll_cfg->cntrs[2]) + | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(pll_cfg->pshift[2]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB); + } + + if (ret == ALT_E_SUCCESS) + { + alt_clrbits_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK); + // allow the phase multiplexer and output counter to leave reset } } + return ret; } +// +// alt_clk_pll_vco_cfg_get() returns the current PLL VCO frequency configuration. +// +ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll, uint32_t * mult, uint32_t * div) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; + + if ( (mult == NULL) || (div == NULL) ) + { + return ALT_E_BAD_ARG; + } + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + *mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp) + 1; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + *mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp) + 1; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + *mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp) + 1; + } + else + { + status = ALT_E_ERROR; + } + + return status; +} + + /****************************************************************************************/ /* This enum enumerates a set of possible change methods that are available for use by */ /* alt_clk_pll_vco_cfg_set() to change VCO parameter settings. */ @@ -2123,10 +2164,20 @@ static ALT_CLK_PLL_VCO_CHG_METHOD_t alt_clk_pll_vco_chg_methods_get(ALT_CLK_t pl uint32_t mult, uint32_t div ) { #if ALT_CLK_PLL_VCO_CHG_METHOD_TEST_MODE + // used for testing - return ALT_VCO_CHG_NOCHANGE; + return ALT_VCO_CHG_NOCHANGE; + +#else + + // check PLL max value limits + if ( (mult == 0) || (mult > ALT_CLK_PLL_MULT_MAX) + || (div == 0) || (div > ALT_CLK_PLL_DIV_MAX) + ) + { + return ALT_VCO_CHG_NONE_VALID; + } -#endif ALT_CLK_PLL_VCO_CHG_METHOD_t ret = ALT_VCO_CHG_NONE_VALID; uint32_t temp; uint32_t numer; @@ -2139,124 +2190,148 @@ static ALT_CLK_PLL_VCO_CHG_METHOD_t alt_clk_pll_vco_chg_methods_get(ALT_CLK_t pl bool denomchg = false; bool within_gb; - if ((mult > 0) && (mult <= ALT_CLK_PLL_MULT_MAX) && (div > 0) - && (div <= ALT_CLK_PLL_DIV_MAX)) // check PLL max value limits + // gather data values according to PLL + if (pll == ALT_CLK_MAIN_PLL) { - // gather data values according to PLL - if (pll == ALT_CLK_MAIN_PLL) + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + + numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.MainPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.MainPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.MainPLL_800.guardband; + + inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; + } + + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + + numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.PeriphPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.PeriphPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.PeriphPLL_800.guardband; + + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); - freqmax = alt_pll_clk_paramblok.MainPLL_800.freqmax; - freqmin = alt_pll_clk_paramblok.MainPLL_800.freqmin; - guardband = alt_pll_clk_paramblok.MainPLL_800.guardband; inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; } - - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); - freqmax = alt_pll_clk_paramblok.PeriphPLL_800.freqmax; - freqmin = alt_pll_clk_paramblok.PeriphPLL_800.freqmin; - guardband = alt_pll_clk_paramblok.PeriphPLL_800.guardband; - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { - inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { - inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { - inputfreq = alt_ext_clk_paramblok.periph.freqcur; - } - else { return ret; } + inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; } - - else if (pll == ALT_CLK_SDRAM_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); - freqmax = alt_pll_clk_paramblok.SDRAMPLL_800.freqmax; - freqmin = alt_pll_clk_paramblok.SDRAMPLL_800.freqmin; - guardband = alt_pll_clk_paramblok.SDRAMPLL_800.guardband; - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { - inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { - inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { - inputfreq = alt_ext_clk_paramblok.sdram.freqcur; - } - else { return ret; } + inputfreq = alt_ext_clk_paramblok.periph.freqcur; } - else { return ret; } + else + { + return ret; + } + } - temp = (mult * inputfreq) / div; - if ((temp <= freqmax) && (temp >= freqmin)) // are the final values within frequency limits? + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + + numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.SDRAMPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.SDRAMPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.SDRAMPLL_800.guardband; + + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) { - numer++; - denom++; - numerchg = (mult != numer); - denomchg = (div != denom); + inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + inputfreq = alt_ext_clk_paramblok.sdram.freqcur; + } + else + { + return ret; + } + } + else + { + return ret; + } - if (!numerchg && !denomchg) + temp = mult * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) // are the final values within frequency limits? + { + numer++; + denom++; + numerchg = (mult != numer); + denomchg = (div != denom); + + if (!numerchg && !denomchg) + { + ret = ALT_VCO_CHG_NOCHANGE; + } + else if (numerchg && !denomchg) + { + within_gb = alt_within_delta(numer, mult, guardband); + // check if change is within the guardband limits + temp = mult * (inputfreq / denom); + if ((temp <= freqmax) && (temp >= freqmin)) { - ret = ALT_VCO_CHG_NOCHANGE; + ret = ALT_VCO_CHG_NUM; + if (!within_gb) ret |= ALT_VCO_CHG_NUM_BYP; } - else if (numerchg && !denomchg) + } + else if (!numerchg && denomchg) + { + within_gb = alt_within_delta(denom, div, guardband); + temp = numer * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) { - within_gb = alt_within_delta(numer, mult, guardband); - // check if change is within the guardband limits - temp = (mult * inputfreq) / denom; - if ((temp <= freqmax) && (temp >= freqmin)) + ret = ALT_VCO_CHG_DENOM; + if (!within_gb) { - ret = ALT_VCO_CHG_NUM; - if (!within_gb) ret |= ALT_VCO_CHG_NUM_BYP; + ret |= ALT_VCO_CHG_DENOM_BYP; } } - else if (!numerchg && denomchg) + } + else //numerchg && denomchg + { + within_gb = alt_within_delta(numer, mult, guardband); + temp = mult * (inputfreq / denom); + if ((temp <= freqmax) && (temp >= freqmin)) { - within_gb = alt_within_delta(denom, div, guardband); - temp = (numer * inputfreq) / div; - if ((temp <= freqmax) && (temp >= freqmin)) + ret = ALT_VCO_CHG_NUM_DENOM; + if (!within_gb) { - ret = ALT_VCO_CHG_DENOM; - if (!within_gb) ret |= ALT_VCO_CHG_DENOM_BYP; + ret |= ALT_VCO_CHG_NUM_DENOM_BYP; } } - else //numerchg && denomchg + within_gb = alt_within_delta(denom, div, guardband); + temp = numer * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) { - within_gb = alt_within_delta(numer, mult, guardband); - temp = (mult * inputfreq) / denom; - if ((temp <= freqmax) && (temp >= freqmin)) + ret = ALT_VCO_CHG_DENOM_NUM; + if (!within_gb) { - ret = ALT_VCO_CHG_NUM_DENOM; - if (!within_gb) ret |= ALT_VCO_CHG_NUM_DENOM_BYP; - } - within_gb = alt_within_delta(denom, div, guardband); - temp = (numer * inputfreq) / div; - if ((temp <= freqmax) && (temp >= freqmin)) - { - ret = ALT_VCO_CHG_DENOM_NUM; - if (!within_gb) ret |= ALT_VCO_CHG_DENOM_NUM_BYP; + ret |= ALT_VCO_CHG_DENOM_NUM_BYP; } } } } return ret; +#endif } @@ -2387,15 +2462,13 @@ ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll, uint32_t mult, uint32_t d } -/****************************************************************************************/ -/* alt_clk_pll_vco_freq_get() gets the VCO frequency of the specified PLL. */ -/* Note that since there is at present no known way for software to obtain the speed */ -/* bin of the SoC or MPU that it is running on, the function below only deals with the */ -/* 800 MHz part. This may need to be revised in the future. */ -/****************************************************************************************/ - - -ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, alt_freq_t* freq) +// +// alt_clk_pll_vco_freq_get() gets the VCO frequency of the specified PLL. +// Note that since there is at present no known way for software to obtain the speed +// bin of the SoC or MPU that it is running on, the function below only deals with the +// 800 MHz part. This may need to be revised in the future. +// +ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, alt_freq_t * freq) { uint64_t temp1 = 0; uint32_t temp; @@ -2403,99 +2476,120 @@ ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, alt_freq_t* freq) uint32_t denom; ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - if (freq != NULL) + if (freq == NULL) { - if (pll == ALT_CLK_MAIN_PLL) + return ret; + } + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; + temp1 *= (numer + 1); + temp1 /= (denom + 1); + + if (temp1 <= UINT32_MAX) + { + temp = (alt_freq_t) temp1; + alt_pll_clk_paramblok.MainPLL_800.freqcur = temp; + // store this value in the parameter block table + *freq = temp; + // should NOT check value against PLL frequency limits + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ERROR; + } + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + } + + if (temp1 != 0) + { temp1 *= (numer + 1); temp1 /= (denom + 1); if (temp1 <= UINT32_MAX) { temp = (alt_freq_t) temp1; - alt_pll_clk_paramblok.MainPLL_800.freqcur = temp; - // store this value in the parameter block table + alt_pll_clk_paramblok.PeriphPLL_800.freqcur = temp; + // store this value in the parameter block table + *freq = temp; - // should NOT check value against PLL frequency limits ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ERROR; } + else + { + ret = ALT_E_ERROR; + } + } // this returns ALT_BAD_ARG if the source isn't known + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; } - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { temp1 = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; } - - if (temp1 != 0) - { - temp1 *= (numer + 1); - temp1 /= (denom + 1); - if (temp1 <= UINT32_MAX) - { - temp = (alt_freq_t) temp1; - alt_pll_clk_paramblok.PeriphPLL_800.freqcur = temp; - // store this value in the parameter block table - - *freq = temp; - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ERROR; } - } // this returns ALT_BAD_ARG if the source isn't known + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; } - else if (pll == ALT_CLK_SDRAM_PLL) + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { temp1 = (uint64_t) alt_ext_clk_paramblok.sdram.freqcur; } + temp1 = (uint64_t) alt_ext_clk_paramblok.sdram.freqcur; + } - if (temp1 != 0) + if (temp1 != 0) + { + temp1 *= (numer + 1); + temp1 /= (denom + 1); + if (temp1 <= UINT32_MAX) { - temp1 *= (numer + 1); - temp1 /= (denom + 1); - if (temp1 <= UINT32_MAX) - { - temp = (alt_freq_t) temp1; - alt_pll_clk_paramblok.SDRAMPLL_800.freqcur = temp; - // store this value in the parameter block table + temp = (alt_freq_t) temp1; + alt_pll_clk_paramblok.SDRAMPLL_800.freqcur = temp; + // store this value in the parameter block table - *freq = temp; - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ERROR; } + *freq = temp; + ret = ALT_E_SUCCESS; } - } // which returns ALT_BAD_ARG if the source isn't known - } + else + { + ret = ALT_E_ERROR; + } + } + } // which returns ALT_BAD_ARG if the source isn't known + return ret; } - -/****************************************************************************************/ -/* Returns the current guard band range in effect for the PLL. */ -/****************************************************************************************/ - - +// +// Returns the current guard band range in effect for the PLL. +// uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll) { - int32_t ret = 0; + uint32_t ret = 0; if (pll == ALT_CLK_MAIN_PLL) { @@ -2512,297 +2606,315 @@ uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll) return ret; } - -/****************************************************************************************/ -/* clk_mgr_pll_guard_band_set() changes the guard band from its current value to permit */ -/* a more lenient or stringent policy to be in effect for the implementation of the */ -/* functions configuring PLL VCO frequency. */ -/****************************************************************************************/ - +// +// clk_mgr_pll_guard_band_set() changes the guard band from its current value to permit +// a more lenient or stringent policy to be in effect for the implementation of the +// functions configuring PLL VCO frequency. +// ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll, uint32_t guard_band) { - ALT_STATUS_CODE ret = ALT_E_ERROR; - - if ((guard_band <= UINT12_MAX) && (guard_band > 0) && (guard_band <= ALT_GUARDBAND_LIMIT)) + if ( (guard_band > UINT12_MAX) || (guard_band <= 0) + || (guard_band > ALT_GUARDBAND_LIMIT) + ) { - if (pll == ALT_CLK_MAIN_PLL) - { - alt_pll_clk_paramblok.MainPLL_800.guardband = guard_band; - //alt_pll_clk_paramblok.MainPLL_600.guardband = guard_band; - // ??? Don't know how to check the MPU speed bin yet, so only 800 MHz struct is used - ret = ALT_E_SUCCESS; - } - else if (pll == ALT_CLK_PERIPHERAL_PLL) - { - alt_pll_clk_paramblok.PeriphPLL_800.guardband = guard_band; - //alt_pll_clk_paramblok.PeriphPLL_600.guardband = guard_band; - ret = ALT_E_SUCCESS; - } - else if (pll == ALT_CLK_SDRAM_PLL) - { - alt_pll_clk_paramblok.SDRAMPLL_800.guardband = guard_band; - //alt_pll_clk_paramblok.SDRAMPLL_600.guardband = guard_band; - ret = ALT_E_SUCCESS; - } + return ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } - return ret; -} + ALT_STATUS_CODE status = ALT_E_SUCCESS; -/****************************************************************************************/ -/* alt_clk_divider_get() gets configured divider value for the specified clock. */ -/****************************************************************************************/ + if (pll == ALT_CLK_MAIN_PLL) + { + alt_pll_clk_paramblok.MainPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.MainPLL_600.guardband = guard_band; + // ??? Don't know how to check the MPU speed bin yet, so only 800 MHz struct is used + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + alt_pll_clk_paramblok.PeriphPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.PeriphPLL_600.guardband = guard_band; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + alt_pll_clk_paramblok.SDRAMPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.SDRAMPLL_600.guardband = guard_band; + } + else + { + status = ALT_E_ERROR; + } + + return status; +} -ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, uint32_t* div) +// +// alt_clk_divider_get() gets configured divider value for the specified clock. +// +ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, uint32_t * div) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; - if (div != NULL) + if (div == NULL) { - switch (clk) - { - /* Main PLL outputs */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MPU: - *div = (ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)) + 1) << 1; - // adjust for the additional divide-by-2 internal counter on C0 - ret = ALT_E_SUCCESS; - break; + return ALT_E_BAD_ARG; + } - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_L4_MAIN: - case ALT_CLK_L3_MAIN: - *div = (ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)) + 1) << 2; - // adjust for the additional divide-by-4 internal counter on C1 - ret = ALT_E_SUCCESS; - break; + switch (clk) + { + // Main PLL outputs + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MPU: + *div = (ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)) + 1); + break; - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_DBG_BASE: - case ALT_CLK_DBG_TIMER: - *div = (ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)) + 1) << 2; - // adjust for the additional divide-by-4 internal counter on C2 - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + *div = (ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)) + 1); + break; - case ALT_CLK_MAIN_PLL_C3: - case ALT_CLK_MAIN_QSPI: - *div = (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_TIMER: + *div = (ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_DBGATCLK_ADDR)) + 1); + break; - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_NAND_SDMMC: - *div = (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_QSPI: + *div = (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR))) + 1; + break; - case ALT_CLK_MAIN_PLL_C5: - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - *div = (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - - /* Peripheral PLL outputs */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_EMAC0: - *div = (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_EMAC1: - *div = (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C2: - *div = (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C3: - *div = (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C4: - *div = (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C5: - case ALT_CLK_H2F_USER1: - *div = (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - - /* SDRAM PLL outputs */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_DDR_DQS: - *div = (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_DDR_2X_DQS: - *div = (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_DDR_DQ: - *div = (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_SDRAM_PLL_C5: - case ALT_CLK_H2F_USER2: - *div = (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - - /* Other clock dividers */ - case ALT_CLK_L3_MP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2) - { - *div = temp + 1; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_NAND_SDMMC: + *div = (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR))) + 1; + break; - case ALT_CLK_L3_SP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2) - { - *div = temp + 1; - ret = ALT_E_SUCCESS; - } - // note that this value does not include the additional effect - // of the L3_MP divider that is upchain from this one - break; + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + *div = (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR))) + 1; + break; - case ALT_CLK_L4_MP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + ///// - case ALT_CLK_L4_SP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + // Peripheral PLL outputs + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_EMAC0: + *div = (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR))) + 1; + break; - case ALT_CLK_DBG_AT: - temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_EMAC1: + *div = (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR))) + 1; + break; - case ALT_CLK_DBG: - temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - // note that this value does not include the value of the upstream dbg_at_clk divder - break; + case ALT_CLK_PERIPHERAL_PLL_C2: + *div = (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR))) + 1; + break; - case ALT_CLK_DBG_TRACE: - temp = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C3: + *div = (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR))) + 1; + break; - case ALT_CLK_USB_MP: - temp = ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C4: + *div = (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR))) + 1; + break; - case ALT_CLK_SPI_M: - temp = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_H2F_USER1: + *div = (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR))) + 1; + break; - case ALT_CLK_CAN0: - temp = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + ///// - case ALT_CLK_CAN1: - temp = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + // SDRAM PLL outputs + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + *div = (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR))) + 1; + break; - case ALT_CLK_GPIO_DB: - temp = ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR)); - *div = temp + 1; - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + *div = (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR))) + 1; + break; - case ALT_CLK_MPU_PERIPH: - *div = 4; // set by hardware - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + *div = (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR))) + 1; + break; - case ALT_CLK_MPU_L2_RAM: - *div = 2; // set by hardware - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + *div = (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR))) + 1; + break; - case ALT_CLK_NAND: - *div = 4; // set by hardware - ret = ALT_E_SUCCESS; - break; + ///// - default: - break; - } - } - return ret; -} + // Other clock dividers + case ALT_CLK_L3_MP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2) + { + *div = temp + 1; + } + else + { + status = ALT_E_ERROR; + } + break; + case ALT_CLK_L3_SP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2) + { + *div = temp + 1; + } + else + { + status = ALT_E_ERROR; + } + // note that this value does not include the additional effect + // of the L3_MP divider that is upchain from this one + break; -/****************************************************************************************/ + case ALT_CLK_L4_MP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; -/****************************************************************************************/ + case ALT_CLK_L4_SP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_DBG_AT: + temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_DBG: + temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + // note that this value does not include the value of the upstream dbg_at_clk divder + break; + + case ALT_CLK_DBG_TRACE: + temp = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_USB_MP: + temp = ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_SPI_M: + temp = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_CAN0: + temp = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_CAN1: + temp = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_GPIO_DB: + temp = ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR)); + *div = temp + 1; + break; + + case ALT_CLK_MPU_PERIPH: + *div = 4; // set by hardware + break; + + case ALT_CLK_MPU_L2_RAM: + *div = 2; // set by hardware + break; + + case ALT_CLK_NAND: + *div = 4; // set by hardware + break; + + default: + status = ALT_E_BAD_ARG; + break; + } + + return status; +} + +///// #define ALT_CLK_WITHIN_FREQ_LIMITS_TEST_MODE false // used for testing writes to the the full range of counters without @@ -2811,143 +2923,156 @@ ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, uint32_t* div) static ALT_STATUS_CODE alt_clk_within_freq_limits(ALT_CLK_t clk, uint32_t div) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t numer; - uint32_t hilimit; - uint32_t lolimit; - #if ALT_CLK_WITHIN_FREQ_LIMITS_TEST_MODE return ALT_E_TRUE; -#endif +#else - if (div != 0) + if (div == 0) { - if (!ALT_CLK_WITHIN_FREQ_LIMITS_TEST_MODE) - { - // Normal mode - do the frequency check + return ALT_E_BAD_ARG; + } - /* Counters of the Main PLL */ - if (clk == ALT_CLK_MAIN_PLL_C0) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C0; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C1) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C1; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C2) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C2; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C3) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C3; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C4) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C4; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C5) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C5; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t numer = 0; + uint32_t hilimit; + uint32_t lolimit; - /* Counters of the Peripheral PLL */ - else if (clk == ALT_CLK_PERIPHERAL_PLL_C0) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C0; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C1) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C1; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C2) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C2; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C3) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C3; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C4) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C4; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C5) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C5; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } + switch (clk) + { + // Counters of the Main PLL + case ALT_CLK_MAIN_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C0; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C1; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C2; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C3: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C3; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C4: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C4; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; - /* Counters of the SDRAM PLL */ - else if (clk == ALT_CLK_SDRAM_PLL_C0) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C0; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else if (clk == ALT_CLK_SDRAM_PLL_C1) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C1; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else if (clk == ALT_CLK_SDRAM_PLL_C2) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C2; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else if (clk == ALT_CLK_SDRAM_PLL_C5) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C5; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else { return ret; } + // Counters of the Peripheral PLL + case ALT_CLK_PERIPHERAL_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C0; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C1; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C2; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C3; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C4; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; - numer = numer / div; - if ((numer <= hilimit) && (numer >= lolimit)) - { - ret = ALT_E_TRUE; - } - else { ret = ALT_E_FALSE; } + // Counters of the SDRAM PLL + case ALT_CLK_SDRAM_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C0; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C1; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C2; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + + default: + status = ALT_E_BAD_ARG; + break; + } + + if (status == ALT_E_SUCCESS) + { + numer = numer / div; + if ((numer <= hilimit) && (numer >= lolimit)) + { + status = ALT_E_TRUE; + } + else + { + status = ALT_E_FALSE; } } - return ret; -} + return status; +#endif +} -/****************************************************************************************/ -/* alt_clk_divider_set() sets the divider value for the specified clock. */ -/* */ -/* See pages 38, 44, 45, and 46 of the HPS-Clocking NPP for a map of the */ -/* HPS clocking architecture and hierarchy of connections. */ -/****************************************************************************************/ +static bool alt_clkmgr_is_val_modulo_n(uint32_t div, uint32_t mod) +{ + if (mod == 1) + { + return true; + } + else if (mod == 2) + { + return (div & 0x1) == 0; + } + else if (mod == 4) + { + return (div & 0x3) == 0; + } + else + { + return (div % mod) == 0; + } +} +// +// alt_clk_divider_set() sets the divider value for the specified clock. +// +// See pages 38, 44, 45, and 46 of the HPS-Clocking NPP for a map of the +// HPS clocking architecture and hierarchy of connections. +// ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk, uint32_t div) { ALT_STATUS_CODE ret = ALT_E_BAD_ARG; @@ -2957,1974 +3082,2473 @@ ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk, uint32_t div) bool restore_1 = false; bool restore_2 = false; - switch (clk) + switch (clk) { - /* ------------ Main PLL outputs ------------ */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MPU: - if ((div <= ((ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK << 1) + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C0, div) == ALT_E_TRUE)) - { - wrval = (div >> 1) + 1; // adjust for the automatic divide-by-two internal counter on C0 - // HW managed clock, change by writing to the external counter, no need to gate clock - // or match phase or wait for transistion time. No other field in the register to mask off either. - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C0, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_L3_MAIN: - if ((div <= ((ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK << 2) + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C1, div) == ALT_E_TRUE)) - { - // HW managed clock, change by writing to the external counter, no need to gate clock - // or match phase or wait for transistion time. No other field in the register to mask off either. - - wrval = (div >> 2) + 1; // adjust for the automatic divide-by-four internal counter on C1 -#if ALT_PREVENT_GLITCH_CHGC1 - // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing - // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); - temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - - if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) - { - restore_0 = true; - } - if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) - { - restore_1 = true; - } - temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } - if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } - - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - // wait a bit before reenabling the L4MP and L4SP clocks - if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } + // Main PLL outputs + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MPU: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)) + 1); + if ( (div <= ((ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C0, div) == ALT_E_TRUE) ) + { + wrval = (div / prediv) - 1; -#else - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, - div >> 2, // adjust for the automatic divide-by-four internal counter on C1 - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); -#endif + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. + alt_write_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, wrval); ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_DBG_BASE: - if ((div <= ((ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK << 2) + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C2, div) == ALT_E_TRUE)) - { - wrval = (div >> 2) + 1; // adjust for the automatic divide-by-four internal counter on C2 - // HW managed clock, change by writing to the external counter, no need to gate clock - // or match phase or wait for transistion time. No other field in the register to mask off either. - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C3: - // The rest of the PLL outputs do not have external counters, but - // their internal counters are programmable rather than fixed - if ((div <= (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C3, div) == ALT_E_TRUE)) + } + else { - if (ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)) - == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - // if the main_qspi_clk input is selected for the qspi_clk - { - restore_0 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; - if (restore_0) // AND if the QSPI clock is enabled - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); - // gate off the QSPI clock - } - - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C3, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - // if the QSPI clock was gated on (enabled) before, return it to that state - } - ret = ALT_E_SUCCESS; - } + ret = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } - break; + } + break; - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_NAND_SDMMC: - if ((div <= (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C4, div) == ALT_E_TRUE)) + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_L3_MAIN: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)) + 1); + + if ( (div <= ((ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C1, div) == ALT_E_TRUE) ) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); - temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. - // do we need to gate off the SDMMC clock ? - if (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) - { - if (temp1 & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK) { restore_0 = true; } - } + wrval = (div / prediv) - 1; - // do we need to gate off the NAND clock and/or the NANDX clock? - if (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) - { - if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK) { restore_1 = true; } - if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK) { restore_2 = true; } - } +#if ALT_PREVENT_GLITCH_CHGC1 + // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing + // bypass state, then gate clock back on. FogBugz #63778 + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - temp = temp1; - if (restore_1 && restore_2) + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) { - temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - // gate nand_clk off at least 8 MPU clock cycles before before nand_x_clk + restore_0 = true; } - - if (restore_0 || restore_1) + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) { - if (restore_0) { temp &= ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; } - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - // gate off sdmmc_clk and/or nand_x_clk + restore_1 = true; } + temp = temp1; + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C4, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, wrval); - if (restore_0 || restore_1) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK); - // if the NANDX and/or SDMMC clock was gated on (enabled) before, return it to that state - if (restore_1 && restore_2) - { - // wait at least 8 clock cycles to turn the nand_clk on - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); - } - } + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + // wait a bit before reenabling the L4MP and L4SP clocks + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } +#else + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, wrval); +#endif ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C5: - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - if ((div <= (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C5, div) == ALT_E_TRUE)) + else { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - restore_0 = ((temp & ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK) - || (temp & ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK)); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & (ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK - & ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK)); // clear 'em both - } + ret = ALT_E_ARG_RANGE; + } + } + break; - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C5, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_DBG_BASE: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_DBGATCLK_ADDR)) + 1); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if ( (div <= ((ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C2, div) == ALT_E_TRUE) ) + { + wrval = (div / prediv) - 1; + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, wrval); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; - - - /* ------------ Peripheral PLL outputs ------------ */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_EMAC0: - if ((div <= (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C0, div) == ALT_E_TRUE)) + else { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK; + ret = ALT_E_ARG_RANGE; + } + } + break; - if (restore_0) + case ALT_CLK_MAIN_PLL_C3: + // The rest of the PLL outputs do not have external counters, but + // their internal counters are programmable rather than fixed + if ( (div <= (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C3, div) == ALT_E_TRUE) ) + { + // if the main_qspi_clk input is selected for the qspi_clk + if (ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)) == + ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + restore_0 = (temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; + if (restore_0) // AND if the QSPI clock is currently enabled { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); + // gate off the QSPI clock } - // now write the new divisor ratio wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C0, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + // the rest are software-managed clocks and require a reset sequence to write to + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // if the QSPI clock was gated on (enabled) before, return it to that state } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_EMAC1: - if ((div <= (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C1, div) == ALT_E_TRUE)) - { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK; + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_NAND_SDMMC: + if ( (div <= (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C4, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK); - } - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // do we need to gate off the SDMMC clock ? + if (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + if (temp1 & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK) { restore_0 = true; } } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_PERIPHERAL_PLL_C2: - if ((div <= (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C2, div) == ALT_E_TRUE)) + // do we need to gate off the NAND clock and/or the NANDX clock? + if (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) { - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - // if qspi source is set to Peripheral PLL C2 - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - // and if qspi_clk is enabled - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); - // gate it off - } - } - - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK) { restore_1 = true; } + if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK) { restore_2 = true; } + } - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - // if the clock was gated on (enabled) before, return it to that state - } - ret = ALT_E_SUCCESS; + temp = temp1; + if (restore_1 && restore_2) + { + temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_clk off at least 8 MPU clock cycles before before nand_x_clk } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_PERIPHERAL_PLL_C3: - if ((div <= (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C3, div) == ALT_E_TRUE)) + if (restore_0 || restore_1) { - // first, are the clock MUX input selections currently set to use the clock we want to change? - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); - restore_0 = (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK); - restore_1 = restore_2 = (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK); - - // now AND those with the current state of the three gate enables - // to get the clocks which must be gated off and then back on - temp1 = temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = restore_0 && (temp & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); - restore_1 = restore_1 && (temp & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - restore_2 = restore_2 && (temp & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - - // gate off the clocks that depend on the clock divider that we want to change - if (restore_2) { temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; } if (restore_0) { temp &= ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; } alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // gate off sdmmc_clk and/or nand_x_clk + } - // the NAND clock must be gated off before the NANDX clock, - if (restore_1) - { - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C3, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C4, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - // NAND clock and NAND_X clock cannot be written together, must be a set sequence with a delay + if (restore_0 || restore_1) + { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK); - if (restore_2) + // if the NANDX and/or SDMMC clock was gated on (enabled) before, return it to that state + if (restore_1 && restore_2) { - // the NANDX clock must be gated on before the NAND clock. - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK ); + // wait at least 8 clock cycles to turn the nand_clk on + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); } - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_PERIPHERAL_PLL_C4: - if ((div <= (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C4, div) == ALT_E_TRUE)) + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + if ( (div <= (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C5, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + restore_0 = ((temp & ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK) || + (temp & ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK)); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & (ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK & + ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK)); // clear both + } + + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + + if (restore_0) { - // look at the L4 set of clock gates first - temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); - restore_0 = (ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL); - restore_1 = (ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL); - temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = restore_0 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); - restore_1 = restore_1 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); - - // if the l4_sp and l4_mp clocks are not set to use the periph_base_clk - // from the Peripheral PLL C4 clock divider output, or if they are - // not currently gated on, don't change their gates - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - // now look at the C4 direct set of clock gates - // first, create a mask of the C4 direct set of clock gate enables - temp = (ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); + ///// - // gate off all the C4 Direct set of clocks - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ~temp); + // Peripheral PLL outputs + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_EMAC0: + if ( (div <= (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C0, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK; - // change the clock divider ratio - the reason we're here - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C4, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - - // gate the affected clocks that were on before back on - both sets of gates - temp = (restore_0) ? ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK : 0; - if (restore_1) { temp |= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK; } - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); - ret = ALT_E_SUCCESS; + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK); } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_PERIPHERAL_PLL_C5: - case ALT_CLK_H2F_USER1: - if ((div <= (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C5, div) == ALT_E_TRUE)) + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C0, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_EMAC1: + if ( (div <= (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C1, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK; + + if (restore_0) { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK); + } + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C1, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C2: + if ( (div <= (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C2, div) == ALT_E_TRUE) ) + { + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + // if qspi source is set to Peripheral PLL C2 temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK; + // and if qspi_clk is enabled + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; if (restore_0) { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); + // gate it off } + } - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C5, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - if (restore_0) { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); } - ret = ALT_E_SUCCESS; + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // if the clock was gated on (enabled) before, return it to that state } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + if ( (div <= (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C3, div) == ALT_E_TRUE) ) + { + // first, are the clock MUX input selections currently set to use the clock we want to change? + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + restore_0 = (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK); + restore_1 = restore_2 = (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK); + + // now AND those with the current state of the three gate enables + // to get the clocks which must be gated off and then back on + temp1 = temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = restore_0 && (temp & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + restore_1 = restore_1 && (temp & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + restore_2 = restore_2 && (temp & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + + // gate off the clocks that depend on the clock divider that we want to change + if (restore_2) { temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK; } + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + + // the NAND clock must be gated off before the NANDX clock, + if (restore_1) + { + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } - /* ------------ SDRAM PLL outputs ------------ */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_DDR_DQS: - if ((div <= (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C0, div) == ALT_E_TRUE)) - { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK); - restore_0 = true; - } - - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C0, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_DDR_2X_DQS: - if ((div <= (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C1, div) == ALT_E_TRUE)) + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + + // NAND clock and NAND_X clock cannot be written together, must be a set sequence with a delay + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK); + if (restore_2) { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK); - restore_0 = true; - } + // the NANDX clock must be gated on before the NAND clock. + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK ); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + case ALT_CLK_PERIPHERAL_PLL_C4: + if ( (div <= (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C4, div) == ALT_E_TRUE) ) + { + // look at the L4 set of clock gates first + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + restore_0 = (ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL); + restore_1 = (ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL); + temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = restore_0 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + restore_1 = restore_1 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + + // if the l4_sp and l4_mp clocks are not set to use the periph_base_clk + // from the Peripheral PLL C4 clock divider output, or if they are + // not currently gated on, don't change their gates + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + + // now look at the C4 direct set of clock gates + // first, create a mask of the C4 direct set of clock gate enables + temp = ( ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK ); + + // gate off all the C4 Direct set of clocks + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ~temp); + + // change the clock divider ratio - the reason we're here + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C4, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + + // gate the affected clocks that were on before back on - both sets of gates + temp = (restore_0) ? ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK : 0; + if (restore_1) { temp |= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK; } + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_H2F_USER1: + if ( (div <= (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C5, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK; + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK); } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_DDR_DQ: - if ((div <= (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C2, div) == ALT_E_TRUE)) + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + if (restore_0) { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + ///// + + // SDRAM PLL outputs + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C0, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK) { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK); - restore_0 = true; - } + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK); + restore_0 = true; + } - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C0, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_SDRAM_PLL_C5: - case ALT_CLK_H2F_USER2: - if ((div <= (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C5, div) == ALT_E_TRUE)) + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C1, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK) { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK); - restore_0 = true; - } + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK); + restore_0 = true; + } + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C1, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C5, - ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C2, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - /* ------------ Other clock dividers ------------ */ - case ALT_CLK_L3_MP: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2; } + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + if ( (div <= (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C5, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK); + restore_0 = true; + } - if (wrval != UINT32_MAX) + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + ///// - case ALT_CLK_L3_SP: - // note that the L3MP divider is upstream from the L3SP divider - // and any changes to the former will affect the output of both - if ( div <= (ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 + 1)) - { - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2; } - - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB); - // no clock gate to close and reopen - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_L4_MP: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16; } - - if (wrval != UINT32_MAX) + // Other clock dividers + case ALT_CLK_L3_MP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_L4_SP: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16; } + case ALT_CLK_L3_SP: + // note that the L3MP divider is upstream from the L3SP divider + // and any changes to the former will affect the output of both + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB); + // no clock gate to close and reopen + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_L4_MP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_DBG_AT: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4; } + case ALT_CLK_L4_SP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_DBG: - if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4; } - else + case ALT_CLK_DBG_AT: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK) { - ret = ALT_E_ARG_RANGE; - break; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK); + restore_0 = true; } + alt_replbits_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_DBG: + if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4; } + if (wrval != UINT32_MAX) + { temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if (temp & ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK) { - // if clock is currently on, gate it off + // if clock is currently on, gate it off alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK); restore_0 = true; } alt_replbits_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK, - wrval << (ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB - 1)); - // account for the fact that the divisor ratios are 2x the value + wrval << (ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB - 1)); + // account for the fact that the divisor ratios are 2x the value alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } ret = ALT_E_SUCCESS; - break; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_DBG_TRACE: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16; } + case ALT_CLK_DBG_TRACE: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_USB_MP: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16; } + case ALT_CLK_USB_MP: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_SPI_M: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16; } + case ALT_CLK_SPI_M: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_CAN0: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16; } + case ALT_CLK_CAN0: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_CAN1: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16; } + case ALT_CLK_CAN1: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK) + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_GPIO_DB: // GPIO debounce clock + if (div <= ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK); + restore_0 = true; + } + wrval = div - 1; + alt_replbits_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_MAIN_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + // get the QSPI clock source + restore_0 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; + // and the current enable state + wrval = div - 1; + + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { // if the main_qspi_clk (Main PLL C3 Ouput) input is selected + if (div <= ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK) + { + if (restore_0) { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + } // gate off the QSPI clock + + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + // if the QSPI clock was gated on (enabled) before, return it to that state } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_GPIO_DB: // GPIO debounce clock - if ( div <= ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK) + else { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK) + ret = ALT_E_ARG_RANGE; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + if (div <= ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK) + { + if (restore_0) { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK); - restore_0 = true; - } - wrval = div - 1; - alt_replbits_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + } // gate off the QSPI clock + + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + // if the QSPI clock was gated on (enabled) before, return it to that state } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; + else + { + ret = ALT_E_ARG_RANGE; + } + } + break; - case ALT_CLK_MAIN_QSPI: - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - // get the QSPI clock source - restore_0 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; - // and the current enable state - wrval = div - 1; - - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - { // if the main_qspi_clk (Main PLL C3 Ouput) input is selected - if (div <= ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK) - { - if (restore_0) - { - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - } // gate off the QSPI clock - - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C3, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - // if the QSPI clock was gated on (enabled) before, return it to that state - } - } - else { ret = ALT_E_ARG_RANGE; } - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - if (div <= ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK) - { - if (restore_0) - { - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - } // gate off the QSPI clock - - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - // if the QSPI clock was gated on (enabled) before, return it to that state - } - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - } - break; + ///// - default: - break; + default: + ret = ALT_E_BAD_ARG; + break; + } - } // end of switch-case construct return ret; -} // end of alt_clk_divider_set() - Hallelujah ! - - -/****************************************************************************************/ -/* alt_clk_freq_get() returns the output frequency of the specified clock. */ -/****************************************************************************************/ +} +// +// alt_clk_freq_get() returns the output frequency of the specified clock. +// ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, alt_freq_t* freq) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; - uint64_t numer = 0; - uint64_t denom = 1; + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + uint32_t temp = 0; + uint64_t numer = 0; + uint64_t denom = 1; + if (freq == NULL) + { + return ret; + } - if (freq != NULL) + switch (clk) { - switch (clk) + // External Inputs + case ALT_CLK_IN_PIN_OSC1: + case ALT_CLK_OSC1: + numer = alt_ext_clk_paramblok.clkosc1.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_IN_PIN_OSC2: + numer = alt_ext_clk_paramblok.clkosc2.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_F2H_PERIPH_REF: + numer = alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_F2H_SDRAM_REF: + numer = alt_ext_clk_paramblok.sdram.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + ///// + + // PLLs + case ALT_CLK_MAIN_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) { - /* External Inputs */ - case ALT_CLK_IN_PIN_OSC1: - case ALT_CLK_OSC1: - numer = alt_ext_clk_paramblok.clkosc1.freqcur; - // denom = 1 by default - ret = ALT_E_SUCCESS; - break; + temp = alt_ext_clk_paramblok.clkosc1.freqcur; + ret = ALT_E_SUCCESS; + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; - case ALT_CLK_IN_PIN_OSC2: - numer = alt_ext_clk_paramblok.clkosc2.freqcur; - // denom = 1 by default + case ALT_CLK_PERIPHERAL_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) + { + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) + { + temp = alt_ext_clk_paramblok.clkosc1.freqcur; ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_F2H_PERIPH_REF: - numer = alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 by default + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) + { + temp = alt_ext_clk_paramblok.clkosc2.freqcur; ret = ALT_E_SUCCESS; - break; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) + { + temp = alt_ext_clk_paramblok.periph.freqcur; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ERROR; + } + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; - case ALT_CLK_F2H_SDRAM_REF: - numer = alt_ext_clk_paramblok.sdram.freqcur; - // denom = 1 by default + case ALT_CLK_SDRAM_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) + { + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + temp = alt_ext_clk_paramblok.clkosc1.freqcur; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + temp = alt_ext_clk_paramblok.clkosc2.freqcur; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + temp = alt_ext_clk_paramblok.sdram.freqcur; ret = ALT_E_SUCCESS; - break; + } + else + { + ret = ALT_E_ERROR; + } + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; - /* PLLs */ - case ALT_CLK_MAIN_PLL: - if (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) - { - temp = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = ALT_E_SUCCESS; - } - else - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - } - numer = (uint64_t) temp; - // denom = 1 by default - break; + ///// - case ALT_CLK_PERIPHERAL_PLL: - if (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) - { - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { - temp = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { - temp = alt_ext_clk_paramblok.clkosc2.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { - temp = alt_ext_clk_paramblok.periph.freqcur; - ret = ALT_E_SUCCESS; - } - } - else - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - } - numer = (uint64_t) temp; - // denom = 1 by default - break; + // Main Clock Group + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(clk, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_SDRAM_PLL: - if (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) - { - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { - temp = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { - temp = alt_ext_clk_paramblok.clkosc2.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { - temp = alt_ext_clk_paramblok.sdram.freqcur; - ret = ALT_E_SUCCESS; - } - } - else - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - } - numer = (uint64_t) temp; - // denom = 1 by default - break; - - /* Main Clock Group */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_MAIN_PLL_C3: - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_PLL_C5: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(clk, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MPU: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_MPU: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MPU_PERIPH: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MPU_PERIPH, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_MPU_PERIPH: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MPU_PERIPH, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_MPU_L2_RAM: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MPU_L2_RAM, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_MPU_L2_RAM: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MPU_L2_RAM, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_L4_MAIN: - case ALT_CLK_L3_MAIN: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_L3_MP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_L3_MP: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_L3_SP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = denom * (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_SP, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_L3_SP: + case ALT_CLK_L4_MP: + ret = alt_clk_divider_get(ALT_CLK_L4_MP, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + temp = ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); + if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) + { ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) + if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = denom * (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_L3_SP, &temp); - denom = denom * (uint64_t) temp; - } - } + denom = denom * (uint64_t) temp; // no real harm if temp is garbage data } - break; - - case ALT_CLK_L4_MP: - ret = alt_clk_divider_get(ALT_CLK_L4_MP, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - temp = ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); - if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - denom = denom * (uint64_t) temp; // no real harm if temp is garbage data - } - } - else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - denom = denom * (uint64_t) temp; - } - } - } - break; - - case ALT_CLK_L4_SP: - ret = alt_clk_divider_get(ALT_CLK_L4_SP, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - temp = ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); - if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - denom = denom * (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL) // periph_base_clk - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - denom = denom * (uint64_t) temp; - } - } - } - break; - - case ALT_CLK_DBG_BASE: - case ALT_CLK_DBG_TIMER: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + } + else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + denom = denom * (uint64_t) temp; } - break; + } + } + break; - case ALT_CLK_DBG_AT: + case ALT_CLK_L4_SP: + ret = alt_clk_divider_get(ALT_CLK_L4_SP, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + temp = ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); + if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) + { ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); - denom = denom * (uint64_t) temp; - } + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + denom = denom * (uint64_t) temp; } - break; - - case ALT_CLK_DBG: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + } + else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL) // periph_base_clk + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = denom * (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG, &temp); - denom = denom * (uint64_t) temp; - } - } + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + denom = denom * (uint64_t) temp; } - break; + } + } + break; - case ALT_CLK_DBG_TRACE: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG_TRACE, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_TIMER: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_MAIN_QSPI: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_DBG_AT: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_MAIN_NAND_SDMMC: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_DBG: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = denom * (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C5, &temp); - denom = (uint64_t) temp; - } - break; - - /* Peripheral Clock Group */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_PERIPHERAL_PLL_C2: - case ALT_CLK_PERIPHERAL_PLL_C3: - case ALT_CLK_PERIPHERAL_PLL_C4: - case ALT_CLK_PERIPHERAL_PLL_C5: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(clk, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_DBG_TRACE: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_TRACE, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_EMAC0: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C0, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MAIN_QSPI: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_EMAC1: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C1, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MAIN_NAND_SDMMC: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_USB_MP: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_USB_MP, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_SPI_M: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SPI_M, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + ///// - case ALT_CLK_CAN0: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_CAN0, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + // Peripheral Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(clk, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_CAN1: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_CAN1, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_EMAC0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_GPIO_DB: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_GPIO_DB, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_EMAC1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_H2F_USER1: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C5, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_USB_MP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_USB_MP, &temp); + denom = denom * (uint64_t) temp; + } + } + break; - /* Clocks That Can Switch Between Different Clock Groups */ - case ALT_CLK_SDMMC: - temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) - { - numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 by default - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); - denom = (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); - denom = (uint64_t) temp; - } - } - break; + case ALT_CLK_SPI_M: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SPI_M, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_NAND: - denom = 4; // the absence of a break statement here is not a mistake - case ALT_CLK_NAND_X: - temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) - { - numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 or 4 by default; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); - denom = denom * (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_CAN0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_CAN0, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_QSPI: - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) - { - numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 by default; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); - denom = (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C2, &temp); - denom = (uint64_t) temp; - } - } - break; + case ALT_CLK_CAN1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_CAN1, &temp); + denom = denom * (uint64_t) temp; + } + break; - /* SDRAM Clock Group */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_DDR_DQS: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C0, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_GPIO_DB: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_GPIO_DB, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_DDR_2X_DQS: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C1, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_H2F_USER1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_DDR_DQ: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C2, &temp); - denom = (uint64_t) temp; - } - break; + /* Clocks That Can Switch Between Different Clock Groups */ + case ALT_CLK_SDMMC: + temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); + denom = (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; - case ALT_CLK_SDRAM_PLL_C5: - case ALT_CLK_H2F_USER2: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C5, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_NAND: + denom = 4; + // the absence of a break statement here is not a mistake + case ALT_CLK_NAND_X: + temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 or 4 by default; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = denom * (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); + denom = denom * (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; - default: - break; + case ALT_CLK_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); + denom = (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C2, &temp); + denom = (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; - } // end of switch-case construct + ///// + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); if (ret == ALT_E_SUCCESS) { - // will not get here if none of above cases match - if (denom > 0) + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C2, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; + + default: + ret = ALT_E_BAD_ARG; + break; + + } // end of switch-case construct + + if (ret == ALT_E_SUCCESS) + { + // will not get here if none of above cases match + if (denom > 0) + { + numer /= denom; + if (numer <= UINT32_MAX) { - numer /= denom; - if (numer <= UINT32_MAX) - { - *freq = (uint32_t) numer; - } - else { ret = ALT_E_ERROR; } + *freq = (uint32_t) numer; + } + else + { + ret = ALT_E_ERROR; } - else { ret = ALT_E_ERROR; } + } + else + { + ret = ALT_E_ERROR; } } + return ret; } - -/****************************************************************************************/ -/* alt_clk_irq_disable() disables one or more of the lock status conditions as */ -/* contributors to the clkmgr_IRQ interrupt signal state. */ -/****************************************************************************************/ - +// +// alt_clk_irq_disable() disables one or more of the lock status conditions as +// contributors to the clkmgr_IRQ interrupt signal state. +// ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - if (!(lock_stat_mask & ALT_CLK_MGR_PLL_LOCK_BITS)) { alt_clrbits_word(ALT_CLKMGR_INTREN_ADDR, lock_stat_mask); - ret = ALT_E_SUCCESS; + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; } - return ret; } - -/****************************************************************************************/ -/* alt_clk_irq_enable() enables one or more of the lock status conditions as */ -/* contributors to the clkmgr_IRQ interrupt signal state. */ -/****************************************************************************************/ - - +// +// alt_clk_irq_enable() enables one or more of the lock status conditions as +// contributors to the clkmgr_IRQ interrupt signal state. +// ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - if (!(lock_stat_mask & ALT_CLK_MGR_PLL_LOCK_BITS)) { alt_setbits_word(ALT_CLKMGR_INTREN_ADDR, lock_stat_mask); - ret = ALT_E_SUCCESS; + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; } - return ret; } +///// -/****************************************************************************************/ -/* alt_clk_group_cfg_raw_get() gets the raw configuration state of the designated */ -/* clock group. */ -/****************************************************************************************/ - +// +// alt_clk_group_cfg_raw_get() gets the raw configuration state of the designated +// clock group. +// ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, - ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg) + ALT_CLK_GROUP_RAW_CFG_t * clk_group_raw_cfg) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t *tmp; + clk_group_raw_cfg->verid = alt_read_word(ALT_SYSMGR_SILICONID1_ADDR); + clk_group_raw_cfg->siliid2 = alt_read_word(ALT_SYSMGR_SILICONID2_ADDR); + clk_group_raw_cfg->clkgrpsel = clk_group; - if (clk_group_raw_cfg != NULL) + if (clk_group == ALT_MAIN_PLL_CLK_GRP) { - alt_write_word(&clk_group_raw_cfg->verid, alt_read_word(ALT_SYSMGR_SILICONID1_ADDR)); - alt_write_word(&clk_group_raw_cfg->siliid2, alt_read_word(ALT_SYSMGR_SILICONID2_ADDR)); - alt_indwrite_word(&clk_group_raw_cfg->clkgrpsel, tmp, clk_group); + // Main PLL VCO register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - if (clk_group == ALT_MAIN_PLL_CLK_GRP) - { - /* Main PLL VCO register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.vco, uint32_t); // compile-time macro that - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.vco, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR)); + // Main PLL Misc register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.misc = alt_read_word(ALT_CLKMGR_MAINPLL_MISC_ADDR); - /* Main PLL Misc register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.misc, uint32_t); // disappears if size is OK - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.misc, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MISC_ADDR)); + // Main PLL C0-C5 Counter registers + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mpuclk = alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations - /* Main PLL C0-C5 Counter registers */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mpuclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mpuclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)); - // doing these as 32-bit reads and writes avoids unnecessary masking operations + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgatclk = alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainqspiclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainnandsdmmcclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.cfgs2fuser0clk = alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mainclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mainclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)); + // Main PLL Enable register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.en = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.dbgatclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.dbgatclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)); + // Main PLL Maindiv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.maindiv = alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mainqspiclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mainqspiclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR)); + // Main PLL Debugdiv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgdiv = alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mainnandsdmmcclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mainnandsdmmcclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR)); + // Main PLL Tracediv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.tracediv = alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.cfgs2fuser0clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.cfgs2fuser0clk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR)); + // Main PLL L4 Source register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.l4src = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); - /* Main PLL Enable register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.en, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.en, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)); + // Main PLL Status register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_MAINPLL_STAT_ADDR); + // clkgrp.mainpllgrp.stat.outresetack is defined in the ALT_CLKMGR_MAINPLL_STAT_s declaration + // as a const but alt_indwrite_word() overrides that restriction. - /* Main PLL Maindiv register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.maindiv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.maindiv, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + // padding ... + clk_group_raw_cfg->clkgrp.mainpllgrp.raw._pad_0x38_0x40[0] = 0; + clk_group_raw_cfg->clkgrp.mainpllgrp.raw._pad_0x38_0x40[1] = 0; - /* Main PLL Debugdiv register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.dbgdiv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.dbgdiv, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); + return ALT_E_SUCCESS; + } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) + { + // Peripheral PLL VCO register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - /* Main PLL Tracediv register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.tracediv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.tracediv, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR)); + // Peripheral PLL Misc register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.misc = alt_read_word(ALT_CLKMGR_PERPLL_MISC_ADDR); - /* Main PLL L4 Source register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.l4src, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.l4src, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); + // Peripheral PLL C0-C5 Counters + clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac0clk = alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations - /* Main PLL Status register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.stat, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.stat, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_STAT_ADDR)); - // clkgrp.mainpllgrp.stat.outresetack is defined in the ALT_CLKMGR_MAINPLL_STAT_s declaration - // as a const but alt_indwrite_word() overrides that restriction. + clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac1clk = alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.perqspiclk = alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.pernandsdmmcclk = alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.perbaseclk = alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.s2fuser1clk = alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR); - /* padding....... */ - clk_group_raw_cfg->clkgrp.mainpllgrp._pad_0x38_0x40[0] = 0; - clk_group_raw_cfg->clkgrp.mainpllgrp._pad_0x38_0x40[1] = 0; - ret = ALT_E_SUCCESS; - } + // Peripheral PLL Enable register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.en = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) - { - /* Peripheral PLL VCO register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.vco, uint32_t); // compile-time macro - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.vco, tmp, alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + // Peripheral PLL Divider register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.div = alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR); - /* Peripheral PLL Misc register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.misc, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.misc, tmp, alt_read_word(ALT_CLKMGR_PERPLL_MISC_ADDR)); + // Peripheral PLL GPIO Divider register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.gpiodiv = alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR); - /* Peripheral PLL C0-C5 Counters */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.emac0clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.emac0clk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR)); - // doing these as 32-bit reads and writes avoids unnecessary masking operations + // Peripheral PLL Source register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.src = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.emac1clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.emac1clk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR)); + // Peripheral PLL Status register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_PERPLL_STAT_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.perqspiclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.perqspiclk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR)); + // padding ... + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[0] = 0; + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[1] = 0; + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[2] = 0; - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.pernandsdmmcclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.pernandsdmmcclk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR)); + return ALT_E_SUCCESS; + } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) + { + // SDRAM PLL VCO register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.perbaseclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.perbaseclk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR)); + // SDRAM PLL Control register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ctrl = alt_read_word(ALT_CLKMGR_SDRPLL_CTL_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.s2fuser1clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.s2fuser1clk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR)); + // SDRAM PLL C0-C2 & C5 Counters + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqsclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations - /* Peripheral PLL Enable register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.en, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.en, tmp, alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)); + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddr2xdqsclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR); + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR); + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.s2fuser2clk = alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR); - /* Peripheral PLL Divider register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.div, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.div, tmp, alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + // SDRAM PLL Enable register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.en = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - /* Peripheral PLL GPIO Divider register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.gpiodiv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.gpiodiv, tmp, alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR)); + // SDRAM PLL Status register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_SDRPLL_STAT_ADDR); - /* Peripheral PLL Source register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.src, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.src, tmp, alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} - /* Peripheral PLL Status register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.stat, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.stat, tmp, alt_read_word(ALT_CLKMGR_PERPLL_STAT_ADDR)); +// +// alt_clk_group_cfg_raw_set() sets the clock group configuration. +// +ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t * clk_group_raw_cfg) +{ + // test for matching silicon ID, but not for matching silicon revision number + if (ALT_SYSMGR_SILICONID1_ID_GET(alt_read_word(ALT_SYSMGR_SILICONID1_ADDR)) != + ALT_SYSMGR_SILICONID1_ID_GET(clk_group_raw_cfg->verid)) + { + return ALT_E_BAD_VERSION; + } - /* padding....... */ - clk_group_raw_cfg->clkgrp.perpllgrp._pad_0x34_0x40[0] = 0; - clk_group_raw_cfg->clkgrp.perpllgrp._pad_0x34_0x40[1] = 0; - clk_group_raw_cfg->clkgrp.perpllgrp._pad_0x34_0x40[2] = 0; - ret = ALT_E_SUCCESS; - } + // get the PLL ID + ALT_CLK_GRP_t clk_group = clk_group_raw_cfg->clkgrpsel; + ALT_CLK_t pll; - else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) + if (clk_group == ALT_MAIN_PLL_CLK_GRP) { pll = ALT_CLK_MAIN_PLL; } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) { pll = ALT_CLK_PERIPHERAL_PLL; } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) { pll = ALT_CLK_SDRAM_PLL; } + else + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // if the PLL isn't in bypass mode, put it in bypass mode + bool byp = false; + if (alt_clk_pll_is_bypassed(pll) == ALT_E_FALSE) + { + status = alt_clk_pll_bypass_enable(pll, false); + if (status != ALT_E_SUCCESS) { - /* SDRAM PLL VCO register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.vco, uint32_t); // compile-time macro - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.vco, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + return status; + } - /* SDRAM PLL Control register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ctrl, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ctrl, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_CTL_ADDR)); + byp = true; + } - /* SDRAM PLL C0-C2 & C5 Counters */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqsclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqsclk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); - // doing these as 32-bit reads and writes avoids unnecessary masking operations + // now write the values in the ALT_CLK_GROUP_RAW_CFG_t structure to the registers + if (clk_group == ALT_MAIN_PLL_CLK_GRP) + { + // Main PLL VCO register + alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.vco & + ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ddr2xdqsclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ddr2xdqsclk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); + // Main PLL Misc register + alt_write_word(ALT_CLKMGR_MAINPLL_MISC_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.misc); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqclk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); + // Main PLL C0-C5 Counter registers + alt_write_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mpuclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainclk); + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgatclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainqspiclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainnandsdmmcclk); + alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.cfgs2fuser0clk); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.s2fuser2clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.s2fuser2clk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); + // Main PLL Counter Enable register + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.en); - /* SDRAM PLL Enable register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.en, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.en, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR)); + // Main PLL Maindiv register + alt_write_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.maindiv); - /* SDRAM PLL Status register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.stat, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.stat, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_STAT_ADDR)); + // Main PLL Debugdiv register + alt_write_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgdiv); - ret = ALT_E_SUCCESS; - } - } - return ret; -} + // Main PLL Tracediv register + alt_write_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.tracediv); + // Main PLL L4 Source register + alt_write_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.l4src); + } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) + { + // Peripheral PLL VCO register + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.vco & + ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now + + // Peripheral PLL Misc register + alt_write_word(ALT_CLKMGR_PERPLL_MISC_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.misc); + + // Peripheral PLL C0-C5 Counters + alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac0clk); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac1clk); + alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.perqspiclk); + alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.pernandsdmmcclk); + alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.perbaseclk); + alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.s2fuser1clk); + + // Peripheral PLL Counter Enable register + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.en); + + // Peripheral PLL Divider register + alt_write_word(ALT_CLKMGR_PERPLL_DIV_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.div); + + // Peripheral PLL GPIO Divider register + alt_write_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.gpiodiv); + + // Peripheral PLL Source register + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.src); + } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) + { + // SDRAM PLL VCO register + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.vco & + ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now + + // SDRAM PLL Control register + alt_write_word(ALT_CLKMGR_SDRPLL_CTL_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ctrl); + + // SDRAM PLL C0-C2 & C5 Counters + alt_write_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqsclk); + alt_write_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddr2xdqsclk); + alt_write_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqclk); + alt_write_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.s2fuser2clk); + + // SDRAM PLL Counter Enable register + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.en); + } -/****************************************************************************************/ -/* alt_clk_group_cfg_raw_set() sets the clock group configuration. */ -/****************************************************************************************/ + // if PLL was not bypassed before, restore that state + if (byp) + { + status = alt_clk_pll_bypass_disable(pll); + } -ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg) -{ - ALT_STATUS_CODE ret = ALT_E_ERROR; - ALT_CLK_GRP_t clk_group; - ALT_CLK_t pll = ALT_CLK_UNKNOWN; - bool byp = false; - uint32_t *tmp; + return status; +} +// +// alt_clk_id_to_string() converts a clock ID to a text string. +// +ALT_STATUS_CODE alt_clk_id_to_string(ALT_CLK_t clk_id, char * output, size_t size) +{ + char * name = NULL; - if (clk_group_raw_cfg != NULL) + switch (clk_id) { - // test for matching silicon ID, but not for matching silicon revision number - if (ALT_SYSMGR_SILICONID1_ID_GET(alt_read_word(ALT_SYSMGR_SILICONID1_ADDR)) == - ALT_SYSMGR_SILICONID1_ID_GET(clk_group_raw_cfg->verid)) - { - // get the PLL ID - clk_group = clk_group_raw_cfg->clkgrpsel; - if (clk_group == ALT_MAIN_PLL_CLK_GRP) { pll = ALT_CLK_MAIN_PLL; } - else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) { pll = ALT_CLK_PERIPHERAL_PLL; } - else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) { pll = ALT_CLK_SDRAM_PLL; } - else { return ret; } - if (pll == ALT_CLK_UNKNOWN) { return ret; } - - // if the PLL isn't in bypass mode, put it in bypass mode - ret = alt_clk_pll_is_bypassed(pll); - if (ret == ALT_E_FALSE) - { - ret = alt_clk_pll_bypass_enable(pll, false); - byp = true; - } + case ALT_CLK_IN_PIN_OSC1: + name = "IN_PIN_OSC1"; + break; + case ALT_CLK_IN_PIN_OSC2: + name = "IN_PIN_OSC2"; + break; + // FPGA Clock Sources External to HPS + case ALT_CLK_F2H_PERIPH_REF: + name = "F2H_PERIPH_REF"; + break; + case ALT_CLK_F2H_SDRAM_REF: + name = "F2H_SDRAM_REF"; + break; - // now write the values in the ALT_CLK_GROUP_RAW_CFG_t structure to the registers - if (clk_group == ALT_MAIN_PLL_CLK_GRP) - { - /* Main PLL VCO register */ - tmp = (uint32_t *) &clk_group_raw_cfg->clkgrp.mainpllgrp.vco; - alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, *tmp & - (ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK)); - // the outreset and outresetall bits were probably clear when the - // state was saved, but make sure they're clear now - - /* Main PLL Misc register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_MISC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.misc); - - /* Main PLL C0-C5 Counter registers */ - alt_indread_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mpuclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mainclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.dbgatclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mainqspiclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mainnandsdmmcclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.cfgs2fuser0clk); - - /* Main PLL Counter Enable register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_EN_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.en); - /* Main PLL Maindiv register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.maindiv); - /* Main PLL Debugdiv register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.dbgdiv); - /* Main PLL Tracediv register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.tracediv); - /* Main PLL L4 Source register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.l4src); - - // remove bypass - ret = ALT_E_SUCCESS; - } + // Other Clock Sources External to HPS + case ALT_CLK_IN_PIN_JTAG: + name = "IN_PIN_JTAG"; + break; + case ALT_CLK_IN_PIN_ULPI0: + name = "IN_PIN_ULPI0"; + break; + case ALT_CLK_IN_PIN_ULPI1: + name = "IN_PIN_ULPI1"; + break; + case ALT_CLK_IN_PIN_EMAC0_RX: + name = "IN_PIN_EMAC0_RX"; + break; + case ALT_CLK_IN_PIN_EMAC1_RX: + name = "IN_PIN_EMAC1_RX"; + break; - else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) - { - /* Peripheral PLL VCO register */ - tmp = (uint32_t *) &clk_group_raw_cfg->clkgrp.perpllgrp.vco; - alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, *tmp & (ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK)); - // the outreset and outresetall bits were probably clear when the - // state was saved, but make sure they're clear now + // PLLs + case ALT_CLK_MAIN_PLL: + name = "MAIN_PLL"; + break; + case ALT_CLK_PERIPHERAL_PLL: + name = "PERIPHERAL_PLL"; + break; + case ALT_CLK_SDRAM_PLL: + name = "SDRAM_PLL"; + break; - /* Peripheral PLL Misc register */ - alt_indread_word(ALT_CLKMGR_PERPLL_MISC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.misc); + // OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived + // directly from the osc_clk_1_HPS pin + case ALT_CLK_OSC1: + name = "OSC1"; + break; - /* Peripheral PLL C0-C5 Counters */ - alt_indread_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.emac0clk); - alt_indread_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.emac1clk); - alt_indread_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.perqspiclk); - alt_indread_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.pernandsdmmcclk); - alt_indread_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.perbaseclk); - alt_indread_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.s2fuser1clk); + // Main Clock Group - The following clocks are derived from the Main PLL. + case ALT_CLK_MAIN_PLL_C0: + name = "MAIN_PLL_C0"; + break; + case ALT_CLK_MAIN_PLL_C1: + name = "MAIN_PLL_C1"; + break; + case ALT_CLK_MAIN_PLL_C2: + name = "MAIN_PLL_C2"; + break; + case ALT_CLK_MAIN_PLL_C3: + name = "MAIN_PLL_C3"; + break; + case ALT_CLK_MAIN_PLL_C4: + name = "MAIN_PLL_C4"; + break; + case ALT_CLK_MAIN_PLL_C5: + name = "MAIN_PLL_C5"; + break; + case ALT_CLK_MPU: + name = "MPU"; + break; + case ALT_CLK_MPU_L2_RAM: + name = "MPU_L2_RAM"; + break; + case ALT_CLK_MPU_PERIPH: + name = "MPU_PERIPH"; + break; + case ALT_CLK_L3_MAIN: + name = "L3_MAIN"; + break; + case ALT_CLK_L3_MP: + name = "L3_MP"; + break; + case ALT_CLK_L3_SP: + name = "L3_SP"; + break; + case ALT_CLK_L4_MAIN: + name = "L4_MAIN"; + break; + case ALT_CLK_L4_MP: + name = "L4_MP"; + break; + case ALT_CLK_L4_SP: + name = "L4_SP"; + break; + case ALT_CLK_DBG_BASE: + name = "DBG_BASE"; + break; + case ALT_CLK_DBG_AT: + name = "DBG_AT"; + break; + case ALT_CLK_DBG_TRACE: + name = "DBG_TRACE"; + break; + case ALT_CLK_DBG_TIMER: + name = "DBG_TIMER"; + break; + case ALT_CLK_DBG: + name = "DBG"; + break; + case ALT_CLK_MAIN_QSPI: + name = "MAIN_QSPI"; + break; + case ALT_CLK_MAIN_NAND_SDMMC: + name = "MAIN_NAND_SDMMC"; + break; + case ALT_CLK_CFG: + name = "CFG"; + break; + case ALT_CLK_H2F_USER0: + name = "H2F_USER0"; + break; - /* Peripheral PLL Counter Enable register */ - alt_indread_word(ALT_CLKMGR_PERPLL_EN_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.en); + // Peripherals Clock Group - The following clocks are derived from the Peripheral PLL. + case ALT_CLK_PERIPHERAL_PLL_C0: + name = "PERIPHERAL_PLL_C0"; + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + name = "PERIPHERAL_PLL_C1"; + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + name = "PERIPHERAL_PLL_C2"; + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + name = "PERIPHERAL_PLL_C3"; + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + name = "PERIPHERAL_PLL_C4"; + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + name = "PERIPHERAL_PLL_C5"; + break; + case ALT_CLK_USB_MP: + name = "USB_MP"; + break; + case ALT_CLK_SPI_M: + name = "SPI_M"; + break; + case ALT_CLK_QSPI: + name = "QSPI"; + break; + case ALT_CLK_NAND_X: + name = "NAND_X"; + break; + case ALT_CLK_NAND: + name = "NAND"; + break; + case ALT_CLK_SDMMC: + name = "SDMMC"; + break; + case ALT_CLK_EMAC0: + name = "EMAC0"; + break; + case ALT_CLK_EMAC1: + name = "EMAC1"; + break; + case ALT_CLK_CAN0: + name = "CAN0"; + break; + case ALT_CLK_CAN1: + name = "CAN1"; + break; + case ALT_CLK_GPIO_DB: + name = "GPIO_DB"; + break; + case ALT_CLK_H2F_USER1: + name = "H2F_USER1"; + break; - /* Peripheral PLL Divider register */ - alt_indread_word(ALT_CLKMGR_PERPLL_DIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.div); + // SDRAM Clock Group - The following clocks are derived from the SDRAM PLL. + case ALT_CLK_SDRAM_PLL_C0: + name = "SDRAM_PLL_C0"; + break; + case ALT_CLK_SDRAM_PLL_C1: + name = "SDRAM_PLL_C1"; + break; + case ALT_CLK_SDRAM_PLL_C2: + name = "SDRAM_PLL_C2"; + break; + case ALT_CLK_SDRAM_PLL_C3: + name = "SDRAM_PLL_C3"; + break; + case ALT_CLK_SDRAM_PLL_C4: + name = "SDRAM_PLL_C4"; + break; + case ALT_CLK_SDRAM_PLL_C5: + name = "SDRAM_PLL_C5"; + break; + case ALT_CLK_DDR_DQS: + name = "DDR_DQS"; + break; + case ALT_CLK_DDR_2X_DQS: + name = "DDR_2X_DQS"; + break; + case ALT_CLK_DDR_DQ: + name = "DDR_DQ"; + break; + case ALT_CLK_H2F_USER2: + name = "H2F_USER2"; + break; - /* Peripheral PLL GPIO Divider register */ - alt_indread_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.gpiodiv); + // Clock Output Pins + case ALT_CLK_OUT_PIN_EMAC0_TX: + name = "OUT_PIN_EMAC0_TX"; + break; + case ALT_CLK_OUT_PIN_EMAC1_TX: + name = "OUT_PIN_EMAC1_TX"; + break; + case ALT_CLK_OUT_PIN_SDMMC: + name = "OUT_PIN_SDMMC"; + break; + case ALT_CLK_OUT_PIN_I2C0_SCL: + name = "OUT_PIN_I2C0_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C1_SCL: + name = "OUT_PIN_I2C1_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C2_SCL: + name = "OUT_PIN_I2C2_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C3_SCL: + name = "OUT_PIN_I2C3_SCL"; + break; + case ALT_CLK_OUT_PIN_SPIM0: + name = "OUT_PIN_SPIM0"; + break; + case ALT_CLK_OUT_PIN_SPIM1: + name = "OUT_PIN_SPIM1"; + break; + case ALT_CLK_OUT_PIN_QSPI: + name = "OUT_PIN_QSPI"; + break; + case ALT_CLK_UNKNOWN: + name = "UNKNOWN"; + break; - /* Peripheral PLL Source register */ - alt_indread_word(ALT_CLKMGR_PERPLL_SRC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.src); + // do *not* put a 'default' statement here. Then the compiler will throw + // an error if another clock id enum is added if the corresponding + // string is not added to this function. + } - ret = ALT_E_SUCCESS; - } - else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) - { - /* SDRAM PLL VCO register */ - tmp = (uint32_t *) &clk_group_raw_cfg->clkgrp.sdrpllgrp.vco; - alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, *tmp & (ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK)); - // the outreset and outresetall bits were probably clear when the - // state was saved, but make sure they're clear now + if (name != NULL) + { + snprintf(output, size, "ALT_CLK_%s", name); + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} - /* SDRAM PLL Control register */ - alt_indread_word(ALT_CLKMGR_SDRPLL_CTL_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ctrl); - /* SDRAM PLL C0-C2 & C5 Counters */ - alt_indread_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqsclk); - alt_indread_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ddr2xdqsclk); - alt_indread_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqclk); - alt_indread_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.s2fuser2clk); +// +// alt_clk_pll_cntr_maxfreq_recalc() recalculate the maxmum frequency of the specified clock. +// +ALT_STATUS_CODE alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_t clk, ALT_PLL_CNTR_FREQMAX_t * maxfreq) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + alt_freq_t freq; - /* SDRAM PLL Counter Enable register */ - alt_indread_word(ALT_CLKMGR_SDRPLL_EN_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.en); + ret = alt_clk_freq_get(clk, &freq); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_BAD_ARG; } - } - else { ret = ALT_E_BAD_VERSION; } + if (ret == ALT_E_SUCCESS) + { + + switch (clk) + { + // Main Clock Group + case ALT_CLK_MAIN_PLL_C0: + maxfreq->MainPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C1: + maxfreq->MainPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C2: + maxfreq->MainPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C3: + maxfreq->MainPLL_C3 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C3 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C4: + maxfreq->MainPLL_C4 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C4 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C5: + maxfreq->MainPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C5 = %10d\n", (unsigned int)freq); + break; + + // Peripheral Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + maxfreq->PeriphPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + maxfreq->PeriphPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + maxfreq->PeriphPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + maxfreq->PeriphPLL_C3 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C3 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + maxfreq->PeriphPLL_C4 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C4 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + maxfreq->PeriphPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C5 = %10d\n", (unsigned int)freq); + break; + + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + maxfreq->SDRAMPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C1: + maxfreq->SDRAMPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C2: + maxfreq->SDRAMPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C5: + maxfreq->SDRAMPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C5 = %10d\n", (unsigned int)freq); + break; + default: + ret = ALT_E_BAD_ARG; + printf("bad max frequency parameter\n"); + break; + } // end of switch-case construct } - // if PLL was not bypassed before, restore that state - if (byp) { ret = alt_clk_pll_bypass_disable(pll); } return ret; } + +// +// u-boot preloader actually initialize clock manager circuitry +// +// alt_clk_clkmgr_init() attempt to fix the pll counter max frequencies, since +// thses frequencies are not known in advance until u-boot programmed clock manager. +// +ALT_STATUS_CODE alt_clk_clkmgr_init(void) +{ + ALT_STATUS_CODE ret = ALT_E_SUCCESS; + ALT_STATUS_CODE status ; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C3,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C4,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C3,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C4,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + + return ret; +} + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c index e2b0135..d5b6afa 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c @@ -35,6 +35,7 @@ #include "socal/hps.h" #include "socal/socal.h" #include "socal/alt_gpio.h" +#include "socal/alt_rstmgr.h" #include "hwlib.h" #include "alt_generalpurpose_io.h" @@ -53,6 +54,37 @@ /****************************************************************************************/ +/* alt_gpio_init() initializes the GPIO modules */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_init(void) +{ + // put GPIO modules into system manager reset if not already there + alt_gpio_uninit(); + // release GPIO modules from system reset (w/ two-instruction delay) + alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK, 0); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_uninit() uninitializes the GPIO modules */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_uninit(void) +{ + // put all GPIO modules into system manager reset + alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK, + ALT_GPIO_BITMASK); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ /* alt_gpio_port_datadir_set() sets the specified GPIO data bits to use the data */ /* direction(s) specified. 0 = input (default). 1 = output. */ /****************************************************************************************/ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 4e3b586..4093831 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -183,6 +183,10 @@ $(PROJECT_INCLUDE)/bsp/hwlib.h: hwlib/include/hwlib.h $(PROJECT_INCLUDE)/bsp/$(d $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwlib.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwlib.h +$(PROJECT_INCLUDE)/bsp/socal/alt_acpidmap.h: hwlib/include/socal/alt_acpidmap.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_acpidmap.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_acpidmap.h + $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h: hwlib/include/socal/alt_clkmgr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h From sebastian.huber at embedded-brains.de Wed Aug 27 10:36:16 2014 From: sebastian.huber at embedded-brains.de (Sebastian Huber) Date: Wed, 27 Aug 2014 10:36:16 -0000 Subject: [rtems commit] arm/lm3s3749: Add tests that do not fit. In-Reply-To: <20140827095637.B08FD70080E@git.rtems.org> References: <20140827095637.B08FD70080E@git.rtems.org> Message-ID: <53FDB494.9010504@embedded-brains.de> On 27/08/14 11:56, Chris Johns wrote: > Module: rtems > Branch: master > Commit: 614a0889b664a9309c3a966e5f0f494d4b94b62f > Changeset:http://git.rtems.org/rtems/commit/?id=614a0889b664a9309c3a966e5f0f494d4b94b62f > > Author: Chris Johns > Date: Wed Aug 27 20:04:26 2014 +1000 > > arm/lm3s3749: Add tests that do not fit. > > You need --enable-c++ for the c++ tests. I think you need --enable-c++ only for the rtems++ stuff. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.huber at embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine gesch?ftliche Mitteilung im Sinne des EHUG. From sebh at rtems.org Tue Aug 5 08:05:21 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 05 Aug 2014 03:05:21 -0500 Subject: [rtems commit] rbtree: Add and use RBTree_Compare_result Message-ID: <20140805080521.6750870008C@git.rtems.org> Module: rtems Branch: master Commit: 60fe374247eba365afb7f1a7055298af575434c7 Changeset: http://git.rtems.org/rtems/commit/?id=60fe374247eba365afb7f1a7055298af575434c7 Author: Sebastian Huber Date: Sun Aug 3 13:02:58 2014 +0200 rbtree: Add and use RBTree_Compare_result --- cpukit/posix/include/rtems/posix/keyimpl.h | 2 +- cpukit/posix/src/key.c | 4 +- cpukit/sapi/include/rtems/rbheap.h | 1 - cpukit/sapi/include/rtems/rbtree.h | 9 ++- cpukit/sapi/src/rbheap.c | 72 +++++++++++--------- cpukit/score/include/rtems/score/rbtree.h | 11 +++- cpukit/score/include/rtems/score/rbtreeimpl.h | 8 ++- .../score/include/rtems/score/scheduleredfimpl.h | 2 +- cpukit/score/include/rtems/score/threadqimpl.h | 2 +- cpukit/score/src/rbtreefind.c | 4 +- cpukit/score/src/rbtreeinsert.c | 13 +++- cpukit/score/src/scheduleredf.c | 2 +- cpukit/score/src/threadq.c | 2 +- testsuites/libtests/rbheap01/init.c | 17 ----- testsuites/sptests/sprbtree01/init.c | 2 +- 15 files changed, 83 insertions(+), 68 deletions(-) diff --git a/cpukit/posix/include/rtems/posix/keyimpl.h b/cpukit/posix/include/rtems/posix/keyimpl.h index aff9749..ded030d 100644 --- a/cpukit/posix/include/rtems/posix/keyimpl.h +++ b/cpukit/posix/include/rtems/posix/keyimpl.h @@ -64,7 +64,7 @@ void _POSIX_Key_Manager_initialization(void); * * This routine compares the rbtree node */ -int _POSIX_Keys_Key_value_compare( +RBTree_Compare_result _POSIX_Keys_Key_value_compare( const RBTree_Node *node1, const RBTree_Node *node2 ); diff --git a/cpukit/posix/src/key.c b/cpukit/posix/src/key.c index e231299..67c6e27 100644 --- a/cpukit/posix/src/key.c +++ b/cpukit/posix/src/key.c @@ -44,7 +44,7 @@ RBTREE_DEFINE_EMPTY( _POSIX_Keys_Key_value_lookup_tree ); * impossible */ -int _POSIX_Keys_Key_value_compare( +RBTree_Compare_result _POSIX_Keys_Key_value_compare( const RBTree_Node *node1, const RBTree_Node *node2 ) @@ -52,7 +52,7 @@ int _POSIX_Keys_Key_value_compare( POSIX_Keys_Key_value_pair *n1; POSIX_Keys_Key_value_pair *n2; Objects_Id thread_id1, thread_id2; - int diff; + RBTree_Compare_result diff; n1 = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node1 ); n2 = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node2 ); diff --git a/cpukit/sapi/include/rtems/rbheap.h b/cpukit/sapi/include/rtems/rbheap.h index 0848b69..c008721 100644 --- a/cpukit/sapi/include/rtems/rbheap.h +++ b/cpukit/sapi/include/rtems/rbheap.h @@ -154,7 +154,6 @@ struct rtems_rbheap_control { * @param[in] handler_arg The handler argument. * * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_INVALID_NUMBER The alignment is not positive. * @retval RTEMS_INVALID_ADDRESS The memory area is invalid. * @retval RTEMS_NO_MEMORY Not enough chunk descriptors. */ diff --git a/cpukit/sapi/include/rtems/rbtree.h b/cpukit/sapi/include/rtems/rbtree.h index eaf2b6e..0e2ea2c 100644 --- a/cpukit/sapi/include/rtems/rbtree.h +++ b/cpukit/sapi/include/rtems/rbtree.h @@ -55,9 +55,12 @@ typedef RBTree_Node rtems_rbtree_node; typedef RBTree_Control rtems_rbtree_control; /** - * This type defines function pointers for user-provided comparison - * function. The function compares two nodes in order to determine - * the order in a red-black tree. + * @copydoc RBTree_Compare_result + */ +typedef RBTree_Compare_result rtems_rbtree_compare_result; + +/** + * @copydoc RBTree_Compare */ typedef RBTree_Compare rtems_rbtree_compare; diff --git a/cpukit/sapi/src/rbheap.c b/cpukit/sapi/src/rbheap.c index 20338eb..049a64d 100644 --- a/cpukit/sapi/src/rbheap.c +++ b/cpukit/sapi/src/rbheap.c @@ -46,12 +46,16 @@ static uintptr_t align_down(uintptr_t alignment, uintptr_t value) return value - excess; } -static int chunk_compare(const rtems_rbtree_node *a, const rtems_rbtree_node *b) +static rtems_rbtree_compare_result chunk_compare( + const rtems_rbtree_node *a, + const rtems_rbtree_node *b +) { const rtems_rbheap_chunk *left = rtems_rbheap_chunk_of_node(a); const rtems_rbheap_chunk *right = rtems_rbheap_chunk_of_node(b); - return (int) (left->begin - right->begin); + return (rtems_rbtree_compare_result) + ((left->begin >> 1) - (right->begin >> 1)); } static rtems_rbheap_chunk *get_chunk(rtems_rbheap_control *control) @@ -93,39 +97,43 @@ rtems_status_code rtems_rbheap_initialize( ) { rtems_status_code sc = RTEMS_SUCCESSFUL; + uintptr_t begin = (uintptr_t) area_begin; + uintptr_t end = begin + area_size; + uintptr_t aligned_begin; + uintptr_t aligned_end; - if (alignment > 0) { - uintptr_t begin = (uintptr_t) area_begin; - uintptr_t end = begin + area_size; - uintptr_t aligned_begin = align_up(alignment, begin); - uintptr_t aligned_end = align_down(alignment, end); - - if (begin < end && begin <= aligned_begin && aligned_begin < aligned_end) { - rtems_chain_control *free_chain = &control->free_chunk_chain; - rtems_rbtree_control *chunk_tree = &control->chunk_tree; - rtems_rbheap_chunk *first = NULL; - - rtems_chain_initialize_empty(free_chain); - rtems_chain_initialize_empty(&control->spare_descriptor_chain); - rtems_rbtree_initialize_empty(chunk_tree); - control->alignment = alignment; - control->handler_arg = handler_arg; - control->extend_descriptors = extend_descriptors; - - first = get_chunk(control); - if (first != NULL) { - first->begin = aligned_begin; - first->size = aligned_end - aligned_begin; - add_to_chain(free_chain, first); - insert_into_tree(chunk_tree, first); - } else { - sc = RTEMS_NO_MEMORY; - } + /* + * Ensure that the alignment is at least two, so that we can keep + * chunk_compare() that simple. + */ + alignment = alignment < 2 ? 2 : alignment; + + aligned_begin = align_up(alignment, begin); + aligned_end = align_down(alignment, end); + + if (begin < end && begin <= aligned_begin && aligned_begin < aligned_end) { + rtems_chain_control *free_chain = &control->free_chunk_chain; + rtems_rbtree_control *chunk_tree = &control->chunk_tree; + rtems_rbheap_chunk *first = NULL; + + rtems_chain_initialize_empty(free_chain); + rtems_chain_initialize_empty(&control->spare_descriptor_chain); + rtems_rbtree_initialize_empty(chunk_tree); + control->alignment = alignment; + control->handler_arg = handler_arg; + control->extend_descriptors = extend_descriptors; + + first = get_chunk(control); + if (first != NULL) { + first->begin = aligned_begin; + first->size = aligned_end - aligned_begin; + add_to_chain(free_chain, first); + insert_into_tree(chunk_tree, first); } else { - sc = RTEMS_INVALID_ADDRESS; + sc = RTEMS_NO_MEMORY; } } else { - sc = RTEMS_INVALID_NUMBER; + sc = RTEMS_INVALID_ADDRESS; } return sc; diff --git a/cpukit/score/include/rtems/score/rbtree.h b/cpukit/score/include/rtems/score/rbtree.h index d23808f..aa84558 100644 --- a/cpukit/score/include/rtems/score/rbtree.h +++ b/cpukit/score/include/rtems/score/rbtree.h @@ -90,6 +90,15 @@ typedef enum { } RBTree_Direction; /** + * @brief Integer type for compare results. + * + * The type is large enough to represent pointers and 32-bit signed integers. + * + * @see RBTree_Compare. + */ +typedef long RBTree_Compare_result; + +/** * @brief Compares two red-black tree nodes. * * @param[in] first The first node. @@ -102,7 +111,7 @@ typedef enum { * @retval negative The key value of the first node is less than the one of the * second node. */ -typedef int ( *RBTree_Compare )( +typedef RBTree_Compare_result ( *RBTree_Compare )( const RBTree_Node *first, const RBTree_Node *second ); diff --git a/cpukit/score/include/rtems/score/rbtreeimpl.h b/cpukit/score/include/rtems/score/rbtreeimpl.h index f3af7fe..451b5f4 100644 --- a/cpukit/score/include/rtems/score/rbtreeimpl.h +++ b/cpukit/score/include/rtems/score/rbtreeimpl.h @@ -144,20 +144,22 @@ RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Parent_sibling( return _RBTree_Sibling(the_node->parent); } -RTEMS_INLINE_ROUTINE bool _RBTree_Is_equal( int compare_result ) +RTEMS_INLINE_ROUTINE bool _RBTree_Is_equal( + RBTree_Compare_result compare_result +) { return compare_result == 0; } RTEMS_INLINE_ROUTINE bool _RBTree_Is_greater( - int compare_result + RBTree_Compare_result compare_result ) { return compare_result > 0; } RTEMS_INLINE_ROUTINE bool _RBTree_Is_lesser( - int compare_result + RBTree_Compare_result compare_result ) { return compare_result < 0; diff --git a/cpukit/score/include/rtems/score/scheduleredfimpl.h b/cpukit/score/include/rtems/score/scheduleredfimpl.h index 50e40bc..a98fb0f 100644 --- a/cpukit/score/include/rtems/score/scheduleredfimpl.h +++ b/cpukit/score/include/rtems/score/scheduleredfimpl.h @@ -44,7 +44,7 @@ RTEMS_INLINE_ROUTINE Scheduler_EDF_Node *_Scheduler_EDF_Thread_get_node( return (Scheduler_EDF_Node *) _Scheduler_Thread_get_node( the_thread ); } -int _Scheduler_EDF_Compare( +RBTree_Compare_result _Scheduler_EDF_Compare( const RBTree_Node* n1, const RBTree_Node* n2 ); diff --git a/cpukit/score/include/rtems/score/threadqimpl.h b/cpukit/score/include/rtems/score/threadqimpl.h index 0e139cd..5931d22 100644 --- a/cpukit/score/include/rtems/score/threadqimpl.h +++ b/cpukit/score/include/rtems/score/threadqimpl.h @@ -260,7 +260,7 @@ void _Thread_queue_Process_timeout( * @retval 0 The @left node is of equal importance with @right node. * @retval 1 The @left node is less important than @right node. */ -int _Thread_queue_Compare_priority( +RBTree_Compare_result _Thread_queue_Compare_priority( const RBTree_Node *left, const RBTree_Node *right ); diff --git a/cpukit/score/src/rbtreefind.c b/cpukit/score/src/rbtreefind.c index f767626..168a108 100644 --- a/cpukit/score/src/rbtreefind.c +++ b/cpukit/score/src/rbtreefind.c @@ -30,8 +30,8 @@ RBTree_Node *_RBTree_Find( RBTree_Node *found = NULL; while ( iter_node != NULL ) { - int compare_result = ( *compare )( the_node, iter_node ); - RBTree_Direction dir; + RBTree_Compare_result compare_result = ( *compare )( the_node, iter_node ); + RBTree_Direction dir; if ( _RBTree_Is_equal( compare_result ) ) { found = iter_node; diff --git a/cpukit/score/src/rbtreeinsert.c b/cpukit/score/src/rbtreeinsert.c index afff1ef..3bccba5 100644 --- a/cpukit/score/src/rbtreeinsert.c +++ b/cpukit/score/src/rbtreeinsert.c @@ -12,6 +12,16 @@ #include +RTEMS_STATIC_ASSERT( + sizeof( RBTree_Compare_result ) >= sizeof( intptr_t ), + RBTree_Compare_result_intptr_t +); + +RTEMS_STATIC_ASSERT( + sizeof( RBTree_Compare_result ) >= sizeof( int32_t ), + RBTree_Compare_result_int32_t +); + /** @brief Validate and fix-up tree properties for a new insert/colored node * * This routine checks and fixes the Red-Black Tree properties based on @@ -77,7 +87,8 @@ RBTree_Node *_RBTree_Insert( } else { /* typical binary search tree insert, descend tree to leaf and insert */ while ( iter_node ) { - int compare_result = ( *compare )( the_node, iter_node ); + RBTree_Compare_result compare_result = + ( *compare )( the_node, iter_node ); if ( is_unique && _RBTree_Is_equal( compare_result ) ) return iter_node; diff --git a/cpukit/score/src/scheduleredf.c b/cpukit/score/src/scheduleredf.c index 6dfa288..00b6181 100644 --- a/cpukit/score/src/scheduleredf.c +++ b/cpukit/score/src/scheduleredf.c @@ -20,7 +20,7 @@ #include -int _Scheduler_EDF_Compare( +RBTree_Compare_result _Scheduler_EDF_Compare( const RBTree_Node* n1, const RBTree_Node* n2 ) diff --git a/cpukit/score/src/threadq.c b/cpukit/score/src/threadq.c index b146ad4..aa08541 100644 --- a/cpukit/score/src/threadq.c +++ b/cpukit/score/src/threadq.c @@ -24,7 +24,7 @@ #include #include -int _Thread_queue_Compare_priority( +RBTree_Compare_result _Thread_queue_Compare_priority( const RBTree_Node *left, const RBTree_Node *right ) diff --git a/testsuites/libtests/rbheap01/init.c b/testsuites/libtests/rbheap01/init.c index 93813b8..6fd86db 100644 --- a/testsuites/libtests/rbheap01/init.c +++ b/testsuites/libtests/rbheap01/init.c @@ -94,22 +94,6 @@ static bool chunk_visitor( return false; } -static void test_init_chunk_alignment(void) -{ - rtems_status_code sc = RTEMS_SUCCESSFUL; - rtems_rbheap_control control; - - sc = rtems_rbheap_initialize( - &control, - area, - sizeof(area), - 0, - extend_descriptors, - NULL - ); - rtems_test_assert(sc == RTEMS_INVALID_NUMBER); -} - static void test_init_begin_greater_than_end(void) { rtems_status_code sc = RTEMS_SUCCESSFUL; @@ -597,7 +581,6 @@ static void Init(rtems_task_argument arg) { TEST_BEGIN(); - test_init_chunk_alignment(); test_init_begin_greater_than_end(); test_init_begin_greater_than_aligned_begin(); test_init_aligned_begin_greater_than_aligned_end(); diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index d78790f..2dd08f5 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -33,7 +33,7 @@ typedef struct { rtems_rbtree_node Node; } test_node; -static int test_compare_function ( +static rtems_rbtree_compare_result test_compare_function ( const rtems_rbtree_node *n1, const rtems_rbtree_node *n2 ) From sebh at rtems.org Tue Aug 5 08:05:21 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 05 Aug 2014 03:05:21 -0500 Subject: [rtems commit] posix: Simplify key implementation Message-ID: <20140805080521.7C7AC7007F6@git.rtems.org> Module: rtems Branch: master Commit: 390cfcda71c5bb0d53493210bcf4a15ee29c0498 Changeset: http://git.rtems.org/rtems/commit/?id=390cfcda71c5bb0d53493210bcf4a15ee29c0498 Author: Sebastian Huber Date: Sat Aug 2 15:49:26 2014 +0200 posix: Simplify key implementation --- cpukit/posix/include/rtems/posix/key.h | 33 +++++++++++++++++++++------ cpukit/posix/include/rtems/posix/keyimpl.h | 4 +- cpukit/posix/src/key.c | 20 ++++++++++------ cpukit/posix/src/keygetspecific.c | 2 +- cpukit/posix/src/keysetspecific.c | 6 +++- 5 files changed, 44 insertions(+), 21 deletions(-) diff --git a/cpukit/posix/include/rtems/posix/key.h b/cpukit/posix/include/rtems/posix/key.h index bfa05b1..7cc179c 100644 --- a/cpukit/posix/include/rtems/posix/key.h +++ b/cpukit/posix/include/rtems/posix/key.h @@ -25,6 +25,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -39,20 +40,36 @@ extern "C" { /**@{**/ /** - * @brief The rbtree node used to manage a POSIX key and value. + * @brief Represents POSIX key and value pair. */ typedef struct { - /** This field is the chain node structure. */ + /** + * @brief The chain node for the per-thread value chain. + */ Chain_Node Key_values_per_thread_node; - /** This field is the rbtree node structure. */ + + /** + * @brief The tree node for the lookup tree. + */ RBTree_Node Key_value_lookup_node; - /** This field is the POSIX key used as an rbtree key */ + + /** + * @brief The POSIX key identifier used in combination with the thread + * pointer as the tree key. + */ pthread_key_t key; - /** This field is the Thread id also used as an rbtree key */ - Objects_Id thread_id; - /** This field points to the POSIX key value of specific thread */ + + /** + * @brief The thread pointer used in combination with the POSIX key + * identifier as the tree key. + */ + Thread_Control *thread; + + /** + * @brief The thread specific POSIX key value. + */ const void *value; -} POSIX_Keys_Key_value_pair; +} POSIX_Keys_Key_value_pair; /** * @brief The data structure used to manage a POSIX key. diff --git a/cpukit/posix/include/rtems/posix/keyimpl.h b/cpukit/posix/include/rtems/posix/keyimpl.h index ded030d..42989b0 100644 --- a/cpukit/posix/include/rtems/posix/keyimpl.h +++ b/cpukit/posix/include/rtems/posix/keyimpl.h @@ -170,12 +170,12 @@ RTEMS_INLINE_ROUTINE void _POSIX_Keys_Key_value_pair_free( RTEMS_INLINE_ROUTINE RBTree_Node *_POSIX_Keys_Find( pthread_key_t key, - Objects_Id thread_id, + Thread_Control *thread, POSIX_Keys_Key_value_pair *search_node ) { search_node->key = key; - search_node->thread_id = thread_id; + search_node->thread = thread; return _RBTree_Find( &_POSIX_Keys_Key_value_lookup_tree, diff --git a/cpukit/posix/src/key.c b/cpukit/posix/src/key.c index 67c6e27..6753d57 100644 --- a/cpukit/posix/src/key.c +++ b/cpukit/posix/src/key.c @@ -51,7 +51,8 @@ RBTree_Compare_result _POSIX_Keys_Key_value_compare( { POSIX_Keys_Key_value_pair *n1; POSIX_Keys_Key_value_pair *n2; - Objects_Id thread_id1, thread_id2; + Thread_Control *thread1; + Thread_Control *thread2; RBTree_Compare_result diff; n1 = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node1 ); @@ -61,15 +62,18 @@ RBTree_Compare_result _POSIX_Keys_Key_value_compare( if ( diff ) return diff; - thread_id1 = n1->thread_id; - thread_id2 = n2->thread_id; + thread1 = n1->thread; + thread2 = n2->thread; - /** - * if thread_id1 or thread_id2 equals to 0, only key1 and key2 is valued. - * it enables us search node only by pthread_key_t type key. + /* + * If thread1 or thread2 equals to NULL, only key1 and key2 is valued. It + * enables us search node only by pthread_key_t type key. Exploit that the + * thread control alignment is at least two to avoid integer overflows. */ - if ( thread_id1 && thread_id2 ) - return thread_id1 - thread_id2; + if ( thread1 != NULL && thread2 != NULL ) + return (RBTree_Compare_result) ( (uintptr_t) thread1 >> 1 ) + - (RBTree_Compare_result) ( (uintptr_t) thread2 >> 1 ); + return 0; } diff --git a/cpukit/posix/src/keygetspecific.c b/cpukit/posix/src/keygetspecific.c index f7e7b71..5ab37a7 100644 --- a/cpukit/posix/src/keygetspecific.c +++ b/cpukit/posix/src/keygetspecific.c @@ -49,7 +49,7 @@ void *pthread_getspecific( switch ( location ) { case OBJECTS_LOCAL: - p = _POSIX_Keys_Find( key, _Thread_Executing->Object.id, &search_node ); + p = _POSIX_Keys_Find( key, _Thread_Executing, &search_node ); if ( p != NULL ) { value_pair_p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( p ); key_data = value_pair_p->value; diff --git a/cpukit/posix/src/keysetspecific.c b/cpukit/posix/src/keysetspecific.c index ec17d47..ee85ac2 100644 --- a/cpukit/posix/src/keysetspecific.c +++ b/cpukit/posix/src/keysetspecific.c @@ -39,12 +39,14 @@ int pthread_setspecific( POSIX_Keys_Key_value_pair *value_pair_ptr; RBTree_Node *p; POSIX_Keys_Key_value_pair search_node; + Thread_Control *executing; the_key = _POSIX_Keys_Get( key, &location ); switch ( location ) { case OBJECTS_LOCAL: - p = _POSIX_Keys_Find( key, _Thread_Executing->Object.id, &search_node ); + executing = _Thread_Executing; + p = _POSIX_Keys_Find( key, executing, &search_node ); if ( p != NULL ) { value_pair_ptr = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( p ); value_pair_ptr->value = value; @@ -58,7 +60,7 @@ int pthread_setspecific( } value_pair_ptr->key = key; - value_pair_ptr->thread_id = _Thread_Executing->Object.id; + value_pair_ptr->thread = executing; value_pair_ptr->value = value; /* The insert can only go wrong if the same node is already in a unique * tree. This has been already checked with the _RBTree_Find() */ From sebh at rtems.org Tue Aug 5 08:05:21 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 05 Aug 2014 03:05:21 -0500 Subject: [rtems commit] Add and use RTEMS_CONTAINER_OF() Message-ID: <20140805080521.2CC8D7007F7@git.rtems.org> Module: rtems Branch: master Commit: 40dcafaf80a29c20d74594853a8ff04441eabd9c Changeset: http://git.rtems.org/rtems/commit/?id=40dcafaf80a29c20d74594853a8ff04441eabd9c Author: Sebastian Huber Date: Sat Aug 2 16:22:31 2014 +0200 Add and use RTEMS_CONTAINER_OF() --- cpukit/libblock/src/bdbuf.c | 4 +- cpukit/posix/include/rtems/posix/keyimpl.h | 3 + cpukit/posix/src/key.c | 4 +- cpukit/posix/src/keyfreememory.c | 8 ++-- cpukit/posix/src/keygetspecific.c | 4 +- cpukit/posix/src/keysetspecific.c | 5 +-- cpukit/sapi/include/rtems/rbheap.h | 2 +- cpukit/sapi/include/rtems/rbtree.h | 10 ---- cpukit/score/include/rtems/score/basedefs.h | 10 ++++ cpukit/score/include/rtems/score/mrspimpl.h | 2 +- cpukit/score/include/rtems/score/rbtree.h | 14 ------ .../score/include/rtems/score/scheduleredfimpl.h | 2 +- cpukit/score/include/rtems/score/schedulerimpl.h | 2 +- cpukit/score/include/rtems/score/threadimpl.h | 18 ++++---- cpukit/score/src/resourceiterate.c | 6 +-- cpukit/score/src/schedulerchangeroot.c | 2 +- cpukit/score/src/scheduleredf.c | 10 +++-- cpukit/score/src/threadq.c | 12 +++--- cpukit/score/src/threadqdequeue.c | 2 +- cpukit/score/src/threadqfirst.c | 5 +- testsuites/sptests/sprbtree01/init.c | 44 ++++++++++---------- 21 files changed, 76 insertions(+), 93 deletions(-) diff --git a/cpukit/libblock/src/bdbuf.c b/cpukit/libblock/src/bdbuf.c index 31dd289..f215911 100644 --- a/cpukit/libblock/src/bdbuf.c +++ b/cpukit/libblock/src/bdbuf.c @@ -3178,8 +3178,8 @@ rtems_bdbuf_read_ahead_task (rtems_task_argument arg) while ((node = rtems_chain_get_unprotected (chain)) != NULL) { - rtems_disk_device *dd = (rtems_disk_device *) - ((char *) node - offsetof (rtems_disk_device, read_ahead.node)); + rtems_disk_device *dd = + RTEMS_CONTAINER_OF (node, rtems_disk_device, read_ahead.node); rtems_blkdev_bnum block = dd->read_ahead.next; rtems_blkdev_bnum media_block = 0; rtems_status_code sc = diff --git a/cpukit/posix/include/rtems/posix/keyimpl.h b/cpukit/posix/include/rtems/posix/keyimpl.h index b21c1d3..aff9749 100644 --- a/cpukit/posix/include/rtems/posix/keyimpl.h +++ b/cpukit/posix/include/rtems/posix/keyimpl.h @@ -49,6 +49,9 @@ extern RBTree_Control _POSIX_Keys_Key_value_lookup_tree; */ POSIX_EXTERN Freechain_Control _POSIX_Keys_Keypool; +#define POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node ) \ + RTEMS_CONTAINER_OF( node, POSIX_Keys_Key_value_pair, Key_value_lookup_node ) + /** * @brief POSIX key manager initialization. * diff --git a/cpukit/posix/src/key.c b/cpukit/posix/src/key.c index 105706a..e231299 100644 --- a/cpukit/posix/src/key.c +++ b/cpukit/posix/src/key.c @@ -54,8 +54,8 @@ int _POSIX_Keys_Key_value_compare( Objects_Id thread_id1, thread_id2; int diff; - n1 = _RBTree_Container_of( node1, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); - n2 = _RBTree_Container_of( node2, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); + n1 = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node1 ); + n2 = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( node2 ); diff = n1->key - n2->key; if ( diff ) diff --git a/cpukit/posix/src/keyfreememory.c b/cpukit/posix/src/keyfreememory.c index b419f1f..4e19832 100644 --- a/cpukit/posix/src/keyfreememory.c +++ b/cpukit/posix/src/keyfreememory.c @@ -39,17 +39,17 @@ void _POSIX_Keys_Free_memory( * find the smallest thread_id node in the rbtree. */ next = _RBTree_Next( iter, RBT_LEFT ); - p = _RBTree_Container_of( next, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); + p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( next ); while ( next != NULL && p->key == key_id) { iter = next; next = _RBTree_Next( iter, RBT_LEFT ); - p = _RBTree_Container_of( next, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); + p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( next ); } /** * delete all nodes belongs to the_key from the rbtree and chain. */ - p = _RBTree_Container_of( iter, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); + p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( iter ); while ( iter != NULL && p->key == key_id ) { next = _RBTree_Next( iter, RBT_RIGHT ); _RBTree_Extract( &_POSIX_Keys_Key_value_lookup_tree, iter ); @@ -57,6 +57,6 @@ void _POSIX_Keys_Free_memory( _POSIX_Keys_Key_value_pair_free( p ); iter = next; - p = _RBTree_Container_of( iter, POSIX_Keys_Key_value_pair, Key_value_lookup_node ); + p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( iter ); } } diff --git a/cpukit/posix/src/keygetspecific.c b/cpukit/posix/src/keygetspecific.c index 9c54112..f7e7b71 100644 --- a/cpukit/posix/src/keygetspecific.c +++ b/cpukit/posix/src/keygetspecific.c @@ -51,9 +51,7 @@ void *pthread_getspecific( case OBJECTS_LOCAL: p = _POSIX_Keys_Find( key, _Thread_Executing->Object.id, &search_node ); if ( p != NULL ) { - value_pair_p = _RBTree_Container_of( p, - POSIX_Keys_Key_value_pair, - Key_value_lookup_node ); + value_pair_p = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( p ); key_data = value_pair_p->value; } else { key_data = NULL; diff --git a/cpukit/posix/src/keysetspecific.c b/cpukit/posix/src/keysetspecific.c index 0f7c682..ec17d47 100644 --- a/cpukit/posix/src/keysetspecific.c +++ b/cpukit/posix/src/keysetspecific.c @@ -46,10 +46,7 @@ int pthread_setspecific( case OBJECTS_LOCAL: p = _POSIX_Keys_Find( key, _Thread_Executing->Object.id, &search_node ); if ( p != NULL ) { - value_pair_ptr = _RBTree_Container_of( p, - POSIX_Keys_Key_value_pair, - Key_value_lookup_node ); - + value_pair_ptr = POSIX_KEYS_RBTREE_NODE_TO_KEY_VALUE_PAIR( p ); value_pair_ptr->value = value; } else { value_pair_ptr = _POSIX_Keys_Key_value_pair_allocate(); diff --git a/cpukit/sapi/include/rtems/rbheap.h b/cpukit/sapi/include/rtems/rbheap.h index 7c44f11..0848b69 100644 --- a/cpukit/sapi/include/rtems/rbheap.h +++ b/cpukit/sapi/include/rtems/rbheap.h @@ -254,7 +254,7 @@ void rtems_rbheap_extend_descriptors_with_malloc( /* Private API */ #define rtems_rbheap_chunk_of_node(node) \ - rtems_rbtree_container_of(node, rtems_rbheap_chunk, tree_node) + RTEMS_CONTAINER_OF(node, rtems_rbheap_chunk, tree_node) static inline bool rtems_rbheap_is_chunk_free(const rtems_rbheap_chunk *chunk) { diff --git a/cpukit/sapi/include/rtems/rbtree.h b/cpukit/sapi/include/rtems/rbtree.h index 4e6d852..eaf2b6e 100644 --- a/cpukit/sapi/include/rtems/rbtree.h +++ b/cpukit/sapi/include/rtems/rbtree.h @@ -74,16 +74,6 @@ typedef RBTree_Compare rtems_rbtree_compare; RBTREE_DEFINE_EMPTY(name) /** - * @brief macro to return the structure containing the @a node. - * - * This macro returns a pointer of type @a object_type that points - * to the structure containing @a node, where @a object_member is the - * field name of the rtems_rbtree_node structure in objects of @a object_type. - */ -#define rtems_rbtree_container_of(node,object_type, object_member) \ - _RBTree_Container_of(node,object_type,object_member) - -/** * @brief Initialize a RBTree header. * * This routine initializes @a the_rbtree structure to manage the diff --git a/cpukit/score/include/rtems/score/basedefs.h b/cpukit/score/include/rtems/score/basedefs.h index 382a97a..ec93951 100644 --- a/cpukit/score/include/rtems/score/basedefs.h +++ b/cpukit/score/include/rtems/score/basedefs.h @@ -217,6 +217,16 @@ */ #define RTEMS_ZERO_LENGTH_ARRAY 0 +/** + * @brief Returns a pointer to the container of a specified member pointer. + * + * @param[in] _m The pointer to a member of the container. + * @param[in] _type The type of the container. + * @param[in] _member_name The designator name of the container member. + */ +#define RTEMS_CONTAINER_OF( _m, _type, _member_name ) \ + ( (_type *) ( (uintptr_t) ( _m ) - offsetof( _type, _member_name ) ) ) + #ifndef ASM #ifdef RTEMS_DEPRECATED_TYPES typedef bool boolean; diff --git a/cpukit/score/include/rtems/score/mrspimpl.h b/cpukit/score/include/rtems/score/mrspimpl.h index 4aaa50b..1571594 100644 --- a/cpukit/score/include/rtems/score/mrspimpl.h +++ b/cpukit/score/include/rtems/score/mrspimpl.h @@ -181,7 +181,7 @@ RTEMS_INLINE_ROUTINE MRSP_Status _MRSP_Wait_for_ownership( _Scheduler_Thread_change_resource_root( executing, - _Thread_Resource_node_to_thread( _Resource_Node_get_root( owner ) ) + THREAD_RESOURCE_NODE_TO_THREAD( _Resource_Node_get_root( owner ) ) ); if ( timeout > 0 ) { diff --git a/cpukit/score/include/rtems/score/rbtree.h b/cpukit/score/include/rtems/score/rbtree.h index c4effce..d23808f 100644 --- a/cpukit/score/include/rtems/score/rbtree.h +++ b/cpukit/score/include/rtems/score/rbtree.h @@ -82,20 +82,6 @@ struct RBTree_Node_struct { }; /** - * @brief Macro to return the structure containing the @a node. - * - * This macro returns a pointer of type @a container_type that points - * to the structure containing @a node, where @a node_field_name is the - * field name of the RBTree_Node structure in @a container_type. - * - */ -#define _RBTree_Container_of(node, container_type, node_field_name) \ -( \ - (container_type*) \ - ( (uintptr_t)(node) - offsetof(container_type, node_field_name) ) \ -) - -/** * This type indicates the direction. */ typedef enum { diff --git a/cpukit/score/include/rtems/score/scheduleredfimpl.h b/cpukit/score/include/rtems/score/scheduleredfimpl.h index 019c544..50e40bc 100644 --- a/cpukit/score/include/rtems/score/scheduleredfimpl.h +++ b/cpukit/score/include/rtems/score/scheduleredfimpl.h @@ -89,7 +89,7 @@ RTEMS_INLINE_ROUTINE void _Scheduler_EDF_Schedule_body( _Scheduler_EDF_Get_context( scheduler ); RBTree_Node *first = _RBTree_First( &context->Ready, RBT_LEFT ); Scheduler_EDF_Node *node = - _RBTree_Container_of(first, Scheduler_EDF_Node, Node); + RTEMS_CONTAINER_OF( first, Scheduler_EDF_Node, Node ); Thread_Control *heir = node->thread; ( void ) the_thread; diff --git a/cpukit/score/include/rtems/score/schedulerimpl.h b/cpukit/score/include/rtems/score/schedulerimpl.h index 4f71408..45a2f8d 100644 --- a/cpukit/score/include/rtems/score/schedulerimpl.h +++ b/cpukit/score/include/rtems/score/schedulerimpl.h @@ -164,7 +164,7 @@ RTEMS_INLINE_ROUTINE bool _Scheduler_Ask_for_help_visitor( Thread_Control *previous_needs_help = help_context->needs_help; Thread_Control *next_needs_help; Thread_Control *offers_help = - _Thread_Resource_node_to_thread( resource_node ); + THREAD_RESOURCE_NODE_TO_THREAD( resource_node ); const Scheduler_Control *scheduler = _Scheduler_Get_own( offers_help ); next_needs_help = ( *scheduler->Operations.ask_for_help )( diff --git a/cpukit/score/include/rtems/score/threadimpl.h b/cpukit/score/include/rtems/score/threadimpl.h index a527c8b..9321c01 100644 --- a/cpukit/score/include/rtems/score/threadimpl.h +++ b/cpukit/score/include/rtems/score/threadimpl.h @@ -76,6 +76,14 @@ SCORE_EXTERN Thread_Control *_Thread_Allocated_fp; SCORE_EXTERN struct _reent **_Thread_libc_reent; #endif +#define THREAD_RBTREE_NODE_TO_THREAD( node ) \ + RTEMS_CONTAINER_OF( node, Thread_Control, RBNode ) + +#if defined(RTEMS_SMP) +#define THREAD_RESOURCE_NODE_TO_THREAD( node ) \ + RTEMS_CONTAINER_OF( node, Thread_Control, Resource_node ) +#endif + /** * @brief Initialize thread handler. * @@ -846,16 +854,6 @@ RTEMS_INLINE_ROUTINE bool _Thread_Owns_resources( return owns_resources; } -#if defined(RTEMS_SMP) -RTEMS_INLINE_ROUTINE Thread_Control *_Thread_Resource_node_to_thread( - Resource_Node *node -) -{ - return (Thread_Control *) - ( (char *) node - offsetof( Thread_Control, Resource_node ) ); -} -#endif - RTEMS_INLINE_ROUTINE void _Thread_Debug_set_real_processor( Thread_Control *the_thread, Per_CPU_Control *cpu diff --git a/cpukit/score/src/resourceiterate.c b/cpukit/score/src/resourceiterate.c index 26f9234..ac8b8b0 100644 --- a/cpukit/score/src/resourceiterate.c +++ b/cpukit/score/src/resourceiterate.c @@ -16,14 +16,12 @@ static Resource_Control *_Resource_Rival_head_to_resource( Chain_Node *head ) { - return (Resource_Control *) - ( (char *) head - offsetof( Resource_Control, Rivals.Head.Node ) ); + return RTEMS_CONTAINER_OF( head, Resource_Control, Rivals.Head.Node ); } static Resource_Node *_Resource_Resource_tail_to_rival( Chain_Node *tail ) { - return (Resource_Node *) - ( (char *) tail - offsetof( Resource_Node, Resources.Tail.Node ) ); + return RTEMS_CONTAINER_OF( tail, Resource_Node, Resources.Tail.Node ); } void _Resource_Iterate( diff --git a/cpukit/score/src/schedulerchangeroot.c b/cpukit/score/src/schedulerchangeroot.c index eba852b..f731117 100644 --- a/cpukit/score/src/schedulerchangeroot.c +++ b/cpukit/score/src/schedulerchangeroot.c @@ -32,7 +32,7 @@ RTEMS_INLINE_ROUTINE bool _Scheduler_Set_root_visitor( Thread_Control *root = ctx->root; Thread_Control *needs_help = root; Thread_Control *offers_help = - _Thread_Resource_node_to_thread( resource_node ); + THREAD_RESOURCE_NODE_TO_THREAD( resource_node ); const Scheduler_Control *scheduler = _Scheduler_Get_own( offers_help ); Thread_Control *needs_help_too; diff --git a/cpukit/score/src/scheduleredf.c b/cpukit/score/src/scheduleredf.c index 01b5244..6dfa288 100644 --- a/cpukit/score/src/scheduleredf.c +++ b/cpukit/score/src/scheduleredf.c @@ -25,10 +25,12 @@ int _Scheduler_EDF_Compare( const RBTree_Node* n2 ) { - Priority_Control value1 = _RBTree_Container_of - (n1,Scheduler_EDF_Node,Node)->thread->current_priority; - Priority_Control value2 = _RBTree_Container_of - (n2,Scheduler_EDF_Node,Node)->thread->current_priority; + Scheduler_EDF_Node *edf1 = + RTEMS_CONTAINER_OF( n1, Scheduler_EDF_Node, Node ); + Scheduler_EDF_Node *edf2 = + RTEMS_CONTAINER_OF( n2, Scheduler_EDF_Node, Node ); + Priority_Control value1 = edf1->thread->current_priority; + Priority_Control value2 = edf2->thread->current_priority; /* * This function compares only numbers for the red-black tree, diff --git a/cpukit/score/src/threadq.c b/cpukit/score/src/threadq.c index 0ffbfad..b146ad4 100644 --- a/cpukit/score/src/threadq.c +++ b/cpukit/score/src/threadq.c @@ -20,19 +20,19 @@ #include #include -#include - #include +#include +#include int _Thread_queue_Compare_priority( const RBTree_Node *left, const RBTree_Node *right ) { - Priority_Control left_priority = _RBTree_Container_of - (left,Thread_Control,RBNode)->current_priority; - Priority_Control right_priority = _RBTree_Container_of - (right,Thread_Control,RBNode)->current_priority; + Priority_Control left_priority = + THREAD_RBTREE_NODE_TO_THREAD( left )->current_priority; + Priority_Control right_priority = + THREAD_RBTREE_NODE_TO_THREAD( right )->current_priority; /* * SuperCore priorities use lower numbers to indicate greater importance. diff --git a/cpukit/score/src/threadqdequeue.c b/cpukit/score/src/threadqdequeue.c index d745ef2..e364aa9 100644 --- a/cpukit/score/src/threadqdequeue.c +++ b/cpukit/score/src/threadqdequeue.c @@ -50,7 +50,7 @@ Thread_Control *_Thread_queue_Dequeue( first = _RBTree_Get( &the_thread_queue->Queues.Priority, RBT_LEFT ); if ( first ) { - the_thread = _RBTree_Container_of( first, Thread_Control, RBNode ); + the_thread = THREAD_RBTREE_NODE_TO_THREAD( first ); } } diff --git a/cpukit/score/src/threadqfirst.c b/cpukit/score/src/threadqfirst.c index 39f7c3f..5d97ae1 100644 --- a/cpukit/score/src/threadqfirst.c +++ b/cpukit/score/src/threadqfirst.c @@ -18,9 +18,10 @@ #include "config.h" #endif +#include #include #include -#include +#include Thread_Control *_Thread_queue_First( Thread_queue_Control *the_thread_queue @@ -41,7 +42,7 @@ Thread_Control *_Thread_queue_First( first = _RBTree_First( &the_thread_queue->Queues.Priority, RBT_LEFT ); if ( first ) - thread = _RBTree_Container_of( first, Thread_Control, RBNode ); + thread = THREAD_RBTREE_NODE_TO_THREAD( first ); } _ISR_Enable( level ); diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index c43871a..d78790f 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -38,8 +38,8 @@ static int test_compare_function ( const rtems_rbtree_node *n2 ) { - int key1 = rtems_rbtree_container_of( n1, test_node, Node )->key; - int key2 = rtems_rbtree_container_of( n2, test_node, Node )->key; + int key1 = RTEMS_CONTAINER_OF( n1, test_node, Node )->key; + int key2 = RTEMS_CONTAINER_OF( n2, test_node, Node )->key; return key1 - key2; } @@ -262,7 +262,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 1 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 2 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -290,7 +290,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 1 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 1 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -345,9 +345,9 @@ rtems_task Init( rtems_task_argument ignored ) rb_insert_unique( &rbtree1, &node2.Node ); puts( "INIT - Verify rtems_rbtree_peek_max/min, rtems_rbtree_extract" ); - test_node *t1 = rtems_rbtree_container_of(rtems_rbtree_peek_max(&rbtree1), + test_node *t1 = RTEMS_CONTAINER_OF(rtems_rbtree_peek_max(&rbtree1), test_node,Node); - test_node *t2 = rtems_rbtree_container_of(rtems_rbtree_peek_min(&rbtree1), + test_node *t2 = RTEMS_CONTAINER_OF(rtems_rbtree_peek_min(&rbtree1), test_node,Node); if (t1->key - t2->key != 1) { puts( "INIT - Peek Min - Max failed" ); @@ -355,7 +355,7 @@ rtems_task Init( rtems_task_argument ignored ) } p = rtems_rbtree_peek_max(&rbtree1); rtems_rbtree_extract(&rbtree1, p); - t1 = rtems_rbtree_container_of(p,test_node,Node); + t1 = RTEMS_CONTAINER_OF(p,test_node,Node); if (t1->key != 2) { puts( "INIT - rtems_rbtree_extract failed"); rtems_test_exit(0); @@ -365,7 +365,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 1 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 2 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -390,7 +390,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -423,7 +423,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -467,7 +467,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0, i = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p, test_node, Node); + test_node *t = RTEMS_CONTAINER_OF(p, test_node, Node); while ( id == numbers_sorted[i] ) { /* skip if expected minimum (id) is in the set of extracted numbers */ @@ -529,7 +529,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_max(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_max(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -561,20 +561,20 @@ rtems_task Init( rtems_task_argument ignored ) puts( "INIT - Verify rtems_rbtree_find" ); search_node.key = 30; p = rb_find_unique(&rbtree1, &search_node.Node); - if(rtems_rbtree_container_of(p,test_node,Node)->id != 30) { + if(RTEMS_CONTAINER_OF(p,test_node,Node)->id != 30) { puts ("INIT - ERROR ON RBTREE ID MISMATCH"); rtems_test_exit(0); } puts( "INIT - Verify rtems_rbtree_predecessor/successor"); p = rtems_rbtree_predecessor(p); - if(p && rtems_rbtree_container_of(p,test_node,Node)->id != 29) { + if(p && RTEMS_CONTAINER_OF(p,test_node,Node)->id != 29) { puts ("INIT - ERROR ON RBTREE ID MISMATCH"); rtems_test_exit(0); } p = rb_find_unique(&rbtree1, &search_node.Node); p = rtems_rbtree_successor(p); - if(p && rtems_rbtree_container_of(p,test_node,Node)->id != 31) { + if(p && RTEMS_CONTAINER_OF(p,test_node,Node)->id != 31) { puts ("INIT - ERROR ON RBTREE ID MISMATCH"); rtems_test_exit(0); } @@ -601,7 +601,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_max(&rbtree1), id = 99 ; p ; p = rtems_rbtree_get_max(&rbtree1) , id-- ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id < 0 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -634,7 +634,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 19 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -666,7 +666,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -703,7 +703,7 @@ rtems_task Init( rtems_task_argument ignored ) puts( "INIT - Verify rtems_rbtree_find in a duplicate tree" ); search_node.key = 2; p = rb_find_multi(&rbtree1, &search_node.Node); - if(rtems_rbtree_container_of(p,test_node,Node)->id != 2) { + if(RTEMS_CONTAINER_OF(p,test_node,Node)->id != 2) { puts ("INIT - ERROR ON RBTREE ID MISMATCH"); rtems_test_exit(0); } @@ -712,7 +712,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); @@ -744,7 +744,7 @@ rtems_task Init( rtems_task_argument ignored ) puts( "INIT - Verify rtems_rbtree_find in a duplicate tree" ); search_node.key = 2; p = rb_find_multi(&rbtree1, &search_node.Node); - if(rtems_rbtree_container_of(p,test_node,Node)->id != 97) { + if(RTEMS_CONTAINER_OF(p,test_node,Node)->id != 97) { puts ("INIT - ERROR ON RBTREE ID MISMATCH"); rtems_test_exit(0); } @@ -753,7 +753,7 @@ rtems_task Init( rtems_task_argument ignored ) for ( p = rtems_rbtree_get_min(&rbtree1), id = 0 ; p ; p = rtems_rbtree_get_min(&rbtree1) , id++ ) { - test_node *t = rtems_rbtree_container_of(p,test_node,Node); + test_node *t = RTEMS_CONTAINER_OF(p,test_node,Node); if ( id > 99 ) { puts( "INIT - TOO MANY NODES ON RBTREE" ); rtems_test_exit(0); From sebh at rtems.org Tue Aug 5 13:11:33 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 05 Aug 2014 08:11:33 -0500 Subject: [rtems commit] sptests/sprbtree01: Reduce stack usage Message-ID: <20140805131133.D3B197007F6@git.rtems.org> Module: rtems Branch: master Commit: 888edf69a9f9db980914fc5f0ed61d62fecaf3f9 Changeset: http://git.rtems.org/rtems/commit/?id=888edf69a9f9db980914fc5f0ed61d62fecaf3f9 Author: Sebastian Huber Date: Tue Aug 5 13:52:45 2014 +0200 sptests/sprbtree01: Reduce stack usage --- testsuites/sptests/sprbtree01/init.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index 2dd08f5..742bd89 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -33,6 +33,8 @@ typedef struct { rtems_rbtree_node Node; } test_node; +static test_node node_array[100]; + static rtems_rbtree_compare_result test_compare_function ( const rtems_rbtree_node *n1, const rtems_rbtree_node *n2 @@ -225,7 +227,6 @@ rtems_task Init( rtems_task_argument ignored ) rtems_rbtree_control rbtree1; rtems_rbtree_node *p; test_node node1, node2; - test_node node_array[100]; test_node search_node; int id; int i; From sebh at rtems.org Tue Aug 5 13:11:33 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 05 Aug 2014 08:11:33 -0500 Subject: [rtems commit] sptests/sprbtree01: Check tree layout Message-ID: <20140805131133.C267C7007F7@git.rtems.org> Module: rtems Branch: master Commit: d472d2178019e3c03359ebdfbd9dcca1be40dfba Changeset: http://git.rtems.org/rtems/commit/?id=d472d2178019e3c03359ebdfbd9dcca1be40dfba Author: Sebastian Huber Date: Tue Aug 5 14:07:07 2014 +0200 sptests/sprbtree01: Check tree layout --- testsuites/sptests/sprbtree01/init.c | 620 ++++++++++++++++++++++++++++++++++ 1 files changed, 620 insertions(+), 0 deletions(-) diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index 742bd89..ffb91b1 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -222,6 +222,614 @@ static void test_rbtree_min_max(void) rtems_test_assert( rtems_rbtree_is_empty( &tree ) ); } +#define TN( i ) &node_array[ i ].Node + +typedef struct { + int key; + const rtems_rbtree_node *parent; + const rtems_rbtree_node *left; + const rtems_rbtree_node *right; + RBTree_Color color; +} test_node_description; + +static const test_node_description test_insert_tree_0[] = { + { 52, NULL, NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_1[] = { + { 52, NULL, NULL, TN( 1 ) , RBT_BLACK }, + { 99, TN( 0 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_2[] = { + { 0, TN( 0 ), NULL, NULL , RBT_RED }, + { 52, NULL, TN( 2 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 0 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_3[] = { + { 0, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 52, NULL, TN( 2 ), TN( 1 ) , RBT_BLACK }, + { 85, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 0 ), TN( 3 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_4[] = { + { 0, TN( 0 ), NULL, TN( 4 ) , RBT_BLACK }, + { 43, TN( 2 ), NULL, NULL , RBT_RED }, + { 52, NULL, TN( 2 ), TN( 1 ) , RBT_BLACK }, + { 85, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 0 ), TN( 3 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_5[] = { + { 0, TN( 4 ), NULL, NULL , RBT_RED }, + { 43, TN( 0 ), TN( 2 ), TN( 5 ) , RBT_BLACK }, + { 44, TN( 4 ), NULL, NULL , RBT_RED }, + { 52, NULL, TN( 4 ), TN( 1 ) , RBT_BLACK }, + { 85, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 0 ), TN( 3 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_6[] = { + { 0, TN( 4 ), NULL, TN( 6 ) , RBT_BLACK }, + { 10, TN( 2 ), NULL, NULL , RBT_RED }, + { 43, TN( 0 ), TN( 2 ), TN( 5 ) , RBT_RED }, + { 44, TN( 4 ), NULL, NULL , RBT_BLACK }, + { 52, NULL, TN( 4 ), TN( 1 ) , RBT_BLACK }, + { 85, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 0 ), TN( 3 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_7[] = { + { 0, TN( 4 ), NULL, TN( 6 ) , RBT_BLACK }, + { 10, TN( 2 ), NULL, NULL , RBT_RED }, + { 43, TN( 0 ), TN( 2 ), TN( 5 ) , RBT_RED }, + { 44, TN( 4 ), NULL, NULL , RBT_BLACK }, + { 52, NULL, TN( 4 ), TN( 3 ) , RBT_BLACK }, + { 60, TN( 3 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 3 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_8[] = { + { 0, TN( 4 ), NULL, TN( 6 ) , RBT_BLACK }, + { 10, TN( 2 ), NULL, NULL , RBT_RED }, + { 43, TN( 0 ), TN( 2 ), TN( 5 ) , RBT_RED }, + { 44, TN( 4 ), NULL, TN( 8 ) , RBT_BLACK }, + { 50, TN( 5 ), NULL, NULL , RBT_RED }, + { 52, NULL, TN( 4 ), TN( 3 ) , RBT_BLACK }, + { 60, TN( 3 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 3 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_9[] = { + { 0, TN( 6 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 6 ), NULL, NULL , RBT_RED }, + { 43, TN( 0 ), TN( 6 ), TN( 5 ) , RBT_RED }, + { 44, TN( 4 ), NULL, TN( 8 ) , RBT_BLACK }, + { 50, TN( 5 ), NULL, NULL , RBT_RED }, + { 52, NULL, TN( 4 ), TN( 3 ) , RBT_BLACK }, + { 60, TN( 3 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 3 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_10[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_RED }, + { 19, TN( 6 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 0 ), NULL, TN( 8 ) , RBT_BLACK }, + { 50, TN( 5 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 5 ), TN( 3 ) , RBT_RED }, + { 60, TN( 3 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 3 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_insert_tree_11[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 6 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 0 ), NULL, TN( 8 ) , RBT_BLACK }, + { 50, TN( 5 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 5 ), TN( 3 ) , RBT_BLACK }, + { 60, TN( 3 ), NULL, TN( 11 ) , RBT_BLACK }, + { 68, TN( 7 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_RED }, + { 99, TN( 3 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_12[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 6 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 12 ), TN( 3 ) , RBT_BLACK }, + { 60, TN( 3 ), NULL, TN( 11 ) , RBT_BLACK }, + { 68, TN( 7 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_RED }, + { 99, TN( 3 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_13[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 6 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 12 ), TN( 3 ) , RBT_BLACK }, + { 57, TN( 7 ), NULL, NULL , RBT_RED }, + { 60, TN( 3 ), TN( 13 ), TN( 11 ) , RBT_BLACK }, + { 68, TN( 7 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_RED }, + { 99, TN( 3 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_14[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 17, TN( 9 ), NULL, NULL , RBT_RED }, + { 19, TN( 6 ), TN( 14 ), NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 12 ), TN( 3 ) , RBT_BLACK }, + { 57, TN( 7 ), NULL, NULL , RBT_RED }, + { 60, TN( 3 ), TN( 13 ), TN( 11 ) , RBT_BLACK }, + { 68, TN( 7 ), NULL, NULL , RBT_RED }, + { 85, TN( 0 ), TN( 7 ), TN( 1 ) , RBT_RED }, + { 99, TN( 3 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_15[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 17, TN( 9 ), NULL, NULL , RBT_RED }, + { 19, TN( 6 ), TN( 14 ), NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_RED }, + { 68, TN( 3 ), TN( 15 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_RED }, + { 99, TN( 3 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_16[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 9 ) , RBT_BLACK }, + { 17, TN( 9 ), NULL, NULL , RBT_RED }, + { 19, TN( 6 ), TN( 14 ), NULL , RBT_BLACK }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_RED }, + { 68, TN( 3 ), TN( 15 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_RED }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_17[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 14 ) , RBT_BLACK }, + { 12, TN( 14 ), NULL, NULL , RBT_RED }, + { 17, TN( 6 ), TN( 17 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_RED }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_RED }, + { 68, TN( 3 ), TN( 15 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_RED }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_18[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 14 ) , RBT_BLACK }, + { 12, TN( 14 ), NULL, NULL , RBT_RED }, + { 17, TN( 6 ), TN( 17 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_RED }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_RED }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_BLACK }, + { 77, TN( 11 ), NULL, NULL , RBT_RED }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_RED }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_insert_tree_19[] = { + { 0, TN( 6 ), NULL, TN( 10 ) , RBT_BLACK }, + { 8, TN( 2 ), NULL, NULL , RBT_RED }, + { 10, TN( 4 ), TN( 2 ), TN( 14 ) , RBT_BLACK }, + { 12, TN( 14 ), NULL, NULL , RBT_RED }, + { 17, TN( 6 ), TN( 17 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_RED }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_RED }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description *const test_insert_trees[] = { + &test_insert_tree_0[ 0 ], + &test_insert_tree_1[ 0 ], + &test_insert_tree_2[ 0 ], + &test_insert_tree_3[ 0 ], + &test_insert_tree_4[ 0 ], + &test_insert_tree_5[ 0 ], + &test_insert_tree_6[ 0 ], + &test_insert_tree_7[ 0 ], + &test_insert_tree_8[ 0 ], + &test_insert_tree_9[ 0 ], + &test_insert_tree_10[ 0 ], + &test_insert_tree_11[ 0 ], + &test_insert_tree_12[ 0 ], + &test_insert_tree_13[ 0 ], + &test_insert_tree_14[ 0 ], + &test_insert_tree_15[ 0 ], + &test_insert_tree_16[ 0 ], + &test_insert_tree_17[ 0 ], + &test_insert_tree_18[ 0 ], + &test_insert_tree_19[ 0 ] +}; + +static const test_node_description test_remove_tree_0[] = { + { 8, TN( 6 ), NULL, NULL , RBT_BLACK }, + { 10, TN( 4 ), TN( 10 ), TN( 14 ) , RBT_BLACK }, + { 12, TN( 14 ), NULL, NULL , RBT_RED }, + { 17, TN( 6 ), TN( 17 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_RED }, + { 43, NULL, TN( 6 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_RED }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_1[] = { + { 10, TN( 14 ), NULL, TN( 17 ) , RBT_BLACK }, + { 12, TN( 6 ), NULL, NULL , RBT_RED }, + { 17, TN( 4 ), TN( 6 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 14 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_RED }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_2[] = { + { 12, TN( 14 ), NULL, NULL , RBT_BLACK }, + { 17, TN( 4 ), TN( 17 ), TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_BLACK }, + { 43, NULL, TN( 14 ), TN( 7 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 4 ), TN( 0 ), TN( 3 ) , RBT_RED }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_3[] = { + { 17, TN( 4 ), NULL, TN( 9 ) , RBT_BLACK }, + { 19, TN( 14 ), NULL, NULL , RBT_RED }, + { 43, TN( 7 ), TN( 14 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 4 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_4[] = { + { 19, TN( 4 ), NULL, NULL , RBT_BLACK }, + { 43, TN( 7 ), TN( 9 ), TN( 0 ) , RBT_BLACK }, + { 44, TN( 12 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 4 ), TN( 12 ), TN( 13 ) , RBT_RED }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 4 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_5[] = { + { 43, TN( 12 ), NULL, TN( 5 ) , RBT_BLACK }, + { 44, TN( 4 ), NULL, NULL , RBT_RED }, + { 48, TN( 0 ), TN( 4 ), TN( 8 ) , RBT_RED }, + { 50, TN( 12 ), NULL, NULL , RBT_BLACK }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_6[] = { + { 44, TN( 12 ), NULL, NULL , RBT_BLACK }, + { 48, TN( 0 ), TN( 5 ), TN( 8 ) , RBT_RED }, + { 50, TN( 12 ), NULL, NULL , RBT_BLACK }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_7[] = { + { 48, TN( 0 ), NULL, TN( 8 ) , RBT_BLACK }, + { 50, TN( 12 ), NULL, NULL , RBT_RED }, + { 52, TN( 7 ), TN( 12 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_8[] = { + { 50, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 52, TN( 7 ), TN( 8 ), TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_BLACK }, + { 60, NULL, TN( 0 ), TN( 3 ) , RBT_BLACK }, + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, TN( 3 ), TN( 15 ), TN( 18 ) , RBT_RED }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 11 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 7 ), TN( 11 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_9[] = { + { 52, TN( 7 ), NULL, TN( 13 ) , RBT_BLACK }, + { 57, TN( 0 ), NULL, NULL , RBT_RED }, + { 60, TN( 11 ), TN( 0 ), TN( 15 ) , RBT_BLACK }, + { 67, TN( 7 ), NULL, NULL , RBT_BLACK }, + { 68, NULL, TN( 7 ), TN( 3 ) , RBT_BLACK }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 3 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 11 ), TN( 18 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_10[] = { + { 57, TN( 7 ), NULL, NULL , RBT_BLACK }, + { 60, TN( 11 ), TN( 13 ), TN( 15 ) , RBT_BLACK }, + { 67, TN( 7 ), NULL, NULL , RBT_BLACK }, + { 68, NULL, TN( 7 ), TN( 3 ) , RBT_BLACK }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 3 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 11 ), TN( 18 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_11[] = { + { 60, TN( 11 ), NULL, TN( 15 ) , RBT_BLACK }, + { 67, TN( 7 ), NULL, NULL , RBT_RED }, + { 68, NULL, TN( 7 ), TN( 3 ) , RBT_BLACK }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 3 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 11 ), TN( 18 ), TN( 1 ) , RBT_RED }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_12[] = { + { 67, TN( 11 ), NULL, NULL , RBT_BLACK }, + { 68, NULL, TN( 15 ), TN( 3 ) , RBT_BLACK }, + { 71, TN( 18 ), NULL, NULL , RBT_RED }, + { 77, TN( 3 ), TN( 19 ), NULL , RBT_BLACK }, + { 85, TN( 11 ), TN( 18 ), TN( 1 ) , RBT_RED }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_13[] = { + { 68, TN( 19 ), NULL, NULL , RBT_BLACK }, + { 71, TN( 3 ), TN( 11 ), TN( 18 ) , RBT_RED }, + { 77, TN( 19 ), NULL, NULL , RBT_BLACK }, + { 85, NULL, TN( 19 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_14[] = { + { 71, TN( 3 ), NULL, TN( 18 ) , RBT_BLACK }, + { 77, TN( 19 ), NULL, NULL , RBT_RED }, + { 85, NULL, TN( 19 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_15[] = { + { 77, TN( 3 ), NULL, NULL , RBT_BLACK }, + { 85, NULL, TN( 18 ), TN( 1 ) , RBT_BLACK }, + { 90, TN( 1 ), NULL, NULL , RBT_RED }, + { 99, TN( 3 ), TN( 16 ), NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_16[] = { + { 85, TN( 16 ), NULL, NULL , RBT_BLACK }, + { 90, NULL, TN( 3 ), TN( 1 ) , RBT_BLACK }, + { 99, TN( 16 ), NULL, NULL , RBT_BLACK } +}; + +static const test_node_description test_remove_tree_17[] = { + { 90, NULL, NULL, TN( 1 ) , RBT_BLACK }, + { 99, TN( 16 ), NULL, NULL , RBT_RED } +}; + +static const test_node_description test_remove_tree_18[] = { + { 99, NULL, NULL, NULL , RBT_BLACK } +}; + +static const test_node_description *const test_remove_trees[] = { + &test_remove_tree_0[ 0 ], + &test_remove_tree_1[ 0 ], + &test_remove_tree_2[ 0 ], + &test_remove_tree_3[ 0 ], + &test_remove_tree_4[ 0 ], + &test_remove_tree_5[ 0 ], + &test_remove_tree_6[ 0 ], + &test_remove_tree_7[ 0 ], + &test_remove_tree_8[ 0 ], + &test_remove_tree_9[ 0 ], + &test_remove_tree_10[ 0 ], + &test_remove_tree_11[ 0 ], + &test_remove_tree_12[ 0 ], + &test_remove_tree_13[ 0 ], + &test_remove_tree_14[ 0 ], + &test_remove_tree_15[ 0 ], + &test_remove_tree_16[ 0 ], + &test_remove_tree_17[ 0 ], + &test_remove_tree_18[ 0 ] +}; + +typedef struct { + int current; + int count; + const test_node_description *tree; +} visitor_context; + +static bool visit_nodes( + const RBTree_Node *node, + RBTree_Direction dir, + void *visitor_arg +) +{ + visitor_context *ctx = visitor_arg; + const test_node_description *td = &ctx->tree[ ctx->current ]; + const test_node *tn = RTEMS_CONTAINER_OF( node, test_node, Node ); + + rtems_test_assert( ctx->current < ctx->count ); + + rtems_test_assert( td->key == tn->id ); + rtems_test_assert( td->key == tn->key ); + + if ( td->parent == NULL ) { + rtems_test_assert( td->parent == tn->Node.parent->parent ); + } else { + rtems_test_assert( td->parent == tn->Node.parent ); + } + + rtems_test_assert( td->left == tn->Node.child[ RBT_LEFT ] ); + rtems_test_assert( td->right == tn->Node.child[ RBT_RIGHT ] ); + rtems_test_assert( td->color == tn->Node.color ); + + ++ctx->current; + + return false; +} + rtems_task Init( rtems_task_argument ignored ) { rtems_rbtree_control rbtree1; @@ -623,10 +1231,15 @@ rtems_task Init( rtems_task_argument ignored ) puts("INIT - Insert 20 random numbers"); for (i = 0; i < 20; i++) { + visitor_context ctx = { 0, i + 1, test_insert_trees[ i ] }; + node_array[i].id = numbers[i]; node_array[i].key = numbers[i]; rb_insert_unique( &rbtree1, &node_array[i].Node ); + _RBTree_Iterate( &rbtree1, RBT_RIGHT, visit_nodes, &ctx ); + rtems_test_assert( ctx.current == ctx.count ); + if (!rb_assert(rbtree1.root) ) puts( "INIT - FAILED TREE CHECK" ); } @@ -647,6 +1260,13 @@ rtems_task Init( rtems_task_argument ignored ) if (!rb_assert(rbtree1.root) ) puts( "INIT - FAILED TREE CHECK" ); + + if ( id < 19 ) { + visitor_context ctx = { 0, 20 - id - 1, test_remove_trees[ id ] }; + + _RBTree_Iterate( &rbtree1, RBT_RIGHT, visit_nodes, &ctx ); + rtems_test_assert( ctx.current == ctx.count ); + } } if(!rtems_rbtree_is_empty(&rbtree1)) { From sebh at rtems.org Thu Aug 7 13:51:57 2014 From: sebh at rtems.org (Sebastian Huber) Date: Thu, 07 Aug 2014 08:51:57 -0500 Subject: [rtems commit] rbtree: Simplify _RBTree_Extract() Message-ID: <20140807135157.7C9677007F7@git.rtems.org> Module: rtems Branch: master Commit: 0ef6e3bfb9f763b4de46a8693d1e7cd59beb754e Changeset: http://git.rtems.org/rtems/commit/?id=0ef6e3bfb9f763b4de46a8693d1e7cd59beb754e Author: Sebastian Huber Date: Thu Jul 24 17:50:58 2014 +0200 rbtree: Simplify _RBTree_Extract() --- cpukit/score/src/rbtreeextract.c | 18 ++++++++++-------- 1 files changed, 10 insertions(+), 8 deletions(-) diff --git a/cpukit/score/src/rbtreeextract.c b/cpukit/score/src/rbtreeextract.c index f3a7328..1aaba27 100644 --- a/cpukit/score/src/rbtreeextract.c +++ b/cpukit/score/src/rbtreeextract.c @@ -23,7 +23,6 @@ static void _RBTree_Extract_validate( RBTree_Node *the_node ) { RBTree_Node *parent; - RBTree_Direction dir; parent = the_node->parent; @@ -40,11 +39,13 @@ static void _RBTree_Extract_validate( RBTree_Node *the_node ) * update sibling pointer. */ if ( _RBTree_Is_red( sibling ) ) { + RBTree_Direction dir = _RBTree_Direction( the_node, parent ); + RBTree_Direction opp_dir = _RBTree_Opposite_direction( dir ); + parent->color = RBT_RED; sibling->color = RBT_BLACK; - dir = the_node != parent->child[ 0 ]; _RBTree_Rotate( parent, dir ); - sibling = parent->child[ _RBTree_Opposite_direction( dir ) ]; + sibling = parent->child[ opp_dir ]; } /* sibling is black, see if both of its children are also black. */ @@ -66,20 +67,21 @@ static void _RBTree_Extract_validate( RBTree_Node *the_node ) * and if so rotate in the proper direction and update sibling pointer. * Then switch the sibling and parent colors, and rotate through parent. */ - dir = the_node != parent->child[ 0 ]; + RBTree_Direction dir = _RBTree_Direction( the_node, parent ); + RBTree_Direction opp_dir = _RBTree_Opposite_direction( dir ); if ( - !_RBTree_Is_red( sibling->child[ _RBTree_Opposite_direction( dir ) ] ) + !_RBTree_Is_red( sibling->child[ opp_dir ] ) ) { sibling->color = RBT_RED; sibling->child[ dir ]->color = RBT_BLACK; - _RBTree_Rotate( sibling, _RBTree_Opposite_direction( dir ) ); - sibling = parent->child[ _RBTree_Opposite_direction( dir ) ]; + _RBTree_Rotate( sibling, opp_dir ); + sibling = parent->child[ opp_dir ]; } sibling->color = parent->color; parent->color = RBT_BLACK; - sibling->child[ _RBTree_Opposite_direction( dir ) ]->color = RBT_BLACK; + sibling->child[ opp_dir ]->color = RBT_BLACK; _RBTree_Rotate( parent, dir ); break; /* done */ } From sebh at rtems.org Thu Aug 7 13:51:57 2014 From: sebh at rtems.org (Sebastian Huber) Date: Thu, 07 Aug 2014 08:51:57 -0500 Subject: [rtems commit] rbtree: Simplify insert and extract Message-ID: <20140807135157.5CD9270072E@git.rtems.org> Module: rtems Branch: master Commit: 993f5acd25cc3d140689c7a0f2c1912da7b2f0f3 Changeset: http://git.rtems.org/rtems/commit/?id=993f5acd25cc3d140689c7a0f2c1912da7b2f0f3 Author: Sebastian Huber Date: Wed Jul 23 13:03:54 2014 +0200 rbtree: Simplify insert and extract Simplify _RBTree_Insert() and _RBTree_Extract(). Remove more superfluous NULL pointer checks. Change _RBTree_Is_root() to use only the node. Add parent parameter to _RBTree_Sibling(). Delete _RBTree_Grandparent() and _RBTree_Parent_sibling(). --- cpukit/sapi/include/rtems/rbtree.h | 12 +---- cpukit/score/include/rtems/score/rbtree.h | 44 +++++++++++++------ cpukit/score/include/rtems/score/rbtreeimpl.h | 53 ++++------------------- cpukit/score/src/rbtreeextract.c | 7 +-- cpukit/score/src/rbtreeinsert.c | 57 ++++++++++++++++--------- testsuites/sptests/sprbtree01/init.c | 14 ++---- 6 files changed, 87 insertions(+), 100 deletions(-) diff --git a/cpukit/sapi/include/rtems/rbtree.h b/cpukit/sapi/include/rtems/rbtree.h index 0e2ea2c..900506f 100644 --- a/cpukit/sapi/include/rtems/rbtree.h +++ b/cpukit/sapi/include/rtems/rbtree.h @@ -195,9 +195,7 @@ RTEMS_INLINE_ROUTINE rtems_rbtree_node *rtems_rbtree_right( } /** - * @brief Return pointer to the parent child node from this node. - * - * This function returns a pointer to the parent node of @a the_node. + * @copydoc _RBTree_Parent() */ RTEMS_INLINE_ROUTINE rtems_rbtree_node *rtems_rbtree_parent( const rtems_rbtree_node *the_node @@ -248,17 +246,13 @@ RTEMS_INLINE_ROUTINE bool rtems_rbtree_is_max( } /** - * @brief Is this node the RBTree root. - * - * This function returns true if @a the_node is the root of @a the_rbtree and - * false otherwise. + * @copydoc _RBTree_Is_root() */ RTEMS_INLINE_ROUTINE bool rtems_rbtree_is_root( - const rtems_rbtree_control *the_rbtree, const rtems_rbtree_node *the_node ) { - return _RBTree_Is_root( the_rbtree, the_node ); + return _RBTree_Is_root( the_node ); } /** diff --git a/cpukit/score/include/rtems/score/rbtree.h b/cpukit/score/include/rtems/score/rbtree.h index aa84558..299b75a 100644 --- a/cpukit/score/include/rtems/score/rbtree.h +++ b/cpukit/score/include/rtems/score/rbtree.h @@ -300,9 +300,16 @@ RTEMS_INLINE_ROUTINE bool _RBTree_Is_node_off_tree( } /** - * @brief Return pointer to RBTree's root node. + * @brief Returns a pointer to root node of the red-black tree. * - * This function returns a pointer to the root node of @a the_rbtree. + * The root node may change after insert or extract operations. + * + * @param[in] the_rbtree The red-black tree control. + * + * @retval NULL The tree is empty. + * @retval root The root node. + * + * @see _RBTree_Is_root(). */ RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Root( const RBTree_Control *the_rbtree @@ -326,15 +333,21 @@ RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_First( } /** - * @brief Return pointer to the parent of this node. + * @brief Returns a pointer to the parent of this node. + * + * The node must have a parent, thus it is invalid to use this function for the + * root node or a node that is not part of a tree. To test for the root node + * compare with _RBTree_Root() or use _RBTree_Is_root(). + * + * @param[in] the_node The node of interest. * - * This function returns a pointer to the parent node of @a the_node. + * @retval parent The parent of this node. + * @retval undefined The node is the root node or not part of a tree. */ RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Parent( const RBTree_Node *the_node ) { - if (!the_node->parent->parent) return NULL; return the_node->parent; } @@ -409,20 +422,25 @@ RTEMS_INLINE_ROUTINE bool _RBTree_Is_first( } /** - * @brief Is this node the RBTree root. - * - * This function returns true if @a the_node is the root of @a the_rbtree and + * @brief Returns true if this node is the root node of a red-black tree, and * false otherwise. * - * @retval true @a the_node is the root of @a the_rbtree. - * @retval false @a the_node is not the root of @a the_rbtree. + * The root node may change after insert or extract operations. In case the + * node is not a node of a tree, then this function yields unpredictable + * results. + * + * @param[in] the_node The node of interest. + * + * @retval true The node is the root node. + * @retval false Otherwise. + * + * @see _RBTree_Root(). */ RTEMS_INLINE_ROUTINE bool _RBTree_Is_root( - const RBTree_Control *the_rbtree, - const RBTree_Node *the_node + const RBTree_Node *the_node ) { - return (the_node == _RBTree_Root(the_rbtree)); + return _RBTree_Parent( _RBTree_Parent( the_node ) ) == NULL; } /** diff --git a/cpukit/score/include/rtems/score/rbtreeimpl.h b/cpukit/score/include/rtems/score/rbtreeimpl.h index 5f5e783..ed4cbd5 100644 --- a/cpukit/score/include/rtems/score/rbtreeimpl.h +++ b/cpukit/score/include/rtems/score/rbtreeimpl.h @@ -107,56 +107,23 @@ RTEMS_INLINE_ROUTINE bool _RBTree_Is_red( } /** - * @brief Return a pointer to node's grandparent. + * @brief Returns the sibling of the node. * - * This function returns a pointer to the grandparent of @a the_node if it - * exists, and NULL if not. - */ -RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Grandparent( - const RBTree_Node *the_node -) -{ - if(!the_node) return NULL; - if(!(the_node->parent)) return NULL; - if(!(the_node->parent->parent)) return NULL; - if(!(the_node->parent->parent->parent)) return NULL; - return(the_node->parent->parent); -} - -/** - * @brief Return a pointer to node's sibling. + * @param[in] the_node The node of interest. + * @param[in] parent The parent of the node. The parent must exist, thus it is + * invalid to use this function for the root node. * - * This function returns a pointer to the sibling of @a the_node if it - * exists, and NULL if not. + * @retval NULL No sibling exists. + * @retval sibling The sibling of the node. */ RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Sibling( - const RBTree_Node *the_node -) -{ - if(!the_node) return NULL; - if(!(the_node->parent)) return NULL; - if(!(the_node->parent->parent)) return NULL; - - if(the_node == the_node->parent->child[RBT_LEFT]) - return the_node->parent->child[RBT_RIGHT]; - else - return the_node->parent->child[RBT_LEFT]; -} - -/** - * @brief Return a pointer to node's parent's sibling. - * - * This function returns a pointer to the sibling of the parent of - * @a the_node if it exists, and NULL if not. - */ -RTEMS_INLINE_ROUTINE RBTree_Node *_RBTree_Parent_sibling( - const RBTree_Node *the_node + const RBTree_Node *the_node, + const RBTree_Node *parent ) { - if(!the_node) return NULL; - if(_RBTree_Grandparent(the_node) == NULL) return NULL; + RBTree_Node *left_child = parent->child[ RBT_LEFT ]; - return _RBTree_Sibling(the_node->parent); + return the_node == left_child ? parent->child[ RBT_RIGHT ] : left_child; } RTEMS_INLINE_ROUTINE bool _RBTree_Is_equal( diff --git a/cpukit/score/src/rbtreeextract.c b/cpukit/score/src/rbtreeextract.c index a1896a9..f3a7328 100644 --- a/cpukit/score/src/rbtreeextract.c +++ b/cpukit/score/src/rbtreeextract.c @@ -22,7 +22,7 @@ */ static void _RBTree_Extract_validate( RBTree_Node *the_node ) { - RBTree_Node *parent, *sibling; + RBTree_Node *parent; RBTree_Direction dir; parent = the_node->parent; @@ -30,10 +30,10 @@ static void _RBTree_Extract_validate( RBTree_Node *the_node ) if ( !parent->parent ) return; - sibling = _RBTree_Sibling( the_node ); - /* continue to correct tree as long as the_node is black and not the root */ while ( !_RBTree_Is_red( the_node ) && parent->parent ) { + RBTree_Node *sibling = _RBTree_Sibling( the_node, parent ); + /* if sibling is red, switch parent (black) and sibling colors, * then rotate parent left, making the sibling be the_node's grandparent. * Now the_node has a black sibling and red parent. After rotation, @@ -59,7 +59,6 @@ static void _RBTree_Extract_validate( RBTree_Node *the_node ) the_node = parent; /* done if parent is red */ parent = the_node->parent; - sibling = _RBTree_Sibling( the_node ); } else { /* at least one of sibling's children is red. we now proceed in two * cases, either the_node is to the left or the right of the parent. diff --git a/cpukit/score/src/rbtreeinsert.c b/cpukit/score/src/rbtreeinsert.c index 3bccba5..a7be449 100644 --- a/cpukit/score/src/rbtreeinsert.c +++ b/cpukit/score/src/rbtreeinsert.c @@ -32,40 +32,55 @@ RTEMS_STATIC_ASSERT( */ static void _RBTree_Validate_insert( RBTree_Node *the_node ) { - RBTree_Node *u, *g; + RBTree_Node *parent = _RBTree_Parent( the_node ); + RBTree_Node *grandparent = _RBTree_Parent( parent ); /* note: the insert root case is handled already */ /* if the parent is black, nothing needs to be done * otherwise may need to loop a few times */ - while ( _RBTree_Is_red( _RBTree_Parent( the_node ) ) ) { - u = _RBTree_Parent_sibling( the_node ); - g = the_node->parent->parent; - - /* if uncle is red, repaint uncle/parent black and grandparent red */ - if ( _RBTree_Is_red( u ) ) { - the_node->parent->color = RBT_BLACK; - u->color = RBT_BLACK; - g->color = RBT_RED; - the_node = g; - } else { /* if uncle is black */ - RBTree_Direction dir = the_node != the_node->parent->child[ 0 ]; - RBTree_Direction pdir = the_node->parent != g->child[ 0 ]; + while ( parent->color == RBT_RED ) { + /* The root is black, so the grandparent must exist */ + RBTree_Node *uncle = _RBTree_Sibling( parent, grandparent ); + + /* + * If uncle exists and is red, repaint uncle/parent black and grandparent + * red. + */ + if ( uncle != NULL && uncle->color == RBT_RED ) { + parent->color = RBT_BLACK; + uncle->color = RBT_BLACK; + grandparent->color = RBT_RED; + the_node = grandparent; + parent = _RBTree_Parent( the_node ); + grandparent = _RBTree_Parent( parent ); + + if ( grandparent == NULL ) + break; + } else { /* If uncle does not exist or is black */ + RBTree_Direction dir = _RBTree_Direction( the_node, parent ); + RBTree_Direction parentdir = _RBTree_Direction( parent, grandparent ); /* ensure node is on the same branch direction as parent */ - if ( dir != pdir ) { - _RBTree_Rotate( the_node->parent, pdir ); - the_node = the_node->child[ pdir ]; + if ( dir != parentdir ) { + RBTree_Node *oldparent = parent; + + parent = the_node; + the_node = oldparent; + _RBTree_Rotate( oldparent, parentdir ); } - the_node->parent->color = RBT_BLACK; - g->color = RBT_RED; + parent->color = RBT_BLACK; + grandparent->color = RBT_RED; /* now rotate grandparent in the other branch direction (toward uncle) */ - _RBTree_Rotate( g, ( 1 - pdir ) ); + _RBTree_Rotate( grandparent, _RBTree_Opposite_direction( parentdir ) ); + + grandparent = _RBTree_Parent( parent ); + break; } } - if ( !the_node->parent->parent ) + if ( grandparent == NULL ) the_node->color = RBT_BLACK; } diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index 734530e..6a02a53 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -816,13 +816,13 @@ static bool visit_nodes( rtems_test_assert( td->key == tn->key ); if ( td->parent == NULL ) { - rtems_test_assert( td->parent == tn->Node.parent->parent ); + rtems_test_assert( rtems_rbtree_is_root( &tn->Node ) ); } else { - rtems_test_assert( td->parent == tn->Node.parent ); + rtems_test_assert( td->parent == rtems_rbtree_parent( &tn->Node ) ); } - rtems_test_assert( td->left == tn->Node.child[ RBT_LEFT ] ); - rtems_test_assert( td->right == tn->Node.child[ RBT_RIGHT ] ); + rtems_test_assert( td->left == rtems_rbtree_left( &tn->Node ) ); + rtems_test_assert( td->right == rtems_rbtree_right( &tn->Node ) ); rtems_test_assert( td->color == tn->Node.color ); ++ctx->current; @@ -1194,12 +1194,6 @@ rtems_task Init( rtems_task_argument ignored ) rtems_test_exit(0); } - if ( _RBTree_Sibling( NULL ) != NULL ) - puts ( "INIT - ERROR ON RBTREE NULL SIBLING MISMATCH" ); - if ( _RBTree_Sibling( rbtree1.root ) != NULL ) - puts ( "INIT - ERROR ON RBTREE NULL SIBLING MISMATCH" ); - if ( _RBTree_Grandparent( NULL ) != NULL ) - puts ( "INIT - ERROR ON RBTREE NULL GRANDPARENT MISMATCH" ); if ( _RBTree_Is_red( NULL ) != 0 ) puts ( "INIT - ERROR ON RBTREE NULL IS RED MISMATCH" ); if ( _RBTree_Is_red( rbtree1.root ) != 0 ) From sebh at rtems.org Thu Aug 7 13:51:57 2014 From: sebh at rtems.org (Sebastian Huber) Date: Thu, 07 Aug 2014 08:51:57 -0500 Subject: [rtems commit] rbtree: Simplify _RBTree_Rotate() Message-ID: <20140807135157.2B2997007F9@git.rtems.org> Module: rtems Branch: master Commit: 4752550f80206d7ab15daefb68532374f1b5a527 Changeset: http://git.rtems.org/rtems/commit/?id=4752550f80206d7ab15daefb68532374f1b5a527 Author: Sebastian Huber Date: Wed Jul 23 13:19:09 2014 +0200 rbtree: Simplify _RBTree_Rotate() Add and use _RBTree_Direction(). --- cpukit/score/include/rtems/score/rbtreeimpl.h | 78 +++++++++++++++++++----- testsuites/sptests/sprbtree01/init.c | 1 - 2 files changed, 61 insertions(+), 18 deletions(-) diff --git a/cpukit/score/include/rtems/score/rbtreeimpl.h b/cpukit/score/include/rtems/score/rbtreeimpl.h index 451b5f4..5f5e783 100644 --- a/cpukit/score/include/rtems/score/rbtreeimpl.h +++ b/cpukit/score/include/rtems/score/rbtreeimpl.h @@ -77,6 +77,21 @@ RTEMS_INLINE_ROUTINE RBTree_Direction _RBTree_Opposite_direction( } /** + * @brief Returns the direction of the node. + * + * @param[in] the_node The node of interest. + * @param[in] parent The parent of the node. The parent must exist, thus it is + * invalid to use this function for the root node. + */ +RTEMS_INLINE_ROUTINE RBTree_Direction _RBTree_Direction( + const RBTree_Node *the_node, + const RBTree_Node *parent +) +{ + return (RBTree_Direction) ( the_node != parent->child[ 0 ] ); +} + +/** * @brief Is this node red. * * This function returns true if @a the_node is red and false otherwise. @@ -166,32 +181,61 @@ RTEMS_INLINE_ROUTINE bool _RBTree_Is_lesser( } /** - * @brief Rotate the_node in the direction passed as second argument. + * @brief Rotates the node in the specified direction. * - * This routine rotates @a the_node to the direction @a dir, swapping - * @a the_node with its child\[@a dir\]. + * The node is swapped with its child in the opposite direction if it exists. + * + * Sub-tree before rotation: + * @dot + * digraph state { + * parent -> the_node; + * the_node -> sibling [label="dir"]; + * the_node -> child [label="opp_dir"]; + * child -> grandchild [label="dir"]; + * child -> grandchildsibling [label="opp_dir"]; + * } + * @enddot + * + * Sub-tree after rotation: + * @dot + * digraph state { + * parent -> child; + * the_node -> sibling [label="dir"]; + * the_node -> grandchild [label="opp_dir"]; + * child -> the_node [label="dir"]; + * child -> grandchildsibling [label="opp_dir"]; + * } + * @enddot + * + * @param[in] the_node The node to rotate. + * @param[in] dir The rotation direction. */ RTEMS_INLINE_ROUTINE void _RBTree_Rotate( - RBTree_Node *the_node, - RBTree_Direction dir - ) + RBTree_Node *the_node, + RBTree_Direction dir +) { - RBTree_Node *c; - if (the_node == NULL) return; - if (the_node->child[_RBTree_Opposite_direction(dir)] == NULL) return; + RBTree_Direction opp_dir = _RBTree_Opposite_direction( dir ); + RBTree_Node *child = the_node->child[ opp_dir ]; + RBTree_Node *grandchild; + RBTree_Node *parent; + + if ( child == NULL) + return; - c = the_node->child[_RBTree_Opposite_direction(dir)]; - the_node->child[_RBTree_Opposite_direction(dir)] = c->child[dir]; + grandchild = child->child[ dir ]; + the_node->child[ opp_dir ] = grandchild; - if (c->child[dir]) - c->child[dir]->parent = the_node; + if ( grandchild != NULL ) + grandchild->parent = the_node; - c->child[dir] = the_node; + child->child[ dir ] = the_node; - the_node->parent->child[the_node != the_node->parent->child[0]] = c; + parent = _RBTree_Parent( the_node ); + parent->child[ _RBTree_Direction( the_node, parent ) ] = child; - c->parent = the_node->parent; - the_node->parent = c; + child->parent = parent; + the_node->parent = child; } /** @} */ diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index ffb91b1..734530e 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -858,7 +858,6 @@ rtems_task Init( rtems_task_argument ignored ) rtems_test_assert( !rtems_rbtree_is_node_off_tree( &node1.Node ) ); - _RBTree_Rotate(NULL, RBT_LEFT); i = (node1.Node.parent == &node2.Node); _RBTree_Rotate( &node1.Node, !node1.Node.child[RBT_LEFT] ? RBT_RIGHT : RBT_LEFT From sebh at rtems.org Fri Aug 8 11:32:40 2014 From: sebh at rtems.org (Sebastian Huber) Date: Fri, 08 Aug 2014 06:32:40 -0500 Subject: [rtems commit] sptests/sprbtree01: Add random ops test case Message-ID: <20140808113240.50F477007F7@git.rtems.org> Module: rtems Branch: master Commit: 0b9fe3ec66ad6db3ac902665a5b6202502542ee7 Changeset: http://git.rtems.org/rtems/commit/?id=0b9fe3ec66ad6db3ac902665a5b6202502542ee7 Author: Sebastian Huber Date: Thu Aug 7 19:41:25 2014 +0200 sptests/sprbtree01: Add random ops test case --- testsuites/sptests/sprbtree01/init.c | 832 +++++++++++++++++++++++++- testsuites/sptests/sprbtree01/sprbtree01.scn | 1 + 2 files changed, 832 insertions(+), 1 deletions(-) diff --git a/testsuites/sptests/sprbtree01/init.c b/testsuites/sptests/sprbtree01/init.c index 6a02a53..22ed76c 100644 --- a/testsuites/sptests/sprbtree01/init.c +++ b/testsuites/sptests/sprbtree01/init.c @@ -812,7 +812,6 @@ static bool visit_nodes( rtems_test_assert( ctx->current < ctx->count ); - rtems_test_assert( td->key == tn->id ); rtems_test_assert( td->key == tn->key ); if ( td->parent == NULL ) { @@ -830,6 +829,836 @@ static bool visit_nodes( return false; } +static const test_node_description random_ops_tree_unique_1[] = { + { 0, NULL, NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_1[] = { + { 0, NULL, NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_2[] = { +}; + +static const test_node_description random_ops_tree_multiple_2[] = { +}; + +static const test_node_description random_ops_tree_unique_3[] = { + { 2, NULL, NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_3[] = { + { 1, NULL, NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_4[] = { + { 0, NULL, NULL, TN( 3 ), RBT_BLACK }, + { 3, TN( 0 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_4[] = { + { 0, NULL, NULL, TN( 3 ), RBT_BLACK }, + { 1, TN( 0 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_5[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, NULL, TN( 0 ), TN( 4 ), RBT_BLACK }, + { 4, TN( 1 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_5[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 0, NULL, TN( 0 ), TN( 4 ), RBT_BLACK }, + { 2, TN( 1 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_6[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 2, NULL, TN( 0 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_6[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 1, NULL, TN( 0 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_7[] = { + { 0, TN( 2 ), NULL, TN( 1 ), RBT_BLACK }, + { 1, TN( 0 ), NULL, NULL, RBT_RED }, + { 2, NULL, TN( 0 ), TN( 5 ), RBT_BLACK }, + { 4, TN( 5 ), NULL, NULL, RBT_RED }, + { 5, TN( 2 ), TN( 4 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_7[] = { + { 0, TN( 2 ), NULL, TN( 1 ), RBT_BLACK }, + { 0, TN( 0 ), NULL, NULL, RBT_RED }, + { 1, NULL, TN( 0 ), TN( 4 ), RBT_BLACK }, + { 2, TN( 4 ), NULL, NULL, RBT_RED }, + { 2, TN( 2 ), TN( 5 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_8[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 5 ), TN( 0 ), NULL, RBT_BLACK }, + { 5, NULL, TN( 1 ), TN( 6 ), RBT_BLACK }, + { 6, TN( 5 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_8[] = { + { 0, TN( 5 ), NULL, TN( 0 ), RBT_BLACK }, + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 2, NULL, TN( 1 ), TN( 6 ), RBT_BLACK }, + { 3, TN( 5 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_9[] = { + { 1, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 6 ), TN( 1 ), TN( 4 ), RBT_RED }, + { 4, TN( 2 ), NULL, TN( 5 ), RBT_BLACK }, + { 5, TN( 4 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 2 ), TN( 7 ), RBT_BLACK }, + { 7, TN( 6 ), NULL, TN( 8 ), RBT_BLACK }, + { 8, TN( 7 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_9[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 6 ), TN( 1 ), TN( 4 ), RBT_RED }, + { 2, TN( 2 ), NULL, TN( 5 ), RBT_BLACK }, + { 2, TN( 4 ), NULL, NULL, RBT_RED }, + { 3, NULL, TN( 2 ), TN( 7 ), RBT_BLACK }, + { 3, TN( 6 ), NULL, TN( 8 ), RBT_BLACK }, + { 4, TN( 7 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_10[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 6 ), TN( 0 ), TN( 4 ), RBT_RED }, + { 3, TN( 4 ), NULL, NULL, RBT_RED }, + { 4, TN( 2 ), TN( 3 ), NULL, RBT_BLACK }, + { 6, NULL, TN( 2 ), TN( 8 ), RBT_BLACK }, + { 8, TN( 6 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_10[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 6 ), TN( 0 ), TN( 4 ), RBT_RED }, + { 1, TN( 4 ), NULL, NULL, RBT_RED }, + { 2, TN( 2 ), TN( 3 ), NULL, RBT_BLACK }, + { 3, NULL, TN( 2 ), TN( 8 ), RBT_BLACK }, + { 4, TN( 6 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_11[] = { + { 2, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 6, NULL, TN( 2 ), TN( 8 ), RBT_BLACK }, + { 7, TN( 8 ), NULL, NULL, RBT_RED }, + { 8, TN( 6 ), TN( 7 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 8 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_11[] = { + { 1, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 3, NULL, TN( 2 ), TN( 8 ), RBT_BLACK }, + { 3, TN( 8 ), NULL, NULL, RBT_RED }, + { 4, TN( 6 ), TN( 7 ), TN( 9 ), RBT_BLACK }, + { 4, TN( 8 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_12[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 3 ), TN( 0 ), TN( 2 ), RBT_BLACK }, + { 2, TN( 1 ), NULL, NULL, RBT_RED }, + { 3, TN( 5 ), TN( 1 ), TN( 4 ), RBT_RED }, + { 4, TN( 3 ), NULL, NULL, RBT_BLACK }, + { 5, NULL, TN( 3 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 5 ), NULL, TN( 11 ), RBT_BLACK }, + { 11, TN( 9 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_12[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 0, TN( 5 ), TN( 0 ), TN( 3 ), RBT_RED }, + { 1, TN( 1 ), NULL, TN( 2 ), RBT_BLACK }, + { 1, TN( 3 ), NULL, NULL, RBT_RED }, + { 2, NULL, TN( 1 ), TN( 9 ), RBT_BLACK }, + { 2, TN( 9 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 5 ), TN( 4 ), TN( 11 ), RBT_RED }, + { 5, TN( 9 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_13[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 3 ), TN( 0 ), NULL, RBT_BLACK }, + { 3, NULL, TN( 1 ), TN( 8 ), RBT_BLACK }, + { 4, TN( 5 ), NULL, NULL, RBT_RED }, + { 5, TN( 8 ), TN( 4 ), TN( 6 ), RBT_BLACK }, + { 6, TN( 5 ), NULL, NULL, RBT_RED }, + { 8, TN( 3 ), TN( 5 ), TN( 11 ), RBT_RED }, + { 10, TN( 11 ), NULL, NULL, RBT_RED }, + { 11, TN( 8 ), TN( 10 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_13[] = { + { 0, TN( 0 ), NULL, NULL, RBT_BLACK }, + { 0, TN( 4 ), TN( 1 ), TN( 3 ), RBT_RED }, + { 1, TN( 0 ), NULL, NULL, RBT_BLACK }, + { 2, NULL, TN( 0 ), TN( 8 ), RBT_BLACK }, + { 2, TN( 6 ), NULL, NULL, RBT_RED }, + { 3, TN( 8 ), TN( 5 ), NULL, RBT_BLACK }, + { 4, TN( 4 ), TN( 6 ), TN( 11 ), RBT_RED }, + { 5, TN( 8 ), NULL, TN( 10 ), RBT_BLACK }, + { 5, TN( 11 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_14[] = { + { 3, TN( 6 ), NULL, TN( 5 ), RBT_BLACK }, + { 5, TN( 3 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 3 ), TN( 12 ), RBT_BLACK }, + { 8, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 12, TN( 6 ), TN( 8 ), TN( 13 ), RBT_RED }, + { 13, TN( 12 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_14[] = { + { 1, TN( 5 ), NULL, NULL, RBT_RED }, + { 2, TN( 6 ), TN( 3 ), NULL, RBT_BLACK }, + { 3, NULL, TN( 5 ), TN( 13 ), RBT_BLACK }, + { 4, TN( 13 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 6 ), TN( 8 ), TN( 12 ), RBT_RED }, + { 6, TN( 13 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_15[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 9 ), TN( 0 ), TN( 8 ), RBT_BLACK }, + { 7, TN( 8 ), NULL, NULL, RBT_RED }, + { 8, TN( 2 ), TN( 7 ), NULL, RBT_BLACK }, + { 9, NULL, TN( 2 ), TN( 12 ), RBT_BLACK }, + { 10, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 12, TN( 9 ), TN( 10 ), TN( 13 ), RBT_BLACK }, + { 13, TN( 12 ), NULL, TN( 14 ), RBT_BLACK }, + { 14, TN( 13 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_15[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 1, TN( 9 ), TN( 0 ), TN( 7 ), RBT_BLACK }, + { 3, TN( 2 ), NULL, NULL, RBT_RED }, + { 4, NULL, TN( 2 ), TN( 13 ), RBT_BLACK }, + { 4, TN( 13 ), NULL, TN( 10 ), RBT_BLACK }, + { 5, TN( 8 ), NULL, NULL, RBT_RED }, + { 6, TN( 9 ), TN( 8 ), TN( 12 ), RBT_RED }, + { 6, TN( 13 ), NULL, TN( 14 ), RBT_BLACK }, + { 7, TN( 12 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_16[] = { + { 0, TN( 5 ), NULL, TN( 3 ), RBT_BLACK }, + { 3, TN( 0 ), NULL, NULL, RBT_RED }, + { 5, NULL, TN( 0 ), TN( 10 ), RBT_BLACK }, + { 7, TN( 10 ), NULL, NULL, RBT_BLACK }, + { 10, TN( 5 ), TN( 7 ), TN( 12 ), RBT_RED }, + { 12, TN( 10 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_16[] = { + { 0, TN( 3 ), NULL, NULL, RBT_RED }, + { 1, TN( 7 ), TN( 0 ), TN( 5 ), RBT_BLACK }, + { 2, TN( 3 ), NULL, NULL, RBT_RED }, + { 3, NULL, TN( 3 ), TN( 12 ), RBT_BLACK }, + { 5, TN( 12 ), NULL, NULL, RBT_RED }, + { 6, TN( 7 ), TN( 10 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_17[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 5 ), TN( 0 ), TN( 3 ), RBT_BLACK }, + { 3, TN( 1 ), NULL, TN( 4 ), RBT_BLACK }, + { 4, TN( 3 ), NULL, NULL, RBT_RED }, + { 5, NULL, TN( 1 ), TN( 9 ), RBT_BLACK }, + { 7, TN( 9 ), NULL, TN( 8 ), RBT_BLACK }, + { 8, TN( 7 ), NULL, NULL, RBT_RED }, + { 9, TN( 5 ), TN( 7 ), TN( 16 ), RBT_BLACK }, + { 16, TN( 9 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_17[] = { + { 0, TN( 0 ), NULL, NULL, RBT_BLACK }, + { 0, TN( 5 ), TN( 1 ), TN( 3 ), RBT_BLACK }, + { 1, TN( 0 ), NULL, NULL, RBT_BLACK }, + { 2, NULL, TN( 0 ), TN( 9 ), RBT_BLACK }, + { 2, TN( 9 ), NULL, TN( 7 ), RBT_BLACK }, + { 3, TN( 4 ), NULL, NULL, RBT_RED }, + { 4, TN( 5 ), TN( 4 ), TN( 16 ), RBT_BLACK }, + { 4, TN( 16 ), NULL, NULL, RBT_RED }, + { 8, TN( 9 ), TN( 8 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_18[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 3 ), TN( 0 ), TN( 2 ), RBT_BLACK }, + { 2, TN( 1 ), NULL, NULL, RBT_RED }, + { 3, TN( 6 ), TN( 1 ), TN( 4 ), RBT_BLACK }, + { 4, TN( 3 ), NULL, TN( 5 ), RBT_BLACK }, + { 5, TN( 4 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 3 ), TN( 14 ), RBT_BLACK }, + { 7, TN( 8 ), NULL, NULL, RBT_RED }, + { 8, TN( 10 ), TN( 7 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 8 ), NULL, NULL, RBT_RED }, + { 10, TN( 14 ), TN( 8 ), TN( 12 ), RBT_RED }, + { 12, TN( 10 ), NULL, NULL, RBT_BLACK }, + { 14, TN( 6 ), TN( 10 ), TN( 17 ), RBT_BLACK }, + { 17, TN( 14 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_18[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 0, TN( 2 ), TN( 0 ), TN( 3 ), RBT_BLACK }, + { 1, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 6 ), TN( 1 ), TN( 4 ), RBT_BLACK }, + { 2, TN( 2 ), NULL, TN( 5 ), RBT_BLACK }, + { 2, TN( 4 ), NULL, NULL, RBT_RED }, + { 3, NULL, TN( 2 ), TN( 12 ), RBT_BLACK }, + { 3, TN( 8 ), NULL, NULL, RBT_RED }, + { 4, TN( 9 ), TN( 7 ), NULL, RBT_BLACK }, + { 4, TN( 12 ), TN( 8 ), TN( 10 ), RBT_RED }, + { 5, TN( 9 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 6 ), TN( 9 ), TN( 14 ), RBT_BLACK }, + { 7, TN( 12 ), NULL, TN( 17 ), RBT_BLACK }, + { 8, TN( 14 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_19[] = { + { 1, TN( 2 ), NULL, NULL, RBT_RED }, + { 2, TN( 6 ), TN( 1 ), NULL, RBT_BLACK }, + { 6, TN( 9 ), TN( 2 ), TN( 8 ), RBT_BLACK }, + { 8, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 9, NULL, TN( 6 ), TN( 12 ), RBT_BLACK }, + { 11, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 12, TN( 9 ), TN( 11 ), TN( 16 ), RBT_BLACK }, + { 14, TN( 16 ), NULL, NULL, RBT_RED }, + { 16, TN( 12 ), TN( 14 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_19[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 1, TN( 6 ), TN( 1 ), NULL, RBT_BLACK }, + { 3, TN( 8 ), TN( 2 ), TN( 9 ), RBT_BLACK }, + { 4, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 4, NULL, TN( 6 ), TN( 12 ), RBT_BLACK }, + { 5, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 8 ), TN( 11 ), TN( 16 ), RBT_BLACK }, + { 7, TN( 16 ), NULL, NULL, RBT_RED }, + { 8, TN( 12 ), TN( 14 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_20[] = { + { 0, TN( 3 ), NULL, TN( 1 ), RBT_BLACK }, + { 1, TN( 0 ), NULL, NULL, RBT_RED }, + { 3, TN( 9 ), TN( 0 ), TN( 4 ), RBT_RED }, + { 4, TN( 3 ), NULL, TN( 7 ), RBT_BLACK }, + { 7, TN( 4 ), NULL, NULL, RBT_RED }, + { 9, NULL, TN( 3 ), TN( 14 ), RBT_BLACK }, + { 10, TN( 14 ), NULL, TN( 12 ), RBT_BLACK }, + { 12, TN( 10 ), NULL, NULL, RBT_RED }, + { 14, TN( 9 ), TN( 10 ), TN( 18 ), RBT_RED }, + { 17, TN( 18 ), NULL, NULL, RBT_RED }, + { 18, TN( 14 ), TN( 17 ), TN( 19 ), RBT_BLACK }, + { 19, TN( 18 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_20[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 0, TN( 4 ), TN( 0 ), TN( 3 ), RBT_BLACK }, + { 1, TN( 1 ), NULL, NULL, RBT_RED }, + { 2, TN( 9 ), TN( 1 ), TN( 7 ), RBT_BLACK }, + { 3, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, NULL, TN( 4 ), TN( 12 ), RBT_BLACK }, + { 5, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 9 ), TN( 10 ), TN( 17 ), RBT_BLACK }, + { 7, TN( 17 ), NULL, NULL, RBT_BLACK }, + { 8, TN( 12 ), TN( 14 ), TN( 18 ), RBT_RED }, + { 9, TN( 17 ), NULL, TN( 19 ), RBT_BLACK }, + { 9, TN( 18 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_21[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 8 ), TN( 0 ), TN( 4 ), RBT_BLACK }, + { 3, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 1 ), TN( 3 ), TN( 5 ), RBT_RED }, + { 5, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 8, NULL, TN( 1 ), TN( 13 ), RBT_BLACK }, + { 11, TN( 13 ), NULL, NULL, RBT_BLACK }, + { 13, TN( 8 ), TN( 11 ), TN( 16 ), RBT_BLACK }, + { 15, TN( 16 ), NULL, NULL, RBT_BLACK }, + { 16, TN( 13 ), TN( 15 ), TN( 17 ), RBT_RED }, + { 17, TN( 16 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_21[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 0, TN( 8 ), TN( 0 ), TN( 4 ), RBT_BLACK }, + { 1, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 1 ), TN( 3 ), TN( 5 ), RBT_RED }, + { 2, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, NULL, TN( 1 ), TN( 13 ), RBT_BLACK }, + { 5, TN( 13 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 8 ), TN( 11 ), TN( 17 ), RBT_BLACK }, + { 7, TN( 17 ), NULL, NULL, RBT_BLACK }, + { 8, TN( 13 ), TN( 15 ), TN( 16 ), RBT_RED }, + { 8, TN( 17 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_22[] = { + { 1, TN( 3 ), NULL, TN( 2 ), RBT_BLACK }, + { 2, TN( 1 ), NULL, NULL, RBT_RED }, + { 3, TN( 8 ), TN( 1 ), TN( 4 ), RBT_BLACK }, + { 4, TN( 3 ), NULL, TN( 7 ), RBT_BLACK }, + { 7, TN( 4 ), NULL, NULL, RBT_RED }, + { 8, NULL, TN( 3 ), TN( 14 ), RBT_BLACK }, + { 10, TN( 11 ), NULL, NULL, RBT_RED }, + { 11, TN( 14 ), TN( 10 ), NULL, RBT_BLACK }, + { 14, TN( 8 ), TN( 11 ), TN( 18 ), RBT_BLACK }, + { 15, TN( 18 ), NULL, NULL, RBT_BLACK }, + { 18, TN( 14 ), TN( 15 ), TN( 21 ), RBT_RED }, + { 21, TN( 18 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_22[] = { + { 0, TN( 3 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 8 ), TN( 1 ), TN( 4 ), RBT_BLACK }, + { 1, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 3 ), TN( 2 ), TN( 7 ), RBT_RED }, + { 3, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, NULL, TN( 3 ), TN( 14 ), RBT_BLACK }, + { 5, TN( 14 ), NULL, TN( 10 ), RBT_BLACK }, + { 5, TN( 11 ), NULL, NULL, RBT_RED }, + { 7, TN( 8 ), TN( 11 ), TN( 18 ), RBT_BLACK }, + { 7, TN( 18 ), NULL, NULL, RBT_BLACK }, + { 9, TN( 14 ), TN( 15 ), TN( 21 ), RBT_RED }, + { 10, TN( 18 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_23[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 8 ), TN( 0 ), TN( 7 ), RBT_BLACK }, + { 7, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 8, NULL, TN( 2 ), TN( 16 ), RBT_BLACK }, + { 11, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 12, TN( 16 ), TN( 11 ), TN( 14 ), RBT_RED }, + { 13, TN( 14 ), NULL, NULL, RBT_RED }, + { 14, TN( 12 ), TN( 13 ), TN( 15 ), RBT_BLACK }, + { 15, TN( 14 ), NULL, NULL, RBT_RED }, + { 16, TN( 8 ), TN( 12 ), TN( 20 ), RBT_BLACK }, + { 17, TN( 20 ), NULL, NULL, RBT_RED }, + { 20, TN( 16 ), TN( 17 ), TN( 21 ), RBT_BLACK }, + { 21, TN( 20 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_23[] = { + { 0, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 8 ), TN( 0 ), TN( 7 ), RBT_RED }, + { 3, TN( 2 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 12 ), TN( 2 ), TN( 11 ), RBT_BLACK }, + { 5, TN( 8 ), NULL, NULL, RBT_BLACK }, + { 6, NULL, TN( 8 ), TN( 17 ), RBT_BLACK }, + { 6, TN( 15 ), NULL, NULL, RBT_BLACK }, + { 7, TN( 17 ), TN( 13 ), TN( 16 ), RBT_RED }, + { 7, TN( 16 ), NULL, NULL, RBT_RED }, + { 8, TN( 15 ), TN( 14 ), NULL, RBT_BLACK }, + { 8, TN( 12 ), TN( 15 ), TN( 20 ), RBT_BLACK }, + { 10, TN( 17 ), NULL, TN( 21 ), RBT_BLACK }, + { 10, TN( 20 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_24[] = { + { 4, TN( 5 ), NULL, NULL, RBT_BLACK }, + { 5, TN( 8 ), TN( 4 ), TN( 6 ), RBT_RED }, + { 6, TN( 5 ), NULL, NULL, RBT_BLACK }, + { 8, TN( 14 ), TN( 5 ), TN( 10 ), RBT_BLACK }, + { 10, TN( 8 ), NULL, NULL, RBT_BLACK }, + { 14, NULL, TN( 8 ), TN( 20 ), RBT_BLACK }, + { 15, TN( 16 ), NULL, NULL, RBT_RED }, + { 16, TN( 20 ), TN( 15 ), NULL, RBT_BLACK }, + { 20, TN( 14 ), TN( 16 ), TN( 22 ), RBT_BLACK }, + { 22, TN( 20 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_24[] = { + { 2, TN( 6 ), NULL, TN( 5 ), RBT_BLACK }, + { 2, TN( 4 ), NULL, NULL, RBT_RED }, + { 3, TN( 10 ), TN( 4 ), TN( 8 ), RBT_BLACK }, + { 4, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 5, NULL, TN( 6 ), TN( 16 ), RBT_BLACK }, + { 7, TN( 16 ), NULL, TN( 15 ), RBT_BLACK }, + { 7, TN( 14 ), NULL, NULL, RBT_RED }, + { 8, TN( 10 ), TN( 14 ), TN( 22 ), RBT_BLACK }, + { 10, TN( 22 ), NULL, NULL, RBT_RED }, + { 11, TN( 16 ), TN( 20 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_unique_25[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 1, TN( 13 ), TN( 0 ), TN( 4 ), RBT_BLACK }, + { 3, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 1 ), TN( 3 ), TN( 6 ), RBT_RED }, + { 5, TN( 6 ), NULL, NULL, RBT_RED }, + { 6, TN( 4 ), TN( 5 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 6 ), NULL, NULL, RBT_RED }, + { 13, NULL, TN( 1 ), TN( 19 ), RBT_BLACK }, + { 14, TN( 15 ), NULL, NULL, RBT_RED }, + { 15, TN( 16 ), TN( 14 ), NULL, RBT_BLACK }, + { 16, TN( 19 ), TN( 15 ), TN( 17 ), RBT_RED }, + { 17, TN( 16 ), NULL, NULL, RBT_BLACK }, + { 19, TN( 13 ), TN( 16 ), TN( 23 ), RBT_BLACK }, + { 23, TN( 19 ), NULL, TN( 24 ), RBT_BLACK }, + { 24, TN( 23 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_25[] = { + { 0, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 0, TN( 5 ), TN( 0 ), TN( 3 ), RBT_RED }, + { 1, TN( 1 ), NULL, NULL, RBT_BLACK }, + { 2, TN( 13 ), TN( 1 ), TN( 6 ), RBT_BLACK }, + { 2, TN( 6 ), NULL, NULL, RBT_RED }, + { 3, TN( 5 ), TN( 4 ), TN( 9 ), RBT_BLACK }, + { 4, TN( 6 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 5 ), TN( 19 ), RBT_BLACK }, + { 7, TN( 17 ), NULL, TN( 14 ), RBT_BLACK }, + { 7, TN( 15 ), NULL, NULL, RBT_RED }, + { 8, TN( 19 ), TN( 15 ), TN( 16 ), RBT_RED }, + { 8, TN( 17 ), NULL, NULL, RBT_BLACK }, + { 9, TN( 13 ), TN( 17 ), TN( 23 ), RBT_BLACK }, + { 11, TN( 19 ), NULL, TN( 24 ), RBT_BLACK }, + { 12, TN( 23 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_26[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 6 ), TN( 0 ), TN( 3 ), RBT_BLACK }, + { 3, TN( 1 ), NULL, NULL, RBT_RED }, + { 6, TN( 11 ), TN( 1 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 6 ), NULL, TN( 10 ), RBT_BLACK }, + { 10, TN( 9 ), NULL, NULL, RBT_RED }, + { 11, NULL, TN( 6 ), TN( 14 ), RBT_BLACK }, + { 12, TN( 14 ), NULL, TN( 13 ), RBT_BLACK }, + { 13, TN( 12 ), NULL, NULL, RBT_RED }, + { 14, TN( 11 ), TN( 12 ), TN( 20 ), RBT_BLACK }, + { 18, TN( 20 ), NULL, NULL, RBT_BLACK }, + { 20, TN( 14 ), TN( 18 ), TN( 23 ), RBT_RED }, + { 21, TN( 23 ), NULL, NULL, RBT_RED }, + { 23, TN( 20 ), TN( 21 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_26[] = { + { 0, TN( 0 ), NULL, NULL, RBT_RED }, + { 0, TN( 6 ), TN( 1 ), TN( 3 ), RBT_BLACK }, + { 1, TN( 0 ), NULL, NULL, RBT_RED }, + { 3, TN( 12 ), TN( 0 ), TN( 11 ), RBT_BLACK }, + { 4, TN( 11 ), NULL, NULL, RBT_RED }, + { 5, TN( 6 ), TN( 9 ), TN( 10 ), RBT_BLACK }, + { 5, TN( 11 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 6 ), TN( 18 ), RBT_BLACK }, + { 6, TN( 14 ), NULL, NULL, RBT_RED }, + { 7, TN( 18 ), TN( 13 ), NULL, RBT_BLACK }, + { 9, TN( 12 ), TN( 14 ), TN( 21 ), RBT_BLACK }, + { 10, TN( 21 ), NULL, NULL, RBT_RED }, + { 10, TN( 18 ), TN( 20 ), TN( 23 ), RBT_BLACK }, + { 11, TN( 21 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_27[] = { + { 3, TN( 8 ), NULL, NULL, RBT_BLACK }, + { 8, TN( 19 ), TN( 3 ), TN( 17 ), RBT_RED }, + { 12, TN( 17 ), NULL, NULL, RBT_RED }, + { 17, TN( 8 ), TN( 12 ), NULL, RBT_BLACK }, + { 19, NULL, TN( 8 ), TN( 23 ), RBT_BLACK }, + { 20, TN( 23 ), NULL, TN( 21 ), RBT_BLACK }, + { 21, TN( 20 ), NULL, NULL, RBT_RED }, + { 23, TN( 19 ), TN( 20 ), TN( 25 ), RBT_RED }, + { 24, TN( 25 ), NULL, NULL, RBT_RED }, + { 25, TN( 23 ), TN( 24 ), TN( 26 ), RBT_BLACK }, + { 26, TN( 25 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_27[] = { + { 1, TN( 8 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 19 ), TN( 3 ), TN( 17 ), RBT_RED }, + { 6, TN( 17 ), NULL, NULL, RBT_RED }, + { 8, TN( 8 ), TN( 12 ), NULL, RBT_BLACK }, + { 9, NULL, TN( 8 ), TN( 23 ), RBT_BLACK }, + { 10, TN( 23 ), NULL, TN( 21 ), RBT_BLACK }, + { 10, TN( 20 ), NULL, NULL, RBT_RED }, + { 11, TN( 19 ), TN( 20 ), TN( 24 ), RBT_RED }, + { 12, TN( 24 ), NULL, NULL, RBT_RED }, + { 12, TN( 23 ), TN( 25 ), TN( 26 ), RBT_BLACK }, + { 13, TN( 24 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_28[] = { + { 0, TN( 5 ), NULL, NULL, RBT_BLACK }, + { 5, TN( 13 ), TN( 0 ), TN( 7 ), RBT_RED }, + { 7, TN( 5 ), NULL, NULL, RBT_BLACK }, + { 13, NULL, TN( 5 ), TN( 17 ), RBT_BLACK }, + { 15, TN( 17 ), NULL, NULL, RBT_BLACK }, + { 17, TN( 13 ), TN( 15 ), TN( 26 ), RBT_RED }, + { 21, TN( 26 ), NULL, NULL, RBT_RED }, + { 26, TN( 17 ), TN( 21 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_28[] = { + { 0, TN( 5 ), NULL, NULL, RBT_RED }, + { 2, TN( 7 ), TN( 0 ), NULL, RBT_BLACK }, + { 3, NULL, TN( 5 ), TN( 15 ), RBT_BLACK }, + { 6, TN( 15 ), NULL, NULL, RBT_BLACK }, + { 7, TN( 7 ), TN( 13 ), TN( 21 ), RBT_RED }, + { 8, TN( 21 ), NULL, NULL, RBT_RED }, + { 10, TN( 15 ), TN( 17 ), TN( 26 ), RBT_BLACK }, + { 13, TN( 21 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_29[] = { + { 0, TN( 1 ), NULL, NULL, RBT_RED }, + { 1, TN( 4 ), TN( 0 ), TN( 3 ), RBT_BLACK }, + { 3, TN( 1 ), NULL, NULL, RBT_RED }, + { 4, TN( 11 ), TN( 1 ), TN( 7 ), RBT_BLACK }, + { 6, TN( 7 ), NULL, NULL, RBT_RED }, + { 7, TN( 4 ), TN( 6 ), TN( 8 ), RBT_BLACK }, + { 8, TN( 7 ), NULL, NULL, RBT_RED }, + { 11, NULL, TN( 4 ), TN( 13 ), RBT_BLACK }, + { 12, TN( 13 ), NULL, NULL, RBT_BLACK }, + { 13, TN( 11 ), TN( 12 ), TN( 22 ), RBT_BLACK }, + { 14, TN( 17 ), NULL, NULL, RBT_RED }, + { 17, TN( 22 ), TN( 14 ), NULL, RBT_BLACK }, + { 22, TN( 13 ), TN( 17 ), TN( 25 ), RBT_RED }, + { 25, TN( 22 ), NULL, TN( 27 ), RBT_BLACK }, + { 27, TN( 25 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_multiple_29[] = { + { 0, TN( 3 ), NULL, TN( 1 ), RBT_BLACK }, + { 0, TN( 0 ), NULL, NULL, RBT_RED }, + { 1, TN( 11 ), TN( 0 ), TN( 6 ), RBT_BLACK }, + { 2, TN( 6 ), NULL, NULL, RBT_BLACK }, + { 3, TN( 3 ), TN( 4 ), TN( 7 ), RBT_RED }, + { 3, TN( 6 ), NULL, TN( 8 ), RBT_BLACK }, + { 4, TN( 7 ), NULL, NULL, RBT_RED }, + { 5, NULL, TN( 3 ), TN( 12 ), RBT_BLACK }, + { 6, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 6, TN( 11 ), TN( 13 ), TN( 22 ), RBT_BLACK }, + { 7, TN( 17 ), NULL, NULL, RBT_RED }, + { 8, TN( 22 ), TN( 14 ), NULL, RBT_BLACK }, + { 11, TN( 12 ), TN( 17 ), TN( 25 ), RBT_RED }, + { 12, TN( 22 ), NULL, TN( 27 ), RBT_BLACK }, + { 13, TN( 25 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_30[] = { + { 0, TN( 4 ), NULL, NULL, RBT_BLACK }, + { 4, TN( 12 ), TN( 0 ), TN( 8 ), RBT_RED }, + { 6, TN( 8 ), NULL, NULL, RBT_RED }, + { 8, TN( 4 ), TN( 6 ), TN( 9 ), RBT_BLACK }, + { 9, TN( 8 ), NULL, NULL, RBT_RED }, + { 12, TN( 14 ), TN( 4 ), TN( 13 ), RBT_BLACK }, + { 13, TN( 12 ), NULL, NULL, RBT_BLACK }, + { 14, NULL, TN( 12 ), TN( 17 ), RBT_BLACK }, + { 16, TN( 17 ), NULL, NULL, RBT_BLACK }, + { 17, TN( 14 ), TN( 16 ), TN( 20 ), RBT_BLACK }, + { 18, TN( 20 ), NULL, NULL, RBT_BLACK }, + { 20, TN( 17 ), TN( 18 ), TN( 28 ), RBT_RED }, + { 27, TN( 28 ), NULL, NULL, RBT_RED }, + { 28, TN( 20 ), TN( 27 ), NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_30[] = { + { 0, TN( 4 ), NULL, NULL, RBT_RED }, + { 2, TN( 6 ), TN( 0 ), NULL, RBT_BLACK }, + { 3, TN( 12 ), TN( 4 ), TN( 8 ), RBT_RED }, + { 4, TN( 8 ), NULL, NULL, RBT_RED }, + { 4, TN( 6 ), TN( 9 ), TN( 13 ), RBT_BLACK }, + { 6, TN( 8 ), NULL, NULL, RBT_RED }, + { 6, NULL, TN( 6 ), TN( 18 ), RBT_BLACK }, + { 7, TN( 17 ), NULL, NULL, RBT_RED }, + { 8, TN( 18 ), TN( 14 ), TN( 16 ), RBT_BLACK }, + { 8, TN( 17 ), NULL, NULL, RBT_RED }, + { 9, TN( 12 ), TN( 17 ), TN( 27 ), RBT_RED }, + { 10, TN( 27 ), NULL, NULL, RBT_RED }, + { 13, TN( 18 ), TN( 20 ), TN( 28 ), RBT_BLACK }, + { 14, TN( 27 ), NULL, NULL, RBT_RED } +}; + +static const test_node_description random_ops_tree_unique_31[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 2, TN( 5 ), TN( 0 ), NULL, RBT_BLACK }, + { 5, TN( 14 ), TN( 2 ), TN( 9 ), RBT_BLACK }, + { 7, TN( 9 ), NULL, NULL, RBT_RED }, + { 9, TN( 5 ), TN( 7 ), TN( 11 ), RBT_BLACK }, + { 11, TN( 9 ), NULL, NULL, RBT_RED }, + { 14, NULL, TN( 5 ), TN( 21 ), RBT_BLACK }, + { 16, TN( 21 ), NULL, TN( 18 ), RBT_BLACK }, + { 18, TN( 16 ), NULL, NULL, RBT_RED }, + { 21, TN( 14 ), TN( 16 ), TN( 30 ), RBT_BLACK }, + { 30, TN( 21 ), NULL, NULL, RBT_BLACK } +}; + +static const test_node_description random_ops_tree_multiple_31[] = { + { 0, TN( 2 ), NULL, NULL, RBT_RED }, + { 1, TN( 5 ), TN( 0 ), NULL, RBT_BLACK }, + { 2, TN( 11 ), TN( 2 ), TN( 9 ), RBT_BLACK }, + { 3, TN( 9 ), NULL, NULL, RBT_RED }, + { 4, TN( 5 ), TN( 7 ), NULL, RBT_BLACK }, + { 5, NULL, TN( 5 ), TN( 21 ), RBT_BLACK }, + { 7, TN( 16 ), NULL, NULL, RBT_RED }, + { 8, TN( 21 ), TN( 14 ), TN( 18 ), RBT_BLACK }, + { 9, TN( 16 ), NULL, NULL, RBT_RED }, + { 10, TN( 11 ), TN( 16 ), TN( 30 ), RBT_BLACK }, + { 15, TN( 21 ), NULL, NULL, RBT_BLACK } +}; + +#define RANDOM_OPS_TREE( i ) \ + { &random_ops_tree_multiple_ ## i[ 0 ], &random_ops_tree_unique_ ## i[ 0 ] } + +static const test_node_description *const random_ops_trees[][2] = { + RANDOM_OPS_TREE( 1 ), + RANDOM_OPS_TREE( 2 ), + RANDOM_OPS_TREE( 3 ), + RANDOM_OPS_TREE( 4 ), + RANDOM_OPS_TREE( 5 ), + RANDOM_OPS_TREE( 6 ), + RANDOM_OPS_TREE( 7 ), + RANDOM_OPS_TREE( 8 ), + RANDOM_OPS_TREE( 9 ), + RANDOM_OPS_TREE( 10 ), + RANDOM_OPS_TREE( 11 ), + RANDOM_OPS_TREE( 12 ), + RANDOM_OPS_TREE( 13 ), + RANDOM_OPS_TREE( 14 ), + RANDOM_OPS_TREE( 15 ), + RANDOM_OPS_TREE( 16 ), + RANDOM_OPS_TREE( 17 ), + RANDOM_OPS_TREE( 18 ), + RANDOM_OPS_TREE( 19 ), + RANDOM_OPS_TREE( 20 ), + RANDOM_OPS_TREE( 21 ), + RANDOM_OPS_TREE( 22 ), + RANDOM_OPS_TREE( 23 ), + RANDOM_OPS_TREE( 24 ), + RANDOM_OPS_TREE( 25 ), + RANDOM_OPS_TREE( 26 ), + RANDOM_OPS_TREE( 27 ), + RANDOM_OPS_TREE( 28 ), + RANDOM_OPS_TREE( 29 ), + RANDOM_OPS_TREE( 30 ), + RANDOM_OPS_TREE( 31 ) +}; + +#define RANDOM_OPS_TREE_COUNT( i ) \ + { \ + RTEMS_ARRAY_SIZE( random_ops_tree_multiple_ ## i ), \ + RTEMS_ARRAY_SIZE( random_ops_tree_unique_ ## i ) \ + } + +static const size_t random_ops_tree_counts[][2] = { + RANDOM_OPS_TREE_COUNT( 1 ), + RANDOM_OPS_TREE_COUNT( 2 ), + RANDOM_OPS_TREE_COUNT( 3 ), + RANDOM_OPS_TREE_COUNT( 4 ), + RANDOM_OPS_TREE_COUNT( 5 ), + RANDOM_OPS_TREE_COUNT( 6 ), + RANDOM_OPS_TREE_COUNT( 7 ), + RANDOM_OPS_TREE_COUNT( 8 ), + RANDOM_OPS_TREE_COUNT( 9 ), + RANDOM_OPS_TREE_COUNT( 10 ), + RANDOM_OPS_TREE_COUNT( 11 ), + RANDOM_OPS_TREE_COUNT( 12 ), + RANDOM_OPS_TREE_COUNT( 13 ), + RANDOM_OPS_TREE_COUNT( 14 ), + RANDOM_OPS_TREE_COUNT( 15 ), + RANDOM_OPS_TREE_COUNT( 16 ), + RANDOM_OPS_TREE_COUNT( 17 ), + RANDOM_OPS_TREE_COUNT( 18 ), + RANDOM_OPS_TREE_COUNT( 19 ), + RANDOM_OPS_TREE_COUNT( 20 ), + RANDOM_OPS_TREE_COUNT( 21 ), + RANDOM_OPS_TREE_COUNT( 22 ), + RANDOM_OPS_TREE_COUNT( 23 ), + RANDOM_OPS_TREE_COUNT( 24 ), + RANDOM_OPS_TREE_COUNT( 25 ), + RANDOM_OPS_TREE_COUNT( 26 ), + RANDOM_OPS_TREE_COUNT( 27 ), + RANDOM_OPS_TREE_COUNT( 28 ), + RANDOM_OPS_TREE_COUNT( 29 ), + RANDOM_OPS_TREE_COUNT( 30 ), + RANDOM_OPS_TREE_COUNT( 31 ) +}; + +static uint32_t simple_random( uint32_t v ) +{ + v *= 1664525; + v += 1013904223; + + return v; +} + +static void random_ops( size_t n, bool unique ) +{ + visitor_context ctx = { + 0, + random_ops_tree_counts[ n - 1 ][ unique ], + random_ops_trees[ n - 1 ][ unique ] + }; + rtems_rbtree_control tree; + test_node *nodes = &node_array[ 0 ]; + size_t m = n * n * n; + size_t s = unique ? 1 : 2; + uint32_t v = 0xdeadbeef; + size_t i; + + rtems_rbtree_initialize_empty( &tree ); + + memset( nodes, 0, n * sizeof( *nodes ) ); + + for ( i = 0; i < n; ++i ) { + nodes[ i ].key = (int) ( i / s ); + } + + for ( i = 0; i < m; ++i ) { + size_t j = ( v >> 13 ) % n; + test_node *tn = &nodes[ j ]; + + if ( tn->id == 0 ) { + tn->id = 1; + rtems_rbtree_insert( &tree, &tn->Node, test_compare_function, unique ); + } else { + tn->id = 0; + rtems_rbtree_extract( &tree, &tn->Node ); + } + + rtems_test_assert( rb_assert( tree.root ) != -1 ); + + v = simple_random( v ); + } + + _RBTree_Iterate( &tree, RBT_RIGHT, visit_nodes, &ctx ); + rtems_test_assert( ctx.current == ctx.count ); +} + +static void test_rbtree_random_ops( void ) +{ + size_t n; + + puts( "INIT - Random operations" ); + + for ( n = 1; n < RTEMS_ARRAY_SIZE( random_ops_trees ); ++n ) { + random_ops( n, true ); + random_ops( n, false ); + } +} + rtems_task Init( rtems_task_argument ignored ) { rtems_rbtree_control rbtree1; @@ -1387,6 +2216,7 @@ rtems_task Init( rtems_task_argument ignored ) } test_rbtree_min_max(); + test_rbtree_random_ops(); TEST_END(); rtems_test_exit(0); diff --git a/testsuites/sptests/sprbtree01/sprbtree01.scn b/testsuites/sptests/sprbtree01/sprbtree01.scn index 73491be..a18a17f 100644 --- a/testsuites/sptests/sprbtree01/sprbtree01.scn +++ b/testsuites/sptests/sprbtree01/sprbtree01.scn @@ -32,4 +32,5 @@ INIT - Verify rtems_rbtree_insert with 100 nodes value [99,0] INIT - Verify rtems_rbtree_find in a duplicate tree INIT - Removing 100 nodes INIT - Verify min/max node updates +INIT - Random operations *** END OF TEST SPRBTREE 1 *** From sebh at rtems.org Mon Aug 11 06:02:44 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 11 Aug 2014 01:02:44 -0500 Subject: [rtems commit] bsp/altera-cyclone-v: Add socal from hwlib. Message-ID: <20140811060246.78B90700340@git.rtems.org> Module: rtems Branch: master Commit: 1642d27e4c0b0f057430f5a5a3d00209db1aa1ca Changeset: http://git.rtems.org/rtems/commit/?id=1642d27e4c0b0f057430f5a5a3d00209db1aa1ca Author: Christian Mauderer Date: Fri Jul 18 12:29:29 2014 +0200 bsp/altera-cyclone-v: Add socal from hwlib. Some of the headers from the hwlib need the files from the socal subdirectory. --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 17 +++++++- .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 45 ++++++++++++++++++++ 2 files changed, 60 insertions(+), 2 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index 6d7115b..e92e728 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -10,6 +10,7 @@ ACLOCAL_AMFLAGS = -I ../../../../aclocal include $(top_srcdir)/../../../../automake/compile.am include_bspdir = $(includedir)/bsp +include_bsp_socaldir = $(includedir)/bsp/socal include_libcpudir = $(includedir)/libcpu dist_project_lib_DATA = bsp_specs @@ -27,6 +28,8 @@ nodist_include_HEADERS = ../../shared/include/coverhd.h \ nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h include_bsp_HEADERS = +include_bsp_socal_HEADERS = + include_bsp_HEADERS += ../../shared/include/utility.h include_bsp_HEADERS += ../../shared/include/irq-generic.h include_bsp_HEADERS += ../../shared/include/irq-info.h @@ -71,8 +74,18 @@ include_bsp_HEADERS += hwlib/include/hwlib.h #include_bsp_HEADERS += hwlib/include/alt_watchdog.h #The following Altera hwlib headers would be problematic with RTEMS: #include_bsp_HEADERS += hwlib/include/alt_interrupt.h -#All header files from hwlib/include/socal are regarded as BSP -#internal and thus not installed + +# Some of the headers from hwlib need the files from socal. Install them. +include_bsp_socal_HEADERS += hwlib/include/socal/alt_clkmgr.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_gpio.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_i2c.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_l3.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_rstmgr.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_sdr.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_sysmgr.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_uart.h +include_bsp_socal_HEADERS += hwlib/include/socal/hps.h +include_bsp_socal_HEADERS += hwlib/include/socal/socal.h include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 3f83665..8873d31 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -33,6 +33,11 @@ $(PROJECT_INCLUDE)/bsp/$(dirstamp): @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) +$(PROJECT_INCLUDE)/bsp/socal/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp/socal + @: > $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) @@ -174,6 +179,46 @@ $(PROJECT_INCLUDE)/bsp/hwlib.h: hwlib/include/hwlib.h $(PROJECT_INCLUDE)/bsp/$(d $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwlib.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwlib.h +$(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h: hwlib/include/socal/alt_clkmgr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h: hwlib/include/socal/alt_gpio.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_i2c.h: hwlib/include/socal/alt_i2c.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_i2c.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_i2c.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_l3.h: hwlib/include/socal/alt_l3.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_l3.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_l3.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h: hwlib/include/socal/alt_rstmgr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_sdr.h: hwlib/include/socal/alt_sdr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_sdr.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_sdr.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_sysmgr.h: hwlib/include/socal/alt_sysmgr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_sysmgr.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_sysmgr.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_uart.h: hwlib/include/socal/alt_uart.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_uart.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_uart.h + +$(PROJECT_INCLUDE)/bsp/socal/hps.h: hwlib/include/socal/hps.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/hps.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/hps.h + +$(PROJECT_INCLUDE)/bsp/socal/socal.h: hwlib/include/socal/socal.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/socal.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/socal.h + $(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h From sebh at rtems.org Mon Aug 11 06:02:44 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 11 Aug 2014 01:02:44 -0500 Subject: [rtems commit] bsp/altera-cyclone-v: Add RTC driver. Message-ID: <20140811060246.0AFD5700121@git.rtems.org> Module: rtems Branch: master Commit: 81329f9ecf7c289c67cf0ff7ee54898d9311429e Changeset: http://git.rtems.org/rtems/commit/?id=81329f9ecf7c289c67cf0ff7ee54898d9311429e Author: Christian Mauderer Date: Tue Jul 15 16:20:37 2014 +0200 bsp/altera-cyclone-v: Add RTC driver. --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 4 + c/src/lib/libbsp/arm/altera-cyclone-v/README | 15 +- .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 6 +- c/src/lib/libbsp/arm/altera-cyclone-v/rtc/rtc.c | 360 ++++++++++++++++++++ 4 files changed, 381 insertions(+), 4 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index 01b0272..939ccc7 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -200,6 +200,10 @@ libbsp_a_SOURCES += i2c/i2cdrv.c libbsp_a_SOURCES += i2c/i2cdrv-config.c include_bsp_HEADERS += include/i2cdrv.h +# RTC +libbsp_a_SOURCES += ../../shared/tod.c +libbsp_a_SOURCES += rtc/rtc.c + # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/README b/c/src/lib/libbsp/arm/altera-cyclone-v/README index 575b72e..0a5bc05 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/README +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/README @@ -1,3 +1,16 @@ +Overview +-------- Evaluation board for this BSP: - Cyclone V SoC FPGA Development Kit -- DK-DEV-5CSXC6N/ES-0L \ No newline at end of file +- DK-DEV-5CSXC6N/ES-0L + +RTC +--- +The evaluation board contains a DS1339C RTC connected to I2C0. To use it you +have to set the following options: + + #define CONFIGURE_APPLICATION_NEEDS_RTC_DRIVER + #define CONFIGURE_BSP_PREREQUISITE_DRIVERS I2C_DRIVER_TABLE_ENTRY + +Additional there has to be one free file descriptor to access the i2c. Set the +CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS accordingly. diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index c13ef6a..4e3b586 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/rtc/rtc.c b/c/src/lib/libbsp/arm/altera-cyclone-v/rtc/rtc.c new file mode 100644 index 0000000..3c18d1c --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/rtc/rtc.c @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* + * Driver for the DS1339 RTC. + * + * Please note the following points: + * - The day of week is ignored. + * - The century bit is interpreted the following way: + * - century not set: TOD_BASE_YEAR .. 1999 + * - century set: 2000 .. 2099 + * - century not set: 2100 .. (TOD_BASE_YEAR + 200) + */ + +#include +#include +#include +#include +#include +#include +#include + +#define ALTERA_CYCLONE_V_RTC_NUMBER 1 + +#define DS1339_I2C_ADDRESS 0x68 +#define DS1339_I2C_BUS_DEVICE "/dev/i2c0" + +#define DS1339_ADDR_CTRL 0x0E +#define DS1339_CTRL_EOSC 0x80 +#define DS1339_CTRL_BBSQI 0x20 +#define DS1339_CTRL_RS2 0x10 +#define DS1339_CTRL_RS1 0x08 +#define DS1339_CTRL_INTCN 0x04 +#define DS1339_CTRL_A2IE 0x02 +#define DS1339_CTRL_A1IE 0x01 + +#define DS1339_CTRL_DEFAULT (0x00) + +#define DS1339_ADDR_TIME 0x00 +#define DS1339_ADDR_STATUS 0x0F +#define DS1339_STATUS_OSF 0x80 +#define DS1339_STATUS_A2F 0x02 +#define DS1339_STATUS_A1F 0x01 + +#define DS1339_STATUS_CLEAR (0x00) + +typedef struct { + uint8_t seconds; + uint8_t minutes; + uint8_t hours; +#define DS1339_HOURS_12_24_FLAG 0x40 +#define DS1339_HOURS_AM_PM_FLAG_OR_20_HOURS 0x20 +#define DS1339_HOURS_10_HOURS 0x10 + uint8_t weekday; + uint8_t date; + uint8_t month; +#define DS1339_MONTH_CENTURY 0x80 + uint8_t year; +} ds1339_time_t; + +/* The longest write transmission is writing the time + one address bit */ +#define DS1339_MAX_WRITE_SIZE (sizeof(ds1339_time_t) + 1) + +/* Functions for converting the fields */ +static unsigned int get_seconds (ds1339_time_t *time) { + uint8_t tens = time->seconds >> 4; + uint8_t ones = time->seconds & 0x0F; + return tens * 10 + ones; +} + +static unsigned int get_minutes (ds1339_time_t *time) { + uint8_t tens = time->minutes >> 4; + uint8_t ones = time->minutes & 0x0F; + return tens * 10 + ones; +} + +static unsigned int get_hours (ds1339_time_t *time) { + uint8_t value = time->hours & 0x0F; + + if(time->hours & DS1339_HOURS_10_HOURS) { + value += 10; + } + if(time->hours & DS1339_HOURS_AM_PM_FLAG_OR_20_HOURS) { + if(time->hours & DS1339_HOURS_12_24_FLAG) { + value += 12; + } else { + value += 20; + } + } + + return value; +} + +static unsigned int get_day_of_month (ds1339_time_t *time) { + uint8_t tens = time->date >> 4; + uint8_t ones = time->date & 0x0F; + return tens * 10 + ones; +} + +static unsigned int get_month (ds1339_time_t *time) { + uint8_t tens = (time->month >> 4) & 0x07; + uint8_t ones = time->month & 0x0F; + return tens * 10 + ones; +} + +static unsigned int get_year (ds1339_time_t *time) { + unsigned int year = 1900; + year += (time->year >> 4) * 10; + year += time->year & 0x0F; + if(time->month & DS1339_MONTH_CENTURY) { + year += 100; + } + if(year < TOD_BASE_YEAR) { + year += 200; + } + return year; +} + +static void set_time ( + ds1339_time_t *time, + unsigned int second, + unsigned int minute, + unsigned int hour, + unsigned int day, + unsigned int month, + unsigned int year +) { + unsigned int tens; + unsigned int ones; + uint8_t century = 0; + + tens = second / 10; + ones = second % 10; + time->seconds = tens << 4 | ones; + + tens = minute / 10; + ones = minute % 10; + time->minutes = tens << 4 | ones; + + tens = hour / 10; + ones = hour % 10; + time->hours = tens << 4 | ones; + + /* Weekday is not used. Therefore it can be set to an arbitrary valid value */ + time->weekday = 1; + + tens = day / 10; + ones = day % 10; + time->date = tens << 4 | ones; + + tens = month / 10; + ones = month % 10; + if(year >= 2000 && year < 2100) { + century = DS1339_MONTH_CENTURY; + } + time->month = century | tens << 4 | ones; + + tens = (year % 100) / 10; + ones = year % 10; + time->year = tens << 4 | ones; +} + +static rtems_status_code ds1339_open_file(int *fd) +{ + int rv = 0; + rtems_status_code sc = RTEMS_SUCCESSFUL; + + *fd = open(DS1339_I2C_BUS_DEVICE, O_RDWR); + if ( *fd == -1 ) { + sc = RTEMS_IO_ERROR; + } + + if ( sc == RTEMS_SUCCESSFUL ) { + rv = ioctl(*fd, I2C_IOC_SET_SLAVE_ADDRESS, DS1339_I2C_ADDRESS); + if ( rv == -1 ) { + sc = RTEMS_IO_ERROR; + } + } + + return sc; +} + +/* Read size bytes from ds1339 register address addr to buf. */ +static rtems_status_code ds1339_read(uint8_t addr, void *buf, size_t size) +{ + int fd = -1; + int rv = 0; + rtems_status_code sc = RTEMS_SUCCESSFUL; + + sc = ds1339_open_file(&fd); + + if ( sc == RTEMS_SUCCESSFUL ) { + rv = write(fd, &addr, sizeof(addr)); + if ( rv != sizeof(addr) ) { + sc = RTEMS_IO_ERROR; + } + } + + if ( sc == RTEMS_SUCCESSFUL ) { + rv = read(fd, buf, size); + if ( rv != size ) { + sc = RTEMS_IO_ERROR; + } + } + + rv = close(fd); + if ( rv != 0 ) { + sc = RTEMS_IO_ERROR; + } + + return sc; +} + +/* Write size bytes from buf to ds1339 register address addr. */ +static rtems_status_code ds1339_write(uint8_t addr, void *buf, size_t size) +{ + int fd = -1; + int rv = 0; + rtems_status_code sc = RTEMS_SUCCESSFUL; + /* The driver never writes many bytes. Therefore it should be less expensive + * to reserve the maximum number of bytes that will be written in one go than + * use a malloc. */ + uint8_t local_buf[DS1339_MAX_WRITE_SIZE]; + int write_size = size + 1; + + assert(write_size <= DS1339_MAX_WRITE_SIZE); + + local_buf[0] = addr; + memcpy(&local_buf[1], buf, size); + + sc = ds1339_open_file(&fd); + + if ( sc == RTEMS_SUCCESSFUL ) { + rv = write(fd, local_buf, write_size); + if ( rv != write_size ) { + sc = RTEMS_IO_ERROR; + } + } + + rv = close(fd); + if ( rv != 0 ) { + sc = RTEMS_IO_ERROR; + } + + return RTEMS_SUCCESSFUL; +} + +static void altera_cyclone_v_rtc_initialize(int minor) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + uint8_t status = 0; + + /* Check RTC valid */ + sc = ds1339_read(DS1339_ADDR_STATUS, &status, sizeof(status)); + assert(sc == RTEMS_SUCCESSFUL); + if(status & DS1339_STATUS_OSF) { + /* RTC has been stopped. Initialise it. */ + ds1339_time_t time; + + uint8_t write = DS1339_CTRL_DEFAULT; + sc = ds1339_write(DS1339_ADDR_CTRL, &write, sizeof(write)); + assert(sc == RTEMS_SUCCESSFUL); + + write = DS1339_STATUS_CLEAR; + sc = ds1339_write(DS1339_ADDR_STATUS, &write, sizeof(write)); + assert(sc == RTEMS_SUCCESSFUL); + + set_time(&time, 0, 0, 0, 1, 1, TOD_BASE_YEAR); + sc = ds1339_write(DS1339_ADDR_TIME, &time, sizeof(time)); + assert(sc == RTEMS_SUCCESSFUL); + } +} + +static int altera_cyclone_v_rtc_get_time(int minor, rtems_time_of_day *tod) +{ + ds1339_time_t time; + rtems_status_code sc = RTEMS_SUCCESSFUL; + rtems_time_of_day temp_tod; + + sc = ds1339_read(DS1339_ADDR_TIME, &time, sizeof(time)); + + if ( sc == RTEMS_SUCCESSFUL ) { + temp_tod.ticks = 0; + temp_tod.second = get_seconds(&time); + temp_tod.minute = get_minutes(&time); + temp_tod.hour = get_hours(&time); + temp_tod.day = get_day_of_month(&time); + temp_tod.month = get_month(&time); + temp_tod.year = get_year(&time); + + if ( _TOD_Validate(&temp_tod) ) { + memcpy(tod, &temp_tod, sizeof(temp_tod)); + } else { + sc = RTEMS_INVALID_CLOCK; + } + } + + return -sc; +} + +static int altera_cyclone_v_rtc_set_time(int minor, const rtems_time_of_day *tod) +{ + ds1339_time_t time; + rtems_status_code sc = RTEMS_SUCCESSFUL; + + set_time ( + &time, + tod->second, + tod->minute, + tod->hour, + tod->day, + tod->month, + tod->year + ); + + sc = ds1339_write(DS1339_ADDR_TIME, &time, sizeof(time)); + + return -sc; +} + +static bool altera_cyclone_v_rtc_probe(int minor) +{ + /* FIXME: Probe for i2c device */ + return true; +} + +const rtc_fns altera_cyclone_v_rtc_ops = { + .deviceInitialize = altera_cyclone_v_rtc_initialize, + .deviceGetTime = altera_cyclone_v_rtc_get_time, + .deviceSetTime = altera_cyclone_v_rtc_set_time +}; + +size_t RTC_Count = ALTERA_CYCLONE_V_RTC_NUMBER; + +rtems_device_minor_number RTC_Minor = 0; + +rtc_tbl RTC_Table [ALTERA_CYCLONE_V_RTC_NUMBER] = { + { + .sDeviceName = "/dev/rtc", + .deviceType = RTC_CUSTOM, + .pDeviceFns = &altera_cyclone_v_rtc_ops, + .deviceProbe = altera_cyclone_v_rtc_probe, + .pDeviceParams = NULL, + .ulCtrlPort1 = 0, + .ulDataPort = 0, + .getRegister = NULL, + .setRegister = NULL + } +}; From sebh at rtems.org Tue Aug 12 18:25:25 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 12 Aug 2014 13:25:25 -0500 Subject: [rtems commit] arm: Add support for FPv4-SP floating point unit Message-ID: <20140812182526.1721970098F@git.rtems.org> Module: rtems Branch: master Commit: 8ae373235b316ff10c3b6f30ac1f2efed9bec011 Changeset: http://git.rtems.org/rtems/commit/?id=8ae373235b316ff10c3b6f30ac1f2efed9bec011 Author: Sebastian Huber Date: Sun Aug 10 18:36:30 2014 +0200 arm: Add support for FPv4-SP floating point unit This floating point unit is available in Cortex-M4 processors and defined by ARMv7-M. This adds basic support for other VFP-D16 variants. --- c/src/lib/libbsp/arm/shared/start/start.S | 15 ++++++++ cpukit/score/cpu/arm/arm-context-validate.S | 31 ++++++++++------ .../score/cpu/arm/arm-context-volatile-clobber.S | 8 +++-- cpukit/score/cpu/arm/arm_exc_interrupt.S | 12 ++++-- cpukit/score/cpu/arm/armv4-exception-default.S | 24 ++++++++++--- cpukit/score/cpu/arm/armv7m-context-switch.c | 13 ++++++- cpukit/score/cpu/arm/armv7m-exception-default.c | 38 ++++++++++++++++++- cpukit/score/cpu/arm/armv7m-isr-dispatch.c | 30 +++++++++++++--- cpukit/score/cpu/arm/cpu.c | 2 +- cpukit/score/cpu/arm/cpu_asm.S | 4 +- cpukit/score/cpu/arm/rtems/score/arm.h | 17 +++++++-- cpukit/score/cpu/arm/rtems/score/armv7m.h | 37 ++++++++++++++++++- cpukit/score/cpu/arm/rtems/score/cpu.h | 8 ++-- 13 files changed, 194 insertions(+), 45 deletions(-) diff --git a/c/src/lib/libbsp/arm/shared/start/start.S b/c/src/lib/libbsp/arm/shared/start/start.S index 096e9bd..63b3250 100644 --- a/c/src/lib/libbsp/arm/shared/start/start.S +++ b/c/src/lib/libbsp/arm/shared/start/start.S @@ -266,6 +266,8 @@ twiddle: #elif defined(ARM_MULTILIB_ARCH_V7M) +#include + .syntax unified .extern bsp_stack_main_end @@ -300,6 +302,19 @@ bsp_start_vector_table_end: _start: +#ifdef ARM_MULTILIB_VFP + /* + * Enable CP10 and CP11 coprocessors for privileged and user mode in + * CPACR (bits 20-23). Ensure that write to register completes. + */ + ldr r0, =ARMV7M_CPACR + ldr r1, [r0] + orr r1, r1, #(0xf << 20) + str r1, [r0] + dsb + isb +#endif + ldr sp, =bsp_stack_main_end ldr lr, =bsp_start_hook_0_done + 1 b bsp_start_hook_0 diff --git a/cpukit/score/cpu/arm/arm-context-validate.S b/cpukit/score/cpu/arm/arm-context-validate.S index f2772b4..fdfb6c1 100644 --- a/cpukit/score/cpu/arm/arm-context-validate.S +++ b/cpukit/score/cpu/arm/arm-context-validate.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -29,7 +29,7 @@ #define FRAME_OFFSET_R11 28 #define FRAME_OFFSET_LR 32 -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP #define FRAME_OFFSET_D8 40 #define FRAME_OFFSET_D9 48 #define FRAME_OFFSET_D10 56 @@ -71,7 +71,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) mov r1, lr str r1, [sp, #FRAME_OFFSET_LR] -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP vstr d8, [sp, #FRAME_OFFSET_D8] vstr d9, [sp, #FRAME_OFFSET_D9] vstr d10, [sp, #FRAME_OFFSET_D10] @@ -96,11 +96,15 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) .endm -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP /* R3 contains the FPSCR */ vmrs r3, FPSCR movs r4, #0x001f +#ifdef ARM_MULTILIB_ARCH_V7M + movt r4, #0xf000 +#else movt r4, #0xf800 +#endif bic r3, r3, r4 and r4, r4, r0 orr r3, r3, r4 @@ -120,7 +124,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) fill_register r12 fill_register lr -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP .macro fill_vfp_register reg add r1, r1, #1 vmov \reg, r1, r1 @@ -142,6 +146,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) fill_vfp_register d13 fill_vfp_register d14 fill_vfp_register d15 +#ifdef ARM_MULTILIB_VFP_D32 fill_vfp_register d16 fill_vfp_register d17 fill_vfp_register d18 @@ -158,7 +163,8 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) fill_vfp_register d29 fill_vfp_register d30 fill_vfp_register d31 -#endif +#endif /* ARM_MULTILIB_VFP_D32 */ +#endif /* ARM_MULTILIB_VFP */ /* Check */ check: @@ -174,7 +180,7 @@ check: mov r1, r0 -#ifndef ARM_MULTILIB_VFP_D32 +#ifndef ARM_MULTILIB_VFP check_register r3 #endif @@ -189,7 +195,7 @@ check: check_register r12 check_register lr -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP b check_vfp #endif @@ -217,7 +223,7 @@ restore: ldr r1, [sp, #FRAME_OFFSET_LR] mov lr, r1 -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP vldr d8, [sp, #FRAME_OFFSET_D8] vldr d9, [sp, #FRAME_OFFSET_D9] vldr d10, [sp, #FRAME_OFFSET_D10] @@ -234,7 +240,7 @@ restore: FUNCTION_END(_CPU_Context_validate) -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP check_vfp: .macro check_vfp_register reg @@ -270,6 +276,7 @@ check_vfp: check_vfp_register d13 check_vfp_register d14 check_vfp_register d15 +#ifdef ARM_MULTILIB_VFP_D32 check_vfp_register d16 check_vfp_register d17 check_vfp_register d18 @@ -286,6 +293,7 @@ check_vfp: check_vfp_register d29 check_vfp_register d30 check_vfp_register d31 +#endif /* ARM_MULTILIB_VFP_D32 */ /* Restore r4 and r5 */ mov r1, r0 @@ -293,5 +301,4 @@ check_vfp: fill_register r5 b check - -#endif +#endif /* ARM_MULTILIB_VFP */ diff --git a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S index 459acba..7970b8e 100644 --- a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S +++ b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -27,7 +27,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber) mov \reg, r0 .endm -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP vmrs r1, FPSCR movs r2, #0x001f movt r2, #0xf800 @@ -49,6 +49,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber) clobber_vfp_register d5 clobber_vfp_register d6 clobber_vfp_register d7 +#ifdef ARM_MULTILIB_VFP_D32 clobber_vfp_register d16 clobber_vfp_register d17 clobber_vfp_register d18 @@ -65,7 +66,8 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber) clobber_vfp_register d29 clobber_vfp_register d30 clobber_vfp_register d31 -#endif +#endif /* ARM_MULTILIB_VFP_D32 */ +#endif /* ARM_MULTILIB_VFP */ clobber_register r1 clobber_register r2 diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S b/cpukit/score/cpu/arm/arm_exc_interrupt.S index e8026c8..7930c32 100644 --- a/cpukit/score/cpu/arm/arm_exc_interrupt.S +++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S @@ -75,13 +75,15 @@ _ARMV4_Exception_interrupt: stmdb sp!, CONTEXT_LIST stmdb sp!, {SP_OF_INTERRUPTED_CONTEXT, lr} -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP /* Save VFP context */ vmrs r0, FPSCR vstmdb sp!, {d0-d7} +#ifdef ARM_MULTILIB_VFP_D32 vstmdb sp!, {d16-d31} - stmdb sp!, {r0, r1} #endif + stmdb sp!, {r0, r1} +#endif /* ARM_MULTILIB_VFP */ /* Get per-CPU control of current processor */ GET_SELF_CPU_CONTROL SELF_CPU_CONTROL, r1 @@ -166,13 +168,15 @@ thread_dispatch_done: /* Switch to ARM instructions if necessary */ SWITCH_FROM_THUMB_TO_ARM -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP /* Restore VFP context */ ldmia sp!, {r0, r1} +#ifdef ARM_MULTILIB_VFP_D32 vldmia sp!, {d16-d31} +#endif vldmia sp!, {d0-d7} vmsr FPSCR, r0 -#endif +#endif /* ARM_MULTILIB_VFP */ /* Restore SP_OF_INTERRUPTED_CONTEXT register and link register */ ldmia sp!, {SP_OF_INTERRUPTED_CONTEXT, lr} diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S index 950ad67..a0ee46c 100644 --- a/cpukit/score/cpu/arm/armv4-exception-default.S +++ b/cpukit/score/cpu/arm/armv4-exception-default.S @@ -118,13 +118,18 @@ save_more_context: /* Argument for high level handler */ mov r0, sp -#ifdef ARM_MULTILIB_VFP_D32 + /* Clear VFP context pointer */ + add r3, sp, #ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET + mov r1, #0 + str r1, [r3] + +#ifdef ARM_MULTILIB_VFP /* Ensure that the FPU is enabled */ vmrs r1, FPEXC tst r1, #(1 << 30) - beq fpu_save_done + beq 1f - add r3, sp, #ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET + /* Save VFP context */ sub sp, #(ARM_VFP_CONTEXT_SIZE + 4) add r4, sp, #4 bic r4, r4, #7 @@ -132,10 +137,19 @@ save_more_context: vmrs r2, FPSCR stmia r4!, {r1-r2} vstmia r4!, {d0-d15} +#ifdef ARM_MULTILIB_VFP_D32 vstmia r4!, {d16-d31} - -fpu_save_done: +#else + mov r1, #0 + mov r2, #0 + adds r3, r4, #128 +2: + stmia r4!, {r1-r2} + cmp r4, r3 + bne 2b #endif +1: +#endif /* ARM_MULTILIB_VFP */ /* Call high level handler */ SWITCH_FROM_ARM_TO_THUMB r1 diff --git a/cpukit/score/cpu/arm/armv7m-context-switch.c b/cpukit/score/cpu/arm/armv7m-context-switch.c index eabf2c8..359a1a7 100644 --- a/cpukit/score/cpu/arm/armv7m-context-switch.c +++ b/cpukit/score/cpu/arm/armv7m-context-switch.c @@ -5,7 +5,7 @@ */ /* - * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * Copyright (c) 2011-2014 Sebastian Huber. All rights reserved. * * embedded brains GmbH * Obere Lagerstr. 30 @@ -37,17 +37,26 @@ void __attribute__((naked)) _CPU_Context_switch( "movt r2, #:upper16:_Per_CPU_Information\n" "ldr r3, [r2, %[isrpcpuoff]]\n" "stm r0, {r4-r11, lr}\n" +#ifdef ARM_MULTILIB_VFP + "add r4, r0, %[d8off]\n" + "vstm r4, {d8-d15}\n" +#endif "str sp, [r0, %[spctxoff]]\n" "str r3, [r0, %[isrctxoff]]\n" "ldr r3, [r1, %[isrctxoff]]\n" "ldr sp, [r1, %[spctxoff]]\n" +#ifdef ARM_MULTILIB_VFP + "add r4, r1, %[d8off]\n" + "vldm r4, {d8-d15}\n" +#endif "ldm r1, {r4-r11, lr}\n" "str r3, [r2, %[isrpcpuoff]]\n" "bx lr\n" : : [spctxoff] "J" (offsetof(Context_Control, register_sp)), [isrctxoff] "J" (offsetof(Context_Control, isr_nest_level)), - [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level)) + [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level)), + [d8off] "J" (ARM_CONTEXT_CONTROL_D8_OFFSET) ); } diff --git a/cpukit/score/cpu/arm/armv7m-exception-default.c b/cpukit/score/cpu/arm/armv7m-exception-default.c index dde1014..e890cdf 100644 --- a/cpukit/score/cpu/arm/armv7m-exception-default.c +++ b/cpukit/score/cpu/arm/armv7m-exception-default.c @@ -38,15 +38,49 @@ void __attribute__((naked)) _ARMV7M_Exception_default( void ) "stm r1, {r3-r5}\n" "mrs r1, ipsr\n" "str r1, [sp, %[cpuvecoff]]\n" + + /* Argument for high level handler */ "mov r0, sp\n" + + /* Clear VFP context pointer */ + "add r3, sp, %[cpuvfpoff]\n" + "mov r1, #0\n" + "str r1, [r3]\n" + +#ifdef ARM_MULTILIB_VFP + /* Ensure that the FPU is enabled */ + "ldr r4, =%[cpacr]\n" + "tst r4, #(0xf << 20)\n" + "bne 1f\n" + + /* Save VFP context */ + "sub sp, %[vfpsz]\n" + "add r4, sp, #4\n" + "bic r4, r4, #7\n" + "str r4, [r3]\n" + "vmrs r2, FPSCR\n" + "stmia r4!, {r1-r2}\n" + "vstmia r4!, {d0-d15}\n" + "mov r1, #0\n" + "mov r2, #0\n" + "adds r3, r4, #128\n" + "2:\n" + "stmia r4!, {r1-r2}\n" + "cmp r4, r3\n" + "bne 2b\n" + "1:\n" +#endif + "b _ARM_Exception_default\n" : : [cpufsz] "i" (sizeof(CPU_Exception_frame)), [v7mfsz] "i" (sizeof(ARMV7M_Exception_frame)), - [cpuspoff] "J" (offsetof(CPU_Exception_frame, register_sp)), [cpulroff] "i" (offsetof(CPU_Exception_frame, register_lr)), [v7mlroff] "i" (offsetof(ARMV7M_Exception_frame, register_lr)), - [cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector)) + [cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector)), + [cpuvfpoff] "i" (ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET), + [cpacr] "i" (ARMV7M_CPACR), + [vfpsz] "i" (ARM_VFP_CONTEXT_SIZE) ); } diff --git a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c index 048ffa8..e460e9c 100644 --- a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c +++ b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c @@ -5,7 +5,7 @@ */ /* - * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * Copyright (c) 2011-2014 Sebastian Huber. All rights reserved. * * embedded brains GmbH * Obere Lagerstr. 30 @@ -37,13 +37,27 @@ static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void ) ); } +static void _ARMV7M_Trigger_lazy_floating_point_context_save( void ) +{ +#ifdef ARM_MULTILIB_VFP + __asm__ volatile ( + "vmov.f32 s0, s0\n" + ); +#endif +} + void _ARMV7M_Pendable_service_call( void ) { + ARMV7M_Exception_frame *ef; + _ISR_Nest_level = 1; + _ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR; - ARMV7M_Exception_frame *ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP(); + _ARMV7M_Trigger_lazy_floating_point_context_save(); + + ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP(); --ef; - _ARMV7M_Set_PSP((uint32_t) ef); + _ARMV7M_Set_PSP( (uint32_t) ef ); /* * According to "ARMv7-M Architecture Reference Manual" section B1.5.6 @@ -57,11 +71,17 @@ void _ARMV7M_Pendable_service_call( void ) void _ARMV7M_Supervisor_call( void ) { - ARMV7M_Exception_frame *ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP(); + ARMV7M_Exception_frame *ef; + + _ARMV7M_Trigger_lazy_floating_point_context_save(); + + ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP(); ++ef; - _ARMV7M_Set_PSP((uint32_t) ef); + _ARMV7M_Set_PSP( (uint32_t) ef ); + _ISR_Nest_level = 0; RTEMS_COMPILER_MEMORY_BARRIER(); + if ( _Thread_Dispatch_necessary ) { _ARMV7M_Pendable_service_call(); } diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c index 089826e..9942c4a 100644 --- a/cpukit/score/cpu/arm/cpu.c +++ b/cpukit/score/cpu/arm/cpu.c @@ -35,7 +35,7 @@ #include #include -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP RTEMS_STATIC_ASSERT( offsetof( Context_Control, register_d8 ) == ARM_CONTEXT_CONTROL_D8_OFFSET, ARM_CONTEXT_CONTROL_D8_OFFSET diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S index d4355b4..344512b 100644 --- a/cpukit/score/cpu/arm/cpu_asm.S +++ b/cpukit/score/cpu/arm/cpu_asm.S @@ -58,7 +58,7 @@ DEFINE_FUNCTION_ARM(_CPU_Context_switch) mrs r2, CPSR stmia r0, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14} -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP add r3, r0, #ARM_CONTEXT_CONTROL_D8_OFFSET vstm r3, {d8-d15} #endif @@ -101,7 +101,7 @@ DEFINE_FUNCTION_ARM(_CPU_Context_switch) mcr p15, 0, r3, c13, c0, 3 #endif -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP add r3, r1, #ARM_CONTEXT_CONTROL_D8_OFFSET vldm r3, {d8-d15} #endif diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h index a105f17..586a8cb 100644 --- a/cpukit/score/cpu/arm/rtems/score/arm.h +++ b/cpukit/score/cpu/arm/rtems/score/arm.h @@ -50,10 +50,19 @@ extern "C" { #define ARM_MULTILIB_HAS_THREAD_ID_REGISTER #endif -#if defined(__ARM_NEON__) - #define ARM_MULTILIB_VFP_D32 -#elif !defined(__SOFTFP__) - #error "FPU support not implemented" +#if !defined(__SOFTFP__) + #if defined(__ARM_NEON__) + #define ARM_MULTILIB_VFP_D32 + #elif defined(__VFP_FP__) + #define ARM_MULTILIB_VFP_D16 + #else + #error "FPU support not implemented" + #endif +#endif + +#if defined(ARM_MULTILIB_VFP_D16) \ + || defined(ARM_MULTILIB_VFP_D32) + #define ARM_MULTILIB_VFP #endif /* diff --git a/cpukit/score/cpu/arm/rtems/score/armv7m.h b/cpukit/score/cpu/arm/rtems/score/armv7m.h index b545859..c5e473e 100644 --- a/cpukit/score/cpu/arm/rtems/score/armv7m.h +++ b/cpukit/score/cpu/arm/rtems/score/armv7m.h @@ -5,7 +5,7 @@ */ /* - * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * Copyright (c) 2011-2014 Sebastian Huber. All rights reserved. * * embedded brains GmbH * Obere Lagerstr. 30 @@ -29,6 +29,11 @@ extern "C" { #ifdef ARM_MULTILIB_ARCH_V7M +/* Coprocessor Access Control Register, CPACR */ +#define ARMV7M_CPACR 0xe000ed88 + +#ifndef ASM + typedef struct { uint32_t reserved_0; uint32_t ictr; @@ -47,6 +52,26 @@ typedef struct { void *register_lr; void *register_pc; uint32_t register_xpsr; +#ifdef ARM_MULTILIB_VFP + uint32_t register_s0; + uint32_t register_s1; + uint32_t register_s2; + uint32_t register_s3; + uint32_t register_s4; + uint32_t register_s5; + uint32_t register_s6; + uint32_t register_s7; + uint32_t register_s8; + uint32_t register_s9; + uint32_t register_s10; + uint32_t register_s11; + uint32_t register_s12; + uint32_t register_s13; + uint32_t register_s14; + uint32_t register_s15; + uint32_t register_fpscr; + uint32_t reserved; +#endif } ARMV7M_Exception_frame; typedef struct { @@ -97,6 +122,14 @@ typedef struct { uint32_t mmfar; uint32_t bfar; uint32_t afsr; + uint32_t reserved_e000ed40[18]; + uint32_t cpacr; + uint32_t reserved_e000ed8c[106]; + uint32_t fpccr; + uint32_t fpcar; + uint32_t fpdscr; + uint32_t mvfr0; + uint32_t mvfr1; } ARMV7M_SCB; typedef struct { @@ -504,6 +537,8 @@ void _ARMV7M_Pendable_service_call( void ); void _ARMV7M_Supervisor_call( void ); +#endif /* ASM */ + #endif /* ARM_MULTILIB_ARCH_V7M */ #ifdef __cplusplus diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h index ad070df..089fc27 100644 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/rtems/score/cpu.h @@ -8,7 +8,7 @@ * This include file contains information pertaining to the ARM * processor. * - * Copyright (c) 2009-2013 embedded brains GmbH. + * Copyright (c) 2009-2014 embedded brains GmbH. * * Copyright (c) 2007 Ray Xu * @@ -212,12 +212,12 @@ #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 #endif -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 #endif #ifdef RTEMS_SMP - #ifdef ARM_MULTILIB_VFP_D32 + #ifdef ARM_MULTILIB_VFP #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 #else #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 @@ -278,7 +278,7 @@ typedef struct { #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER uint32_t thread_id; #endif -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP uint64_t register_d8; uint64_t register_d9; uint64_t register_d10; From sebh at rtems.org Tue Aug 12 18:25:25 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 12 Aug 2014 13:25:25 -0500 Subject: [rtems commit] bsp/lpc24xx: Add LPC40XX variants Message-ID: <20140812182526.BFA6C700903@git.rtems.org> Module: rtems Branch: master Commit: 6cdc090ff0574a87fbfb17a7095d64583fc9c669 Changeset: http://git.rtems.org/rtems/commit/?id=6cdc090ff0574a87fbfb17a7095d64583fc9c669 Author: Sebastian Huber Date: Sun Aug 10 18:35:27 2014 +0200 bsp/lpc24xx: Add LPC40XX variants --- c/src/lib/libbsp/arm/lpc24xx/Makefile.am | 27 +++++----- c/src/lib/libbsp/arm/lpc24xx/configure.ac | 12 ++-- .../lib/libbsp/arm/lpc24xx/make/custom/lpc40xx.inc | 11 ++++ .../arm/lpc24xx/make/custom/lpc40xx_ea_ram.cfg | 5 ++ .../arm/lpc24xx/make/custom/lpc40xx_ea_rom_int.cfg | 5 ++ c/src/lib/libbsp/arm/lpc24xx/preinstall.am | 56 ++++++++++++++++++++ .../arm/lpc24xx/startup/linkcmds.lpc40xx_ea_ram | 1 + .../lpc24xx/startup/linkcmds.lpc40xx_ea_rom_int | 1 + 8 files changed, 99 insertions(+), 19 deletions(-) diff --git a/c/src/lib/libbsp/arm/lpc24xx/Makefile.am b/c/src/lib/libbsp/arm/lpc24xx/Makefile.am index 3b5c94f..b2fdd5f 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/Makefile.am +++ b/c/src/lib/libbsp/arm/lpc24xx/Makefile.am @@ -66,19 +66,20 @@ libbspstart_a_SOURCES = ../shared/start/start.S project_lib_DATA = start.$(OBJEXT) project_lib_DATA += startup/linkcmds -EXTRA_DIST = -EXTRA_DIST += startup/linkcmds.lpc17xx_ea_ram -EXTRA_DIST += startup/linkcmds.lpc17xx_ea_rom_int -EXTRA_DIST += startup/linkcmds.lpc17xx_plx800_ram -EXTRA_DIST += startup/linkcmds.lpc17xx_plx800_rom_int -EXTRA_DIST += startup/linkcmds.lpc2362 -EXTRA_DIST += startup/linkcmds.lpc23xx_tli800 -EXTRA_DIST += startup/linkcmds.lpc24xx_ea -EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_ram -EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_ext -EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_int -EXTRA_DIST += startup/linkcmds.lpc24xx_plx800_ram -EXTRA_DIST += startup/linkcmds.lpc24xx_plx800_rom_int +project_lib_DATA += startup/linkcmds.lpc17xx_ea_ram +project_lib_DATA += startup/linkcmds.lpc17xx_ea_rom_int +project_lib_DATA += startup/linkcmds.lpc17xx_plx800_ram +project_lib_DATA += startup/linkcmds.lpc17xx_plx800_rom_int +project_lib_DATA += startup/linkcmds.lpc2362 +project_lib_DATA += startup/linkcmds.lpc23xx_tli800 +project_lib_DATA += startup/linkcmds.lpc24xx_ea +project_lib_DATA += startup/linkcmds.lpc24xx_ncs_ram +project_lib_DATA += startup/linkcmds.lpc24xx_ncs_rom_ext +project_lib_DATA += startup/linkcmds.lpc24xx_ncs_rom_int +project_lib_DATA += startup/linkcmds.lpc24xx_plx800_ram +project_lib_DATA += startup/linkcmds.lpc24xx_plx800_rom_int +project_lib_DATA += startup/linkcmds.lpc40xx_ea_ram +project_lib_DATA += startup/linkcmds.lpc40xx_ea_rom_int ############################################################################### # LibBSP # diff --git a/c/src/lib/libbsp/arm/lpc24xx/configure.ac b/c/src/lib/libbsp/arm/lpc24xx/configure.ac index 737501f..e3747d5 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/configure.ac +++ b/c/src/lib/libbsp/arm/lpc24xx/configure.ac @@ -28,17 +28,17 @@ RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_MAIN],[main oscillator frequency in Hz]) RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_RTC],[*],[32768U]) RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_RTC],[RTC oscillator frequency in Hz]) -RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc17xx_ea*],[96000000U]) +RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc17xx_ea* | lpc40xx_ea*],[96000000U]) RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc23*],[58982400U]) RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc24xx_plx800_*],[51612800U]) RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[*],[72000000U]) RTEMS_BSPOPTS_HELP([LPC24XX_CCLK],[CPU clock in Hz]) -RTEMS_BSPOPTS_SET([LPC24XX_PCLKDIV],[lpc17xx_ea*],[2U]) +RTEMS_BSPOPTS_SET([LPC24XX_PCLKDIV],[lpc17xx_ea* | lpc40xx_ea*],[2U]) RTEMS_BSPOPTS_SET([LPC24XX_PCLKDIV],[*],[1U]) RTEMS_BSPOPTS_HELP([LPC24XX_PCLKDIV],[clock divider for default PCLK (PCLK = CCLK / PCLKDIV)]) -RTEMS_BSPOPTS_SET([LPC24XX_EMCCLKDIV],[lpc17xx_ea*],[2U]) +RTEMS_BSPOPTS_SET([LPC24XX_EMCCLKDIV],[lpc17xx_ea* | lpc40xx_ea*],[2U]) RTEMS_BSPOPTS_SET([LPC24XX_EMCCLKDIV],[*],[1U]) RTEMS_BSPOPTS_HELP([LPC24XX_EMCCLKDIV],[clock divider for EMCCLK (EMCCLK = CCLK / EMCCLKDIV)]) @@ -60,7 +60,7 @@ RTEMS_BSPOPTS_HELP([LPC24XX_EMC_W9825G2JB75I],[enable Winbond W9825G2JB75I confi RTEMS_BSPOPTS_SET([LPC24XX_EMC_IS42S32800D7],[*_plx800_rom_*],[1]) RTEMS_BSPOPTS_HELP([LPC24XX_EMC_IS42S32800D7],[enable ISSI IS42S32800D7 configuration for EMC]) -RTEMS_BSPOPTS_SET([LPC24XX_EMC_IS42S32800B],[lpc17xx_ea_rom_*],[1]) +RTEMS_BSPOPTS_SET([LPC24XX_EMC_IS42S32800B],[lpc17xx_ea_rom_* | lpc40xx_ea_rom_*],[1]) RTEMS_BSPOPTS_HELP([LPC24XX_EMC_IS42S32800B],[enable ISSI IS42S32800B configuration for EMC]) RTEMS_BSPOPTS_SET([LPC24XX_EMC_M29W160E],[lpc24xx_ncs_rom_*],[1]) @@ -112,14 +112,14 @@ RTEMS_BSPOPTS_SET([LPC24XX_STOP_USB],[lpc23*],[]) RTEMS_BSPOPTS_SET([LPC24XX_STOP_USB],[*],[1]) RTEMS_BSPOPTS_HELP([LPC24XX_STOP_USB],[stop USB controller at start-up to avoid DMA interference]) -RTEMS_BSPOPTS_SET([LPC_DMA_CHANNEL_COUNT],[lpc17*],[8]) +RTEMS_BSPOPTS_SET([LPC_DMA_CHANNEL_COUNT],[lpc17* | lpc40*],[8]) RTEMS_BSPOPTS_SET([LPC_DMA_CHANNEL_COUNT],[*],[2]) RTEMS_BSPOPTS_HELP([LPC_DMA_CHANNEL_COUNT],[DMA channel count]) RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[lpc24xx_ncs_rom_ext],[0x80000040]) RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) -RTEMS_BSPOPTS_SET([BSP_USB_OTG_TRANSCEIVER_I2C_ADDR],[lpc17xx_ea*],[(0x2f << 1)]) +RTEMS_BSPOPTS_SET([BSP_USB_OTG_TRANSCEIVER_I2C_ADDR],[lpc17xx_ea* | lpc40xx_ea*],[(0x2f << 1)]) RTEMS_BSPOPTS_HELP([BSP_USB_OTG_TRANSCEIVER_I2C_ADDR],[USB OTG transceiver I2C address used by USB stack]) RTEMS_BSP_CLEANUP_OPTIONS(0, 1) diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx.inc b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx.inc new file mode 100644 index 0000000..2c921db --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx.inc @@ -0,0 +1,11 @@ +# +# Config file for LPC40XX. +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = arm + +CPU_CFLAGS = -mthumb -march=armv7-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mtune=cortex-m4 + +CFLAGS_OPTIMIZE_V = -O2 -g diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_ram.cfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_ram.cfg new file mode 100644 index 0000000..4c4eb4d --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_ram.cfg @@ -0,0 +1,5 @@ +# +# Config file for LPC40XX OEM Board from Embedded Artists. +# + +include $(RTEMS_ROOT)/make/custom/lpc40xx.inc diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int.cfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int.cfg new file mode 100644 index 0000000..4c4eb4d --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int.cfg @@ -0,0 +1,5 @@ +# +# Config file for LPC40XX OEM Board from Embedded Artists. +# + +include $(RTEMS_ROOT)/make/custom/lpc40xx.inc diff --git a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am index a022b02..3bf67a6 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am @@ -173,3 +173,59 @@ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds +$(PROJECT_LIB)/linkcmds.lpc17xx_ea_ram: startup/linkcmds.lpc17xx_ea_ram $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc17xx_ea_ram +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc17xx_ea_ram + +$(PROJECT_LIB)/linkcmds.lpc17xx_ea_rom_int: startup/linkcmds.lpc17xx_ea_rom_int $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc17xx_ea_rom_int +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc17xx_ea_rom_int + +$(PROJECT_LIB)/linkcmds.lpc17xx_plx800_ram: startup/linkcmds.lpc17xx_plx800_ram $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc17xx_plx800_ram +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc17xx_plx800_ram + +$(PROJECT_LIB)/linkcmds.lpc17xx_plx800_rom_int: startup/linkcmds.lpc17xx_plx800_rom_int $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc17xx_plx800_rom_int +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc17xx_plx800_rom_int + +$(PROJECT_LIB)/linkcmds.lpc2362: startup/linkcmds.lpc2362 $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc2362 +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc2362 + +$(PROJECT_LIB)/linkcmds.lpc23xx_tli800: startup/linkcmds.lpc23xx_tli800 $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc23xx_tli800 +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc23xx_tli800 + +$(PROJECT_LIB)/linkcmds.lpc24xx_ea: startup/linkcmds.lpc24xx_ea $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_ea +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_ea + +$(PROJECT_LIB)/linkcmds.lpc24xx_ncs_ram: startup/linkcmds.lpc24xx_ncs_ram $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_ram +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_ram + +$(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_ext: startup/linkcmds.lpc24xx_ncs_rom_ext $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_ext +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_ext + +$(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_int: startup/linkcmds.lpc24xx_ncs_rom_int $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_int +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_ncs_rom_int + +$(PROJECT_LIB)/linkcmds.lpc24xx_plx800_ram: startup/linkcmds.lpc24xx_plx800_ram $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_plx800_ram +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_plx800_ram + +$(PROJECT_LIB)/linkcmds.lpc24xx_plx800_rom_int: startup/linkcmds.lpc24xx_plx800_rom_int $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc24xx_plx800_rom_int +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc24xx_plx800_rom_int + +$(PROJECT_LIB)/linkcmds.lpc40xx_ea_ram: startup/linkcmds.lpc40xx_ea_ram $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc40xx_ea_ram +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc40xx_ea_ram + +$(PROJECT_LIB)/linkcmds.lpc40xx_ea_rom_int: startup/linkcmds.lpc40xx_ea_rom_int $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc40xx_ea_rom_int +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc40xx_ea_rom_int + diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_ram b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_ram new file mode 100644 index 0000000..d453596 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_ram @@ -0,0 +1 @@ +INCLUDE linkcmds.lpc17xx_ea_ram diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_rom_int b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_rom_int new file mode 100644 index 0000000..612f491 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc40xx_ea_rom_int @@ -0,0 +1 @@ +INCLUDE linkcmds.lpc17xx_ea_rom_int From joel at rtems.org Tue Aug 12 18:32:17 2014 From: joel at rtems.org (Joel Sherrill) Date: Tue, 12 Aug 2014 13:32:17 -0500 Subject: [rtems commit] Add support for OpenRISC - Fixed issues Message-ID: <20140812183217.2DD1B700903@git.rtems.org> Module: rtems Branch: master Commit: 94d45f6ffe22c640566ddc4432adcb97ab6c907f Changeset: http://git.rtems.org/rtems/commit/?id=94d45f6ffe22c640566ddc4432adcb97ab6c907f Author: Hesham ALMatary Date: Tue Aug 12 10:57:42 2014 -0500 Add support for OpenRISC - Fixed issues This work is based on the old or32 port (that has been removed back in 2005) authored by Chris Ziomkowski. The patch includes the basic functions every port should implement like: context switch, exception handling, OpenRISC ABI and machine definitions and configurations. --- cpukit/configure.ac | 1 + cpukit/score/cpu/Makefile.am | 1 + cpukit/score/cpu/or1k/Makefile.am | 36 + cpukit/score/cpu/or1k/cpu.c | 112 +++ cpukit/score/cpu/or1k/or1k-context-initialize.c | 43 + cpukit/score/cpu/or1k/or1k-context-switch.S | 114 +++ cpukit/score/cpu/or1k/or1k-exception-default.c | 23 + cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 22 + cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 216 ++++ cpukit/score/cpu/or1k/rtems/asm.h | 99 ++ cpukit/score/cpu/or1k/rtems/score/cpu.h | 1051 ++++++++++++++++++++ cpukit/score/cpu/or1k/rtems/score/cpu_asm.h | 74 ++ cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 371 +++++++ cpukit/score/cpu/or1k/rtems/score/or1k.h | 49 + cpukit/score/cpu/or1k/rtems/score/types.h | 51 + 15 files changed, 2263 insertions(+), 0 deletions(-) diff --git a/cpukit/configure.ac b/cpukit/configure.ac index 19e5b81..56815e2 100644 --- a/cpukit/configure.ac +++ b/cpukit/configure.ac @@ -382,6 +382,7 @@ score/cpu/m32r/Makefile score/cpu/mips/Makefile score/cpu/moxie/Makefile score/cpu/nios2/Makefile +score/cpu/or1k/Makefile score/cpu/powerpc/Makefile score/cpu/sh/Makefile score/cpu/sparc/Makefile diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am index 8d28fc2..69abcd6 100644 --- a/cpukit/score/cpu/Makefile.am +++ b/cpukit/score/cpu/Makefile.am @@ -14,6 +14,7 @@ DIST_SUBDIRS += mips DIST_SUBDIRS += moxie DIST_SUBDIRS += nios2 DIST_SUBDIRS += no_cpu +DIST_SUBDIRS += or1k DIST_SUBDIRS += powerpc DIST_SUBDIRS += sh DIST_SUBDIRS += sparc diff --git a/cpukit/score/cpu/or1k/Makefile.am b/cpukit/score/cpu/or1k/Makefile.am new file mode 100644 index 0000000..cb96856 --- /dev/null +++ b/cpukit/score/cpu/or1k/Makefile.am @@ -0,0 +1,36 @@ +include $(top_srcdir)/automake/compile.am + +CLEANFILES = +DISTCLEANFILES = + +include_rtemsdir = $(includedir)/rtems + +include_rtems_HEADERS = rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score + +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += rtems/score/cpu.h +include_rtems_score_HEADERS += rtems/score/cpu_asm.h +include_rtems_score_HEADERS += rtems/score/types.h +include_rtems_score_HEADERS += rtems/score/or1k.h +include_rtems_score_HEADERS += rtems/score/or1k-utility.h + + + +noinst_LIBRARIES = libscorecpu.a + +libscorecpu_a_SOURCES = +libscorecpu_a_SOURCES += cpu.c +libscorecpu_a_SOURCES += or1k-context-switch.S +libscorecpu_a_SOURCES += or1k-context-initialize.c +libscorecpu_a_SOURCES += or1k-exception-default.c +libscorecpu_a_SOURCES += or1k-exception-frame-print.c +libscorecpu_a_SOURCES += or1k-exception-handler-low.S + +libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) + +all-local: $(PREINSTALL_FILES) + +include $(srcdir)/preinstall.am +include $(top_srcdir)/automake/local.am diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c new file mode 100644 index 0000000..9d1ae49 --- /dev/null +++ b/cpukit/score/cpu/or1k/cpu.c @@ -0,0 +1,112 @@ +/* + * Opencore OR1K CPU Dependent Source + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#include +#include +#include +#include +#include + +/** + * @brief Performs processor dependent initialization. + */ +void _CPU_Initialize(void) +{ + /* Do nothing */ +} + +/** + * @brief Sets the hardware interrupt level by the level value. + * + * @param[in] level for or1k can only range over two values: + * 0 (enable interrupts) and 1 (disable interrupts). In future + * implementations if fast context switch is implemented, the level + * can range from 0 to 15. @see OpenRISC architecture manual. + * + */ +void _CPU_ISR_Set_level(uint32_t level) +{ + uint32_t sr = 0; + level = (level > 0)? 1 : 0; + + /* map level bit to or1k interrupt enable/disable bit in sr register */ + level <<= CPU_OR1K_SPR_SR_SHAMT_IEE; + + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + + if (level == 0){ /* Enable all interrupts */ + sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE; + + } else{ + sr &= ~CPU_OR1K_SPR_SR_IEE; + } + + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); + } + +uint32_t _CPU_ISR_Get_level( void ) +{ + uint32_t sr = 0; + + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + + return (sr & CPU_OR1K_SPR_SR_IEE)? 0 : 1; +} + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ +} + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + proc_ptr *table = + (proc_ptr *) bsp_start_vector_table_begin; + proc_ptr current_handler; + + ISR_Level level; + + _ISR_Disable( level ); + + current_handler = table [vector]; + + /* The current handler is now the old one */ + if (old_handler != NULL) { + *old_handler = (proc_ptr) current_handler; + } + + /* Write only if necessary to avoid writes to a maybe read-only memory */ + if (current_handler != new_handler) { + table [vector] = new_handler; + } + + _ISR_Enable( level ); +} + +void _CPU_Install_interrupt_stack( void ) +{ +} + +void _CPU_Thread_Idle_body( void ) +{ + do { + _OR1K_CPU_Sleep(); + } while (1); +} diff --git a/cpukit/score/cpu/or1k/or1k-context-initialize.c b/cpukit/score/cpu/or1k/or1k-context-initialize.c new file mode 100644 index 0000000..7ac2875 --- /dev/null +++ b/cpukit/score/cpu/or1k/or1k-context-initialize.c @@ -0,0 +1,43 @@ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * COPYRIGHT (c) 1989-2006 + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include + +#include +#include +#include + +void _CPU_Context_Initialize( + Context_Control *context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +) +{ + uint32_t stack = (uint32_t) stack_area_begin; + uint32_t sr; + + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + + memset(context, 0, sizeof(*context)); + + context->r1 = stack; + context->r2 = stack; + context->r9 = (uint32_t) entry_point; + context->sr = sr; +} diff --git a/cpukit/score/cpu/or1k/or1k-context-switch.S b/cpukit/score/cpu/or1k/or1k-context-switch.S new file mode 100644 index 0000000..91521e4 --- /dev/null +++ b/cpukit/score/cpu/or1k/or1k-context-switch.S @@ -0,0 +1,114 @@ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include +#include "rtems/score/or1k-utility.h" + +.text +.align 4 + +PUBLIC(_CPU_Context_switch) +PUBLIC(_CPU_Context_restore) +PUBLIC(_CPU_Context_restore_fp) +PUBLIC(_CPU_Context_save_fp) + +SYM(_CPU_Context_switch): + l.sw 0(r3),r1 + l.sw 4(r3),r2 + l.sw 8(r3),r3 + l.sw 12(r3),r4 + l.sw 16(r3),r5 + l.sw 20(r3),r6 + l.sw 24(r3),r7 + l.sw 28(r3),r8 + l.sw 32(r3),r9 + /* Skip r10 as it's preserved to be used by TLS */ + /* The following set if registers are preserved across function calls */ + l.sw 52(r3),r14 + l.sw 60(r3),r16 + l.sw 68(r3),r18 + l.sw 76(r3),r20 + l.sw 84(r3),r22 + l.sw 92(r3),r24 + l.sw 100(r3),r26 + l.sw 108(r3),r28 + l.sw 116(r3),r30 + + /* Supervision Register */ + l.mfspr r13,r0, CPU_OR1K_SPR_SR + l.sw 124(r3),r13 + + /* EPCR */ + l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0 + l.sw 128(r3), r13 /* epcr */ + + /* EEAR */ + l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0 + l.sw 132(r3), r13 /* eear */ + + /* ESR */ + l.mfspr r13, r0, CPU_OR1K_SPR_ESR0 + l.sw 136(r3), r13 /* esr */ + +SYM(restore): + l.lwz r13,124(r4) + l.mtspr r0,r13, CPU_OR1K_SPR_SR + + /* Exception level related registers */ + + /* EPCR */ + l.lwz r13, 128(r4) + l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0 + + /* EEAR */ + l.lwz r13, 132(r4) + l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0 + + /* ESR */ + l.lwz r13, 136(r4) + l.mtspr r0, r13, CPU_OR1K_SPR_ESR0 + + l.lwz r1,0(r4) + l.lwz r2,4(r4) + l.lwz r3,8(r4) + /* Skip r4 as it contains the current buffer address */ + l.lwz r5,16(r4) + l.lwz r6,20(r4) + l.lwz r7,24(r4) + l.lwz r8,28(r4) + l.lwz r9,32(r4) + l.lwz r14,52(r4) + l.lwz r16,60(r4) + l.lwz r18,68(r4) + l.lwz r20,76(r4) + l.lwz r22,84(r4) + l.lwz r24,92(r4) + l.lwz r26,100(r4) + l.lwz r28,108(r4) + l.lwz r30,116(r4) + + l.lwz r4,12(r4) + + l.jr r9 + l.nop + + SYM(_CPU_Context_restore): + l.add r4,r3,r0 + l.add r13,r0,r0 + l.j restore + l.nop + + SYM(_CPU_Context_restore_fp): + l.nop + + SYM(_CPU_Context_save_fp): + l.nop diff --git a/cpukit/score/cpu/or1k/or1k-exception-default.c b/cpukit/score/cpu/or1k/or1k-exception-default.c new file mode 100644 index 0000000..645a7f9 --- /dev/null +++ b/cpukit/score/cpu/or1k/or1k-exception-default.c @@ -0,0 +1,23 @@ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include +#include +#include +#include + +void _OR1K_Exception_default(uint32_t vector, CPU_Exception_frame *frame); + +void _OR1K_Exception_default(uint32_t vector, CPU_Exception_frame *frame) +{ + rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame ); +} diff --git a/cpukit/score/cpu/or1k/or1k-exception-frame-print.c b/cpukit/score/cpu/or1k/or1k-exception-frame-print.c new file mode 100644 index 0000000..75e169c --- /dev/null +++ b/cpukit/score/cpu/or1k/or1k-exception-frame-print.c @@ -0,0 +1,22 @@ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include +#include + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) +{ + uint32_t i; + for ( i = 0; i < 32; ++i ) { + printk( "r%02i = 0x%016x\n",i, frame->r[i]); + } +} diff --git a/cpukit/score/cpu/or1k/or1k-exception-handler-low.S b/cpukit/score/cpu/or1k/or1k-exception-handler-low.S new file mode 100644 index 0000000..964a054 --- /dev/null +++ b/cpukit/score/cpu/or1k/or1k-exception-handler-low.S @@ -0,0 +1,216 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief OR1K exception support implementation. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include "rtems/score/or1k-utility.h" + +.align 4 +.text +PUBLIC(_ISR_Handler) +.type _ISR_Handler, at function + + SYM(_ISR_Handler): + + l.addi r1, r1, -140 + + l.sw 8(r1),r2 + /* r3 is saved by BSP exception handler */ + l.sw 16(r1),r4 + l.sw 20(r1),r5 + l.sw 24(r1),r6 + l.sw 28(r1),r7 + l.sw 32(r1),r8 + l.sw 36(r1),r9 + l.sw 40(r1),r10 + l.sw 44(r1),r11 + l.sw 48(r1),r12 + l.sw 52(r1),r13 + l.sw 56(r1),r14 + l.sw 60(r1),r15 + l.sw 64(r1),r16 + l.sw 68(r1),r17 + l.sw 72(r1),r18 + l.sw 76(r1),r19 + l.sw 80(r1),r20 + l.sw 84(r1),r21 + l.sw 88(r1),r22 + l.sw 92(r1),r23 + l.sw 96(r1),r24 + l.sw 100(r1),r25 + l.sw 104(r1),r26 + l.sw 108(r1),r27 + l.sw 112(r1),r28 + l.sw 116(r1),r29 + l.sw 120(r1),r30 + l.sw 124(r1),r31 + + /* Exception level related registers */ + + /* EPCR */ + l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0 + l.sw 128(r1), r13 /* epcr */ + + /* EEAR */ + l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0 + l.sw 132(r1), r13 /* eear */ + + /* ESR */ + l.mfspr r13, r0, CPU_OR1K_SPR_ESR0 + l.sw 136(r1), r13 /* esr */ + + /* Increment nesting level */ + l.movhi r6, hi(ISR_NEST_LEVEL) + l.ori r6, r6, lo(ISR_NEST_LEVEL) + + /* Disable multitasking */ + l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL) + l.ori r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL) + + l.lwz r5, 0(r6) + l.lwz r7, 0(r8) + l.addi r5, r5, 1 + l.addi r7, r7, 1 + l.sw 0(r6), r5 + l.sw 0(r8), r7 + + /* Save interrupted task stack pointer */ + l.addi r4, r1, 144 + l.sw 4(r1), r4 + + /* Save interrupted task r3 (first arg) value */ + l.addi r4, r1, 140 + l.lwz r4, 0(r4) + l.sw 12(r1), r4 + + /* Keep r1 (Exception frame address) in r14 */ + l.add r14, r1, r0 + + /* Call the exception handler from vector table */ + + /* First function arg for C handler is vector number, + * and the second is a pointer to exception frame. + */ + l.add r13, r3, r0 + l.add r4, r1, r0 + l.slli r13, r13, 2 + l.addi r13, r13, lo(bsp_start_vector_table_begin) + l.lwz r13, 0(r13) + + /* Do not switch stacks if we are in a nested interrupt. At + * this point r5 should be holding ISR_NEST_LEVEL value. + */ + l.sfgtui r5, 2 + l.bf jump_to_c_handler + l.nop + + /* Switch to RTEMS dedicated interrupt stack */ + l.movhi r1, hi(INTERRUPT_STACK_HIGH) + l.ori r1, r1, lo(INTERRUPT_STACK_HIGH) + l.lwz r1, 0(r1) + +jump_to_c_handler: + l.jalr r13 + l.nop + + /* Switch back to the interrupted task stack */ + l.add r1, r14, r0 + + /* Check if dispatch needed */ + l.movhi r31, hi(DISPATCH_NEEDED) + l.ori r31, r31, lo(DISPATCH_NEEDED) + l.lwz r31, 0(r31) + l.sfeq r31, r0 + l.bf exception_frame_restore + l.nop + + l.movhi r13, hi(_Thread_Dispatch) + l.ori r13, r13, lo(_Thread_Dispatch) + l.jalr r13 + l.nop + + SYM(exception_frame_restore): + + /* Exception level related registers */ + + /* EPCR */ + l.lwz r13, 128(r1) + l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0 + + /* EEAR */ + l.lwz r13, 132(r1) + l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0 + + /* ESR */ + l.lwz r13, 136(r1) + l.mtspr r0, r13, CPU_OR1K_SPR_ESR0 + + /* Increment nesting level */ + l.movhi r6, hi(ISR_NEST_LEVEL) + l.ori r6, r6, lo(ISR_NEST_LEVEL) + + /* Disable multitasking */ + l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL) + l.ori r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL) + + l.lwz r5, 0(r6) + l.lwz r7, 0(r8) + l.addi r5, r5, -1 + l.addi r7, r7, -1 + l.sw 0(r6), r5 + l.sw 0(r8), r7 + + l.lwz r2, 8(r1) + l.lwz r3, 12(r1) + l.lwz r4, 16(r1) + l.lwz r5, 20(r1) + l.lwz r6, 24(r1) + l.lwz r7, 28(r1) + l.lwz r8, 32(r1) + l.lwz r9, 36(r1) + l.lwz r10, 40(r1) + l.lwz r11, 44(r1) + l.lwz r12, 48(r1) + l.lwz r13, 52(r1) + l.lwz r14, 56(r1) + l.lwz r15, 60(r1) + l.lwz r16, 64(r1) + l.lwz r17, 68(r1) + l.lwz r18, 72(r1) + l.lwz r19, 76(r1) + l.lwz r20, 80(r1) + l.lwz r21, 84(r1) + l.lwz r22, 88(r1) + l.lwz r23, 92(r1) + l.lwz r24, 96(r1) + l.lwz r25, 100(r1) + l.lwz r26, 104(r1) + l.lwz r27, 108(r1) + l.lwz r28, 112(r1) + l.lwz r29, 116(r1) + l.lwz r30, 120(r1) + + l.addi r1, r1, 140 + + l.addi r1, r1, 4 + + l.rfe + l.nop diff --git a/cpukit/score/cpu/or1k/rtems/asm.h b/cpukit/score/cpu/or1k/rtems/asm.h new file mode 100644 index 0000000..4d2c226 --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/asm.h @@ -0,0 +1,99 @@ +/** + * @file rtems/asm.h + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + */ + +/* + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + * + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-1997. + * On-Line Applications Research Corporation (OAR). + * + */ + +#ifndef __OR1K_ASM_h +#define __OR1K_ASM_h + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +/* ANSI concatenation macros. */ + +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a ## b + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .global SYM (sym) +#define EXTERN(sym) .global SYM (sym) + +#endif diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h b/cpukit/score/cpu/or1k/rtems/score/cpu.h new file mode 100644 index 0000000..01e07a2 --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/score/cpu.h @@ -0,0 +1,1051 @@ +/** + * @file rtems/score/cpu.h + */ + +/* + * This include file contains macros pertaining to the Opencores + * or1k processor family. + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * This file adapted from no_cpu example of the RTEMS distribution. + * The body has been modified for the Opencores OR1k implementation by + * Chris Ziomkowski. + * + */ + +#ifndef _OR1K_CPU_H +#define _OR1K_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#include /* pick up machine definitions */ +#include +#include +#ifndef ASM +#include +#include +#include /* for printk */ +#endif + +/* conditional compilation parameters */ + +/* + * Should the calls to _Thread_Enable_dispatch be inlined? + * + * If TRUE, then they are inlined. + * If FALSE, then a subroutine call is made. + * + * Basically this is an example of the classic trade-off of size + * versus speed. Inlining the call (TRUE) typically increases the + * size of RTEMS while speeding up the enabling of dispatching. + * [NOTE: In general, the _Thread_Dispatch_disable_level will + * only be 0 or 1 unless you are in an interrupt handler and that + * interrupt handler invokes the executive.] When not inlined + * something calls _Thread_Enable_dispatch which in turns calls + * _Thread_Dispatch. If the enable dispatch is inlined, then + * one subroutine call is avoided entirely.] + * + */ + +#define CPU_INLINE_ENABLE_DISPATCH FALSE + +/* + * Should the body of the search loops in _Thread_queue_Enqueue_priority + * be unrolled one time? In unrolled each iteration of the loop examines + * two "nodes" on the chain being searched. Otherwise, only one node + * is examined per iteration. + * + * If TRUE, then the loops are unrolled. + * If FALSE, then the loops are not unrolled. + * + * The primary factor in making this decision is the cost of disabling + * and enabling interrupts (_ISR_Flash) versus the cost of rest of the + * body of the loop. On some CPUs, the flash is more expensive than + * one iteration of the loop body. In this case, it might be desirable + * to unroll the loop. It is important to note that on some CPUs, this + * code is the longest interrupt disable period in RTEMS. So it is + * necessary to strike a balance when setting this parameter. + * + */ + +#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Currently, for or1k port, _ISR_Handler is responsible for switching to + * RTEMS dedicated interrupt task. + * + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/* + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + */ + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE + * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. + * + */ + +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + */ + +#define CPU_ISR_PASSES_FRAME_POINTER 1 + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "OR1K_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + * + * The CPU_SOFTWARE_FP is used to indicate whether or not there + * is software implemented floating point that must be context + * switched. The determination of whether or not this applies + * is very tool specific and the state saved/restored is also + * compiler specific. + * + * Or1k Specific Information: + * + * At this time there are no implementations of Or1k that are + * expected to implement floating point. More importantly, the + * floating point architecture is expected to change significantly + * before such chips are fabricated. + */ + +#define CPU_HARDWARE_FP FALSE +#define CPU_SOFTWARE_FP FALSE + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + */ + +#define CPU_ALL_TASKS_ARE_FP FALSE + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + * + */ + +#define CPU_IDLE_TASK_IS_FP FALSE + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + */ + +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + * + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + */ + +#define CPU_STACK_GROWS_UP FALSE + +/* + * The following is the variable attribute used to force alignment + * of critical RTEMS structures. On some processors it may make + * sense to have these aligned on tighter boundaries than + * the minimum requirements of the compiler in order to have as + * much of the critical data area as possible in a cache line. + * + * The placement of this macro in the declaration of the variables + * is based on the syntactically requirements of the GNU C + * "__attribute__" extension. For example with GNU C, use + * the following to force a structures to a 32 byte boundary. + * + * __attribute__ ((aligned (32))) + * + * NOTE: Currently only the Priority Bit Map table uses this feature. + * To benefit from using this, the data must be heavily + * used so it will stay in the cache and used frequently enough + * in the executive to justify turning this on. + * + */ + +#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) + +/* + * Define what is required to specify how the network to host conversion + * routines are handled. + * + * Or1k Specific Information: + * + * This version of RTEMS is designed specifically to run with + * big endian architectures. If you want little endian, you'll + * have to make the appropriate adjustments here and write + * efficient routines for byte swapping. The Or1k architecture + * doesn't do this very well. + */ + +#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE +#define CPU_BIG_ENDIAN TRUE +#define CPU_LITTLE_ENDIAN FALSE + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + * + */ + +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +/* + * Processor defined structures required for cpukit/score. + */ + + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + * + * + */ +#ifndef ASM +#ifdef OR1K_64BIT_ARCH +#define or1kreg uint64_t +#else +#define or1kreg uint32_t +#endif + +typedef struct { + uint32_t r1; /* Stack pointer */ + uint32_t r2; /* Frame pointer */ + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t r13; + uint32_t r14; + uint32_t r15; + uint32_t r16; + uint32_t r17; + uint32_t r18; + uint32_t r19; + uint32_t r20; + uint32_t r21; + uint32_t r22; + uint32_t r23; + uint32_t r24; + uint32_t r25; + uint32_t r26; + uint32_t r27; + uint32_t r28; + uint32_t r29; + uint32_t r30; + uint32_t r31; + + uint32_t sr; /* Current supervision register non persistent values */ + uint32_t epcr; + uint32_t eear; + uint32_t esr; +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->r1 + +typedef struct { + /** FPU registers are listed here */ + double some_float_register; +} Context_Control_fp; + +typedef Context_Control CPU_Interrupt_frame; + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + * + * Or1k Specific Information: + * + */ + +#define CPU_CONTEXT_FP_SIZE 0 +SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; + +/* + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + * + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * Should be large enough to run all RTEMS tests. This insures + * that a "reasonable" small application should not have any problems. + * + */ + +#define CPU_STACK_MINIMUM_SIZE 4096 + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + */ + +#define CPU_ALIGNMENT 8 + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/** + * Size of a pointer. + * + * This must be an integer literal that can be used by the assembler. This + * value will be used to calculate offsets of structure members. These + * offsets will be used in assembler code. + */ +#define CPU_SIZEOF_POINTER 4 + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2 although it should be + * a multiple of 2 greater than or equal to 2. The requirement + * to be a multiple of 2 is because the heap uses the least + * significant field of the front and back flags to indicate + * that a block is in use or free. So you do not want any odd + * length blocks really putting length data in that bit. + * + * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will + * have to be greater or equal to than CPU_ALIGNMENT to ensure that + * elements allocated from the heap meet all restrictions. + * + */ + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + * + */ + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + * + */ + +#define CPU_STACK_ALIGNMENT 0 + +/* ISR handler macros */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +#define _CPU_Initialize_vectors() + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + * + */ + +static inline uint32_t or1k_interrupt_disable( void ) +{ + uint32_t sr; + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + + _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)); + + return sr; +} + +static inline void or1k_interrupt_enable(uint32_t level) +{ + uint32_t sr; + + /* Enable interrupts and restore rs */ + sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE; + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); + +} + +#define _CPU_ISR_Disable( _level ) \ + _level = or1k_interrupt_disable() + + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _level is not modified. + * + */ + +#define _CPU_ISR_Enable( _level ) \ + or1k_interrupt_enable( _level ) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + * + */ + +#define _CPU_ISR_Flash( _level ) \ + do{ \ + _CPU_ISR_Enable( _level ); \ + _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \ + } while(0) + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * The get routine usually must be implemented as a subroutine. + * + */ + +void _CPU_ISR_Set_level( uint32_t level ); + +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +#define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * + */ + +/** + * @brief Initializes the CPU context. + * + * The following steps are performed: + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * + * @param[in] context points to the context area + * @param[in] stack_area_begin is the low address of the allocated stack area + * @param[in] stack_area_size is the size of the stack area in bytes + * @param[in] new_level is the interrupt level for the task + * @param[in] entry_point is the task's entry point + * @param[in] is_fp is set to @c true if the task is a floating point task + * @param[in] tls_area is the thread-local storage (TLS) area + */ +void _CPU_Context_Initialize( + Context_Control *context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + * + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* + * The purpose of this macro is to allow the initial pointer into + * a floating point context area (used to save the floating point + * context) to be at an arbitrary place in the floating point + * context area. + * + * This is necessary because some FP units are designed to have + * their context saved as a stack which grows into lower addresses. + * Other FP units can be saved by simply moving registers into offsets + * from the base of the context area. Finally some FP units provide + * a "dump context" instruction which could fill in from high to low + * or low to high based on the whim of the CPU designers. + * + */ + +#define _CPU_Context_Fp_start( _base, _offset ) \ + ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) + +/* + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other models include (1) not doing anything, and (2) putting + * a "null FP status word" in the correct place in the FP context. + * + */ + +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + * + */ + +#define _CPU_Fatal_halt( _error ) \ + printk("Fatal Error %d Halted\n",_error); \ + for(;;) + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +/* + * This routine sets _output to the bit number of the first bit + * set in _value. _value is of CPU dependent type Priority_Bit_map_control. + * This type may be either 16 or 32 bits wide although only the 16 + * least significant bits will be used. + * + * There are a number of variables in using a "find first bit" type + * instruction. + * + * (1) What happens when run on a value of zero? + * (2) Bits may be numbered from MSB to LSB or vice-versa. + * (3) The numbering may be zero or one based. + * (4) The "find first bit" instruction may search from MSB or LSB. + * + * RTEMS guarantees that (1) will never happen so it is not a concern. + * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and + * _CPU_Priority_bits_index(). These three form a set of routines + * which must logically operate together. Bits in the _value are + * set and cleared based on masks built by _CPU_Priority_mask(). + * The basic major and minor values calculated by _Priority_Major() + * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() + * to properly range between the values returned by the "find first bit" + * instruction. This makes it possible for _Priority_Get_highest() to + * calculate the major and directly index into the minor table. + * This mapping is necessary to ensure that 0 (a high priority major/minor) + * is the first bit found. + * + * This entire "find first bit" and mapping process depends heavily + * on the manner in which a priority is broken into a major and minor + * components with the major being the 4 MSB of a priority and minor + * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest + * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next + * to the lowest priority. + * + * If your CPU does not have a "find first bit" instruction, then + * there are ways to make do without it. Here are a handful of ways + * to implement this in software: + * + * - a series of 16 bit test instructions + * - a "binary search using if's" + * - _number = 0 + * if _value > 0x00ff + * _value >>=8 + * _number = 8; + * + * if _value > 0x0000f + * _value >=8 + * _number += 4 + * + * _number += bit_set_table[ _value ] + * + * where bit_set_table[ 16 ] has values which indicate the first + * bit set + * + */ + + /* #define CPU_USE_GENERIC_BITFIELD_CODE FALSE */ +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE +#define CPU_USE_GENERIC_BITFIELD_DATA TRUE + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + + /* Get a value between 0 and N where N is the bit size */ + /* This routine makes use of the fact that CPUCFGR defines + OB32S to have value 32, and OB64S to have value 64. If + this ever changes then this routine will fail. */ +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + asm volatile ("l.mfspr %0,r0,0x2 \n\t"\ + "l.andi %0,%0,0x60 \n\t"\ + "l.ff1 %1,%1,r0 \n\t"\ + "l.sub %0,%0,%1 \n\t" : "=&r" (_output), "+r" (_value)); + +#endif + +/* end of Bitfield handler macros */ + +/* + * This routine builds the mask which corresponds to the bit fields + * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion + * for that routine. + * + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_Mask( _bit_number ) \ + (1 << _bit_number) + +#endif + +/* + * This routine translates the bit numbers returned by + * _CPU_Bitfield_Find_first_bit() into something suitable for use as + * a major or minor component of a priority. See the discussion + * for that routine. + * + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +#endif + +#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE +#define CPU_TIMESTAMP_USE_INT64 TRUE +#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE + +typedef struct { +/* There is no CPU specific per-CPU state */ +} CPU_Per_CPU_control; +#endif /* ASM */ + +#define CPU_SIZEOF_POINTER 4 +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM +typedef uint32_t CPU_Counter_ticks; +typedef uint16_t Priority_bit_map_Word; + +typedef struct { + uint32_t r[32]; + + /* The following registers must be saved if we have + fast context switch disabled and nested interrupt + levels are enabled. + */ +#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED + uint32_t epcr; /* exception PC register */ + uint32_t eear; /* exception effective address register */ + uint32_t esr; /* exception supervision register */ +#endif + +} CPU_Exception_frame; + +/** + * @brief Prints the exception frame via printk(). + * + * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. + */ +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + + +/* end of Priority handler macros */ + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + * + */ + +void _CPU_Initialize( + void +); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + * + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + * + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Thread_Idle_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + * + */ + +void _CPU_Thread_Idle_body( void ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + * + * Or1k Specific Information: + * + * Please see the comments in the .c file for a description of how + * this function works. There are several things to be aware of. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + * + */ + +void _CPU_Context_restore( + Context_Control *new_context +); + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + * + */ + +void _CPU_Context_save_fp( + void **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + * + */ + +void _CPU_Context_restore_fp( + void **fp_context_ptr +); + +/* The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to insure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + */ + +static inline unsigned int CPU_swap_u32( + unsigned int value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +); + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h b/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h new file mode 100644 index 0000000..a5659f3 --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h @@ -0,0 +1,74 @@ +/** + * @file + * + * @brief OR1K Assembly File + * + * Very loose template for an include file for the cpu_asm.? file + * if it is implemented as a ".S" file (preprocessed by cpp) instead + * of a ".s" file (preprocessed by gm4 or gasp). + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + +/* pull in the generated offsets */ + +/* +#include +*/ + +/* + * Hardware General Registers + */ + +/* put something here */ + +/* + * Hardware Floating Point Registers + */ + +/* put something here */ + +/* + * Hardware Control Registers + */ + +/* put something here */ + +/* + * Calling Convention + */ + +/* put something here */ + +/* + * Temporary registers + */ + +/* put something here */ + +/* + * Floating Point Registers - SW Conventions + */ + +/* put something here */ + +/* + * Temporary floating point registers + */ + +/* put something here */ + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h new file mode 100644 index 0000000..74c14d7 --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h @@ -0,0 +1,371 @@ +/** + * @file + * + * @brief OR1K utility + */ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_OR1K_UTILITY_H +#define _RTEMS_SCORE_OR1K_UTILITY_H + +/* SPR groups definitions */ +#define SPR_GRP_SHAMT 11 +#define SPR_GRP0_SYS_CTRL (0 << SPR_GRP_SHAMT) +#define SPR_GRP1_DMMU (1 << SPR_GRP_SHAMT) +#define SPR_GRP2_IMMU (2 << SPR_GRP_SHAMT) +#define SPR_GRP3_DC (3 << SPR_GRP_SHAMT) +#define SPR_GRP4_IC (4 << SPR_GRP_SHAMT) +#define SPR_GRP5_MAC (5 << SPR_GRP_SHAMT) +#define SPR_GRP6_DEBUG (6 << SPR_GRP_SHAMT) +#define SPR_GRP7_PERF_CTR (7 << SPR_GRP_SHAMT) +#define SPR_GRP8_PWR_MNG (8 << SPR_GRP_SHAMT) +#define SPR_GRP9_PIC (9 << SPR_GRP_SHAMT) +#define SPR_GPR10_TICK_TMR (10 << SPR_GRP_SHAMT) +#define SPR_GPR11_FPU (11 << SPR_GRP_SHAMT) + +/* SPR registers definitions */ + +/* Group 0: System control registers */ +#define CPU_OR1K_SPR_VR (SPR_GRP0_SYS_CTRL + 0) +#define CPU_OR1K_SPR_UPR (SPR_GRP0_SYS_CTRL + 1) +#define CPU_OR1K_SPR_CPUCFGR (SPR_GRP0_SYS_CTRL + 2) +#define CPU_OR1K_SPR_DMMUCFGR (SPR_GRP0_SYS_CTRL + 3) +#define CPU_OR1K_SPR_IMMUCFGR (SPR_GRP0_SYS_CTRL + 4) +#define CPU_OR1K_SPR_DCCFGR (SPR_GRP0_SYS_CTRL + 5) +#define CPU_OR1K_SPR_ICCFGR (SPR_GRP0_SYS_CTRL + 6) +#define CPU_OR1K_SPR_DCFGR (SPR_GRP0_SYS_CTRL + 7) +#define CPU_OR1K_SPR_PCCFGR (SPR_GRP0_SYS_CTRL + 8) +#define CPU_OR1K_SPR_VR2 (SPR_GRP0_SYS_CTRL + 9) +#define CPU_OR1K_SPR_AVR (SPR_GRP0_SYS_CTRL + 10) +#define CPU_OR1K_SPR_EVBAR (SPR_GRP0_SYS_CTRL + 11) +#define CPU_OR1K_SPR_AECR (SPR_GRP0_SYS_CTRL + 12) +#define CPU_OR1K_SPR_AESR (SPR_GRP0_SYS_CTRL + 13) +#define CPU_OR1K_SPR_NPC (SPR_GRP0_SYS_CTRL + 16) +#define CPU_OR1K_SPR_SR (SPR_GRP0_SYS_CTRL + 17) +#define CPU_OR1K_SPR_PPC (SPR_GRP0_SYS_CTRL + 18) +#define CPU_OR1K_SPR_FPCSR (SPR_GRP0_SYS_CTRL + 20) +#define CPU_OR1K_SPR_EPCR0 (SPR_GRP0_SYS_CTRL + 32) +#define CPU_OR1K_SPR_EPCR1 (SPR_GRP0_SYS_CTRL + 33) +#define CPU_OR1K_SPR_EPCR2 (SPR_GRP0_SYS_CTRL + 34) +#define CPU_OR1K_SPR_EPCR3 (SPR_GRP0_SYS_CTRL + 35) +#define CPU_OR1K_SPR_EPCR4 (SPR_GRP0_SYS_CTRL + 36) +#define CPU_OR1K_SPR_EPCR5 (SPR_GRP0_SYS_CTRL + 37) +#define CPU_OR1K_SPR_EPCR6 (SPR_GRP0_SYS_CTRL + 38) +#define CPU_OR1K_SPR_EPCR7 (SPR_GRP0_SYS_CTRL + 39) +#define CPU_OR1K_SPR_EPCR8 (SPR_GRP0_SYS_CTRL + 40) +#define CPU_OR1K_SPR_EPCR9 (SPR_GRP0_SYS_CTRL + 41) +#define CPU_OR1K_SPR_EPCR10 (SPR_GRP0_SYS_CTRL + 42) +#define CPU_OR1K_SPR_EPCR11 (SPR_GRP0_SYS_CTRL + 43) +#define CPU_OR1K_SPR_EPCR12 (SPR_GRP0_SYS_CTRL + 44) +#define CPU_OR1K_SPR_EPCR13 (SPR_GRP0_SYS_CTRL + 45) +#define CPU_OR1K_SPR_EPCR14 (SPR_GRP0_SYS_CTRL + 46) +#define CPU_OR1K_SPR_EPCR15 (SPR_GRP0_SYS_CTRL + 47) +#define CPU_OR1K_SPR_EEAR0 (SPR_GRP0_SYS_CTRL + 48) +#define CPU_OR1K_SPR_EEAR1 (SPR_GRP0_SYS_CTRL + 49) +#define CPU_OR1K_SPR_EEAR2 (SPR_GRP0_SYS_CTRL + 50) +#define CPU_OR1K_SPR_EEAR3 (SPR_GRP0_SYS_CTRL + 51) +#define CPU_OR1K_SPR_EEAR4 (SPR_GRP0_SYS_CTRL + 52) +#define CPU_OR1K_SPR_EEAR5 (SPR_GRP0_SYS_CTRL + 53) +#define CPU_OR1K_SPR_EEAR6 (SPR_GRP0_SYS_CTRL + 54) +#define CPU_OR1K_SPR_EEAR7 (SPR_GRP0_SYS_CTRL + 55) +#define CPU_OR1K_SPR_EEAR8 (SPR_GRP0_SYS_CTRL + 56) +#define CPU_OR1K_SPR_EEAR9 (SPR_GRP0_SYS_CTRL + 57) +#define CPU_OR1K_SPR_EEAR10 (SPR_GRP0_SYS_CTRL + 58) +#define CPU_OR1K_SPR_EEAR11 (SPR_GRP0_SYS_CTRL + 59) +#define CPU_OR1K_SPR_EEAR12 (SPR_GRP0_SYS_CTRL + 60) +#define CPU_OR1K_SPR_EEAR13 (SPR_GRP0_SYS_CTRL + 61) +#define CPU_OR1K_SPR_EEAR14 (SPR_GRP0_SYS_CTRL + 62) +#define CPU_OR1K_SPR_EEAR15 (SPR_GRP0_SYS_CTRL + 63) +#define CPU_OR1K_SPR_ESR0 (SPR_GRP0_SYS_CTRL + 64) +#define CPU_OR1K_SPR_ESR1 (SPR_GRP0_SYS_CTRL + 65) +#define CPU_OR1K_SPR_ESR2 (SPR_GRP0_SYS_CTRL + 66) +#define CPU_OR1K_SPR_ESR3 (SPR_GRP0_SYS_CTRL + 67) +#define CPU_OR1K_SPR_ESR4 (SPR_GRP0_SYS_CTRL + 68) +#define CPU_OR1K_SPR_ESR5 (SPR_GRP0_SYS_CTRL + 69) +#define CPU_OR1K_SPR_ESR6 (SPR_GRP0_SYS_CTRL + 70) +#define CPU_OR1K_SPR_ESR7 (SPR_GRP0_SYS_CTRL + 71) +#define CPU_OR1K_SPR_ESR8 (SPR_GRP0_SYS_CTRL + 72) +#define CPU_OR1K_SPR_ESR9 (SPR_GRP0_SYS_CTRL + 73) +#define CPU_OR1K_SPR_ESR10 (SPR_GRP0_SYS_CTRL + 74) +#define CPU_OR1K_SPR_ESR11 (SPR_GRP0_SYS_CTRL + 75) +#define CPU_OR1K_SPR_ESR12 (SPR_GRP0_SYS_CTRL + 76) +#define CPU_OR1K_SPR_ESR13 (SPR_GRP0_SYS_CTRL + 77) +#define CPU_OR1K_SPR_ESR14 (SPR_GRP0_SYS_CTRL + 78) +#define CPU_OR1K_SPR_ESR15 (SPR_GRP0_SYS_CTRL + 79) + +/* Shadow registers base */ +#define CPU_OR1K_SPR_GPR32 (SPR_GRP0_SYS_CTRL + 1024) + +/* Group1: Data MMU registers */ +#define CPU_OR1K_SPR_DMMUCR (SPR_GRP1_DMMU + 0) +#define CPU_OR1K_SPR_DMMUPR (SPR_GRP1_DMMU + 1) +#define CPU_OR1K_SPR_DTLBEIR (SPR_GRP1_DMMU + 2) +#define CPU_OR1K_SPR_DATBMR0 (SPR_GRP1_DMMU + 4) +#define CPU_OR1K_SPR_DATBMR1 (SPR_GRP1_DMMU + 5) +#define CPU_OR1K_SPR_DATBMR2 (SPR_GRP1_DMMU + 6) +#define CPU_OR1K_SPR_DATBMR3 (SPR_GRP1_DMMU + 7) +#define CPU_OR1K_SPR_DATBTR0 (SPR_GRP1_DMMU + 8) +#define CPU_OR1K_SPR_DATBTR1 (SPR_GRP1_DMMU + 9) +#define CPU_OR1K_SPR_DATBTR2 (SPR_GRP1_DMMU + 10) +#define CPU_OR1K_SPR_DATBTR3 (SPR_GRP1_DMMU + 11) + +/* Group2: Instruction MMU registers */ +#define CPU_OR1K_SPR_IMMUCR (SPR_GRP2_IMMU + 0) +#define CPU_OR1K_SPR_IMMUPR (SPR_GRP2_IMMU + 1) +#define CPU_OR1K_SPR_ITLBEIR (SPR_GRP2_IMMU + 2) +#define CPU_OR1K_SPR_IATBMR0 (SPR_GRP2_IMMU + 4) +#define CPU_OR1K_SPR_IATBMR1 (SPR_GRP2_IMMU + 5) +#define CPU_OR1K_SPR_IATBMR2 (SPR_GRP2_IMMU + 6) +#define CPU_OR1K_SPR_IATBMR3 (SPR_GRP2_IMMU + 7) +#define CPU_OR1K_SPR_IATBTR0 (SPR_GRP2_IMMU + 8) +#define CPU_OR1K_SPR_IATBTR1 (SPR_GRP2_IMMU + 9) +#define CPU_OR1K_SPR_IATBTR2 (SPR_GRP2_IMMU + 10) +#define CPU_OR1K_SPR_IATBTR3 (SPR_GRP2_IMMU + 11) + +/* Group3: Data Cache registers */ +#define CPU_OR1K_SPR_DCCR (SPR_GRP3_DC + 0) +#define CPU_OR1K_SPR_DCBPR (SPR_GRP3_DC + 1) +#define CPU_OR1K_SPR_DCBFR (SPR_GRP3_DC + 2) +#define CPU_OR1K_SPR_DCBIR (SPR_GRP3_DC + 3) +#define CPU_OR1K_SPR_DCBWR (SPR_GRP3_DC + 4) +#define CPU_OR1K_SPR_DCBLR (SPR_GRP3_DC + 5) + +/* Group4: Instruction Cache registers */ +#define CPU_OR1K_SPR_ICCR (SPR_GRP4_IC + 0) +#define CPU_OR1K_SPR_ICBPR (SPR_GRP4_IC + 1) +#define CPU_OR1K_SPR_ICBIR (SPR_GRP4_IC + 2) +#define CPU_OR1K_SPR_ICBLR (SPR_GRP4_IC + 3) + +/* Group5: MAC registers */ +#define CPU_OR1K_SPR_MACLO (SPR_GRP5_MAC + 1) +#define CPU_OR1K_SPR_MACHI (SPR_GRP5_MAC + 2) + +/* Group6: Debug registers */ +#define CPU_OR1K_SPR_DVR0 (SPR_GRP6_DEBUG + 0) +#define CPU_OR1K_SPR_DVR1 (SPR_GRP6_DEBUG + 1) +#define CPU_OR1K_SPR_DVR2 (SPR_GRP6_DEBUG + 2) +#define CPU_OR1K_SPR_DVR3 (SPR_GRP6_DEBUG + 3) +#define CPU_OR1K_SPR_DVR4 (SPR_GRP6_DEBUG + 4) +#define CPU_OR1K_SPR_DVR5 (SPR_GRP6_DEBUG + 5) +#define CPU_OR1K_SPR_DVR6 (SPR_GRP6_DEBUG + 6) +#define CPU_OR1K_SPR_DVR7 (SPR_GRP6_DEBUG + 7) +#define CPU_OR1K_SPR_DCR0 (SPR_GRP6_DEBUG + 8) +#define CPU_OR1K_SPR_DCR1 (SPR_GRP6_DEBUG + 9) +#define CPU_OR1K_SPR_DCR2 (SPR_GRP6_DEBUG + 10) +#define CPU_OR1K_SPR_DCR3 (SPR_GRP6_DEBUG + 11) +#define CPU_OR1K_SPR_DCR4 (SPR_GRP6_DEBUG + 12) +#define CPU_OR1K_SPR_DCR5 (SPR_GRP6_DEBUG + 13) +#define CPU_OR1K_SPR_DCR6 (SPR_GRP6_DEBUG + 14) +#define CPU_OR1K_SPR_DCR7 (SPR_GRP6_DEBUG + 15) +#define CPU_OR1K_SPR_DMR1 (SPR_GRP6_DEBUG + 16) +#define CPU_OR1K_SPR_DMR2 (SPR_GRP6_DEBUG + 17) +#define CPU_OR1K_SPR_DCWR0 (SPR_GRP6_DEBUG + 18) +#define CPU_OR1K_SPR_DCWR1 (SPR_GRP6_DEBUG + 19) +#define CPU_OR1K_SPR_DSR (SPR_GRP6_DEBUG + 20) +#define CPU_OR1K_SPR_DRR (SPR_GRP6_DEBUG + 21) + +/* Group7: Performance counters registers */ +#define CPU_OR1K_SPR_PCCR0 (SPR_GRP7_PERF_CTR + 0) +#define CPU_OR1K_SPR_PCCR1 (SPR_GRP7_PERF_CTR + 1) +#define CPU_OR1K_SPR_PCCR2 (SPR_GRP7_PERF_CTR + 2) +#define CPU_OR1K_SPR_PCCR3 (SPR_GRP7_PERF_CTR + 3) +#define CPU_OR1K_SPR_PCCR4 (SPR_GRP7_PERF_CTR + 4) +#define CPU_OR1K_SPR_PCCR5 (SPR_GRP7_PERF_CTR + 5) +#define CPU_OR1K_SPR_PCCR6 (SPR_GRP7_PERF_CTR + 6) +#define CPU_OR1K_SPR_PCCR7 (SPR_GRP7_PERF_CTR + 7) +#define CPU_OR1K_SPR_PCMR0 (SPR_GRP7_PERF_CTR + 8) +#define CPU_OR1K_SPR_PCMR1 (SPR_GRP7_PERF_CTR + 9) +#define CPU_OR1K_SPR_PCMR2 (SPR_GRP7_PERF_CTR + 10) +#define CPU_OR1K_SPR_PCMR3 (SPR_GRP7_PERF_CTR + 11) +#define CPU_OR1K_SPR_PCMR4 (SPR_GRP7_PERF_CTR + 12) +#define CPU_OR1K_SPR_PCMR5 (SPR_GRP7_PERF_CTR + 13) +#define CPU_OR1K_SPR_PCMR6 (SPR_GRP7_PERF_CTR + 14) +#define CPU_OR1K_SPR_PCMR7 (SPR_GRP7_PERF_CTR + 15) + +/* Group8: Power management register */ +#define CPU_OR1K_SPR_PMR (SPR_GRP8_PWR_MNG + 0) + +/* Group9: PIC registers */ +#define CPU_OR1K_SPR_PICMR (SPR_GRP9_PIC + 0) +#define CPU_OR1K_SPR_PICSR (SPR_GRP9_PIC + 2) + +/* Group10: Tick Timer registers */ +#define CPU_OR1K_SPR_TTMR (SPR_GPR10_TICK_TMR + 0) +#define CPU_OR1K_SPR_TTCR (SPR_GPR10_TICK_TMR + 1) + + /* Shift amount macros for bits position in Supervision Register */ +#define CPU_OR1K_SPR_SR_SHAMT_SM (0) +#define CPU_OR1K_SPR_SR_SHAMT_TEE (1) +#define CPU_OR1K_SPR_SR_SHAMT_IEE (2) +#define CPU_OR1K_SPR_SR_SHAMT_DCE (3) +#define CPU_OR1K_SPR_SR_SHAMT_ICE (4) +#define CPU_OR1K_SPR_SR_SHAMT_DME (5) +#define CPU_OR1K_SPR_SR_SHAMT_IME (6) +#define CPU_OR1K_SPR_SR_SHAMT_LEE (7) +#define CPU_OR1K_SPR_SR_SHAMT_CE (8) +#define CPU_OR1K_SPR_SR_SHAMT_F (9) +#define CPU_OR1K_SPR_SR_SHAMT_CY (10) +#define CPU_OR1K_SPR_SR_SHAMT_OV (11) +#define CPU_OR1K_SPR_SR_SHAMT_OVE (12) +#define CPU_OR1K_SPR_SR_SHAMT_DSX (13) +#define CPU_OR1K_SPR_SR_SHAMT_EPH (14) +#define CPU_OR1K_SPR_SR_SHAMT_FO (15) +#define CPU_OR1K_SPR_SR_SHAMT_SUMRA (16) +#define CPU_OR1K_SPR_SR_SHAMT_CID (28) + +/* Supervision Mode Register. @see OpenRISC architecture manual*/ + + /* Supervisor Mode */ +#define CPU_OR1K_SPR_SR_SM (1 << CPU_OR1K_SPR_SR_SHAMT_SM) +/* Tick Timer Exception Enabled */ +#define CPU_OR1K_SPR_SR_TEE (1 << CPU_OR1K_SPR_SR_SHAMT_TEE) +/* Interrupt Exception Enabled */ +#define CPU_OR1K_SPR_SR_IEE (1 << CPU_OR1K_SPR_SR_SHAMT_IEE) +/* Data Cache Enable */ +#define CPU_OR1K_SPR_SR_DCE (1 << CPU_OR1K_SPR_SR_SHAMT_DCE) +/* Instruction Cache Enable */ +#define CPU_OR1K_SPR_SR_ICE (1 << CPU_OR1K_SPR_SR_SHAMT_ICE) +/* Data MMU Enable */ +#define CPU_OR1K_SPR_SR_DME (1 << CPU_OR1K_SPR_SR_SHAMT_DME) +/* Instruction MMU Enable */ +#define CPU_OR1K_SPR_SR_IME (1 << CPU_OR1K_SPR_SR_SHAMT_IME) +/* Little Endian Enable */ +#define CPU_OR1K_SPR_SR_LEE (1 << CPU_OR1K_SPR_SR_SHAMT_LEE) +/* CID Enable */ +#define CPU_OR1K_SPR_SR_CE (1 << CPU_OR1K_SPR_SR_SHAMT_CE) +/* Conditional branch flag */ +#define CPU_OR1K_SPR_SR_F (1 << CPU_OR1K_SPR_SR_SHAMT_F) +/* Carry flag */ +#define CPU_OR1K_SPR_SR_CY (1 << CPU_OR1K_SPR_SR_SHAMT_CY) +/* Overflow flag */ +#define CPU_OR1K_SPR_SR_OV (1 << CPU_OR1K_SPR_SR_SHAMT_OV) +/* Overflow flag Exception */ +#define CPU_OR1K_SPR_SR_OVE (1 << CPU_OR1K_SPR_SR_SHAMT_OVE) +/* Delay Slot Exception */ +#define CPU_OR1K_SPR_SR_DSX (1 << CPU_OR1K_SPR_SR_SHAMT_DSX) + /* Exception Prefix High */ +#define CPU_OR1K_SPR_SR_EPH (1 << CPU_OR1K_SPR_SR_SHAMT_EPH) +/* Fixed One */ +#define CPU_OR1K_SPR_SR_FO (1 << CPU_OR1K_SPR_SR_SHAMT_FO) +/* SPRs User Mode Read Access */ +#define CPU_OR1K_SPR_SR_SUMRA (1 << CPU_OR1K_SPR_SR_SHAMT_SUMRA) +/*Context ID (Fast Context Switching) */ +#define CPU_OR1K_SPR_SR_CID (F << CPU_OR1K_SPR_SR_SHAMT_CID) + +/* Power management register bits */ +#define CPU_OR1K_SPR_PMR_SHAMT_SDF 0 +#define CPU_OR1K_SPR_PMR_SHAMT_DME 4 +#define CPU_OR1K_SPR_PMR_SHAMT_SME 5 +#define CPU_OR1K_SPR_PMR_SHAMT_DCGE 6 +#define CPU_OR1K_SPR_PMR_SHAMT_SUME 7 + +#define CPU_OR1K_SPR_PMR_SDF (0xF << CPU_OR1K_SPR_PMR_SHAMT_SDF) +#define CPU_OR1K_SPR_PMR_DME (1 << CPU_OR1K_SPR_PMR_SHAMT_DME) +#define CPU_OR1K_SPR_PMR_SME (1 << CPU_OR1K_SPR_PMR_SHAMT_SME) +#define CPU_OR1K_SPR_PMR_DCGE (1 << CPU_OR1K_SPR_PMR_SHAMT_DCGE) +#define CPU_OR1K_SPR_PMR_SUME (1 << CPU_OR1K_SPR_PMR_SHAMT_SUME) + +/* Shift amount macros for bit positions in Power Management register */ + +#ifndef ASM + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Supervision Mode registers definitions. + * + * @see OpenRISC architecture manual - revision 0. + */ +typedef enum { + OR1K_EXCEPTION_RESET = 1, + OR1K_EXCEPTION_BUS_ERR = 2, + OR1K_EXCEPTION_D_PF = 3, /* Data Page Fault */ + OR1K_EXCEPTION_I_PF = 4, /* Instruction Page Fault */ + OR1K_EXCEPTION_TICK_TIMER = 5, + OR1K_EXCEPTION_ALIGNMENT = 6, + OR1K_EXCEPTION_I_UNDEF= 7, /* Undefiend instruction */ + OR1K_EXCEPTION_IRQ = 8, /* External interrupt */ + OR1K_EXCPETION_D_TLB = 9, /* Data TLB miss */ + OR1K_EXCPETION_I_TLB = 10, /* Instruction TLB miss */ + OR1K_EXCPETION_RANGE = 11, /* Range exception */ + OR1K_EXCPETION_SYS_CALL = 12, + OR1K_EXCPETION_FP = 13, /* Floating point exception */ + OR1K_EXCPETION_TRAP = 14, /* Caused by l.trap instruction or by debug unit */ + OR1K_EXCPETION_RESERVED1 = 15, + OR1K_EXCPETION_RESERVED2 = 16, + OR1K_EXCPETION_RESERVED3 = 17, + MAX_EXCEPTIONS = 17, + OR1K_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff +} OR1K_Symbolic_exception_name; + +static inline uint32_t _OR1K_mfspr(uint32_t reg) +{ + uint32_t spr_value; + + asm volatile ( + "l.mfspr %0, %1, 0;\n\t" + : "=r" (spr_value) : "r" (reg)); + + return spr_value; +} + +static inline void _OR1K_mtspr(uint32_t reg, uint32_t value) +{ + asm volatile ( + "l.mtspr %1, %0, 0;\n\t" + :: "r" (value), "r" (reg) + ); +} + +/** + * @brief The slow down feature takes advantage of the low-power + * dividers in external clock generation circuitry to enable full + * functionality, but at a lower frequency so that power consumption + * is reduced. @see OpenRISC architecture manual, power management section. + * + * @param[in] value is 4 bit value to be written in PMR[SDF]. + * A lower value specifies higher expected performance from the processor core. + * + */ +#define _OR1K_CPU_SlowDown(value) \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, (value & CPU_OR1K_SPR_PMR_SDF)) + + +#define _OR1K_CPU_Doze() \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_DME) + + +#define _OR1K_CPU_Sleep() \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME) + + +#define _OR1K_CPU_Suspend() \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME) + +static inline void _OR1K_Sync_mem( void ) +{ + asm volatile("l.msync"); +} + +static inline void _OR1K_Sync_pipeline( void ) +{ + asm volatile("l.psync"); +} + +#else /* ASM */ + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_OR1K_UTILITY_H */ diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k.h b/cpukit/score/cpu/or1k/rtems/score/or1k.h new file mode 100644 index 0000000..e1a3ddc --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/score/or1k.h @@ -0,0 +1,49 @@ +/** + * @file rtems/score/or1k.h + */ + +/* + * This file contains information pertaining to the OR1K processor. + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * Based on code with the following copyright... + * COPYRIGHT (c) 1989-1999, 2010. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_OR1K_H +#define _RTEMS_SCORE_OR1K_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the OR1K family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + + /* + * Define the name of the CPU family and specific model. + */ + +#define CPU_NAME "OR1K" +#define CPU_MODEL_NAME "OR1200" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_OR1K_H */ diff --git a/cpukit/score/cpu/or1k/rtems/score/types.h b/cpukit/score/cpu/or1k/rtems/score/types.h new file mode 100644 index 0000000..843a10f --- /dev/null +++ b/cpukit/score/cpu/or1k/rtems/score/types.h @@ -0,0 +1,51 @@ +/** + * @file + * + * @brief OR1K Architecture Types API + */ + +/* + * This include file contains type definitions pertaining to the + * arm processor family. + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + + #ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup ScoreCPU + */ +/**@{**/ + +/* + * This section defines the basic types for this processor. + */ + +typedef uint16_t Priority_bit_map_Word; +typedef void or1k_isr; +typedef void ( *or1k_isr_entry )( void ); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif From joel at rtems.org Tue Aug 12 18:38:06 2014 From: joel at rtems.org (Joel Sherrill) Date: Tue, 12 Aug 2014 13:38:06 -0500 Subject: [rtems commit] or1k/.../preinstall.am: Add missing file Message-ID: <20140812183806.D5E5D700903@git.rtems.org> Module: rtems Branch: master Commit: 700f97ea675f3fdd9c8b4b9ff315a5c6b2e45c74 Changeset: http://git.rtems.org/rtems/commit/?id=700f97ea675f3fdd9c8b4b9ff315a5c6b2e45c74 Author: Joel Sherrill Date: Tue Aug 12 13:46:49 2014 -0500 or1k/.../preinstall.am: Add missing file --- cpukit/score/cpu/or1k/preinstall.am | 49 +++++++++++++++++++++++++++++++++++ 1 files changed, 49 insertions(+), 0 deletions(-) diff --git a/cpukit/score/cpu/or1k/preinstall.am b/cpukit/score/cpu/or1k/preinstall.am new file mode 100644 index 0000000..f4d7153 --- /dev/null +++ b/cpukit/score/cpu/or1k/preinstall.am @@ -0,0 +1,49 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) + +$(PROJECT_INCLUDE)/rtems/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems + @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h + +$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score + @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h + +$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h + +$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h + +$(PROJECT_INCLUDE)/rtems/score/or1k.h: rtems/score/or1k.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/or1k.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/or1k.h + +$(PROJECT_INCLUDE)/rtems/score/or1k-utility.h: rtems/score/or1k-utility.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/or1k-utility.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/or1k-utility.h + From sebh at rtems.org Thu Aug 14 12:19:47 2014 From: sebh at rtems.org (Sebastian Huber) Date: Thu, 14 Aug 2014 07:19:47 -0500 Subject: [rtems commit] arm: PR2186: Fix compile error Message-ID: <20140814121947.7C3517008D8@git.rtems.org> Module: rtems Branch: master Commit: 1a2d349776f8072ec6a45cc8dfa4fa02d87489f4 Changeset: http://git.rtems.org/rtems/commit/?id=1a2d349776f8072ec6a45cc8dfa4fa02d87489f4 Author: Sebastian Huber Date: Thu Aug 14 14:27:40 2014 +0200 arm: PR2186: Fix compile error --- cpukit/score/cpu/arm/armv7m-context-switch.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/cpukit/score/cpu/arm/armv7m-context-switch.c b/cpukit/score/cpu/arm/armv7m-context-switch.c index 359a1a7..aa09276 100644 --- a/cpukit/score/cpu/arm/armv7m-context-switch.c +++ b/cpukit/score/cpu/arm/armv7m-context-switch.c @@ -54,9 +54,11 @@ void __attribute__((naked)) _CPU_Context_switch( "bx lr\n" : : [spctxoff] "J" (offsetof(Context_Control, register_sp)), +#ifdef ARM_MULTILIB_VFP + [d8off] "J" (ARM_CONTEXT_CONTROL_D8_OFFSET), +#endif [isrctxoff] "J" (offsetof(Context_Control, isr_nest_level)), - [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level)), - [d8off] "J" (ARM_CONTEXT_CONTROL_D8_OFFSET) + [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level)) ); } From joel at rtems.org Mon Aug 18 22:01:22 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 18 Aug 2014 17:01:22 -0500 Subject: [rtems commit] Add or1k tick timer register definitions Message-ID: <20140818220123.390347006BA@git.rtems.org> Module: rtems Branch: master Commit: de62e5d861f41f7f8898ed7c8fbe9ee1201af880 Changeset: http://git.rtems.org/rtems/commit/?id=de62e5d861f41f7f8898ed7c8fbe9ee1201af880 Author: Hesham ALMatary Date: Mon Aug 18 16:06:46 2014 -0500 Add or1k tick timer register definitions --- cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 16 ++++++++++++++-- 1 files changed, 14 insertions(+), 2 deletions(-) diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h index 74c14d7..6b238b1 100644 --- a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h +++ b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h @@ -258,7 +258,21 @@ /*Context ID (Fast Context Switching) */ #define CPU_OR1K_SPR_SR_CID (F << CPU_OR1K_SPR_SR_SHAMT_CID) +/* Tick timer configuration bits */ +#define CPU_OR1K_SPR_TTMR_SHAMT_IP 28 +#define CPU_OR1K_SPR_TTMR_SHAMT_IE 29 +#define CPU_OR1K_SPR_TTMR_SHAMT_MODE 30 + +#define CPU_OR1K_SPR_TTMR_TP_MASK (0x0FFFFFFF) +#define CPU_OR1K_SPR_TTMR_IP (1 << CPU_OR1K_SPR_TTMR_SHAMT_IP) +#define CPU_OR1K_SPR_TTMR_IE (1 << CPU_OR1K_SPR_TTMR_SHAMT_IE) +#define CPU_OR1K_SPR_TTMR_MODE_RESTART (1 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) +#define CPU_OR1K_SPR_TTMR_MODE_ONE_SHOT (2 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) +#define CPU_OR1K_SPR_TTMR_MODE_CONT (3 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) + /* Power management register bits */ + +/* Shift amount macros for bit positions in Power Management register */ #define CPU_OR1K_SPR_PMR_SHAMT_SDF 0 #define CPU_OR1K_SPR_PMR_SHAMT_DME 4 #define CPU_OR1K_SPR_PMR_SHAMT_SME 5 @@ -271,8 +285,6 @@ #define CPU_OR1K_SPR_PMR_DCGE (1 << CPU_OR1K_SPR_PMR_SHAMT_DCGE) #define CPU_OR1K_SPR_PMR_SUME (1 << CPU_OR1K_SPR_PMR_SHAMT_SUME) -/* Shift amount macros for bit positions in Power Management register */ - #ifndef ASM #include From joel at rtems.org Mon Aug 18 23:31:17 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 18 Aug 2014 18:31:17 -0500 Subject: [rtems commit] rtems_termios_puts: Copy and write more than one char at once Message-ID: <20140818233118.0DB4D7006BA@git.rtems.org> Module: rtems Branch: master Commit: 3654667f77851c02b05bb3f964b8e56a5a529912 Changeset: http://git.rtems.org/rtems/commit/?id=3654667f77851c02b05bb3f964b8e56a5a529912 Author: Kolja Waschk Date: Thu Aug 14 10:02:29 2014 -0500 rtems_termios_puts: Copy and write more than one char at once Renamed startXmit(), nToSend is unsigned, just check FL_ORCVXOF, no (void) cast anymore, compute nToSend in single if/else if/else. --- cpukit/libcsupport/src/termios.c | 135 ++++++++++++++++++++++++-------------- 1 files changed, 85 insertions(+), 50 deletions(-) diff --git a/cpukit/libcsupport/src/termios.c b/cpukit/libcsupport/src/termios.c index 2448ea1..33cbacb 100644 --- a/cpukit/libcsupport/src/termios.c +++ b/cpukit/libcsupport/src/termios.c @@ -974,6 +974,49 @@ rtems_termios_ioctl (void *arg) } /* + * Send as many chars at once as possible to device-specific code. + * If transmitting==true then assume transmission is already running and + * an explicit write(0) is needed if output has to stop for flow control. + */ +static unsigned int +startXmit ( + struct rtems_termios_tty *tty, + unsigned int newTail, + bool transmitting +) +{ + unsigned int nToSend; + + tty->rawOutBufState = rob_busy; + + /* if XOFF was received, do not (re)start output */ + if (tty->flow_ctrl & FL_ORCVXOF) { + /* set flag, that output has been stopped */ + tty->flow_ctrl |= FL_OSTOP; + nToSend = 0; + /* stop transmitter */ + if (transmitting) { + (*tty->handler.write) (tty, NULL, 0); + } + } else { + /* when flow control XON or XOF, don't send blocks of data */ + /* to allow fast reaction on incoming flow ctrl and low latency*/ + /* for outgoing flow control */ + if (tty->flow_ctrl & (FL_MDXON | FL_MDXOF)) + nToSend = 1; + else if (newTail > tty->rawOutBuf.Head) + nToSend = tty->rawOutBuf.Size - newTail; + else + nToSend = tty->rawOutBuf.Head - newTail; + + (*tty->handler.write)( + tty, &tty->rawOutBuf.theBuf[newTail], nToSend); + } + + return nToSend; +} + +/* * Send characters to device-specific code */ void @@ -989,21 +1032,16 @@ rtems_termios_puts ( (*tty->handler.write)(tty, buf, len); return; } - newHead = tty->rawOutBuf.Head; + while (len) { - /* - * Performance improvement could be made here. - * Copy multiple bytes to raw buffer: - * if (len > 1) && (space to buffer end, or tail > 1) - * ncopy = MIN (len, space to buffer end or tail) - * memcpy (raw buffer, buf, ncopy) - * buf += ncopy - * len -= ncopy - * - * To minimize latency, the memcpy should be done - * with interrupts enabled. - */ - newHead = (newHead + 1) % tty->rawOutBuf.Size; + size_t nToCopy; + size_t nAvail; + + /* Check space for at least one char */ + newHead = tty->rawOutBuf.Head + 1; + if (newHead >= tty->rawOutBuf.Size) + newHead -= tty->rawOutBuf.Size; + rtems_termios_interrupt_lock_acquire (tty, &lock_context); while (newHead == tty->rawOutBuf.Tail) { tty->rawOutBufState = rob_wait; @@ -1014,21 +1052,41 @@ rtems_termios_puts ( rtems_fatal_error_occurred (sc); rtems_termios_interrupt_lock_acquire (tty, &lock_context); } - tty->rawOutBuf.theBuf[tty->rawOutBuf.Head] = *buf++; + + /* Determine free space up to current tail or end of ring buffer */ + nToCopy = len; + if (tty->rawOutBuf.Tail > tty->rawOutBuf.Head) { + /* Available space is contiguous from Head to Tail */ + nAvail = tty->rawOutBuf.Tail - tty->rawOutBuf.Head - 1; + } else { + /* Available space wraps at buffer end. To keep it simple, utilize + only the free space from Head to end during this iteration */ + nAvail = tty->rawOutBuf.Size - tty->rawOutBuf.Head; + /* Head may not touch Tail after wraparound */ + if (tty->rawOutBuf.Tail == 0) + nAvail--; + } + if (nToCopy > nAvail) + nToCopy = nAvail; + + /* To minimize latency, the memcpy could be done + * with interrupts enabled or with limit on nToCopy (TBD) + */ + memcpy(&tty->rawOutBuf.theBuf[tty->rawOutBuf.Head], buf, nToCopy); + + newHead = tty->rawOutBuf.Head + nToCopy; + if (newHead >= tty->rawOutBuf.Size) + newHead -= tty->rawOutBuf.Size; tty->rawOutBuf.Head = newHead; + if (tty->rawOutBufState == rob_idle) { - /* check, whether XOFF has been received */ - if (!(tty->flow_ctrl & FL_ORCVXOF)) { - (*tty->handler.write)( - tty, &tty->rawOutBuf.theBuf[tty->rawOutBuf.Tail],1); - } else { - /* remember that output has been stopped due to flow ctrl*/ - tty->flow_ctrl |= FL_OSTOP; - } - tty->rawOutBufState = rob_busy; + startXmit (tty, tty->rawOutBuf.Tail, false); } + rtems_termios_interrupt_lock_release (tty, &lock_context); - len--; + + buf += nToCopy; + len -= nToCopy; } } @@ -1678,35 +1736,12 @@ rtems_termios_refill_transmitter (struct rtems_termios_tty *tty) if ( tty->tty_snd.sw_pfn != NULL) { (*tty->tty_snd.sw_pfn)(&tty->termios, tty->tty_snd.sw_arg); } - } - /* check, whether output should stop due to received XOFF */ - else if ((tty->flow_ctrl & (FL_MDXON | FL_ORCVXOF)) - == (FL_MDXON | FL_ORCVXOF)) { - /* Buffer not empty, but output stops due to XOFF */ - /* set flag, that output has been stopped */ - tty->flow_ctrl |= FL_OSTOP; - tty->rawOutBufState = rob_busy; /*apm*/ - (*tty->handler.write) (tty, NULL, 0); - nToSend = 0; } else { /* - * Buffer not empty, start tranmitter + * Buffer not empty, check flow control, start transmitter */ - if (newTail > tty->rawOutBuf.Head) - nToSend = tty->rawOutBuf.Size - newTail; - else - nToSend = tty->rawOutBuf.Head - newTail; - /* when flow control XON or XOF, don't send blocks of data */ - /* to allow fast reaction on incoming flow ctrl and low latency*/ - /* for outgoing flow control */ - if (tty->flow_ctrl & (FL_MDXON | FL_MDXOF)) { - nToSend = 1; - } - tty->rawOutBufState = rob_busy; /*apm*/ - (*tty->handler.write)( - tty, &tty->rawOutBuf.theBuf[newTail], nToSend); + nToSend = startXmit (tty, newTail, true); } - tty->rawOutBuf.Tail = newTail; /*apm*/ } rtems_termios_interrupt_lock_release (tty, &lock_context); From sebh at rtems.org Wed Aug 20 06:09:33 2014 From: sebh at rtems.org (Sebastian Huber) Date: Wed, 20 Aug 2014 01:09:33 -0500 Subject: [rtems commit] score: PR2179: Fix initially locked PI mutex Message-ID: <20140820060933.D651C7006BA@git.rtems.org> Module: rtems Branch: master Commit: bba3507723041f451c9da1ecee43819bcbe57f23 Changeset: http://git.rtems.org/rtems/commit/?id=bba3507723041f451c9da1ecee43819bcbe57f23 Author: Sebastian Huber Date: Tue Aug 19 17:43:36 2014 +0200 score: PR2179: Fix initially locked PI mutex --- cpukit/score/src/coremutex.c | 15 +++++++++++---- testsuites/sptests/sp51/init.c | 36 ++++++++++++++++++++++++++++++++++++ testsuites/sptests/sp51/sp51.doc | 3 +++ 3 files changed, 50 insertions(+), 4 deletions(-) diff --git a/cpukit/score/src/coremutex.c b/cpukit/score/src/coremutex.c index e13c7aa..949aa70 100644 --- a/cpukit/score/src/coremutex.c +++ b/cpukit/score/src/coremutex.c @@ -39,10 +39,14 @@ CORE_mutex_Status _CORE_mutex_Initialize( the_mutex->Attributes = *the_mutex_attributes; if ( initially_locked ) { + bool is_priority_ceiling = + _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ); + the_mutex->nest_count = 1; the_mutex->holder = executing; - if ( _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) || - _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) { + + if ( is_priority_ceiling || + _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) ) { Priority_Control ceiling = the_mutex->Attributes.priority_ceiling; /* @@ -52,7 +56,7 @@ CORE_mutex_Status _CORE_mutex_Initialize( */ _Thread_Disable_dispatch(); - if ( executing->current_priority < ceiling ) { + if ( is_priority_ceiling && executing->current_priority < ceiling ) { _Thread_Enable_dispatch(); return CORE_MUTEX_STATUS_CEILING_VIOLATED; } @@ -65,7 +69,10 @@ CORE_mutex_Status _CORE_mutex_Initialize( executing->resource_count++; - _Thread_Change_priority( executing, ceiling, false ); + if ( is_priority_ceiling ) { + _Thread_Change_priority( executing, ceiling, false ); + } + _Thread_Enable_dispatch(); } } else { diff --git a/testsuites/sptests/sp51/init.c b/testsuites/sptests/sp51/init.c index 98d362f..48f0146 100644 --- a/testsuites/sptests/sp51/init.c +++ b/testsuites/sptests/sp51/init.c @@ -18,6 +18,40 @@ const char rtems_test_name[] = "SP 51"; /* forward declarations to avoid warnings */ rtems_task Init(rtems_task_argument argument); +static void test_create_initially_locked_prio_inherit_sema(void) +{ + rtems_status_code sc; + rtems_id id; + rtems_task_priority prio_a; + rtems_task_priority prio_b; + rtems_task_priority prio_ceiling = 0; + + sc = rtems_task_set_priority(RTEMS_SELF, RTEMS_CURRENT_PRIORITY, &prio_a); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + rtems_test_assert(prio_a != prio_ceiling); + + sc = rtems_semaphore_create( + rtems_build_name( 'S', 'E', 'M', 'A' ), + 0, + RTEMS_BINARY_SEMAPHORE | RTEMS_PRIORITY | RTEMS_INHERIT_PRIORITY, + prio_ceiling, + &id + ); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_task_set_priority(RTEMS_SELF, RTEMS_CURRENT_PRIORITY, &prio_b); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + rtems_test_assert(prio_a == prio_b); + + sc = rtems_semaphore_release(id); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_semaphore_delete(id); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); +} + rtems_task Init( rtems_task_argument argument ) @@ -57,6 +91,8 @@ rtems_task Init( fatal_directive_status( sc, RTEMS_NOT_OWNER_OF_RESOURCE, "rtems_semaphore_release" ); + test_create_initially_locked_prio_inherit_sema(); + TEST_END(); rtems_test_exit( 0 ); } diff --git a/testsuites/sptests/sp51/sp51.doc b/testsuites/sptests/sp51/sp51.doc index a1003db..fac5534 100644 --- a/testsuites/sptests/sp51/sp51.doc +++ b/testsuites/sptests/sp51/sp51.doc @@ -23,3 +23,6 @@ concepts: + Ensure the when the binary semaphore lock fails to acquire the mutex, it is an error to release it since the lock failed. + ++ Verify that creation of an initially locked priority inheritance mutex does + not change the priority of the executing thread. From sebh at rtems.org Wed Aug 20 06:12:24 2014 From: sebh at rtems.org (Sebastian Huber) Date: Wed, 20 Aug 2014 01:12:24 -0500 Subject: [rtems commit] score: PR2179: Fix initially locked PI mutex Message-ID: <20140820061224.8450C7006BA@git.rtems.org> Module: rtems Branch: 4.10 Commit: a62a3c32b1788f8d1dd318b5e36acc1cf16daf69 Changeset: http://git.rtems.org/rtems/commit/?id=a62a3c32b1788f8d1dd318b5e36acc1cf16daf69 Author: Sebastian Huber Date: Tue Aug 19 17:43:36 2014 +0200 score: PR2179: Fix initially locked PI mutex --- cpukit/score/src/coremutex.c | 14 ++++++++++---- testsuites/sptests/sp51/init.c | 36 ++++++++++++++++++++++++++++++++++++ testsuites/sptests/sp51/sp51.doc | 3 +++ 3 files changed, 49 insertions(+), 4 deletions(-) diff --git a/cpukit/score/src/coremutex.c b/cpukit/score/src/coremutex.c index 9745f82..261e18e 100644 --- a/cpukit/score/src/coremutex.c +++ b/cpukit/score/src/coremutex.c @@ -59,14 +59,19 @@ CORE_mutex_Status _CORE_mutex_Initialize( the_mutex->blocked_count = 0; if ( initial_lock == CORE_MUTEX_LOCKED ) { + bool is_priority_ceiling = + _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ); + the_mutex->nest_count = 1; the_mutex->holder = _Thread_Executing; the_mutex->holder_id = _Thread_Executing->Object.id; - if ( _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) || - _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) { + + if ( is_priority_ceiling || + _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) ) { Priority_Control ceiling = the_mutex->Attributes.priority_ceiling; - if ( _Thread_Executing->current_priority < ceiling ) + if ( is_priority_ceiling && + _Thread_Executing->current_priority < ceiling ) return CORE_MUTEX_STATUS_CEILING_VIOLATED; #ifdef __RTEMS_STRICT_ORDER_MUTEX__ _Chain_Prepend_unprotected( &_Thread_Executing->lock_mutex, @@ -75,7 +80,8 @@ CORE_mutex_Status _CORE_mutex_Initialize( #endif _Thread_Executing->resource_count++; - _Thread_Change_priority( _Thread_Executing, ceiling, false ); + if ( is_priority_ceiling ) + _Thread_Change_priority( _Thread_Executing, ceiling, false ); } } else { the_mutex->nest_count = 0; diff --git a/testsuites/sptests/sp51/init.c b/testsuites/sptests/sp51/init.c index 8f34cab..82deb53 100644 --- a/testsuites/sptests/sp51/init.c +++ b/testsuites/sptests/sp51/init.c @@ -11,6 +11,40 @@ #include +static void test_create_initially_locked_prio_inherit_sema(void) +{ + rtems_status_code sc; + rtems_id id; + rtems_task_priority prio_a; + rtems_task_priority prio_b; + rtems_task_priority prio_ceiling = 0; + + sc = rtems_task_set_priority(RTEMS_SELF, RTEMS_CURRENT_PRIORITY, &prio_a); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + rtems_test_assert(prio_a != prio_ceiling); + + sc = rtems_semaphore_create( + rtems_build_name( 'S', 'E', 'M', 'A' ), + 0, + RTEMS_BINARY_SEMAPHORE | RTEMS_PRIORITY | RTEMS_INHERIT_PRIORITY, + prio_ceiling, + &id + ); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_task_set_priority(RTEMS_SELF, RTEMS_CURRENT_PRIORITY, &prio_b); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + rtems_test_assert(prio_a == prio_b); + + sc = rtems_semaphore_release(id); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_semaphore_delete(id); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); +} + rtems_task Init( rtems_task_argument argument ) @@ -50,6 +84,8 @@ rtems_task Init( sc = rtems_semaphore_release( mutex ); directive_failed( sc, "rtems_semaphore_release" ); + test_create_initially_locked_prio_inherit_sema(); + puts( "*** END OF TEST 51 ***" ); rtems_test_exit( 0 ); } diff --git a/testsuites/sptests/sp51/sp51.doc b/testsuites/sptests/sp51/sp51.doc index bbf162a..fee5cf3 100644 --- a/testsuites/sptests/sp51/sp51.doc +++ b/testsuites/sptests/sp51/sp51.doc @@ -26,3 +26,6 @@ concepts: + Ensure the when the binary semaphore lock fails to acquire the mutex, it is an error to release it since the lock failed. + ++ Verify that creation of an initially locked priority inheritance mutex does + not change the priority of the executing thread. From sebh at rtems.org Wed Aug 20 11:34:17 2014 From: sebh at rtems.org (Sebastian Huber) Date: Wed, 20 Aug 2014 06:34:17 -0500 Subject: [rtems commit] lpc24xx/lpc17xx: lpc24xx_pin_set_function() keep LPC4088 W type pin in digital mode for non-analog function. Message-ID: <20140820113417.63B727006BA@git.rtems.org> Module: rtems Branch: master Commit: 0a66c1266f1f0968345b2a0bcb7acbeeba0c1d82 Changeset: http://git.rtems.org/rtems/commit/?id=0a66c1266f1f0968345b2a0bcb7acbeeba0c1d82 Author: Pavel Pisa Date: Sat Aug 16 16:15:17 2014 +0200 lpc24xx/lpc17xx: lpc24xx_pin_set_function() keep LPC4088 W type pin in digital mode for non-analog function. The problem wit incorrect switching of pins into analog mode manifestes on LPC4088 based board. LPC4088 implements pin P1.17 (ENET_MDIO) as new W type (digital pin with analog option). The pin was listed as D category on LPC1788 which does not have analog mode control bit. If analog option is not explicitly switched off on LPC4088 then the pin does not work as digital pin. Code tested on LPC1788 and no problems has been observed even that manual specifies the IOCON_ADMODE field as reserved and should be written as zero. But even RTEMS lpc24xx_gpio_config sets this bit unconditionally. Signed-off-by: Pavel Pisa --- c/src/lib/libbsp/arm/lpc24xx/misc/io.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/arm/lpc24xx/misc/io.c b/c/src/lib/libbsp/arm/lpc24xx/misc/io.c index 45e0c94..c28b518 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/misc/io.c +++ b/c/src/lib/libbsp/arm/lpc24xx/misc/io.c @@ -395,9 +395,14 @@ lpc24xx_pin_set_function( rtems_interrupt_enable(level); #else uint32_t iocon_extra = 0; + uint32_t iocon_not_analog = IOCON_ADMODE; /* TODO */ switch (pin_range.fields.type) { + case LPC17XX_PIN_TYPE_ADC: + case LPC17XX_PIN_TYPE_DAC: + iocon_not_analog = 0; + break; case LPC17XX_PIN_TYPE_I2C_FAST_PLUS: iocon_extra |= IOCON_HS; break; @@ -408,7 +413,7 @@ lpc24xx_pin_set_function( break; } - *iocon = IOCON_FUNC(pin_range.fields.function) | iocon_extra; + *iocon = IOCON_FUNC(pin_range.fields.function) | iocon_extra | iocon_not_analog; #endif return RTEMS_SUCCESSFUL; From gedare at rtems.org Wed Aug 20 17:37:01 2014 From: gedare at rtems.org (Gedare Bloom) Date: Wed, 20 Aug 2014 12:37:01 -0500 Subject: [rtems commit] BSP for TMS570LS31x Hercules Development Kit from TI ( TMS570LS3137) Message-ID: <20140820173701.E2DAB7006BA@git.rtems.org> Module: rtems Branch: master Commit: 4407ee675cb22e8bb870a76eafc590eb6e754315 Changeset: http://git.rtems.org/rtems/commit/?id=4407ee675cb22e8bb870a76eafc590eb6e754315 Author: Premysl Houdek Date: Wed Aug 20 17:24:23 2014 +0200 BSP for TMS570LS31x Hercules Development Kit from TI (TMS570LS3137) Included variants: tms570ls3137_hdk_intram - place code and data into internal SRAM tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM tms570ls3137_hdk - variant prepared for stand-alone RTEMS aplication stored and running directly from flash. Not working yet. Chip initialization code not included in BSP. External startup generated by TI's HalCoGen was used for testing and debugging. More information about TMS570 BSP can be found at http://www.rtems.org/wiki/index.php/Tms570 Patch version 2 - most of the formatting suggestion applied. - BSP converted to use clock shell - console driver "set attributes" tested. Baudrate change working Patch version 3 - more formatting changes. - removed leftover defines and test functions Todo: refactor header files (name register fields) --- c/src/lib/libbsp/arm/tms570/Makefile.am | 145 +++++ c/src/lib/libbsp/arm/tms570/README | 67 +++ c/src/lib/libbsp/arm/tms570/bsp_specs | 13 + c/src/lib/libbsp/arm/tms570/clock/clock.c | 159 ++++++ c/src/lib/libbsp/arm/tms570/configure.ac | 52 ++ .../lib/libbsp/arm/tms570/console/printk-support.c | 85 +++ c/src/lib/libbsp/arm/tms570/console/tms570-sci.c | 559 ++++++++++++++++++++ c/src/lib/libbsp/arm/tms570/include/bsp.h | 59 ++ c/src/lib/libbsp/arm/tms570/include/irq.h | 156 ++++++ c/src/lib/libbsp/arm/tms570/include/tms570-pom.h | 101 ++++ c/src/lib/libbsp/arm/tms570/include/tms570-rti.h | 95 ++++ .../libbsp/arm/tms570/include/tms570-sci-driver.h | 57 ++ c/src/lib/libbsp/arm/tms570/include/tms570-sci.h | 76 +++ c/src/lib/libbsp/arm/tms570/include/tms570-vim.h | 75 +++ c/src/lib/libbsp/arm/tms570/include/tms570.h | 28 + c/src/lib/libbsp/arm/tms570/irq/irq.c | 207 ++++++++ .../make/custom/tms570ls3137_hdk-testsuite.tcfg | 19 + .../arm/tms570/make/custom/tms570ls3137_hdk.cfg | 20 + .../tms570/make/custom/tms570ls3137_hdk_intram.cfg | 20 + .../tms570/make/custom/tms570ls3137_hdk_sdram.cfg | 20 + c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c | 53 ++ c/src/lib/libbsp/arm/tms570/preinstall.am | 123 +++++ c/src/lib/libbsp/arm/tms570/startup/bspreset.c | 36 ++ c/src/lib/libbsp/arm/tms570/startup/bspstart.c | 41 ++ .../lib/libbsp/arm/tms570/startup/bspstarthooks.c | 41 ++ .../arm/tms570/startup/linkcmds.tms570ls3137_hdk | 27 + .../startup/linkcmds.tms570ls3137_hdk_intram | 28 + .../tms570/startup/linkcmds.tms570ls3137_hdk_sdram | 27 + 28 files changed, 2389 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/arm/tms570/Makefile.am b/c/src/lib/libbsp/arm/tms570/Makefile.am new file mode 100644 index 0000000..02d7b66 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/Makefile.am @@ -0,0 +1,145 @@ +## +# +# @file makefile.am +# +# @brief Makefile of LibBSP for the TMS570 boards. +# + +ACLOCAL_AMFLAGS = -I ../../../../aclocal + +include $(top_srcdir)/../../../../automake/compile.am + +include_bspdir = $(includedir)/bsp + +dist_project_lib_DATA = bsp_specs + +# ---------------------------- +# ------ Headers +# ---------------------------- + +include_HEADERS = include/bsp.h + +nodist_include_HEADERS = ../../shared/include/coverhd.h +nodist_include_HEADERS += include/bspopts.h + +nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h + +include_bsp_HEADERS = +include_bsp_HEADERS += ../../shared/include/utility.h +include_bsp_HEADERS += ../../shared/include/irq-generic.h +include_bsp_HEADERS += ../../shared/include/irq-info.h +include_bsp_HEADERS += ../../shared/include/stackalloc.h +include_bsp_HEADERS += ../../shared/include/uart-output-char.h +include_bsp_HEADERS += ../../shared/tod.h +include_bsp_HEADERS += ../shared/include/start.h +include_bsp_HEADERS += include/tms570.h +include_bsp_HEADERS += include/tms570-sci.h +include_bsp_HEADERS += include/irq.h +include_bsp_HEADERS += include/tms570-rti.h +include_bsp_HEADERS += include/tms570-vim.h +include_bsp_HEADERS += include/tms570-pom.h +include_bsp_HEADERS += include/tms570-sci-driver.h + +include_HEADERS += ../../shared/include/tm27.h + +# ---------------------------- +# ------ Data +# ---------------------------- + +noinst_LIBRARIES = libbspstart.a + +libbspstart_a_SOURCES = ../shared/start/start.S + +project_lib_DATA = start.$(OBJEXT) +project_lib_DATA += startup/linkcmds + +EXTRA_DIST = +EXTRA_DIST += startup/linkcmds.tms570ls3137_hdk +EXTRA_DIST += startup/linkcmds.tms570ls3137_hdk_sdram +EXTRA_DIST += startup/linkcmds.tms570ls3137_hdk_intram + +# ---------------------------- +# ------ LibBSP +# ---------------------------- + +noinst_LIBRARIES += libbsp.a + +libbsp_a_SOURCES = +libbsp_a_CPPFLAGS = +libbsp_a_LIBADD = + +# Shared +libbsp_a_SOURCES += ../../shared/bootcard.c +libbsp_a_SOURCES += ../../shared/bspclean.c +libbsp_a_SOURCES += ../../shared/bspgetworkarea.c +libbsp_a_SOURCES += ../../shared/bsplibc.c +libbsp_a_SOURCES += ../../shared/bsppost.c +libbsp_a_SOURCES += ../../shared/bsppredriverhook.c +libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c +libbsp_a_SOURCES += ../../shared/sbrk.c +libbsp_a_SOURCES += ../../shared/src/stackalloc.c + +# Startup +libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S +libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c +libbsp_a_SOURCES += startup/bspreset.c +libbsp_a_SOURCES += startup/bspstart.c + +# POM +libbsp_a_SOURCES += pom/tms570-pom.c + +# IRQ +libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c +libbsp_a_SOURCES += ../../shared/src/irq-generic.c +libbsp_a_SOURCES += ../../shared/src/irq-info.c +libbsp_a_SOURCES += ../../shared/src/irq-legacy.c +libbsp_a_SOURCES += ../../shared/src/irq-server.c +libbsp_a_SOURCES += ../../shared/src/irq-shell.c +libbsp_a_SOURCES += irq/irq.c + +# Console +libbsp_a_SOURCES += ../../shared/console-termios.c +libbsp_a_SOURCES += console/printk-support.c +libbsp_a_SOURCES += console/tms570-sci.c + +# Clock +libbsp_a_SOURCES += ../../shared/clockdrv_shell.h +libbsp_a_SOURCES += clock/clock.c + +# RTC + +# GPIO + +# Timer + +# Benchmark Timer + +# Misc + +# Watchdog + +# Start hooks +libbsp_a_SOURCES += startup/bspstarthooks.c + +# Network + +if HAS_NETWORKING + +noinst_PROGRAMS = network.rel + +network_rel_CPPFLAGS = $(AM_CPPFLAGS) +network_rel_CPPFLAGS += -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE +network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + +libbsp_a_LIBADD += network.rel + +endif + +# ---------------------------- +# ------ Special Rules +# ---------------------------- + +DISTCLEANFILES = include/bspopts.h + +include $(srcdir)/preinstall.am +include $(top_srcdir)/../../../../automake/local.am diff --git a/c/src/lib/libbsp/arm/tms570/README b/c/src/lib/libbsp/arm/tms570/README new file mode 100644 index 0000000..e1be925 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/README @@ -0,0 +1,67 @@ +Development Board: TMS570LS31x Hercules Development Kit from TI + +http://www.ti.com/tool/tmds570ls31hdk + +Drivers: + + o Console + o Clock + o Ethernet - work in progress + +BSP variants: + tms570ls3137_hdk_intram - place code and data into internal SRAM + tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM + tms570ls3137_hdk - variant prepared for stand-alone RTEMS application + stored and running directly from flash. Not working yet. + +Tool-chain + GCC 4.9.0 + Newlib 2.1.0 + Binutils 2.24 configuration: + + CFLAGS="-O2 -pipe" LDFLAGS=-s \ + ../../../src/gcc-4.9/configure --target=arm-rtems4.11 --prefix=/usr \ + --enable-languages=c,c++ \ + --disable-libstdcxx-pch \ + --with-gnu-ld \ + --with-gnu-as \ + --enable-threads \ + --enable-target-optspace \ + --with-system-zlib \ + --verbose \ + --disable-nls --without-included-gettext \ + --disable-win32-registry \ + --with-newlib \ + --enable-plugin \ + --enable-newlib-io-c99-formats \ + --enable-version-specific-runtime-libs \ + --enable-newlib-iconv \ + --disable-lto \ + +Patches required for Cortex-R and big-endian ARM support are already +accepted by the mainline. + +Execution + +Currently, a bootloader is not used. For test and debug purposes, TI's +HalCoGen generated application is used to set up the board and then +the RTEMS application image is loaded using OpenOCD to internal +EEC SRAM or external DRAM. The following features are +not implemented in the BSP: + + + Initial complex CPU and peripheral initialization + + Cores Self-test + +Setup application code is available there: + https://github.com/hornmich/tms570ls3137-hdk-sdram + +Howto setup TMDS570LS31HDK? + + o Unpack board. + o Verify that demo application runs. + o Upload bootloader specified above + o write BSP application either to sdram or intram and jump to RTEMS start code + +Additional information about the board can be found at + http://www.rtems.org/wiki/index.php/Tms570 + +Additional information about the CPU can be found at + http://www.ti.com/product/tms570ls3137 diff --git a/c/src/lib/libbsp/arm/tms570/bsp_specs b/c/src/lib/libbsp/arm/tms570/bsp_specs new file mode 100644 index 0000000..1afa2ba --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/bsp_specs @@ -0,0 +1,13 @@ +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -EB } + +*endfile: +%{!qrtems: *(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s } diff --git a/c/src/lib/libbsp/arm/tms570/clock/clock.c b/c/src/lib/libbsp/arm/tms570/clock/clock.c new file mode 100644 index 0000000..2a8bb5f --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/clock/clock.c @@ -0,0 +1,159 @@ +/** + * @file clock.c + * + * @ingroup tms570 + * + * @brief clock functions definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#include +#include +#include +#include + +/** + * holds HW counter value since last interrupt event + * sets in tms570_clock_driver_support_at_tick + * used in tms570_clock_driver_nanoseconds_since_last_tick + */ +static uint32_t tms570_rti_last_tick_fcr0; + +/** + * @brief Initialize the HW peripheral for clock driver + * + * Clock driver is implemented by RTI module + * + * @retval Void + */ +static void tms570_clock_driver_support_initialize_hardware( void ) +{ + + uint32_t microsec_per_tick = rtems_configuration_get_microseconds_per_tick(); + + /* Hardware specific initialize */ + TMS570_RTI.RTIGCTRL = 0; + TMS570_RTI.RTICPUC0 = BSP_PLL_OUT_CLOCK /1000000 / 2; /* prescaler */ + TMS570_RTI.RTITBCTRL = 2; + TMS570_RTI.RTICAPCTRL = 0; + TMS570_RTI.RTICOMPCTRL = 0; + /* set counter to zero */ + TMS570_RTI.RTIUC0 = 0; + TMS570_RTI.RTIFRC0 = 0; + /* clear interrupts*/ + TMS570_RTI.RTICLEARINTENA = 0x00070f0f; + TMS570_RTI.RTIINTFLAG = 0x0007000f; + /* set timer */ + TMS570_RTI.RTICOMP0 = TMS570_RTI.RTIFRC0 + microsec_per_tick; + TMS570_RTI.RTICOMP0CLR = TMS570_RTI.RTICOMP0 + microsec_per_tick / 2; + TMS570_RTI.RTIUDCP0 = microsec_per_tick; + /* enable interupt */ + TMS570_RTI.RTISETINTENA = 0x1; + /* enable timer */ + TMS570_RTI.RTIGCTRL = 1; +} + +/** + * @brief Clears interrupt source + * + * @retval Void + */ +static void tms570_clock_driver_support_at_tick( void ) +{ + TMS570_RTI.RTIINTFLAG = 0x00000001; + tms570_rti_last_tick_fcr0 = TMS570_RTI.RTICOMP0 - TMS570_RTI.RTIUDCP0; + /* TMS570_RTI.RTICOMP0 += 1000; */ +} + +/** + * @brief registers RTI interrupt handler + * + * @param[in] Clock_isr new ISR handler + * @param[in] Old_ticker old ISR handler (unused and type broken) + * + * @retval Void + */ +static void tms570_clock_driver_support_install_isr( + rtems_isr_entry Clock_isr +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + sc = rtems_interrupt_handler_install( + TMS570_IRQ_TIMER_0, + "Clock", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) Clock_isr, + NULL + ); + if ( sc != RTEMS_SUCCESSFUL ) { + rtems_fatal_error_occurred(0xdeadbeef); + } +} + +/** + * @brief disables RTI interrupt + * + * Called when closing clock driver + * + * @retval Void + */ +static void tms570_clock_driver_support_shutdown_hardware( void ) +{ + /* turn off the timer interrupts */ + TMS570_RTI.RTICLEARINTENA = 0x20000; +} + +/** + * @brief returns the nanoseconds since last tick + * + * Return the nanoseconds since last tick + * + * @retval x nanoseconds + * + */ +static uint32_t tms570_clock_driver_nanoseconds_since_last_tick( void ) +{ + uint32_t actual_fcr0 = TMS570_RTI.RTIFRC0; + uint32_t usec_since_tick; + + usec_since_tick = actual_fcr0 - tms570_rti_last_tick_fcr0; + + return usec_since_tick * 1000; +} + +#define Clock_driver_support_initialize_hardware \ + tms570_clock_driver_support_initialize_hardware +#define Clock_driver_support_at_tick \ + tms570_clock_driver_support_at_tick +#define Clock_driver_support_initialize_hardware \ + tms570_clock_driver_support_initialize_hardware +#define Clock_driver_support_shutdown_hardware \ + tms570_clock_driver_support_shutdown_hardware +#define Clock_driver_nanoseconds_since_last_tick \ + tms570_clock_driver_nanoseconds_since_last_tick + +#define Clock_driver_support_install_isr(Clock_isr, Old_ticker ) \ + tms570_clock_driver_support_install_isr( Clock_isr ) + +void Clock_isr(void *arg); /* to supress warning */ + +#include "../../../shared/clockdrv_shell.h" diff --git a/c/src/lib/libbsp/arm/tms570/configure.ac b/c/src/lib/libbsp/arm/tms570/configure.ac new file mode 100644 index 0000000..10a2920 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/configure.ac @@ -0,0 +1,52 @@ +## +# +# @file configure.ac +# +# @brief Configure script of LibBSP for the TMS570 board. +# + +AC_PREREQ([2.69]) +AC_INIT([rtems-c-src-lib-libbsp-arm-tms570],[_RTEMS_VERSION], + [http://www.rtems.org/bugzilla]) +AC_CONFIG_SRCDIR([bsp_specs]) +RTEMS_TOP(../../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) +RTEMS_BSP_CONFIGURE + +RTEMS_PROG_CC_FOR_TARGET +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +RTEMS_CHECK_NETWORKING +AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "no") + +RTEMS_BSPOPTS_SET([TMS570_SCI_BAUD_RATE],[*],[115200U]) +RTEMS_BSPOPTS_HELP([TMS570_SCI_BAUD_RATE],[baud for UARTs]) + +RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[1]) +RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS], +[The tms570 console driver can operate in either polled or interrupt mode.]) + +RTEMS_BSPOPTS_SET([ARM_TMS570LS3137],[*],[0]) +RTEMS_BSPOPTS_HELP([ARM_TMS570LS3137],[target used for identify TMS570LS3137 board]) + +RTEMS_BSPOPTS_SET([BSP_MINIMUM_TASK_STACK_SIZE],[*],[1024]) +RTEMS_BSPOPTS_HELP([BSP_MINIMUM_TASK_STACK_SIZE],[Suggested minimum task stack + size in bytes]) + +RTEMS_BSPOPTS_SET([TMS570_OSCILLATOR_MAIN],[*],[12000000U]) +RTEMS_BSPOPTS_HELP([TMS570_OSCILLATOR_MAIN],[main oscillator frequency in Hz]) + +RTEMS_BSPOPTS_SET([TMS570_OSCILLATOR_RTC],[*],[32768U]) +RTEMS_BSPOPTS_HELP([TMS570_OSCILLATOR_RTC],[RTC oscillator frequency in Hz]) + +RTEMS_BSPOPTS_SET([TMS570_CCLK],[*],[96000000U]) +RTEMS_BSPOPTS_HELP([TMS570_CCLK],[CPU clock in Hz]) + +RTEMS_BSP_CLEANUP_OPTIONS(0, 1) +RTEMS_BSP_LINKCMDS + +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/arm/tms570/console/printk-support.c b/c/src/lib/libbsp/arm/tms570/console/printk-support.c new file mode 100644 index 0000000..241ca9b --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/console/printk-support.c @@ -0,0 +1,85 @@ +/** + * @file printk-support.c + * + * @ingroup tms570 + * + * @brief definitions of serial line for debugging. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include + + +/** + * @brief Puts chars into peripheral + * + * debug functions always use serial dev 0 peripheral + * + * @retval Void + */ +static void tms570_putc(char ch) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + while ( ( driver_context_table[0].regs->SCIFLR & 0x100 ) == 0) { + rtems_interrupt_flash(level); + } + driver_context_table[0].regs->SCITD = ch; + rtems_interrupt_enable(level); +} + +/** + * @brief debug console output + * + * debug functions always use serial dev 0 peripheral + * + * @retval Void + */ +static void tms570_uart_output(char c) +{ + if ( c == '\n' ) { + char r = '\r'; + tms570_putc(r); + } + tms570_putc(c); +} + +/** + * @brief debug console input + * + * debug functions always use serial dev 0 peripheral + * + * @retval x Read char + * @retval -1 No input character available + */ +static int tms570_uart_input( void ) +{ + if ( driver_context_table[0].regs->SCIFLR & (1<<9) ) { + return driver_context_table[0].regs->SCIRD; + } else { + return -1; + } +} + +BSP_output_char_function_type BSP_output_char = tms570_uart_output; +BSP_polling_getchar_function_type BSP_poll_char = tms570_uart_input; diff --git a/c/src/lib/libbsp/arm/tms570/console/tms570-sci.c b/c/src/lib/libbsp/arm/tms570/console/tms570-sci.c new file mode 100644 index 0000000..8aa3caf --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/console/tms570-sci.c @@ -0,0 +1,559 @@ +/** + * @file tms570-sci.c + * + * @ingroup tms570 + * + * @brief Serial communication interface (SCI) functions definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TMS570_SCI_BUFFER_SIZE 1 + +/** + * @brief Table including all serial drivers + * + * Definitions of all serial drivers + */ +const tms570_sci_context driver_context_table[] = { + { + .device_name = "/dev/console", + .regs = &TMS570_SCI, + .irq = TMS570_IRQ_SCI_LEVEL_0, + }, + { + .device_name = "/dev/ttyS1", + .regs = &TMS570_SCI2, + .irq = TMS570_IRQ_SCI2_LEVEL_0, + } +}; + +/** + * @brief Serial drivers init function + * + * Initialize all serial drivers specified in driver_context_table + * + * @param[in] major + * @param[in] minor + * @param[in] arg + * @retval RTEMS_SUCCESSFUL Initialization completed + */ +rtems_device_driver console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code sc; +#if CONSOLE_USE_INTERRUPTS + const rtems_termios_device_handler *handler = &tms570_sci_handler_interrupt; +#else + const rtems_termios_device_handler *handler = &tms570_sci_handler_polled; +#endif + + /* + * Initialize the Termios infrastructure. If Termios has already + * been initialized by another device driver, then this call will + * have no effect. + */ + rtems_termios_initialize(); + + /* Initialize each device */ + for ( + minor = 0; + minor < RTEMS_ARRAY_SIZE(driver_context_table); + ++minor + ) { + const tms570_sci_context *ctx = &driver_context_table[minor]; + + /* + * Install this device in the file system and Termios. In order + * to use the console (i.e. being able to do printf, scanf etc. + * on stdin, stdout and stderr), one device must be registered as + * "/dev/console" (CONSOLE_DEVICE_NAME). + */ + sc = rtems_termios_device_install( + ctx->device_name, + major, + minor, + handler, + (void *) ctx + ); + if ( sc != RTEMS_SUCCESSFUL ) { + bsp_fatal(BSP_FATAL_CONSOLE_NO_DEV); + } + } + return RTEMS_SUCCESSFUL; +} + +/** + * @brief Reads chars from HW + * + * Reads chars from HW peripheral specified in driver context. + * TMS570 does not have HW buffer for serial line so this function can + * return only 0 or 1 char + * + * @param[in] ctx context of the driver + * @param[out] buf read data buffer + * @param[in] N size of buffer + * @retval x Number of read chars from peripherals + */ +static int tms570_sci_read_received_chars( + tms570_sci_context * ctx, + char * buf, + int N) +{ + if ( N < 1 ) { + return 0; + } + if ( ctx->regs->SCIRD != 0 ) { + buf[0] = ctx->regs->SCIRD; + return 1; + } + return 0; +} + +/** + * @brief Enables RX interrupt + * + * Enables RX interrupt source of SCI peripheral + * specified in the driver context. + * + * @param[in] ctx context of the driver + * @retval Void + */ +static void tms570_sci_enable_interrupts(tms570_sci_context * ctx) +{ + ctx->regs->SCISETINT = (1<<9); +} + +/** + * @brief Disables RX interrupt + * + * Disables RX interrupt source of SCI peripheral specified in the driver + * context. + * + * @param[in] ctx context of the driver + * @retval Void + */ +static void tms570_sci_disable_interrupts(tms570_sci_context * ctx) +{ + ctx->regs->SCICLEARINT = (1<<9); +} + +/** + * @brief Check whether driver has put char in HW + * + * Check whether driver has put char in HW. + * This information is read from the driver context not from a peripheral. + * TMS570 does not have write data buffer asociated with SCI + * so the return can be only 0 or 1. + * + * @param[in] ctx context of the driver + * @retval x + */ +static int tms570_sci_transmitted_chars(tms570_sci_context * ctx) +{ + int ret; + + ret = ctx->tx_chars_in_hw; + if ( ret == 1 ) { + ctx->tx_chars_in_hw = 0; + return 1; + } + return ret; +} + +/** + * @brief Set attributes of the HW peripheral + * + * Sets attributes of the HW peripheral (parity, baud rate, etc.) + * + * @param[in] tty rtems_termios_tty + * @param[in] t termios driver + * @retval true peripheral setting is changed + */ +static bool tms570_sci_set_attributes( + rtems_termios_tty *tty, + const struct termios *t +) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + rtems_interrupt_lock_context lock_context; + int32_t bauddiv; + int32_t baudrate; + + rtems_termios_interrupt_lock_acquire(tty, &lock_context); + + ctx->regs->SCIGCR1 &= ~( (1<<7) | (1<<25) | (1<<24) ); + + ctx->regs->SCIGCR1 &= ~(1<<4); /*one stop bit*/ + ctx->regs->SCIFORMAT = 0x7; + + switch ( t->c_cflag & ( PARENB|PARODD ) ) { + case ( PARENB|PARODD ): + /* Odd parity */ + ctx->regs->SCIGCR1 &= ~(1<<3); + ctx->regs->SCIGCR1 |= (1<<2); + break; + + case PARENB: + /* Even parity */ + ctx->regs->SCIGCR1 |= (1<<3); + ctx->regs->SCIGCR1 |= (1<<2); + break; + + default: + case 0: + case PARODD: + /* No Parity */ + ctx->regs->SCIGCR1 &= ~(1<<2); + } + + /* Baud rate */ + baudrate = rtems_termios_baud_to_number(cfgetospeed(t)); + baudrate *= 2 * 16; + bauddiv = (BSP_PLL_OUT_CLOCK + baudrate / 2) / baudrate; + ctx->regs->BRS = bauddiv; + + ctx->regs->SCIGCR1 |= (1<<7) | (1<<25) | (1<<24); + + rtems_termios_interrupt_lock_release(tty, &lock_context); + + return true; +} + +/** + * @brief sci interrupt handler + * + * Handler checks which interrupt occured and provides nessesary maintenance + * dequeue characters in termios driver whether character is send succesfully + * enqueue characters in termios driver whether character is recieved + * + * @param[in] arg rtems_termios_tty + * @retval Void + */ +static void tms570_sci_interrupt_handler(void * arg) +{ + rtems_termios_tty *tty = arg; + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + char buf[TMS570_SCI_BUFFER_SIZE]; + size_t n; + + /* + * Check if we have received something. + */ + if ( (ctx->regs->SCIFLR & (1<<9) ) == (1<<9) ) { + n = tms570_sci_read_received_chars(ctx, buf, TMS570_SCI_BUFFER_SIZE); + if ( n > 0 ) { + /* Hand the data over to the Termios infrastructure */ + rtems_termios_enqueue_raw_characters(tty, buf, n); + } + } + /* + * Check if we have something transmitted. + */ + if ( (ctx->regs->SCIFLR & (1<<8) ) == (1<<8) ) { + n = tms570_sci_transmitted_chars(ctx); + if ( n > 0 ) { + /* + * Notify Termios that we have transmitted some characters. It + * will call now the interrupt write function if more characters + * are ready for transmission. + */ + rtems_termios_dequeue_characters(tty, n); + } + } +} + +/** + * @brief sci write function called from interrupt + * + * Nonblocking write function. Writes characters to HW peripheral + * TMS570 does not have write data buffer asociated with SCI + * so only one character can be written. + * + * @param[in] tty rtems_termios_tty + * @param[in] buf buffer of characters pending to send + * @param[in] len size of the buffer + * @retval Void + */ +static void tms570_sci_interrupt_write( + rtems_termios_tty *tty, + const char *buf, + size_t len +) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + + if ( len > 0 ) { + /* start UART TX, this will result in an interrupt when done */ + ctx->regs->SCITD = *buf; + /* character written - raise count*/ + ctx->tx_chars_in_hw = 1; + /* Enable TX interrupt (interrupt is edge-triggered) */ + ctx->regs->SCISETINT = (1<<8); + + } else { + /* No more to send, disable TX interrupts */ + ctx->regs->SCICLEARINT = (1<<8); + /* Tell close that we sent everything */ + } +} + +/** + * @brief sci write function + * + * Blocking write function. Waits until HW peripheral is ready and then writes + * character to HW peripheral. Writes all characters in the buffer. + * + * @param[in] tty rtems_termios_tty + * @param[in] buf buffer of characters pending to send + * @param[in] len size of the buffer + * @retval Void + */ +static void tms570_sci_poll_write( + rtems_termios_tty *tty, + const char *buf, + size_t n +) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + size_t i; + + /* Write */ + + for ( i = 0; i < n; ++i ) { + while ( (ctx->regs->SCIFLR & (1<<11) ) == 0) { + ; + } + ctx->regs->SCITD = buf[i]; + } +} + +/** + * @brief See if there is recieved charakter to read + * + * read the RX flag from peripheral specified in context + * + * @param[in] ctx context of the driver + * @retval 0 No character to read + * @retval x Character ready to read + */ +static int TMS570_sci_can_read_char( + tms570_sci_context * ctx +) +{ + return ctx->regs->SCIFLR & (1<<9); +} + +/** + * @brief reads character from peripheral + * + * reads the recieved character from peripheral specified in context + * + * @param[in] ctx context of the driver + * @retval x Character + */ +static char TMS570_sci_read_char( + tms570_sci_context * ctx +) +{ + return ctx->regs->SCIRD; +} + +/** + * @brief sci read function + * + * check if there is recieved character to be read and reads it. + * + * @param[in] tty rtems_termios_tty (context of the driver) + * @retval -1 No character to be read + * @retval x Read character + */ +static int tms570_sci_poll_read(rtems_termios_tty *tty) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + + /* Check if a character is available */ + if ( TMS570_sci_can_read_char(ctx) ) { + return TMS570_sci_read_char(ctx); + } else { + return -1; + } +} + +/** + * @brief initialization of the driver + * + * initialization of the HW peripheral specified in contex of the driver. + * This function is called only once when opening the driver. + * + * @param[in] tty context of the driver + * @param[in] args + * @retval false Error occured during initialization + * @retval true Driver is open and ready + */ +static bool tms570_sci_poll_first_open( + rtems_termios_tty *tty, + rtems_libio_open_close_args_t *args +) +{ + bool ok; + + rtems_termios_set_best_baud(tty, TMS570_SCI_BAUD_RATE); + ok = tms570_sci_set_attributes(tty, rtems_termios_get_termios(tty)); + if ( !ok ) { + return false; + } + return true; +} + +/** + * @brief initialization of the interrupt driven driver + * + * calls tms570_sci_poll_first_open function. + * install and enables interrupts. + * + * @param[in] tty context of the driver + * @param[in] args + * @retval false Error occured during initialization + * @retval true Driver is open and ready + */ +static bool tms570_sci_interrupt_first_open( + rtems_termios_tty *tty, + rtems_libio_open_close_args_t *args +) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + rtems_status_code sc; + bool ret; + + ret = tms570_sci_poll_first_open(tty,args); + if ( ret == false ) { + return false; + } + ctx->regs->SCISETINTLVL = 0; + /* Register Interrupt handler */ + sc = rtems_interrupt_handler_install(ctx->irq, + ctx->device_name, + RTEMS_INTERRUPT_SHARED, + tms570_sci_interrupt_handler, + tty + ); + if ( sc != RTEMS_SUCCESSFUL ) { + return false; + } + tms570_sci_enable_interrupts(rtems_termios_get_device_context(tty)); + return true; +} + +/** + * @brief closes sci peripheral + * + * @param[in] tty context of the driver + * @param[in] args + * @retval false Error occured during initialization + * @retval true Driver is open and ready + */ +static void tms570_sci_poll_last_close( + rtems_termios_tty *tty, + rtems_libio_open_close_args_t *args +) +{ + ; +} + +/** + * @brief closes sci peripheral of interrupt driven driver + * + * calls tms570_sci_poll_last_close and disables interrupts + * + * @param[in] tty context of the driver + * @param[in] args + * @retval false Error occured during initialization + * @retval true Driver is open and ready + */ +static void tms570_sci_interrupt_last_close( + rtems_termios_tty *tty, + rtems_libio_open_close_args_t *args +) +{ + tms570_sci_context *ctx = rtems_termios_get_device_context(tty); + rtems_interrupt_lock_context lock_context; + + /* Turn off RX interrupts */ + rtems_termios_interrupt_lock_acquire(tty, &lock_context); + tms570_sci_disable_interrupts(ctx); + rtems_termios_interrupt_lock_release(tty, &lock_context); + + /* Flush device */ + while ( ( ctx->regs->SCIFLR & (1<<11) ) > 0 ) { + ;/* Wait until all data has been sent */ + } + + /* uninstall ISR */ + rtems_interrupt_handler_remove(ctx->irq, tms570_sci_interrupt_handler, tty); + + tms570_sci_poll_last_close(tty,args); +} + +/** + * @brief Struct containing definitions of polled driver functions. + * + * Encapsulates polled driver functions. + * Use of this table is determited by not defining TMS570_USE_INTERRUPTS + */ +const rtems_termios_device_handler tms570_sci_handler_polled = { + .first_open = tms570_sci_poll_first_open, + .last_close = tms570_sci_poll_last_close, + .poll_read = tms570_sci_poll_read, + .write = tms570_sci_poll_write, + .set_attributes = tms570_sci_set_attributes, + .stop_remote_tx = NULL, + .start_remote_tx = NULL, + .mode = TERMIOS_POLLED +}; + +/** + * @brief Struct containing definitions of interrupt driven driver functions. + * + * Encapsulates interrupt driven driver functions. + * Use of this table is determited by defining TMS570_USE_INTERRUPTS + */ +const rtems_termios_device_handler tms570_sci_handler_interrupt = { + .first_open = tms570_sci_interrupt_first_open, + .last_close = tms570_sci_interrupt_last_close, + .poll_read = NULL, + .write = tms570_sci_interrupt_write, + .set_attributes = tms570_sci_set_attributes, + .stop_remote_tx = NULL, + .start_remote_tx = NULL, + .mode = TERMIOS_IRQ_DRIVEN +}; diff --git a/c/src/lib/libbsp/arm/tms570/include/bsp.h b/c/src/lib/libbsp/arm/tms570/include/bsp.h new file mode 100644 index 0000000..81bc4cd --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/bsp.h @@ -0,0 +1,59 @@ +/** + * @file bsp.h + * + * @ingroup tms570 + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_BSP_H +#define LIBBSP_ARM_TMS570_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include +#include +#include +#include + +#define BSP_OSCILATOR_CLOCK 8000000 +#define BSP_PLL_OUT_CLOCK 160000000 + +/** Define operation count for Tests */ +#define OPERATION_COUNT 4 + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct rtems_bsdnet_ifconfig; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_TMS570_BSP_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/irq.h b/c/src/lib/libbsp/arm/tms570/include/irq.h new file mode 100644 index 0000000..f35e7fe --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/irq.h @@ -0,0 +1,156 @@ +/** + * @file irq.h + * + * @ingroup tms570 + * + * @brief TMS570 interrupt definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_IRQ_H +#define LIBBSP_ARM_TMS570_IRQ_H + +#ifndef ASM +#include +#include +#include +#endif + +#define BSP_INTERRUPT_VECTOR_MIN 0U +#define TMS570_IRQ_ESM_HIGH 0 +#define TMS570_IRQ_RESERVED 1 +#define TMS570_IRQ_TIMER_0 2 +#define TMS570_IRQ_TIMER_1 3 +#define TMS570_IRQ_TIMER_2 4 +#define TMS570_IRQ_TIMER_3 5 +#define TMS570_IRQ_RTI_OVERFLOW_0 6 +#define TMS570_IRQ_RTI_OVERFLOW_1 7 +#define TMS570_IRQ_RTI_TIMEBASE 8 +#define TMS570_IRQ_GIO_HIGH 9 +#define TMS570_IRQ_HET_HIGH 10 +#define TMS570_IRQ_HET_TU_HIGH 11 +#define TMS570_IRQ_MIBSPI1_HIGH 12 +#define TMS570_IRQ_SCI_LEVEL_0 13 +#define TMS570_IRQ_ADC1_EVENT 14 +#define TMS570_IRQ_ADC1_GROUP_1 15 +#define TMS570_IRQ_CAN1_HIGH 16 +#define TMS570_IRQ_RESERVED 17 +#define TMS570_IRQ_FLEXRAY_HIGH 18 +#define TMS570_IRQ_CRC_1 19 +#define TMS570_IRQ_ESM_LOW 20 +#define TMS570_IRQ_SSI 21 +#define TMS570_IRQ_PMU 22 +#define TMS570_IRQ_GIO_LOW 23 +#define TMS570_IRQ_HET_LOW 24 +#define TMS570_IRQ_HET_TU_LOW 25 +#define TMS570_IRQ_MIBSPI1_LOW 26 +#define TMS570_IRQ_SCI_LEVEL_1 27 +#define TMS570_IRQ_ADC1_GROUP_2 28 +#define TMS570_IRQ_CAN1_LOW 29 +#define TMS570_IRQ_RESERVED +#define TMS570_IRQ_ADC1_MAG 31 +#define TMS570_IRQ_FLEXRAY_LOW 32 +#define TMS570_IRQ_DMA_FTCA 33 +#define TMS570_IRQ_DMA_LFSA 34 +#define TMS570_IRQ_CAN2_HIGH 35 +#define TMS570_IRQ_DMM_HIGH 36 +#define TMS570_IRQ_MIBSPI3_HIGH 37 +#define TMS570_IRQ_MIBSPI3_LOW 38 +#define TMS570_IRQ_DMA_HBCA 39 +#define TMS570_IRQ_DMA_BTCA 40 +#define TMS570_IRQ_DMA_BERA 41 +#define TMS570_IRQ_CAN2_LOW 42 +#define TMS570_IRQ_DMM_LOW 43 +#define TMS570_IRQ_CAN1_IF3 44 +#define TMS570_IRQ_CAN3_HIGH 45 +#define TMS570_IRQ_CAN2_IF3 46 +#define TMS570_IRQ_FPU 47 +#define TMS570_IRQ_FLEXRAY_TU 48 +#define TMS570_IRQ_SPI4_HIGH 49 +#define TMS570_IRQ_ADC2_EVENT 50 +#define TMS570_IRQ_ADC2_GROUP_1 51 +#define TMS570_IRQ_FLEXRAY_T0C 52 +#define TMS570_IRQ_MIBSPIP5_HIGH 53 +#define TMS570_IRQ_SPI4_LOW 54 +#define TMS570_IRQ_CAN3_LOW 55 +#define TMS570_IRQ_MIBSPIP5_LOW 56 +#define TMS570_IRQ_ADC2_GROUP_2 57 +#define TMS570_IRQ_FLEXRAY_TU_ERROR 58 +#define TMS570_IRQ_ADC2_MAG 59 +#define TMS570_IRQ_CAN3_IF3 60 +#define TMS570_IRQ_FSM_DONE 61 +#define TMS570_IRQ_FLEXRAY_T1C 62 +#define TMS570_IRQ_HET2_LEVEL_0 63 +#define TMS570_IRQ_SCI2_LEVEL_0 64 +#define TMS570_IRQ_HET_TU2_LEVEL_0 65 +#define TMS570_IRQ_IC2_INTERRUPT 66 +#define TMS570_IRQ_HET2_LEVEL_1 73 +#define TMS570_IRQ_SCI2_LEVEL_1 74 +#define TMS570_IRQ_HET_TU2_LEVEL_1 75 +#define TMS570_IRQ_HWA_INT_REQ_H 80 +#define TMS570_IRQ_HWA_INT_REQ_H 81 +#define TMS570_IRQ_DCC_DONE_INTERRUPT 82 +#define TMS570_IRQ_DCC2_DONE_INTERRUPT 83 +#define TMS570_IRQ_HWAG1_INT_REQ_L 88 +#define TMS570_IRQ_HWAG2_INT_REQ_L 89 +#define BSP_INTERRUPT_VECTOR_MAX 94 + +#define TMS570_IRQ_PRIORITY_VALUE_MIN 0U +#define TMS570_IRQ_PRIORITY_VALUE_MAX 0U + +#define TMS570_IRQ_PRIORITY_COUNT ( TMS570_IRQ_PRIORITY_VALUE_MAX + 1U ) +#define TMS570_IRQ_PRIORITY_HIGHEST TMS570_IRQ_PRIORITY_VALUE_MIN +#define TMS570_IRQ_PRIORITY_LOWEST TMS570_IRQ_PRIORITY_VALUE_MAX + +#ifndef ASM + +/** + * @brief Set priority of the interrupt vector. + * + * This function is here because of compability. It should set + * priority of the interrupt vector. + * @warning It does not set any priority at HW layer. It is nearly imposible to + * @warning set priority of the interrupt on TMS570 in a nice way. + * @param[in] vector vector of isr + * @param[in] priority new priority assigned to the vector + * @return Void + */ +void tms570_irq_set_priority( + rtems_vector_number vector, + unsigned priority +); + +/** + * @brief Gets priority of the interrupt vector. + * + * This function is here because of compability. It returns priority + * of the isr vector last set by tms570_irq_set_priority function. + * + * @warning It does not return any real priority of the HW layer. + * @param[in] vector vector of isr + * @retval 0 vector is invalid. + * @retval priority priority of the interrupt + */ +unsigned tms570_irq_get_priority( rtems_vector_number vector ); + +#endif /* ASM */ + +/** @} */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570-pom.h b/c/src/lib/libbsp/arm/tms570/include/tms570-pom.h new file mode 100644 index 0000000..a447711 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570-pom.h @@ -0,0 +1,101 @@ +/** + * @file tms570-pom.h + * @ingroup tms570 + * @brief Parameter Overlay Module (POM) header file + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_POM_H +#define LIBBSP_ARM_TMS570_POM_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define TMS570_POM_REGIONS 32 +#define TMS570_POM_GLBCTRL_ENABLE 0x000000a0a + +/* Specification of memory size used for field REGSIZE of tms570_pom_region_t */ +#define TMS570_POM_REGSIZE_DISABLED 0x0 +#define TMS570_POM_REGSIZE_64B 0x1 +#define TMS570_POM_REGSIZE_128B 0x2 +#define TMS570_POM_REGSIZE_256B 0x3 +#define TMS570_POM_REGSIZE_512B 0x4 +#define TMS570_POM_REGSIZE_1KB 0x5 +#define TMS570_POM_REGSIZE_2KB 0x6 +#define TMS570_POM_REGSIZE_4KB 0x7 +#define TMS570_POM_REGSIZE_8KB 0x8 +#define TMS570_POM_REGSIZE_16KB 0x9 +#define TMS570_POM_REGSIZE_32KB 0xa +#define TMS570_POM_REGSIZE_64KB 0xb +#define TMS570_POM_REGSIZE_128KB 0xc +#define TMS570_POM_REGSIZE_256KB 0xd + +#define TMS570_POM_REGADDRMASK ((1<<23)-1) + +typedef struct tms570_pom_region_t { + uint32_t PROGSTART; + uint32_t OVLSTART; + uint32_t REGSIZE; + uint32_t res0; +} tms570_pom_region_t; + +typedef struct tms570_pom_t { + uint32_t GLBCTRL; /* 000h Global Control Register */ + uint32_t REV; /* 004h Revision ID */ + uint32_t CLKCTRL; /* 008h Clock Gate Control Register */ + uint32_t FLG; /* 00Ch Status Register */ + uint32_t reserved1[0x1f0/4]; + tms570_pom_region_t REG[TMS570_POM_REGIONS]; /* 200h Program Regions */ + uint32_t reserved2[0xb00/4]; + uint32_t ITCTRL; /* F00h Integration Control Register */ + uint32_t reserved3[0x09c/4]; + uint32_t CLAIMSET; /* FA0h Claim Set Register */ + uint32_t CLAIMCLR; /* FA4h Claim Clear Register */ + uint32_t reserved4[0x008/4]; + uint32_t LOCKACCESS; /* FB0h Lock Access Register */ + uint32_t LOCKSTATUS; /* FB4h Lock Status Register */ + uint32_t AUTHSTATUS; /* FB8h Authentication Status Register */ + uint32_t reserved5[0x00c/4]; + uint32_t DEVID; /* FC8h Device ID Register */ + uint32_t DEVTYPE; /* FCCh Device Type Register */ + uint32_t PERIPHERALID4; /* FD0h Peripheral ID 4 Register */ + uint32_t PERIPHERALID5; /* FD4h Peripheral ID 5 Register */ + uint32_t PERIPHERALID6; /* FD8h Peripheral ID 6 Register */ + uint32_t PERIPHERALID7; /* FDCh Peripheral ID 7 Register */ + uint32_t PERIPHERALID0; /* FE0h Peripheral ID 0 Register */ + uint32_t PERIPHERALID1; /* FE4h Peripheral ID 1 Register */ + uint32_t PERIPHERALID2; /* FE8h Peripheral ID 2 Register */ + uint32_t PERIPHERALID3; /* FECh Peripheral ID 3 Register */ + uint32_t COMPONENTID0; /* FF0h Component ID 0 Register */ + uint32_t COMPONENTID1; /* FF4h Component ID 1 Register */ + uint32_t COMPONENTID2; /* FF8h Component ID 2 Register */ + uint32_t COMPONENTID3; /* FFCh Component ID 3 Register */ +} tms570_pom_t; + +#define TMS570_POM (*(volatile tms570_pom_t*)0xffa04000) + +int mem_dump(void *buf, unsigned long start, unsigned long len, int blen); +void tms570_pom_remap(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_POM_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570-rti.h b/c/src/lib/libbsp/arm/tms570/include/tms570-rti.h new file mode 100644 index 0000000..25c02e5 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570-rti.h @@ -0,0 +1,95 @@ +/** + * @file tms570-rti.h + * + * @ingroup tms570 + * + * @brief Real Time Interrupt module (RTI) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_RTI_H +#define LIBBSP_ARM_TMS570_RTI_H + +#ifndef ASM + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + uint32_t RTIGCTRL; /* RTIGlobalControlRegister */ + uint32_t RTITBCTRL; /* RTITimebaseControlRegister */ + uint32_t RTICAPCTRL; /* RTICaptureControlRegister */ + uint32_t RTICOMPCTRL; /* RTICompareControlRegister */ + uint32_t RTIFRC0; /* RTIFreeRunningCounter0Register */ + uint32_t RTIUC0; /* RTIUpCounter0Register */ + uint32_t RTICPUC0; /* RTICompareUpCounter0Register */ + uint32_t reserved1 [0x4/4]; + uint32_t RTICAFRC0; /* RTICaptureFreeRunningCounter0Register */ + uint32_t RTICAUC0; /* RTICaptureUpCounter0Register */ + uint32_t reserved2 [0x8/4]; + uint32_t RTIFRC1; /* RTIFreeRunningCounter1Register */ + uint32_t RTIUC1; /* RTIUpCounter1Register */ + uint32_t RTICPUC1; /* RTICompareUpCounter1Register */ + uint32_t reserved3 [0x4/4]; + uint32_t RTICAFRC1; /* RTICaptureFreeRunningCounter1Register */ + uint32_t RTICAUC1; /* RTICaptureUpCounter1Register */ + uint32_t reserved4 [0x8/4]; + uint32_t RTICOMP0; /* RTICompare0Register */ + uint32_t RTIUDCP0; /* RTIUpdateCompare0Register */ + uint32_t RTICOMP1; /* RTICompare1Register */ + uint32_t RTIUDCP1; /* RTIUpdateCompare1Register */ + uint32_t RTICOMP2; /* RTICompare2Register */ + uint32_t RTIUDCP2; /* RTIUpdateCompare2Register */ + uint32_t RTICOMP3; /* RTICompare3Register */ + uint32_t RTIUDCP3; /* RTIUpdateCompare3Register */ + uint32_t RTITBLCOMP; /* RTITimebaseLowCompareRegister */ + uint32_t RTITBHCOMP; /* RTITimebaseHighCompareRegister */ + uint32_t reserved5 [0x8/4]; + uint32_t RTISETINTENA; /* RTISetInterruptEnableRegister */ + uint32_t RTICLEARINTENA; /* RTIClearInterruptEnableRegister */ + uint32_t RTIINTFLAG; /* RTIInterruptFlagRegister */ + uint32_t reserved6 [0x4/4]; + uint32_t RTIDWDCTRL; /* DigitalWatchdogControlRegister */ + uint32_t RTIDWDPRLD; /* DigitalWatchdogPreloadRegister */ + uint32_t RTIWDSTATUS; /* WatchdogStatusRegister */ + uint32_t RTIWDKEY; /* RTIWatchdogKeyRegister */ + uint32_t RTIDWDCNTR; /* RTIDigitalWatchdogDownCounterRegister */ + uint32_t RTIWWDRXNCTRL; /* DigitalWindowedWatchdogReactionControlRegister */ + uint32_t RTIWWDSIZECTRL; /* DigitalWindowedWatchdogWindowSizeControlRegister */ + uint32_t RTIINTCLRENABLE;/* RTICompareInterruptClearEnableRegister */ + uint32_t RTICOMP0CLR; /* RTICompare0ClearRegister */ + uint32_t RTICOMP1CLR; /* RTICompare1ClearRegister */ + uint32_t RTICOMP2CLR; /* RTICompare2ClearRegister */ + uint32_t RTICOMP3CLR; /* RTICompare3ClearRegister */ +}tms570_rti_t; + +#define TMS570_RTI (*(volatile tms570_rti_t*)0xFFFFFC00) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570-sci-driver.h b/c/src/lib/libbsp/arm/tms570/include/tms570-sci-driver.h new file mode 100644 index 0000000..5f38908 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570-sci-driver.h @@ -0,0 +1,57 @@ +/** + * @file tms570-sci-driver.h + * + * @ingroup tms570 + * + * @brief Declaration of serial's driver inner structure. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef TMS570_SCI_DRIVER +#define TMS570_SCI_DRIVER + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Low-level driver specific data structure */ +typedef struct { + const char *device_name; + volatile tms570_sci_t *regs; + int tx_chars_in_hw; + rtems_vector_number irq; +} tms570_sci_context; + +extern const rtems_termios_device_handler tms570_sci_handler_polled; + +extern const rtems_termios_device_handler tms570_sci_handler_interrupt; + +extern const tms570_sci_context driver_context_table[]; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* TMS570_SCI_DRIVER */ diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570-sci.h b/c/src/lib/libbsp/arm/tms570/include/tms570-sci.h new file mode 100644 index 0000000..6ed68e2 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570-sci.h @@ -0,0 +1,76 @@ +/** + * @file tms570-sci.h + * + * @ingroup tms570 + * + * @brief Serial Communication Interface (SCI) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_SCI_H +#define LIBBSP_ARM_TMS570_SCI_H + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + uint32_t SCIGCR0; /*SCIGlobalControlRegister0*/ + uint32_t SCIGCR1; /*SCIGlobalControlRegister1*/ + uint32_t reserved1 [0x4/4]; + uint32_t SCISETINT; /*SCISetInterruptRegister*/ + uint32_t SCICLEARINT; /*SCIClearInterruptRegister*/ + uint32_t SCISETINTLVL; /*SCISetInterruptLevelRegister*/ + uint32_t SCICLEARINTLVL; /*SCIClearInterruptLevelRegister*/ + uint32_t SCIFLR; /*SCIFlagsRegister*/ + uint32_t SCIINTVECT0; /*SCIInterruptVectorOffset0*/ + uint32_t SCIINTVECT1; /*SCIInterruptVectorOffset1*/ + uint32_t SCIFORMAT; /*SCIFormatControlRegister*/ + uint32_t BRS; /*BaudRateSelectionRegister*/ + uint32_t SCIED; /*ReceiverEmulationDataBuffer*/ + uint32_t SCIRD; /*ReceiverDataBuffer*/ + uint32_t SCITD; /*TransmitDataBuffer*/ + uint32_t SCIPIO0; /*SCIPinI/OControlRegister0*/ + uint32_t SCIPIO1; /*SCIPinI/OControlRegister1*/ + uint32_t SCIPIO2; /*SCIPinI/OControlRegister2*/ + uint32_t SCIPIO3; /*SCIPinI/OControlRegister3*/ + uint32_t SCIPIO4; /*SCIPinI/OControlRegister4*/ + uint32_t SCIPIO5; /*SCIPinI/OControlRegister5*/ + uint32_t SCIPIO6; /*SCIPinI/OControlRegister6*/ + uint32_t SCIPIO7; /*SCIPinI/OControlRegister7*/ + uint32_t SCIPIO8; /*SCIPinI/OControlRegister8*/ + uint32_t reserved2 [0x30/4]; + uint32_t IODFTCTRL; /*Input/OutputErrorEnableRegister*/ +}tms570_sci_t; + +#define TMS570_SCI (*(volatile tms570_sci_t*)0xFFF7E400U) +#define TMS570_SCI2 (*(volatile tms570_sci_t*)0xFFF7E500U) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570-vim.h b/c/src/lib/libbsp/arm/tms570/include/tms570-vim.h new file mode 100644 index 0000000..136af53 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570-vim.h @@ -0,0 +1,75 @@ +/** + * @file tms570-vim.h + * + * @ingroup tms570 + * + * @brief Vectored Interrupt Module (VIM) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_VIM_H +#define LIBBSP_ARM_TMS570_VIM_H + +#ifndef ASM +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct{ + uint32_t PARFLG; /* InterruptVectorTableParityFlagRegister */ + uint32_t PARCTL; /* InterruptVectorTableParityControlRegister */ + uint32_t ADDERR; /* AddressParityErrorRegister */ + uint32_t FBPARERR; /* Fall-BackAddressParityErrorRegister */ + uint32_t reserved1 [0x4/4]; + uint32_t IRQINDEX; /* IRQIndexOffsetVectorRegister */ + uint32_t FIQINDEX; /* FIQIndexOffsetVectorRegister */ + uint32_t reserved2 [0x8/4]; + uint32_t FIRQPR[3]; /* FIQ/IRQProgramControlRegister0 */ + uint32_t reserved3 [0x4/4]; + uint32_t INTREQ[3]; /* PendingInterruptReadLocationRegister0 */ + uint32_t reserved4 [0x4/4]; + uint32_t REQENASET[3]; /* InterruptEnableSetRegister0 */ + uint32_t reserved5 [0x4/4]; + uint32_t REQENACLR[3]; /* InterruptEnableClearRegister0 */ + uint32_t reserved6 [0x4/4]; + uint32_t WAKEENASET[3]; /* Wake-upEnableSetRegister0 */ + uint32_t reserved7 [0x4/4]; + uint32_t WAKEENACLR[3]; /* Wake-upEnableClearRegister0 */ + uint32_t reserved8 [0x4/4]; + uint32_t IRQVECREG; /* IRQInterruptVectorRegister */ + uint32_t FIQVECREG; /* FIQInterruptVectorRegister */ + uint32_t CAPEVT; /* CaptureEventRegister */ + uint32_t reserved9 [0x4/4]; + uint32_t CHANCTRL [0x5c/4]; /* VIM Interrupt Control Register (PARSER ERROR) */ +}tms570_vim_t; + +#define TMS570_VIM (*(volatile tms570_vim_t*)0xFFFFFDEC) + +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570.h b/c/src/lib/libbsp/arm/tms570/include/tms570.h new file mode 100644 index 0000000..2023a29 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/tms570.h @@ -0,0 +1,28 @@ +/** + * @file tms570.h + * + * @ingroup tms570 + * + * @brief Specific register definitions according to tms570 family boards. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_H +#define LIBBSP_ARM_TMS570_H + +#endif /* LIBBSP_ARM_TMS570_H */ diff --git a/c/src/lib/libbsp/arm/tms570/irq/irq.c b/c/src/lib/libbsp/arm/tms570/irq/irq.c new file mode 100644 index 0000000..2e6e3db --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/irq/irq.c @@ -0,0 +1,207 @@ +/** + * @file irq.c + * + * @ingroup tms570 + * + * @brief TMS570 interrupt support functions definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include +#include + +/** + * @brief Check if isr vector is valid + * + * Check if isr vector is valid by using BSP_INTERRUPT_VECTOR_MAX and + * BSP_INTERRUPT_VECTOR_MIN defined in irq.h + * + * @param[in] vector interrupt vector to be checked. + * @retval TRUE vector is valid. + * @retval FALSE vector is invalid + */ +static inline bool tms570_irq_is_valid( + rtems_vector_number vector +) +{ + return (vector <= BSP_INTERRUPT_VECTOR_MAX) && + (vector > BSP_INTERRUPT_VECTOR_MIN); +} + +unsigned int priorityTable[BSP_INTERRUPT_VECTOR_MAX+1]; + +/** + * @brief Set priority of the interrupt vector. + * + * This function is here because of compability. It should set + * priority of the interrupt vector. + * @warning It does not set any priority at HW layer. It is nearly imposible to + * @warning set priority of the interrupt on TMS570 in a nice way. + * @param[in] vector vector of isr + * @param[in] priority new priority assigned to the vector + * @return Void + */ +void tms570_irq_set_priority( + rtems_vector_number vector, + unsigned priority +) +{ + if ( tms570_irq_is_valid(vector) ) { + priorityTable[vector] = priority; + } +} + +/** + * @brief Gets priority of the interrupt vector. + * + * This function is here because of compability. It returns priority + * of the isr vector last set by tms570_irq_set_priority function. + * + * @warning It does not return any real priority of the HW layer. + * @param[in] vector vector of isr + * @retval 0 vector is invalid. + * @retval priority priority of the interrupt + */ +unsigned tms570_irq_get_priority( + rtems_vector_number vector +) +{ + if ( tms570_irq_is_valid(vector) ) { + return priorityTable[vector]; + } + return 0; +} + +/** + * @brief Interrupt dispatch + * + * Called by OS to determine which interrupt occured. + * Function passes control to interrupt handler. + * + * @return Void + */ +void bsp_interrupt_dispatch(void) +{ + rtems_vector_number vector = TMS570_VIM.IRQINDEX-1; + + bsp_interrupt_handler_dispatch(vector); +} + +/** + * @brief enables interrupt vector in the HW + * + * Enables HW interrupt for specified vector + * + * @param[in] vector vector of the isr which needs to be enabled. + * @retval RTEMS_INVALID_ID vector is invalid. + * @retval RTEMS_SUCCESSFUL interrupt source enabled. + */ +rtems_status_code bsp_interrupt_vector_enable( + rtems_vector_number vector +) +{ + if( !tms570_irq_is_valid(vector) ) { + return RTEMS_INVALID_ID; + } + + TMS570_VIM.REQENASET[vector >> 5] = 1 << (vector & 0x1f); + + return RTEMS_SUCCESSFUL; +} + +/** + * @brief disables interrupt vector in the HW + * + * Disables HW interrupt for specified vector + * + * @param[in] vector vector of the isr which needs to be disabled. + * @retval RTEMS_INVALID_ID vector is invalid. + * @retval RTEMS_SUCCESSFUL interrupt source disabled. + */ +rtems_status_code bsp_interrupt_vector_disable( + rtems_vector_number vector +) +{ + if( !tms570_irq_is_valid(vector) ) { + return RTEMS_INVALID_ID; + } + + TMS570_VIM.REQENACLR[vector >> 5] = 1 << (vector & 0x1f); + + return RTEMS_SUCCESSFUL; +} + +/** + * @brief Init function of interrupt module + * + * Resets vectored interrupt interface to default state. + * Disables all interrupts. + * Set all sources as IRQ (not FIR). + * + * @retval RTEMS_SUCCESSFUL All is set + */ +rtems_status_code bsp_interrupt_facility_initialize(void) +{ + void (**vim_vec)(void) = (void (**)(void)) 0xFFF82000; + unsigned int value = 0x00010203; + unsigned int i = 0; + uint32_t sctlr; + + /* Disable interrupts */ + for ( i = 0; i < 3; i++ ) { + TMS570_VIM.REQENACLR[i] = 0xffffffff; + } + /* Map default events on interrupt vectors */ + for ( i = 0; i < 24; i += 1, value += 0x04040404) { + TMS570_VIM.CHANCTRL[i] = value; + } + /* Set all vectors as IRQ (not FIR) */ + TMS570_VIM.FIRQPR[0] = 3; + TMS570_VIM.FIRQPR[1] = 0; + TMS570_VIM.FIRQPR[2] = 0; + + /* + _CPU_ISR_install_vector( + ARM_EXCEPTION_IRQ, + _ARMV4_Exception_interrupt, + NULL + ); + + Call to setup of interrupt entry in CPU level exception vectors table + is not used (necessary/possible) because the table is provided + by c/src/lib/libbsp/arm/shared/start/start.S and POM overlay + solution remaps that to address zero. + */ + + for ( i = 0; i <= 94; ++i ) { + vim_vec[i] = _ARMV4_Exception_interrupt; + } + /* Clear bit VE in SCTLR register to not use VIM IRQ exception bypass*/ + asm volatile ("mrc p15, 0, %0, c1, c0, 0\n": "=r" (sctlr)); + /* + * Disable bypass of CPU level exception table for interrupt entry which + * can be provided by VIM hardware + */ + sctlr &= ~(1 << 24); + asm volatile ("mcr p15, 0, %0, c1, c0, 0\n": : "r" (sctlr)); + + return RTEMS_SUCCESSFUL; +} diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg new file mode 100644 index 0000000..6f722bc --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg @@ -0,0 +1,19 @@ +# +# tms570ls3137 mbed RTEMS Test Database. +# +# Format is one line per test that is _NOT_ built. +# + +flashdisk01 +utf8proc01 +spstkalloc02 +fsdosfsname01 +jffs2_fserror +jffs2_fslink +jffs2_fspatheval +jffs2_fspermission +jffs2_fsrdwr +jffs2_fssymlink +jffs2_fstime +pppd +mghttpd01 diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg new file mode 100644 index 0000000..eb4a65f --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg @@ -0,0 +1,20 @@ +# +# Config file for TMS570LS3137 board. +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = arm + +CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian + +CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +BINEXT?=.bin + +# This defines the operations performed on the linked executable. +# is currently required. +define bsp-post-link + $(OBJCOPY) -O binary --strip-all \ + $(basename $@)$(EXEEXT) $(basename $@)$(BINEXT) + $(SIZE) $(basename $@)$(EXEEXT) +endef diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg new file mode 100644 index 0000000..eb4a65f --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg @@ -0,0 +1,20 @@ +# +# Config file for TMS570LS3137 board. +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = arm + +CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian + +CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +BINEXT?=.bin + +# This defines the operations performed on the linked executable. +# is currently required. +define bsp-post-link + $(OBJCOPY) -O binary --strip-all \ + $(basename $@)$(EXEEXT) $(basename $@)$(BINEXT) + $(SIZE) $(basename $@)$(EXEEXT) +endef diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg new file mode 100644 index 0000000..eb4a65f --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg @@ -0,0 +1,20 @@ +# +# Config file for TMS570LS3137 board. +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = arm + +CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian + +CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +BINEXT?=.bin + +# This defines the operations performed on the linked executable. +# is currently required. +define bsp-post-link + $(OBJCOPY) -O binary --strip-all \ + $(basename $@)$(EXEEXT) $(basename $@)$(BINEXT) + $(SIZE) $(basename $@)$(EXEEXT) +endef diff --git a/c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c b/c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c new file mode 100644 index 0000000..6514368 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c @@ -0,0 +1,53 @@ +/** + * @file tms570-pom.c + * + * @ingroup tms570 + * + * @brief TMS570 Parameter Overlay Module functions definitions. + */ + + /* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include + +/** + * @brief remaps vector table + * + * transfer the rtems start vector table to address 0x0 + * + * @retval Void + */ +void tms570_pom_remap(void) +{ + int i; + uint32_t vec_overlay_start = 0x08000000; + + memcpy((void*)vec_overlay_start, bsp_start_vector_table_begin, 64); + + TMS570_POM.GLBCTRL = 0; + + for ( i = 0; i < TMS570_POM_REGIONS; ++i ) { + TMS570_POM.REG[i].REGSIZE = TMS570_POM_REGSIZE_DISABLED; + } + + TMS570_POM.REG[0].PROGSTART = 0x0 & TMS570_POM_REGADDRMASK; + TMS570_POM.REG[0].OVLSTART = vec_overlay_start & TMS570_POM_REGADDRMASK; + TMS570_POM.REG[0].REGSIZE = TMS570_POM_REGSIZE_64B; + + TMS570_POM.GLBCTRL = TMS570_POM_GLBCTRL_ENABLE | + (vec_overlay_start & ~TMS570_POM_REGADDRMASK); +} diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am b/c/src/lib/libbsp/arm/tms570/preinstall.am new file mode 100644 index 0000000..81dbad1 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/preinstall.am @@ -0,0 +1,123 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES = $(TMPINSTALL_FILES) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) + +$(PROJECT_LIB)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_LIB) + @: > $(PROJECT_LIB)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) + +$(PROJECT_INCLUDE)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE) + @: > $(PROJECT_INCLUDE)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) + +$(PROJECT_INCLUDE)/bsp/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp + @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) + +$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs +PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs + +$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h + +$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h + +$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h + +$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h + +$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h + +$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h + +$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h + +$(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h + +$(PROJECT_INCLUDE)/bsp/uart-output-char.h: ../../shared/include/uart-output-char.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart-output-char.h + +$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h + +$(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h + +$(PROJECT_INCLUDE)/bsp/tms570.h: include/tms570.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570.h + +$(PROJECT_INCLUDE)/bsp/tms570-sci.h: include/tms570-sci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-sci.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-sci.h + +$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h + +$(PROJECT_INCLUDE)/bsp/tms570-rti.h: include/tms570-rti.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-rti.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-rti.h + +$(PROJECT_INCLUDE)/bsp/tms570-vim.h: include/tms570-vim.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-vim.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-vim.h + +$(PROJECT_INCLUDE)/bsp/tms570-pom.h: include/tms570-pom.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-pom.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-pom.h + +$(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h: include/tms570-sci-driver.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h + +$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h + +$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) +TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) + +$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds + diff --git a/c/src/lib/libbsp/arm/tms570/startup/bspreset.c b/c/src/lib/libbsp/arm/tms570/startup/bspreset.c new file mode 100644 index 0000000..d47920c --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/bspreset.c @@ -0,0 +1,36 @@ +/** + * @file bspreset.c + * + * @ingroup tms570 + * + * @brief Reset code. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#include +#include +#include + +BSP_START_TEXT_SECTION __attribute__( ( flatten ) ) void bsp_reset( void ) +{ + while ( true ) { + /* Do nothing */ + } +} diff --git a/c/src/lib/libbsp/arm/tms570/startup/bspstart.c b/c/src/lib/libbsp/arm/tms570/startup/bspstart.c new file mode 100644 index 0000000..31ad1e7 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/bspstart.c @@ -0,0 +1,41 @@ +/** + * @file bspstart.c + * + * @ingroup tms570 + * + * @brief Startup code. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include +#include + +void bsp_start( void ) +{ + /* set the cpu mode to supervisor and big endian */ + arm_cpu_mode = 0x213; + + tms570_pom_remap(); + + /* Interrupts */ + bsp_interrupt_initialize(); + +} diff --git a/c/src/lib/libbsp/arm/tms570/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/tms570/startup/bspstarthooks.c new file mode 100644 index 0000000..a9e189b --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/bspstarthooks.c @@ -0,0 +1,41 @@ +/** + * @file bspstarthooks.c + * + * @ingroup tms570 + * + * @brief First configurations and initializations to the correct + * functionality of the board. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include + +BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) +{ + ; +} + +BSP_START_TEXT_SECTION void bsp_start_hook_1( void ) +{ + bsp_start_copy_sections(); + bsp_start_clear_bss(); + + /* At this point we can use objects outside the .start section */ +} diff --git a/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk new file mode 100644 index 0000000..e02dcd6 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk @@ -0,0 +1,27 @@ + +MEMORY { + ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M + RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 256k + RAM_EXT (AIWX) : ORIGIN = 0x80000000, LENGTH = 8M +} + +REGION_ALIAS ("REGION_START", ROM_INT); +REGION_ALIAS ("REGION_VECTOR", RAM_INT); +REGION_ALIAS ("REGION_TEXT", ROM_INT); +REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT); +REGION_ALIAS ("REGION_RODATA", ROM_INT); +REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_DATA", RAM_INT); +REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_INT); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT); +REGION_ALIAS ("REGION_BSS", RAM_INT); +REGION_ALIAS ("REGION_WORK", RAM_INT); +REGION_ALIAS ("REGION_STACK", RAM_INT); + +bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 1024; +bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align); + +INCLUDE linkcmds.armv4 diff --git a/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_intram b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_intram new file mode 100644 index 0000000..19bb7b2 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_intram @@ -0,0 +1,28 @@ + +MEMORY { + ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M + RAM_INT_VEC : ORIGIN = 0x08000000, LENGTH = 1k + RAM_INT (AIWX) : ORIGIN = 0x08000400, LENGTH = 256k - 1k + RAM_EXT (AIW) : ORIGIN = 0x80000000, LENGTH = 8M +} + +REGION_ALIAS ("REGION_START", RAM_INT); +REGION_ALIAS ("REGION_VECTOR", RAM_INT); +REGION_ALIAS ("REGION_TEXT", RAM_INT); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM_INT); +REGION_ALIAS ("REGION_RODATA", RAM_INT); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM_INT); +REGION_ALIAS ("REGION_DATA", RAM_INT); +REGION_ALIAS ("REGION_DATA_LOAD", RAM_INT); +REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_INT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_INT); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_INT); +REGION_ALIAS ("REGION_BSS", RAM_INT); +REGION_ALIAS ("REGION_WORK", RAM_INT); +REGION_ALIAS ("REGION_STACK", RAM_INT); + +bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 1024; +bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align); + +INCLUDE linkcmds.armv4 diff --git a/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_sdram b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_sdram new file mode 100644 index 0000000..110179f --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_sdram @@ -0,0 +1,27 @@ + +MEMORY { + ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M + RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 256k + RAM_EXT (AIWX) : ORIGIN = 0x80000000, LENGTH = 8M +} + +REGION_ALIAS ("REGION_START", RAM_EXT); +REGION_ALIAS ("REGION_VECTOR", RAM_EXT); +REGION_ALIAS ("REGION_TEXT", RAM_EXT); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_RODATA", RAM_EXT); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_DATA", RAM_EXT); +REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_FAST_TEXT", RAM_EXT); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_EXT); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_BSS", RAM_EXT); +REGION_ALIAS ("REGION_WORK", RAM_EXT); +REGION_ALIAS ("REGION_STACK", RAM_EXT); + +bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 1024; +bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align); + +INCLUDE linkcmds.armv4 From joel at rtems.org Wed Aug 20 19:44:36 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 20 Aug 2014 14:44:36 -0500 Subject: [rtems commit] libbsp/arm/acinclude.m4: Regenerate for tms570 Message-ID: <20140820194436.789BB700650@git.rtems.org> Module: rtems Branch: master Commit: 2ed97d94dad5a4370584090853b3d4bc6326ba2c Changeset: http://git.rtems.org/rtems/commit/?id=2ed97d94dad5a4370584090853b3d4bc6326ba2c Author: Joel Sherrill Date: Wed Aug 20 14:53:18 2014 -0500 libbsp/arm/acinclude.m4: Regenerate for tms570 --- c/src/lib/libbsp/arm/acinclude.m4 | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/arm/acinclude.m4 b/c/src/lib/libbsp/arm/acinclude.m4 index 9192267..91c0fff 100644 --- a/c/src/lib/libbsp/arm/acinclude.m4 +++ b/c/src/lib/libbsp/arm/acinclude.m4 @@ -38,6 +38,8 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR], AC_CONFIG_SUBDIRS([smdk2410]);; stm32f4 ) AC_CONFIG_SUBDIRS([stm32f4]);; + tms570 ) + AC_CONFIG_SUBDIRS([tms570]);; xilinx-zynq ) AC_CONFIG_SUBDIRS([xilinx-zynq]);; *) From joel at rtems.org Wed Aug 20 19:44:36 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 20 Aug 2014 14:44:36 -0500 Subject: [rtems commit] Add new (first) OpenRISC BSP called or1ksim. Message-ID: <20140820194436.677E97006E4@git.rtems.org> Module: rtems Branch: master Commit: fd5701587f7961259253e66e4dd8fa8c44e8ee91 Changeset: http://git.rtems.org/rtems/commit/?id=fd5701587f7961259253e66e4dd8fa8c44e8ee91 Author: Hesham ALMatary Date: Wed Aug 20 12:23:20 2014 -0500 Add new (first) OpenRISC BSP called or1ksim. This BSP is intended to run on or1ksim (the main OpenRISC emulator). Fixed version according to Joel comments from the mailing list. --- c/src/aclocal/rtems-cpu-subdirs.m4 | 1 + c/src/lib/libbsp/or1k/Makefile.am | 10 + c/src/lib/libbsp/or1k/acinclude.m4 | 10 + c/src/lib/libbsp/or1k/configure.ac | 19 ++ c/src/lib/libbsp/or1k/or1ksim/Makefile.am | 109 +++++++ c/src/lib/libbsp/or1k/or1ksim/README | 17 + c/src/lib/libbsp/or1k/or1ksim/bsp_specs | 11 + c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c | 104 +++++++ c/src/lib/libbsp/or1k/or1ksim/configure.ac | 30 ++ .../libbsp/or1k/or1ksim/console/console-config.c | 58 ++++ c/src/lib/libbsp/or1k/or1ksim/console/uart.c | 144 +++++++++ c/src/lib/libbsp/or1k/or1ksim/include/bsp.h | 47 +++ c/src/lib/libbsp/or1k/or1ksim/include/irq.h | 45 +++ c/src/lib/libbsp/or1k/or1ksim/include/or1ksim.h | 118 ++++++++ c/src/lib/libbsp/or1k/or1ksim/include/uart.h | 42 +++ c/src/lib/libbsp/or1k/or1ksim/irq/irq.c | 42 +++ .../or1k/or1ksim/make/custom/or1k_or1ksim.cfg | 7 + c/src/lib/libbsp/or1k/or1ksim/preinstall.am | 114 +++++++ c/src/lib/libbsp/or1k/or1ksim/start/start.S | 182 ++++++++++++ c/src/lib/libbsp/or1k/or1ksim/startup/linkcmds | 41 +++ c/src/lib/libbsp/or1k/or1ksim/timer/timer.c | 64 ++++ c/src/lib/libbsp/or1k/preinstall.am | 6 + .../libbsp/or1k/shared/include/linker-symbols.h | 79 +++++ c/src/lib/libbsp/or1k/shared/startup/linkcmds.base | 310 ++++++++++++++++++++ 24 files changed, 1610 insertions(+), 0 deletions(-) diff --git a/c/src/aclocal/rtems-cpu-subdirs.m4 b/c/src/aclocal/rtems-cpu-subdirs.m4 index c5a4a19..9593d34 100644 --- a/c/src/aclocal/rtems-cpu-subdirs.m4 +++ b/c/src/aclocal/rtems-cpu-subdirs.m4 @@ -23,6 +23,7 @@ _RTEMS_CPU_SUBDIR([mips],[$1]);; _RTEMS_CPU_SUBDIR([moxie],[$1]);; _RTEMS_CPU_SUBDIR([nios2],[$1]);; _RTEMS_CPU_SUBDIR([no_cpu],[$1]);; +_RTEMS_CPU_SUBDIR([or1k],[$1]);; _RTEMS_CPU_SUBDIR([powerpc],[$1]);; _RTEMS_CPU_SUBDIR([sh],[$1]);; _RTEMS_CPU_SUBDIR([sparc],[$1]);; diff --git a/c/src/lib/libbsp/or1k/Makefile.am b/c/src/lib/libbsp/or1k/Makefile.am new file mode 100644 index 0000000..0ce20e6 --- /dev/null +++ b/c/src/lib/libbsp/or1k/Makefile.am @@ -0,0 +1,10 @@ +ACLOCAL_AMFLAGS = -I ../../../aclocal + +## Descend into the @RTEMS_BSP_FAMILY@ directory +## Currently, the shared directory is not explicitly +## added but it is present in the source tree. +SUBDIRS = @RTEMS_BSP_FAMILY@ + +include $(srcdir)/preinstall.am +include $(top_srcdir)/../../../automake/subdirs.am +include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libbsp/or1k/acinclude.m4 b/c/src/lib/libbsp/or1k/acinclude.m4 new file mode 100644 index 0000000..c593670 --- /dev/null +++ b/c/src/lib/libbsp/or1k/acinclude.m4 @@ -0,0 +1,10 @@ +# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY) +AC_DEFUN([RTEMS_CHECK_BSPDIR], +[ + case "$1" in + or1ksim ) + AC_CONFIG_SUBDIRS([or1ksim]);; + *) + AC_MSG_ERROR([Invalid BSP]);; + esac +]) diff --git a/c/src/lib/libbsp/or1k/configure.ac b/c/src/lib/libbsp/or1k/configure.ac new file mode 100644 index 0000000..96bba16 --- /dev/null +++ b/c/src/lib/libbsp/or1k/configure.ac @@ -0,0 +1,19 @@ +# Process this file with autoconf to produce a configure script. + +AC_PREREQ([2.69]) +AC_INIT([rtems-c-src-lib-libbsp-or1k],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla]) +AC_CONFIG_SRCDIR([or1ksim]) +RTEMS_TOP(../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define foreign 1.12.2]) +AM_MAINTAINER_MODE + +RTEMS_ENV_RTEMSBSP +RTEMS_PROJECT_ROOT + +RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY]) + +# Explicitly list all Makefiles here +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am new file mode 100644 index 0000000..d5eb10c --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am @@ -0,0 +1,109 @@ +# +# @file +# +# @brief Makefile of LibBSP for the or1ksim BSP. +# + +ACLOCAL_AMFLAGS = -I ../../../../aclocal + +include $(top_srcdir)/../../../../automake/compile.am + +include_bspdir = $(includedir)/bsp +#include_libcpudir = $(includedir)/libcpu + +dist_project_lib_DATA = bsp_specs + +############################################################################### +# Header # +############################################################################### + +include_bsp_HEADERS = +include_HEADERS = include/bsp.h + +nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h + +include_bsp_HEADERS += ../shared/include/linker-symbols.h +include_bsp_HEADERS += ../../../libbsp/shared/include/mm.h +include_bsp_HEADERS += ../../shared/include/utility.h +include_bsp_HEADERS += ../../shared/include/irq-generic.h +include_bsp_HEADERS += ../../shared/include/irq-info.h +include_bsp_HEADERS += ../../shared/include/stackalloc.h +include_bsp_HEADERS += ../../shared/include/uart-output-char.h +include_bsp_HEADERS += ../../shared/tod.h +include_bsp_HEADERS += ../../shared/include/tm27.h +include_bsp_HEADERS += include/irq.h +include_bsp_HEADERS += include/uart.h +include_bsp_HEADERS += include/or1ksim.h + +nodist_include_HEADERS = ../../shared/include/coverhd.h \ + include/bspopts.h + +############################################################################### +# Data # +############################################################################### + +noinst_LIBRARIES = libbspstart.a + +libbspstart_a_SOURCES = start/start.S + +project_lib_DATA = start.$(OBJEXT) + +project_lib_DATA += startup/linkcmds +project_lib_DATA += ../shared/startup/linkcmds.base + +############################################################################### +# LibBSP # +############################################################################### + +noinst_LIBRARIES += libbsp.a + +libbsp_a_SOURCES = +libbsp_a_CPPFLAGS = +libbsp_a_LIBADD = + +# Startup +libbsp_a_SOURCES += ../../shared/bspstart.c +libbsp_a_SOURCES += ../../shared/bspreset.c + +# Shared +libbsp_a_SOURCES += ../../shared/bootcard.c +libbsp_a_SOURCES += ../../shared/bspclean.c +libbsp_a_SOURCES += ../../shared/bspgetworkarea.c +libbsp_a_SOURCES += ../../shared/bsplibc.c +libbsp_a_SOURCES += ../../shared/bsppost.c +libbsp_a_SOURCES += ../../shared/bsppredriverhook.c +libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c +libbsp_a_SOURCES += ../../shared/cpucounterread.c +libbsp_a_SOURCES += ../../shared/cpucounterdiff.c +libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c +libbsp_a_SOURCES += ../../shared/sbrk.c +libbsp_a_SOURCES += ../../shared/src/stackalloc.c + +# Console +libbsp_a_SOURCES += ../../shared/console.c +libbsp_a_SOURCES += ../../shared/console_control.c +libbsp_a_SOURCES += ../../shared/console_read.c +libbsp_a_SOURCES += ../../shared/console_select.c +libbsp_a_SOURCES += ../../shared/console_write.c +libbsp_a_SOURCES += console/console-config.c +libbsp_a_SOURCES += console/uart.c + +# Timer +libbsp_a_SOURCES += timer/timer.c + +# clock +libbsp_a_SOURCES += clock/clockdrv.c ../../../shared/clockdrv_shell.h + +# IRQ +libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c +libbsp_a_SOURCES += ../../shared/src/irq-generic.c +libbsp_a_SOURCES += ../../shared/src/irq-info.c +libbsp_a_SOURCES += irq/irq.c +############################################################################### +# Special Rules # +############################################################################### + +DISTCLEANFILES = include/bspopts.h + +include $(srcdir)/preinstall.am +include $(top_srcdir)/../../../../automake/local.am diff --git a/c/src/lib/libbsp/or1k/or1ksim/README b/c/src/lib/libbsp/or1k/or1ksim/README new file mode 100644 index 0000000..43b4703 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/README @@ -0,0 +1,17 @@ +This BSP should run only on or1ksim: the main simulator for or1k architecture. +or1ksim should be used for testing purposes. + +svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/or1ksim +cd or1ksim +mkdir builddir_or1ksim +cd builddir_or1ksim +../configure --target=or32-elf --prefix=/opt/or1ksim +make all +make install +export PATH=/opt/or1ksim/bin:$PATH + +Configuration file "sim.cfg" should be provided for complex board +configurations at the current directory (which you run or1ksim from) or at +~/.or1k/ + +sim -f sim.cfg hello.exe diff --git a/c/src/lib/libbsp/or1k/or1ksim/bsp_specs b/c/src/lib/libbsp/or1k/or1ksim/bsp_specs new file mode 100644 index 0000000..0fcd2dc --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/bsp_specs @@ -0,0 +1,11 @@ +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*startfile: +%{!qrtems: %(old_startfile)} %{!nostdlib: %{qrtems: \ +%{!qrtems_debug: start.o%s} \ +%{qrtems_debug: start_g.o%s}}} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e _start} diff --git a/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c b/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c new file mode 100644 index 0000000..3877fe0 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c @@ -0,0 +1,104 @@ +/** + * @file + * + * @ingroup bsp_clock + * + * @brief or1ksim clock support. + */ + +/* + * or1ksim Clock driver + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#include +#include +#include +#include +#include +#include + +/* The number of clock cycles before generating a tick timer interrupt. */ +#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT 0xFFED9 +#define OR1KSIM_CLOCK_CYCLE_TIME_NANOSECONDS 10 + +/* This prototype is added here to Avoid warnings */ +void Clock_isr(void *arg); + +static void or1ksim_clock_at_tick(void) +{ + uint32_t TTMR; + + /* For TTMR register, + * The least significant 28 bits are the number of clock cycles + * before generating a tick timer interrupt. While the most + * significant 4 bits are used for mode configuration, tick timer + * interrupt enable and pending interrupts status. + */ + TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE | + (TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT & CPU_OR1K_SPR_TTMR_TP_MASK) + ) & ~(CPU_OR1K_SPR_TTMR_IP); + + _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR); + _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0); +} + +static void or1ksim_clock_handler_install(proc_ptr new_isr, proc_ptr old_isr) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + old_isr = NULL; + _CPU_ISR_install_vector(OR1K_EXCEPTION_TICK_TIMER, + new_isr, + old_isr); + + if (sc != RTEMS_SUCCESSFUL) { + rtems_fatal_error_occurred(0xdeadbeef); + } +} + +static void or1ksim_clock_initialize(void) +{ + uint32_t sr; + + or1ksim_clock_at_tick(); + + /* Enable tick timer */ + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + sr |= CPU_OR1K_SPR_SR_TEE; + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); +} + + static void or1ksim_clock_cleanup(void) +{ +} + +/* + * Return the nanoseconds since last tick + */ +static uint32_t or1ksim_clock_nanoseconds_since_last_tick(void) +{ + return + TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT * OR1KSIM_CLOCK_CYCLE_TIME_NANOSECONDS; +} + +#define Clock_driver_support_at_tick() or1ksim_clock_at_tick() + +#define Clock_driver_support_initialize_hardware() or1ksim_clock_initialize() + +#define Clock_driver_support_install_isr(isr, old_isr) \ + do { \ + or1ksim_clock_handler_install(isr, old_isr); \ + old_isr = NULL; \ + } while (0) + +#define Clock_driver_support_shutdown_hardware() or1ksim_clock_cleanup() + +#define Clock_driver_nanoseconds_since_last_tick \ + or1ksim_clock_nanoseconds_since_last_tick + +#include "../../../shared/clockdrv_shell.h" diff --git a/c/src/lib/libbsp/or1k/or1ksim/configure.ac b/c/src/lib/libbsp/or1k/or1ksim/configure.ac new file mode 100644 index 0000000..8aff7e3 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/configure.ac @@ -0,0 +1,30 @@ +# +# @file +# +# @brief Configure script of LibBSP for or1ksim BSP. +# + +AC_PREREQ(2.69) +AC_INIT([rtems-c-src-lib-libbsp-or1k-or1ksim],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla]) +AC_CONFIG_SRCDIR([bsp_specs]) +RTEMS_TOP(../../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) +RTEMS_BSP_CONFIGURE + +RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) +RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) + +RTEMS_BSPOPTS_SET([BSP_OR1K_OR1KSIM_PERIPHCLK],[*],[100000000U]) +RTEMS_BSPOPTS_HELP([BSP_OR1K_OR1KSIM_PERIPHCLK],[or1ksim PERIPHCLK clock frequency in Hz]) + +RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm]) +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +RTEMS_BSP_CLEANUP_OPTIONS(0, 0) +RTEMS_BSP_LINKCMDS + +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/or1k/or1ksim/console/console-config.c b/c/src/lib/libbsp/or1k/or1ksim/console/console-config.c new file mode 100644 index 0000000..9853f20 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/console/console-config.c @@ -0,0 +1,58 @@ +/** + * @file + * + * @ingroup or1ksim_uart + * + * @brief Console Configuration. + */ + +/* + * Copyright (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#include + +#include + +#include +#include +#include + +console_tbl Console_Configuration_Ports [] = { + { + .sDeviceName = "/dev/ttyS0", + .deviceType = SERIAL_CUSTOM, + .pDeviceFns = &or1ksim_uart_fns, + .deviceProbe = NULL, + .pDeviceFlow = NULL, + .ulCtrlPort1 = OR1KSIM_BSP_UART_BASE, + .ulCtrlPort2 = 0, + .ulClock = OR1KSIM_UART_DEFAULT_BAUD, + .ulIntVector = OR1KSIM_BSP_UART_IRQ + } +}; + +#define PORT_COUNT \ + (sizeof(Console_Configuration_Ports) \ + / sizeof(Console_Configuration_Ports [0])) + +unsigned long Console_Configuration_Count = PORT_COUNT; + +static void output_char(char c) +{ + const console_fns *con = + Console_Configuration_Ports [Console_Port_Minor].pDeviceFns; + + if (c == '\n') { + con->deviceWritePolled((int) Console_Port_Minor, '\r'); + } + con->deviceWritePolled((int) Console_Port_Minor, c); +} + +BSP_output_char_function_type BSP_output_char = output_char; + +BSP_polling_getchar_function_type BSP_poll_char = NULL; diff --git a/c/src/lib/libbsp/or1k/or1ksim/console/uart.c b/c/src/lib/libbsp/or1k/or1ksim/console/uart.c new file mode 100644 index 0000000..f1cfa09 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/console/uart.c @@ -0,0 +1,144 @@ +/** + * @file + * + * @ingroup or1ksim_uart + * + * @brief UART support. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#include +#include +#include +#include +#include +#include + +static rtems_vector_number uart_get_irq_number(const console_tbl *ct) +{ + return ct->ulIntVector; +} + +static uint32_t uart_get_baud(const console_tbl *ct) +{ + return ct->ulClock; +} + +static void uart_set_baud(int baud) +{ + int divisor = (OR1KSIM_BSP_CLOCK_FREQ) / (16 * baud); + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) |= + OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB; + + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_LOW) = divisor & 0xff; + + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_HIGH) = + (divisor >> 8) & 0xff; + + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) &= + ~(OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB); +} + +static void uart_initialize(int minor) +{ + /* Disable all interrupts */ + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_INT_ENABLE) = 0x00; + + /* Reset receiver and transmitter */ + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_FIFO_CTRL) = + OR1KSIM_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO | + OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR | + OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_XMIT | + OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_14; + + /* Set data pattern configuration */ + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) = + OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN8 & + (OR1KSIM_BSP_UART_REG_LINE_CTRL_STOP | + OR1KSIM_BSP_UART_REG_LINE_CTRL_PARITY); + + /* Set baud rate */ + uart_set_baud(OR1KSIM_UART_DEFAULT_BAUD); +} + +static int uart_first_open(int major, int minor, void *arg) +{ + rtems_libio_open_close_args_t *oc = (rtems_libio_open_close_args_t *) arg; + struct rtems_termios_tty *tty = (struct rtems_termios_tty *) oc->iop->data1; + const console_tbl *ct = Console_Port_Tbl [minor]; + console_data *cd = &Console_Port_Data [minor]; + + cd->termios_data = tty; + rtems_termios_set_initial_baud(tty, ct->ulClock); + + return 0; +} + +static int uart_last_close(int major, int minor, void *arg) +{ + return 0; +} + +static int uart_read_polled(int minor) +{ + return -1; +} + +static void uart_write_polled(int minor, char c) +{ + unsigned char lsr; + const uint32_t transmit_finished = + (OR1KSIM_BSP_UART_REG_LINE_STATUS_TEMT | + OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE); + + /* Wait until there is no pending data in the transmitter FIFO (empty) */ + do { + lsr = OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_STATUS); + } while (!(lsr & OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE)); + + OR1KSIM_REG(OR1KSIM_BSP_UART_REG_TX) = c; + + /* Wait until trasmit data is finished */ + do { + lsr = OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_STATUS); + } while ( (lsr & transmit_finished) != transmit_finished ); +} + +static ssize_t uart_write_support_polled( + int minor, + const char *s, + size_t n +) +{ + ssize_t i = 0; + + for (i = 0; i < n; ++i){ + uart_write_polled(minor, s [i]); + } + + return n; +} + +static int uart_set_attributes(int minor, const struct termios *term) +{ + return -1; +} + +const console_fns or1ksim_uart_fns = { + .deviceProbe = libchip_serial_default_probe, + .deviceFirstOpen = uart_first_open, + .deviceLastClose = uart_last_close, + .deviceRead = uart_read_polled, + .deviceWrite = uart_write_support_polled, + .deviceInitialize = uart_initialize, + .deviceWritePolled = uart_write_polled, + .deviceSetAttributes = uart_set_attributes, + .deviceOutputUsesInterrupts = false +}; diff --git a/c/src/lib/libbsp/or1k/or1ksim/include/bsp.h b/c/src/lib/libbsp/or1k/or1ksim/include/bsp.h new file mode 100644 index 0000000..502e4d9 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/include/bsp.h @@ -0,0 +1,47 @@ +/** + * @file + * + * @ingroup or1k_or1ksim + * + * @brief Global BSP definitions. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#ifndef LIBBSP_OR1K_OR1KSIM_H +#define LIBBSP_OR1K_OR1KSIM_H + +#include +#include +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_OR1K_OR1KSIM_H */ + +/** + * @defgroup or1k_or1ksim support + * + * @ingroup bsp_or1k + * + * @brief or1ksim support package + * + */ diff --git a/c/src/lib/libbsp/or1k/or1ksim/include/irq.h b/c/src/lib/libbsp/or1k/or1ksim/include/irq.h new file mode 100644 index 0000000..be669d8 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/include/irq.h @@ -0,0 +1,45 @@ +/** + * @file + * + * @ingroup or1ksim_interrupt + * + * @brief Interrupt definitions. + */ + +/** + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#ifndef LIBBSP_OR1K_OR1KSIM_IRQ_H +#define LIBBSP_OR1K_OR1KSIM_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#define BSP_INTERRUPT_VECTOR_MIN 0x100 +#define BSP_INTERRUPT_VECTOR_MAX 0x1F00 + +/* Interrupt Identification Register */ +#define OR1KSIM_BSP_UART_REG_INT_ID_MSI (0x00) +#define OR1KSIM_BSP_UART_REG_INT_ID_NO_INT (0x01) +#define OR1KSIM_BSP_UART_REG_INT_ID_THRI (0x02) +#define OR1KSIM_BSP_UART_REG_INT_ID_RDI (0x04) +#define OR1KSIM_BSP_UART_REG_INT_ID_ID (0x06) +#define OR1KSIM_BSP_UART_REG_INT_ID_RLSI (0x06) +#define OR1KSIM_BSP_UART_REG_INT_ID_TOI (0x0c) + +/* Interrupt Enable Register */ +#define OR1KSIM_BSP_UART_REG_INT_ENABLE_RDI (0x01) +#define OR1KSIM_BSP_UART_REG_INT_ENABLE_THRI (0x02) +#define OR1KSIM_BSP_UART_REG_INT_ENABLE_RLSI (0x04) +#define OR1KSIM_BSP_UART_REG_INT_ENABLE_MSI (0x08) + +#endif /* ASM */ +#endif /* LIBBSP_OR1K_OR1KSIM_IRQ_H */ diff --git a/c/src/lib/libbsp/or1k/or1ksim/include/or1ksim.h b/c/src/lib/libbsp/or1k/or1ksim/include/or1ksim.h new file mode 100644 index 0000000..8279566 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/include/or1ksim.h @@ -0,0 +1,118 @@ +/** + * @file + * + * @ingroup or1ksim_reg + * + * @brief Register definitions. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#ifndef LIBBSP_OR1K_OR1KSIM_H +#define LIBBSP_OR1K_OR1KSIM_H + +#include + +/** + * @defgroup or1ksim_reg Register Definitions + * + * @ingroup or1k_or1ksim + * + * @brief Register Definitions + * + * @{ + */ + +/** + * @name Register Macros + * + * @{ + */ + + #define OR1KSIM_REG(x) (*((volatile char *) (x))) + #define OR1KSIM_BIT(n) (1 << (n)) + +/** @} */ + +/** + * @name Internal OR1K UART Registers + * + * @{ + */ +#define OR1KSIM_BSP_CLOCK_FREQ 100000000UL +#define OR1KSIM_BSP_UART_BASE 0x90000000 + +#define OR1KSIM_BSP_UART_REG_TX (OR1KSIM_BSP_UART_BASE+0) +#define OR1KSIM_BSP_UART_REG_RX (OR1KSIM_BSP_UART_BASE+0) +#define OR1KSIM_BSP_UART_REG_DEV_LATCH_LOW (OR1KSIM_BSP_UART_BASE+1) +#define OR1KSIM_BSP_UART_REG_DEV_LATCH_HIGH (OR1KSIM_BSP_UART_BASE+1) +#define OR1KSIM_BSP_UART_REG_INT_ENABLE (OR1KSIM_BSP_UART_BASE+2) +#define OR1KSIM_BSP_UART_REG_INT_ID (OR1KSIM_BSP_UART_BASE+2) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL (OR1KSIM_BSP_UART_BASE+2) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL (OR1KSIM_BSP_UART_BASE+3) +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL (OR1KSIM_BSP_UART_BASE+4) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS (OR1KSIM_BSP_UART_BASE+5) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS (OR1KSIM_BSP_UART_BASE+6) +#define OR1KSIM_BSP_UART_REG_SCRATCH (OR1KSIM_BSP_UART_BASE+7) + +/* FIFO Control Register */ +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_1 (0x00) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO (0x01) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR (0x02) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_XMIT (0x03) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_DMA_SELECT (0x08) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_4 (0x40) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_8 (0x80) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_14 (0xC0) +#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_MASK (0xC0) + +/* Line Control Register */ +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN5 (0x00) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN6 (0x01) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN7 (0x02) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN8 (0x03) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_STOP (0x04) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_PARITY (0x08) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_EPAR (0x10) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_SPAR (0x20) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_SBC (0x40) +#define OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB (0x80) + +/* Line Status Register */ +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_DR (0x01) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_OE (0x02) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_PE (0x04) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_FE (0x08) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_BI (0x10) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE (0x20) +#define OR1KSIM_BSP_UART_REG_LINE_STATUS_TEMT (0x40) + +/* Modem Control Register */ +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_DTR (0x01) +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_RTS (0x02) +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_OUT1 (0x04) +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_OUT2 (0x08) +#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_LOOP (0x10) + +/* Modem Status Register */ +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DCTS (0x01) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DDSR (0x02) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_TERI (0x04) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DDCD (0x08) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_CTS (0x10) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DSR (0x20) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_RI (0x40) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DCD (0x80) +#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_ANY_DELTA (0x0F) + +/** @} */ + +/** @} */ + +#endif /* LIBBSP_OR1K_OR1KSIM_H */ diff --git a/c/src/lib/libbsp/or1k/or1ksim/include/uart.h b/c/src/lib/libbsp/or1k/or1ksim/include/uart.h new file mode 100644 index 0000000..92ed203 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/include/uart.h @@ -0,0 +1,42 @@ +/** + * @file + * + * @ingroup or1ksim_uart + * + * @brief UART support. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +/** + * @defgroup or1ksim_uart UART Support + * + * @ingroup or1k_or1ksim + * + * @brief Universal Asynchronous Receiver/Transmitter (UART) Support + */ + +#ifndef LIBBSP_OR1K_OR1KSIM_UART_H +#define LIBBSP_OR1K_OR1KSIM_UART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define OR1KSIM_UART_DEFAULT_BAUD 115200 +#define OR1KSIM_BSP_UART_IRQ 13 +extern const console_fns or1ksim_uart_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_OR1K_OR1KSIM_UART_H */ diff --git a/c/src/lib/libbsp/or1k/or1ksim/irq/irq.c b/c/src/lib/libbsp/or1k/or1ksim/irq/irq.c new file mode 100644 index 0000000..c3c4d6d --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/irq/irq.c @@ -0,0 +1,42 @@ +/** + * @file + * + * @ingroup or1k_interrupt + * + * @brief Interrupt support. + */ + +/* + * Copyright (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include + +/* Almost all of the jobs that the following functions should + * do are implemented in cpukit + */ + +void bsp_interrupt_handler_default(rtems_vector_number vector) +{ + printk("spurious interrupt: %u\n", vector); +} + +rtems_status_code bsp_interrupt_facility_initialize() +{ + return 0; +} + +rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) +{ + return 0; +} + +rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) +{ + return 0; +} diff --git a/c/src/lib/libbsp/or1k/or1ksim/make/custom/or1k_or1ksim.cfg b/c/src/lib/libbsp/or1k/or1ksim/make/custom/or1k_or1ksim.cfg new file mode 100644 index 0000000..fff00ae --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/make/custom/or1k_or1ksim.cfg @@ -0,0 +1,7 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = or1k + +CPU_CFLAGS = -O2 + +CFLAGS_OPTIMIZE_V ?= -O0 -g diff --git a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am new file mode 100644 index 0000000..e75733c --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am @@ -0,0 +1,114 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES = $(TMPINSTALL_FILES) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) + +$(PROJECT_LIB)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_LIB) + @: > $(PROJECT_LIB)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) + +$(PROJECT_INCLUDE)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE) + @: > $(PROJECT_INCLUDE)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) + +$(PROJECT_INCLUDE)/bsp/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp + @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) + +$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs +PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs + +$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h + +$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h + +$(PROJECT_INCLUDE)/bsp/linker-symbols.h: ../shared/include/linker-symbols.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/linker-symbols.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/linker-symbols.h + +$(PROJECT_INCLUDE)/bsp/mm.h: ../../../libbsp/shared/include/mm.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mm.h + +$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h + +$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h + +$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h + +$(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h + +$(PROJECT_INCLUDE)/bsp/uart-output-char.h: ../../shared/include/uart-output-char.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart-output-char.h + +$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h + +$(PROJECT_INCLUDE)/bsp/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tm27.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tm27.h + +$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h + +$(PROJECT_INCLUDE)/bsp/uart.h: include/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h + +$(PROJECT_INCLUDE)/bsp/or1ksim.h: include/or1ksim.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/or1ksim.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/or1ksim.h + +$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h + +$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h + +$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) +TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) + +$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds + +$(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base diff --git a/c/src/lib/libbsp/or1k/or1ksim/start/start.S b/c/src/lib/libbsp/or1k/or1ksim/start/start.S new file mode 100644 index 0000000..6942b52 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/start/start.S @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ +#include + +/* The following macro defines the first instructions every exception + * should execute before jumping to its handler function from the + * exception vector table. r3 is saved into the stack and loaded with + * vector number before jumping to _ISR_Handler. r3 value is restored + * back from _ISR_Handler after handling the exception and before + * returning from interrupt. + */ +#define EXCEPTION_SETUP(vector) \ + l.nop ;\ + l.addi r1, r1, -4 ;\ + l.sw 0(r1), r3; \ + l.addi r3, r0, vector; \ + l.j _ISR_Handler; \ + l.nop + + .extern bsp_start + .extern boot_card + .extern bsp_section_bss_begin + .extern bsp_section_bss_end + + .extern bsp_start_vector_table_end + .extern bsp_start_vector_table_size + .extern bsp_vector_table_size + .extern bsp_section_stack_begin + + .extern exception_frame_save + .extern _OR1K_Exception_Process + .extern _OR1K_Exception_default + .extern rtems_clock_tick + .extern _exit + .extern printk + .extern bsp_interrupt_handler_default + + /* Global symbols */ + .global _start + .global bsp_start_vector_table_begin + +/* Popualte HW vector table */ + +.section .vector, "ax" + +.org 0x100 +_reset: + l.j _start + l.nop + +.org 0x200 +_buserr: + EXCEPTION_SETUP(2) + +.org 0x300 +_dPageFault: + EXCEPTION_SETUP(3) + +.org 0x400 +_iPageFaule: + EXCEPTION_SETUP(4) + +.org 0x500 +_timer: + EXCEPTION_SETUP(5) + +.org 0x600 +_unalign: + EXCEPTION_SETUP(6) + +.org 0x700 +_undefIns: + EXCEPTION_SETUP(7) + +.org 0x800 +_exInt: + EXCEPTION_SETUP(8) + +.org 0x900 +_dTLB: + EXCEPTION_SETUP(9) + +.org 0xA00 +_iTLB: + EXCEPTION_SETUP(10) + +.org 0xB00 +_range: + EXCEPTION_SETUP(11) + +.org 0xC00 +_syscall: + EXCEPTION_SETUP(12) + +.org 0xD00 +_fp: + EXCEPTION_SETUP(13) + +.org 0xE00 +_trap: + EXCEPTION_SETUP(14) + +.org 0xF00 +_undef1: + EXCEPTION_SETUP(15) + +.org 0x1500 +_undef2: + EXCEPTION_SETUP(16) + +.org 0x1900 +_undef3: + EXCEPTION_SETUP(17) + +.org 0x1F00 + +bsp_start_vector_table_begin: + + .word 0 + .word _start /* Reset */ + .word _OR1K_Exception_default /* Bus Error */ + .word _OR1K_Exception_default /* Data Page Fault */ + .word _OR1K_Exception_default /* Instruction Page Fault */ + .word _OR1K_Exception_default /* Tick timer */ + .word _OR1K_Exception_default /* Alignment */ + .word _OR1K_Exception_default /* Undefiend Instruction */ + .word _OR1K_Exception_default /* External Interrupt */ + .word _OR1K_Exception_default /* Data TLB Miss */ + .word _OR1K_Exception_default /* Instruction TLB Miss */ + .word _OR1K_Exception_default /* Range Exception */ + .word _OR1K_Exception_default /* System Call */ + .word _OR1K_Exception_default /* Floating Point Exception */ + .word _OR1K_Exception_default /* Trap */ + .word _OR1K_Exception_default /* Reserver for future use */ + .word _OR1K_Exception_default /* Reserved for implementation-specific */ + .word _OR1K_Exception_default /* Reserved for custom exceptions. */ + +bsp_start_vector_table_end: + + .section ".bsp_start_text", "ax" + .type _start, at function + +_start: + /* Set SR register to Supervision mode */ + l.ori r1, r0, 0x1 + l.mtspr r0, r1, 17 + + /* load stack and frame pointers */ + l.movhi r1, hi(bsp_section_stack_begin) + l.ori r1, r1, lo(bsp_section_stack_begin) + l.add r2, r0, r1 + +/* Clearing .bss */ + l.movhi r13, hi(bsp_section_bss_begin) + l.ori r13, r13, lo(bsp_section_bss_begin) + l.movhi r15, hi(bsp_section_bss_end) + l.ori r15, r15, lo(bsp_section_bss_end) + +_loop_clear_bss: + l.sfgeu r13, r15 + l.bf _end_clear_bss + l.addi r13, r13, 4 + l.sw 0(r13), r0 + l.j _loop_clear_bss + l.nop +_end_clear_bss: + + l.j boot_card + l.nop + +/* Temporary code for unhandled exceptions */ +.section .text +.align +.global _unhandled_exception + +unhandled_exception: + l.nop diff --git a/c/src/lib/libbsp/or1k/or1ksim/startup/linkcmds b/c/src/lib/libbsp/or1k/or1ksim/startup/linkcmds new file mode 100644 index 0000000..cef99d3 --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/startup/linkcmds @@ -0,0 +1,41 @@ +/** + * @file + * + * @ingroup bsp_linker + * + * @brief Memory map + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +MEMORY + { + VECTOR_RAM (AIW) : ORIGIN = 0x0 , LENGTH = 8260 + RAM : org = 0x00002048, l = 0x1FFDFB8 + UNEXPECTED_SECTIONS : ORIGIN = 0xffffffff, LENGTH = 0 + } + +REGION_ALIAS ("REGION_START", RAM); +REGION_ALIAS ("REGION_VECTOR", VECTOR_RAM); +REGION_ALIAS ("REGION_TEXT", RAM); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM); +REGION_ALIAS ("REGION_RODATA", RAM); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM); +REGION_ALIAS ("REGION_DATA", RAM); +REGION_ALIAS ("REGION_DATA_LOAD", RAM); +REGION_ALIAS ("REGION_FAST_DATA", RAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); +REGION_ALIAS ("REGION_BSS", RAM); +REGION_ALIAS ("REGION_WORK", RAM); +REGION_ALIAS ("REGION_STACK", RAM); + +bsp_section_vector_begin = 0; +bsp_section_stack_begin = 0x1FFDFB8; + +INCLUDE linkcmds.base diff --git a/c/src/lib/libbsp/or1k/or1ksim/timer/timer.c b/c/src/lib/libbsp/or1k/or1ksim/timer/timer.c new file mode 100644 index 0000000..ec3c33e --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/timer/timer.c @@ -0,0 +1,64 @@ +/** + * @file + * + * @ingroup or1ksim + * + * @brief Benchmark timer support. + */ + +/* + * Copyright (c) 2014 by Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#include +#include +#include +#include + +#define OR1KSIM_NANOSECONDS_PER_CLK_CYCLE 10 + +static bool benchmark_timer_find_average_overhead = false; +static uint64_t benchmark_timer_base; + +void benchmark_timer_initialize(void) +{ + benchmark_timer_base = _OR1K_mfspr(CPU_OR1K_SPR_TTCR); +} + +#define AVG_OVERHEAD 0 +#define LEAST_VALID 1 + +uint32_t benchmark_timer_read( void ) +{ + uint64_t clicks; + uint64_t total; + uint64_t delta; + /* + * Read the timer and see how many clicks (clock cycles) + * has passed since timer initialization. + */ + clicks = _OR1K_mfspr(CPU_OR1K_SPR_TTCR); + + delta = clicks - benchmark_timer_base; + + /* total in nanoseconds */ + total = OR1KSIM_NANOSECONDS_PER_CLK_CYCLE * (delta); + + if ( benchmark_timer_find_average_overhead == true ) + return total; /* in nanoseconds microsecond units */ + else { + if ( total < LEAST_VALID ) + return 0; /* below timer resolution */ + + return (total - AVG_OVERHEAD); + } +} + +void benchmark_timer_disable_subtracting_average_overhead(bool find_flag) +{ + benchmark_timer_find_average_overhead = find_flag; +} diff --git a/c/src/lib/libbsp/or1k/preinstall.am b/c/src/lib/libbsp/or1k/preinstall.am new file mode 100644 index 0000000..fe8d090 --- /dev/null +++ b/c/src/lib/libbsp/or1k/preinstall.am @@ -0,0 +1,6 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif diff --git a/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h b/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h new file mode 100644 index 0000000..f0f8377 --- /dev/null +++ b/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h @@ -0,0 +1,79 @@ +#ifndef LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup or1k_linker Linker Support + * + * @ingroup or1k_shared + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM + #define LINKER_SYMBOL(sym) extern char sym []; +#else + #define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_vector_begin) +LINKER_SYMBOL(bsp_section_vector_end) +LINKER_SYMBOL(bsp_section_vector_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_vector_table_begin) +LINKER_SYMBOL(bsp_vector_table_end) +LINKER_SYMBOL(bsp_vector_table_size) + +LINKER_SYMBOL(bsp_start_vector_table_begin) +LINKER_SYMBOL(bsp_start_vector_table_end) +LINKER_SYMBOL(bsp_start_vector_table_size) + +LINKER_SYMBOL(bsp_translation_table_base) +LINKER_SYMBOL(bsp_translation_table_end) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_OR1K_SHARED_LINKER_SYMBOLS_H */ diff --git a/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base b/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base new file mode 100644 index 0000000..31bb92d --- /dev/null +++ b/c/src/lib/libbsp/or1k/shared/startup/linkcmds.base @@ -0,0 +1,310 @@ +/** + * @file + * + * @ingroup bsp_linker + * + * @brief Linker command base file. + */ + +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +OUTPUT_ARCH (or1k) + +ENTRY (_start) + +/* + * Global symbols that may be defined externally + */ + +bsp_start_vector_table_begin = 0x1F00; +bsp_vector_table_size = DEFINED (bsp_vector_table_size) ? bsp_vector_table_size +: 8260; +/* 8192 for raw vector table, and 17 * 4 for handlers vector. */ + +bsp_section_xbarrier_align = DEFINED (bsp_section_xbarrier_align) ? bsp_section_xbarrier_align : 1; +bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1; +bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1; + +bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 8; + +bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 0; +bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align); + +bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 1; + +SECTIONS { + + .vector : ALIGN_WITH_INPUT { + *(.vector) + . = ALIGN(bsp_vector_table_size); + bsp_section_vector_end = .; + } > REGION_VECTOR AT > REGION_VECTOR + bsp_section_vector_size = bsp_section_vector_end - bsp_section_vector_begin; + bsp_vector_table_begin = bsp_section_vector_begin; + bsp_vector_table_end = bsp_vector_table_begin + bsp_vector_table_size; + + .start : ALIGN_WITH_INPUT { + bsp_section_start_begin = .; + KEEP (*(.bsp_start_text)) + KEEP (*(.bsp_start_data)) + bsp_section_start_end = .; + } > REGION_START AT > REGION_START + bsp_section_start_size = bsp_section_start_end - bsp_section_start_begin; + +.xbarrier : ALIGN_WITH_INPUT { + . = ALIGN (bsp_section_xbarrier_align); + } > REGION_VECTOR AT > REGION_VECTOR + +.text : ALIGN_WITH_INPUT { + bsp_section_text_begin = .; + *(.text.unlikely .text.*_unlikely) + *(.text .stub .text.* .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .init : ALIGN_WITH_INPUT { + KEEP (*(.init)) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .fini : ALIGN_WITH_INPUT { + KEEP (*(.fini)) + bsp_section_text_end = .; + } > REGION_TEXT AT > REGION_TEXT_LOAD + bsp_section_text_size = bsp_section_text_end - bsp_section_text_begin; + bsp_section_text_load_begin = LOADADDR (.text); + bsp_section_text_load_end = bsp_section_text_load_begin + bsp_section_text_size; + +.robarrier : ALIGN_WITH_INPUT { + . = ALIGN (bsp_section_robarrier_align); + } > REGION_RODATA AT > REGION_RODATA + +.rodata : ALIGN_WITH_INPUT { + bsp_section_rodata_begin = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD +.eh_frame : ALIGN_WITH_INPUT { + KEEP (*(.eh_frame)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gcc_except_table : ALIGN_WITH_INPUT { + *(.gcc_except_table .gcc_except_table.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tdata : ALIGN_WITH_INPUT { + _TLS_Data_begin = .; + *(.tdata .tdata.* .gnu.linkonce.td.*) + _TLS_Data_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tbss : ALIGN_WITH_INPUT { + _TLS_BSS_begin = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) + _TLS_BSS_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; + _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; + _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; + _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; + _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; + _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); + .preinit_array : ALIGN_WITH_INPUT { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .init_array : ALIGN_WITH_INPUT { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .fini_array : ALIGN_WITH_INPUT { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .ctors : ALIGN_WITH_INPUT { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dtors : ALIGN_WITH_INPUT { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .data.rel.ro : ALIGN_WITH_INPUT { + *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) + *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .jcr : ALIGN_WITH_INPUT { + KEEP (*(.jcr)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .interp : ALIGN_WITH_INPUT { + *(.interp) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .note.gnu.build-id : ALIGN_WITH_INPUT { + *(.note.gnu.build-id) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .hash : ALIGN_WITH_INPUT { + *(.hash) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.hash : ALIGN_WITH_INPUT { + *(.gnu.hash) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynsym : ALIGN_WITH_INPUT { + *(.dynsym) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynstr : ALIGN_WITH_INPUT { + *(.dynstr) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version : ALIGN_WITH_INPUT { + *(.gnu.version) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version_d : ALIGN_WITH_INPUT { + *(.gnu.version_d) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version_r : ALIGN_WITH_INPUT { + *(.gnu.version_r) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rel.dyn : ALIGN_WITH_INPUT { + *(.rel.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rel.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rel.dtors) + *(.rel.got) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + PROVIDE_HIDDEN (__rel_iplt_start = .); + *(.rel.iplt) + PROVIDE_HIDDEN (__rel_iplt_end = .); + PROVIDE_HIDDEN (__rela_iplt_start = .); + PROVIDE_HIDDEN (__rela_iplt_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rela.dyn : ALIGN_WITH_INPUT { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + PROVIDE_HIDDEN (__rel_iplt_start = .); + PROVIDE_HIDDEN (__rel_iplt_end = .); + PROVIDE_HIDDEN (__rela_iplt_start = .); + *(.rela.iplt) + PROVIDE_HIDDEN (__rela_iplt_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rel.plt : ALIGN_WITH_INPUT { + *(.rel.plt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rela.plt : ALIGN_WITH_INPUT { + *(.rela.plt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .plt : ALIGN_WITH_INPUT { + *(.plt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .iplt : ALIGN_WITH_INPUT { + *(.iplt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynamic : ALIGN_WITH_INPUT { + *(.dynamic) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .got : ALIGN_WITH_INPUT { + *(.got.plt) *(.igot.plt) *(.got) *(.igot) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rtemsroset : ALIGN_WITH_INPUT { + /* Special FreeBSD linker set sections */ + __start_set_sysctl_set = .; + *(set_sysctl_*); + __stop_set_sysctl_set = .; + *(set_domain_*); + *(set_pseudo_*); + + KEEP (*(SORT(.rtemsroset.*))) + bsp_section_rodata_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + bsp_section_rodata_size = bsp_section_rodata_end - bsp_section_rodata_begin; + bsp_section_rodata_load_begin = LOADADDR (.rodata); + bsp_section_rodata_load_end = bsp_section_rodata_load_begin + bsp_section_rodata_size; + +.rwbarrier : ALIGN_WITH_INPUT { + . = ALIGN (bsp_section_rwbarrier_align); + } > REGION_DATA AT > REGION_DATA + +.data : ALIGN_WITH_INPUT { + bsp_section_data_begin = .; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } > REGION_DATA AT > REGION_DATA_LOAD + .data1 : ALIGN_WITH_INPUT { + *(.data1) + } > REGION_DATA AT > REGION_DATA_LOAD + .rtemsrwset : ALIGN_WITH_INPUT { + KEEP (*(SORT(.rtemsrwset.*))) + bsp_section_data_end = .; + } > REGION_DATA AT > REGION_DATA_LOAD + bsp_section_data_size = bsp_section_data_end - bsp_section_data_begin; + bsp_section_data_load_begin = LOADADDR (.data); + bsp_section_data_load_end = bsp_section_data_load_begin + bsp_section_data_size; + + .bss : ALIGN_WITH_INPUT { + bsp_section_bss_begin = .; + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + bsp_section_bss_end = .; + } > REGION_BSS AT > REGION_BSS + bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_begin; + +.work : ALIGN_WITH_INPUT { + /* + * The work section will occupy the remaining REGION_WORK region and + * contains the RTEMS work space and heap. + */ + bsp_section_work_begin = .; + . += ORIGIN (REGION_WORK) + LENGTH (REGION_WORK) - ABSOLUTE (.); + bsp_section_work_end = .; + } > REGION_WORK AT > REGION_WORK + bsp_section_work_size = bsp_section_work_end - bsp_section_work_begin; + + .stack : ALIGN_WITH_INPUT { + bsp_section_stack_end = .; + } > REGION_STACK AT > REGION_STACK + bsp_section_stack_size = bsp_section_stack_begin - bsp_section_stack_end; + + RamBase = ORIGIN (REGION_WORK); + RamSize = LENGTH (REGION_WORK); + WorkAreaBase = bsp_section_work_begin; + HeapSize = 0; +} From joel at rtems.org Wed Aug 20 20:41:01 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 20 Aug 2014 15:41:01 -0500 Subject: [rtems commit] or1k.t: Fix spelling errors Message-ID: <20140820204101.1C1B37006E4@git.rtems.org> Module: rtems Branch: master Commit: a7ec6fac9b3c5821031249791d7446d5bf7fca15 Changeset: http://git.rtems.org/rtems/commit/?id=a7ec6fac9b3c5821031249791d7446d5bf7fca15 Author: Joel Sherrill Date: Wed Aug 20 15:49:42 2014 -0500 or1k.t: Fix spelling errors --- doc/cpu_supplement/or1k.t | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/doc/cpu_supplement/or1k.t b/doc/cpu_supplement/or1k.t index 4f1bf18..cce55fd 100644 --- a/doc/cpu_supplement/or1k.t +++ b/doc/cpu_supplement/or1k.t @@ -59,10 +59,10 @@ There are only two levels: interrupts enabled and interrupts disabled. @subsection Interrupt Stack -OpenRISC RTEMS port uses RTEMS SW interrupt stack. -The stack for interrupts is allocated during interrupt driver initilization. -When an interrup entered, the _ISR_Handler routine is resposible for -switching from the interrupted task stack to RTEMS SW interrupt stack. +The OpenRISC RTEMS port uses a dedicated software interrupt stack. +The stack for interrupts is allocated during interrupt driver initialization. +When an interrupt is entered, the _ISR_Handler routine is responsible for +switching from the interrupted task stack to RTEMS software interrupt stack. @section Default Fatal Error Processing From joel at rtems.org Wed Aug 20 20:41:01 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 20 Aug 2014 15:41:01 -0500 Subject: [rtems commit] Add new documentation section for OpenRISC CPU architecture. Message-ID: <20140820204101.3D44F7006BA@git.rtems.org> Module: rtems Branch: master Commit: b08829228d2efc6c506fa3a05b0266baf70f8681 Changeset: http://git.rtems.org/rtems/commit/?id=b08829228d2efc6c506fa3a05b0266baf70f8681 Author: Hesham ALMatary Date: Sat Aug 16 11:30:19 2014 -0500 Add new documentation section for OpenRISC CPU architecture. --- doc/cpu_supplement/Makefile.am | 6 +++ doc/cpu_supplement/cpu_supplement.texi | 2 + doc/cpu_supplement/or1k.t | 76 ++++++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+), 0 deletions(-) diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am index 3083922..300ff78 100644 --- a/doc/cpu_supplement/Makefile.am +++ b/doc/cpu_supplement/Makefile.am @@ -23,6 +23,7 @@ GENERATED_FILES += m32r.texi GENERATED_FILES += m68k.texi GENERATED_FILES += microblaze.texi GENERATED_FILES += mips.texi +GENERATED_FILES += or1k.texi GENERATED_FILES += powerpc.texi GENERATED_FILES += nios2.texi GENERATED_FILES += sh.texi @@ -101,6 +102,11 @@ mips.texi: mips.t -u "Top" \ -n "" < $< > $@ +or1k.texi: or1k.t + $(BMENU2) -p "" \ + -u "Top" \ + -n "" < $< > $@ + powerpc.texi: powerpc.t $(BMENU2) -p "" \ -u "Top" \ diff --git a/doc/cpu_supplement/cpu_supplement.texi b/doc/cpu_supplement/cpu_supplement.texi index 1087538..5c484d0 100644 --- a/doc/cpu_supplement/cpu_supplement.texi +++ b/doc/cpu_supplement/cpu_supplement.texi @@ -73,6 +73,7 @@ * M68xxx and Coldfire Specific Information:: * Xilinx MicroBlaze Specific Information:: * MIPS Specific Information:: +* OpenRISC 1000 Specific Information:: * Altera Nios II Specific Information:: * PowerPC Specific Information:: * SuperH Specific Information:: @@ -97,6 +98,7 @@ @include microblaze.texi @include mips.texi @include nios2.texi + at include or1k.texi @include powerpc.texi @include sh.texi @include sparc.texi diff --git a/doc/cpu_supplement/or1k.t b/doc/cpu_supplement/or1k.t new file mode 100644 index 0000000..4f1bf18 --- /dev/null +++ b/doc/cpu_supplement/or1k.t @@ -0,0 +1,76 @@ + at c + at c COPYRIGHT (c) 2014 Hesham ALMatary + at c All rights reserved. + + at ifinfo + at end ifinfo + at chapter OpenRISC 1000 Specific Information + +This chapter discusses the + at uref{http://opencores.org/or1k/Main_Page, OpenRISC 1000 architecture} +dependencies in this port of RTEMS. There are many implementations +for OpenRISC like or1200 and mor1kx. Currently RTEMS supports basic +features that all implementations should have. + + at subheading Architecture Documents + +For information on the OpenRISC 1000 architecture refer to the + at uref{http://openrisc.github.io/or1k.html,OpenRISC 1000 architecture manual}. + + at section Calling Conventions + +Please refer to the + at uref{http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882,Function Calling Sequence}. + + at subsection Floating Point Unit + +A floating point unit is currently not supported. + + at section Memory Model + +A flat 32-bit memory model is supported. + + at section Interrupt Processing + +OpenRISC 1000 architecture has 13 exception types: + + at itemize @bullet + + at item Reset + at item Bus Error + at item Data Page Fault + at item Instruction Page Fault + at item Tick Timer + at item Alignment + at item Illegal Instruction + at item External Interrupt + at item D-TLB Miss + at item I-TLB Miss + at item Range + at item System Call + at item Floating Point + at item Trap + + at end itemize + + at subsection Interrupt Levels + +There are only two levels: interrupts enabled and interrupts disabled. + + at subsection Interrupt Stack + +OpenRISC RTEMS port uses RTEMS SW interrupt stack. +The stack for interrupts is allocated during interrupt driver initilization. +When an interrup entered, the _ISR_Handler routine is resposible for +switching from the interrupted task stack to RTEMS SW interrupt stack. + + at section Default Fatal Error Processing + +The default fatal error handler for this architecture performs the +following actions: + + at itemize @bullet + at item disables operating system supported interrupts (IRQ), + at item places the error code in @code{r0}, and + at item executes an infinite loop to simulate a halt processor instruction. + at end itemize From joel at rtems.org Wed Aug 20 22:00:19 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 20 Aug 2014 17:00:19 -0500 Subject: [rtems commit] mpc55xx/misc/flash_support.c: Properly flush cache when writing. Message-ID: <20140820220019.41C827006BA@git.rtems.org> Module: rtems Branch: master Commit: dc661c87e1d8cda26330016976c4416805c65c7c Changeset: http://git.rtems.org/rtems/commit/?id=dc661c87e1d8cda26330016976c4416805c65c7c Author: Peter Dufault Date: Wed Aug 20 17:08:23 2014 -0500 mpc55xx/misc/flash_support.c: Properly flush cache when writing. Also cleanup: * Remove un-needed interrupt disables. * Address errata "e989: FLASH: Disable Prefetch during programming and erase" * Use RTEMS_ARRAY_SIZE() macro instead of own macro. --- .../libcpu/powerpc/mpc55xx/misc/flash_support.c | 85 +++++++++----------- 1 files changed, 39 insertions(+), 46 deletions(-) diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c index 17c4e3f..b286b51 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c +++ b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c @@ -135,8 +135,6 @@ range_set( *p_bits = bits; } -#define N(ARG) (sizeof(ARG)/sizeof(ARG[0])) - /** Return the size of the on-chip flash * verifying that this is a device that we know about. * @return 0 for OK, non-zero for error: @@ -207,7 +205,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) union LMLR_tag lmlr; union SLMLR_tag slmlr; union HLR_tag hlr; - rtems_interrupt_level level; /* If we're already locked return. */ @@ -217,7 +214,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) /* Do we have to lock something in the low or mid block? */ - rtems_interrupt_disable(level); lmlr = FLASH.LMLR; if ((lsel || msel) && (lmlr.B.LME == 0)) { union LMLR_tag lmlr_unlock; @@ -228,7 +224,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) if (lmlr.B.LLOCK != lmlr_unlock.B.LLOCK || lmlr.B.MLOCK != lmlr_unlock.B.MLOCK) { if (p_locked == 0) { - rtems_interrupt_enable(level); return MPC55XX_FLASH_LOCK_ERR; } else { *p_locked = 1; @@ -237,9 +232,7 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) FLASH.LMLR = lmlr_unlock; } } - rtems_interrupt_enable(level); - rtems_interrupt_disable(level); slmlr = FLASH.SLMLR; if ((lsel || msel) && (slmlr.B.SLE == 0)) { union SLMLR_tag slmlr_unlock; @@ -250,7 +243,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) if (slmlr.B.SLLOCK != slmlr_unlock.B.SLLOCK || slmlr.B.SMLOCK != slmlr_unlock.B.SMLOCK) { if (p_locked == 0) { - rtems_interrupt_enable(level); return MPC55XX_FLASH_LOCK_ERR; } else { *p_locked = 1; @@ -259,11 +251,9 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) FLASH.SLMLR = slmlr_unlock; } } - rtems_interrupt_enable(level); /* Do we have to unlock something in the high block? */ - rtems_interrupt_disable(level); hlr = FLASH.HLR; if (hbsel && (hlr.B.HBE == 0)) { union HLR_tag hlr_unlock; @@ -272,7 +262,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) if (hlr.B.HBLOCK != hlr_unlock.B.HBLOCK) { if (p_locked == 0) { return MPC55XX_FLASH_LOCK_ERR; - rtems_interrupt_enable(level); } else { *p_locked = 1; } @@ -280,7 +269,6 @@ unlock_once(int lsel, int msel, int hbsel, int *p_locked) FLASH.HLR = hlr_unlock; } } - rtems_interrupt_enable(level); return 0; } @@ -398,24 +386,25 @@ mpc55xx_flash_copy_op( { uint32_t udest, usrc, flash_size; int r; - int peg; /* Program or Erase Good - Did it work? */ + int peg; /* Program or Erase Good - Did it work? */ - int lsel; /* Low block select bits. */ - int msel; /* Mid block select bits. */ - int hbsel; /* High block select bits. */ + int lsel; /* Low block select bits. */ + int msel; /* Mid block select bits. */ + int hbsel; /* High block select bits. */ - int s_lsel; /* Source Low block select bits. */ - int s_msel; /* Source Mid block select bits. */ - int s_hbsel; /* Source High block select bits. */ + int s_lsel; /* Source Low block select bits. */ + int s_msel; /* Source Mid block select bits. */ + int s_hbsel; /* Source High block select bits. */ int unlocked = 0; int *p_unlocked; int i; - int nwords; /* The number of 32 bit words to write. */ - volatile uint32_t *flash; /* Where the flash is mapped in. */ - volatile uint32_t *memory; /* What to copy into flash. */ - uint32_t offset; /* Where the FLASH is mapped into memory. */ - rtems_interrupt_level level; + int nwords; /* The number of 32 bit words to write. */ + volatile uint32_t *flash; /* Where the flash is mapped in. */ + volatile uint32_t *memory; /* What to copy into flash. */ + const void *flashing_from; /* Where we are flahsing from. + * "const" is to match invalidate cache function signature. */ + uint32_t offset; /* Where the FLASH is mapped into memory. */ if ( (r = mpc55xx_flash_size(&flash_size))) { return r; @@ -461,13 +450,13 @@ mpc55xx_flash_copy_op( /* Set up the bit masks for the blocks to program or erase. */ - range_set(udest, udest + nbytes, &lsel, lsel_ranges, N( lsel_ranges)); - range_set(udest, udest + nbytes, &msel, msel_ranges, N( msel_ranges)); - range_set(udest, udest + nbytes, &hbsel, hbsel_ranges, N(hbsel_ranges)); + range_set(udest, udest + nbytes, &lsel, lsel_ranges, RTEMS_ARRAY_SIZE( lsel_ranges)); + range_set(udest, udest + nbytes, &msel, msel_ranges, RTEMS_ARRAY_SIZE( msel_ranges)); + range_set(udest, udest + nbytes, &hbsel, hbsel_ranges, RTEMS_ARRAY_SIZE(hbsel_ranges)); - range_set(usrc, usrc + nbytes, &s_lsel, lsel_ranges, N( lsel_ranges)); - range_set(usrc, usrc + nbytes, &s_msel, msel_ranges, N( msel_ranges)); - range_set(usrc, usrc + nbytes, &s_hbsel, hbsel_ranges, N(hbsel_ranges)); + range_set(usrc, usrc + nbytes, &s_lsel, lsel_ranges, RTEMS_ARRAY_SIZE( lsel_ranges)); + range_set(usrc, usrc + nbytes, &s_msel, msel_ranges, RTEMS_ARRAY_SIZE( msel_ranges)); + range_set(usrc, usrc + nbytes, &s_hbsel, hbsel_ranges, RTEMS_ARRAY_SIZE(hbsel_ranges)); /* Are we attempting overlapping flash? */ @@ -481,33 +470,39 @@ mpc55xx_flash_copy_op( /* In the following sections any "Step N" notes refer to * the steps in "13.4.2.3 Flash Programming" in the reference manual. - * XXX Do parts of this neeed to be protected by interrupt locks? */ if (opmask & MPC55XX_FLASH_ERASE) { /* Erase. */ + uint32_t flash_biucr_r; if ( (r = unlock_once(lsel, msel, hbsel, p_unlocked)) ) { return r; } - rtems_interrupt_disable(level); + /* Per errata "e989: FLASH: Disable Prefetch during programming and erase" */ + flash_biucr_r = FLASH.BIUCR.R; + FLASH.BIUCR.B.PFLIM = 0; + + FLASH.MCR.B.ESUS = 0; /* Be sure ESUS is clear. */ + FLASH.MCR.B.ERS = 1; /* Step 1: Select erase. */ FLASH.LMSR.B.LSEL = lsel; /* Step 2: Select blocks to be erased. */ FLASH.LMSR.B.MSEL = msel; FLASH.HSR.B.HBSEL = hbsel; - flash[0] = 1; /* Step 3: Write to any address in the flash + flash[0] = 0xffffffff; /* Step 3: Write to any address in the flash * (the "erase interlock write)". */ + rtems_cache_flush_multiple_data_lines(flash, sizeof(flash[0])); + FLASH.MCR.B.EHV = 1; /* Step 4: Enable high V to start erase. */ - rtems_interrupt_enable(level); while (FLASH.MCR.B.DONE == 0) { /* Step 5: Wait until done. */ } - rtems_interrupt_disable(level); peg = FLASH.MCR.B.PEG; /* Save result. */ FLASH.MCR.B.EHV = 0; /* Disable high voltage. */ FLASH.MCR.B.ERS = 0; /* De-select erase. */ - rtems_interrupt_enable(level); + FLASH.BIUCR.R = flash_biucr_r; + if (peg == 0) { return MPC55XX_FLASH_ERASE_ERR; /* Flash erase failed. */ } @@ -534,9 +529,7 @@ mpc55xx_flash_copy_op( } FLASH.MCR.B.PGM = 1; /* Step 1 */ - rtems_interrupt_disable(level); - - for (i = 0; i < nwords; i += 2) { + for (flashing_from = (const void *)flash, i = 0; i < nwords; i += 2) { flash[i] = memory[i]; /* Step 2 */ flash[i + 1] = memory[i + 1]; /* Always program in min 64 bits. */ @@ -548,45 +541,45 @@ mpc55xx_flash_copy_op( chunk++; if (chunk == 4) { /* Collected 4 64-bits for a 256 bit chunk. */ + + rtems_cache_flush_multiple_data_lines(flashing_from, 32); /* Flush cache. */ + FLASH.MCR.B.EHV = 1; /* Step 4: Enable high V. */ - rtems_interrupt_enable(level); while (FLASH.MCR.B.DONE == 0) { /* Step 5: Wait until done. */ } - rtems_interrupt_disable(level); peg = FLASH.MCR.B.PEG; /* Step 6: Save result. */ FLASH.MCR.B.EHV = 0; /* Step 7: Disable high V. */ if (peg == 0) { FLASH.MCR.B.PGM = 0; - rtems_interrupt_enable(level); if (p_fail) { *p_fail = (uint32_t)(flash + i); } return MPC55XX_FLASH_PROGRAM_ERR; /* Programming failed. */ } chunk = 0; /* Reset chunk counter. */ + flashing_from = (const void *)(flash + i); } /* Step 8: Back to step 2. */ } if (!chunk) { FLASH.MCR.B.PGM = 0; - rtems_interrupt_enable(level); } else { /* If there is anything left in that last chunk flush it out: */ + + rtems_cache_flush_multiple_data_lines(flashing_from, chunk * 8); + FLASH.MCR.B.EHV = 1; - rtems_interrupt_enable(level); while (FLASH.MCR.B.DONE == 0) { /* Wait until done. */ } - rtems_interrupt_disable(level); peg = FLASH.MCR.B.PEG; /* Save result. */ FLASH.MCR.B.EHV = 0; /* Disable high voltage. */ FLASH.MCR.B.PGM = 0; - rtems_interrupt_enable(level); if (peg == 0) { if (p_fail) { From joel at rtems.org Thu Aug 21 13:33:42 2014 From: joel at rtems.org (Joel Sherrill) Date: Thu, 21 Aug 2014 08:33:42 -0500 Subject: [rtems commit] Add configuration to detect toolset has sigaltstack() prototype Message-ID: <20140821133342.530957006BA@git.rtems.org> Module: rtems Branch: master Commit: 57871880b203d1225065640dbe8c16aa6d0f3c62 Changeset: http://git.rtems.org/rtems/commit/?id=57871880b203d1225065640dbe8c16aa6d0f3c62 Author: Joel Sherrill Date: Wed Aug 20 18:47:02 2014 -0500 Add configuration to detect toolset has sigaltstack() prototype --- cpukit/configure.ac | 12 ++++++++++++ cpukit/libnetworking/rtems/rtems_bsdnet_internal.h | 10 ++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/cpukit/configure.ac b/cpukit/configure.ac index 56815e2..fcf3437 100644 --- a/cpukit/configure.ac +++ b/cpukit/configure.ac @@ -116,6 +116,12 @@ RTEMS_CHECK_FUNC([pthread_getattr_np],[ #include ]) AC_CHECK_HEADERS([sys/cpuset.h]) +# This was added to newlib in August 2014 to improve conformance. +# Disable use of internal definition if it is present. +RTEMS_CHECK_FUNC([sigaltstack],[ + #define _GNU_SOURCE + #include ]) + # Mandated by POSIX, not declared in some versions of newlib. AC_CHECK_DECLS([getrusage],,,[#include sys/resource.h]) @@ -236,6 +242,12 @@ RTEMS_CPUOPT([__RTEMS_HAVE_SYS_CPUSET_H__], [1], [indicate if is present in toolset]) +## Header file differences that need to be known in .h after install +RTEMS_CPUOPT([__RTEMS_HAVE_DECL_SIGALTSTACK__], + [test x"${ac_cv_have_decl_sigaltstack}" = x"yes"], + [1], + [indicate if in toolset has sigaltstack()]) + ## This improves both the size and coverage analysis. RTEMS_CPUOPT([__RTEMS_DO_NOT_INLINE_THREAD_ENABLE_DISPATCH__], [test x"${RTEMS_DO_NOT_INLINE_THREAD_ENABLE_DISPATCH}" = x"1"], diff --git a/cpukit/libnetworking/rtems/rtems_bsdnet_internal.h b/cpukit/libnetworking/rtems/rtems_bsdnet_internal.h index 05e54b2..567cc8a 100644 --- a/cpukit/libnetworking/rtems/rtems_bsdnet_internal.h +++ b/cpukit/libnetworking/rtems/rtems_bsdnet_internal.h @@ -83,11 +83,13 @@ typedef quad_t * qaddr_t; typedef void __sighandler_t(int); typedef __sighandler_t *sig_t; /* type of pointer to a signal function */ #define NSIG 32 -struct sigaltstack { - char *ss_sp; /* signal stack base */ - int ss_size; /* signal stack length */ - int ss_flags; /* SS_DISABLE and/or SS_ONSTACK */ +#if (__RTEMS_HAVE_DECL_SIGALTSTACK__ == 0) +struct sigaltstack { + char *ss_sp; /* signal stack base */ + int ss_size; /* signal stack length */ + int ss_flags; /* SS_DISABLE and/or SS_ONSTACK */ }; +#endif #ifdef _KERNEL typedef int boolean_t; From joel at rtems.org Thu Aug 21 13:59:27 2014 From: joel at rtems.org (Joel Sherrill) Date: Thu, 21 Aug 2014 08:59:27 -0500 Subject: [rtems commit] bsp/tms570: implemented support functions to satisfy complete tests build requirements . Message-ID: <20140821135928.0EE167006BA@git.rtems.org> Module: rtems Branch: master Commit: 46265063e3300ab613c03151d7aaade580b10554 Changeset: http://git.rtems.org/rtems/commit/?id=46265063e3300ab613c03151d7aaade580b10554 Author: Pavel Pisa Date: Thu Aug 21 08:38:24 2014 -0500 bsp/tms570: implemented support functions to satisfy complete tests build requirements. This patch enables to build all RTEMS tests for tms570ls3137_hdk_sdram BSP variant in in default build. Debug build with --enable-rtems-debug set has succeed for samples subset of tests as well. --- c/src/lib/libbsp/arm/tms570/Makefile.am | 9 +++ .../lib/libbsp/arm/tms570/clock/benchmark_timer.c | 61 +++++++++++++++++++ c/src/lib/libbsp/arm/tms570/clock/clock.c | 4 +- .../lib/libbsp/arm/tms570/include/system-clocks.h | 62 ++++++++++++++++++++ .../arm/tms570/make/custom/tms570ls3137_hdk.cfg | 2 +- .../tms570/make/custom/tms570ls3137_hdk_intram.cfg | 2 +- .../tms570/make/custom/tms570ls3137_hdk_sdram.cfg | 2 +- c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c | 44 ++++++++++++++ c/src/lib/libbsp/arm/tms570/preinstall.am | 4 + 9 files changed, 186 insertions(+), 4 deletions(-) diff --git a/c/src/lib/libbsp/arm/tms570/Makefile.am b/c/src/lib/libbsp/arm/tms570/Makefile.am index 02d7b66..e66cf79 100644 --- a/c/src/lib/libbsp/arm/tms570/Makefile.am +++ b/c/src/lib/libbsp/arm/tms570/Makefile.am @@ -39,6 +39,7 @@ include_bsp_HEADERS += include/tms570-rti.h include_bsp_HEADERS += include/tms570-vim.h include_bsp_HEADERS += include/tms570-pom.h include_bsp_HEADERS += include/tms570-sci-driver.h +include_bsp_HEADERS += include/system-clocks.h include_HEADERS += ../../shared/include/tm27.h @@ -78,6 +79,7 @@ libbsp_a_SOURCES += ../../shared/bsppredriverhook.c libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c libbsp_a_SOURCES += ../../shared/sbrk.c libbsp_a_SOURCES += ../../shared/src/stackalloc.c +libbsp_a_SOURCES += ../../shared/cpucounterdiff.c # Startup libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S @@ -105,6 +107,7 @@ libbsp_a_SOURCES += console/tms570-sci.c # Clock libbsp_a_SOURCES += ../../shared/clockdrv_shell.h libbsp_a_SOURCES += clock/clock.c +libbsp_a_SOURCES += clock/benchmark_timer.c # RTC @@ -115,9 +118,15 @@ libbsp_a_SOURCES += clock/clock.c # Benchmark Timer # Misc +libbsp_a_SOURCES += misc/cpucounterread.c # Watchdog +# Cache +libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c +libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h +libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include + # Start hooks libbsp_a_SOURCES += startup/bspstarthooks.c diff --git a/c/src/lib/libbsp/arm/tms570/clock/benchmark_timer.c b/c/src/lib/libbsp/arm/tms570/clock/benchmark_timer.c new file mode 100644 index 0000000..b45f0f4 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/clock/benchmark_timer.c @@ -0,0 +1,61 @@ +/** + * @file benchmark_timer.c + * + * @ingroup tms570 + * + * @brief clock functions definitions. + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#include +#include +#include +#include +#include + +bool benchmark_timer_find_average_overhead = false; + +static uint32_t benchmark_timer_base; + +void benchmark_timer_initialize(void) +{ + benchmark_timer_base = _CPU_Counter_read(); +} + +uint32_t benchmark_timer_read(void) +{ + uint32_t delta = _CPU_Counter_read() - benchmark_timer_base; + + if (benchmark_timer_find_average_overhead) { + return delta; + } else { + /* TODO check on hardware */ + if (delta > 74) { + return delta - 74; + } else { + return 0; + } + } +} + +void benchmark_timer_disable_subtracting_average_overhead(bool find_average_overhead ) +{ + benchmark_timer_find_average_overhead = find_average_overhead; +} diff --git a/c/src/lib/libbsp/arm/tms570/clock/clock.c b/c/src/lib/libbsp/arm/tms570/clock/clock.c index 2a8bb5f..4dba949 100644 --- a/c/src/lib/libbsp/arm/tms570/clock/clock.c +++ b/c/src/lib/libbsp/arm/tms570/clock/clock.c @@ -29,6 +29,7 @@ #include #include #include +#include /** * holds HW counter value since last interrupt event @@ -49,6 +50,8 @@ static void tms570_clock_driver_support_initialize_hardware( void ) uint32_t microsec_per_tick = rtems_configuration_get_microseconds_per_tick(); + rtems_counter_initialize_converter(BSP_PLL_OUT_CLOCK); + /* Hardware specific initialize */ TMS570_RTI.RTIGCTRL = 0; TMS570_RTI.RTICPUC0 = BSP_PLL_OUT_CLOCK /1000000 / 2; /* prescaler */ @@ -80,7 +83,6 @@ static void tms570_clock_driver_support_at_tick( void ) { TMS570_RTI.RTIINTFLAG = 0x00000001; tms570_rti_last_tick_fcr0 = TMS570_RTI.RTICOMP0 - TMS570_RTI.RTIUDCP0; - /* TMS570_RTI.RTICOMP0 += 1000; */ } /** diff --git a/c/src/lib/libbsp/arm/tms570/include/system-clocks.h b/c/src/lib/libbsp/arm/tms570/include/system-clocks.h new file mode 100644 index 0000000..d441ec4 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/system-clocks.h @@ -0,0 +1,62 @@ +/** + * @file benchmark_timer.c + * + * @ingroup tms570 + * + * @brief System clocks. + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H +#define LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup tms570_clock System Clocks + * + * @ingroup tms570 + * + * @brief System clocks. + * + * @{ + */ + +/** + * @brief Returns current standard timer value in microseconds. + * + * This function uses RTI module free running counter 0 used + * which is used as system tick timebase as well. + */ +static inline unsigned tms570_timer(void) +{ + uint32_t actual_fcr0 = TMS570_RTI.RTIFRC0; + return actual_fcr0; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H */ diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg index eb4a65f..e90414a 100644 --- a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk.cfg @@ -8,7 +8,7 @@ RTEMS_CPU = arm CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian -CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +CFLAGS_OPTIMIZE_V = -O2 -ggdb BINEXT?=.bin # This defines the operations performed on the linked executable. diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg index eb4a65f..e90414a 100644 --- a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram.cfg @@ -8,7 +8,7 @@ RTEMS_CPU = arm CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian -CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +CFLAGS_OPTIMIZE_V = -O2 -ggdb BINEXT?=.bin # This defines the operations performed on the linked executable. diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg index eb4a65f..e90414a 100644 --- a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_sdram.cfg @@ -8,7 +8,7 @@ RTEMS_CPU = arm CPU_CFLAGS = -march=armv7-r -mthumb -mbig-endian -CFLAGS_OPTIMIZE_V = -O2 -ggdb3 -DNDEBUG +CFLAGS_OPTIMIZE_V = -O2 -ggdb BINEXT?=.bin # This defines the operations performed on the linked executable. diff --git a/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c b/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c new file mode 100644 index 0000000..f25380c --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c @@ -0,0 +1,44 @@ +/** + * @file + * + * @ingroup tms570_clocks + * + * @brief System clocks. + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#include +#include + + +/** + * @brief returns the actual value of Cortex-R cycle counter register + * + * The register is incremented at each core clock period + * + * @retval x actual core clock counter value + * + */ +CPU_Counter_ticks _CPU_Counter_read(void) +{ + uint32_t ticks; + asm volatile ("mrc p15, 0, %0, c9, c13, 0\n": "=r" (ticks)); + return ticks; +} diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am b/c/src/lib/libbsp/arm/tms570/preinstall.am index 81dbad1..d7ac628 100644 --- a/c/src/lib/libbsp/arm/tms570/preinstall.am +++ b/c/src/lib/libbsp/arm/tms570/preinstall.am @@ -109,6 +109,10 @@ $(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h: include/tms570-sci-driver.h $(PROJEC $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570-sci-driver.h +$(PROJECT_INCLUDE)/bsp/system-clocks.h: include/system-clocks.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/system-clocks.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/system-clocks.h + $(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h From joel at rtems.org Thu Aug 21 15:47:33 2014 From: joel at rtems.org (Joel Sherrill) Date: Thu, 21 Aug 2014 10:47:33 -0500 Subject: [rtems commit] bsp/tms570: disable huge memory demanding tests for internal RAM build variant. Message-ID: <20140821154733.988F37006BA@git.rtems.org> Module: rtems Branch: master Commit: 66f1ca64c8eda561bc16cb14bd097f4c0778127b Changeset: http://git.rtems.org/rtems/commit/?id=66f1ca64c8eda561bc16cb14bd097f4c0778127b Author: Pavel Pisa Date: Thu Aug 21 09:57:47 2014 -0500 bsp/tms570: disable huge memory demanding tests for internal RAM build variant. BSP completes build with tests and debug enabled for all three variants now tms570ls3137_hdk tms570ls3137_hdk_intram tms570ls3137_hdk_sdram Even that all enabled tests builds for internal RAM variant, many of them are expected to fail on hardware because whole tests including code, data and runtime work area demands has to fit into 256 kB of RAM. --- .../make/custom/tms570ls3137_hdk-testsuite.tcfg | 13 ----------- .../custom/tms570ls3137_hdk_intram-testsuite.tcfg | 23 ++++++++++++++++++++ 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg index 6f722bc..b79994e 100644 --- a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk-testsuite.tcfg @@ -4,16 +4,3 @@ # Format is one line per test that is _NOT_ built. # -flashdisk01 -utf8proc01 -spstkalloc02 -fsdosfsname01 -jffs2_fserror -jffs2_fslink -jffs2_fspatheval -jffs2_fspermission -jffs2_fsrdwr -jffs2_fssymlink -jffs2_fstime -pppd -mghttpd01 diff --git a/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram-testsuite.tcfg b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram-testsuite.tcfg new file mode 100644 index 0000000..f4f00e8 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/make/custom/tms570ls3137_hdk_intram-testsuite.tcfg @@ -0,0 +1,23 @@ +# +# tms570ls3137 RTEMS Test Database. +# +# Format is one line per test that is _NOT_ built. +# + +fileio +iostream +pppd +loopback +syscall01 +utf8proc01 +monitor02 +mghttpd01 +ftp01 +fsdosfsname01 +jffs2_fserror +jffs2_fslink +jffs2_fspatheval +jffs2_fspermission +jffs2_fsrdwr +jffs2_fssymlink +jffs2_fstime From sebh at rtems.org Fri Aug 22 09:40:39 2014 From: sebh at rtems.org (Sebastian Huber) Date: Fri, 22 Aug 2014 04:40:39 -0500 Subject: [rtems commit] libchip/dwmac: Make PHY address user configurable Message-ID: <20140822094039.4169C7006BA@git.rtems.org> Module: rtems Branch: master Commit: d5f543296737df9b9410fccca4b7105679d0e17a Changeset: http://git.rtems.org/rtems/commit/?id=d5f543296737df9b9410fccca4b7105679d0e17a Author: Christian Mauderer Date: Fri Aug 22 08:53:10 2014 +0200 libchip/dwmac: Make PHY address user configurable This patch allows the user to configure the PHY address for the DWMAC driver by giving a pointer to a dwmac_user_cfg structure to network stack via rtems_bsdnet_ifconfig::drv_ctrl. --- c/src/lib/libbsp/arm/altera-cyclone-v/README | 28 +++++++++++++++++++++++ c/src/libchip/network/dwmac-common.h | 1 + c/src/libchip/network/dwmac.c | 31 ++++++++++++++++---------- c/src/libchip/network/dwmac.h | 10 ++++++++ 4 files changed, 58 insertions(+), 12 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/README b/c/src/lib/libbsp/arm/altera-cyclone-v/README index 0a5bc05..658fe77 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/README +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/README @@ -14,3 +14,31 @@ have to set the following options: Additional there has to be one free file descriptor to access the i2c. Set the CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS accordingly. + +Network +------- +The default PHY address can be overwritten by the application. To do this, the +drv_ctrl pointer of the rtems_bsdnet_ifconfig structure should point to a +dwmac_ifconfig_drv_ctrl object with the appropriate settings before the +rtems_bsdnet_initialize_network() is called. E.g.: + + #include + #include + + static dwmac_ifconfig_drv_ctrl drv_ctrl = { + .phy_addr = 1 + }; + + ... + + static struct rtems_bsdnet_ifconfig some_ifconfig = { + .name = RTEMS_BSP_NETWORK_DRIVER_NAME, + .attach = RTEMS_BSP_NETWORK_DRIVER_ATTACH, + .drv_ctrl = &drv_ctrl + }; + + ... + + rtems_bsdnet_initialize_network(); + +If drv_ctrl is the NULL pointer, default values will be used instead. diff --git a/c/src/libchip/network/dwmac-common.h b/c/src/libchip/network/dwmac-common.h index b61b833..05bf941 100644 --- a/c/src/libchip/network/dwmac-common.h +++ b/c/src/libchip/network/dwmac-common.h @@ -227,6 +227,7 @@ typedef struct { struct mbuf **mbuf_addr_rx; struct mbuf **mbuf_addr_tx; const dwmac_cfg *CFG; + int MDIO_BUS_ADDR; } dwmac_common_context; struct dwmac_common_core_ops { diff --git a/c/src/libchip/network/dwmac.c b/c/src/libchip/network/dwmac.c index 20d87dc..ddcf365 100644 --- a/c/src/libchip/network/dwmac.c +++ b/c/src/libchip/network/dwmac.c @@ -131,7 +131,7 @@ static int dwmac_if_mdio_read( if ( phy == -1 ) { reg_value = MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET( reg_value, - self->CFG->MDIO_BUS_ADDR + self->MDIO_BUS_ADDR ); } else { reg_value = MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET( @@ -187,7 +187,7 @@ static int dwmac_if_mdio_write( if ( phy == -1 ) { reg_value = MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET( reg_value, - self->CFG->MDIO_BUS_ADDR + self->MDIO_BUS_ADDR ); } else { reg_value = MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET( @@ -347,7 +347,7 @@ static int dwmac_if_interface_stats( void *arg ) volatile macgrp *macgrp = self->macgrp; int media = 0; bool media_ok = dwmac_if_media_status( - self, &media, self->CFG->MDIO_BUS_ADDR ); + self, &media, self->MDIO_BUS_ADDR ); uint32_t oui; uint8_t model; uint8_t revision; @@ -364,7 +364,7 @@ static int dwmac_if_interface_stats( void *arg ) printf( "\n" ); eno = dwmac_get_phy_info( self, - self->CFG->MDIO_BUS_ADDR, + self->MDIO_BUS_ADDR, &oui, &model, &revision ); @@ -372,7 +372,7 @@ static int dwmac_if_interface_stats( void *arg ) if ( eno == 0 ) { printf( "PHY 0x%02x: OUI = 0x%04" PRIX32 ", Model = 0x%02" PRIX8 ", Rev = " "0x%02" PRIX8 "\n", - self->CFG->MDIO_BUS_ADDR, + self->MDIO_BUS_ADDR, oui, model, revision ); @@ -387,7 +387,7 @@ static int dwmac_if_interface_stats( void *arg ) ); } } else { - printf( "PHY %d communication error\n", self->CFG->MDIO_BUS_ADDR ); + printf( "PHY %d communication error\n", self->MDIO_BUS_ADDR ); } printf( "\nHardware counters:\n" ); @@ -1250,7 +1250,7 @@ static int dwmac_update_autonegotiation_params( dwmac_common_context *self ) uint32_t value = self->macgrp->mac_configuration; int media = 0; bool media_ok = dwmac_if_media_status( - self, &media, self->CFG->MDIO_BUS_ADDR ); + self, &media, self->MDIO_BUS_ADDR ); if ( media_ok ) { @@ -2065,7 +2065,8 @@ static int dwmac_if_attach( const dwmac_callback_cfg *CALLBACK = &driver_config->CALLBACK; const dwmac_common_desc_ops *DESC_OPS = (const dwmac_common_desc_ops *) driver_config->DESC_OPS->ops; - + const dwmac_ifconfig_drv_ctrl *drv_ctrl = + (const dwmac_ifconfig_drv_ctrl *) bsd_config->drv_ctrl; assert( self != NULL ); assert( bsd_config != NULL ); @@ -2135,9 +2136,15 @@ static int dwmac_if_attach( } if ( eno == 0 ) { - assert( 32 >= driver_config->MDIO_BUS_ADDR ); + if ( drv_ctrl == NULL ) { + self->MDIO_BUS_ADDR = driver_config->MDIO_BUS_ADDR; + } else { + self->MDIO_BUS_ADDR = drv_ctrl->phy_addr; + } + + assert( 32 >= self->MDIO_BUS_ADDR ); - if ( 32 < driver_config->MDIO_BUS_ADDR ) { + if ( 32 < self->MDIO_BUS_ADDR ) { eno = EINVAL; } } @@ -2317,7 +2324,7 @@ int dwmac_if_read_from_phy( if ( arg != NULL ) { eno = dwmac_if_mdio_read( - self->CFG->MDIO_BUS_ADDR, + self->MDIO_BUS_ADDR, self, phy_reg, &value ); @@ -2341,7 +2348,7 @@ int dwmac_if_write_to_phy( if ( arg != NULL ) { eno = dwmac_if_mdio_write( - self->CFG->MDIO_BUS_ADDR, + self->MDIO_BUS_ADDR, self, phy_reg, val ); diff --git a/c/src/libchip/network/dwmac.h b/c/src/libchip/network/dwmac.h index 9ccf75a..8270988 100644 --- a/c/src/libchip/network/dwmac.h +++ b/c/src/libchip/network/dwmac.h @@ -31,6 +31,16 @@ extern "C" { #endif /* __cplusplus */ +/** @brief DWMAC user configuration structure. + * + * Gives the user the possibility to overwrite some configuration data by + * setting the drv_ctrl pointer of the @ref rtems_bsdnet_ifconfig structure to a + * object with this type. + */ +typedef struct { + int phy_addr; +} dwmac_ifconfig_drv_ctrl; + /** @brief PHY event. * * Data type to be used for PHY events and event sets. From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] smptests/smpcache01: Test the SMP cache manager Message-ID: <20140822110754.E4916700656@git.rtems.org> Module: rtems Branch: master Commit: 9a9ab85b45260be326d7a59f40c2d7363097eb10 Changeset: http://git.rtems.org/rtems/commit/?id=9a9ab85b45260be326d7a59f40c2d7363097eb10 Author: Daniel Cederman Date: Thu Jul 3 16:42:24 2014 +0200 smptests/smpcache01: Test the SMP cache manager Invokes SMP cache management routines under different scenarios. --- testsuites/smptests/Makefile.am | 1 + testsuites/smptests/configure.ac | 1 + testsuites/smptests/smpcache01/Makefile.am | 19 ++ testsuites/smptests/smpcache01/init.c | 291 +++++++++++++++++++++++++ testsuites/smptests/smpcache01/smpcache01.doc | 16 ++ testsuites/smptests/smpcache01/smpcache01.scn | 14 ++ 6 files changed, 342 insertions(+), 0 deletions(-) diff --git a/testsuites/smptests/Makefile.am b/testsuites/smptests/Makefile.am index a6e7209..1e72d43 100644 --- a/testsuites/smptests/Makefile.am +++ b/testsuites/smptests/Makefile.am @@ -11,6 +11,7 @@ SUBDIRS += smp08 SUBDIRS += smp09 SUBDIRS += smpaffinity01 SUBDIRS += smpatomic01 +SUBDIRS += smpcache01 SUBDIRS += smpfatal01 SUBDIRS += smpfatal02 SUBDIRS += smpfatal03 diff --git a/testsuites/smptests/configure.ac b/testsuites/smptests/configure.ac index d88b9a0..9b6d99b 100644 --- a/testsuites/smptests/configure.ac +++ b/testsuites/smptests/configure.ac @@ -66,6 +66,7 @@ smp08/Makefile smp09/Makefile smpaffinity01/Makefile smpatomic01/Makefile +smpcache01/Makefile smpfatal01/Makefile smpfatal02/Makefile smpfatal03/Makefile diff --git a/testsuites/smptests/smpcache01/Makefile.am b/testsuites/smptests/smpcache01/Makefile.am new file mode 100644 index 0000000..3b092bc --- /dev/null +++ b/testsuites/smptests/smpcache01/Makefile.am @@ -0,0 +1,19 @@ +rtems_tests_PROGRAMS = smpcache01 +smpcache01_SOURCES = init.c + +dist_rtems_tests_DATA = smpcache01.scn smpcache01.doc + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP at .cfg +include $(top_srcdir)/../automake/compile.am +include $(top_srcdir)/../automake/leaf.am + +AM_CPPFLAGS += -I$(top_srcdir)/../support/include + +LINK_OBJS = $(smpcache01_OBJECTS) +LINK_LIBS = $(smpcache01_LDLIBS) + +smpcache01$(EXEEXT): $(smpcache01_OBJECTS) $(smpcache01_DEPENDENCIES) + @rm -f smpcache01$(EXEEXT) + $(make-exe) + +include $(top_srcdir)/../automake/local.am diff --git a/testsuites/smptests/smpcache01/init.c b/testsuites/smptests/smpcache01/init.c new file mode 100644 index 0000000..dd2f9f1 --- /dev/null +++ b/testsuites/smptests/smpcache01/init.c @@ -0,0 +1,291 @@ +/* + * Copyright (c) 2014 Aeroflex Gaisler AB. All rights reserved. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include +#include +#include +#include +#include + +#include "tmacros.h" + +const char rtems_test_name[] = "SMPCACHE 1"; + +#define CPU_COUNT 32 + +#define WORKER_PRIORITY 100 + +typedef void (*Cache_manager_Function_ptr)(const void *d_addr, size_t n_bytes); + +void +_Cache_manager_Send_smp_msg( + const size_t setsize, + const cpu_set_t *set, + Cache_manager_Function_ptr func, + const void * addr, + size_t size + ); + +typedef struct { + SMP_barrier_Control barrier; + uint32_t count[CPU_COUNT]; +} test_context; + +static test_context ctx = { + .barrier = SMP_BARRIER_CONTROL_INITIALIZER, +}; + +static void test_cache_message( const void *d_addr, size_t n_bytes ) +{ + rtems_test_assert(n_bytes == 123); + rtems_test_assert(d_addr == 0); + + ctx.count[rtems_get_current_processor()]++; +} + +static void all_cache_manager_smp_functions( size_t set_size, + cpu_set_t *cpu_set ) +{ + rtems_cache_flush_multiple_data_lines_processor_set( 0, 10, set_size, + cpu_set ); + rtems_cache_invalidate_multiple_data_lines_processor_set( 0, 10, set_size, + cpu_set ); + rtems_cache_flush_entire_data_processor_set( set_size, cpu_set ); + rtems_cache_invalidate_entire_data_processor_set( set_size, cpu_set ); + rtems_cache_invalidate_entire_instruction(); + rtems_cache_invalidate_multiple_instruction_lines( 0, 10 ); +} + +static void standard_funcs_test( size_t set_size, cpu_set_t *cpu_set ) +{ + all_cache_manager_smp_functions( set_size, cpu_set ); +} + +static void standard_funcs_isrdisabled_test( size_t set_size, + cpu_set_t *cpu_set, SMP_barrier_State *bs ) +{ + ISR_Level isr_level; + + _ISR_Disable_without_giant( isr_level ); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + all_cache_manager_smp_functions( set_size, cpu_set ); + + _ISR_Enable_without_giant( isr_level ); +} + +static void standard_funcs_giant_taken_test( size_t set_size, + cpu_set_t *cpu_set, SMP_barrier_State *bs ) +{ + if ( rtems_get_current_processor() == 0) + _Giant_Acquire(); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + all_cache_manager_smp_functions( set_size, cpu_set ); + + if ( rtems_get_current_processor() == 0) + _Giant_Release(); +} + +static void test_func_test( size_t set_size, cpu_set_t *cpu_set, + SMP_barrier_State *bs ) +{ + ctx.count[rtems_get_current_processor()] = 0; + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + _Cache_manager_Send_smp_msg( set_size, cpu_set, test_cache_message, 0, 123 ); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + rtems_test_assert( ctx.count[rtems_get_current_processor()] == + rtems_get_processor_count() ); +} + +static void test_func_isrdisabled_test( size_t set_size, cpu_set_t *cpu_set, + SMP_barrier_State *bs ) +{ + ISR_Level isr_level; + + ctx.count[rtems_get_current_processor()] = 0; + _ISR_Disable_without_giant( isr_level ); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + _Cache_manager_Send_smp_msg( set_size, cpu_set, test_cache_message, 0, 123 ); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + rtems_test_assert( ctx.count[rtems_get_current_processor()] == + rtems_get_processor_count() ); + + _ISR_Enable_without_giant( isr_level ); +} + +static void test_func_giant_taken_test( size_t set_size, cpu_set_t *cpu_set, + SMP_barrier_State *bs ) +{ + ctx.count[rtems_get_current_processor()] = 0; + + if ( rtems_get_current_processor() == 0) + _Giant_Acquire(); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + _Cache_manager_Send_smp_msg( set_size, cpu_set, test_cache_message, 0, 123 ); + + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); + + rtems_test_assert( ctx.count[rtems_get_current_processor()] == + rtems_get_processor_count() ); + + if ( rtems_get_current_processor() == 0) + _Giant_Release(); +} + +static void cmlog( const char* str ) +{ + if ( rtems_get_current_processor() == 0 ) + printf( "%s", str ); +} + +static void all_tests( void ) +{ + uint32_t cpu_count = rtems_get_processor_count(); + size_t set_size = CPU_ALLOC_SIZE( rtems_get_processor_count() ); + cpu_set_t *cpu_set = CPU_ALLOC( rtems_get_processor_count() ); + SMP_barrier_State bs = SMP_BARRIER_STATE_INITIALIZER; + + /* Send message to all available CPUs */ + CPU_FILL_S( set_size, cpu_set ); + + /* Call all SMP cache manager functions */ + cmlog( "Calling all standard SMP cache functions\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + standard_funcs_test( set_size, cpu_set ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n"); + + /* Call all SMP cache manager functions with ISR disabled */ + cmlog( "Calling all standard SMP cache functions. With ISR disabled\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + standard_funcs_isrdisabled_test( set_size, cpu_set, &bs ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n" ); + + /* Call all SMP cache manager functions with core 0 holding the giant lock */ + cmlog( "Calling all standard SMP cache functions. With CPU0 holding " + "the giant lock\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + standard_funcs_giant_taken_test( set_size, cpu_set, &bs ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n"); + + /* Call a test function using SMP cache manager and verify that all + * cores invoke the function */ + cmlog( "Calling a test function using the SMP cache manager to " + "verify that all CPUs receive the SMP message\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + test_func_test( set_size, cpu_set, &bs ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n"); + + /* Call a test function using SMP cache manager and verify that all + * cores invoke the function. ISR disabled. */ + cmlog( "Calling a test function using the SMP cache manager to " + "verify that all CPUs receive the SMP message. With ISR disabled\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + test_func_isrdisabled_test( set_size, cpu_set, &bs ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n" ); + + /* Call a test function using SMP cache manager and verify that all + * cores invoke the function. Core 0 holding giant lock. */ + cmlog( "Calling a test function using the SMP cache manager to " + "verify that all CPUs receive the SMP message. With CPU0 " + "holding the giant lock\n" ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + test_func_giant_taken_test( set_size, cpu_set, &bs ); + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count ); + cmlog( "Done!\n" ); + + /* Done. Free up memory. */ + _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count); + CPU_FREE( cpu_set ); +} + +static void worker_task(rtems_task_argument arg) +{ + rtems_status_code sc; + + all_tests(); + + sc = rtems_task_suspend(RTEMS_SELF); + rtems_test_assert(sc == RTEMS_SUCCESSFUL); +} + +static void test_smp_cache_manager( void ) +{ + rtems_status_code sc; + size_t worker_index; + uint32_t cpu_count = rtems_get_processor_count(); + + for (worker_index = 1; worker_index < cpu_count; ++worker_index) { + rtems_id worker_id; + + sc = rtems_task_create( + rtems_build_name('W', 'R', 'K', '0'+worker_index), + WORKER_PRIORITY, + RTEMS_MINIMUM_STACK_SIZE, + RTEMS_DEFAULT_MODES, + RTEMS_DEFAULT_ATTRIBUTES, + &worker_id + ); + rtems_test_assert( sc == RTEMS_SUCCESSFUL ); + + sc = rtems_task_start( worker_id, worker_task, 0 ); + rtems_test_assert( sc == RTEMS_SUCCESSFUL ); + } + + all_tests(); +} + + +static void Init(rtems_task_argument arg) +{ + TEST_BEGIN(); + + test_smp_cache_manager(); + + TEST_END(); + rtems_test_exit(0); +} + +#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER +#define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER + +#define CONFIGURE_SMP_APPLICATION + +#define CONFIGURE_SMP_MAXIMUM_PROCESSORS CPU_COUNT + +#define CONFIGURE_MAXIMUM_TASKS CPU_COUNT + +#define CONFIGURE_MAXIMUM_TIMERS 1 + +#define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION + +#define CONFIGURE_RTEMS_INIT_TASKS_TABLE + +#define CONFIGURE_INIT + +#include diff --git a/testsuites/smptests/smpcache01/smpcache01.doc b/testsuites/smptests/smpcache01/smpcache01.doc new file mode 100644 index 0000000..f6041b2 --- /dev/null +++ b/testsuites/smptests/smpcache01/smpcache01.doc @@ -0,0 +1,16 @@ +This file describes the directives and concepts tested by this test set. + +test set name: smpcache01 + +directives: + + - rtems_cache_flush_multiple_data_lines_processor_set + - rtems_cache_invalidate_multiple_data_lines_processor_set + - rtems_cache_flush_entire_data_processor_set + - rtems_cache_invalidate_entire_data_processor_set + - rtems_cache_invalidate_entire_instruction + - rtems_cache_invalidate_multiple_instruction_lines + +concepts: + + - Ensure that cache related SMP messages are delivered properly. diff --git a/testsuites/smptests/smpcache01/smpcache01.scn b/testsuites/smptests/smpcache01/smpcache01.scn new file mode 100644 index 0000000..5964d3e --- /dev/null +++ b/testsuites/smptests/smpcache01/smpcache01.scn @@ -0,0 +1,14 @@ +*** BEGIN OF TEST SMPCACHE 1 *** +Calling all standard SMP cache functions +Done! +Calling all standard SMP cache functions. With ISR disabled +Done! +Calling all standard SMP cache functions. With CPU0 holding the giant lock +Done! +Calling a test function using the SMP cache manager to verify that all CPUs receive the SMP message +Done! +Calling a test function using the SMP cache manager to verify that all CPUs receive the SMP message. With ISR disabled +Done! +Calling a test function using the SMP cache manager to verify that all CPUs receive the SMP message. With CPU0 holding the giant lock +Done! +*** END OF TEST SMPCACHE 1 *** From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] score: Rename SMP broadcast message function Message-ID: <20140822110754.D9FD17006FE@git.rtems.org> Module: rtems Branch: master Commit: aed38189be6503f51d2a4f7fb234ba578a3e227e Changeset: http://git.rtems.org/rtems/commit/?id=aed38189be6503f51d2a4f7fb234ba578a3e227e Author: Daniel Cederman Date: Tue Jul 8 11:35:14 2014 +0200 score: Rename SMP broadcast message function Change message type to unsigned long to match other SMP message functions. --- cpukit/score/include/rtems/score/smpimpl.h | 4 ++-- cpukit/score/src/smp.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cpukit/score/include/rtems/score/smpimpl.h b/cpukit/score/include/rtems/score/smpimpl.h index d49f88f..cbc6428 100644 --- a/cpukit/score/include/rtems/score/smpimpl.h +++ b/cpukit/score/include/rtems/score/smpimpl.h @@ -171,8 +171,8 @@ void _SMP_Send_message( uint32_t cpu_index, unsigned long message ); * * @param [in] message is message to send */ -void _SMP_Broadcast_message( - uint32_t message +void _SMP_Send_message_broadcast( + unsigned long message ); /** diff --git a/cpukit/score/src/smp.c b/cpukit/score/src/smp.c index 7140664..09246e3 100644 --- a/cpukit/score/src/smp.c +++ b/cpukit/score/src/smp.c @@ -162,7 +162,7 @@ void _SMP_Send_message( uint32_t cpu_index, unsigned long message ) _CPU_SMP_Send_interrupt( cpu_index ); } -void _SMP_Broadcast_message( uint32_t message ) +void _SMP_Send_message_broadcast( unsigned long message ) { uint32_t cpu_count = _SMP_Get_processor_count(); uint32_t cpu_index_self = _SMP_Get_current_processor(); From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] bsp/sparc: Flush only instruction cache Message-ID: <20140822110755.0D6FD7006BA@git.rtems.org> Module: rtems Branch: master Commit: 62f373fb57a7c3d6b4bc86f59f42169a84bddf06 Changeset: http://git.rtems.org/rtems/commit/?id=62f373fb57a7c3d6b4bc86f59f42169a84bddf06 Author: Daniel Cederman Date: Mon Aug 11 10:02:13 2014 +0200 bsp/sparc: Flush only instruction cache The flush instruction on LEON flushes both the data and the instruction cache. Flushing of just the instruction cache can be done by setting the "flush instruction cache" bit in the cache control register. --- c/src/lib/libbsp/sparc/leon3/include/cache_.h | 5 ++++- c/src/lib/libbsp/sparc/leon3/include/leon.h | 5 +++++ 2 files changed, 9 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/sparc/leon3/include/cache_.h b/c/src/lib/libbsp/sparc/leon3/include/cache_.h index 70c1e2c..c781367 100644 --- a/c/src/lib/libbsp/sparc/leon3/include/cache_.h +++ b/c/src/lib/libbsp/sparc/leon3/include/cache_.h @@ -134,7 +134,10 @@ static inline void _CPU_cache_unfreeze_data(void) static inline void _CPU_cache_invalidate_entire_instruction(void) { - __asm__ volatile ("flush"); + uint32_t cache_reg = leon3_get_cache_control_register(); + + cache_reg |= LEON3_REG_CACHE_CTRL_FI; + leon3_set_cache_control_register(cache_reg); } static inline void _CPU_cache_invalidate_instruction_range( diff --git a/c/src/lib/libbsp/sparc/leon3/include/leon.h b/c/src/lib/libbsp/sparc/leon3/include/leon.h index 1fc4e28..14cbc85 100644 --- a/c/src/lib/libbsp/sparc/leon3/include/leon.h +++ b/c/src/lib/libbsp/sparc/leon3/include/leon.h @@ -86,6 +86,11 @@ extern "C" { #define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ /* 0 = no function */ +/* + * The following defines the bits in the LEON Cache Control Register. + */ +#define LEON3_REG_CACHE_CTRL_FI 0x00200000 /* Flush instruction cache */ + /* LEON3 Interrupt Controller */ extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; /* LEON3 GP Timer */ From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] score/sparc: Add comment on icache flush after trap table update Message-ID: <20140822110755.1D0C2700656@git.rtems.org> Module: rtems Branch: master Commit: bba83e5191eaed493bd619a5458ac5f22501f59b Changeset: http://git.rtems.org/rtems/commit/?id=bba83e5191eaed493bd619a5458ac5f22501f59b Author: Daniel Cederman Date: Fri Jul 11 16:09:41 2014 +0200 score/sparc: Add comment on icache flush after trap table update Changes to the trap table might be missed by other cores. If the system state is up, the other cores can be notified using SMP messages that they need to flush their icache. If the up state has not been reached there is no need to notify other cores. They will do an automatic flush of the icache just after entering the up state, but before enabling interrupts. Cache invalidation is required for both single and multiprocessor systems. --- cpukit/score/cpu/sparc/cpu.c | 17 ++++++++++++++--- 1 files changed, 14 insertions(+), 3 deletions(-) diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c index c616de4..8941bca 100644 --- a/cpukit/score/cpu/sparc/cpu.c +++ b/cpukit/score/cpu/sparc/cpu.c @@ -210,10 +210,21 @@ void _CPU_ISR_install_raw_handler( (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); - /* need to flush icache after this !!! */ - + /* + * There is no instruction cache snooping, so we need to invalidate + * the instruction cache to make sure that the processor sees the + * changes to the trap table. This step is required on both single- + * and multiprocessor systems. + * + * In a SMP configuration a change to the trap table might be + * missed by other cores. If the system state is up, the other + * cores can be notified using SMP messages that they need to + * flush their icache. If the up state has not been reached + * there is no need to notify other cores. They will do an + * automatic flush of the icache just after entering the up + * state, but before enabling interrupts. + */ rtems_cache_invalidate_entire_instruction(); - } void _CPU_ISR_install_vector( From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] score: Add SMP support to the cache manager Message-ID: <20140822110755.1429A7006E4@git.rtems.org> Module: rtems Branch: master Commit: ddbc3f8d83678313ca61d2936e6efd50b3e044b0 Changeset: http://git.rtems.org/rtems/commit/?id=ddbc3f8d83678313ca61d2936e6efd50b3e044b0 Author: Daniel Cederman Date: Fri Jul 11 16:37:56 2014 +0200 score: Add SMP support to the cache manager Adds functions that allows the user to specify which cores that should perform the cache operation. SMP messages are sent to all the specified cores and the caller waits until all cores have acknowledged that they have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is defined the instruction cache invalidation function will perform the operation on all cores using the previous method. --- c/src/lib/libbsp/sparc/leon3/include/cache_.h | 2 + c/src/lib/libcpu/shared/src/cache_manager.c | 258 ++++++++++++++++++++++++- cpukit/rtems/include/rtems/rtems/cache.h | 82 ++++++++ cpukit/score/include/rtems/score/smpimpl.h | 19 ++ 4 files changed, 355 insertions(+), 6 deletions(-) diff --git a/c/src/lib/libbsp/sparc/leon3/include/cache_.h b/c/src/lib/libbsp/sparc/leon3/include/cache_.h index c781367..ced5b6d 100644 --- a/c/src/lib/libbsp/sparc/leon3/include/cache_.h +++ b/c/src/lib/libbsp/sparc/leon3/include/cache_.h @@ -26,6 +26,8 @@ extern "C" { #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS +#define CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING + #define CPU_INSTRUCTION_CACHE_ALIGNMENT 64 #define CPU_DATA_CACHE_ALIGNMENT 64 diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c index 420a013..7dd408f 100644 --- a/c/src/lib/libcpu/shared/src/cache_manager.c +++ b/c/src/lib/libcpu/shared/src/cache_manager.c @@ -37,6 +37,214 @@ #include #include "cache_.h" +#include +#include +#include +#include + +#if defined( RTEMS_SMP ) + +typedef void (*Cache_manager_Function_ptr)(const void *d_addr, size_t n_bytes); + +typedef struct { + Chain_Node Node; + Cache_manager_Function_ptr func; + const void *addr; + size_t size; + cpu_set_t *recipients; + size_t setsize; + Atomic_Ulong done; +} Cache_manager_SMP_node; + +typedef struct { + SMP_lock_Control Lock; + Chain_Control List; +} Cache_manager_SMP_control; + +static Cache_manager_SMP_control _Cache_manager_SMP_control = { + .Lock = SMP_LOCK_INITIALIZER("cachemgr"), + .List = CHAIN_INITIALIZER_EMPTY(_Cache_manager_SMP_control.List) +}; + +void +_SMP_Cache_manager_message_handler(void) +{ + SMP_lock_Context lock_context; + Cache_manager_SMP_node *node; + Cache_manager_SMP_node *next; + uint32_t cpu_self_idx; + + _SMP_lock_ISR_disable_and_acquire( &_Cache_manager_SMP_control.Lock, + &lock_context ); + cpu_self_idx = _SMP_Get_current_processor(); + + node = (Cache_manager_SMP_node*)_Chain_First( + &_Cache_manager_SMP_control.List ); + while ( !_Chain_Is_tail( &_Cache_manager_SMP_control.List, &node->Node ) ) { + next = (Cache_manager_SMP_node*)_Chain_Next( &node->Node ); + if ( CPU_ISSET_S ( cpu_self_idx, node->setsize, node->recipients ) ) { + CPU_CLR_S ( cpu_self_idx, node->setsize, node->recipients ); + + node->func( node->addr, node->size ); + + if ( CPU_COUNT_S( node->setsize, node->recipients ) == 0 ) { + _Chain_Extract_unprotected( &node->Node ); + _Atomic_Store_ulong( &node->done, 1, ATOMIC_ORDER_RELEASE ); + } + } + node = next; + } + + _SMP_lock_Release_and_ISR_enable( &_Cache_manager_SMP_control.Lock, + &lock_context ); +} + +#if defined(CPU_DATA_CACHE_ALIGNMENT) || \ + (defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) && \ + defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING)) + +static void +_Cache_manager_Process_cache_messages( void ) +{ + unsigned long message; + Per_CPU_Control *cpu_self; + ISR_Level isr_level; + + _ISR_Disable_without_giant( isr_level ); + + cpu_self = _Per_CPU_Get(); + + message = _Atomic_Load_ulong( &cpu_self->message, ATOMIC_ORDER_RELAXED ); + + if ( message & SMP_MESSAGE_CACHE_MANAGER ) { + if ( _Atomic_Compare_exchange_ulong( &cpu_self->message, &message, + message & ~SMP_MESSAGE_CACHE_MANAGER, ATOMIC_ORDER_RELAXED, + ATOMIC_ORDER_RELAXED ) ) { + _SMP_Cache_manager_message_handler(); + } + } + + _ISR_Enable_without_giant( isr_level ); +} + +/* + * We can not make this function static as we need to access it + * from the test program. + */ +void +_Cache_manager_Send_smp_msg( + const size_t setsize, + const cpu_set_t *set, + Cache_manager_Function_ptr func, + const void * addr, + size_t size + ); + +void +_Cache_manager_Send_smp_msg( + const size_t setsize, + const cpu_set_t *set, + Cache_manager_Function_ptr func, + const void * addr, + size_t size + ) +{ + uint32_t i; + Cache_manager_SMP_node node; + size_t set_size = CPU_ALLOC_SIZE( _SMP_Get_processor_count() ); + char cpu_set_copy[set_size]; + SMP_lock_Context lock_context; + + if ( ! _System_state_Is_up( _System_state_Get() ) ) { + func( addr, size ); + return; + } + + memset( cpu_set_copy, 0, set_size ); + if( set == NULL ) { + for( i=0; i<_SMP_Get_processor_count(); ++i ) + CPU_SET_S( i, set_size, (cpu_set_t *)cpu_set_copy ); + } else { + for( i=0; i<_SMP_Get_processor_count(); ++i ) + if( CPU_ISSET_S( i, set_size, set ) ) + CPU_SET_S( i, set_size, (cpu_set_t *)cpu_set_copy ); + } + + node.func = func; + node.addr = addr; + node.size = size; + node.setsize = set_size; + node.recipients = (cpu_set_t *)cpu_set_copy; + _Atomic_Store_ulong( &node.done, 0, ATOMIC_ORDER_RELAXED ); + + + _SMP_lock_ISR_disable_and_acquire( &_Cache_manager_SMP_control.Lock, + &lock_context ); + _Chain_Prepend_unprotected( &_Cache_manager_SMP_control.List, &node.Node ); + _SMP_lock_Release_and_ISR_enable( &_Cache_manager_SMP_control.Lock, + &lock_context ); + + _SMP_Send_message_multicast( set_size, node.recipients, + SMP_MESSAGE_CACHE_MANAGER ); + + _Cache_manager_Process_cache_messages(); + + while ( !_Atomic_Load_uint( &node.done, ATOMIC_ORDER_ACQUIRE ) ); +} +#endif + +void +rtems_cache_flush_multiple_data_lines_processor_set( + const void *addr, + size_t size, + const size_t setsize, + const cpu_set_t *set +) +{ +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _Cache_manager_Send_smp_msg( setsize, set, + rtems_cache_flush_multiple_data_lines, addr, size ); +#endif +} + +void +rtems_cache_invalidate_multiple_data_lines_processor_set( + const void *addr, + size_t size, + const size_t setsize, + const cpu_set_t *set +) +{ +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _Cache_manager_Send_smp_msg( setsize, set, + rtems_cache_invalidate_multiple_data_lines, addr, size ); +#endif +} + +void +rtems_cache_flush_entire_data_processor_set( + const size_t setsize, + const cpu_set_t *set +) +{ +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _Cache_manager_Send_smp_msg( setsize, set, + (Cache_manager_Function_ptr)rtems_cache_flush_entire_data, 0, 0 ); +#endif +} + +void +rtems_cache_invalidate_entire_data_processor_set( + const size_t setsize, + const cpu_set_t *set +) +{ +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _Cache_manager_Send_smp_msg( setsize, set, + (Cache_manager_Function_ptr)rtems_cache_invalidate_entire_data, 0, 0 ); +#endif +} +#endif /* * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE @@ -219,18 +427,21 @@ rtems_cache_disable_data( void ) * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE */ + + /* * This function is responsible for performing an instruction cache * invalidate. It must determine how many cache lines need to be invalidated * and then perform the invalidations. */ -void -rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n_bytes ) + +#if !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) +static void +_invalidate_multiple_instruction_lines_no_range_functions( + const void * i_addr, + size_t n_bytes +) { -#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) -#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) - _CPU_cache_invalidate_instruction_range( i_addr, n_bytes ); -#else const void * final_address; /* @@ -249,6 +460,35 @@ rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n _CPU_cache_invalidate_1_instruction_line( i_addr ); i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT); } +} +#endif + +void +rtems_cache_invalidate_multiple_instruction_lines( + const void * i_addr, + size_t n_bytes +) +{ +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) +#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) + +#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) + _Cache_manager_Send_smp_msg( 0, 0, _CPU_cache_invalidate_instruction_range, + i_addr, n_bytes ); +#else + _CPU_cache_invalidate_instruction_range( i_addr, n_bytes ); +#endif + +#else + +#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) + _Cache_manager_Send_smp_msg( 0, 0, + _invalidate_multiple_instruction_lines_no_range_functions, i_addr, + n_bytes ); +#else + _invalidate_multiple_instruction_lines_no_range_functions( i_addr, n_bytes ); +#endif + #endif #endif } @@ -266,8 +506,14 @@ rtems_cache_invalidate_entire_instruction( void ) * Call the CPU-specific routine */ +#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) + _Cache_manager_Send_smp_msg( 0, 0, + (Cache_manager_Function_ptr)_CPU_cache_invalidate_entire_instruction, + 0, 0 ); +#else _CPU_cache_invalidate_entire_instruction(); #endif +#endif } diff --git a/cpukit/rtems/include/rtems/rtems/cache.h b/cpukit/rtems/include/rtems/rtems/cache.h index 05f6612..ce399c6 100644 --- a/cpukit/rtems/include/rtems/rtems/cache.h +++ b/cpukit/rtems/include/rtems/rtems/cache.h @@ -113,6 +113,9 @@ void rtems_cache_invalidate_multiple_data_lines( * * The cache lines covering the area are marked as invalid. A later * instruction fetch from the area will result in a load from memory. + * In SMP mode, on processors without instruction cache snooping, this + * operation will invalidate the instruction cache lines on all processors. + * It should not be called from interrupt context in such case. * * @param[in] addr The start address of the area to invalidate. * @param[in] size The size in bytes of the area to invalidate. @@ -188,6 +191,85 @@ void rtems_cache_disable_instruction( void ); */ void *rtems_cache_aligned_malloc ( size_t nbytes ); +#if defined( RTEMS_SMP ) + +/** + * @brief Flushes multiple data cache lines for a set of processors + * + * Dirty cache lines covering the area are transferred to memory. + * Depending on the cache implementation this may mark the lines as invalid. + * + * This operation should not be called from interrupt context. + * + * @param[in] addr The start address of the area to flush. + * @param[in] size The size in bytes of the area to flush. + * @param[in] setsize The size of the processor set. + * @param[in] set The target processor set. + */ +void rtems_cache_flush_multiple_data_lines_processor_set( + const void *addr, + size_t size, + const size_t setsize, + const cpu_set_t *set +); + +/** + * @brief Invalidates multiple data cache lines for a set of processors + * + * The cache lines covering the area are marked as invalid. A later read + * access in the area will load the data from memory. + * + * In case the area is not aligned on cache line boundaries, then this + * operation may destroy unrelated data. + * + * This operation should not be called from interrupt context. + * + * @param[in] addr The start address of the area to invalidate. + * @param[in] size The size in bytes of the area to invalidate. + * @param[in] setsize The size of the processor set. + * @param[in] set The target processor set. + */ +void rtems_cache_invalidate_multiple_data_lines_processor_set( + const void *addr, + size_t size, + const size_t setsize, + const cpu_set_t *set +); + +/** + * @brief Flushes the entire data cache for a set of processors + * + * This operation should not be called from interrupt context. + * + * @see rtems_cache_flush_multiple_data_lines(). + * + * @param[in] setsize The size of the processor set. + * @param[in] set The target processor set. + */ +void rtems_cache_flush_entire_data_processor_set( + const size_t setsize, + const cpu_set_t *set +); + +/** + * @brief Invalidates the entire cache for a set of processors + * + * This function is responsible for performing a data cache + * invalidate. It invalidates the entire cache for a set of + * processors. + * + * This operation should not be called from interrupt context. + * + * @param[in] setsize The size of the processor set. + * @param[in] set The target processor set. + */ +void rtems_cache_invalidate_entire_data_processor_set( + const size_t setsize, + const cpu_set_t *set +); + +#endif + /**@}*/ #ifdef __cplusplus diff --git a/cpukit/score/include/rtems/score/smpimpl.h b/cpukit/score/include/rtems/score/smpimpl.h index cbc6428..dca8a6b 100644 --- a/cpukit/score/include/rtems/score/smpimpl.h +++ b/cpukit/score/include/rtems/score/smpimpl.h @@ -21,6 +21,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -51,6 +52,13 @@ extern "C" { #define SMP_MESSAGE_TEST 0x2UL /** + * @brief SMP message to request a cache manager invocation. + * + * @see _SMP_Send_message(). + */ +#define SMP_MESSAGE_CACHE_MANAGER 0x4UL + +/** * @brief SMP fatal codes. */ typedef enum { @@ -127,6 +135,12 @@ static inline void _SMP_Set_test_message_handler( } /** + * @brief Handles cache invalidation/flush requests from a remote processor. + * + */ +void _SMP_Cache_manager_message_handler( void ); + +/** * @brief Interrupt handler for inter-processor interrupts. */ static inline void _SMP_Inter_processor_interrupt_handler( void ) @@ -148,6 +162,11 @@ static inline void _SMP_Inter_processor_interrupt_handler( void ) if ( ( message & SMP_MESSAGE_TEST ) != 0 ) { ( *_SMP_Test_message_handler )( cpu_self ); } + + if ( ( message & SMP_MESSAGE_CACHE_MANAGER ) != 0 ) { + _SMP_Cache_manager_message_handler(); + } + } } From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] score: Add function to send a SMP message to a set of CPUs Message-ID: <20140822110754.9B5A47006E4@git.rtems.org> Module: rtems Branch: master Commit: a68cc1bb10e72504a6c4169c64eb1cfc1280da67 Changeset: http://git.rtems.org/rtems/commit/?id=a68cc1bb10e72504a6c4169c64eb1cfc1280da67 Author: Daniel Cederman Date: Tue Jul 8 11:33:55 2014 +0200 score: Add function to send a SMP message to a set of CPUs --- cpukit/score/include/rtems/score/smpimpl.h | 15 +++++++++++++++ cpukit/score/src/smp.c | 16 ++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/cpukit/score/include/rtems/score/smpimpl.h b/cpukit/score/include/rtems/score/smpimpl.h index e2fee39..d49f88f 100644 --- a/cpukit/score/include/rtems/score/smpimpl.h +++ b/cpukit/score/include/rtems/score/smpimpl.h @@ -175,6 +175,21 @@ void _SMP_Broadcast_message( uint32_t message ); +/** + * @brief Sends a SMP message to a set of processors. + * + * The sending processor may be part of the set. + * + * @param[in] setsize The size of the set of target processors of the message. + * @param[in] cpus The set of target processors of the message. + * @param[in] message The message. + */ +void _SMP_Send_message_multicast( + const size_t setsize, + const cpu_set_t *cpus, + unsigned long message +); + #endif /* defined( RTEMS_SMP ) */ /** diff --git a/cpukit/score/src/smp.c b/cpukit/score/src/smp.c index f0554fe..7140664 100644 --- a/cpukit/score/src/smp.c +++ b/cpukit/score/src/smp.c @@ -177,4 +177,20 @@ void _SMP_Broadcast_message( uint32_t message ) } } +void _SMP_Send_message_multicast( + const size_t setsize, + const cpu_set_t *cpus, + unsigned long message +) +{ + uint32_t cpu_count = _SMP_Get_processor_count(); + uint32_t cpu_index; + + for ( cpu_index = 0 ; cpu_index < cpu_count ; ++cpu_index ) { + if ( CPU_ISSET_S( cpu_index, setsize, cpus ) ) { + _SMP_Send_message( cpu_index, message ); + } + } +} + SMP_Test_message_handler _SMP_Test_message_handler; From danielh at rtems.org Fri Aug 22 11:07:54 2014 From: danielh at rtems.org (Daniel Hellstrom) Date: Fri, 22 Aug 2014 06:07:54 -0500 Subject: [rtems commit] bsp/sparc: Flush icache before first time enabling interrupts Message-ID: <20140822110754.A7804700656@git.rtems.org> Module: rtems Branch: master Commit: 54f3476e2493a957efb0e30c77226d496e7fc5a1 Changeset: http://git.rtems.org/rtems/commit/?id=54f3476e2493a957efb0e30c77226d496e7fc5a1 Author: Daniel Cederman Date: Thu Jul 3 11:18:55 2014 +0200 bsp/sparc: Flush icache before first time enabling interrupts A secondary processor might miss changes done to the trap table if the instruction cache is not flushed. Once interrupts are enabled any other required cache flushes can be ordered via the cache manager. --- c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c | 9 +++++++++ cpukit/score/cpu/sparc/rtems/score/cpu.h | 4 ++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c b/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c index 567eecc..9166ad5 100644 --- a/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c +++ b/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -80,3 +81,11 @@ void _CPU_SMP_Send_interrupt(uint32_t target_processor_index) /* send interrupt to destination CPU */ LEON3_IrqCtrl_Regs->force[target_processor_index] = 1 << LEON3_MP_IRQ; } + +void _BSP_Start_multitasking( + Context_Control *heir +) +{ + _CPU_cache_invalidate_entire_instruction(); + _CPU_Context_Restart_self( heir ); +} diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index 39b7825..9c38b55 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -1203,6 +1203,10 @@ register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + void _BSP_Start_multitasking( Context_Control *heir ) + RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + #define _CPU_Start_multitasking _BSP_Start_multitasking + static inline void _CPU_SMP_Processor_event_broadcast( void ) { __asm__ volatile ( "" : : : "memory" ); From joel at rtems.org Fri Aug 22 15:16:09 2014 From: joel at rtems.org (Joel Sherrill) Date: Fri, 22 Aug 2014 10:16:09 -0500 Subject: [rtems commit] bsp/tms570: implemented and tested initialization of Cortex-R performance counters. Message-ID: <20140822151610.0CAB27006BA@git.rtems.org> Module: rtems Branch: master Commit: d13ce7553b86a5b86fb360d8fc530ddd3ceef14a Changeset: http://git.rtems.org/rtems/commit/?id=d13ce7553b86a5b86fb360d8fc530ddd3ceef14a Author: Pavel Pisa Date: Fri Aug 22 10:20:46 2014 -0500 bsp/tms570: implemented and tested initialization of Cortex-R performance counters. The code is written as BSP specific now but it should work for all Cortex-A and R based CPUs and can be moved to ARM generic place in future. StackOverflow suggested sequences of writes to the registers required to start counters is used. http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor --- c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c | 88 ++++++++++++++++++++- 1 files changed, 84 insertions(+), 4 deletions(-) diff --git a/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c b/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c index f25380c..3ce2f63 100644 --- a/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c +++ b/c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c @@ -3,7 +3,14 @@ * * @ingroup tms570_clocks * - * @brief System clocks. + * @brief Cortex-R performace counters + * + * The counters setup functions are these which has been suggested + * on StackOverflow + * + * Code is probably for use on Cortex-A without modifications as well. + * + * http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor */ /* @@ -14,9 +21,6 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others - * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.org/license/LICENSE. @@ -27,6 +31,79 @@ #include #include +static int cpu_counter_initialized; + + +/** + * @brief set mode of Cortex-R performance counters + * + * Based on example found on http://stackoverflow.com + * + * @param[in] do_reset if set, values of the counters are reset + * @param[in] enable_divider if set, CCNT counts clocks divided by 64 + * @retval Void + */ +static inline void _CPU_Counter_init_perfcounters( + int32_t do_reset, + int32_t enable_divider +) +{ + /* in general enable all counters (including cycle counter) */ + int32_t value = 1; + + /* peform reset */ + if (do_reset) + { + value |= 2; /* reset all counters to zero */ + value |= 4; /* reset cycle counter to zero */ + } + + if (enable_divider) + value |= 8; /* enable "by 64" divider for CCNT */ + + value |= 16; + + /* program the performance-counter control-register */ + asm volatile ("mcr p15, 0, %0, c9, c12, 0\t\n" :: "r"(value)); + + /* enable all counters */ + asm volatile ("mcr p15, 0, %0, c9, c12, 1\t\n" :: "r"(0x8000000f)); + + /* clear overflows */ + asm volatile ("mcr p15, 0, %0, c9, c12, 3\t\n" :: "r"(0x8000000f)); +} + +/** + * @brief initialize Cortex-R performance counters subsystem + * + * Based on example found on http://stackoverflow.com + * + * @retval Void + * + */ +static void _CPU_Counter_initialize(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + + if ( cpu_counter_initialized ) { + rtems_interrupt_enable(level); + return; + } + + /* enable user-mode access to the performance counter */ + asm volatile ("mcr p15, 0, %0, c9, c14, 0\n\t" :: "r"(1)); + + /* disable counter overflow interrupts (just in case) */ + asm volatile ("mcr p15, 0, %0, c9, c14, 2\n\t" :: "r"(0x8000000f)); + + _CPU_Counter_init_perfcounters(false, false); + + cpu_counter_initialized = 1; + + rtems_interrupt_enable(level); +} /** * @brief returns the actual value of Cortex-R cycle counter register @@ -39,6 +116,9 @@ CPU_Counter_ticks _CPU_Counter_read(void) { uint32_t ticks; + if ( !cpu_counter_initialized ) { + _CPU_Counter_initialize(); + } asm volatile ("mrc p15, 0, %0, c9, c13, 0\n": "=r" (ticks)); return ticks; } From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Add printers to stage. Message-ID: <20140824234534.43ED2700A5D@git.rtems.org> Module: rtems-tools Branch: master Commit: a785e254f2360e946baa14a11fbd3f403047b880 Changeset: http://git.rtems.org/rtems-tools/commit/?id=a785e254f2360e946baa14a11fbd3f403047b880 Author: Dhananjay Balan Date: Fri Jul 12 19:25:46 2013 +0530 Add printers to stage. --- tools/gdb/python/classic_printer.py | 62 +++++++++++++++ tools/gdb/python/supercore.py | 24 ++++++ tools/gdb/python/supercore_printer.py | 140 +++++++++++++++++++++++++++++++++ 3 files changed, 226 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/classic_printer.py b/tools/gdb/python/classic_printer.py new file mode 100644 index 0000000..e9d7cb8 --- /dev/null +++ b/tools/gdb/python/classic_printer.py @@ -0,0 +1,62 @@ +# +# RTEMS Classic pretty printers for GDB +# + +class attribute_printer: + + def __init__(self, attribute): + ''' ToDo: Verify - usage of all ''' + self.attr = classic.attribute(attribute,'all') + + def to_string(self): + return gdb.Value(self.attr.to_string()) + +class semaphore_printer: + """WIP: Print a Semaphore_Control object. Print using the struct display hint + and an iterator. """ + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, semaphore): + self.semaphore = semaphore + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return self.semaphore['Object'] + elif self.count == 2: + attr = attribute(self.semaphore['attribute_set'], + 'semaphore') + return attr.to_string() + elif self.count == 3: + return self.semaphore['Core_control'] + raise StopIteration + + def __init__(self, semaphore): + self.semaphore = semaphore + + def to_string(self): + return '' + + @staticmethod + def key(i): + if i == 0: + return 'Object' + elif i == 1: + return 'attribute_set' + elif i == 2: + return 'Core_control' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.semaphore)) + + def display_hint (self): + return 'struct' diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py new file mode 100644 index 0000000..4378e12 --- /dev/null +++ b/tools/gdb/python/supercore.py @@ -0,0 +1,24 @@ +# +# RTEMS Supercore Objects +# + +import threads + +# ToDo: Move this to helper. +def tasks_printer_rotuine(wait_queue): + tasks = wait_queue.tasks() + print ' Queue: len = %d, state = %s' % (len(tasks),wait_queue.state()) + for t in range(0, len(tasks)): + print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) + +class CORE_message_queue: + '''Manage a Supercore message_queue''' + + def __init__(self, message_queue): + self.queue = message_queue + self.wait_queue = threads.queue(self.queue['Wait_queue']) + # ToDo: self.attribute ='' + # self.buffer + + def show(self): + tasks_printer_rotuine(self.wait_queue) diff --git a/tools/gdb/python/supercore_printer.py b/tools/gdb/python/supercore_printer.py new file mode 100644 index 0000000..cee9097 --- /dev/null +++ b/tools/gdb/python/supercore_printer.py @@ -0,0 +1,140 @@ +# +# RTEMS Supercore pretty printers for GDB +# +import objects +import itertools + +class id_printer: + """Print an object given the ID. Print using the struct display hint and an + iterator.""" + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, id): + self.id = id + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return int(self.id.value()) + elif self.count == 2: + return self.id.node() + elif self.count == 3: + return self.id.api() + elif self.count == 4: + return self.id._class() + elif self.count == 5: + return self.id.index() + raise StopIteration + + def __init__(self, id): + self.id = objects.ident(id) + + def to_string(self): + return '' + + @staticmethod + def key(i): + if i == 0: + return 'id' + elif i == 1: + return 'node' + elif i == 2: + return 'api' + elif i == 3: + return 'class' + elif i == 4: + return 'index' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.id)) + + def display_hint (self): + return 'struct' + +class name_printer: + """Pretty printer for an object's name. It has to guess the type as no + information is available to help determine it.""" + + def __init__(self, nameval): + self.name = objects.name(nameval) + + def to_string(self): + return str(self.name) + +class control_printer: + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, object): + self.object = object + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return self.object.node() + elif self.count == 2: + return self.object.id() + elif self.count == 3: + return self.object.name() + raise StopIteration + + def to_string(self): + return '' + + def __init__(self, object): + self.object = objects.control(object) + + @staticmethod + def key(i): + if i == 0: + return 'Node' + elif i == 1: + return 'id' + elif i == 2: + return 'name' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.object)) + + def display_hint (self): + return 'struct' + + +class state_printer: + + def __init__(self, state): + self.state = threads.state(state) + def to_string(self): + return self.state.to_string() + +class chains_printer: + + def __init__(self,chain): + self.chain = chains.control(chain) + + def to_string(self): + return "First:"+str(self.chain.first())+"\n Last:"+str(self.chain.last()) + +class node_printer: + def __init__(self, node): + self.node = chains.node(node) + + def to_string(self): + return "Node: "+str(self.node)+" Next: "+str(self.node.next())+" Prev: "+str(self.node.previous()) \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Heavy refactoring + Improved mesege queu printing. Message-ID: <20140824234534.B146B700A5B@git.rtems.org> Module: rtems-tools Branch: master Commit: b061a67742d58bedaa161970c5cae028aa440e1f Changeset: http://git.rtems.org/rtems-tools/commit/?id=b061a67742d58bedaa161970c5cae028aa440e1f Author: Dhananjay Balan Date: Fri Jul 12 19:22:37 2013 +0530 Heavy refactoring + Improved mesege queu printing. - pretty printers moved to the corresponding api_printer module - object abstractions moved to - their own name for core modules - supercore for other supercore objects - classic for classic api objects --- tools/gdb/python/__init__.py | 9 ++++++ tools/gdb/python/chains.py | 5 ++- tools/gdb/python/classic.py | 64 ++++-------------------------------------- tools/gdb/python/objects.py | 63 ----------------------------------------- tools/gdb/python/rtems.py | 18 +++++++---- tools/gdb/python/threads.py | 12 -------- 6 files changed, 30 insertions(+), 141 deletions(-) diff --git a/tools/gdb/python/__init__.py b/tools/gdb/python/__init__.py index 0664d21..dd55529 100644 --- a/tools/gdb/python/__init__.py +++ b/tools/gdb/python/__init__.py @@ -3,14 +3,23 @@ if __name__ == "__main__": import sys import os.path sys.path.append(os.path.dirname(__file__)) + import supercore import chains import rtems import classic import objects import threads + + import supercore_printer + import classic_printer + + # Needed to reload code inside gdb source command + reload(supercore) reload(chains) reload(rtems) reload(classic) reload(objects) reload(threads) + reload(supercore_printer) + reload(classic_printer) print 'RTEMS GDB Support loaded' diff --git a/tools/gdb/python/chains.py b/tools/gdb/python/chains.py index d691822..0826ba9 100644 --- a/tools/gdb/python/chains.py +++ b/tools/gdb/python/chains.py @@ -32,6 +32,8 @@ class node: return self.node_val.cast(nodetype) return None + def to_string(self): + return self.node_val['next'] + "Prev: "+self.node_val['previous'] class control: """Manage the Chain_Control.""" @@ -44,4 +46,5 @@ class control: return t def last(self): - return node(self.ctrl['first']) + return node(self.ctrl['Tail']['Node']) + diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index d3f624d..e82078d 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -11,6 +11,7 @@ import re import objects import threads +import supercore class attribute: """The Classic API attribute.""" @@ -98,63 +99,6 @@ class attribute: return True return False -class attribute_printer: - - def __init__(self, attr): - self.attr = attribute(attr,'all') - - def to_string(self): - return gdb.Value(self.attr.to_string()) - -class semaphore_printer: - """Print a Semaphore_Control object. Print using the struct display hint - and an iterator.""" - - class iterator: - """Use an iterator for each field expanded from the id so GDB output - is formatted correctly.""" - - def __init__(self, semaphore): - self.semaphore = semaphore - self.count = 0 - - def __iter__(self): - return self - - def next(self): - self.count += 1 - if self.count == 1: - return self.semaphore['Object'] - elif self.count == 2: - attr = attribute(self.semaphore['attribute_set'], - 'semaphore') - return attr.to_string() - elif self.count == 3: - return self.semaphore['Core_control'] - raise StopIteration - - def __init__(self, semaphore): - self.semaphore = semaphore - - def to_string(self): - return '' - - @staticmethod - def key(i): - if i == 0: - return 'Object' - elif i == 1: - return 'attribute_set' - elif i == 2: - return 'Core_control' - return 'bad' - - def children(self): - counter = itertools.imap (self.key, itertools.count()) - return itertools.izip (counter, self.iterator(self.semaphore)) - - def display_hint (self): - return 'struct' class semaphore: "Print a classic semaphore." @@ -225,9 +169,13 @@ class message_queue: self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], \ 'message_queue') + self.wait_queue = threads.queue( \ + self.object['message_queue']['Wait_queue']) + + self.core_control = supercore.CORE_message_queue(self.object['message_queue']) def show(self, from_tty): print ' Name:', self.object_control.name() print ' Attr:', self.attr.to_string() - + self.core_control.show() \ No newline at end of file diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 25353d7..d2ba216 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -247,71 +247,8 @@ class control: is_string = information.is_string(self._id.api(), self._id._class()) return str(name(self.object['name'], is_string)) -class id_printer: - """Print an object given the ID. Print using the struct display hint and an - iterator.""" - class iterator: - """Use an iterator for each field expanded from the id so GDB output - is formatted correctly.""" - - def __init__(self, id): - self.id = id - self.count = 0 - def __iter__(self): - return self - - def next(self): - self.count += 1 - if self.count == 1: - return int(self.id.value()) - elif self.count == 2: - return self.id.node() - elif self.count == 3: - return self.id.api() - elif self.count == 4: - return self.id._class() - elif self.count == 5: - return self.id.index() - raise StopIteration - - def __init__(self, id): - self.id = ident(id) - - def to_string(self): - return '' - - @staticmethod - def key(i): - if i == 0: - return 'id' - elif i == 1: - return 'node' - elif i == 2: - return 'api' - elif i == 3: - return 'class' - elif i == 4: - return 'index' - return 'bad' - - def children(self): - counter = itertools.imap (self.key, itertools.count()) - return itertools.izip (counter, self.iterator(self.id)) - - def display_hint (self): - return 'struct' - -class name_printer: - """Pretty printer for an object's name. It has to guess the type as no - information is available to help determine it.""" - - def __init__(self, nameval): - self.name = name(nameval) - - def to_string(self): - return gdb.Value(str(self.name)) class control_printer: diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 398f4e5..d530e6e 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -12,6 +12,10 @@ import objects import threads import classic +# ToDo: Move every printing out +import supercore_printer +import classic_printer + nesting = 0 def type_from_value(val): @@ -50,13 +54,13 @@ def lookup_function (val): return None def build_rtems_dict(): - pp_dict[re.compile('^rtems_id$')] = lambda val: objects.id_printer(val) - pp_dict[re.compile('^Objects_Id$')] = lambda val: objects.id_printer(val) - pp_dict[re.compile('^Objects_Name$')] = lambda val: objects.name_printer(val) - pp_dict[re.compile('^Objects_Control$')] = lambda val: objects.control_printer(val) - pp_dict[re.compile('^States_Control$')] = lambda val: threads.state_printer(val) - pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic.attribute_printer(val) - pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic.semaphore_printer(val) + pp_dict[re.compile('^rtems_id$')] = lambda val: supercore_printer.id_printer(val) + pp_dict[re.compile('^Objects_Id$')] = lambda val: supercore_printer.id_printer(val) + pp_dict[re.compile('^Objects_Name$')] = lambda val: supercore_printer.name_printer(val) + pp_dict[re.compile('^Objects_Control$')] = lambda val: supercore_printer.control_printer(val) + pp_dict[re.compile('^States_Control$')] = lambda val: supercore_printer.state_printer(val) + pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic_printer.attribute_printer(val) + pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic_printer.semaphore_printer(val) class rtems(gdb.Command): """Prefix command for RTEMS.""" diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py index 3debbe7..b5ac3fb 100644 --- a/tools/gdb/python/threads.py +++ b/tools/gdb/python/threads.py @@ -191,17 +191,5 @@ class queue: self.que['Queues']['Priority'][ph]))) return t - def to_string(self): - if self.fifo(): - s = 'fifo' - else: - s = 'priority' - return -class state_printer: - def __init__(self, s): - self.s = state(s) - - def to_string(self): - return self.s.to_string() From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Update readme. Message-ID: <20140824234534.C9438700A89@git.rtems.org> Module: rtems-tools Branch: master Commit: 6e75f4ebf5450154231a1f7c1c2ba97e60d2c074 Changeset: http://git.rtems.org/rtems-tools/commit/?id=6e75f4ebf5450154231a1f7c1c2ba97e60d2c074 Author: Dhananjay Balan Date: Tue Jul 9 22:39:27 2013 +0530 Update readme. Included useage instructions. --- tools/gdb/python/README.md | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 567c195..8858a4f 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -2,3 +2,5 @@ rtems-gdb ========= GDB extenstions to RTEMS. + +See [this blog post for instructions](http://dbalan.github.io/blog/2013/06/23/debugging-rtems-with-gdb/) From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Fix typo: Global timer control object name. Message-ID: <20140824234534.BE671700A25@git.rtems.org> Module: rtems-tools Branch: master Commit: 591fbf65d31d167dcab31138fc5b4da0ad5b40e6 Changeset: http://git.rtems.org/rtems-tools/commit/?id=591fbf65d31d167dcab31138fc5b4da0ad5b40e6 Author: Dhananjay Balan Date: Tue Jul 16 18:35:03 2013 +0530 Fix typo: Global timer control object name. --- tools/gdb/python/objects.py | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 23ea7be..c433039 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -14,7 +14,7 @@ class infotables: tables_types = { 'classic/tasks' : ('Thread_Control', '_RTEMS_tasks_Information'), - 'classic/timers' : ('Timer_Control', '_Timers_Information'), + 'classic/timers' : ('Timer_Control', '_Timer_Information'), 'classic/semaphores' : ('Semaphore_Control', '_Semaphore_Information'), 'classic/message_queues' : ('Message_queue_Control', '_Message_queue_Information'), 'classic/partitions' : ('Partition_Control', '_Partition_Information'), From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Initial commit Message-ID: <20140824234534.EDD0D700812@git.rtems.org> Module: rtems-tools Branch: master Commit: 911e71038cee3bcf3b9fa60a415dbda824bc3a80 Changeset: http://git.rtems.org/rtems-tools/commit/?id=911e71038cee3bcf3b9fa60a415dbda824bc3a80 Author: Dhananjay Balan Date: Mon Jun 17 08:31:09 2013 -0700 Initial commit --- tools/gdb/python/.gitignore | 35 +++++++++++++++++++++++++++++++++++ tools/gdb/python/README.md | 4 ++++ 2 files changed, 39 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/.gitignore b/tools/gdb/python/.gitignore new file mode 100644 index 0000000..d2d6f36 --- /dev/null +++ b/tools/gdb/python/.gitignore @@ -0,0 +1,35 @@ +*.py[cod] + +# C extensions +*.so + +# Packages +*.egg +*.egg-info +dist +build +eggs +parts +bin +var +sdist +develop-eggs +.installed.cfg +lib +lib64 + +# Installer logs +pip-log.txt + +# Unit test / coverage reports +.coverage +.tox +nosetests.xml + +# Translations +*.mo + +# Mr Developer +.mr.developer.cfg +.project +.pydevproject diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md new file mode 100644 index 0000000..567c195 --- /dev/null +++ b/tools/gdb/python/README.md @@ -0,0 +1,4 @@ +rtems-gdb +========= + +GDB extenstions to RTEMS. From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Fix pretty printers Message-ID: <20140824234535.21F1F700812@git.rtems.org> Module: rtems-tools Branch: master Commit: 385640641ef618061cc0d26f711a54bf95661124 Changeset: http://git.rtems.org/rtems-tools/commit/?id=385640641ef618061cc0d26f711a54bf95661124 Author: Dhananjay Balan Date: Tue Jul 9 14:55:20 2013 +0530 Fix pretty printers pretty printers for rtems_id and rtems_attribute --- tools/gdb/python/classic.py | 4 +++- tools/gdb/python/objects.py | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 99d6397..d3f624d 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -101,7 +101,7 @@ class attribute: class attribute_printer: def __init__(self, attr): - self.attr = attr + self.attr = attribute(attr,'all') def to_string(self): return gdb.Value(self.attr.to_string()) @@ -229,3 +229,5 @@ class message_queue: def show(self, from_tty): print ' Name:', self.object_control.name() print ' Attr:', self.attr.to_string() + + diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index bedf875..25353d7 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -307,8 +307,8 @@ class name_printer: """Pretty printer for an object's name. It has to guess the type as no information is available to help determine it.""" - def __init__(self, name): - self.name = name(name) + def __init__(self, nameval): + self.name = name(nameval) def to_string(self): return gdb.Value(str(self.name)) From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Object can have index from 1 to 'maximum' Message-ID: <20140824234535.39322700810@git.rtems.org> Module: rtems-tools Branch: master Commit: ce55b57c4c4d6e3a090bdfbf9053a4e931eeb078 Changeset: http://git.rtems.org/rtems-tools/commit/?id=ce55b57c4c4d6e3a090bdfbf9053a4e931eeb078 Author: Dhananjay Balan Date: Mon Jul 8 21:58:21 2013 +0530 Object can have index from 1 to 'maximum' --- tools/gdb/python/objects.py | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 16ceac1..bedf875 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -68,7 +68,7 @@ class infotables: n = self.name(api, _class) self.load(n) max = self.maximum(api, _class) - if index >= max: + if index > max: raise IndexError('object index out of range (%d)' % (max)) table_type = self.tables_types[n] expr = '(' + table_type[0] + '*)' + \ From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Update Readme. Message-ID: <20140824234535.79D4E70080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 52fc20058b33fb877e38ca9af898a24ea28069f5 Changeset: http://git.rtems.org/rtems-tools/commit/?id=52fc20058b33fb877e38ca9af898a24ea28069f5 Author: Dhananjay Balan Date: Fri Aug 23 10:13:07 2013 +0530 Update Readme. Add wiki pages, usage instructions etc. --- tools/gdb/python/README.md | 33 +++++++++++++++++++++++++++++---- 1 files changed, 29 insertions(+), 4 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 8858a4f..1fbbd3e 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -1,6 +1,31 @@ -rtems-gdb -========= +# RTEMS GDB -GDB extenstions to RTEMS. +GDB extensions to help accelarting RTEMS debugging. + +## Usage + - Clone the git repo + - Fire up gdb and use source command +``` +$ sparc-rtems4.11-gdb + +GNU gdb (GDB) 7.5.1 +Copyright (C) 2012 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "--host=x86_64-linux-gnu --target=sparc-rtems4.11". +For bug reporting instructions, please see: +. +(gdb) source path/to/clone/__init__.py +RTEMS GDB Support loaded +(gdb) +``` + +## Commands Implemented + - `rtems object` : Prints rtems objects by ID + - [rtems index subcommands](Subcommands) + +## Developer documentation +We have a document to get started with [pretty printer development](Writing-a-pretty-printer). -See [this blog post for instructions](http://dbalan.github.io/blog/2013/06/23/debugging-rtems-with-gdb/) From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Update README.md Message-ID: <20140824234535.953E3700A25@git.rtems.org> Module: rtems-tools Branch: master Commit: b5c4f41b0e46690e9629eed0db11011994eaca07 Changeset: http://git.rtems.org/rtems-tools/commit/?id=b5c4f41b0e46690e9629eed0db11011994eaca07 Author: Dhananjay Balan Date: Fri Aug 23 10:13:48 2013 +0530 Update README.md Fix indentation. --- tools/gdb/python/README.md | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 1fbbd3e..16ad8dc 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -5,6 +5,7 @@ GDB extensions to help accelarting RTEMS debugging. ## Usage - Clone the git repo - Fire up gdb and use source command + ``` $ sparc-rtems4.11-gdb From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Refactoring Message-ID: <20140824234535.150D9700814@git.rtems.org> Module: rtems-tools Branch: master Commit: 0967a1b679495f728781bd05318379024cadf5c5 Changeset: http://git.rtems.org/rtems-tools/commit/?id=0967a1b679495f728781bd05318379024cadf5c5 Author: Dhananjay Balan Date: Sat Jul 13 16:49:59 2013 +0530 Refactoring - drop _printer suffix from printer classes. --- tools/gdb/python/__init__.py | 3 +- tools/gdb/python/classic.py | 1 + tools/gdb/python/classic_printer.py | 6 ++-- tools/gdb/python/helper.py | 8 +++++ tools/gdb/python/objects.py | 51 +-------------------------------- tools/gdb/python/rtems.py | 14 ++++---- tools/gdb/python/supercore.py | 10 +----- tools/gdb/python/supercore_printer.py | 12 ++++---- 8 files changed, 30 insertions(+), 75 deletions(-) diff --git a/tools/gdb/python/__init__.py b/tools/gdb/python/__init__.py index dd55529..694eb06 100644 --- a/tools/gdb/python/__init__.py +++ b/tools/gdb/python/__init__.py @@ -13,7 +13,7 @@ if __name__ == "__main__": import supercore_printer import classic_printer - # Needed to reload code inside gdb source command + # Needed inorder to reload code from inside gdb reload(supercore) reload(chains) reload(rtems) @@ -22,4 +22,5 @@ if __name__ == "__main__": reload(threads) reload(supercore_printer) reload(classic_printer) + print 'RTEMS GDB Support loaded' diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index e82078d..9af11df 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -79,6 +79,7 @@ class attribute: self.attrtype = attrtype self.attr = attr + #ToDo: Move this out def to_string(self): s = '0x%08x,' % (self.attr) if self.attrtype != 'none': diff --git a/tools/gdb/python/classic_printer.py b/tools/gdb/python/classic_printer.py index e9d7cb8..a25d756 100644 --- a/tools/gdb/python/classic_printer.py +++ b/tools/gdb/python/classic_printer.py @@ -2,7 +2,7 @@ # RTEMS Classic pretty printers for GDB # -class attribute_printer: +class attribute: def __init__(self, attribute): ''' ToDo: Verify - usage of all ''' @@ -11,8 +11,8 @@ class attribute_printer: def to_string(self): return gdb.Value(self.attr.to_string()) -class semaphore_printer: - """WIP: Print a Semaphore_Control object. Print using the struct display hint +class semaphore: + """ToDo: Print a Semaphore_Control object. Print using the struct display hint and an iterator. """ class iterator: diff --git a/tools/gdb/python/helper.py b/tools/gdb/python/helper.py new file mode 100644 index 0000000..ec17400 --- /dev/null +++ b/tools/gdb/python/helper.py @@ -0,0 +1,8 @@ +# +# RTEMS GDB support helper routins. + +def tasks_printer_rotuine(wait_queue): + tasks = wait_queue.tasks() + print ' Queue: len = %d, state = %s' % (len(tasks),wait_queue.state()) + for t in range(0, len(tasks)): + print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) \ No newline at end of file diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index d2ba216..23ea7be 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -245,53 +245,4 @@ class control: def name(self): is_string = information.is_string(self._id.api(), self._id._class()) - return str(name(self.object['name'], is_string)) - - - - -class control_printer: - - class iterator: - """Use an iterator for each field expanded from the id so GDB output - is formatted correctly.""" - - def __init__(self, object): - self.object = object - self.count = 0 - - def __iter__(self): - return self - - def next(self): - self.count += 1 - if self.count == 1: - return self.object.node() - elif self.count == 2: - return self.object.id() - elif self.count == 3: - return self.object.name() - raise StopIteration - - def to_string(self): - return '' - - def __init__(self, object): - self.object = control(object) - - @staticmethod - def key(i): - if i == 0: - return 'Node' - elif i == 1: - return 'id' - elif i == 2: - return 'name' - return 'bad' - - def children(self): - counter = itertools.imap (self.key, itertools.count()) - return itertools.izip (counter, self.iterator(self.object)) - - def display_hint (self): - return 'struct' + return str(name(self.object['name'], is_string)) \ No newline at end of file diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index d530e6e..4622ced 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -54,13 +54,13 @@ def lookup_function (val): return None def build_rtems_dict(): - pp_dict[re.compile('^rtems_id$')] = lambda val: supercore_printer.id_printer(val) - pp_dict[re.compile('^Objects_Id$')] = lambda val: supercore_printer.id_printer(val) - pp_dict[re.compile('^Objects_Name$')] = lambda val: supercore_printer.name_printer(val) - pp_dict[re.compile('^Objects_Control$')] = lambda val: supercore_printer.control_printer(val) - pp_dict[re.compile('^States_Control$')] = lambda val: supercore_printer.state_printer(val) - pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic_printer.attribute_printer(val) - pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic_printer.semaphore_printer(val) + pp_dict[re.compile('^rtems_id$')] = lambda val: supercore_printer.id(val) + pp_dict[re.compile('^Objects_Id$')] = lambda val: supercore_printer.id(val) + pp_dict[re.compile('^Objects_Name$')] = lambda val: supercore_printer.name(val) + pp_dict[re.compile('^Objects_Control$')] = lambda val: supercore_printer.control(val) + pp_dict[re.compile('^States_Control$')] = lambda val: supercore_printer.state(val) + pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic_printer.attribute(val) + pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic_printer.semaphore(val) class rtems(gdb.Command): """Prefix command for RTEMS.""" diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py index 4378e12..7e958b1 100644 --- a/tools/gdb/python/supercore.py +++ b/tools/gdb/python/supercore.py @@ -3,13 +3,7 @@ # import threads - -# ToDo: Move this to helper. -def tasks_printer_rotuine(wait_queue): - tasks = wait_queue.tasks() - print ' Queue: len = %d, state = %s' % (len(tasks),wait_queue.state()) - for t in range(0, len(tasks)): - print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) +import helper class CORE_message_queue: '''Manage a Supercore message_queue''' @@ -21,4 +15,4 @@ class CORE_message_queue: # self.buffer def show(self): - tasks_printer_rotuine(self.wait_queue) + helper.tasks_printer_rotuine(self.wait_queue) diff --git a/tools/gdb/python/supercore_printer.py b/tools/gdb/python/supercore_printer.py index cee9097..ec1d416 100644 --- a/tools/gdb/python/supercore_printer.py +++ b/tools/gdb/python/supercore_printer.py @@ -4,7 +4,7 @@ import objects import itertools -class id_printer: +class id: """Print an object given the ID. Print using the struct display hint and an iterator.""" @@ -60,7 +60,7 @@ class id_printer: def display_hint (self): return 'struct' -class name_printer: +class name: """Pretty printer for an object's name. It has to guess the type as no information is available to help determine it.""" @@ -70,7 +70,7 @@ class name_printer: def to_string(self): return str(self.name) -class control_printer: +class control: class iterator: """Use an iterator for each field expanded from the id so GDB output @@ -117,14 +117,14 @@ class control_printer: return 'struct' -class state_printer: +class state: def __init__(self, state): self.state = threads.state(state) def to_string(self): return self.state.to_string() -class chains_printer: +class chains: def __init__(self,chain): self.chain = chains.control(chain) @@ -132,7 +132,7 @@ class chains_printer: def to_string(self): return "First:"+str(self.chain.first())+"\n Last:"+str(self.chain.last()) -class node_printer: +class node: def __init__(self, node): self.node = chains.node(node) From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Messege Queue Objects Message-ID: <20140824234534.07D58700AB8@git.rtems.org> Module: rtems-tools Branch: master Commit: f814c7629cf5c87f0262ee877116166a02241c84 Changeset: http://git.rtems.org/rtems-tools/commit/?id=f814c7629cf5c87f0262ee877116166a02241c84 Author: Dhananjay Balan Date: Mon Jul 8 22:00:48 2013 +0530 Messege Queue Objects Added intial support for printing --- tools/gdb/python/classic.py | 29 ++++++++++++++++++++++------- tools/gdb/python/rtems.py | 9 +++++---- 2 files changed, 27 insertions(+), 11 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 8748bbf..99d6397 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -36,7 +36,9 @@ class attribute: 'semaphore-pri-ceiling'], 'barrier' : ['scope', 'priority', - 'barrier'] + 'barrier'], + 'message_queue' : ['priority', + 'scope'] } masks = { @@ -64,7 +66,7 @@ class attribute: (0x00000040, 'inherit-pri')], 'semaphore-pri-ceiling' : [(0x00000000, 'no-pri-ceiling'), (0x00000080, 'pri-ceiling')], - 'barrier' : [(0x00000010, 'barrier-auto-release'), + 'barrier' : [(0x00000010, 'barrier-auto-release'), (0x00000000, 'barrier-manual-release')], 'task' : [(0x00000000, 'app-task'), (0x00008000, 'sys-task')] @@ -97,7 +99,7 @@ class attribute: return False class attribute_printer: - + def __init__(self, attr): self.attr = attr @@ -124,7 +126,7 @@ class semaphore_printer: if self.count == 1: return self.semaphore['Object'] elif self.count == 2: - attr = attribute(self.semaphore['attribute_set'], + attr = attribute(self.semaphore['attribute_set'], 'semaphore') return attr.to_string() elif self.count == 3: @@ -162,7 +164,7 @@ class semaphore: self.object = objects.information.object(self.id).dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'semaphore') - + def show(self, from_tty): print ' Name:', self.object_control.name() print ' Attr:', self.attr.to_string() @@ -202,7 +204,7 @@ class task: self.id = id; self.task = \ threads.control(objects.information.object(self.id).dereference()) - + def show(self, from_tty): print ' Name:', self.task.name() print ' State:', self.task.current_state() @@ -213,4 +215,17 @@ class task: print ' Preempt:', self.task.preemptible() print ' T Budget:', self.task.cpu_time_budget() wait_info = self.task.wait_info() - + +class message_queue: + "Print a classic messege queue" + + def __init__(self,id): + self.id = id + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.attr = attribute(self.object['attribute_set'], \ + 'message_queue') + + def show(self, from_tty): + print ' Name:', self.object_control.name() + print ' Attr:', self.attr.to_string() diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index e227c6f..398f4e5 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -72,12 +72,13 @@ class rtems_object(gdb.Command): objects = { 'classic/semaphores': lambda id: classic.semaphore(id), - 'classic/tasks': lambda id: classic.task(id) + 'classic/tasks': lambda id: classic.task(id), + 'classic/message_queues': lambda id: classic.message_queue(id) } def __init__(self): self.__doc__ = 'Display the RTEMS object given a numeric ID.' - super(rtems_object, self).__init__('rtems object', + super(rtems_object, self).__init__('rtems object', gdb.COMMAND_STATUS) def invoke(self, arg, from_tty): @@ -98,7 +99,7 @@ class rtems_object(gdb.Command): object = self.objects[objectname](id) object.show(from_tty) objects.information.invalidate() - + # # Main # @@ -107,4 +108,4 @@ build_rtems_dict() gdb.pretty_printers = [] gdb.pretty_printers.append (lookup_function) rtems() -rtems_object() +rtems_object() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Catch nonvalid indexes. Message-ID: <20140824234536.2C691700A25@git.rtems.org> Module: rtems-tools Branch: master Commit: b743d63fde73cde72ddd80f5cd654e369e7d7bf0 Changeset: http://git.rtems.org/rtems-tools/commit/?id=b743d63fde73cde72ddd80f5cd654e369e7d7bf0 Author: Dhananjay Balan Date: Fri Aug 9 18:04:37 2013 +0530 Catch nonvalid indexes. Catch IndexErrors generated while referancing non existant indexes. --- tools/gdb/python/rtems.py | 10 +++++++--- 1 files changed, 7 insertions(+), 3 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 8eb49c9..dbfd7c7 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -130,10 +130,14 @@ class rtems_semaphore(gdb.Command): except ValueError: print "error: %s is not an index" % (val) return + try: + obj = objects.information.object_return( self.api, + self._class, + index ).dereference() + except IndexError: + print "error: index %s is invalid" % (index) + return - obj = objects.information.object_return( self.api, - self._class, - int(index)).dereference() instance = classic.semaphore(obj) instance.show(from_tty) objects.information.invalidate() From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Add message_queue subcommand. Message-ID: <20140824234536.5A57A700AF5@git.rtems.org> Module: rtems-tools Branch: master Commit: 2c25dc56edf95d1d60c48070431e68a31f9865f1 Changeset: http://git.rtems.org/rtems-tools/commit/?id=2c25dc56edf95d1d60c48070431e68a31f9865f1 Author: Dhananjay Balan Date: Thu Aug 15 20:44:30 2013 +0530 Add message_queue subcommand. --- tools/gdb/python/rtems.py | 35 ++++++++++++++++++++++++++++++++++- 1 files changed, 34 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index dbfd7c7..9ae2105 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -172,6 +172,38 @@ class rtems_task(gdb.Command): instance.show(from_tty) objects.information.invalidate() +class rtems_message_queue(gdb.Command): + '''Message Queue subcommand''' + + api = 'classic' + _class = 'message_queues' + + def __init__(self): + self.__doc__ = 'Display the RTEMS message_queue by index(s)' + super(rtems_message_queue,self).__init__('rtems mqueue', gdb.COMMAND_STATUS) + + def invoke(self, arg, from_tty): + for val in arg.split(): + try: + index = int(val) + except ValueError: + print "error: %s is not an index" % (val) + return + + try: + obj = objects.information.object_return(self.api, + self._class, + index).dereference() + except IndexError: + print "error: index %s is invalid" % (index) + return + + print "Ahi" + instance = classic.message_queue(obj) + instance.show(from_tty) + objects.information.invalidate() + + # # Main # @@ -182,4 +214,5 @@ gdb.pretty_printers.append (lookup_function) rtems() rtems_object() rtems_semaphore() -rtems_task() \ No newline at end of file +rtems_task() +rtems_message_queue() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Update chains structures Message-ID: <20140824234535.4A923700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 10bcd5d4dc77a9296d458855c9385fdd82c97ac0 Changeset: http://git.rtems.org/rtems-tools/commit/?id=10bcd5d4dc77a9296d458855c9385fdd82c97ac0 Author: Dhananjay Balan Date: Mon Jun 24 09:58:59 2013 +0530 Update chains structures - Fixes chains structure parsing - Fix Semaphore node parsing --- tools/gdb/python/chains.py | 12 ++++++++---- tools/gdb/python/objects.py | 7 +++++-- tools/gdb/python/threads.py | 16 ++++++++-------- 3 files changed, 21 insertions(+), 14 deletions(-) diff --git a/tools/gdb/python/chains.py b/tools/gdb/python/chains.py index 961ca2d..d691822 100644 --- a/tools/gdb/python/chains.py +++ b/tools/gdb/python/chains.py @@ -14,15 +14,17 @@ class node: self.node_val = node_val def null(self): - return self.node_val['next'] == 0 + if not self.node_val: + return True + return False def next(self): if not self.null(): - self.node_val = self.node_val['next'].dereference() + self.node_val = self.node_val['next'] def previous(self): if not self.null(): - self.node_val = self.node_val['previous'].dereference() + self.node_val = self.node_val['previous'] def cast(self, typename): if not self.null(): @@ -30,6 +32,7 @@ class node: return self.node_val.cast(nodetype) return None + class control: """Manage the Chain_Control.""" @@ -37,7 +40,8 @@ class control: self.ctrl = ctrl def first(self): - return node(self.ctrl['first'].dereference()) + t = node(self.ctrl['Head']['Node']) + return t def last(self): return node(self.ctrl['first']) diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 22d2b2c..16ceac1 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -62,6 +62,9 @@ class infotables: api = id.api() _class = id._class() index = id.index() + return self.object_return(api, _class, index) + + def object_return(self, api, _class, index): n = self.name(api, _class) self.load(n) max = self.maximum(api, _class) @@ -96,7 +99,7 @@ class ident: { 'index': (0, 15), 'node': (16, 23), 'api': (24, 26), - 'class': (27, 31) } + 'class': (27, 31) } ] OBJECT_16_BITS = 0 @@ -147,7 +150,7 @@ class ident: 'variable_memory_pools', 'fixed_memory_pools') } - + def __init__(self, id): if type(id) != gdb.Value and type(id) != int and type(id) != unicode: raise TypeError('%s: must be gdb.Value, int, unicoded int' % (type(id))) diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py index 906cf5a..3debbe7 100644 --- a/tools/gdb/python/threads.py +++ b/tools/gdb/python/threads.py @@ -14,7 +14,6 @@ def task_chain(chain): tasks = [] node = chain.first() while not node.null(): - print node.addr tasks.append(control(node.cast('Thread_Control'))) node.next() return tasks @@ -62,7 +61,7 @@ class state: WAITING_FOR_EVENT | \ WAITING_ON_THREAD_QUEUE | \ INTERRUPTIBLE_BY_SIGNAL - + masks = { ALL_SET : 'all-set', READY : 'ready', @@ -85,7 +84,7 @@ class state: WAITING_FOR_BARRIER : 'waiting-for-barrier', WAITING_FOR_RWLOCK : 'waiting-for-rwlock' } - + def __init__(self, s): self.s = s @@ -121,16 +120,16 @@ class wait_info: def block2n(self): return task_chain(chains.control(self.info['Block2n'])) - + def queue(self): return task_chain(chains.control(self.info['queue'])) class control: - + def __init__(self, ctrl): self.ctrl = ctrl self.object = objects.control(ctrl['Object']) - + def id(self): return self.object.id() @@ -181,14 +180,15 @@ class queue: def state(self): return state(self.que['state']).to_string() - + def tasks(self): if self.fifo(): t = task_chain(chains.control(self.que['Queues']['Fifo'])) else: t = [] for ph in range(0, self.priority_headers): - t.extend(task_chain(chains.control(self.que['Queues']['Fifo']))) + t.extend(task_chain(chains.control( \ + self.que['Queues']['Priority'][ph]))) return t def to_string(self): From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Add classic barrier. Message-ID: <20140824234535.B65A770080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 8e0de06b2bc6fecf8e055361590176698d0a648b Changeset: http://git.rtems.org/rtems-tools/commit/?id=8e0de06b2bc6fecf8e055361590176698d0a648b Author: Dhananjay Balan Date: Mon Jul 29 10:43:38 2013 +0530 Add classic barrier. - Add support for classic barrier object. - Drop CORE_ from names in supercore --- tools/gdb/python/classic.py | 30 +++++++++++++++++++++++++----- tools/gdb/python/rtems.py | 3 ++- tools/gdb/python/supercore.py | 37 ++++++++++++++++++++++++++++++++++++- 3 files changed, 63 insertions(+), 7 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index e2ecfaa..617a0db 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -39,9 +39,7 @@ class attribute: 'semaphore-type', 'semaphore-pri', 'semaphore-pri-ceiling'], - 'barrier' : ['scope', - 'priority', - 'barrier'], + 'barrier' : ['barrier'], 'message_queue' : ['priority', 'scope'], 'partition' : ['scope'], @@ -149,7 +147,7 @@ class semaphore: print 'semaphore' class task: - "Print a classic tasks." + "Print a classic task" def __init__(self, id): self.id = id; @@ -179,7 +177,7 @@ class message_queue: self.wait_queue = threads.queue( \ self.object['message_queue']['Wait_queue']) - self.core_control = supercore.CORE_message_queue(self.object['message_queue']) + self.core_control = supercore.message_queue(self.object['message_queue']) def show(self, from_tty): print ' Name:', self.object_control.name() @@ -238,3 +236,25 @@ class region: helper.tasks_printer_routine(self.wait_queue) print ' Memory:' self.heap.show() + +class barrier: + '''classic barrier abstraction''' + + def __init__(self,id): + self.id = id + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.attr = attribute(self.object['attribute_set'],'barrier') + self.core_b_control = supercore.barrier_control(self.object['Barrier']) + + def show(self,from_tty): + print ' Name:',self.object_control.name() + print ' Attr:',self.attr.to_string() + + if self.attr.test('barrier','barrier-auto-release'): + max_count = self.core_b_control.max_count() + print 'Aut Count:', max_count + + print ' Waiting:',self.core_b_control.waiting_threads() + helper.tasks_printer_routine(self.core_b_control.tasks()) + diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 8738736..adab86d 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -80,7 +80,8 @@ class rtems_object(gdb.Command): 'classic/message_queues': lambda id: classic.message_queue(id), 'classic/timers' : lambda id: classic.timer(id), 'classic/partitions' : lambda id: classic.partition(id), - 'classic/regions' : lambda id: classic.region(id) + 'classic/regions' : lambda id: classic.region(id), + 'classic/barriers' : lambda id: classic.barrier(id) } def __init__(self): diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py index 073bbd0..e60813a 100644 --- a/tools/gdb/python/supercore.py +++ b/tools/gdb/python/supercore.py @@ -5,7 +5,7 @@ import threads import helper -class CORE_message_queue: +class message_queue: '''Manage a Supercore message_queue''' def __init__(self, message_queue): @@ -16,3 +16,38 @@ class CORE_message_queue: def show(self): helper.tasks_printer_routine(self.wait_queue) + +class barrier_attributes: + '''supercore bbarrier attribute''' + + def __init__(self,attr): + self.attr = attr + + def max_count(self): + c = self.attr['maximum_count'] + return c + + def discipline(self): + d = self.attr['discipline'] + return d + +class barrier_control: + '''Manage a Supercore barrier''' + + def __init__(self, barrier): + self.barrier = barrier + self.wait_queue = threads.queue(self.barrier['Wait_queue']) + self.attr = barrier_attributes(self.barrier['Attributes']) + + def waiting_threads(self): + wt = self.barrier['number_of_waiting_threads'] + return wt + + def max_count(self): + return self.attr.max_count() + + def discipline(self): + return self.attr.discipline() + + def tasks(self): + return self.wait_queue From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Barrier taks queue Message-ID: <20140824234535.D41F3700A25@git.rtems.org> Module: rtems-tools Branch: master Commit: 66d0779c33ac817c8f23a24294d617800581ca36 Changeset: http://git.rtems.org/rtems-tools/commit/?id=66d0779c33ac817c8f23a24294d617800581ca36 Author: Dhananjay Balan Date: Mon Aug 5 00:25:47 2013 +0530 Barrier taks queue Print the barrier taks queue. --- tools/gdb/python/classic.py | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 29ffab5..b919383 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -251,3 +251,4 @@ class barrier: print ' Waiting:',self.core_b_control.waiting_threads() helper.tasks_printer_routine(self.core_b_control.tasks()) + From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Catch invalid object ID. Message-ID: <20140824234536.1136D70080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 559bd50d27023ccd7d65f1c023e075fe965dcbfd Changeset: http://git.rtems.org/rtems-tools/commit/?id=559bd50d27023ccd7d65f1c023e075fe965dcbfd Author: Dhananjay Balan Date: Mon Aug 5 00:35:39 2013 +0530 Catch invalid object ID. --- tools/gdb/python/rtems.py | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index b2dc776..20f44a2 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -100,6 +100,8 @@ class rtems_object(gdb.Command): id = objects.ident(num) if not id.valid(): print 'Invalid object id' + return + print 'API:%s Class:%s Node:%d Index:%d Id:%08X' % \ (id.api(), id._class(), id.node(), id.index(), id.value()) objectname = id.api() + '/' + id._class() From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Abstraction for HEAP. Message-ID: <20140824234536.49A00700A5D@git.rtems.org> Module: rtems-tools Branch: master Commit: c3d06d531c497c665671386bc32dd18fbfac49b3 Changeset: http://git.rtems.org/rtems-tools/commit/?id=c3d06d531c497c665671386bc32dd18fbfac49b3 Author: Dhananjay Balan Date: Sun Jul 28 13:19:06 2013 +0530 Abstraction for HEAP. Heap_Control Abstraction is added. It will need some more grooming though. --- tools/gdb/python/heaps.py | 62 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 62 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/heaps.py b/tools/gdb/python/heaps.py new file mode 100644 index 0000000..4798912 --- /dev/null +++ b/tools/gdb/python/heaps.py @@ -0,0 +1,62 @@ +# +# RTEMS heap +# + +class block: + '''Abstract a heap block structure''' + + def __init__(self, blk): + self.block = blk + self.prev_size = self.block['prev_size'] + self.size_flag = self.block['size_and_flag'] + + def null(self): + if self.block: + return False + return True + + + def next(self): + if not self.null(): + self.block = self.block['next'] + + def prev(self): + if not self.null(): + self.block = self.block['prev'] + +class stats: + ''heap statistics'' + + def __init__(self,stat): + self.stat = stat + + def avail(self): + val = self.stat['size'] + return val + + def free(self): + return self.stat['free_size'] + + # ToDo : incorporate others + +def control: + '''Abstract a heap control structure''' + + def __init__(self, ctl): + self.ctl = ctl + + def first(self): + b = block(self.ctl['first_block']) + return b + + def last(self): + b = block(self.ctl['last_block']) + return b + + def free(self): + b = block(self.ctl['free_list']) + return b + + def stat(self): + st = stats(self.ctl['stats']) + return st \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Update README.md Message-ID: <20140824234536.3AF0D700A87@git.rtems.org> Module: rtems-tools Branch: master Commit: a0bf9f207ac34ddaca42e0506b3743e6f416bd85 Changeset: http://git.rtems.org/rtems-tools/commit/?id=a0bf9f207ac34ddaca42e0506b3743e6f416bd85 Author: Dhananjay Balan Date: Fri Aug 23 10:16:22 2013 +0530 Update README.md Fix Links. --- tools/gdb/python/README.md | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 16ad8dc..dbf3bda 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -25,8 +25,8 @@ RTEMS GDB Support loaded ## Commands Implemented - `rtems object` : Prints rtems objects by ID - - [rtems index subcommands](Subcommands) + - [rtems index subcommands](https://github.com/dbalan/rtems-gdb/wiki/Subcommands) ## Developer documentation -We have a document to get started with [pretty printer development](Writing-a-pretty-printer). +We have a document to get started with [pretty printer development](https://github.com/dbalan/rtems-gdb/wiki/Writing-a-pretty-printer). From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] New todo Message-ID: <20140824234536.00787700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 59c4946ba345c8d7b72e71aadc51f31cceff5354 Changeset: http://git.rtems.org/rtems-tools/commit/?id=59c4946ba345c8d7b72e71aadc51f31cceff5354 Author: Dhananjay Balan Date: Mon Jul 29 10:44:02 2013 +0530 New todo --- tools/gdb/python/README.md | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index c471cd9..6dc9b5e 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -7,3 +7,4 @@ See [this blog post for instructions](http://dbalan.github.io/blog/2013/06/23/de TODO: - classic abstractions address on id - change this to more proper hierarchy. + - Inherit from object_control class From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Intial commit. Message-ID: <20140824234535.54F5D700A87@git.rtems.org> Module: rtems-tools Branch: master Commit: 56a70aec5536a568fe302a3c84b349fcf17db2fa Changeset: http://git.rtems.org/rtems-tools/commit/?id=56a70aec5536a568fe302a3c84b349fcf17db2fa Author: Dhananjay Balan Date: Mon Jun 17 22:58:17 2013 +0530 Intial commit. Chris's intial work on the extenstions. --- tools/gdb/python/__init__.py | 16 ++ tools/gdb/python/chains.py | 43 +++++ tools/gdb/python/classic.py | 216 +++++++++++++++++++++++++ tools/gdb/python/objects.py | 357 ++++++++++++++++++++++++++++++++++++++++++ tools/gdb/python/rtems.py | 110 +++++++++++++ tools/gdb/python/threads.py | 207 ++++++++++++++++++++++++ tools/gdb/python/watchdog.py | 56 +++++++ 7 files changed, 1005 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/__init__.py b/tools/gdb/python/__init__.py new file mode 100644 index 0000000..0664d21 --- /dev/null +++ b/tools/gdb/python/__init__.py @@ -0,0 +1,16 @@ + +if __name__ == "__main__": + import sys + import os.path + sys.path.append(os.path.dirname(__file__)) + import chains + import rtems + import classic + import objects + import threads + reload(chains) + reload(rtems) + reload(classic) + reload(objects) + reload(threads) + print 'RTEMS GDB Support loaded' diff --git a/tools/gdb/python/chains.py b/tools/gdb/python/chains.py new file mode 100644 index 0000000..961ca2d --- /dev/null +++ b/tools/gdb/python/chains.py @@ -0,0 +1,43 @@ +# +# RTEMS Chains Support +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb + +class node: + """Manage the Chain_Node.""" + + def __init__(self, node_val): + self.node_val = node_val + + def null(self): + return self.node_val['next'] == 0 + + def next(self): + if not self.null(): + self.node_val = self.node_val['next'].dereference() + + def previous(self): + if not self.null(): + self.node_val = self.node_val['previous'].dereference() + + def cast(self, typename): + if not self.null(): + nodetype = gdb.lookup_type(typename) + return self.node_val.cast(nodetype) + return None + +class control: + """Manage the Chain_Control.""" + + def __init__(self, ctrl): + self.ctrl = ctrl + + def first(self): + return node(self.ctrl['first'].dereference()) + + def last(self): + return node(self.ctrl['first']) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py new file mode 100644 index 0000000..8748bbf --- /dev/null +++ b/tools/gdb/python/classic.py @@ -0,0 +1,216 @@ +# +# RTEMS Classic API Support +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb +import itertools +import re + +import objects +import threads + +class attribute: + """The Classic API attribute.""" + + groups = { + 'none' : [], + 'all' : ['scope', + 'priority', + 'fpu', + 'semaphore-type', + 'semaphore-pri', + 'semaphore-pri-ceiling', + 'barrier', + 'task'], + 'task' : ['scope', + 'priority', + 'fpu', + 'task'], + 'semaphore' : ['scope', + 'priority', + 'semaphore-type', + 'semaphore-pri', + 'semaphore-pri-ceiling'], + 'barrier' : ['scope', + 'priority', + 'barrier'] + } + + masks = { + 'scope' : 0x00000002, + 'priority' : 0x00000004, + 'fpu' : 0x00000001, + 'semaphore-type' : 0x00000030, + 'semaphore-pri' : 0x00000040, + 'semaphore-pri-ceiling' : 0x00000080, + 'barrier' : 0x00000010, + 'task' : 0x00008000 + } + + fields = { + 'scope' : [(0x00000000, 'local'), + (0x00000002, 'global')], + 'priority' : [(0x00000000, 'fifo'), + (0x00000004, 'pri')], + 'fpu' : [(0x00000000, 'no-fpu'), + (0x00000001, 'fpu')], + 'semaphore-type' : [(0x00000000, 'count-sema'), + (0x00000010, 'bin-sema'), + (0x00000020, 'simple-bin-sema')], + 'semaphore-pri' : [(0x00000000, 'no-inherit-pri'), + (0x00000040, 'inherit-pri')], + 'semaphore-pri-ceiling' : [(0x00000000, 'no-pri-ceiling'), + (0x00000080, 'pri-ceiling')], + 'barrier' : [(0x00000010, 'barrier-auto-release'), + (0x00000000, 'barrier-manual-release')], + 'task' : [(0x00000000, 'app-task'), + (0x00008000, 'sys-task')] + } + + def __init__(self, attr, attrtype = 'none'): + if attrtype not in self.groups: + raise 'invalid attribute type' + self.attrtype = attrtype + self.attr = attr + + def to_string(self): + s = '0x%08x,' % (self.attr) + if self.attrtype != 'none': + for m in self.groups[self.attrtype]: + v = self.attr & self.masks[m] + for f in self.fields[m]: + if f[0] == v: + s += f[1] + ',' + break + return s[:-1] + + def test(self, mask, value): + if self.attrtype != 'none' and \ + mask in self.groups[self.attrtype]: + v = self.masks[mask] & self.attr + for f in self.fields[mask]: + if v == f[0] and value == f[1]: + return True + return False + +class attribute_printer: + + def __init__(self, attr): + self.attr = attr + + def to_string(self): + return gdb.Value(self.attr.to_string()) + +class semaphore_printer: + """Print a Semaphore_Control object. Print using the struct display hint + and an iterator.""" + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, semaphore): + self.semaphore = semaphore + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return self.semaphore['Object'] + elif self.count == 2: + attr = attribute(self.semaphore['attribute_set'], + 'semaphore') + return attr.to_string() + elif self.count == 3: + return self.semaphore['Core_control'] + raise StopIteration + + def __init__(self, semaphore): + self.semaphore = semaphore + + def to_string(self): + return '' + + @staticmethod + def key(i): + if i == 0: + return 'Object' + elif i == 1: + return 'attribute_set' + elif i == 2: + return 'Core_control' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.semaphore)) + + def display_hint (self): + return 'struct' + +class semaphore: + "Print a classic semaphore." + + def __init__(self, id): + self.id = id; + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.attr = attribute(self.object['attribute_set'], 'semaphore') + + def show(self, from_tty): + print ' Name:', self.object_control.name() + print ' Attr:', self.attr.to_string() + if self.attr.test('semaphore-type', 'bin-sema') or \ + self.attr.test('semaphore-type', 'simple-bin-sema'): + core_mutex = self.object['Core_control']['mutex'] + locked = core_mutex['lock'] == 0 + if locked: + s = 'locked' + else: + s = 'unlocked' + print ' Lock:', s + print ' Nesting:', core_mutex['nest_count'] + print ' Blocked:', core_mutex['blocked_count'] + print ' Holder:', + holder = core_mutex['holder'] + if holder and locked: + holder = threads.control(holder.dereference()) + print holder.brief() + elif holder == 0 and locked: + print 'locked but no holder' + else: + print 'unlocked' + wait_queue = threads.queue(core_mutex['Wait_queue']) + tasks = wait_queue.tasks() + print ' Queue: len = %d, state = %s' % (len(tasks), + wait_queue.state()) + for t in range(0, len(tasks)): + print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) + else: + print 'semaphore' + +class task: + "Print a classic tasks." + + def __init__(self, id): + self.id = id; + self.task = \ + threads.control(objects.information.object(self.id).dereference()) + + def show(self, from_tty): + print ' Name:', self.task.name() + print ' State:', self.task.current_state() + print ' Current:', self.task.current_priority() + print ' Real:', self.task.real_priority() + print ' Suspends:', self.task.suspends() + print ' Post Ext:', self.task.post_task_switch_ext() + print ' Preempt:', self.task.preemptible() + print ' T Budget:', self.task.cpu_time_budget() + wait_info = self.task.wait_info() + diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py new file mode 100644 index 0000000..22d2b2c --- /dev/null +++ b/tools/gdb/python/objects.py @@ -0,0 +1,357 @@ +# +# RTEMS Objects Support +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb +import itertools +import re + +class infotables: + """Manage the object information tables.""" + + tables_types = { + 'classic/tasks' : ('Thread_Control', '_RTEMS_tasks_Information'), + 'classic/timers' : ('Timer_Control', '_Timers_Information'), + 'classic/semaphores' : ('Semaphore_Control', '_Semaphore_Information'), + 'classic/message_queues' : ('Message_queue_Control', '_Message_queue_Information'), + 'classic/partitions' : ('Partition_Control', '_Partition_Information'), + 'classic/regions' : ('Region_Control', '_Regions_Information'), + 'classic/ports' : ('Port_Control', '_Port_Information'), + 'classic/periods' : ('Period_Control', '_Period_Information'), + 'classic/extensions' : ('Extension_Control', '_Extension_Information'), + 'classic/barriers' : ('Barrier_Control', '_Barrier_Information') + } + + def __init__(self): + self.invalidate() + + def invalidate(self): + self.tables = {} + + def name(self, api, _class): + return api + '/' + _class + + def load(self, n): + if n in self.tables_types: + if n not in self.tables: + self.tables[n] = gdb.parse_and_eval(self.tables_types[n][1]) + + def get(self, api, _class): + n = self.name(api, _class) + self.load(n) + if n in self.tables: + return self.tables[n] + return None + + def maximum(self, api, _class): + n = self.name(api, _class) + self.load(n) + return int(self.tables[n]['maximum']) + + def object(self, id): + if type(id) == gdb.Value: + id = ident(id) + if type(id) == tuple: + api = id[0] + _class = id[1] + index = id[2] + else: + api = id.api() + _class = id._class() + index = id.index() + n = self.name(api, _class) + self.load(n) + max = self.maximum(api, _class) + if index >= max: + raise IndexError('object index out of range (%d)' % (max)) + table_type = self.tables_types[n] + expr = '(' + table_type[0] + '*)' + \ + table_type[1] + '.local_table[' + str(index) + ']' + return gdb.parse_and_eval(expr) + + def is_string(self, api, _class): + n = self.name(api, _class) + self.load(n) + if n in self.tables: + if self.tables[n]['is_string']: + return True + return False + +# +# Global info tables. These are global in the target. +# +information = infotables() + +class ident: + "An RTEMS object id with support for its bit fields." + + bits = [ + { 'index': (0, 15), + 'node': (0, 0), + 'api': (8, 10), + 'class': (11, 15) }, + { 'index': (0, 15), + 'node': (16, 23), + 'api': (24, 26), + 'class': (27, 31) } + ] + + OBJECT_16_BITS = 0 + OBJECT_31_BITS = 1 + + api_labels = [ + 'none', + 'internal', + 'classic', + 'posix', + 'itron' + ] + + class_labels = { + 'internal' : ('threads', + 'mutexes'), + 'classic' : ('none', + 'tasks', + 'timers', + 'semaphores', + 'message_queues', + 'partitions', + 'regions', + 'ports', + 'periods', + 'extensions', + 'barriers'), + 'posix' : ('none', + 'threads', + 'keys', + 'interrupts', + 'message_queue_fds', + 'message_queues', + 'mutexes', + 'semaphores', + 'condition_variables', + 'timers', + 'barriers', + 'spinlocks', + 'rwlocks'), + 'itron' : ('none', + 'tasks', + 'eventflags', + 'mailboxes', + 'message_buffers', + 'ports', + 'semaphores', + 'variable_memory_pools', + 'fixed_memory_pools') + } + + def __init__(self, id): + if type(id) != gdb.Value and type(id) != int and type(id) != unicode: + raise TypeError('%s: must be gdb.Value, int, unicoded int' % (type(id))) + if type(id) == int: + id = gdb.Value(id) + self.id = id + if self.id.type.sizeof == 2: + self.idSize = self.OBJECT_16_BITS + else: + self.idSize = self.OBJECT_31_BITS + + def get(self, field): + if field in self.bits[self.idSize]: + bits = self.bits[self.idSize][field] + if bits[1] > 0: + return (int(self.id) >> bits[0]) & ((1 << (bits[1] - bits[0] + 1)) - 1) + return 0 + + def value(self): + return int(self.id) + + def index(self): + return self.get('index') + + def node(self): + return self.get('node') + + def api_val(self): + return self.get('api') + + def class_val(self): + return self.get('class') + + def api(self): + api = self.api_val() + if api < len(self.api_labels): + return self.api_labels[api] + return 'none' + + def _class(self): + api = self.api() + if api == 'none': + return 'invalid' + _class = self.class_val() + if _class < len(self.class_labels[api]): + return self.class_labels[api][_class] + return 'invalid' + + def valid(self): + return self.api() != 'none' and self._class() != 'invalid' + +class name: + """The Objects_Name can either be told what the name is or can take a + guess.""" + + def __init__(self, name, is_string = None): + self.name = name + if is_string == None: + self.is_string = 'auto' + else: + if is_string: + self.is_string = 'yes' + else: + self.is_string = 'no' + + def __str__(self): + if self.is_string != 'yes': + u32 = int(self.name['name_u32']) + s = chr((u32 >> 24) & 0xff) + \ + chr((u32 >> 16) & 0xff) + chr((u32 >> 8) & 0xff) + \ + chr(u32 & 0xff) + for c in range(0,4): + if s[c] < ' ' or s[c] > '~': + s = None + break + if s: + return s + return str(self.name['name_p'].dereference()) + +class control: + """The Objects_Control structure.""" + + def __init__(self, object): + self.object = object + self._id = ident(self.object['id']) + + def node(self): + return self.object['Node'] + + def id(self): + return self.object['id'] + + def name(self): + is_string = information.is_string(self._id.api(), self._id._class()) + return str(name(self.object['name'], is_string)) + +class id_printer: + """Print an object given the ID. Print using the struct display hint and an + iterator.""" + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, id): + self.id = id + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return int(self.id.value()) + elif self.count == 2: + return self.id.node() + elif self.count == 3: + return self.id.api() + elif self.count == 4: + return self.id._class() + elif self.count == 5: + return self.id.index() + raise StopIteration + + def __init__(self, id): + self.id = ident(id) + + def to_string(self): + return '' + + @staticmethod + def key(i): + if i == 0: + return 'id' + elif i == 1: + return 'node' + elif i == 2: + return 'api' + elif i == 3: + return 'class' + elif i == 4: + return 'index' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.id)) + + def display_hint (self): + return 'struct' + +class name_printer: + """Pretty printer for an object's name. It has to guess the type as no + information is available to help determine it.""" + + def __init__(self, name): + self.name = name(name) + + def to_string(self): + return gdb.Value(str(self.name)) + +class control_printer: + + class iterator: + """Use an iterator for each field expanded from the id so GDB output + is formatted correctly.""" + + def __init__(self, object): + self.object = object + self.count = 0 + + def __iter__(self): + return self + + def next(self): + self.count += 1 + if self.count == 1: + return self.object.node() + elif self.count == 2: + return self.object.id() + elif self.count == 3: + return self.object.name() + raise StopIteration + + def to_string(self): + return '' + + def __init__(self, object): + self.object = control(object) + + @staticmethod + def key(i): + if i == 0: + return 'Node' + elif i == 1: + return 'id' + elif i == 2: + return 'name' + return 'bad' + + def children(self): + counter = itertools.imap (self.key, itertools.count()) + return itertools.izip (counter, self.iterator(self.object)) + + def display_hint (self): + return 'struct' diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py new file mode 100644 index 0000000..e227c6f --- /dev/null +++ b/tools/gdb/python/rtems.py @@ -0,0 +1,110 @@ +# +# RTEMS Pretty Printers +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb +import re + +import objects +import threads +import classic + +nesting = 0 + +def type_from_value(val): + type = val.type; + # If it points to a reference, get the reference. + if type.code == gdb.TYPE_CODE_REF: + type = type.target () + # Get the unqualified type + return type.unqualified () + +def register_rtems_printers (obj): + "Register RTEMS pretty-printers with objfile Obj." + + if obj == None: + obj = gdb + + obj.pretty_printers.append (lookup_function) + +def lookup_function (val): + "Look-up and return a pretty-printer that can print val." + + global nesting + + typename = str(type_from_value(val)) + + for function in pp_dict: + if function.search (typename): + nesting += 1 + result = pp_dict[function] (val) + nesting -= 1 + if nesting == 0: + objects.information.invalidate() + return result + + # Cannot find a pretty printer. Return None. + return None + +def build_rtems_dict(): + pp_dict[re.compile('^rtems_id$')] = lambda val: objects.id_printer(val) + pp_dict[re.compile('^Objects_Id$')] = lambda val: objects.id_printer(val) + pp_dict[re.compile('^Objects_Name$')] = lambda val: objects.name_printer(val) + pp_dict[re.compile('^Objects_Control$')] = lambda val: objects.control_printer(val) + pp_dict[re.compile('^States_Control$')] = lambda val: threads.state_printer(val) + pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic.attribute_printer(val) + pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic.semaphore_printer(val) + +class rtems(gdb.Command): + """Prefix command for RTEMS.""" + + def __init__(self): + super(rtems, self).__init__('rtems', + gdb.COMMAND_STATUS, + gdb.COMPLETE_NONE, + True) + +class rtems_object(gdb.Command): + """Object sub-command for RTEMS""" + + objects = { + 'classic/semaphores': lambda id: classic.semaphore(id), + 'classic/tasks': lambda id: classic.task(id) + } + + def __init__(self): + self.__doc__ = 'Display the RTEMS object given a numeric ID.' + super(rtems_object, self).__init__('rtems object', + gdb.COMMAND_STATUS) + + def invoke(self, arg, from_tty): + for num in arg.split(): + try: + val = gdb.parse_and_eval(num) + num = int(val) + except: + print 'error: "%s" is not a number' % (num) + return + id = objects.ident(num) + if not id.valid(): + print 'Invalid object id' + print 'API:%s Class:%s Node:%d Index:%d Id:%08X' % \ + (id.api(), id._class(), id.node(), id.index(), id.value()) + objectname = id.api() + '/' + id._class() + if objectname in self.objects: + object = self.objects[objectname](id) + object.show(from_tty) + objects.information.invalidate() + +# +# Main +# +pp_dict = {} +build_rtems_dict() +gdb.pretty_printers = [] +gdb.pretty_printers.append (lookup_function) +rtems() +rtems_object() diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py new file mode 100644 index 0000000..906cf5a --- /dev/null +++ b/tools/gdb/python/threads.py @@ -0,0 +1,207 @@ +# +# RTEMS Threads Support +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb + +import chains +import objects + +def task_chain(chain): + tasks = [] + node = chain.first() + while not node.null(): + print node.addr + tasks.append(control(node.cast('Thread_Control'))) + node.next() + return tasks + +class state: + + ALL_SET = 0x000fffff + READY = 0x00000000 + DORMANT = 0x00000001 + SUSPENDED = 0x00000002 + TRANSIENT = 0x00000004 + DELAYING = 0x00000008 + WAITING_FOR_TIME = 0x00000010 + WAITING_FOR_BUFFER = 0x00000020 + WAITING_FOR_SEGMENT = 0x00000040 + WAITING_FOR_MESSAGE = 0x00000080 + WAITING_FOR_EVENT = 0x00000100 + WAITING_FOR_SEMAPHORE = 0x00000200 + WAITING_FOR_MUTEX = 0x00000400 + WAITING_FOR_CONDITION_VARIABLE = 0x00000800 + WAITING_FOR_JOIN_AT_EXIT = 0x00001000 + WAITING_FOR_RPC_REPLY = 0x00002000 + WAITING_FOR_PERIOD = 0x00004000 + WAITING_FOR_SIGNAL = 0x00008000 + WAITING_FOR_BARRIER = 0x00010000 + WAITING_FOR_RWLOCK = 0x00020000 + INTERRUPTIBLE_BY_SIGNAL = 0x10000000 + LOCALLY_BLOCKED = \ + WAITING_FOR_BUFFER | \ + WAITING_FOR_SEGMENT | \ + WAITING_FOR_MESSAGE | \ + WAITING_FOR_SEMAPHORE | \ + WAITING_FOR_MUTEX | \ + WAITING_FOR_CONDITION_VARIABLE | \ + WAITING_FOR_JOIN_AT_EXIT | \ + WAITING_FOR_SIGNAL | \ + WAITING_FOR_BARRIER | \ + WAITING_FOR_RWLOCK + WAITING_ON_THREAD_QUEUE = \ + LOCALLY_BLOCKED | WAITING_FOR_RPC_REPLY + BLOCKED = \ + DELAYING | \ + WAITING_FOR_TIME | \ + WAITING_FOR_PERIOD | \ + WAITING_FOR_EVENT | \ + WAITING_ON_THREAD_QUEUE | \ + INTERRUPTIBLE_BY_SIGNAL + + masks = { + ALL_SET : 'all-set', + READY : 'ready', + DORMANT : 'dormant', + SUSPENDED : 'suspended', + TRANSIENT : 'transient', + DELAYING : 'delaying', + WAITING_FOR_TIME : 'waiting-for-time', + WAITING_FOR_BUFFER : 'waiting-for-buffer', + WAITING_FOR_SEGMENT : 'waiting-for-segment', + WAITING_FOR_MESSAGE : 'waiting-for-message', + WAITING_FOR_EVENT : 'waiting-for-event', + WAITING_FOR_SEMAPHORE : 'waiting-for-semaphore', + WAITING_FOR_MUTEX : 'waiting-for-mutex', + WAITING_FOR_CONDITION_VARIABLE : 'waiting-for-condition-variable', + WAITING_FOR_JOIN_AT_EXIT : 'waiting-for-join-at-exit', + WAITING_FOR_RPC_REPLY : 'waiting-for-rpc-reply', + WAITING_FOR_PERIOD : 'waiting-for-period', + WAITING_FOR_SIGNAL : 'waiting-for-signal', + WAITING_FOR_BARRIER : 'waiting-for-barrier', + WAITING_FOR_RWLOCK : 'waiting-for-rwlock' + } + + def __init__(self, s): + self.s = s + + def to_string(self): + if (self.s & self.LOCALLY_BLOCKED) == self.LOCALLY_BLOCKED: + return 'locally-blocked' + if (self.s & self.WAITING_ON_THREAD_QUEUE) == self.WAITING_ON_THREAD_QUEUE: + return 'waiting-on-thread-queue' + if (self.s & self.BLOCKED) == self.BLOCKED: + return 'blocked' + s = ',' + for m in self.masks: + if (self.s & m) == m: + s = self.masks[m] + ',' + return s[:-1] + +class wait_info: + + def __init__(self, info): + self.info = info + + def id(self): + return self.info['id'] + + def count(self): + return self.info['count'] + + def return_arg(self): + return self.info['return_argument'] + + def option(self): + return self.info['option'] + + def block2n(self): + return task_chain(chains.control(self.info['Block2n'])) + + def queue(self): + return task_chain(chains.control(self.info['queue'])) + +class control: + + def __init__(self, ctrl): + self.ctrl = ctrl + self.object = objects.control(ctrl['Object']) + + def id(self): + return self.object.id() + + def name(self): + return self.object.name() + + def current_state(self): + return state(self.ctrl['current_state']).to_string() + + def current_priority(self): + return self.ctrl['current_priority'] + + def real_priority(self): + return self.ctrl['real_priority'] + + def suspends(self): + return self.ctrl['suspend_count'] + + def post_task_switch_ext(self): + return self.ctrl['do_post_task_switch_extension'] + + def preemptible(self): + return self.ctrl['is_preemptible'] + + def cpu_time_budget(self): + return self.ctrl['cpu_time_budget'] + + def wait_info(self): + return wait_info(self.ctrl['Wait']) + + def brief(self): + return "'%s' (c:%d, r:%d)" % \ + (self.name(), self.current_priority(), self.real_priority()) + +class queue: + """Manage the Thread_queue_Control.""" + + priority_headers = 4 + + def __init__(self, que): + self.que = que + + def fifo(self): + return str(self.que['discipline']) == 'THREAD_QUEUE_DISCIPLINE_FIFO' + + def priority(self): + return str(self.que['discipline']) == 'THREAD_QUEUE_DISCIPLINE_PRIORITY' + + def state(self): + return state(self.que['state']).to_string() + + def tasks(self): + if self.fifo(): + t = task_chain(chains.control(self.que['Queues']['Fifo'])) + else: + t = [] + for ph in range(0, self.priority_headers): + t.extend(task_chain(chains.control(self.que['Queues']['Fifo']))) + return t + + def to_string(self): + if self.fifo(): + s = 'fifo' + else: + s = 'priority' + return + +class state_printer: + + def __init__(self, s): + self.s = state(s) + + def to_string(self): + return self.s.to_string() diff --git a/tools/gdb/python/watchdog.py b/tools/gdb/python/watchdog.py new file mode 100644 index 0000000..0766575 --- /dev/null +++ b/tools/gdb/python/watchdog.py @@ -0,0 +1,56 @@ +# +# RTEMS Watchdog Support +# Copyright 2010 Chris Johns (chrisj at rtems.org) +# +# $Id$ +# + +import gdb + +import chains +import objects + +class state: + + INACTIVE = 0 + BEING_INSERTED = 1 + ACTIVE = 2 + REMOVE_IT = 3 + + states = { + 0: 'inactive', + 1: 'being-inserted', + 2: 'active', + 3: 'remove-it' + } + + def __init__(self, s): + self.s = s + + def to_string(self): + return self.states[self.s] + +class control: + + def __init__(self, ctrl): + self.ctrl = ctrl + + def state(self): + return state(self.ctrl['state']).to_string() + + def initial(self): + return self.ctrl['initial'] + + def delta_interval(self): + return self.ctrl['delta_interval'] + + def start_time(self): + return self.ctrl['start_time'] + + def stop_time(self): + return self.ctrl['stop_time'] + + def routine(self): + addr = self.ctrl['routine'] + sym = gdb.lookup_symbol(addr) + print sym From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Remove the header. Message-ID: <20140824234537.479F270080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 5a4834c6415f5e621bc753744fe6fafbb064aca0 Changeset: http://git.rtems.org/rtems-tools/commit/?id=5a4834c6415f5e621bc753744fe6fafbb064aca0 Author: Dhananjay Balan Date: Mon Aug 26 21:23:59 2013 +0530 Remove the header. --- tools/gdb/python/rtems.py | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 5f0aa7d..6c987cf 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -229,7 +229,6 @@ class rtems_watchdog_chain(gdb.Command): nd = inst.first() i = 0 - print ' Ticks Chain' while not nd.null(): wd = watchdog.control(nd.cast('Watchdog_Control')) print ' #'+str(i) From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Fix README mistakes. Message-ID: <20140824234535.E3E4D700A5B@git.rtems.org> Module: rtems-tools Branch: master Commit: 4dbd0db60d1d0a3af7c2311911d6a6a638ccca84 Changeset: http://git.rtems.org/rtems-tools/commit/?id=4dbd0db60d1d0a3af7c2311911d6a6a638ccca84 Author: Chris Johns Date: Mon Aug 25 09:48:23 2014 +1000 Fix README mistakes. --- README | 12 +++++++----- 1 files changed, 7 insertions(+), 5 deletions(-) diff --git a/README b/README index 9325e0d..be8aacd 100644 --- a/README +++ b/README @@ -10,13 +10,15 @@ All tools are distributed as source code. They should work on a range of host computers. Windows support may be via cross building on suitable Unix systems. The tools contained in this package each come with documentation so please -locate and refer to it. +locate and refer to that. The RTEMS Tools Project has been developed for the RTEMS Project however these -tools can be used for a range of things no relate to RTEMS. The RTEMS Project -welcomes this and +tools can be used for a range of things not related to RTEMS. The RTEMS Project +welcomes this. If you have a problem or question post to rtems-user at rtems.org or drop by the -RTEMS IRC channel #rtems on chat.freenode.net. Drop by and tell us is you are -using this tools for other uses. +RTEMS IRC channel #rtems on chat.freenode.net. Drop by and tell us if you are +using these tools for other uses. +If you have any patches please post them to the devel at rtems.org mailing list in +git format patches with your details. From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Categories the commands. Message-ID: <20140824234536.6F28D700B15@git.rtems.org> Module: rtems-tools Branch: master Commit: d4fc2d5e54adb8d0f48d94166e5e41926e3f47e3 Changeset: http://git.rtems.org/rtems-tools/commit/?id=d4fc2d5e54adb8d0f48d94166e5e41926e3f47e3 Author: Dhananjay Balan Date: Tue Aug 20 22:16:16 2013 +0530 Categories the commands. The subcommands fall onto DATA. See http://sourceware.org/gdb/onlinedocs/gdb/Commands-In-Python.html#Commands-In-Python --- tools/gdb/python/rtems.py | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index c45d72e..718701c 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -36,9 +36,11 @@ class rtems_object(gdb.Command): } def __init__(self): - self.__doc__ = 'Display the RTEMS object given a numeric ID (Or a reference to rtems_object).' + self.__doc__ = 'Display the RTEMS object given a numeric ID \ + (Or a reference to rtems_object).' super(rtems_object, self).__init__('rtems object', - gdb.COMMAND_STATUS) + gdb.COMMAND_DATA, + gdb.COMPLETE_SYMBOL) def invoke(self, arg, from_tty): for num in arg.split(): @@ -71,8 +73,8 @@ class rtems_semaphore(gdb.Command): def __init__(self): self.__doc__ = 'Display the RTEMS semaphores by index' - super(rtems_semaphore, self).__init__('rtems semaphore', - gdb.COMMAND_STATUS) + super(rtems_semaphore, self).__init__( 'rtems semaphore', + gdb.COMMAND_DATA, gdb.COMPLETE_NONE ) def invoke(self, arg, from_tty): for val in arg.split(): @@ -101,7 +103,8 @@ class rtems_task(gdb.Command): def __init__(self): self.__doc__ = 'Display the RTEMS tasks by index(s)' - super(rtems_task,self).__init__('rtems task', gdb.COMMAND_STATUS) + super(rtems_task,self).__init__('rtems task', + gdb.COMMAND_DATA, gdb.COMPLETE_NONE) def invoke(self, arg, from_tty): for val in arg.split(): @@ -130,7 +133,9 @@ class rtems_message_queue(gdb.Command): def __init__(self): self.__doc__ = 'Display the RTEMS message_queue by index(s)' - super(rtems_message_queue,self).__init__('rtems mqueue', gdb.COMMAND_STATUS) + super(rtems_message_queue,self).__init__('rtems mqueue', + gdb.COMMAND_DATA, + gdb.COMPLETE_NONE) def invoke(self, arg, from_tty): for val in arg.split(): From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] gdb-python: Clean up and ignore waf generated files. Message-ID: <20140824234536.E2F3170080E@git.rtems.org> Module: rtems-tools Branch: master Commit: f750e82bbc904a60ea40116e34fa0a5495020c85 Changeset: http://git.rtems.org/rtems-tools/commit/?id=f750e82bbc904a60ea40116e34fa0a5495020c85 Author: Chris Johns Date: Mon Aug 25 09:39:26 2014 +1000 gdb-python: Clean up and ignore waf generated files. --- tools/gdb/python/.gitignore | 36 ++---------------------------------- 1 files changed, 2 insertions(+), 34 deletions(-) diff --git a/tools/gdb/python/.gitignore b/tools/gdb/python/.gitignore index d2d6f36..7b4e3af 100644 --- a/tools/gdb/python/.gitignore +++ b/tools/gdb/python/.gitignore @@ -1,35 +1,3 @@ -*.py[cod] - -# C extensions -*.so - -# Packages -*.egg -*.egg-info -dist +*.pyc +.lock-waf* build -eggs -parts -bin -var -sdist -develop-eggs -.installed.cfg -lib -lib64 - -# Installer logs -pip-log.txt - -# Unit test / coverage reports -.coverage -.tox -nosetests.xml - -# Translations -*.mo - -# Mr Developer -.mr.developer.cfg -.project -.pydevproject From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Refactor Message-ID: <20140824234537.1E72C700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 6d89e3c34e68e61013abb39ff058bc5715eaa455 Changeset: http://git.rtems.org/rtems-tools/commit/?id=6d89e3c34e68e61013abb39ff058bc5715eaa455 Author: Dhananjay Balan Date: Thu Aug 1 12:38:23 2013 +0530 Refactor - The objects are intialized using the objects rather than the ID. --- tools/gdb/python/classic.py | 36 +++++++++++++++--------------------- tools/gdb/python/rtems.py | 18 ++++++++++-------- 2 files changed, 25 insertions(+), 29 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 50514ff..29ffab5 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -108,9 +108,8 @@ class attribute: class semaphore: "Print a classic semaphore." - def __init__(self, id): - self.id = id; - self.object = objects.information.object(self.id).dereference() + def __init__(self, obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'semaphore') @@ -149,10 +148,10 @@ class semaphore: class task: "Print a classic task" - def __init__(self, id): - self.id = id; + def __init__(self, obj): + self.object = obj self.task = \ - threads.control(objects.information.object(self.id).dereference()) + threads.control(self.object) self.wait_info = self.task.wait_info() def show(self, from_tty): @@ -167,9 +166,8 @@ class task: class message_queue: "Print classic messege queue" - def __init__(self,id): - self.id = id - self.object = objects.information.object(self.id).dereference() + def __init__(self,obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], \ 'message_queue') @@ -187,9 +185,8 @@ class message_queue: class timer: '''Print a classic timer''' - def __init__(self, id): - self.id = id - self.object = objects.information.object(self.id).dereference() + def __init__(self, obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.watchdog = watchdog.control(self.object['Ticker']) @@ -200,9 +197,8 @@ class timer: class partition: ''' Print a rtems partition ''' - def __init__(self, id): - self.id = id - self.object = objects.information.object(self.id).dereference() + def __init__(self, obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'partition') self.starting_addr = self.object['starting_address'] @@ -221,9 +217,8 @@ class partition: class region: "prints a classic region" - def __init__(self,id): - self.id = id - self.object = objects.information.object(self.id).dereference() + def __init__(self,obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'region') self.wait_queue = threads.queue(self.object['Wait_queue']) @@ -239,9 +234,8 @@ class region: class barrier: '''classic barrier abstraction''' - def __init__(self,id): - self.id = id - self.object = objects.information.object(self.id).dereference() + def __init__(self,obj): + self.object = obj self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'],'barrier') self.core_b_control = supercore.barrier_control(self.object['Barrier']) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index adab86d..b2dc776 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -75,13 +75,13 @@ class rtems_object(gdb.Command): """Object sub-command for RTEMS""" objects = { - 'classic/semaphores': lambda id: classic.semaphore(id), - 'classic/tasks': lambda id: classic.task(id), - 'classic/message_queues': lambda id: classic.message_queue(id), - 'classic/timers' : lambda id: classic.timer(id), - 'classic/partitions' : lambda id: classic.partition(id), - 'classic/regions' : lambda id: classic.region(id), - 'classic/barriers' : lambda id: classic.barrier(id) + 'classic/semaphores': lambda obj: classic.semaphore(obj), + 'classic/tasks': lambda obj: classic.task(obj), + 'classic/message_queues': lambda obj: classic.message_queue(obj), + 'classic/timers' : lambda obj: classic.timer(obj), + 'classic/partitions' : lambda obj: classic.partition(obj), + 'classic/regions' : lambda obj: classic.region(obj), + 'classic/barriers' : lambda obj: classic.barrier(obj) } def __init__(self): @@ -103,8 +103,10 @@ class rtems_object(gdb.Command): print 'API:%s Class:%s Node:%d Index:%d Id:%08X' % \ (id.api(), id._class(), id.node(), id.index(), id.value()) objectname = id.api() + '/' + id._class() + + obj = objects.information.object(id).dereference() if objectname in self.objects: - object = self.objects[objectname](id) + object = self.objects[objectname](obj) object.show(from_tty) objects.information.invalidate() From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Complete index subcommands. Message-ID: <20140824234537.80060700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 8da0a3745770547d1ebdcaca97702087ce4bc8a5 Changeset: http://git.rtems.org/rtems-tools/commit/?id=8da0a3745770547d1ebdcaca97702087ce4bc8a5 Author: Dhananjay Balan Date: Wed Aug 21 18:49:01 2013 +0530 Complete index subcommands. --- tools/gdb/python/rtems.py | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 48 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 7d26542..b142f23 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -136,3 +136,51 @@ class rtems_message_queue(rtems_index): def instance(self,obj): return classic.message_queue(obj) +class rtems_timer(rtems_index): + '''Index subcommand''' + + _class = 'timers' + + def __init__(self): + self.__doc__ = 'Display RTEMS timer(s) by index(es)' + super(rtems_timer, self).__init__('rtems timer') + + def instance(self,obj): + return classic.timer(obj) + +class rtems_partition(rtems_index): + '''Partition subcommand''' + + _class = 'partitions' + + def __init__(self): + self.__doc__ = 'Display RTEMS partition(s) by index(es)' + super(rtems_partition, self).__init__('rtems partition') + + def instance(self, obj): + return classic.partition(obj) + +class rtems_region(rtems_index): + '''Region subcomamnd''' + + _class = 'regions' + + def __init__(self): + self.__doc__ = 'Display RTEMS region(s) by index(es)' + super(rtems_region , self).__init__('rtems regions') + + def instance(self, obj): + return classic.region(obj) + +class rtems_barrier(rtems_index): + '''Barrier subcommand''' + + _class = 'barriers' + + def __init__(self): + self.__doc__ = 'Display RTEMS barrier(s) by index(es)' + super(rtems_barrier , self).__init__('rtems barrier') + + def instance(self, obj): + return classic.barrier(obj) + From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add helper func. Message-ID: <20140824234537.AB8C270080E@git.rtems.org> Module: rtems-tools Branch: master Commit: a4d0739522651592f5f2b45e51f3957f3d11cdeb Changeset: http://git.rtems.org/rtems-tools/commit/?id=a4d0739522651592f5f2b45e51f3957f3d11cdeb Author: Dhananjay Balan Date: Sun Aug 25 23:22:20 2013 +0530 Add helper func. - tests a bit at specified position. --- tools/gdb/python/helper.py | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/helper.py b/tools/gdb/python/helper.py index 146ee69..dfd01eb 100644 --- a/tools/gdb/python/helper.py +++ b/tools/gdb/python/helper.py @@ -16,3 +16,6 @@ def type_from_value(val): type = type.target () # Get the unqualified type return type.unqualified () + +def test_bit(val, pos): + return bool(val & (1 << (pos-1))) \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Catch empty task names, Message-ID: <20140824234537.B75B0700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 7a415d4e43de67e0eabcca3a1375c4e530f37a07 Changeset: http://git.rtems.org/rtems-tools/commit/?id=7a415d4e43de67e0eabcca3a1375c4e530f37a07 Author: Dhananjay Balan Date: Sat Aug 24 20:44:06 2013 +0530 Catch empty task names, - All the tasks do not have a name. --- tools/gdb/python/classic.py | 2 ++ tools/gdb/python/objects.py | 9 ++++++++- tools/gdb/python/threads.py | 6 ++++-- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index b919383..261f648 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -140,6 +140,8 @@ class semaphore: tasks = wait_queue.tasks() print ' Queue: len = %d, state = %s' % (len(tasks), wait_queue.state()) + print ' Tasks:' + print ' Name (c:current, r:real), (id)' for t in range(0, len(tasks)): print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) else: diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 58c2730..f4ae5e1 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -253,4 +253,11 @@ class control: def name(self): is_string = information.is_string(self._id.api(), self._id._class()) - return str(name(self.object['name'], is_string)) \ No newline at end of file + val = str(name(self.object['name'],is_string)) + + # Normal comaprision is a bit tricky with quotes + # 0 '\000' in hex == '3020275c30303027' + if val.encode('hex') == '3020275c30303027': + val = "" + + return val \ No newline at end of file diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py index 77c7efa..7098481 100644 --- a/tools/gdb/python/threads.py +++ b/tools/gdb/python/threads.py @@ -6,7 +6,6 @@ # import gdb - import chains import objects @@ -134,7 +133,10 @@ class control: return self.object.id() def name(self): - return self.object.name() + val = self.object.name() + if val == "": + val = '*' + return val def current_state(self): return state(self.ctrl['current_state']).to_string() From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add watchdog seconds command Message-ID: <20140824234537.4DF01700810@git.rtems.org> Module: rtems-tools Branch: master Commit: 61154bf302d5f022b54094e0fc58e9a0fc00f983 Changeset: http://git.rtems.org/rtems-tools/commit/?id=61154bf302d5f022b54094e0fc58e9a0fc00f983 Author: Dhananjay Balan Date: Mon Aug 26 21:14:30 2013 +0530 Add watchdog seconds command - prints the watchdog chain managed at second boundaries. --- tools/gdb/python/main.py | 3 ++- tools/gdb/python/objects.py | 1 + tools/gdb/python/rtems.py | 8 ++++++++ 3 files changed, 11 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/main.py b/tools/gdb/python/main.py index a0ff7dc..6fb7c54 100644 --- a/tools/gdb/python/main.py +++ b/tools/gdb/python/main.py @@ -18,4 +18,5 @@ rtems.rtems_semaphore() rtems.rtems_task() rtems.rtems_message_queue() rtems.rtems_tod() -rtems.rtems_wdt() \ No newline at end of file +rtems.rtems_wdt() +rtems.rtems_wsec() \ No newline at end of file diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index ae2a4c7..ee59cbc 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -15,6 +15,7 @@ class infotables: tables_types = { 'internal/time' : ('TOD_Control', '_TOD'), 'internal/wdticks' : ('Chain_Control', '_Watchdog_Ticks_chain'), + 'internal/wdseconds' : ('Chain_Control', '_Watchdog_Seconds_chain'), 'classic/tasks' : ('Thread_Control', '_RTEMS_tasks_Information'), 'classic/timers' : ('Timer_Control', '_Timer_Information'), diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 340c7ff..5f0aa7d 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -245,3 +245,11 @@ class rtems_wdt(rtems_watchdog_chain): self.__doc__ = 'Display watchdog ticks chain' super(rtems_wdt, self).__init__('rtems wdticks') +class rtems_wsec(rtems_watchdog_chain): + + _class = 'wdseconds' + + def __init__(self): + self.__doc__ = 'Display watchdog seconds chain' + super(rtems_wsec, self).__init__('rtems wdseconds') + From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] gdb-python: Add waf script to install under a prefix. Message-ID: <20140824234537.CF124700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 504e1de9de483f6f8ba54c5424c2327db1be6755 Changeset: http://git.rtems.org/rtems-tools/commit/?id=504e1de9de483f6f8ba54c5424c2327db1be6755 Author: Chris Johns Date: Mon Aug 25 09:40:57 2014 +1000 gdb-python: Add waf script to install under a prefix. --- tools/gdb/python/wscript | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/wscript b/tools/gdb/python/wscript new file mode 100644 index 0000000..22d44e8 --- /dev/null +++ b/tools/gdb/python/wscript @@ -0,0 +1,23 @@ +# +# Install the RTEMS gdb python +# + +def configure(conf): + conf.load('python') + +def build(bld): + bld.install_files('${PREFIX}/share/gdb/python/rtems', + ['chains.py', + 'classic.py', + 'classic_printer.py', + 'heaps.py', + 'helper.py', + 'main.py', + 'objects.py', + 'pretty.py', + 'rtems.py', + 'sparc.py', + 'supercore.py', + 'supercore_printer.py', + 'threads.py', + 'watchdog.py']) From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Move todo Message-ID: <20140824234537.893E9700814@git.rtems.org> Module: rtems-tools Branch: master Commit: e282b6efcb7b5cc5611d829663171b5bda9d3bb6 Changeset: http://git.rtems.org/rtems-tools/commit/?id=e282b6efcb7b5cc5611d829663171b5bda9d3bb6 Author: Dhananjay Balan Date: Mon Jul 29 16:42:24 2013 +0530 Move todo Why else is there issues? --- tools/gdb/python/README.md | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 6dc9b5e..8858a4f 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -4,7 +4,3 @@ rtems-gdb GDB extenstions to RTEMS. See [this blog post for instructions](http://dbalan.github.io/blog/2013/06/23/debugging-rtems-with-gdb/) - -TODO: - - classic abstractions address on id - change this to more proper hierarchy. - - Inherit from object_control class From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Add region support. Message-ID: <20140824234537.5474E700679@git.rtems.org> Module: rtems-tools Branch: master Commit: b9ee5df588aa1a4cf0a64cf511b0585309ff5510 Changeset: http://git.rtems.org/rtems-tools/commit/?id=b9ee5df588aa1a4cf0a64cf511b0585309ff5510 Author: Dhananjay Balan Date: Sun Jul 28 15:03:58 2013 +0530 Add region support. Abstractions for classic/region added. --- tools/gdb/python/classic.py | 27 ++++++++++++++++++++++++--- tools/gdb/python/heaps.py | 28 +++++++++++++++++++++++++--- tools/gdb/python/helper.py | 2 +- tools/gdb/python/objects.py | 2 +- tools/gdb/python/rtems.py | 3 ++- tools/gdb/python/supercore.py | 2 +- 6 files changed, 54 insertions(+), 10 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index f7d4dfc..e2ecfaa 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -8,10 +8,13 @@ import gdb import itertools import re +#ToDo This shouldn't be here +import helper import objects import threads import watchdog +import heaps import supercore class attribute: @@ -41,7 +44,8 @@ class attribute: 'barrier'], 'message_queue' : ['priority', 'scope'], - 'partition' : ['scope'] + 'partition' : ['scope'], + 'region' : ['priority'] } masks = { @@ -214,6 +218,23 @@ class partition: print ' Name:', self.object_control.name() print ' Attr:', self.attr.to_string() print ' Length:', self.length - print 'Buffer Size:', self.buffer_size - print 'Used Blocks:', self.used_blocks + print ' B Size:', self.buffer_size + print ' U Blocks:', self.used_blocks +class region: + "prints a classic region" + + def __init__(self,id): + self.id = id + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.attr = attribute(self.object['attribute_set'], 'region') + self.wait_queue = threads.queue(self.object['Wait_queue']) + self.heap = heaps.control(self.object['Memory']) + + def show(self, from_tty): + print ' Name:', self.object_control.name() + print ' Attr:', self.attr.to_string() + helper.tasks_printer_routine(self.wait_queue) + print ' Memory:' + self.heap.show() diff --git a/tools/gdb/python/heaps.py b/tools/gdb/python/heaps.py index 4798912..2cc7907 100644 --- a/tools/gdb/python/heaps.py +++ b/tools/gdb/python/heaps.py @@ -15,6 +15,8 @@ class block: return False return True + def val(self): + return str(self.block) def next(self): if not self.null(): @@ -25,11 +27,15 @@ class block: self.block = self.block['prev'] class stats: - ''heap statistics'' + '''heap statistics''' def __init__(self,stat): self.stat = stat + def inst(self): + i = self.stat['instance'] + return i + def avail(self): val = self.stat['size'] return val @@ -37,9 +43,14 @@ class stats: def free(self): return self.stat['free_size'] + def show(self): + print ' Instance:',self.inst() + print ' Avail:',self.avail() + print ' Free:',self.free() + # ToDo : incorporate others -def control: +class control: '''Abstract a heap control structure''' def __init__(self, ctl): @@ -59,4 +70,15 @@ def control: def stat(self): st = stats(self.ctl['stats']) - return st \ No newline at end of file + return st + + def show(self): + fi = self.first() + la = self.last() + + print ' First:', fi.val() + print ' Last:', la.val() + + stats = self.stat() + print ' stats:' + stats.show() \ No newline at end of file diff --git a/tools/gdb/python/helper.py b/tools/gdb/python/helper.py index ec17400..c9c9a42 100644 --- a/tools/gdb/python/helper.py +++ b/tools/gdb/python/helper.py @@ -1,7 +1,7 @@ # # RTEMS GDB support helper routins. -def tasks_printer_rotuine(wait_queue): +def tasks_printer_routine(wait_queue): tasks = wait_queue.tasks() print ' Queue: len = %d, state = %s' % (len(tasks),wait_queue.state()) for t in range(0, len(tasks)): diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index c433039..1a64a8d 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -18,7 +18,7 @@ class infotables: 'classic/semaphores' : ('Semaphore_Control', '_Semaphore_Information'), 'classic/message_queues' : ('Message_queue_Control', '_Message_queue_Information'), 'classic/partitions' : ('Partition_Control', '_Partition_Information'), - 'classic/regions' : ('Region_Control', '_Regions_Information'), + 'classic/regions' : ('Region_Control', '_Region_Information'), 'classic/ports' : ('Port_Control', '_Port_Information'), 'classic/periods' : ('Period_Control', '_Period_Information'), 'classic/extensions' : ('Extension_Control', '_Extension_Information'), diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index eac5042..8738736 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -79,7 +79,8 @@ class rtems_object(gdb.Command): 'classic/tasks': lambda id: classic.task(id), 'classic/message_queues': lambda id: classic.message_queue(id), 'classic/timers' : lambda id: classic.timer(id), - 'classic/partitions' : lambda id: classic.partition(id) + 'classic/partitions' : lambda id: classic.partition(id), + 'classic/regions' : lambda id: classic.region(id) } def __init__(self): diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py index 7e958b1..073bbd0 100644 --- a/tools/gdb/python/supercore.py +++ b/tools/gdb/python/supercore.py @@ -15,4 +15,4 @@ class CORE_message_queue: # self.buffer def show(self): - helper.tasks_printer_rotuine(self.wait_queue) + helper.tasks_printer_routine(self.wait_queue) From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Refactor Message-ID: <20140824234536.B9CCB700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 8d035f8556f5c121b709c1cd6ed223fa2b70b66c Changeset: http://git.rtems.org/rtems-tools/commit/?id=8d035f8556f5c121b709c1cd6ed223fa2b70b66c Author: Dhananjay Balan Date: Tue Aug 20 22:05:22 2013 +0530 Refactor - pretty printers moved to pretty module - command and subcommands get own module --- tools/gdb/python/__init__.py | 20 +----------- tools/gdb/python/helper.py | 12 +++++++- tools/gdb/python/main.py | 19 +++++++++++ tools/gdb/python/pretty.py | 53 ++++++++++++++++++++++++++++++++ tools/gdb/python/rtems.py | 69 +---------------------------------------- 5 files changed, 86 insertions(+), 87 deletions(-) diff --git a/tools/gdb/python/__init__.py b/tools/gdb/python/__init__.py index 694eb06..36d2c06 100644 --- a/tools/gdb/python/__init__.py +++ b/tools/gdb/python/__init__.py @@ -3,24 +3,6 @@ if __name__ == "__main__": import sys import os.path sys.path.append(os.path.dirname(__file__)) - import supercore - import chains - import rtems - import classic - import objects - import threads - - import supercore_printer - import classic_printer - - # Needed inorder to reload code from inside gdb - reload(supercore) - reload(chains) - reload(rtems) - reload(classic) - reload(objects) - reload(threads) - reload(supercore_printer) - reload(classic_printer) + import main print 'RTEMS GDB Support loaded' diff --git a/tools/gdb/python/helper.py b/tools/gdb/python/helper.py index c9c9a42..146ee69 100644 --- a/tools/gdb/python/helper.py +++ b/tools/gdb/python/helper.py @@ -1,8 +1,18 @@ # # RTEMS GDB support helper routins. +import gdb + def tasks_printer_routine(wait_queue): tasks = wait_queue.tasks() print ' Queue: len = %d, state = %s' % (len(tasks),wait_queue.state()) for t in range(0, len(tasks)): - print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) \ No newline at end of file + print ' ', tasks[t].brief(), ' (%08x)' % (tasks[t].id()) + +def type_from_value(val): + type = val.type; + # If it points to a reference, get the reference. + if type.code == gdb.TYPE_CODE_REF: + type = type.target () + # Get the unqualified type + return type.unqualified () diff --git a/tools/gdb/python/main.py b/tools/gdb/python/main.py new file mode 100644 index 0000000..2ef475a --- /dev/null +++ b/tools/gdb/python/main.py @@ -0,0 +1,19 @@ +# +# RTEMS GDB Extensions +# +# main + +import gdb +import pretty +import rtems + +gdb.pretty_printers = [] +gdb.pretty_printers.append(pretty.lookup_function) + +# Register commands +# rtems and subcommands +rtems.rtems() +rtems.rtems_object() +rtems.rtems_semaphore() +rtems.rtems_task() +rtems.rtems_message_queue() \ No newline at end of file diff --git a/tools/gdb/python/pretty.py b/tools/gdb/python/pretty.py new file mode 100644 index 0000000..929c245 --- /dev/null +++ b/tools/gdb/python/pretty.py @@ -0,0 +1,53 @@ +# +# RTEMS pretty printers +# +import re +import helper +import objects + +import supercore_printer +import classic_printer + +pretty_printer = { + + '^rtems_id$' : supercore_printer.id, + '^Objects_Id$' : supercore_printer.id, + '^Objects_Name$' : supercore_printer.name, + '^Objects_Control$' : supercore_printer.control, + '^States_Control$' : supercore_printer.state, + '^rtems_attribute$' : classic_printer.attribute, + '^Semaphore_Control$' : classic_printer.semaphore +} + + +def build_pretty_printer (): + pp_dict = {} + + for name in pretty_printer: + pp_dict[re.compile(name)] = pretty_printer[name] + + return pp_dict + +def lookup_function (val): + "Look-up and return a pretty-printer that can print val." + + global nesting + + typename = str(helper.type_from_value(val)) + + for function in pp_dict: + if function.search (typename): + nesting += 1 + result = pp_dict[function] (val) + nesting -= 1 + if nesting == 0: + objects.information.invalidate() + return result + + # Cannot find a pretty printer. Return None. + return None + +# ToDo: properly document. +nesting = 0 + +pp_dict = build_pretty_printer() diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 9ae2105..c45d72e 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -12,55 +12,6 @@ import objects import threads import classic -# ToDo: Move every printing out -import supercore_printer -import classic_printer - -nesting = 0 - -def type_from_value(val): - type = val.type; - # If it points to a reference, get the reference. - if type.code == gdb.TYPE_CODE_REF: - type = type.target () - # Get the unqualified type - return type.unqualified () - -def register_rtems_printers (obj): - "Register RTEMS pretty-printers with objfile Obj." - - if obj == None: - obj = gdb - - obj.pretty_printers.append (lookup_function) - -def lookup_function (val): - "Look-up and return a pretty-printer that can print val." - - global nesting - - typename = str(type_from_value(val)) - - for function in pp_dict: - if function.search (typename): - nesting += 1 - result = pp_dict[function] (val) - nesting -= 1 - if nesting == 0: - objects.information.invalidate() - return result - - # Cannot find a pretty printer. Return None. - return None - -def build_rtems_dict(): - pp_dict[re.compile('^rtems_id$')] = lambda val: supercore_printer.id(val) - pp_dict[re.compile('^Objects_Id$')] = lambda val: supercore_printer.id(val) - pp_dict[re.compile('^Objects_Name$')] = lambda val: supercore_printer.name(val) - pp_dict[re.compile('^Objects_Control$')] = lambda val: supercore_printer.control(val) - pp_dict[re.compile('^States_Control$')] = lambda val: supercore_printer.state(val) - pp_dict[re.compile('^rtems_attribute$')] = lambda val: classic_printer.attribute(val) - pp_dict[re.compile('^Semaphore_Control$')] = lambda val: classic_printer.semaphore(val) class rtems(gdb.Command): """Prefix command for RTEMS.""" @@ -157,8 +108,7 @@ class rtems_task(gdb.Command): try: index = int(val) except ValueError: - print "error: %s is not an index" % (val) - return + raise gdb.GdbError( "Value is not an integer") try: obj = objects.information.object_return(self.api, @@ -198,21 +148,6 @@ class rtems_message_queue(gdb.Command): print "error: index %s is invalid" % (index) return - print "Ahi" instance = classic.message_queue(obj) instance.show(from_tty) - objects.information.invalidate() - - -# -# Main -# -pp_dict = {} -build_rtems_dict() -gdb.pretty_printers = [] -gdb.pretty_printers.append (lookup_function) -rtems() -rtems_object() -rtems_semaphore() -rtems_task() -rtems_message_queue() \ No newline at end of file + objects.information.invalidate() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Add task subcommand Message-ID: <20140824234537.E0910700814@git.rtems.org> Module: rtems-tools Branch: master Commit: a71368892a2010c9a2b8e9ae3ce1c23742b296c3 Changeset: http://git.rtems.org/rtems-tools/commit/?id=a71368892a2010c9a2b8e9ae3ce1c23742b296c3 Author: Dhananjay Balan Date: Fri Aug 9 18:02:18 2013 +0530 Add task subcommand rtems tasks - Prints tasks by index. --- tools/gdb/python/rtems.py | 33 ++++++++++++++++++++++++++++++++- 1 files changed, 32 insertions(+), 1 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index cf1ae07..8eb49c9 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -138,6 +138,36 @@ class rtems_semaphore(gdb.Command): instance.show(from_tty) objects.information.invalidate() +class rtems_task(gdb.Command): + '''tasks subcommand for rtems''' + + api = 'classic' + _class = 'tasks' + + def __init__(self): + self.__doc__ = 'Display the RTEMS tasks by index(s)' + super(rtems_task,self).__init__('rtems task', gdb.COMMAND_STATUS) + + def invoke(self, arg, from_tty): + for val in arg.split(): + try: + index = int(val) + except ValueError: + print "error: %s is not an index" % (val) + return + + try: + obj = objects.information.object_return(self.api, + self._class, + index).dereference() + except IndexError: + print "error: index %s is invalid" % (index) + return + + instance = classic.task(obj) + instance.show(from_tty) + objects.information.invalidate() + # # Main # @@ -147,4 +177,5 @@ gdb.pretty_printers = [] gdb.pretty_printers.append (lookup_function) rtems() rtems_object() -rtems_semaphore() \ No newline at end of file +rtems_semaphore() +rtems_task() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Update Readme. Message-ID: <20140824234537.BBE36700814@git.rtems.org> Module: rtems-tools Branch: master Commit: c63080ddb2231ca0577514e393f4e793f1819d19 Changeset: http://git.rtems.org/rtems-tools/commit/?id=c63080ddb2231ca0577514e393f4e793f1819d19 Author: Dhananjay Balan Date: Sun Jul 28 18:13:22 2013 +0530 Update Readme. ToDo. --- tools/gdb/python/README.md | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/README.md b/tools/gdb/python/README.md index 8858a4f..c471cd9 100644 --- a/tools/gdb/python/README.md +++ b/tools/gdb/python/README.md @@ -4,3 +4,6 @@ rtems-gdb GDB extenstions to RTEMS. See [this blog post for instructions](http://dbalan.github.io/blog/2013/06/23/debugging-rtems-with-gdb/) + +TODO: + - classic abstractions address on id - change this to more proper hierarchy. From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Added register class Message-ID: <20140824234537.D782970080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 04d95ec2b272953b719836a283c35280c816e189 Changeset: http://git.rtems.org/rtems-tools/commit/?id=04d95ec2b272953b719836a283c35280c816e189 Author: Dhananjay Balan Date: Sun Aug 25 18:48:48 2013 +0530 Added register class - sparc.register, basic represenation of sparc's registers. --- tools/gdb/python/sparc.py | 39 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 39 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/sparc.py b/tools/gdb/python/sparc.py index fa7b037..b0e251d 100644 --- a/tools/gdb/python/sparc.py +++ b/tools/gdb/python/sparc.py @@ -68,6 +68,45 @@ class psr: return val +class register: + '''SPARC Registers''' + + def __init__(self,reg): + self.reg = reg + + def global_regs(self): + val = [self.reg['g0_g1']] + + for i in range(2,7): + val.append(int(self.reg['g'+str(i)])) + return val + + def local_regs(self): + val = [] + + for i in range(0,8): + val.append(self.reg['l'+str(i)]) + return val + + def in_regs(self): + val = [] + + for i in range(0,8): + if i==6: + val.append(self.reg['i6_fp']) + else: + val.append(self.reg['i'+str(i)]) + return val + + def out_regs(self): + val = [] + + for i in range(0,8): + if i==6: + val.append(self.reg['o6_sp']) + else: + val.append(self.reg['o'+str(i)]) + return val From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Refactor subcommands Message-ID: <20140824234537.B2DC0700810@git.rtems.org> Module: rtems-tools Branch: master Commit: ddbc5306fa4f92048a8b1e94a35c25227adcf4fb Changeset: http://git.rtems.org/rtems-tools/commit/?id=ddbc5306fa4f92048a8b1e94a35c25227adcf4fb Author: Dhananjay Balan Date: Wed Aug 21 18:30:36 2013 +0530 Refactor subcommands - index commands inherit from a parent class. --- tools/gdb/python/rtems.py | 88 +++++++++++++++++--------------------------- 1 files changed, 34 insertions(+), 54 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 718701c..7d26542 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -65,16 +65,20 @@ class rtems_object(gdb.Command): object.show(from_tty) objects.information.invalidate() -class rtems_semaphore(gdb.Command): - '''Semaphore subcommand for rtems''' +class rtems_index(gdb.Command): + '''Print object by index''' api = 'classic' - _class = 'semaphores' + _class = '' - def __init__(self): - self.__doc__ = 'Display the RTEMS semaphores by index' - super(rtems_semaphore, self).__init__( 'rtems semaphore', - gdb.COMMAND_DATA, gdb.COMPLETE_NONE ) + def __init__(self,command): + super(rtems_index, self).__init__( command, + gdb.COMMAND_DATA, + gdb.COMPLETE_NONE) + + def instance(self,obj): + '''Returns a n instance of corresponding object, the child should extend this''' + return obj def invoke(self, arg, from_tty): for val in arg.split(): @@ -91,68 +95,44 @@ class rtems_semaphore(gdb.Command): print "error: index %s is invalid" % (index) return - instance = classic.semaphore(obj) + instance = self.instance(obj) instance.show(from_tty) objects.information.invalidate() -class rtems_task(gdb.Command): + +class rtems_semaphore(rtems_index): + '''semaphore subcommand''' + _class = 'semaphores' + + def __init__(self): + self.__doc__ = 'Display RTEMS semaphore(s) by index(es)' + super(rtems_semaphore, self).__init__('rtems semaphore') + + def instance(self,obj): + return classic.semaphore(obj) + +class rtems_task(rtems_index): '''tasks subcommand for rtems''' - api = 'classic' _class = 'tasks' def __init__(self): - self.__doc__ = 'Display the RTEMS tasks by index(s)' - super(rtems_task,self).__init__('rtems task', - gdb.COMMAND_DATA, gdb.COMPLETE_NONE) + self.__doc__ = 'Display RTEMS task(s) by index(es)' + super(rtems_task,self).__init__('rtems task') - def invoke(self, arg, from_tty): - for val in arg.split(): - try: - index = int(val) - except ValueError: - raise gdb.GdbError( "Value is not an integer") + def instance(self,obj): + return classic.task(obj) - try: - obj = objects.information.object_return(self.api, - self._class, - index).dereference() - except IndexError: - print "error: index %s is invalid" % (index) - return - instance = classic.task(obj) - instance.show(from_tty) - objects.information.invalidate() - -class rtems_message_queue(gdb.Command): +class rtems_message_queue(rtems_index): '''Message Queue subcommand''' - api = 'classic' _class = 'message_queues' def __init__(self): - self.__doc__ = 'Display the RTEMS message_queue by index(s)' - super(rtems_message_queue,self).__init__('rtems mqueue', - gdb.COMMAND_DATA, - gdb.COMPLETE_NONE) - - def invoke(self, arg, from_tty): - for val in arg.split(): - try: - index = int(val) - except ValueError: - print "error: %s is not an index" % (val) - return + self.__doc__ = 'Display RTEMS message_queue(s) by index(es)' + super(rtems_message_queue,self).__init__('rtems mqueue') - try: - obj = objects.information.object_return(self.api, - self._class, - index).dereference() - except IndexError: - print "error: index %s is invalid" % (index) - return + def instance(self,obj): + return classic.message_queue(obj) - instance = classic.message_queue(obj) - instance.show(from_tty) - objects.information.invalidate() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add sparc PSR Message-ID: <20140824234536.8F521700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 788a71578f394f1938b455385da75f722373232a Changeset: http://git.rtems.org/rtems-tools/commit/?id=788a71578f394f1938b455385da75f722373232a Author: Dhananjay Balan Date: Sun Aug 25 15:14:57 2013 +0530 Add sparc PSR - added a class to print SPARC status register --- tools/gdb/python/sparc.py | 76 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 76 insertions(+), 0 deletions(-) diff --git a/tools/gdb/python/sparc.py b/tools/gdb/python/sparc.py new file mode 100644 index 0000000..fa7b037 --- /dev/null +++ b/tools/gdb/python/sparc.py @@ -0,0 +1,76 @@ +# +# RTEMS gdb extensions +# sparc archetecture specific abstractions + +from helper import test_bit + +class psr: + '''status register''' + + sv_table = { + 0 : 'user', + 1 : 'superviser' + } + + + def __init__(self, psr): + self.psr = psr + + def current_window(self): + return int(self.psr & 0xf) + + def traps(self): + return test_bit(self.psr, 5) + + def prev_superviser(self): + return int(test_bit(self.psr,6)) + + def superviser(self): + return int(test_bit(self.psr,7)) + + def interrupt_level(self): + # bits 8 to 11 + return (self.spr & 0x780) >> 7 + + def floating_point_status(self): + return test_bit(self.psr, 12) + + def coproc_status(self): + return test_bit(self.psr,13) + + def carry(self): + return test_bit(self.psr, 20) + + def overflow(self): + return test_bit(self.psr, 21) + + def zero(self): + return test_bit(self.psr, 22) + + def icc(self): + n = test_bit(self.psr,23) + z = test_bit(self.psr,22) + v = test_bit(self.psr,21) + c = test_bit(self.psr,20) + return (n,z,v,c) + + def to_string(self): + val = " Status Register" + val += "\n R Window : " + str(self.current_window()) + val += "\n Traps Enabled : " + str(self.traps()) + val += "\n Flaoting Point : " + str(self.floating_point_status()) + val += "\n Coprocessor : " + str(self.coproc_status()) + val += "\n Processor Mode : " + self.sv_table[self.superviser()] + val += "\n Prev. Mode : " + self.sv_table[self.superviser()] + val += "\n Carry : " + str(int(self.carry())) + val += "\n Overflow : " + str(int(self.overflow())) + val += "\n Zero : " + str(int(self.zero())) + + return val + + + + + + + From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Fix wdticks command Message-ID: <20140824234538.0C7BC700810@git.rtems.org> Module: rtems-tools Branch: master Commit: 1fcff75505e4be2916bcd273a3670828363a0f67 Changeset: http://git.rtems.org/rtems-tools/commit/?id=1fcff75505e4be2916bcd273a3670828363a0f67 Author: Dhananjay Balan Date: Mon Aug 26 20:53:57 2013 +0530 Fix wdticks command - Type is Chain_Control - chain.node.next -> null --- tools/gdb/python/objects.py | 1 + tools/gdb/python/rtems.py | 9 +++++++-- tools/gdb/python/watchdog.py | 17 +++++++++++------ 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index f4ae5e1..ae2a4c7 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -14,6 +14,7 @@ class infotables: tables_types = { 'internal/time' : ('TOD_Control', '_TOD'), + 'internal/wdticks' : ('Chain_Control', '_Watchdog_Ticks_chain'), 'classic/tasks' : ('Thread_Control', '_RTEMS_tasks_Information'), 'classic/timers' : ('Timer_Control', '_Timer_Information'), diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 64c7f1a..340c7ff 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -11,6 +11,7 @@ import re import objects import threads import chains +import watchdog import supercore import classic @@ -227,10 +228,14 @@ class rtems_watchdog_chain(gdb.Command): return nd = inst.first() + i = 0 + print ' Ticks Chain' while not nd.null(): wd = watchdog.control(nd.cast('Watchdog_Control')) - wd.show() - nd = nd.next() + print ' #'+str(i) + print wd.to_string() + nd.next() + i += 1 class rtems_wdt(rtems_watchdog_chain): diff --git a/tools/gdb/python/watchdog.py b/tools/gdb/python/watchdog.py index fef2f39..71a1816 100644 --- a/tools/gdb/python/watchdog.py +++ b/tools/gdb/python/watchdog.py @@ -52,10 +52,15 @@ class control: addr = self.ctrl['routine'] return str(addr) + def to_string(self): + val = "" + val += " State:" + str(self.state()) + val += "\n Intial Interval:" + str(self.initial()) + val += "\n Delta Interval:"+ str(self.delta_interval()) + val += "\n Start time:" + str(self.start_time()) + val += "\n Stop time:" + str(self.stop_time()) + val += "\n WD Routine:" + str(self.routine()) + return val + def show(self): - print " State:", self.state() - print " Intial Interval:", self.initial() - print " Delta Interval:", self.delta_interval() - print " Start time:", self.start_time() - print " Stop time:", self.stop_time() - print " WD Routine:", self.routine() \ No newline at end of file + print self.to_string() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add watchdog ticks command. Message-ID: <20140824234537.6F1DE70080E@git.rtems.org> Module: rtems-tools Branch: master Commit: a7176a8a7e5542d9371026b135a864f15d79e1b5 Changeset: http://git.rtems.org/rtems-tools/commit/?id=a7176a8a7e5542d9371026b135a864f15d79e1b5 Author: Dhananjay Balan Date: Sun Aug 25 23:21:44 2013 +0530 Add watchdog ticks command. - ToDo : Fix watchdog states. --- tools/gdb/python/chains.py | 3 +++ tools/gdb/python/main.py | 3 ++- tools/gdb/python/rtems.py | 35 +++++++++++++++++++++++++++++++++++ tools/gdb/python/watchdog.py | 10 +++------- 4 files changed, 43 insertions(+), 8 deletions(-) diff --git a/tools/gdb/python/chains.py b/tools/gdb/python/chains.py index 0826ba9..ef33ed6 100644 --- a/tools/gdb/python/chains.py +++ b/tools/gdb/python/chains.py @@ -48,3 +48,6 @@ class control: def last(self): return node(self.ctrl['Tail']['Node']) + def empty(self): + if self.last() == self.first().next(): + return True diff --git a/tools/gdb/python/main.py b/tools/gdb/python/main.py index 0ec4a28..a0ff7dc 100644 --- a/tools/gdb/python/main.py +++ b/tools/gdb/python/main.py @@ -17,4 +17,5 @@ rtems.rtems_object() rtems.rtems_semaphore() rtems.rtems_task() rtems.rtems_message_queue() -rtems.rtems_tod() \ No newline at end of file +rtems.rtems_tod() +rtems.rtems_wdt() \ No newline at end of file diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index cf2000a..64c7f1a 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -10,6 +10,7 @@ import re import objects import threads +import chains import supercore import classic @@ -205,3 +206,37 @@ class rtems_tod(gdb.Command): instance = supercore.time_of_day(obj) instance.show() objects.information.invalidate() + +class rtems_watchdog_chain(gdb.Command): + '''Print watchdog ticks chain''' + + api = 'internal' + _class = '' + + def __init__(self,command): + super(rtems_watchdog_chain, self).__init__ \ + (command, gdb.COMMAND_DATA, gdb.COMPLETE_NONE) + + def invoke(self, arg, from_tty): + obj = objects.information.object_return(self.api, self._class) + + inst = chains.control(obj) + + if inst.empty(): + print ' error: empty chain' + return + + nd = inst.first() + while not nd.null(): + wd = watchdog.control(nd.cast('Watchdog_Control')) + wd.show() + nd = nd.next() + +class rtems_wdt(rtems_watchdog_chain): + + _class = 'wdticks' + + def __init__(self): + self.__doc__ = 'Display watchdog ticks chain' + super(rtems_wdt, self).__init__('rtems wdticks') + diff --git a/tools/gdb/python/watchdog.py b/tools/gdb/python/watchdog.py index 3678550..fef2f39 100644 --- a/tools/gdb/python/watchdog.py +++ b/tools/gdb/python/watchdog.py @@ -12,11 +12,6 @@ import objects class state: - INACTIVE = 0 - BEING_INSERTED = 1 - ACTIVE = 2 - REMOVE_IT = 3 - states = { 0: 'inactive', 1: 'being-inserted', @@ -35,9 +30,10 @@ class control: def __init__(self, ctrl): self.ctrl = ctrl - # Not sure if an extra class is needed. + # ToDo: fix this.1 def state(self): - return state(int(self.ctrl['state'])).to_string() + return state(1).to_string() + #return state(int(self.ctrl['state'])).to_string() def initial(self): return self.ctrl['initial'] From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add cpu registers to task output. Message-ID: <20140824234538.00794700679@git.rtems.org> Module: rtems-tools Branch: master Commit: bd0b98d55e4bcb29ce0631e6c717f873739bf80b Changeset: http://git.rtems.org/rtems-tools/commit/?id=bd0b98d55e4bcb29ce0631e6c717f873739bf80b Author: Dhananjay Balan Date: Mon Aug 26 22:30:25 2013 +0530 Add cpu registers to task output. --- tools/gdb/python/classic.py | 5 ++ tools/gdb/python/sparc.py | 135 ++++++++++++++++++++++++++----------------- 2 files changed, 86 insertions(+), 54 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 261f648..e492657 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -16,6 +16,7 @@ import threads import watchdog import heaps import supercore +import sparc class attribute: """The Classic API attribute.""" @@ -155,6 +156,8 @@ class task: self.task = \ threads.control(self.object) self.wait_info = self.task.wait_info() + # ToDo: Insert platform dep. code here. + self.regs = sparc.register(self.object['Registers']) def show(self, from_tty): print ' Name:', self.task.name() @@ -163,6 +166,8 @@ class task: print ' Real:', self.task.real_priority() print ' Preempt:', self.task.preemptible() print ' T Budget:', self.task.cpu_time_budget() + print ' Regsters:' + self.regs.show() class message_queue: diff --git a/tools/gdb/python/sparc.py b/tools/gdb/python/sparc.py index b0e251d..70ef5d3 100644 --- a/tools/gdb/python/sparc.py +++ b/tools/gdb/python/sparc.py @@ -4,72 +4,74 @@ from helper import test_bit -class psr: - '''status register''' - sv_table = { - 0 : 'user', - 1 : 'superviser' - } +class register: + '''SPARC Registers''' - def __init__(self, psr): - self.psr = psr + class psr: + '''status register''' - def current_window(self): - return int(self.psr & 0xf) + sv_table = { + 0 : 'user', + 1 : 'superviser' + } - def traps(self): - return test_bit(self.psr, 5) - def prev_superviser(self): - return int(test_bit(self.psr,6)) + def __init__(self, psr): + self.psr = psr - def superviser(self): - return int(test_bit(self.psr,7)) + def current_window(self): + return int(self.psr & 0xf) - def interrupt_level(self): - # bits 8 to 11 - return (self.spr & 0x780) >> 7 + def traps(self): + return test_bit(self.psr, 5) - def floating_point_status(self): - return test_bit(self.psr, 12) + def prev_superviser(self): + return int(test_bit(self.psr,6)) - def coproc_status(self): - return test_bit(self.psr,13) + def superviser(self): + return int(test_bit(self.psr,7)) - def carry(self): - return test_bit(self.psr, 20) + def interrupt_level(self): + # bits 8 to 11 + return (self.spr & 0x780) >> 7 - def overflow(self): - return test_bit(self.psr, 21) + def floating_point_status(self): + return test_bit(self.psr, 12) - def zero(self): - return test_bit(self.psr, 22) + def coproc_status(self): + return test_bit(self.psr,13) - def icc(self): - n = test_bit(self.psr,23) - z = test_bit(self.psr,22) - v = test_bit(self.psr,21) - c = test_bit(self.psr,20) - return (n,z,v,c) + def carry(self): + return test_bit(self.psr, 20) - def to_string(self): - val = " Status Register" - val += "\n R Window : " + str(self.current_window()) - val += "\n Traps Enabled : " + str(self.traps()) - val += "\n Flaoting Point : " + str(self.floating_point_status()) - val += "\n Coprocessor : " + str(self.coproc_status()) - val += "\n Processor Mode : " + self.sv_table[self.superviser()] - val += "\n Prev. Mode : " + self.sv_table[self.superviser()] - val += "\n Carry : " + str(int(self.carry())) - val += "\n Overflow : " + str(int(self.overflow())) - val += "\n Zero : " + str(int(self.zero())) + def overflow(self): + return test_bit(self.psr, 21) - return val + def zero(self): + return test_bit(self.psr, 22) -class register: - '''SPARC Registers''' + def icc(self): + n = test_bit(self.psr,23) + z = test_bit(self.psr,22) + v = test_bit(self.psr,21) + c = test_bit(self.psr,20) + return (n,z,v,c) + + def to_string(self): + val = " Status Register" + val += "\n R Window : " + str(self.current_window()) + val += "\n Traps Enabled : " + str(self.traps()) + val += "\n Flaoting Point : " + str(self.floating_point_status()) + val += "\n Coprocessor : " + str(self.coproc_status()) + val += "\n Processor Mode : " + self.sv_table[self.superviser()] + val += "\n Prev. Mode : " + self.sv_table[self.superviser()] + val += "\n Carry : " + str(int(self.carry())) + val += "\n Overflow : " + str(int(self.overflow())) + val += "\n Zero : " + str(int(self.zero())) + + return val def __init__(self,reg): self.reg = reg @@ -108,8 +110,33 @@ class register: val.append(self.reg['o'+str(i)]) return val - - - - - + def status(self): + return self.psr(self.reg['psr']) + + def show(self): + print ' Global Regs:', + print ' [', + for i in self.global_regs(): + print str(i)+',', + print '\b\b ]' + + print ' Local Regs:', + print ' [', + for i in self.local_regs(): + print str(i)+',', + print '\b\b ]' + + print ' In Regs:', + print ' [', + for i in self.in_regs(): + print str(i)+',', + print '\b\b ]' + + print ' Out Regs:', + print ' [', + for i in self.out_regs(): + print str(i)+',', + print '\b\b ]' + + sr = self.status() + print sr.to_string() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:35 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:35 -0500 Subject: [rtems-tools commit] Add subcommand Message-ID: <20140824234537.DBFD6700810@git.rtems.org> Module: rtems-tools Branch: master Commit: a245635a2e3c7b9ef5ebfc480b6115544c3d4340 Changeset: http://git.rtems.org/rtems-tools/commit/?id=a245635a2e3c7b9ef5ebfc480b6115544c3d4340 Author: Dhananjay Balan Date: Sat Aug 24 15:26:16 2013 +0530 Add subcommand rtems tod - prints the time of day. --- tools/gdb/python/main.py | 3 ++- tools/gdb/python/objects.py | 20 ++++++++++++++------ tools/gdb/python/rtems.py | 21 +++++++++++++++++++++ tools/gdb/python/supercore.py | 25 +++++++++++++++++++++++++ 4 files changed, 62 insertions(+), 7 deletions(-) diff --git a/tools/gdb/python/main.py b/tools/gdb/python/main.py index 2ef475a..0ec4a28 100644 --- a/tools/gdb/python/main.py +++ b/tools/gdb/python/main.py @@ -16,4 +16,5 @@ rtems.rtems() rtems.rtems_object() rtems.rtems_semaphore() rtems.rtems_task() -rtems.rtems_message_queue() \ No newline at end of file +rtems.rtems_message_queue() +rtems.rtems_tod() \ No newline at end of file diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index 1a64a8d..58c2730 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -13,6 +13,8 @@ class infotables: """Manage the object information tables.""" tables_types = { + 'internal/time' : ('TOD_Control', '_TOD'), + 'classic/tasks' : ('Thread_Control', '_RTEMS_tasks_Information'), 'classic/timers' : ('Timer_Control', '_Timer_Information'), 'classic/semaphores' : ('Semaphore_Control', '_Semaphore_Information'), @@ -64,15 +66,21 @@ class infotables: index = id.index() return self.object_return(api, _class, index) - def object_return(self, api, _class, index): + def object_return(self, api, _class, index=-1): n = self.name(api, _class) self.load(n) - max = self.maximum(api, _class) - if index > max: - raise IndexError('object index out of range (%d)' % (max)) + table_type = self.tables_types[n] - expr = '(' + table_type[0] + '*)' + \ - table_type[1] + '.local_table[' + str(index) + ']' + + if api == 'internal': + expr = '(' + table_type[0] + ')' + table_type[1] + + else: + max = self.maximum(api, _class) + if index > max: + raise IndexError('object index out of range (%d)' % (max)) + expr = '(' + table_type[0] + '*)' + \ + table_type[1] + '.local_table[' + str(index) + ']' return gdb.parse_and_eval(expr) def is_string(self, api, _class): diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index b142f23..cf2000a 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -10,6 +10,7 @@ import re import objects import threads +import supercore import classic @@ -184,3 +185,23 @@ class rtems_barrier(rtems_index): def instance(self, obj): return classic.barrier(obj) +class rtems_tod(gdb.Command): + '''Print rtems time of day''' + + api = 'internal' + _class = 'time' + + def __init__(self): + self.__doc__ = 'Display RTEMS time of day' + super(rtems_tod, self).__init__ \ + ('rtems tod', gdb.COMMAND_STATUS,gdb.COMPLETE_NONE) + + def invoke(self, arg, from_tty): + + if arg: + print "warning: commad takes no arguments!" + + obj = objects.information.object_return(self.api,self._class) + instance = supercore.time_of_day(obj) + instance.show() + objects.information.invalidate() diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py index e60813a..6116626 100644 --- a/tools/gdb/python/supercore.py +++ b/tools/gdb/python/supercore.py @@ -5,6 +5,31 @@ import threads import helper +class time_of_day: + '''Manage time of day object''' + + def __init__(self, tod): + self.tod = tod + + def now(self): + return self.tod['now'] + + def timer(self): + return self.tod['uptime'] + + def is_set(self): + return bool(self.tod['is_set']) + + def show(self): + print ' Time Of Day' + + if not self.is_set(): + print ' Application has not set a TOD' + + print ' Now:', self.now() + print ' Uptime:', self.timer() + + class message_queue: '''Manage a Supercore message_queue''' From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Add subcommand semaphore Message-ID: <20140824234537.9CEC4700679@git.rtems.org> Module: rtems-tools Branch: master Commit: 479717912afe27705874805f3a3786dd9d665bb6 Changeset: http://git.rtems.org/rtems-tools/commit/?id=479717912afe27705874805f3a3786dd9d665bb6 Author: Dhananjay Balan Date: Fri Aug 9 14:25:43 2013 +0530 Add subcommand semaphore rtems semaphore : prints rtems semaphores by index number --- tools/gdb/python/rtems.py | 31 +++++++++++++++++++++++++++++-- 1 files changed, 29 insertions(+), 2 deletions(-) diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 20f44a2..cf1ae07 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -85,7 +85,7 @@ class rtems_object(gdb.Command): } def __init__(self): - self.__doc__ = 'Display the RTEMS object given a numeric ID.' + self.__doc__ = 'Display the RTEMS object given a numeric ID (Or a reference to rtems_object).' super(rtems_object, self).__init__('rtems object', gdb.COMMAND_STATUS) @@ -112,6 +112,32 @@ class rtems_object(gdb.Command): object.show(from_tty) objects.information.invalidate() +class rtems_semaphore(gdb.Command): + '''Semaphore subcommand for rtems''' + + api = 'classic' + _class = 'semaphores' + + def __init__(self): + self.__doc__ = 'Display the RTEMS semaphores by index' + super(rtems_semaphore, self).__init__('rtems semaphore', + gdb.COMMAND_STATUS) + + def invoke(self, arg, from_tty): + for val in arg.split(): + try: + index = int(val) + except ValueError: + print "error: %s is not an index" % (val) + return + + obj = objects.information.object_return( self.api, + self._class, + int(index)).dereference() + instance = classic.semaphore(obj) + instance.show(from_tty) + objects.information.invalidate() + # # Main # @@ -120,4 +146,5 @@ build_rtems_dict() gdb.pretty_printers = [] gdb.pretty_printers.append (lookup_function) rtems() -rtems_object() \ No newline at end of file +rtems_object() +rtems_semaphore() \ No newline at end of file From chrisj at rtems.org Sun Aug 24 23:45:34 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:34 -0500 Subject: [rtems-tools commit] Fix Task and state printer bugs. Message-ID: <20140824234537.848F8700810@git.rtems.org> Module: rtems-tools Branch: master Commit: e60a5eec0b1e8b16d984e4baf7dccb3323b88928 Changeset: http://git.rtems.org/rtems-tools/commit/?id=e60a5eec0b1e8b16d984e4baf7dccb3323b88928 Author: Dhananjay Balan Date: Tue Jul 30 09:12:35 2013 +0530 Fix Task and state printer bugs. - Removed ITRON api objects in thread control - fixes #1 --- tools/gdb/python/classic.py | 5 ++--- tools/gdb/python/supercore_printer.py | 1 + tools/gdb/python/threads.py | 6 ------ 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 617a0db..50514ff 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -153,17 +153,16 @@ class task: self.id = id; self.task = \ threads.control(objects.information.object(self.id).dereference()) + self.wait_info = self.task.wait_info() def show(self, from_tty): print ' Name:', self.task.name() print ' State:', self.task.current_state() print ' Current:', self.task.current_priority() print ' Real:', self.task.real_priority() - print ' Suspends:', self.task.suspends() - print ' Post Ext:', self.task.post_task_switch_ext() print ' Preempt:', self.task.preemptible() print ' T Budget:', self.task.cpu_time_budget() - wait_info = self.task.wait_info() + class message_queue: "Print classic messege queue" diff --git a/tools/gdb/python/supercore_printer.py b/tools/gdb/python/supercore_printer.py index ec1d416..3ce8110 100644 --- a/tools/gdb/python/supercore_printer.py +++ b/tools/gdb/python/supercore_printer.py @@ -3,6 +3,7 @@ # import objects import itertools +import threads class id: """Print an object given the ID. Print using the struct display hint and an diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py index b5ac3fb..77c7efa 100644 --- a/tools/gdb/python/threads.py +++ b/tools/gdb/python/threads.py @@ -145,12 +145,6 @@ class control: def real_priority(self): return self.ctrl['real_priority'] - def suspends(self): - return self.ctrl['suspend_count'] - - def post_task_switch_ext(self): - return self.ctrl['do_post_task_switch_extension'] - def preemptible(self): return self.ctrl['is_preemptible'] From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Support classic/partitions Message-ID: <20140824234538.07EEF70080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 09086b415db7bb08cca41fc3fff212bbaece327a Changeset: http://git.rtems.org/rtems-tools/commit/?id=09086b415db7bb08cca41fc3fff212bbaece327a Author: Dhananjay Balan Date: Sat Jul 27 14:29:19 2013 +0530 Support classic/partitions Added support for partition object. --- tools/gdb/python/classic.py | 29 ++++++++++++++++++++++++++--- tools/gdb/python/classic_printer.py | 4 +++- tools/gdb/python/rtems.py | 3 ++- 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 1f5daf2..f7d4dfc 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -40,7 +40,8 @@ class attribute: 'priority', 'barrier'], 'message_queue' : ['priority', - 'scope'] + 'scope'], + 'partition' : ['scope'] } masks = { @@ -163,7 +164,7 @@ class task: wait_info = self.task.wait_info() class message_queue: - "Print a classic messege queue" + "Print classic messege queue" def __init__(self,id): self.id = id @@ -193,4 +194,26 @@ class timer: def show(self, from_tty): print ' Name:', self.object_control.name() - self.watchdog.show() \ No newline at end of file + self.watchdog.show() + +class partition: + ''' Print a rtems partition ''' + + def __init__(self, id): + self.id = id + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.attr = attribute(self.object['attribute_set'], 'partition') + self.starting_addr = self.object['starting_address'] + self.length = self.object['length'] + self.buffer_size = self.object['buffer_size'] + self.used_blocks = self.object['number_of_used_blocks'] + + def show(self, from_tty): + # ToDo: the printing still somewhat crude. + print ' Name:', self.object_control.name() + print ' Attr:', self.attr.to_string() + print ' Length:', self.length + print 'Buffer Size:', self.buffer_size + print 'Used Blocks:', self.used_blocks + diff --git a/tools/gdb/python/classic_printer.py b/tools/gdb/python/classic_printer.py index a25d756..86e0eeb 100644 --- a/tools/gdb/python/classic_printer.py +++ b/tools/gdb/python/classic_printer.py @@ -1,6 +1,8 @@ # # RTEMS Classic pretty printers for GDB # +import classic +import gdb class attribute: @@ -12,7 +14,7 @@ class attribute: return gdb.Value(self.attr.to_string()) class semaphore: - """ToDo: Print a Semaphore_Control object. Print using the struct display hint + """Print a Semaphore_Control object. Print using the struct display hint and an iterator. """ class iterator: diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index bd2d8e4..eac5042 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -78,7 +78,8 @@ class rtems_object(gdb.Command): 'classic/semaphores': lambda id: classic.semaphore(id), 'classic/tasks': lambda id: classic.task(id), 'classic/message_queues': lambda id: classic.message_queue(id), - 'classic/timers' : lambda id: classic.timer(id) + 'classic/timers' : lambda id: classic.timer(id), + 'classic/partitions' : lambda id: classic.partition(id) } def __init__(self): From chrisj at rtems.org Sun Aug 24 23:45:33 2014 From: chrisj at rtems.org (Chris Johns) Date: Sun, 24 Aug 2014 18:45:33 -0500 Subject: [rtems-tools commit] Added support for classic/timers. Message-ID: <20140824234536.A0DEA70080E@git.rtems.org> Module: rtems-tools Branch: master Commit: 086e689955e3b0692d00bf2fc0ea1be7ed244e07 Changeset: http://git.rtems.org/rtems-tools/commit/?id=086e689955e3b0692d00bf2fc0ea1be7ed244e07 Author: Dhananjay Balan Date: Wed Jul 17 16:18:57 2013 +0530 Added support for classic/timers. --- tools/gdb/python/classic.py | 16 +++++++++++++++- tools/gdb/python/rtems.py | 3 ++- tools/gdb/python/watchdog.py | 19 ++++++++++++++----- 3 files changed, 31 insertions(+), 7 deletions(-) diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index 9af11df..1f5daf2 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -11,6 +11,7 @@ import re import objects import threads +import watchdog import supercore class attribute: @@ -179,4 +180,17 @@ class message_queue: print ' Name:', self.object_control.name() print ' Attr:', self.attr.to_string() - self.core_control.show() \ No newline at end of file + self.core_control.show() + +class timer: + '''Print a classic timer''' + + def __init__(self, id): + self.id = id + self.object = objects.information.object(self.id).dereference() + self.object_control = objects.control(self.object['Object']) + self.watchdog = watchdog.control(self.object['Ticker']) + + def show(self, from_tty): + print ' Name:', self.object_control.name() + self.watchdog.show() \ No newline at end of file diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 4622ced..bd2d8e4 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -77,7 +77,8 @@ class rtems_object(gdb.Command): objects = { 'classic/semaphores': lambda id: classic.semaphore(id), 'classic/tasks': lambda id: classic.task(id), - 'classic/message_queues': lambda id: classic.message_queue(id) + 'classic/message_queues': lambda id: classic.message_queue(id), + 'classic/timers' : lambda id: classic.timer(id) } def __init__(self): diff --git a/tools/gdb/python/watchdog.py b/tools/gdb/python/watchdog.py index 0766575..3678550 100644 --- a/tools/gdb/python/watchdog.py +++ b/tools/gdb/python/watchdog.py @@ -16,14 +16,14 @@ class state: BEING_INSERTED = 1 ACTIVE = 2 REMOVE_IT = 3 - + states = { 0: 'inactive', 1: 'being-inserted', 2: 'active', 3: 'remove-it' } - + def __init__(self, s): self.s = s @@ -35,8 +35,9 @@ class control: def __init__(self, ctrl): self.ctrl = ctrl + # Not sure if an extra class is needed. def state(self): - return state(self.ctrl['state']).to_string() + return state(int(self.ctrl['state'])).to_string() def initial(self): return self.ctrl['initial'] @@ -50,7 +51,15 @@ class control: def stop_time(self): return self.ctrl['stop_time'] + # ToDo: Better printing of watchdog. def routine(self): addr = self.ctrl['routine'] - sym = gdb.lookup_symbol(addr) - print sym + return str(addr) + + def show(self): + print " State:", self.state() + print " Intial Interval:", self.initial() + print " Delta Interval:", self.delta_interval() + print " Start time:", self.start_time() + print " Stop time:", self.stop_time() + print " WD Routine:", self.routine() \ No newline at end of file From sebh at rtems.org Mon Aug 25 06:50:14 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 25 Aug 2014 01:50:14 -0500 Subject: [rtems commit] rtems: Inline rtems_clock_get_ticks_since_boot() Message-ID: <20140825065014.CF784700812@git.rtems.org> Module: rtems Branch: master Commit: f553c6ebbe4c61b239da07e6b7d70afa3b10828e Changeset: http://git.rtems.org/rtems/commit/?id=f553c6ebbe4c61b239da07e6b7d70afa3b10828e Author: Sebastian Huber Date: Fri Aug 22 16:39:47 2014 +0200 rtems: Inline rtems_clock_get_ticks_since_boot() Update documentation. --- cpukit/rtems/Makefile.am | 1 - cpukit/rtems/include/rtems/rtems/clock.h | 14 +++++----- cpukit/rtems/src/clockgettickssinceboot.c | 31 ----------------------- cpukit/score/include/rtems/score/watchdog.h | 7 +++++ cpukit/score/include/rtems/score/watchdogimpl.h | 8 ------ doc/user/clock.t | 31 +++++++--------------- 6 files changed, 24 insertions(+), 68 deletions(-) diff --git a/cpukit/rtems/Makefile.am b/cpukit/rtems/Makefile.am index b00e251..a1fafb1 100644 --- a/cpukit/rtems/Makefile.am +++ b/cpukit/rtems/Makefile.am @@ -151,7 +151,6 @@ librtems_a_SOURCES += src/barrierdata.c librtems_a_SOURCES += src/clockget.c librtems_a_SOURCES += src/clockgetsecondssinceepoch.c librtems_a_SOURCES += src/clockgettickspersecond.c -librtems_a_SOURCES += src/clockgettickssinceboot.c librtems_a_SOURCES += src/clockgettod.c librtems_a_SOURCES += src/clockgettodtimeval.c librtems_a_SOURCES += src/clockgetuptime.c diff --git a/cpukit/rtems/include/rtems/rtems/clock.h b/cpukit/rtems/include/rtems/rtems/clock.h index d80218d..ff71665 100644 --- a/cpukit/rtems/include/rtems/rtems/clock.h +++ b/cpukit/rtems/include/rtems/rtems/clock.h @@ -149,15 +149,15 @@ rtems_status_code rtems_clock_get_seconds_since_epoch( ); /** - * @brief Obtain Ticks Since Boot + * @brief Gets the current ticks counter value. * - * This routine implements the rtems_clock_get_ticks_since_boot - * directive. - * - * @retval This method returns the number of ticks since boot. It cannot - * fail since RTEMS always keeps a running count of ticks since boot. + * @return The current tick counter value. With a 1ms clock tick, this counter + * overflows after 50 days since boot. */ -rtems_interval rtems_clock_get_ticks_since_boot(void); +RTEMS_INLINE_ROUTINE rtems_interval rtems_clock_get_ticks_since_boot(void) +{ + return _Watchdog_Ticks_since_boot; +} /** * @brief Obtain Ticks Per Seconds diff --git a/cpukit/rtems/src/clockgettickssinceboot.c b/cpukit/rtems/src/clockgettickssinceboot.c deleted file mode 100644 index 4aced96..0000000 --- a/cpukit/rtems/src/clockgettickssinceboot.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file - * - * @brief Obtain Ticks Since Boot - * @ingroup ClassicClock - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#if HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include -#include -#include -#include - -rtems_interval rtems_clock_get_ticks_since_boot(void) -{ - return _Watchdog_Ticks_since_boot; -} diff --git a/cpukit/score/include/rtems/score/watchdog.h b/cpukit/score/include/rtems/score/watchdog.h index 7327f77..06c87a1 100644 --- a/cpukit/score/include/rtems/score/watchdog.h +++ b/cpukit/score/include/rtems/score/watchdog.h @@ -124,6 +124,13 @@ typedef struct { void *user_data; } Watchdog_Control; +/** + * @brief The watchdog ticks counter. + * + * With a 1ms watchdog tick, this counter overflows after 50 days since boot. + */ +SCORE_EXTERN volatile Watchdog_Interval _Watchdog_Ticks_since_boot; + /**@}*/ #ifdef __cplusplus diff --git a/cpukit/score/include/rtems/score/watchdogimpl.h b/cpukit/score/include/rtems/score/watchdogimpl.h index 72b6b3b..d50e279 100644 --- a/cpukit/score/include/rtems/score/watchdogimpl.h +++ b/cpukit/score/include/rtems/score/watchdogimpl.h @@ -85,14 +85,6 @@ SCORE_EXTERN volatile uint32_t _Watchdog_Sync_level; SCORE_EXTERN volatile uint32_t _Watchdog_Sync_count; /** - * @brief The number of ticks since the system was booted. - * - * This contains the number of ticks since the system was booted. - */ - -SCORE_EXTERN volatile Watchdog_Interval _Watchdog_Ticks_since_boot; - -/** * @brief Watchdog chain which is managed at ticks. * * This is the watchdog chain which is managed at ticks. diff --git a/doc/user/clock.t b/doc/user/clock.t index fdbd91d..921d1cb 100644 --- a/doc/user/clock.t +++ b/doc/user/clock.t @@ -20,7 +20,7 @@ the clock manager are: @item @code{@value{DIRPREFIX}clock_get_tod_timeval} - Get date and time in timeval format @item @code{@value{DIRPREFIX}clock_get_seconds_since_epoch} - Get seconds since epoch @item @code{@value{DIRPREFIX}clock_get_ticks_per_second} - Get ticks per second - at item @code{@value{DIRPREFIX}clock_get_ticks_since_boot} - Get ticks since boot + at item @code{@value{DIRPREFIX}clock_get_ticks_since_boot} - Get current ticks counter value @item @code{@value{DIRPREFIX}clock_get_uptime} - Get time since boot @item @code{@value{DIRPREFIX}clock_get_uptime_timeval} - Get time since boot in timeval format @item @code{@value{DIRPREFIX}clock_get_uptime_seconds} - Get seconds since boot @@ -569,19 +569,16 @@ application has configured. This directive is callable from an ISR. -This directive will not cause the running task to be -preempted. Re-initializing RTEMS causes the system date and -time to be reset to an uninitialized state. Another call to - at code{@value{DIRPREFIX}clock_set} is required to re-initialize the -system date and time to application specific specifications. +This directive will not cause the running task to be preempted. @c @c @c @page - at subsection CLOCK_GET_TICKS_SINCE_BOOT - Get ticks since boot + at subsection CLOCK_GET_TICKS_SINCE_BOOT - Get current ticks counter value @cindex obtain ticks since boot + at cindex get current ticks counter value @subheading CALLING SEQUENCE: @@ -604,25 +601,17 @@ NONE @subheading DESCRIPTION: -This directive returns the number of clock ticks that have elapsed -since the system was booted. This is the historical measure of uptime -in an RTEMS system. The newer service - at code{@value{DIRPREFIX}clock_get_uptime} is another and potentially -more accurate way of obtaining similar information. +This directive returns the current tick counter value. With a 1ms clock tick, +this counter overflows after 50 days since boot. This is the historical +measure of uptime in an RTEMS system. The newer service + at code{@value{DIRPREFIX}clock_get_uptime} is another and potentially more +accurate way of obtaining similar information. @subheading NOTES: This directive is callable from an ISR. -This directive will not cause the running task to be -preempted. Re-initializing RTEMS causes the system date and -time to be reset to an uninitialized state. Another call to - at code{@value{DIRPREFIX}clock_set} is required to re-initialize the -system date and time to application specific specifications. - -This directive simply returns the number of times the dirivective - at code{@value{DIRPREFIX}clock_tick} has been invoked since the -system was booted. +This directive will not cause the running task to be preempted. @c @c From sebh at rtems.org Mon Aug 25 06:50:14 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 25 Aug 2014 01:50:14 -0500 Subject: [rtems commit] score: Add missing define to cache manager Message-ID: <20140825065014.F3D3C70080E@git.rtems.org> Module: rtems Branch: master Commit: e7a42a0cfbafc2311888780b086010aef6556311 Changeset: http://git.rtems.org/rtems/commit/?id=e7a42a0cfbafc2311888780b086010aef6556311 Author: Daniel Cederman Date: Mon Aug 25 08:48:17 2014 +0200 score: Add missing define to cache manager --- c/src/lib/libcpu/shared/src/cache_manager.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c index 7dd408f..7ff1166 100644 --- a/c/src/lib/libcpu/shared/src/cache_manager.c +++ b/c/src/lib/libcpu/shared/src/cache_manager.c @@ -435,6 +435,7 @@ rtems_cache_disable_data( void ) * and then perform the invalidations. */ +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) #if !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) static void _invalidate_multiple_instruction_lines_no_range_functions( @@ -462,6 +463,7 @@ _invalidate_multiple_instruction_lines_no_range_functions( } } #endif +#endif void rtems_cache_invalidate_multiple_instruction_lines( From sebh at rtems.org Mon Aug 25 07:02:40 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 25 Aug 2014 02:02:40 -0500 Subject: [rtems commit] bsp/mpc55xx: Limit flash support to MPC55[56]X Message-ID: <20140825070240.6C219700810@git.rtems.org> Module: rtems Branch: master Commit: 0a314839012ab765a70df05eaadc4dba7440223b Changeset: http://git.rtems.org/rtems/commit/?id=0a314839012ab765a70df05eaadc4dba7440223b Author: Sebastian Huber Date: Mon Aug 25 09:09:45 2014 +0200 bsp/mpc55xx: Limit flash support to MPC55[56]X --- .../libcpu/powerpc/mpc55xx/misc/flash_support.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c index b286b51..74bbd39 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c +++ b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c @@ -38,7 +38,7 @@ #include #include -#if MPC55XX_CHIP_TYPE / 100 == 55 +#if MPC55XX_CHIP_FAMILY == 555 || MPC55XX_CHIP_FAMILY == 556 /* Set up the memory ranges for the flash on * the MPC5553, MPC5554, MPC5566 and MPC5567. From sebh at rtems.org Mon Aug 25 07:22:35 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 25 Aug 2014 02:22:35 -0500 Subject: [rtems commit] bsp/mpc55xx: Add defines for MPC5668 Message-ID: <20140825072235.9D691700810@git.rtems.org> Module: rtems Branch: master Commit: f3237a3c3bbe5a298b5ae30a36b24e6f601c6f8b Changeset: http://git.rtems.org/rtems/commit/?id=f3237a3c3bbe5a298b5ae30a36b24e6f601c6f8b Author: Sebastian Huber Date: Mon Aug 25 09:30:53 2014 +0200 bsp/mpc55xx: Add defines for MPC5668 --- .../libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h | 14 +++++++------- c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h | 6 ++++++ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h index bf388ad..b7a1793 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h +++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h @@ -5184,7 +5184,7 @@ extern "C" { } B; } EISR; /* External Interrupt Status Register */ - union { + union SIU_DIRER_tag { uint32_t R; struct { uint32_t:16; @@ -5207,7 +5207,7 @@ extern "C" { } B; } DIRER; /* DMA/Interrupt Request Enable Register */ - union { + union SIU_DIRSR_tag { uint32_t R; struct { uint32_t:30; @@ -5239,7 +5239,7 @@ extern "C" { } B; } OSR; /* Overrun Status Register */ - union { + union SIU_ORER_tag { uint32_t R; struct { uint32_t:16; @@ -5262,7 +5262,7 @@ extern "C" { } B; } ORER; /* Overrun Request Enable Register */ - union { + union SIU_IREER_tag { uint32_t R; struct { uint32_t NREE0:1; @@ -5287,7 +5287,7 @@ extern "C" { } B; } IREER; /* External IRQ Rising-Edge Event Enable Register */ - union { + union SIU_IFEER_tag { uint32_t R; struct { uint32_t NFEE0:1; @@ -5312,7 +5312,7 @@ extern "C" { } B; } IFEER; /* External IRQ Falling-Edge Event Enable Register */ - union { + union SIU_IDFR_tag { uint32_t R; struct { uint32_t:28; @@ -5354,7 +5354,7 @@ extern "C" { uint16_t PA:2; uint16_t OBE:1; uint16_t IBE:1; - uint16_t:2; + uint16_t DSC:2; uint16_t ODE:1; uint16_t HYS:1; uint16_t SRC:2; diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h index 638d679..4efa922 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h +++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h @@ -223,6 +223,12 @@ extern "C" { #define MPC55XX_IRQ_PIT_CHANNEL(ch) \ ((unsigned) (ch) < 9U ? 148U + (ch) : MPC55XX_IRQ_INVALID) + /* SIU external interrupts */ + #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U + #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U + #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U + #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U + /* eMIOS */ #define MPC55XX_IRQ_EMIOS(ch) \ ((unsigned) (ch) < 24U ? 58U + (ch) : \ From sebh at rtems.org Mon Aug 25 11:31:47 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 25 Aug 2014 06:31:47 -0500 Subject: [rtems commit] bsp/mpc55xx: Fix comment Message-ID: <20140825113147.4CFCA700810@git.rtems.org> Module: rtems Branch: master Commit: 4b104834ebd0faa1d631c037e92dde47c22d2fa2 Changeset: http://git.rtems.org/rtems/commit/?id=4b104834ebd0faa1d631c037e92dde47c22d2fa2 Author: Sebastian Huber Date: Mon Aug 25 13:39:34 2014 +0200 bsp/mpc55xx: Fix comment --- .../libcpu/powerpc/mpc55xx/misc/flash_support.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c index 74bbd39..2769efe 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c +++ b/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash_support.c @@ -692,4 +692,4 @@ mpc55xx_flash_address(void) return mas2 & 0xFFFFF000; } -#endif /* MPC55XX_CHIP_TYPE / 100 == 55 */ +#endif /* MPC55XX_CHIP_FAMILY == 555 || MPC55XX_CHIP_FAMILY == 556 */ From joel at rtems.org Mon Aug 25 16:05:53 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 11:05:53 -0500 Subject: [rtems commit] Add or1k to the list of targets that use IEEE 754 in xdr_float.c Message-ID: <20140825160553.CEB3A700812@git.rtems.org> Module: rtems Branch: master Commit: e5f6ca87e122b85c1b757dfedd1432f60ea96c85 Changeset: http://git.rtems.org/rtems/commit/?id=e5f6ca87e122b85c1b757dfedd1432f60ea96c85 Author: Hesham ALMatary Date: Fri Aug 22 15:22:04 2014 -0500 Add or1k to the list of targets that use IEEE 754 in xdr_float.c --- cpukit/librpc/src/xdr/xdr_float.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/cpukit/librpc/src/xdr/xdr_float.c b/cpukit/librpc/src/xdr/xdr_float.c index 8640058..cf081a7 100644 --- a/cpukit/librpc/src/xdr/xdr_float.c +++ b/cpukit/librpc/src/xdr/xdr_float.c @@ -69,6 +69,7 @@ static char *rcsid = "$FreeBSD: src/lib/libc/xdr/xdr_float.c,v 1.7 1999/08/28 00 defined(__mips__) || defined(__moxie__) || \ defined(__nios2__) || \ defined(__ns32k__) || \ + defined(__or1k__) || \ defined(__sparc__) || \ defined(__ppc__) || defined(__PPC__) || \ defined(__sh__) || \ From joel at rtems.org Mon Aug 25 16:05:52 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 11:05:52 -0500 Subject: [rtems commit] sptests/spcache01: Make inline assembly conditional to account for OpenRISC l.nop instruction . Message-ID: <20140825160553.B50BD700A25@git.rtems.org> Module: rtems Branch: master Commit: 23b14f87cf701654b231017171a61b1e6fb4a322 Changeset: http://git.rtems.org/rtems/commit/?id=23b14f87cf701654b231017171a61b1e6fb4a322 Author: Hesham ALMatary Date: Fri Aug 22 15:20:16 2014 -0500 sptests/spcache01: Make inline assembly conditional to account for OpenRISC l.nop instruction. --- testsuites/sptests/spcache01/init.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/testsuites/sptests/spcache01/init.c b/testsuites/sptests/spcache01/init.c index 2c9d184..ad9b54f 100644 --- a/testsuites/sptests/spcache01/init.c +++ b/testsuites/sptests/spcache01/init.c @@ -27,7 +27,11 @@ const char rtems_test_name[] = "SPCACHE 1"; -#define I() __asm__ volatile ("nop") +#ifdef __or1k__ + #define I() __asm__ volatile ("l.nop") +#else + #define I() __asm__ volatile ("nop") +#endif #define I8() I(); I(); I(); I(); I(); I(); I(); I() From joel at rtems.org Mon Aug 25 16:05:52 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 11:05:52 -0500 Subject: [rtems commit] Rename or1k_or1ksim BSP to or1ksim Message-ID: <20140825160553.CA29C70080D@git.rtems.org> Module: rtems Branch: master Commit: 9d92a43ff74abb30e6cf9a58560183b58877408e Changeset: http://git.rtems.org/rtems/commit/?id=9d92a43ff74abb30e6cf9a58560183b58877408e Author: Hesham ALMatary Date: Fri Aug 22 15:21:35 2014 -0500 Rename or1k_or1ksim BSP to or1ksim --- .../make/custom/{or1k_or1ksim.cfg => or1ksim.cfg} | 0 1 files changed, 0 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/or1k/or1ksim/make/custom/or1k_or1ksim.cfg b/c/src/lib/libbsp/or1k/or1ksim/make/custom/or1ksim.cfg similarity index 100% rename from c/src/lib/libbsp/or1k/or1ksim/make/custom/or1k_or1ksim.cfg rename to c/src/lib/libbsp/or1k/or1ksim/make/custom/or1ksim.cfg From joel at rtems.org Mon Aug 25 16:05:53 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 11:05:53 -0500 Subject: [rtems commit] or1ksim BSP: Include cache manager stubs, and re-generate preinstall.am files. Message-ID: <20140825160553.A2618700814@git.rtems.org> Module: rtems Branch: master Commit: baa3c91ecb8a3b48ef387b938fcdb6e60b5bdc8a Changeset: http://git.rtems.org/rtems/commit/?id=baa3c91ecb8a3b48ef387b938fcdb6e60b5bdc8a Author: Hesham ALMatary Date: Fri Aug 22 15:22:37 2014 -0500 or1ksim BSP: Include cache manager stubs, and re-generate preinstall.am files. --- c/src/lib/libbsp/or1k/or1ksim/Makefile.am | 9 +++- c/src/lib/libbsp/or1k/or1ksim/preinstall.am | 71 ++++++++++++++------------ c/src/lib/libbsp/or1k/preinstall.am | 2 +- 3 files changed, 46 insertions(+), 36 deletions(-) diff --git a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am index d5eb10c..f1315c4 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am +++ b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am @@ -9,7 +9,7 @@ ACLOCAL_AMFLAGS = -I ../../../../aclocal include $(top_srcdir)/../../../../automake/compile.am include_bspdir = $(includedir)/bsp -#include_libcpudir = $(includedir)/libcpu +include_libcpudir = $(includedir)/libcpu dist_project_lib_DATA = bsp_specs @@ -21,7 +21,6 @@ include_bsp_HEADERS = include_HEADERS = include/bsp.h nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h - include_bsp_HEADERS += ../shared/include/linker-symbols.h include_bsp_HEADERS += ../../../libbsp/shared/include/mm.h include_bsp_HEADERS += ../../shared/include/utility.h @@ -99,6 +98,12 @@ libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c libbsp_a_SOURCES += ../../shared/src/irq-generic.c libbsp_a_SOURCES += ../../shared/src/irq-info.c libbsp_a_SOURCES += irq/irq.c + +# Cache +libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c +libbsp_a_SOURCES += ../../shared/include/cache_.h +libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include + ############################################################################### # Special Rules # ############################################################################### diff --git a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am index e75733c..cbdf3df 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am +++ b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am @@ -2,113 +2,118 @@ if AMPOLISH3 $(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_LIB) - @: > $(PROJECT_LIB)/$(dirstamp) + @$(MKDIR_P) $(PROJECT_LIB) + @: > $(PROJECT_LIB)/$(dirstamp) PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) $(PROJECT_INCLUDE)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE) - @: > $(PROJECT_INCLUDE)/$(dirstamp) + @$(MKDIR_P) $(PROJECT_INCLUDE) + @: > $(PROJECT_INCLUDE)/$(dirstamp) PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) $(PROJECT_INCLUDE)/bsp/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp - @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp + @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) +$(PROJECT_INCLUDE)/libcpu/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu + @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) + $(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs + $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs $(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h $(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h $(PROJECT_INCLUDE)/bsp/linker-symbols.h: ../shared/include/linker-symbols.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/linker-symbols.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/linker-symbols.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/linker-symbols.h $(PROJECT_INCLUDE)/bsp/mm.h: ../../../libbsp/shared/include/mm.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mm.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mm.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mm.h $(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h $(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h $(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h $(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h $(PROJECT_INCLUDE)/bsp/uart-output-char.h: ../../shared/include/uart-output-char.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart-output-char.h $(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h $(PROJECT_INCLUDE)/bsp/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tm27.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tm27.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tm27.h $(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h $(PROJECT_INCLUDE)/bsp/uart.h: include/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h $(PROJECT_INCLUDE)/bsp/or1ksim.h: include/or1ksim.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/or1ksim.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/or1ksim.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/or1ksim.h $(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h $(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) + $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds $(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base diff --git a/c/src/lib/libbsp/or1k/preinstall.am b/c/src/lib/libbsp/or1k/preinstall.am index fe8d090..1143c2e 100644 --- a/c/src/lib/libbsp/or1k/preinstall.am +++ b/c/src/lib/libbsp/or1k/preinstall.am @@ -2,5 +2,5 @@ if AMPOLISH3 $(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif From joel at rtems.org Mon Aug 25 16:05:52 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 11:05:52 -0500 Subject: [rtems commit] libcpu: Add new entry for or1k cpu and include cache manager stubs. Message-ID: <20140825160553.64987700A5B@git.rtems.org> Module: rtems Branch: master Commit: eeea9e30a2c5d3ea01e9fc13202fa77e22bd0f02 Changeset: http://git.rtems.org/rtems/commit/?id=eeea9e30a2c5d3ea01e9fc13202fa77e22bd0f02 Author: Hesham ALMatary Date: Fri Aug 22 15:20:47 2014 -0500 libcpu: Add new entry for or1k cpu and include cache manager stubs. --- c/src/lib/libcpu/or1k/Makefile.am | 20 +++++++++++++++++ c/src/lib/libcpu/or1k/configure.ac | 31 +++++++++++++++++++++++++++ c/src/lib/libcpu/or1k/preinstall.am | 23 ++++++++++++++++++++ c/src/lib/libcpu/or1k/shared/cache/cache_.h | 11 +++++++++ 4 files changed, 85 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libcpu/or1k/Makefile.am b/c/src/lib/libcpu/or1k/Makefile.am new file mode 100644 index 0000000..f4a6372 --- /dev/null +++ b/c/src/lib/libcpu/or1k/Makefile.am @@ -0,0 +1,20 @@ +ACLOCAL_AMFLAGS = -I ../../../aclocal + +include $(top_srcdir)/../../../automake/compile.am + +CLEANFILES = +DISTCLEANFILES = +noinst_PROGRAMS = + +include_libcpudir = $(includedir)/libcpu + +## shared/cache +include_libcpu_HEADERS = ../shared/include/cache.h +noinst_PROGRAMS += shared/cache.rel +shared_cache_rel_SOURCES = ../shared/src/no_cache.c shared/cache/cache_.h +shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache +shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + +include $(srcdir)/preinstall.am + +include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/or1k/configure.ac b/c/src/lib/libcpu/or1k/configure.ac new file mode 100644 index 0000000..c87c0f1 --- /dev/null +++ b/c/src/lib/libcpu/or1k/configure.ac @@ -0,0 +1,31 @@ +## Process this file with autoconf to produce a configure script. + +AC_PREREQ([2.69]) +AC_INIT([rtems-c-src-lib-libcpu-or1k],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla]) +RTEMS_TOP([../../../../..],[../../..]) + +RTEMS_CANONICAL_TARGET_CPU + +AM_INIT_AUTOMAKE([no-define foreign subdir-objects 1.12.2]) +AM_MAINTAINER_MODE + +RTEMS_ENV_RTEMSBSP + +RTEMS_PROJECT_ROOT + +RTEMS_PROG_CC_FOR_TARGET +AM_PROG_CC_C_O +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +# At this time all models should use the shared directory so do this +AM_CONDITIONAL(shared, true) + +AC_PATH_PROG([AMPOLISH3],[ampolish3],[]) + +RTEMS_AMPOLISH3 + +# Explicitly list all Makefiles here +AC_CONFIG_FILES([Makefile +]) +AC_OUTPUT diff --git a/c/src/lib/libcpu/or1k/preinstall.am b/c/src/lib/libcpu/or1k/preinstall.am new file mode 100644 index 0000000..9670596 --- /dev/null +++ b/c/src/lib/libcpu/or1k/preinstall.am @@ -0,0 +1,23 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +$(PROJECT_INCLUDE)/libcpu/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu + @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) + +$(PROJECT_INCLUDE)/libcpu/cache.h: ../shared/include/cache.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache.h diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h b/c/src/lib/libcpu/or1k/shared/cache/cache_.h new file mode 100644 index 0000000..08d9ecc --- /dev/null +++ b/c/src/lib/libcpu/or1k/shared/cache/cache_.h @@ -0,0 +1,11 @@ +/* + * or1k Cache Manager Support + */ + +#ifndef __OR1K_CACHE_H +#define __OR1K_CACHE_H + +#include + +#endif +/* end of include file */ From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] or1k/Makefile.am: libbsp_a_CPPFLAGS was defined twice Message-ID: <20140825222255.7D48E700814@git.rtems.org> Module: rtems Branch: master Commit: 8f1bdcb9ada7d02d9dcc1ef03e3787a48fc7ddf8 Changeset: http://git.rtems.org/rtems/commit/?id=8f1bdcb9ada7d02d9dcc1ef03e3787a48fc7ddf8 Author: Joel Sherrill Date: Mon Aug 25 17:07:12 2014 -0500 or1k/Makefile.am: libbsp_a_CPPFLAGS was defined twice --- c/src/lib/libbsp/or1k/or1ksim/Makefile.am | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am index f1315c4..1ff43ed 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am +++ b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am @@ -102,7 +102,7 @@ libbsp_a_SOURCES += irq/irq.c # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c libbsp_a_SOURCES += ../../shared/include/cache_.h -libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include +libbsp_a_CPPFLAGS += -I$(srcdir)/../../shared/include ############################################################################### # Special Rules # From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] gensh4/bsp_specs: Account for big/little endian Message-ID: <20140825222255.2C0B4700812@git.rtems.org> Module: rtems Branch: master Commit: bf1f8764831eb20cccecc9a45f5ec8e30bbcebc2 Changeset: http://git.rtems.org/rtems/commit/?id=bf1f8764831eb20cccecc9a45f5ec8e30bbcebc2 Author: Joel Sherrill Date: Mon Aug 25 16:52:45 2014 -0500 gensh4/bsp_specs: Account for big/little endian --- c/src/lib/libbsp/sh/gensh4/bsp_specs | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/sh/gensh4/bsp_specs b/c/src/lib/libbsp/sh/gensh4/bsp_specs index 975c0b2..5151eaa 100644 --- a/c/src/lib/libbsp/sh/gensh4/bsp_specs +++ b/c/src/lib/libbsp/sh/gensh4/bsp_specs @@ -7,7 +7,7 @@ %{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}} *link: -%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} %{ml|!mb:-EL}%{mb:-EB} *endfile: %{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s} From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] gensh4: Improve ROM vs RAM startup configuration Message-ID: <20140825222254.E858E700810@git.rtems.org> Module: rtems Branch: master Commit: 3d99c17deb0e61db71e332a6890bce0651500de7 Changeset: http://git.rtems.org/rtems/commit/?id=3d99c17deb0e61db71e332a6890bce0651500de7 Author: Joel Sherrill Date: Mon Aug 25 16:53:13 2014 -0500 gensh4: Improve ROM vs RAM startup configuration --- c/src/lib/libbsp/sh/gensh4/configure.ac | 13 +++++++------ c/src/lib/libbsp/sh/gensh4/start/start.S | 12 +++++++++--- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/c/src/lib/libbsp/sh/gensh4/configure.ac b/c/src/lib/libbsp/sh/gensh4/configure.ac index eeaf6d8..372d65a 100644 --- a/c/src/lib/libbsp/sh/gensh4/configure.ac +++ b/c/src/lib/libbsp/sh/gensh4/configure.ac @@ -23,12 +23,13 @@ AC_DEFINE_UNQUOTED( # START_HW_INIT # This switch selects whether 'early_hw_init()' is called from # 'start.S'; 'bsp_hw_init()' is always called from 'bspstart.c' -# -START_HW_INIT=${START_HW_INIT-1} -AC_DEFINE_UNQUOTED( - [START_HW_INIT], - [$START_HW_INIT], - [Whether to call early_hw_init from start.S]) +RTEMS_BSPOPTS_SET([START_HW_INIT],[*],[0]) +RTEMS_BSPOPTS_HELP([START_HW_INIT], + [Whether to call early_hw_init from start.S]) + +RTEMS_BSPOPTS_SET([COPY_DATA_FROM_ROM],[*],[0]) +RTEMS_BSPOPTS_HELP([COPY_DATA_FROM_ROM], + [Whether to copy data from ROM to RAM in start.S]) RTEMS_BSP_CLEANUP_OPTIONS(0, 0) diff --git a/c/src/lib/libbsp/sh/gensh4/start/start.S b/c/src/lib/libbsp/sh/gensh4/start/start.S index 7dce1a7..a695daa 100644 --- a/c/src/lib/libbsp/sh/gensh4/start/start.S +++ b/c/src/lib/libbsp/sh/gensh4/start/start.S @@ -80,10 +80,10 @@ fake_func: bt hw_init_end nop -#if defined(START_HW_INIT) /* from $RTEMS_BSP.cfg */ +#if START_HW_INIT /* from $RTEMS_BSP.cfg */ ! Initialize minimal hardware ! to run hw_init we need to calculate its address - ! as it is before data coping + ! as it is before data copying mov.l hw_init_k, r0 mov.l copy_start_k, r1 mov.l copy_end_k, r2 @@ -102,6 +102,7 @@ fake_func: #endif /* START_HW_INIT */ hw_init_end: +#if COPY_DATA_FROM_ROM ! copy data from rom to ram mov.l copy_start_k, r0 mov.l copy_end_k, r1 @@ -123,6 +124,7 @@ copy_data_cycle: nop end_of_copy_data_cycle: +#endif ! go to 0x8....... adresses mov.l real_address_k, r0 lds r0, pr @@ -193,12 +195,16 @@ __stop: END_CODE .align 2 +#if START_HW_INIT copy_start_k: .long copy_start copy_end_k: .long copy_end +#endif +#if COPY_DATA_FROM_ROM copy_start_in_rom_k: .long copy_start_in_rom +#endif real_address_k: .long real_address @@ -219,7 +225,7 @@ main_k: exit_k: .long SYM(_exit) -#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ +#if START_HW_INIT /* from $RTEMS_BSP.cfg */ hw_init_k: .long SYM(early_hw_init) #endif /* START_HW_INIT */ From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] simsh2e-testsuite.tcfg: new file Message-ID: <20140825222254.76E1B700A5D@git.rtems.org> Module: rtems Branch: master Commit: d26cded81b50f2b02da5d11823c43265094a851d Changeset: http://git.rtems.org/rtems/commit/?id=d26cded81b50f2b02da5d11823c43265094a851d Author: Joel Sherrill Date: Mon Aug 25 16:51:30 2014 -0500 simsh2e-testsuite.tcfg: new file --- .../sh/shsim/make/custom/simsh2e-testsuite.tcfg | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg index 2374bb2..6cf297a 100644 --- a/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg +++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg @@ -1,5 +1,9 @@ # -# The GDB SH Simulator does not have a tick interrupt. +# The GDB SH Simulator does not have a tick interrupt +# and the simsh2e configuration has limited memory. # include: testdata/require-tick-isr.tcfg + +fsdosfsname01 +utf8proc01 From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] shsim/bsp_specs: Account for big/little endian Message-ID: <20140825222255.0AF80700A25@git.rtems.org> Module: rtems Branch: master Commit: a4d355b426576ec9ad550b3eb0329d5860957e99 Changeset: http://git.rtems.org/rtems/commit/?id=a4d355b426576ec9ad550b3eb0329d5860957e99 Author: Joel Sherrill Date: Mon Aug 25 16:50:13 2014 -0500 shsim/bsp_specs: Account for big/little endian --- c/src/lib/libbsp/sh/shsim/bsp_specs | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/sh/shsim/bsp_specs b/c/src/lib/libbsp/sh/shsim/bsp_specs index 975c0b2..70c5ecb 100644 --- a/c/src/lib/libbsp/sh/shsim/bsp_specs +++ b/c/src/lib/libbsp/sh/shsim/bsp_specs @@ -7,7 +7,7 @@ %{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}} *link: -%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} %{ml:-EL}%{mb:-EB} *endfile: %{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s} From joel at rtems.org Mon Aug 25 22:22:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Mon, 25 Aug 2014 17:22:54 -0500 Subject: [rtems commit] simsh4-testsuite.tcfg: new file Message-ID: <20140825222254.CD66370080D@git.rtems.org> Module: rtems Branch: master Commit: e75907d58ea61dad96602027f8c8fb949492d9d9 Changeset: http://git.rtems.org/rtems/commit/?id=e75907d58ea61dad96602027f8c8fb949492d9d9 Author: Joel Sherrill Date: Mon Aug 25 16:51:44 2014 -0500 simsh4-testsuite.tcfg: new file --- .../sh/shsim/make/custom/simsh4-testsuite.tcfg | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg index 2374bb2..6c9e078 100644 --- a/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg +++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg @@ -1,5 +1,9 @@ # -# The GDB SH Simulator does not have a tick interrupt. +# The GDB SH Simulator does not have a tick interrupt +# and the simsh4 configuration has limited memory. # include: testdata/require-tick-isr.tcfg + +fsdosfsname01 +utf8proc01 From chrisj at rtems.org Tue Aug 26 04:51:22 2014 From: chrisj at rtems.org (Chris Johns) Date: Mon, 25 Aug 2014 23:51:22 -0500 Subject: [rtems-tools commit] gdb-python: Update so 'rtems task' lists the classic tasks. Message-ID: <20140826045123.33E55700810@git.rtems.org> Module: rtems-tools Branch: master Commit: 3162858a3a0ec414d2b5ce3d9153ca0efb2c9d27 Changeset: http://git.rtems.org/rtems-tools/commit/?id=3162858a3a0ec414d2b5ce3d9153ca0efb2c9d27 Author: Chris Johns Date: Tue Aug 26 14:57:57 2014 +1000 gdb-python: Update so 'rtems task' lists the classic tasks. This is a first pass at cleaning up the support. To use: $ waf configure --prefix=$HOME/development/rtems/4.11 $ waf build install Start GDB and break at Init: (gdb) py import rtems (gdb) rtems task will list the classic API tasks. --- tools/gdb/python/__init__.py | 44 ++++++++++-- tools/gdb/python/chains.py | 32 ++++++++- tools/gdb/python/classic.py | 95 +++++++++++++++++-------- tools/gdb/python/configuration.py | 110 ++++++++++++++++++++++++++++ tools/gdb/python/heaps.py | 31 ++++++++- tools/gdb/python/helper.py | 31 ++++++++- tools/gdb/python/objects.py | 126 ++++++++++++++++++++------------ tools/gdb/python/percpu.py | 57 +++++++++++++++ tools/gdb/python/pretty.py | 29 ++++++++ tools/gdb/python/rtems.py | 126 +++++++++++++++++++++++---------- tools/gdb/python/sparc.py | 4 +- tools/gdb/python/supercore.py | 29 ++++++++ tools/gdb/python/supercore_printer.py | 31 ++++++++- tools/gdb/python/threads.py | 122 +++++++++++++++++++++++++++++--- tools/gdb/python/watchdog.py | 34 ++++++++- tools/gdb/python/wscript | 34 +++++---- 16 files changed, 778 insertions(+), 157 deletions(-) diff --git a/tools/gdb/python/__init__.py b/tools/gdb/python/__init__.py index 36d2c06..58c8625 100644 --- a/tools/gdb/python/__init__.py +++ b/tools/gdb/python/__init__.py @@ -1,8 +1,40 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# -if __name__ == "__main__": - import sys - import os.path - sys.path.append(os.path.dirname(__file__)) - import main +import gdb +import rtems - print 'RTEMS GDB Support loaded' +def get_architure(): + frame = gdb.selected_frame() + arch = frame.architecture() + return arch.name() + +_cmds = rtems.create() + +print 'RTEMS GDB Support' diff --git a/tools/gdb/python/chains.py b/tools/gdb/python/chains.py index ef33ed6..6ae2518 100644 --- a/tools/gdb/python/chains.py +++ b/tools/gdb/python/chains.py @@ -1,8 +1,34 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Chains Support -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. # -# $Id$ +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# RTEMS Chains Support # import gdb diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py index e492657..44a92b4 100644 --- a/tools/gdb/python/classic.py +++ b/tools/gdb/python/classic.py @@ -1,8 +1,34 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Classic API Support -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # -# $Id$ +# RTEMS Classic API Support # import gdb @@ -16,7 +42,6 @@ import threads import watchdog import heaps import supercore -import sparc class attribute: """The Classic API attribute.""" @@ -110,7 +135,8 @@ class semaphore: "Print a classic semaphore." def __init__(self, obj): - self.object = obj + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'semaphore') @@ -152,29 +178,38 @@ class task: "Print a classic task" def __init__(self, obj): - self.object = obj - self.task = \ - threads.control(self.object) + self.reference = obj + self.object = obj.dereference() + self.task = threads.control(self.reference) self.wait_info = self.task.wait_info() - # ToDo: Insert platform dep. code here. - self.regs = sparc.register(self.object['Registers']) + self.regs = self.task.registers() + #self.regs = sparc.register(self.object['Registers']) def show(self, from_tty): - print ' Name:', self.task.name() - print ' State:', self.task.current_state() - print ' Current:', self.task.current_priority() - print ' Real:', self.task.real_priority() - print ' Preempt:', self.task.preemptible() - print ' T Budget:', self.task.cpu_time_budget() - print ' Regsters:' - self.regs.show() - + cpu = self.task.executing() + if cpu == -1: + cpu = 'not executing' + print ' Id:', '0x%08x' % (self.task.id()) + print ' Name:', self.task.name() + print ' Active CPU:', cpu + print ' State:', self.task.current_state() + print ' Current:', self.task.current_priority() + print ' Real:', self.task.real_priority() + print ' Preempt:', self.task.preemptible() + print ' T Budget:', self.task.cpu_time_budget() + print ' Time:', self.task.cpu_time_used() + print ' Resources:', self.task.resource_count() + print ' Regsters:' + for name in self.regs.names(): + val = self.regs.get(name) + print ' %20s: %08x (%d)' % (name, val, val) class message_queue: "Print classic messege queue" - def __init__(self,obj): - self.object = obj + def __init__(self, obj): + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], \ 'message_queue') @@ -193,7 +228,8 @@ class timer: '''Print a classic timer''' def __init__(self, obj): - self.object = obj + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.watchdog = watchdog.control(self.object['Ticker']) @@ -205,7 +241,8 @@ class partition: ''' Print a rtems partition ''' def __init__(self, obj): - self.object = obj + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'partition') self.starting_addr = self.object['starting_address'] @@ -224,8 +261,9 @@ class partition: class region: "prints a classic region" - def __init__(self,obj): - self.object = obj + def __init__(self, obj): + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'], 'region') self.wait_queue = threads.queue(self.object['Wait_queue']) @@ -241,8 +279,9 @@ class region: class barrier: '''classic barrier abstraction''' - def __init__(self,obj): - self.object = obj + def __init__(self, obj): + self.reference = obj + self.object = obj.dereference() self.object_control = objects.control(self.object['Object']) self.attr = attribute(self.object['attribute_set'],'barrier') self.core_b_control = supercore.barrier_control(self.object['Barrier']) @@ -257,5 +296,3 @@ class barrier: print ' Waiting:',self.core_b_control.waiting_threads() helper.tasks_printer_routine(self.core_b_control.tasks()) - - diff --git a/tools/gdb/python/configuration.py b/tools/gdb/python/configuration.py new file mode 100644 index 0000000..d20224b --- /dev/null +++ b/tools/gdb/python/configuration.py @@ -0,0 +1,110 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# RTEMS Configuration Table +# + +import gdb + +def _table(): + return gdb.parse_and_eval('Configuration') + +def fields(): + return [field.name for field in _table().type.fields()] + +def mp(): + return '_Configuration_MP_table' in fields() + +def smp(): + if 'smp_enabled' in fields(): + return int(_table()['smp_enabled']) != 0 + return False + +def maximum_processors(): + if smp(): + return int(_table()['maximum_processors']) + return 1 + +def work_space_size(): + return long(_table()['work_space_size']) + +def stack_space_size(): + return long(_table()['stack_space_size']) + +def maximum_extensions(): + return long(_table()['maximum_extensions']) + +def maximum_keys(): + return long(_table()['maximum_keys']) + +def maximum_key_value_pairs(): + return long(_table()['maximum_key_value_pairs']) + +def microseconds_per_tick(): + return long(_table()['microseconds_per_tick']) + +def nanoseconds_per_tick(): + return long(_table()['nanoseconds_per_tick']) + +def ticks_per_timeslice(): + return long(_table()['ticks_per_timeslice']) + +def idle_task(): + return long(_table()['idle_task']) + +def idle_task_stack_size(): + return long(_table()['idle_task_stack_size']) + +def interrupt_stack_size(): + return long(_table()['interrupt_stack_size']) + +def stack_allocate_init_hook(): + return long(_table()['stack_allocate_init_hook']) + +def stack_allocate_hook(): + return long(_table()['stack_allocate_hook']) + +def stack_free_hook(): + return long(_table()['stack_free_hook']) + +def do_zero_of_workspace(): + return int(_table()['do_zero_of_workspace']) != 0 + +def unified_work_area(): + return int(_table()['unified_work_area']) != 0 + +def stack_allocator_avoids_work_space(): + return long(_table()['stack_allocator_avoids_work_space']) + +def number_of_initial_extensions(): + return int(_table()['number_of_initial_extensions']) + +def user_extension_table(): + return _table()['User_extension_table'] diff --git a/tools/gdb/python/heaps.py b/tools/gdb/python/heaps.py index 2cc7907..e843f33 100644 --- a/tools/gdb/python/heaps.py +++ b/tools/gdb/python/heaps.py @@ -1,3 +1,32 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # # RTEMS heap # @@ -81,4 +110,4 @@ class control: stats = self.stat() print ' stats:' - stats.show() \ No newline at end of file + stats.show() diff --git a/tools/gdb/python/helper.py b/tools/gdb/python/helper.py index dfd01eb..5efcf02 100644 --- a/tools/gdb/python/helper.py +++ b/tools/gdb/python/helper.py @@ -1,5 +1,34 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # # RTEMS GDB support helper routins. +# import gdb @@ -18,4 +47,4 @@ def type_from_value(val): return type.unqualified () def test_bit(val, pos): - return bool(val & (1 << (pos-1))) \ No newline at end of file + return bool(val & (1 << (pos-1))) diff --git a/tools/gdb/python/objects.py b/tools/gdb/python/objects.py index ee59cbc..4898d81 100644 --- a/tools/gdb/python/objects.py +++ b/tools/gdb/python/objects.py @@ -1,15 +1,41 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Objects Support -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # -# $Id$ +# RTEMS Objects Support # import gdb import itertools import re -class infotables: +class infotables(): """Manage the object information tables.""" tables_types = { @@ -36,7 +62,7 @@ class infotables: self.tables = {} def name(self, api, _class): - return api + '/' + _class + return '%s/%s' % (api, _class) def load(self, n): if n in self.tables_types: @@ -50,6 +76,16 @@ class infotables: return self.tables[n] return None + def minimum_id(self, api, _class): + n = self.name(api, _class) + self.load(n) + return int(self.tables[n]['minimum_id']) + + def maximum_id(self, api, _class): + n = self.name(api, _class) + self.load(n) + return int(self.tables[n]['maximum_id']) + def maximum(self, api, _class): n = self.name(api, _class) self.load(n) @@ -71,18 +107,14 @@ class infotables: def object_return(self, api, _class, index=-1): n = self.name(api, _class) self.load(n) - table_type = self.tables_types[n] - if api == 'internal': - expr = '(' + table_type[0] + ')' + table_type[1] - + expr = '(%s) %s' % (table_type[0], table_type[1]) else: max = self.maximum(api, _class) if index > max: raise IndexError('object index out of range (%d)' % (max)) - expr = '(' + table_type[0] + '*)' + \ - table_type[1] + '.local_table[' + str(index) + ']' + expr = '(%s*) %s.local_table[%d]' % (table_type[0], table_type[1], index) return gdb.parse_and_eval(expr) def is_string(self, api, _class): @@ -98,7 +130,7 @@ class infotables: # information = infotables() -class ident: +class ident(): "An RTEMS object id with support for its bit fields." bits = [ @@ -113,14 +145,13 @@ class ident: ] OBJECT_16_BITS = 0 - OBJECT_31_BITS = 1 + OBJECT_32_BITS = 1 api_labels = [ 'none', 'internal', 'classic', - 'posix', - 'itron' + 'posix' ] class_labels = { @@ -150,15 +181,6 @@ class ident: 'barriers', 'spinlocks', 'rwlocks'), - 'itron' : ('none', - 'tasks', - 'eventflags', - 'mailboxes', - 'message_buffers', - 'ports', - 'semaphores', - 'variable_memory_pools', - 'fixed_memory_pools') } def __init__(self, id): @@ -170,7 +192,7 @@ class ident: if self.id.type.sizeof == 2: self.idSize = self.OBJECT_16_BITS else: - self.idSize = self.OBJECT_31_BITS + self.idSize = self.OBJECT_32_BITS def get(self, field): if field in self.bits[self.idSize]: @@ -212,7 +234,7 @@ class ident: def valid(self): return self.api() != 'none' and self._class() != 'invalid' -class name: +class name(): """The Objects_Name can either be told what the name is or can take a guess.""" @@ -220,6 +242,10 @@ class name: self.name = name if is_string == None: self.is_string = 'auto' + try: + self.name_p = self.name['name_p'] + except gdb.Error: + self.is_string = 'no' else: if is_string: self.is_string = 'yes' @@ -227,25 +253,39 @@ class name: self.is_string = 'no' def __str__(self): + return self.get() + + def get(self): if self.is_string != 'yes': u32 = int(self.name['name_u32']) - s = chr((u32 >> 24) & 0xff) + \ - chr((u32 >> 16) & 0xff) + chr((u32 >> 8) & 0xff) + \ - chr(u32 & 0xff) - for c in range(0,4): - if s[c] < ' ' or s[c] > '~': - s = None - break - if s: - return s - return str(self.name['name_p'].dereference()) - -class control: + if u32 != 0: + s = chr((u32 >> 24) & 0xff) + \ + chr((u32 >> 16) & 0xff) + \ + chr((u32 >> 8) & 0xff) + \ + chr(u32 & 0xff) + for c in range(0, 4): + if s[c] < ' ' or s[c] > '~': + s = None + break + if s: + return s + if self.is_string == 'xno': + return None + try: + name_p = self.name['name_p'] + return str(name_p.dereference()) + except gdb.Error: + pass + return None + +class control(): """The Objects_Control structure.""" def __init__(self, object): self.object = object self._id = ident(self.object['id']) + self._name = name(self.object['name'], + information.is_string(self._id.api(), self._id._class())) def node(self): return self.object['Node'] @@ -254,12 +294,4 @@ class control: return self.object['id'] def name(self): - is_string = information.is_string(self._id.api(), self._id._class()) - val = str(name(self.object['name'],is_string)) - - # Normal comaprision is a bit tricky with quotes - # 0 '\000' in hex == '3020275c30303027' - if val.encode('hex') == '3020275c30303027': - val = "" - - return val \ No newline at end of file + return self._name.get() diff --git a/tools/gdb/python/percpu.py b/tools/gdb/python/percpu.py new file mode 100644 index 0000000..991bdf8 --- /dev/null +++ b/tools/gdb/python/percpu.py @@ -0,0 +1,57 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# RTEMS Per CPU Table +# + +import gdb + +import configuration + +def _table(cpu): + max_cpus = configuration.maximum_processors() + if cpu >= max_cpus: + raise IndexError('cpu index out of range (%d)' % (max_cpus)) + return gdb.parse_and_eval('_Per_CPU_Information[%d].per_cpu' % (cpu)) + +def get(cpu): + return _table(cpu) + +def thread_active(thread): + for cpu in range(0, configuration.maximum_processors()): + if thread == _table(cpu)['executing']: + return cpu + return -1 + +def thread_heir(thread): + for cpu in range(0, configuration.maximum_processors()): + if thread == _table(cpu)['heir']: + return cpu + return -1 diff --git a/tools/gdb/python/pretty.py b/tools/gdb/python/pretty.py index 929c245..3cbe052 100644 --- a/tools/gdb/python/pretty.py +++ b/tools/gdb/python/pretty.py @@ -1,6 +1,35 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # # RTEMS pretty printers # + import re import helper import objects diff --git a/tools/gdb/python/rtems.py b/tools/gdb/python/rtems.py index 6c987cf..534cb0d 100644 --- a/tools/gdb/python/rtems.py +++ b/tools/gdb/python/rtems.py @@ -1,8 +1,34 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Pretty Printers -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. # -# $Id$ +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# RTEMS Pretty Printers # import gdb @@ -29,18 +55,18 @@ class rtems_object(gdb.Command): """Object sub-command for RTEMS""" objects = { - 'classic/semaphores': lambda obj: classic.semaphore(obj), - 'classic/tasks': lambda obj: classic.task(obj), + 'classic/semaphores': lambda obj: classic.semaphore(obj), + 'classic/tasks': lambda obj: classic.task(obj), 'classic/message_queues': lambda obj: classic.message_queue(obj), - 'classic/timers' : lambda obj: classic.timer(obj), - 'classic/partitions' : lambda obj: classic.partition(obj), - 'classic/regions' : lambda obj: classic.region(obj), - 'classic/barriers' : lambda obj: classic.barrier(obj) - } + 'classic/timers' : lambda obj: classic.timer(obj), + 'classic/partitions' : lambda obj: classic.partition(obj), + 'classic/regions' : lambda obj: classic.region(obj), + 'classic/barriers' : lambda obj: classic.barrier(obj) + } def __init__(self): - self.__doc__ = 'Display the RTEMS object given a numeric ID \ - (Or a reference to rtems_object).' + self.__doc__ = 'Display the RTEMS object given a numeric ID' \ + '(Or a reference to the object).' super(rtems_object, self).__init__('rtems object', gdb.COMMAND_DATA, gdb.COMPLETE_SYMBOL) @@ -79,29 +105,47 @@ class rtems_index(gdb.Command): gdb.COMMAND_DATA, gdb.COMPLETE_NONE) - def instance(self,obj): - '''Returns a n instance of corresponding object, the child should extend this''' + def instance(self, obj): + '''Returns a n instance of corresponding object, the child should extend + this''' return obj def invoke(self, arg, from_tty): - for val in arg.split(): - try: - index = int(val) - except ValueError: - print "error: %s is not an index" % (val) - return - try: - obj = objects.information.object_return( self.api, - self._class, - index ).dereference() - except IndexError: - print "error: index %s is invalid" % (index) - return - - instance = self.instance(obj) - instance.show(from_tty) - objects.information.invalidate() - + maximum = objects.information.maximum(self.api, self._class) + minimum_id = objects.ident(objects.information.minimum_id(self.api, self._class)) + maximum_id = objects.ident(objects.information.minimum_id(self.api, self._class)) + args = arg.split() + if len(args): + for val in args: + try: + index = int(val, base = 0) + if index < maximum: + if index < minimum_id.index(): + print "error: %s is not an index (min is %d)" % (val, + minimum_id.index()) + return + else: + index = objects.ident(index).index() + except ValueError: + print "error: %s is not an index" % (val) + return + try: + obj = objects.information.object_return(self.api, + self._class, + index) + except IndexError: + print "error: index %s is invalid" % (index) + return + instance = self.instance(obj) + instance.show(from_tty) + objects.information.invalidate() + else: + print '-' * 70 + print ' %s: %d [%08x -> %08x]' % (objects.information.name(self.api, self._class), + maximum, minimum_id.value(), maximum_id.value()) + for index in range(minimum_id.index(), minimum_id.index() + maximum): + print '-' * 70 + self.invoke(str(index), from_tty) class rtems_semaphore(rtems_index): '''semaphore subcommand''' @@ -111,7 +155,7 @@ class rtems_semaphore(rtems_index): self.__doc__ = 'Display RTEMS semaphore(s) by index(es)' super(rtems_semaphore, self).__init__('rtems semaphore') - def instance(self,obj): + def instance(self, obj): return classic.semaphore(obj) class rtems_task(rtems_index): @@ -123,10 +167,9 @@ class rtems_task(rtems_index): self.__doc__ = 'Display RTEMS task(s) by index(es)' super(rtems_task,self).__init__('rtems task') - def instance(self,obj): + def instance(self, obj): return classic.task(obj) - class rtems_message_queue(rtems_index): '''Message Queue subcommand''' @@ -136,7 +179,7 @@ class rtems_message_queue(rtems_index): self.__doc__ = 'Display RTEMS message_queue(s) by index(es)' super(rtems_message_queue,self).__init__('rtems mqueue') - def instance(self,obj): + def instance(self, obj): return classic.message_queue(obj) class rtems_timer(rtems_index): @@ -148,7 +191,7 @@ class rtems_timer(rtems_index): self.__doc__ = 'Display RTEMS timer(s) by index(es)' super(rtems_timer, self).__init__('rtems timer') - def instance(self,obj): + def instance(self, obj): return classic.timer(obj) class rtems_partition(rtems_index): @@ -252,3 +295,12 @@ class rtems_wsec(rtems_watchdog_chain): self.__doc__ = 'Display watchdog seconds chain' super(rtems_wsec, self).__init__('rtems wdseconds') +def create(): + return (rtems(), + rtems_object(), + rtems_semaphore(), + rtems_task(), + rtems_message_queue(), + rtems_tod(), + rtems_wdt(), + rtems_wsec()) diff --git a/tools/gdb/python/sparc.py b/tools/gdb/python/sparc.py index 70ef5d3..41b6fec 100644 --- a/tools/gdb/python/sparc.py +++ b/tools/gdb/python/sparc.py @@ -73,7 +73,7 @@ class register: return val - def __init__(self,reg): + def __init__(self, reg): self.reg = reg def global_regs(self): @@ -139,4 +139,4 @@ class register: print '\b\b ]' sr = self.status() - print sr.to_string() \ No newline at end of file + print sr.to_string() diff --git a/tools/gdb/python/supercore.py b/tools/gdb/python/supercore.py index 6116626..0790cc9 100644 --- a/tools/gdb/python/supercore.py +++ b/tools/gdb/python/supercore.py @@ -1,3 +1,32 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # # RTEMS Supercore Objects # diff --git a/tools/gdb/python/supercore_printer.py b/tools/gdb/python/supercore_printer.py index 3ce8110..61241e3 100644 --- a/tools/gdb/python/supercore_printer.py +++ b/tools/gdb/python/supercore_printer.py @@ -1,6 +1,35 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# All rights reserved. +# +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + # # RTEMS Supercore pretty printers for GDB # + import objects import itertools import threads @@ -138,4 +167,4 @@ class node: self.node = chains.node(node) def to_string(self): - return "Node: "+str(self.node)+" Next: "+str(self.node.next())+" Prev: "+str(self.node.previous()) \ No newline at end of file + return "Node: "+str(self.node)+" Next: "+str(self.node.next())+" Prev: "+str(self.node.previous()) diff --git a/tools/gdb/python/threads.py b/tools/gdb/python/threads.py index 7098481..1719187 100644 --- a/tools/gdb/python/threads.py +++ b/tools/gdb/python/threads.py @@ -1,13 +1,41 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Threads Support -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. # -# $Id$ + +# +# RTEMS Threads Support # import gdb + import chains import objects +import percpu def task_chain(chain): tasks = [] @@ -17,7 +45,7 @@ def task_chain(chain): node.next() return tasks -class state: +class state(): ALL_SET = 0x000fffff READY = 0x00000000 @@ -100,7 +128,7 @@ class state: s = self.masks[m] + ',' return s[:-1] -class wait_info: +class wait_info(): def __init__(self, info): self.info = info @@ -123,11 +151,68 @@ class wait_info: def queue(self): return task_chain(chains.control(self.info['queue'])) -class control: +class registers(): + + def __init__(self, regs): + self.regs = regs + + def names(self): + return [field.name for field in self.regs.type.fields()] + + def get(self, reg): + t = str(self.regs[reg].type) + if t in ['double']: + return float(self.regs[reg]) + return int(self.regs[reg]) + + + def format(self, reg): + t = self.regs[reg].type + if t in ['uint32_t', 'unsigned', 'unsigned long']: + return '%08x (%d)' % (val) + +class control(): + ''' + Thread_Control has the following fields: + Object Objects_Control + RBNode RBTree_Node + current_state States_Control + current_priority Priority_Control + real_priority Priority_Control + resource_count uint32_t + Wait Thread_Wait_information + Timer Watchdog_Control + receive_packet MP_packet_Prefix* X + lock_mutex Chain_Control X + Resource_node Resource_Node X + is_global bool X + is_preemptible bool + Scheduler Thread_Scheduler_control + rtems_ada_self void* X + cpu_time_budget uint32_t + budget_algorithm Thread_CPU_budget_algorithms + budget_callout Thread_CPU_budget_algorithm_callout + cpu_time_used Thread_CPU_usage_t + Start Thread_Start_information + Post_switch_actions Thread_Action_control + Registers Context_Control + fp_context Context_Control_fp* X + libc_reent struct _reent* + API_Extensions void*[THREAD_API_LAST + 1] + task_variables rtems_task_variable_t* X + Key_Chain Chain_Control + Life Thread_Life_control + extensions void*[RTEMS_ZERO_LENGTH_ARRAY] + + where 'X' means the field is condition and may no exist. + ''' def __init__(self, ctrl): - self.ctrl = ctrl + self.reference = ctrl + self.ctrl = ctrl.dereference() self.object = objects.control(ctrl['Object']) + self._executing = percpu.thread_active(self.reference) + self._heir = percpu.thread_heir(self.reference) def id(self): return self.object.id() @@ -138,6 +223,12 @@ class control: val = '*' return val + def executing(self): + return self._executing + + def heir(self): + return self._heir + def current_state(self): return state(self.ctrl['current_state']).to_string() @@ -147,6 +238,15 @@ class control: def real_priority(self): return self.ctrl['real_priority'] + def resource_count(self): + return self.ctrl['resource_count'] + + def cpu_time_budget(self): + return self.ctrl['cpu_time_budget'] + + def cpu_time_used(self): + return self.ctrl['cpu_time_used'] + def preemptible(self): return self.ctrl['is_preemptible'] @@ -156,11 +256,14 @@ class control: def wait_info(self): return wait_info(self.ctrl['Wait']) + def registers(self): + return registers(self.ctrl['Registers']) + def brief(self): return "'%s' (c:%d, r:%d)" % \ (self.name(), self.current_priority(), self.real_priority()) -class queue: +class queue(): """Manage the Thread_queue_Control.""" priority_headers = 4 @@ -186,6 +289,3 @@ class queue: t.extend(task_chain(chains.control( \ self.que['Queues']['Priority'][ph]))) return t - - - diff --git a/tools/gdb/python/watchdog.py b/tools/gdb/python/watchdog.py index 71a1816..dfa57a0 100644 --- a/tools/gdb/python/watchdog.py +++ b/tools/gdb/python/watchdog.py @@ -1,8 +1,34 @@ +# RTEMS Tools Project (http://www.rtems.org/) +# Copyright 2010-2014 Chris Johns (chrisj at rtems.org) +# All rights reserved. # -# RTEMS Watchdog Support -# Copyright 2010 Chris Johns (chrisj at rtems.org) +# This file is part of the RTEMS Tools package in 'rtems-tools'. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. # -# $Id$ +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# RTEMS Watchdog Support # import gdb @@ -63,4 +89,4 @@ class control: return val def show(self): - print self.to_string() \ No newline at end of file + print self.to_string() diff --git a/tools/gdb/python/wscript b/tools/gdb/python/wscript index 22d44e8..a7f428c 100644 --- a/tools/gdb/python/wscript +++ b/tools/gdb/python/wscript @@ -6,18 +6,22 @@ def configure(conf): conf.load('python') def build(bld): - bld.install_files('${PREFIX}/share/gdb/python/rtems', - ['chains.py', - 'classic.py', - 'classic_printer.py', - 'heaps.py', - 'helper.py', - 'main.py', - 'objects.py', - 'pretty.py', - 'rtems.py', - 'sparc.py', - 'supercore.py', - 'supercore_printer.py', - 'threads.py', - 'watchdog.py']) + source = ['__init__.py', + 'chains.py', + 'classic.py', + 'classic_printer.py', + 'configuration.py', + 'heaps.py', + 'helper.py', + 'main.py', + 'objects.py', + 'percpu.py', + 'pretty.py', + 'rtems.py', + 'sparc.py', + 'supercore.py', + 'supercore_printer.py', + 'threads.py', + 'watchdog.py'] + bld(features = 'py', source = source, install_path = None) + bld.install_files('${PREFIX}/share/gdb/python/rtems', source) From sebh at rtems.org Tue Aug 26 08:12:57 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 26 Aug 2014 03:12:57 -0500 Subject: [rtems commit] rtems: Add more clock tick functions Message-ID: <20140826081257.3B8A2700810@git.rtems.org> Module: rtems Branch: master Commit: 96ec8ee80a18502c2159497e821df3fcd0dc7411 Changeset: http://git.rtems.org/rtems/commit/?id=96ec8ee80a18502c2159497e821df3fcd0dc7411 Author: Sebastian Huber Date: Fri Aug 22 17:09:36 2014 +0200 rtems: Add more clock tick functions Add rtems_clock_tick_later(), rtems_clock_tick_later_usec() and rtems_clock_tick_before(). --- cpukit/rtems/include/rtems/rtems/clock.h | 71 ++++++++++++++++++++ doc/user/clock.t | 104 ++++++++++++++++++++++++++++++ testsuites/sptests/sp37/init.c | 55 ++++++++++++++++ testsuites/sptests/sp37/sp37.doc | 5 ++ testsuites/sptests/sp37/system.h | 4 + 5 files changed, 239 insertions(+), 0 deletions(-) diff --git a/cpukit/rtems/include/rtems/rtems/clock.h b/cpukit/rtems/include/rtems/rtems/clock.h index ff71665..7595f5e 100644 --- a/cpukit/rtems/include/rtems/rtems/clock.h +++ b/cpukit/rtems/include/rtems/rtems/clock.h @@ -34,6 +34,7 @@ #include #include #include +#include #include /* struct timeval */ @@ -160,6 +161,76 @@ RTEMS_INLINE_ROUTINE rtems_interval rtems_clock_get_ticks_since_boot(void) } /** + * @brief Returns the ticks counter value delta ticks in the future. + * + * @param[in] delta The ticks delta value. + * + * @return The tick counter value delta ticks in the future. + */ +RTEMS_INLINE_ROUTINE rtems_interval rtems_clock_tick_later( + rtems_interval delta +) +{ + return _Watchdog_Ticks_since_boot + delta; +} + +/** + * @brief Returns the ticks counter value at least delta microseconds in the + * future. + * + * @param[in] delta_in_usec The delta value in microseconds. + * + * @return The tick counter value at least delta microseconds in the future. + */ +RTEMS_INLINE_ROUTINE rtems_interval rtems_clock_tick_later_usec( + rtems_interval delta_in_usec +) +{ + rtems_interval us_per_tick = rtems_configuration_get_microseconds_per_tick(); + + /* + * Add one additional tick, since we don't know the time to the clock next + * tick. + */ + return _Watchdog_Ticks_since_boot + + (delta_in_usec + us_per_tick - 1) / us_per_tick + 1; +} + +/** + * @brief Returns true if the current ticks counter value indicates a time + * before the time specified by the tick value and false otherwise. + * + * @param[in] tick The tick value. + * + * This can be used to write busy loops with a timeout. + * + * @code + * status busy( void ) + * { + * rtems_interval timeout = rtems_clock_tick_later_usec( 10000 ); + * + * do { + * if ( ok() ) { + * return success; + * } + * } while ( rtems_clock_tick_before( timeout ) ); + * + * return timeout; + * } + * @endcode + * + * @retval true The current ticks counter value indicates a time before the + * time specified by the tick value. + * @retval false Otherwise. + */ +RTEMS_INLINE_ROUTINE bool rtems_clock_tick_before( + rtems_interval tick +) +{ + return (int32_t) ( tick - _Watchdog_Ticks_since_boot ) > 0; +} + +/** * @brief Obtain Ticks Per Seconds * * This routine implements the rtems_clock_get_ticks_per_second diff --git a/doc/user/clock.t b/doc/user/clock.t index 921d1cb..1e821ad 100644 --- a/doc/user/clock.t +++ b/doc/user/clock.t @@ -21,6 +21,9 @@ the clock manager are: @item @code{@value{DIRPREFIX}clock_get_seconds_since_epoch} - Get seconds since epoch @item @code{@value{DIRPREFIX}clock_get_ticks_per_second} - Get ticks per second @item @code{@value{DIRPREFIX}clock_get_ticks_since_boot} - Get current ticks counter value + at item @code{@value{DIRPREFIX}clock_tick_later} - Get tick value in the future + at item @code{@value{DIRPREFIX}clock_tick_later_usec} - Get tick value in the future in microseconds + at item @code{@value{DIRPREFIX}clock_tick_before} - Is tick value is before a point in time @item @code{@value{DIRPREFIX}clock_get_uptime} - Get time since boot @item @code{@value{DIRPREFIX}clock_get_uptime_timeval} - Get time since boot in timeval format @item @code{@value{DIRPREFIX}clock_get_uptime_seconds} - Get seconds since boot @@ -617,6 +620,107 @@ This directive will not cause the running task to be preempted. @c @c @page + at subsection CLOCK_TICK_LATER - Get tick value in the future + + at subheading CALLING SEQUENCE: + + at ifset is-C + at findex rtems_clock_tick_later + at example +rtems_interval rtems_clock_tick_later( + rtems_interval delta +); + at end example + at end ifset + + at subheading DESCRIPTION: + +Returns the ticks counter value delta ticks in the future. + + at subheading NOTES: + +This directive is callable from an ISR. + +This directive will not cause the running task to be preempted. + + at c + at c + at c + at page + at subsection CLOCK_TICK_LATER_USEC - Get tick value in the future in microseconds + + at subheading CALLING SEQUENCE: + + at ifset is-C + at findex rtems_clock_tick_later_usec + at example +rtems_interval rtems_clock_tick_later_usec( + rtems_interval delta_in_usec +); + at end example + at end ifset + + at subheading DESCRIPTION: + +Returns the ticks counter value at least delta microseconds in the future. + + at subheading NOTES: + +This directive is callable from an ISR. + +This directive will not cause the running task to be preempted. + + at c + at c + at c + at page + at subsection CLOCK_TICK_BEFORE - Is tick value is before a point in time + + at subheading CALLING SEQUENCE: + + at ifset is-C + at findex rtems_clock_tick_before + at example +rtems_interval rtems_clock_tick_before( + rtems_interval tick +); + at end example + at end ifset + + at subheading DESCRIPTION: + +Returns true if the current ticks counter value indicates a time before the +time specified by the tick value and false otherwise. + + at subheading NOTES: + +This directive is callable from an ISR. + +This directive will not cause the running task to be preempted. + + at subheading EXAMPLE: + + at example + at group +status busy( void ) +@{ + rtems_interval timeout = rtems_clock_tick_later_usec( 10000 ); + + do @{ + if ( ok() ) @{ + return success; + @} + @} while ( rtems_clock_tick_before( timeout ) ); + + return timeout; +@} + at end group + at end example + + at c + at c + at c + at page @subsection CLOCK_GET_UPTIME - Get the time since boot @cindex clock get uptime diff --git a/testsuites/sptests/sp37/init.c b/testsuites/sptests/sp37/init.c index be0bd32..60ae01b 100644 --- a/testsuites/sptests/sp37/init.c +++ b/testsuites/sptests/sp37/init.c @@ -230,6 +230,59 @@ static void test_interrupt_locks( void ) rtems_interrupt_lock_destroy( &initialized ); } +static void test_clock_tick_functions( void ) +{ + rtems_interrupt_level level; + Watchdog_Interval saved_ticks; + + _Thread_Disable_dispatch(); + rtems_interrupt_disable( level ); + + saved_ticks = _Watchdog_Ticks_since_boot; + + _Watchdog_Ticks_since_boot = 0xdeadbeef; + rtems_test_assert( rtems_clock_get_ticks_since_boot() == 0xdeadbeef ); + + rtems_test_assert( rtems_clock_tick_later( 0 ) == 0xdeadbeef ); + rtems_test_assert( rtems_clock_tick_later( 0x8160311e ) == 0x600df00d ); + + _Watchdog_Ticks_since_boot = 0; + rtems_test_assert( rtems_clock_tick_later_usec( 0 ) == 1 ); + rtems_test_assert( rtems_clock_tick_later_usec( 1 ) == 2 ); + rtems_test_assert( rtems_clock_tick_later_usec( US_PER_TICK ) == 2 ); + rtems_test_assert( rtems_clock_tick_later_usec( US_PER_TICK + 1 ) == 3 ); + + _Watchdog_Ticks_since_boot = 0; + rtems_test_assert( !rtems_clock_tick_before( 0xffffffff ) ); + rtems_test_assert( !rtems_clock_tick_before( 0 ) ); + rtems_test_assert( rtems_clock_tick_before( 1 ) ); + + _Watchdog_Ticks_since_boot = 1; + rtems_test_assert( !rtems_clock_tick_before( 0 ) ); + rtems_test_assert( !rtems_clock_tick_before( 1 ) ); + rtems_test_assert( rtems_clock_tick_before( 2 ) ); + + _Watchdog_Ticks_since_boot = 0x7fffffff; + rtems_test_assert( !rtems_clock_tick_before( 0x7ffffffe ) ); + rtems_test_assert( !rtems_clock_tick_before( 0x7fffffff ) ); + rtems_test_assert( rtems_clock_tick_before( 0x80000000 ) ); + + _Watchdog_Ticks_since_boot = 0x80000000; + rtems_test_assert( !rtems_clock_tick_before( 0x7fffffff ) ); + rtems_test_assert( !rtems_clock_tick_before( 0x80000000 ) ); + rtems_test_assert( rtems_clock_tick_before( 0x80000001 ) ); + + _Watchdog_Ticks_since_boot = 0xffffffff; + rtems_test_assert( !rtems_clock_tick_before( 0xfffffffe ) ); + rtems_test_assert( !rtems_clock_tick_before( 0xffffffff ) ); + rtems_test_assert( rtems_clock_tick_before( 0 ) ); + + _Watchdog_Ticks_since_boot = saved_ticks; + + rtems_interrupt_enable( level ); + _Thread_Enable_dispatch(); +} + void test_interrupt_inline(void) { rtems_interrupt_level level; @@ -413,6 +466,8 @@ rtems_task Init( directive_failed( status, "rtems_clock_tick" ); puts( "clock_tick from task level" ); + test_clock_tick_functions(); + /* * Now do a dispatch directly out of a clock tick that is * called from a task. We need to create a task that will diff --git a/testsuites/sptests/sp37/sp37.doc b/testsuites/sptests/sp37/sp37.doc index 9e814f2..b98faa1 100644 --- a/testsuites/sptests/sp37/sp37.doc +++ b/testsuites/sptests/sp37/sp37.doc @@ -13,6 +13,9 @@ test set name: sp37 directives: rtems_clock_tick + rtems_clock_tick_later() + rtems_clock_tick_later_usec() + rtems_clock_tick_before() rtems_interrupt_disable (inline/body) rtems_interrupt_enable (inline/body) rtems_interrupt_flash (inline/body) @@ -24,6 +27,8 @@ concepts: + Ensure that rtems_clock_tick operates properly when invoked from a task rather than an ISR. ++ Ensure that clock tick counter functions work properly. + + Ensure that the interrupt disable, enable, and flash directives operate as expected. diff --git a/testsuites/sptests/sp37/system.h b/testsuites/sptests/sp37/system.h index 43bef81..6bb47ec 100644 --- a/testsuites/sptests/sp37/system.h +++ b/testsuites/sptests/sp37/system.h @@ -15,6 +15,8 @@ #include +#define US_PER_TICK 10000 + /* functions */ rtems_task Init( @@ -28,6 +30,8 @@ rtems_task Init( #define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION +#define CONFIGURE_MICROSECONDS_PER_TICK US_PER_TICK + #define CONFIGURE_RTEMS_INIT_TASKS_TABLE #define CONFIGURE_INIT_TASK_PRIORITY 2 #define CONFIGURE_INIT_TASK_INITIAL_MODES RTEMS_PREEMPT From joel at rtems.org Tue Aug 26 20:21:45 2014 From: joel at rtems.org (Joel Sherrill) Date: Tue, 26 Aug 2014 15:21:45 -0500 Subject: [rtems-testing commit] sim-scripts: Add new or1ksim OpenRISC simulator script. Message-ID: <20140826202145.CDC0E700810@git.rtems.org> Module: rtems-testing Branch: master Commit: 4813bac6d2c39bd4a73e0dc47aa08979bd603c2a Changeset: http://git.rtems.org/rtems-testing/commit/?id=4813bac6d2c39bd4a73e0dc47aa08979bd603c2a Author: Hesham ALMatary Date: Tue Aug 26 12:59:47 2014 -0500 sim-scripts: Add new or1ksim OpenRISC simulator script. --- sim-scripts/Makefile | 5 +- sim-scripts/or1ksim.in | 155 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 159 insertions(+), 1 deletions(-) diff --git a/sim-scripts/Makefile b/sim-scripts/Makefile index 9d9baaf..e45feae 100644 --- a/sim-scripts/Makefile +++ b/sim-scripts/Makefile @@ -1,6 +1,6 @@ INSTALL_DIR=../bin GDBSIM_SCRIPTS=bf537Stamp ezkit533 gdbarmsim h8sim jmr3904 lm32_evr \ - m32csim m32rsim psim sis simsh v850sim + m32csim m32rsim or1ksim psim sis simsh v850sim SKYEYE_SCRIPTS=ant5206 bf537Stamp-skyeye csb337 csb350 csb360 edb7312 \ ezkit533-skyeye gumstix rtl22xx smdk2410 leon2-skyeye @@ -130,6 +130,9 @@ m32csim m32csim-gdb: gdb-sim-run.in gdb-sim.in m32csim.in m32rsim m32rsim-gdb: gdb-sim-run.in gdb-sim.in m32rsim.in ./mkrun yes M32R m32r m32rsim +or1ksim or1ksim-gdb: or1ksim.in + ./mkrun yes OR1K or1k or1ksim + psim psim-gdb: gdb-sim-run.in gdb-sim.in psim.in ./mkrun yes PowerPC powerpc psim diff --git a/sim-scripts/or1ksim.in b/sim-scripts/or1ksim.in new file mode 100644 index 0000000..b71e0f6 --- /dev/null +++ b/sim-scripts/or1ksim.in @@ -0,0 +1,155 @@ +# +# or1k/or1ksim Support +# +bspSupportsGDBServerMode="yes" +runBSP=or32-elf-sim +bspTreeFile=sim.cfg + +runARGS() +{ + echo "-f ${bspTreeFile} ${1}" +} + +checkBSPFaults() +{ + return 0 +} + +bspLimit() +{ + testname=$1 + case ${testname} in + *stackchk*)limit=5 ;; + *fatal*) limit=1 ;; + *minimum*) limit=1 ;; + *psxtime*) limit=180 ;; + *) limit=60 ;; + esac + echo ${limit} +} + +bspGeneratesGDBCommands="yes" + +gdbServerARGS() +{ + echo "-c ${bspTreeFile}" +} + +bspGenerateGDBCommands() +{ +cat < Module: rtems Branch: master Commit: 2cd68a8bf626e94d906a97c337935e93094cd8f5 Changeset: http://git.rtems.org/rtems/commit/?id=2cd68a8bf626e94d906a97c337935e93094cd8f5 Author: Hesham ALMatary Date: Tue Aug 26 14:42:47 2014 -0500 Add or1ksim (sim.cfg) configuration file and edit README. OpenRISC/or1ksim BSP: The new sim.cfg file configures or1ksim emulator with HW capabilities that the current RTEMS/or1ksim BSP supports. README: HOWTO run the or1ksim simulator. --- c/src/lib/libbsp/or1k/or1ksim/README | 20 ++++++- c/src/lib/libbsp/or1k/or1ksim/sim.cfg | 104 +++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+), 1 deletions(-) diff --git a/c/src/lib/libbsp/or1k/or1ksim/README b/c/src/lib/libbsp/or1k/or1ksim/README index 43b4703..9ce5709 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/README +++ b/c/src/lib/libbsp/or1k/or1ksim/README @@ -14,4 +14,22 @@ Configuration file "sim.cfg" should be provided for complex board configurations at the current directory (which you run or1ksim from) or at ~/.or1k/ -sim -f sim.cfg hello.exe +The current sim.cfg file that configures or1ksim emulator to RTEMS/or1ksim BSP +is at the same directory as this README. You can also use or1ksim script from +rtems-tools/sim-scripts. + +From command line type: + +sim -f sim.cfg $PATH_TO_RTEMS_EXE + +or (if you use a stable or1ksim release) + +or32-elf-sim -f sim.cfg $PATH_TO_RTEMS_EXE + +from sim-scripts: + +or1ksim $PATH_TO_RTEMS_EXE + +and then attach GDB to or1ksim from another terminal by running + +or1ksim-gdb $PATH_TO_RTEMS_EXE diff --git a/c/src/lib/libbsp/or1k/or1ksim/sim.cfg b/c/src/lib/libbsp/or1k/or1ksim/sim.cfg new file mode 100644 index 0000000..061f61a --- /dev/null +++ b/c/src/lib/libbsp/or1k/or1ksim/sim.cfg @@ -0,0 +1,104 @@ +section memory + name = "RAM" + random_seed = 12345 + type = random + ce = 0 + mc = 0 + baseaddr = 0x00000000 + size = 0x08000000 + delayr = 1 + delayw = 2 +end + +section immu + enabled = 0 + nsets = 64 + nways = 1 + pagesize = 8192 + hitdelay = 0 + missdelay = 0 +end + +section dmmu + enabled = 0 + nsets = 64 + nways = 1 + pagesize = 8192 + hitdelay = 0 + missdelay = 0 +end +section mc + enabled = 0 + baseaddr = 0x90000000 + POC = 0x0000000a /* 32 bit SSRAM */ + index = 0 +end + +section ic + enabled = 0 + nsets = 256 + nways = 1 + blocksize = 16 + hitdelay = 20 + missdelay = 20 +end + +section dc + enabled = 0 + nsets = 256 + nways = 1 + blocksize = 16 + load_hitdelay = 0 + load_missdelay = 0 + store_hitdelay = 0 + store_missdelay = 0 +end + +section pic + enabled = 1 + edge_trigger = 1 +end + +section sim + verbose = 1 + debug = 0 + profile = 0 + history = 0 + clkcycle = 10ns /* 100MHz clock */ +end + +section VAPI + enabled = 1 + server_port = 50000 + log_enabled = 1 + vapi_log_file = "vapi.log" +end + +section cpu + ver = 0x12 + cfg = 0x00 + rev = 0x0001 + superscalar = 0 + hazards = 0 + dependstats = 0 + sbuf_len = 100 +end + +section debug + enabled = 1 + rsp_enabled = 1 + rsp_port = 50001 +end + +section uart + enabled = 1 + baseaddr = 0x90000000 + #channel = "xterm" + channel = "file:uart0.rx,uart0.tx" + irq = 2 + 16550 = 1 +end + +section pm + enabled = 1 +end From chrisj at rtems.org Wed Aug 27 09:56:37 2014 From: chrisj at rtems.org (Chris Johns) Date: Wed, 27 Aug 2014 04:56:37 -0500 Subject: [rtems commit] arm/lm3s3749: Add tests that do not fit. Message-ID: <20140827095637.B08FD70080E@git.rtems.org> Module: rtems Branch: master Commit: 614a0889b664a9309c3a966e5f0f494d4b94b62f Changeset: http://git.rtems.org/rtems/commit/?id=614a0889b664a9309c3a966e5f0f494d4b94b62f Author: Chris Johns Date: Wed Aug 27 20:04:26 2014 +1000 arm/lm3s3749: Add tests that do not fit. You need --enable-c++ for the c++ tests. --- .../lm3s69xx/make/custom/lm3s3749-testsuite.tcfg | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749-testsuite.tcfg b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749-testsuite.tcfg index 6925cd3..5d20dda 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s3749-testsuite.tcfg @@ -5,6 +5,7 @@ # capture +iostream ftp01 fileio flashdisk01 @@ -30,5 +31,7 @@ mrfs_fsrdwr mrfs_fssymlink mrfs_fstime pppd +rtems++ +sptls02 syscall01 utf8proc01 From sebh at rtems.org Wed Aug 27 11:58:05 2014 From: sebh at rtems.org (Sebastian Huber) Date: Wed, 27 Aug 2014 06:58:05 -0500 Subject: [rtems commit] rtems: SMP fix for timer server Message-ID: <20140827115806.0DF1D70080E@git.rtems.org> Module: rtems Branch: master Commit: 34db8ec9322f8c9ae6d416c94f6d66fd236184cb Changeset: http://git.rtems.org/rtems/commit/?id=34db8ec9322f8c9ae6d416c94f6d66fd236184cb Author: Sebastian Huber Date: Wed Aug 27 14:06:10 2014 +0200 rtems: SMP fix for timer server --- cpukit/rtems/src/timerserver.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/cpukit/rtems/src/timerserver.c b/cpukit/rtems/src/timerserver.c index 7523ebc..ad32172 100644 --- a/cpukit/rtems/src/timerserver.c +++ b/cpukit/rtems/src/timerserver.c @@ -513,7 +513,9 @@ rtems_status_code rtems_timer_initiate_server( _Objects_Build_name('T','I','M','E'), /* "TIME" */ _priority, /* create with priority 1 since 0 is illegal */ stack_size, /* let user specify stack size */ - RTEMS_NO_PREEMPT, /* no preempt is like an interrupt */ + rtems_configuration_is_smp_enabled() ? + RTEMS_DEFAULT_MODES : /* no preempt is not supported for SMP */ + RTEMS_NO_PREEMPT, /* no preempt is like an interrupt */ /* user may want floating point but we need */ /* system task specified for 0 priority */ attribute_set | RTEMS_SYSTEM_TASK, From sebh at rtems.org Wed Aug 27 13:10:34 2014 From: sebh at rtems.org (Sebastian Huber) Date: Wed, 27 Aug 2014 08:10:34 -0500 Subject: [rtems-libbsd commit] Update due to rbtree API changes Message-ID: <20140827131034.2473970080E@git.rtems.org> Module: rtems-libbsd Branch: master Commit: 8e2e9b3e655f130aa7dd8151a1ce0cabe59cbdf3 Changeset: http://git.rtems.org/rtems-libbsd/commit/?id=8e2e9b3e655f130aa7dd8151a1ce0cabe59cbdf3 Author: Sebastian Huber Date: Wed Aug 27 15:00:09 2014 +0200 Update due to rbtree API changes --- rtemsbsd/rtems/rtems-bsd-chunk.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/rtemsbsd/rtems/rtems-bsd-chunk.c b/rtemsbsd/rtems/rtems-bsd-chunk.c index 5c9c6eb..c10c220 100644 --- a/rtemsbsd/rtems/rtems-bsd-chunk.c +++ b/rtemsbsd/rtems/rtems-bsd-chunk.c @@ -47,7 +47,7 @@ #define chunk_of_node(n) ((rtems_bsd_chunk_info *) n) -static int +static rtems_rbtree_compare_result chunk_compare(const rtems_rbtree_node *a, const rtems_rbtree_node *b) { const rtems_bsd_chunk_info *left = chunk_of_node(a); @@ -71,7 +71,7 @@ rtems_bsd_chunk_init(rtems_bsd_chunk_control *self, uintptr_t info_size, self->info_size = info_size; self->info_ctor = info_ctor; self->info_dtor = info_dtor; - rtems_rbtree_initialize_empty(&self->chunks, chunk_compare, true); + rtems_rbtree_initialize_empty(&self->chunks); } void * @@ -90,7 +90,7 @@ rtems_bsd_chunk_alloc(rtems_bsd_chunk_control *self, uintptr_t chunk_size) (*self->info_ctor)(self, info); _RTEMS_Lock_allocator(); - rtems_rbtree_insert(&self->chunks, &info->node); + rtems_rbtree_insert(&self->chunks, &info->node, chunk_compare, true); _RTEMS_Unlock_allocator(); } @@ -122,7 +122,7 @@ rtems_bsd_chunk_get_info(rtems_bsd_chunk_control *self, }; return chunk_of_node(rtems_rbtree_find(&self->chunks, - &find_me.node)); + &find_me.node, chunk_compare, true)); } void * From joel at rtems.org Wed Aug 27 15:55:46 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 27 Aug 2014 10:55:46 -0500 Subject: [rtems commit] lpc40xx_ea_rom_int-testsuite.tcfg: New file Message-ID: <20140827155546.4210270080E@git.rtems.org> Module: rtems Branch: master Commit: 7d3a3456303ab21a9453ac4ee2f04ba6eac60bab Changeset: http://git.rtems.org/rtems/commit/?id=7d3a3456303ab21a9453ac4ee2f04ba6eac60bab Author: Joel Sherrill Date: Tue Aug 26 13:53:27 2014 -0500 lpc40xx_ea_rom_int-testsuite.tcfg: New file --- .../make/custom/lpc40xx_ea_rom_int-testsuite.tcfg | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int-testsuite.tcfg new file mode 100644 index 0000000..b8b9bbe --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc40xx_ea_rom_int-testsuite.tcfg @@ -0,0 +1,7 @@ +# +# lpc40xx_ea_rom_int RTEMS Test Database. +# +# Format is one line per test that is _NOT_ built. +# + +fsdosfsname01 From joel at rtems.org Wed Aug 27 15:55:46 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 27 Aug 2014 10:55:46 -0500 Subject: [rtems commit] nds/Makefile.am: Rework to avoid creating ltos of .rel files Message-ID: <20140827155546.2C997700810@git.rtems.org> Module: rtems Branch: master Commit: 6e60140daf1c7e4a39dcd17b0240eb812ead2f77 Changeset: http://git.rtems.org/rtems/commit/?id=6e60140daf1c7e4a39dcd17b0240eb812ead2f77 Author: Joel Sherrill Date: Wed Aug 27 11:00:07 2014 -0500 nds/Makefile.am: Rework to avoid creating ltos of .rel files This was necessary to enable all tests to link. --- c/src/lib/libbsp/arm/nds/Makefile.am | 106 +++++++++++----------------------- 1 files changed, 35 insertions(+), 71 deletions(-) diff --git a/c/src/lib/libbsp/arm/nds/Makefile.am b/c/src/lib/libbsp/arm/nds/Makefile.am index 76bab01..c8d8811 100644 --- a/c/src/lib/libbsp/arm/nds/Makefile.am +++ b/c/src/lib/libbsp/arm/nds/Makefile.am @@ -30,72 +30,43 @@ libbsp_a_SOURCES = include_ndsdir = $(includedir)/nds include_nds_HEADERS = touchscreen/touchscreen.h sound/sound.h -noinst_PROGRAMS += startup.rel -startup_rel_SOURCES = ../../shared/bsplibc.c ../../shared/bsppost.c \ - startup/bspstart.c ../../shared/bspclean.c startup/bspreset.c \ - ../../shared/bspgetworkarea.c ../../shared/bsppredriverhook.c \ - ../../shared/bsppretaskinghook.c ../../shared/bootcard.c +libbsp_a_CPPFLAGS = -DARM9 +libbsp_a_CPPFLAGS += -I$(srcdir)/../../shared/include +libbsp_a_CPPFLAGS += -I$(srcdir)/include +libbsp_a_CPPFLAGS += -I$(srcdir)/libnds/include +libbsp_a_CPPFLAGS += -I$(srcdir)/libfat/source/disc_io +libbsp_a_SOURCES += ../../shared/bsplibc.c +libbsp_a_SOURCES += ../../shared/bsppost.c +libbsp_a_SOURCES += startup/bspstart.c +libbsp_a_SOURCES += ../../shared/bspclean.c +libbsp_a_SOURCES += startup/bspreset.c +libbsp_a_SOURCES += ../../shared/bspgetworkarea.c +libbsp_a_SOURCES += ../../shared/bsppredriverhook.c +libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c +libbsp_a_SOURCES += ../../shared/bootcard.c libbsp_a_SOURCES += ../../shared/cpucounterread.c libbsp_a_SOURCES += ../../shared/cpucounterdiff.c -startup_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += gnatsupp.rel -gnatsupp_rel_SOURCES = ../../shared/gnatinstallhandler.c -gnatsupp_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -gnatsupp_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += clock.rel -clock_rel_SOURCES = clock/clock.c -clock_rel_SOURCES += ../../shared/clockdrv_shell.h -clock_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += rtc.rel -rtc_rel_SOURCES = rtc/rtc.c ../../shared/tod.c -rtc_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -rtc_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += console.rel -console_rel_SOURCES = console/console.c -console_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -I$(srcdir)/include -console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += fb.rel -fb_rel_SOURCES = fb/fb.c -fb_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -fb_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += touchscreen.rel -touchscreen_rel_SOURCES = touchscreen/touchscreen.c touchscreen/parser.c \ - touchscreen/reco.c -touchscreen_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -touchscreen_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += timer.rel -timer_rel_SOURCES = timer/timer.c -timer_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += sound.rel -sound_rel_SOURCES = sound/sound.c -sound_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -sound_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += block.rel -block_rel_SOURCES = block/block.c -block_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -DNDS -I$(srcdir)/libfat/source/disc_io -block_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - -noinst_PROGRAMS += irq.rel -irq_rel_SOURCES = irq/irq.c -irq_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/libnds/include -irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) +libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c +libbsp_a_SOURCES += clock/clock.c +libbsp_a_SOURCES += ../../shared/clockdrv_shell.h +libbsp_a_SOURCES += rtc/rtc.c +libbsp_a_SOURCES += ../../shared/tod.c +libbsp_a_SOURCES += console/console.c +libbsp_a_SOURCES += fb/fb.c +libbsp_a_SOURCES += touchscreen/touchscreen.c +libbsp_a_SOURCES += touchscreen/parser.c +libbsp_a_SOURCES += touchscreen/reco.c +libbsp_a_SOURCES += timer/timer.c +libbsp_a_SOURCES += sound/sound.c +libbsp_a_SOURCES += block/block.c +libbsp_a_SOURCES += irq/irq.c +# Cache +libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c +libbsp_a_SOURCES += ../../shared/include/cache_.h if HAS_NETWORKING noinst_PROGRAMS += wifi.rel -wifi_rel_SOURCES = wifi/wifi.c \ - wifi/compat.c +wifi_rel_SOURCES = wifi/wifi.c wifi/compat.c wifi_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/dswifi/include -I$(srcdir)/libnds/include -I$(srcdir)/dswifi/include -D_KERNEL -D__BSD_VISIBLE wifi_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif @@ -144,8 +115,8 @@ libnds9_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) if HAS_NETWORKING # dswifi, ARM9 side noinst_PROGRAMS += dswifi9.rel -dswifi9_rel_SOURCES = dswifi/arm9/source/wifi_arm9.c \ - dswifi/common/source/spinlock.S +dswifi9_rel_SOURCES = dswifi/arm9/source/wifi_arm9.c +dswifi9_rel_SOURCES += dswifi/common/source/spinlock.S dswifi9_rel_CPPFLAGS = $(AM_CPPFLAGS) -DARM9 -I$(srcdir)/dswifi/include -I$(srcdir)/libnds/include -I$(srcdir)/dswifi/common/source -I$(srcdir)/wifi -D_KERNEL dswifi9_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif @@ -255,14 +226,7 @@ coproc.bin: coproc/coproc.S coproc/coproc.c libnds7.rel endif project_lib_DATA += coproc.bin -# Cache -libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c -libbsp_a_SOURCES += ../../shared/include/cache_.h -libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include - -libbsp_a_LIBADD = clock.rel console.rel gnatsupp.rel startup.rel irq.rel \ - timer.rel libnds9.rel rtc.rel fb.rel touchscreen.rel sound.rel \ - block.rel libdldi.rel +libbsp_a_LIBADD = libnds9.rel libdldi.rel if HAS_NETWORKING libbsp_a_LIBADD += wifi.rel dswifi9.rel From joel at rtems.org Wed Aug 27 17:41:54 2014 From: joel at rtems.org (Joel Sherrill) Date: Wed, 27 Aug 2014 12:41:54 -0500 Subject: [rtems commit] virtex5/.../bsp.h: Add BSP_Convert_decrementer() macro required by MPC6xx timer driver Message-ID: <20140827174155.0759370080E@git.rtems.org> Module: rtems Branch: master Commit: bfa2b8c39ee19006e75d5ea3890fdda3eec4f9b7 Changeset: http://git.rtems.org/rtems/commit/?id=bfa2b8c39ee19006e75d5ea3890fdda3eec4f9b7 Author: Joel Sherrill Date: Wed Aug 27 12:50:36 2014 -0500 virtex5/.../bsp.h: Add BSP_Convert_decrementer() macro required by MPC6xx timer driver --- c/src/lib/libbsp/powerpc/virtex5/include/bsp.h | 27 +++++++++++++++++++++-- 1 files changed, 24 insertions(+), 3 deletions(-) diff --git a/c/src/lib/libbsp/powerpc/virtex5/include/bsp.h b/c/src/lib/libbsp/powerpc/virtex5/include/bsp.h index 2e21129..8558faa 100644 --- a/c/src/lib/libbsp/powerpc/virtex5/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/virtex5/include/bsp.h @@ -1,7 +1,9 @@ -/* bsp.h +/* @file * * This include file contains all GEN405 board IO definitions. - * + */ + +/* * derived from helas403/include/bsp.h: * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp * Author: Thomas Doerfler @@ -67,7 +69,26 @@ extern "C" { /* miscellaneous stuff assumed to exist */ extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ -extern rtems_configuration_table BSP_Configuration; /* owned by BSP */ +/* + * Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * Processor Clock Frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +/* + * Macro used by shared MPC6xx timer driver + */ +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + + #endif /* ASM */ void BSP_ask_for_reset(void); From chrisj at rtems.org Thu Aug 28 00:54:02 2014 From: chrisj at rtems.org (Chris Johns) Date: Wed, 27 Aug 2014 19:54:02 -0500 Subject: [rtems commit] preinstall: Regenerated files differ from the repo. Message-ID: <20140828005403.4B659700810@git.rtems.org> Module: rtems Branch: master Commit: 5826a1b284450778be4b73276560a48ccd0cd9a7 Changeset: http://git.rtems.org/rtems/commit/?id=5826a1b284450778be4b73276560a48ccd0cd9a7 Author: Chris Johns Date: Thu Aug 28 10:08:00 2014 +1000 preinstall: Regenerated files differ from the repo. --- .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 12 ++++++------ c/src/lib/libbsp/or1k/or1ksim/preinstall.am | 13 +++++++------ c/src/lib/libbsp/or1k/preinstall.am | 1 + c/src/lib/libcpu/or1k/preinstall.am | 7 ++++--- 4 files changed, 18 insertions(+), 15 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 768c01d..5b6b9fd 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) +CLEANFILES = $(TMPINSTALL_FILES) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am index cbdf3df..2569864 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am +++ b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) +CLEANFILES = $(TMPINSTALL_FILES) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @@ -117,3 +117,4 @@ TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds $(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base + diff --git a/c/src/lib/libbsp/or1k/preinstall.am b/c/src/lib/libbsp/or1k/preinstall.am index 1143c2e..dba6cc4 100644 --- a/c/src/lib/libbsp/or1k/preinstall.am +++ b/c/src/lib/libbsp/or1k/preinstall.am @@ -4,3 +4,4 @@ if AMPOLISH3 $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif + diff --git a/c/src/lib/libcpu/or1k/preinstall.am b/c/src/lib/libcpu/or1k/preinstall.am index 9670596..ee9d0da 100644 --- a/c/src/lib/libcpu/or1k/preinstall.am +++ b/c/src/lib/libcpu/or1k/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) @@ -21,3 +21,4 @@ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) $(PROJECT_INCLUDE)/libcpu/cache.h: ../shared/include/cache.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache.h + From chrisj at rtems.org Thu Aug 28 04:25:49 2014 From: chrisj at rtems.org (Chris Johns) Date: Wed, 27 Aug 2014 23:25:49 -0500 Subject: [rtems commit] arm: Add tests which fail to build with C++ enabled. Message-ID: <20140828042549.D503C70080E@git.rtems.org> Module: rtems Branch: master Commit: d04cb1242d0b359acd9c7f976dd8b6472e5da101 Changeset: http://git.rtems.org/rtems/commit/?id=d04cb1242d0b359acd9c7f976dd8b6472e5da101 Author: Chris Johns Date: Thu Aug 28 14:34:10 2014 +1000 arm: Add tests which fail to build with C++ enabled. --- .../lm3s69xx/make/custom/lm3s6965-testsuite.tcfg | 2 ++ .../lm3s69xx/make/custom/lm4f120-testsuite.tcfg | 4 ++++ .../make/custom/lpc1768_mbed-testsuite.tcfg | 2 ++ .../custom/lpc1768_mbed_ahb_ram-testsuite.tcfg | 2 ++ .../arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg | 4 ++++ .../make/custom/lpc23xx_tli800-testsuite.tcfg | 4 ++++ .../make/custom/lpc32xx_mzx_stage_1-testsuite.tcfg | 2 ++ .../arm/rtl22xx/make/custom/rtl22xx-testsuite.tcfg | 2 ++ .../stm32f4/make/custom/stm32f105rc-testsuite.tcfg | 2 ++ 9 files changed, 24 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965-testsuite.tcfg b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965-testsuite.tcfg index 77395c7..7e1706e 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm3s6965-testsuite.tcfg @@ -5,6 +5,7 @@ # fileio +iostream flashdisk01 fsdosfsname01 ftp01 @@ -19,3 +20,4 @@ mghttpd01 monitor02 utf8proc01 pppd +rtems++ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm4f120-testsuite.tcfg b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm4f120-testsuite.tcfg index d7ec311..b4b9365 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm4f120-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lm3s69xx/make/custom/lm4f120-testsuite.tcfg @@ -5,6 +5,8 @@ # fileio +cdtest +iostream flashdisk01 fsdosfsname01 ftp01 @@ -22,4 +24,6 @@ sp16 sp25 sp48 spstkalloc02 +sptls02 +rtems++ utf8proc01 diff --git a/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed-testsuite.tcfg index 910bf59..2a7d71b 100644 --- a/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed-testsuite.tcfg @@ -17,3 +17,5 @@ jffs2_fssymlink jffs2_fstime pppd mghttpd01 +iostream +rtems++ diff --git a/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed_ahb_ram-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed_ahb_ram-testsuite.tcfg index 659276b..748b271 100644 --- a/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed_ahb_ram-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lpc176x/make/custom/lpc1768_mbed_ahb_ram-testsuite.tcfg @@ -17,3 +17,5 @@ mghttpd01 pppd spstkalloc02 utf8proc01 +iostream +rtems++ diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg index 47bd346..4d7f178 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg @@ -5,11 +5,13 @@ # capture +cdtest fileio flashdisk01 fsdosfsname01 fsrfsbitmap01 ftp01 +iostream jffs2_fserror jffs2_fslink jffs2_fspatheval @@ -30,6 +32,8 @@ mrfs_fsrdwr mrfs_fssymlink mrfs_fstime pppd +rtems++ spstkalloc02 +sptls02 syscall01 utf8proc01 diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc23xx_tli800-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc23xx_tli800-testsuite.tcfg index 4b47039..a678ca2 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc23xx_tli800-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc23xx_tli800-testsuite.tcfg @@ -5,12 +5,14 @@ # capture +cdtest fileio flashdisk01 fsdosfsformat01 fsdosfsname01 fsrfsbitmap01 ftp01 +iostream jffs2_fserror jffs2_fslink jffs2_fspatheval @@ -33,6 +35,8 @@ mrfs_fstime mdosfs_fsrdwr paranoia pppd +rtems++ +sptls02 spstkalloc02 syscall01 utf8proc01 diff --git a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_stage_1-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_stage_1-testsuite.tcfg index 9228d0e..68cfc64 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_stage_1-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_stage_1-testsuite.tcfg @@ -7,6 +7,7 @@ fileio ftp01 fsdosfsname01 +iostream jffs2_fserror jffs2_fslink jffs2_fspatheval @@ -17,4 +18,5 @@ jffs2_fstime mghttpd01 monitor02 pppd +rtems++ utf8proc01 diff --git a/c/src/lib/libbsp/arm/rtl22xx/make/custom/rtl22xx-testsuite.tcfg b/c/src/lib/libbsp/arm/rtl22xx/make/custom/rtl22xx-testsuite.tcfg index 3992b31..d23a630 100644 --- a/c/src/lib/libbsp/arm/rtl22xx/make/custom/rtl22xx-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/rtl22xx/make/custom/rtl22xx-testsuite.tcfg @@ -5,4 +5,6 @@ # fsdosfsname01 +iostream +rtems++ utf8proc01 diff --git a/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f105rc-testsuite.tcfg b/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f105rc-testsuite.tcfg index 89fdf29..be079fb 100644 --- a/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f105rc-testsuite.tcfg +++ b/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f105rc-testsuite.tcfg @@ -8,6 +8,7 @@ fileio flashdisk01 fsdosfsname01 ftp01 +iostream jffs2_fserror jffs2_fslink jffs2_fspatheval @@ -18,4 +19,5 @@ jffs2_fstime mghttpd01 monitor02 pppd +rtems++ utf8proc01 From joel at rtems.org Thu Aug 28 13:36:52 2014 From: joel at rtems.org (Joel Sherrill) Date: Thu, 28 Aug 2014 08:36:52 -0500 Subject: [rtems commit] Regenerate all preinstall.am files. Message-ID: <20140828133652.753BF700810@git.rtems.org> Module: rtems Branch: master Commit: b597c0d60ce789c3f3708108c7a5abd75eecfbdf Changeset: http://git.rtems.org/rtems/commit/?id=b597c0d60ce789c3f3708108c7a5abd75eecfbdf Author: Joel Sherrill Date: Thu Aug 28 08:44:52 2014 -0500 Regenerate all preinstall.am files. Apparently, at some point automake output changed and these were not updated. --- .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/csb336/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/csb337/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/edb7312/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/gdbarmsim/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/gp32/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/gumstix/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/lm3s69xx/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/lpc24xx/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/lpc32xx/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/nds/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/raspberrypi/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/stm32f4/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/tms570/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am | 14 +++++++------- c/src/lib/libbsp/bfin/TLL6527M/preinstall.am | 6 +++--- c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am | 14 +++++++------- c/src/lib/libbsp/bfin/eZKit533/preinstall.am | 12 ++++++------ c/src/lib/libbsp/lm32/lm32_evr/preinstall.am | 6 +++--- c/src/lib/libbsp/lm32/milkymist/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m32r/m32rsim/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/av5282/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/csb360/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/gen68302/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/gen68340/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/gen68360/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/genmcf548x/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/idp/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mcf52235/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mcf5235/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/mcf5329/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mrm332/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mvme136/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mvme147/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mvme147s/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/mvme162/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/mvme167/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/ods68302/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/uC5282/preinstall.am | 14 +++++++------- c/src/lib/libbsp/mips/csb350/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/genmongoosev/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/malta/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/rbtx4938/preinstall.am | 12 ++++++------ c/src/lib/libbsp/moxie/moxiesim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/nios2/nios2_iss/preinstall.am | 6 +++--- c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am | 6 +++--- c/src/lib/libbsp/or1k/or1ksim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/beatnik/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/ep1a/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/gen5200/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/gen83xx/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/haleakala/preinstall.am | 14 +++++++------- c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am | 12 ++++++------ .../libbsp/powerpc/motorola_powerpc/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/mpc8260ads/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/psim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/qemuppc/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/qoriq/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/score603e/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/ss555/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/t32mppc/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/virtex/preinstall.am | 14 +++++++------- c/src/lib/libbsp/powerpc/virtex4/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/virtex5/preinstall.am | 14 +++++++------- c/src/lib/libbsp/sh/gensh1/preinstall.am | 10 +++++----- c/src/lib/libbsp/sh/gensh2/preinstall.am | 10 +++++----- c/src/lib/libbsp/sh/gensh4/preinstall.am | 6 +++--- c/src/lib/libbsp/sh/shsim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/sparc/erc32/preinstall.am | 12 ++++++------ c/src/lib/libbsp/sparc/leon2/preinstall.am | 12 ++++++------ c/src/lib/libbsp/sparc/leon3/preinstall.am | 6 +++--- c/src/lib/libbsp/sparc64/usiii/preinstall.am | 6 +++--- c/src/lib/libcpu/arm/preinstall.am | 6 +++--- c/src/lib/libcpu/bfin/preinstall.am | 6 +++--- c/src/lib/libcpu/lm32/preinstall.am | 6 +++--- c/src/lib/libcpu/mips/preinstall.am | 6 +++--- c/src/lib/libcpu/powerpc/preinstall.am | 6 +++--- c/src/lib/libcpu/sparc64/preinstall.am | 6 +++--- c/src/librtems++/preinstall.am | 12 ++++++------ cpukit/ftpd/preinstall.am | 6 +++--- cpukit/mghttpd/preinstall.am | 12 ++++++------ cpukit/posix/preinstall.am | 6 +++--- cpukit/preinstall.am | 6 +++--- cpukit/score/cpu/bfin/preinstall.am | 6 +++--- cpukit/score/cpu/h8300/preinstall.am | 6 +++--- cpukit/score/cpu/i386/preinstall.am | 6 +++--- cpukit/score/cpu/m32r/preinstall.am | 6 +++--- cpukit/score/cpu/mips/preinstall.am | 6 +++--- cpukit/score/cpu/powerpc/preinstall.am | 6 +++--- cpukit/score/cpu/sparc64/preinstall.am | 6 +++--- cpukit/score/preinstall.am | 6 +++--- cpukit/telnetd/preinstall.am | 12 ++++++------ cpukit/zlib/preinstall.am | 6 +++--- 95 files changed, 464 insertions(+), 464 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 5b6b9fd..2627812 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/csb336/preinstall.am b/c/src/lib/libbsp/arm/csb336/preinstall.am index 389ac9a..9fdcef7 100644 --- a/c/src/lib/libbsp/arm/csb336/preinstall.am +++ b/c/src/lib/libbsp/arm/csb336/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/csb337/preinstall.am b/c/src/lib/libbsp/arm/csb337/preinstall.am index f067f39..33eaa98 100644 --- a/c/src/lib/libbsp/arm/csb337/preinstall.am +++ b/c/src/lib/libbsp/arm/csb337/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/edb7312/preinstall.am b/c/src/lib/libbsp/arm/edb7312/preinstall.am index 59bd50a..7b0639f 100644 --- a/c/src/lib/libbsp/arm/edb7312/preinstall.am +++ b/c/src/lib/libbsp/arm/edb7312/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am b/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am index 049f288..53ad826 100644 --- a/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am +++ b/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/gp32/preinstall.am b/c/src/lib/libbsp/arm/gp32/preinstall.am index e2bd7e9..1d72ddf 100644 --- a/c/src/lib/libbsp/arm/gp32/preinstall.am +++ b/c/src/lib/libbsp/arm/gp32/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/gumstix/preinstall.am b/c/src/lib/libbsp/arm/gumstix/preinstall.am index dea7ee9..2188049 100644 --- a/c/src/lib/libbsp/arm/gumstix/preinstall.am +++ b/c/src/lib/libbsp/arm/gumstix/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am b/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am index db476c2..eb4b176 100644 --- a/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lm3s69xx/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am index 3bf67a6..0e65c58 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am index 79dfb0e..6ba42de 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/nds/preinstall.am b/c/src/lib/libbsp/arm/nds/preinstall.am index e0555de..5ae1d49 100644 --- a/c/src/lib/libbsp/arm/nds/preinstall.am +++ b/c/src/lib/libbsp/arm/nds/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/raspberrypi/preinstall.am b/c/src/lib/libbsp/arm/raspberrypi/preinstall.am index d754fa7..398581a 100644 --- a/c/src/lib/libbsp/arm/raspberrypi/preinstall.am +++ b/c/src/lib/libbsp/arm/raspberrypi/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am b/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am index 0f38c23..5f72122 100644 --- a/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am +++ b/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/stm32f4/preinstall.am b/c/src/lib/libbsp/arm/stm32f4/preinstall.am index a75e3d0..a081a88 100644 --- a/c/src/lib/libbsp/arm/stm32f4/preinstall.am +++ b/c/src/lib/libbsp/arm/stm32f4/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am b/c/src/lib/libbsp/arm/tms570/preinstall.am index d7ac628..f88c7fd 100644 --- a/c/src/lib/libbsp/arm/tms570/preinstall.am +++ b/c/src/lib/libbsp/arm/tms570/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am index f846d75..c079c07 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am b/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am index 557599a..525f222 100644 --- a/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am +++ b/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am b/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am index bdd3a3e..0142ef7 100644 --- a/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am +++ b/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/bfin/eZKit533/preinstall.am b/c/src/lib/libbsp/bfin/eZKit533/preinstall.am index 557599a..e25c8d7 100644 --- a/c/src/lib/libbsp/bfin/eZKit533/preinstall.am +++ b/c/src/lib/libbsp/bfin/eZKit533/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am b/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am index a95af39..981d677 100644 --- a/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am +++ b/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/lm32/milkymist/preinstall.am b/c/src/lib/libbsp/lm32/milkymist/preinstall.am index c3217ef..0ee384d 100644 --- a/c/src/lib/libbsp/lm32/milkymist/preinstall.am +++ b/c/src/lib/libbsp/lm32/milkymist/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m32r/m32rsim/preinstall.am b/c/src/lib/libbsp/m32r/m32rsim/preinstall.am index 73323b5..67ceb2b 100644 --- a/c/src/lib/libbsp/m32r/m32rsim/preinstall.am +++ b/c/src/lib/libbsp/m32r/m32rsim/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/av5282/preinstall.am b/c/src/lib/libbsp/m68k/av5282/preinstall.am index 73323b5..e3970ec 100644 --- a/c/src/lib/libbsp/m68k/av5282/preinstall.am +++ b/c/src/lib/libbsp/m68k/av5282/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/csb360/preinstall.am b/c/src/lib/libbsp/m68k/csb360/preinstall.am index ed79155..1c64e4f 100644 --- a/c/src/lib/libbsp/m68k/csb360/preinstall.am +++ b/c/src/lib/libbsp/m68k/csb360/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/gen68302/preinstall.am b/c/src/lib/libbsp/m68k/gen68302/preinstall.am index 540e452..a63094d 100644 --- a/c/src/lib/libbsp/m68k/gen68302/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68302/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/gen68340/preinstall.am b/c/src/lib/libbsp/m68k/gen68340/preinstall.am index 0c891ea..298545c 100644 --- a/c/src/lib/libbsp/m68k/gen68340/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68340/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/gen68360/preinstall.am b/c/src/lib/libbsp/m68k/gen68360/preinstall.am index 24d5ce9..0a6c6d6 100644 --- a/c/src/lib/libbsp/m68k/gen68360/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68360/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am b/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am index 31ce6bc..331f0b5 100644 --- a/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am +++ b/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/idp/preinstall.am b/c/src/lib/libbsp/m68k/idp/preinstall.am index 1bcb5b6..73bd6bd 100644 --- a/c/src/lib/libbsp/m68k/idp/preinstall.am +++ b/c/src/lib/libbsp/m68k/idp/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mcf52235/preinstall.am b/c/src/lib/libbsp/m68k/mcf52235/preinstall.am index 73323b5..67ceb2b 100644 --- a/c/src/lib/libbsp/m68k/mcf52235/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf52235/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/mcf5235/preinstall.am b/c/src/lib/libbsp/m68k/mcf5235/preinstall.am index 916e8d1..321a130 100644 --- a/c/src/lib/libbsp/m68k/mcf5235/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf5235/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mcf5329/preinstall.am b/c/src/lib/libbsp/m68k/mcf5329/preinstall.am index aaadccc..24be79a 100644 --- a/c/src/lib/libbsp/m68k/mcf5329/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf5329/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mrm332/preinstall.am b/c/src/lib/libbsp/m68k/mrm332/preinstall.am index 4ab583c..e8ddde2 100644 --- a/c/src/lib/libbsp/m68k/mrm332/preinstall.am +++ b/c/src/lib/libbsp/m68k/mrm332/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mvme136/preinstall.am b/c/src/lib/libbsp/m68k/mvme136/preinstall.am index ed79155..312b0f4 100644 --- a/c/src/lib/libbsp/m68k/mvme136/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme136/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mvme147/preinstall.am b/c/src/lib/libbsp/m68k/mvme147/preinstall.am index ed79155..312b0f4 100644 --- a/c/src/lib/libbsp/m68k/mvme147/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme147/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mvme147s/preinstall.am b/c/src/lib/libbsp/m68k/mvme147s/preinstall.am index ed79155..312b0f4 100644 --- a/c/src/lib/libbsp/m68k/mvme147s/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme147s/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mvme162/preinstall.am b/c/src/lib/libbsp/m68k/mvme162/preinstall.am index 528c115..59198f3 100644 --- a/c/src/lib/libbsp/m68k/mvme162/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme162/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mvme167/preinstall.am b/c/src/lib/libbsp/m68k/mvme167/preinstall.am index fd59d14..ea1d67d 100644 --- a/c/src/lib/libbsp/m68k/mvme167/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme167/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/ods68302/preinstall.am b/c/src/lib/libbsp/m68k/ods68302/preinstall.am index f95a843..7f0436f 100644 --- a/c/src/lib/libbsp/m68k/ods68302/preinstall.am +++ b/c/src/lib/libbsp/m68k/ods68302/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/uC5282/preinstall.am b/c/src/lib/libbsp/m68k/uC5282/preinstall.am index 73323b5..e3970ec 100644 --- a/c/src/lib/libbsp/m68k/uC5282/preinstall.am +++ b/c/src/lib/libbsp/m68k/uC5282/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/csb350/preinstall.am b/c/src/lib/libbsp/mips/csb350/preinstall.am index 244a228..d05c802 100644 --- a/c/src/lib/libbsp/mips/csb350/preinstall.am +++ b/c/src/lib/libbsp/mips/csb350/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/genmongoosev/preinstall.am b/c/src/lib/libbsp/mips/genmongoosev/preinstall.am index b2e4615..a6505c0 100644 --- a/c/src/lib/libbsp/mips/genmongoosev/preinstall.am +++ b/c/src/lib/libbsp/mips/genmongoosev/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/malta/preinstall.am b/c/src/lib/libbsp/mips/malta/preinstall.am index 8d22a8c..091e11b 100644 --- a/c/src/lib/libbsp/mips/malta/preinstall.am +++ b/c/src/lib/libbsp/mips/malta/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/rbtx4938/preinstall.am b/c/src/lib/libbsp/mips/rbtx4938/preinstall.am index b2d7806..11efecd 100644 --- a/c/src/lib/libbsp/mips/rbtx4938/preinstall.am +++ b/c/src/lib/libbsp/mips/rbtx4938/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/moxie/moxiesim/preinstall.am b/c/src/lib/libbsp/moxie/moxiesim/preinstall.am index bdd3a3e..347e43d 100644 --- a/c/src/lib/libbsp/moxie/moxiesim/preinstall.am +++ b/c/src/lib/libbsp/moxie/moxiesim/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am b/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am index 5e40708..87f904e 100644 --- a/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am +++ b/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am b/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am index 72d079a..a6a238d 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am +++ b/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am index 2569864..a83e053 100644 --- a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am +++ b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/beatnik/preinstall.am b/c/src/lib/libbsp/powerpc/beatnik/preinstall.am index f2dbe5f..10efa55 100644 --- a/c/src/lib/libbsp/powerpc/beatnik/preinstall.am +++ b/c/src/lib/libbsp/powerpc/beatnik/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/ep1a/preinstall.am b/c/src/lib/libbsp/powerpc/ep1a/preinstall.am index 3680071..88a9e13 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/preinstall.am +++ b/c/src/lib/libbsp/powerpc/ep1a/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/gen5200/preinstall.am b/c/src/lib/libbsp/powerpc/gen5200/preinstall.am index 6720cd2..9f5d146 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/preinstall.am +++ b/c/src/lib/libbsp/powerpc/gen5200/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am index 8fe05dc..ab9dd65 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am +++ b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/haleakala/preinstall.am b/c/src/lib/libbsp/powerpc/haleakala/preinstall.am index fc36cf9..8f70554 100644 --- a/c/src/lib/libbsp/powerpc/haleakala/preinstall.am +++ b/c/src/lib/libbsp/powerpc/haleakala/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am b/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am index 047971f..43ca5a9 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/preinstall.am b/c/src/lib/libbsp/powerpc/motorola_powerpc/preinstall.am index 248ed37..86585eb 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/preinstall.am +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am b/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am index 50714c3..aa78beb 100644 --- a/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/preinstall.am b/c/src/lib/libbsp/powerpc/mpc8260ads/preinstall.am index 82ab792..071a7e3 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/psim/preinstall.am b/c/src/lib/libbsp/powerpc/psim/preinstall.am index 044618b..ecf4a2b 100644 --- a/c/src/lib/libbsp/powerpc/psim/preinstall.am +++ b/c/src/lib/libbsp/powerpc/psim/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am b/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am index 0a0653a..4fa463d 100644 --- a/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am +++ b/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/qoriq/preinstall.am b/c/src/lib/libbsp/powerpc/qoriq/preinstall.am index 34d6cab..8adee61 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/preinstall.am +++ b/c/src/lib/libbsp/powerpc/qoriq/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/score603e/preinstall.am b/c/src/lib/libbsp/powerpc/score603e/preinstall.am index 4d2f767..036f227 100644 --- a/c/src/lib/libbsp/powerpc/score603e/preinstall.am +++ b/c/src/lib/libbsp/powerpc/score603e/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/ss555/preinstall.am b/c/src/lib/libbsp/powerpc/ss555/preinstall.am index a21da1f..6d7cb01 100644 --- a/c/src/lib/libbsp/powerpc/ss555/preinstall.am +++ b/c/src/lib/libbsp/powerpc/ss555/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am b/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am index 2d73712..d3bec9c 100644 --- a/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am +++ b/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/virtex/preinstall.am b/c/src/lib/libbsp/powerpc/virtex/preinstall.am index 07c6ff9..e8b4481 100644 --- a/c/src/lib/libbsp/powerpc/virtex/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/virtex4/preinstall.am b/c/src/lib/libbsp/powerpc/virtex4/preinstall.am index e441f38..f507474 100644 --- a/c/src/lib/libbsp/powerpc/virtex4/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex4/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/virtex5/preinstall.am b/c/src/lib/libbsp/powerpc/virtex5/preinstall.am index e441f38..b0155fc 100644 --- a/c/src/lib/libbsp/powerpc/virtex5/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex5/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sh/gensh1/preinstall.am b/c/src/lib/libbsp/sh/gensh1/preinstall.am index 639852c..0334fd7 100644 --- a/c/src/lib/libbsp/sh/gensh1/preinstall.am +++ b/c/src/lib/libbsp/sh/gensh1/preinstall.am @@ -8,16 +8,16 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/sh/gensh2/preinstall.am b/c/src/lib/libbsp/sh/gensh2/preinstall.am index 7d4c5ec..b44511c 100644 --- a/c/src/lib/libbsp/sh/gensh2/preinstall.am +++ b/c/src/lib/libbsp/sh/gensh2/preinstall.am @@ -8,16 +8,16 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/sh/gensh4/preinstall.am b/c/src/lib/libbsp/sh/gensh4/preinstall.am index 3821249..b7d09e5 100644 --- a/c/src/lib/libbsp/sh/gensh4/preinstall.am +++ b/c/src/lib/libbsp/sh/gensh4/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libbsp/sh/shsim/preinstall.am b/c/src/lib/libbsp/sh/shsim/preinstall.am index 9e08790..202e051 100644 --- a/c/src/lib/libbsp/sh/shsim/preinstall.am +++ b/c/src/lib/libbsp/sh/shsim/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sparc/erc32/preinstall.am b/c/src/lib/libbsp/sparc/erc32/preinstall.am index 71ef19e..7bae1e1 100644 --- a/c/src/lib/libbsp/sparc/erc32/preinstall.am +++ b/c/src/lib/libbsp/sparc/erc32/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sparc/leon2/preinstall.am b/c/src/lib/libbsp/sparc/leon2/preinstall.am index 006bb70..a3bcae5 100644 --- a/c/src/lib/libbsp/sparc/leon2/preinstall.am +++ b/c/src/lib/libbsp/sparc/leon2/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sparc/leon3/preinstall.am b/c/src/lib/libbsp/sparc/leon3/preinstall.am index 210558e..443400d 100644 --- a/c/src/lib/libbsp/sparc/leon3/preinstall.am +++ b/c/src/lib/libbsp/sparc/leon3/preinstall.am @@ -5,9 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -18,6 +15,9 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/sparc64/usiii/preinstall.am b/c/src/lib/libbsp/sparc64/usiii/preinstall.am index 73f10f9..2122b19 100644 --- a/c/src/lib/libbsp/sparc64/usiii/preinstall.am +++ b/c/src/lib/libbsp/sparc64/usiii/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = diff --git a/c/src/lib/libcpu/arm/preinstall.am b/c/src/lib/libcpu/arm/preinstall.am index 751a085..c756d19 100644 --- a/c/src/lib/libcpu/arm/preinstall.am +++ b/c/src/lib/libcpu/arm/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/bfin/preinstall.am b/c/src/lib/libcpu/bfin/preinstall.am index a8b2fa9..36f6ca9 100644 --- a/c/src/lib/libcpu/bfin/preinstall.am +++ b/c/src/lib/libcpu/bfin/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/lm32/preinstall.am b/c/src/lib/libcpu/lm32/preinstall.am index 0516c2c..9667d9c 100644 --- a/c/src/lib/libcpu/lm32/preinstall.am +++ b/c/src/lib/libcpu/lm32/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + if shared $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu diff --git a/c/src/lib/libcpu/mips/preinstall.am b/c/src/lib/libcpu/mips/preinstall.am index 4a83d60..0f5a379 100644 --- a/c/src/lib/libcpu/mips/preinstall.am +++ b/c/src/lib/libcpu/mips/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) diff --git a/c/src/lib/libcpu/powerpc/preinstall.am b/c/src/lib/libcpu/powerpc/preinstall.am index 129855e..33d79d9 100644 --- a/c/src/lib/libcpu/powerpc/preinstall.am +++ b/c/src/lib/libcpu/powerpc/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/sparc64/preinstall.am b/c/src/lib/libcpu/sparc64/preinstall.am index 83b9153..ab9d46e 100644 --- a/c/src/lib/libcpu/sparc64/preinstall.am +++ b/c/src/lib/libcpu/sparc64/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + if shared $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu diff --git a/c/src/librtems++/preinstall.am b/c/src/librtems++/preinstall.am index 256004c..55d3cbf 100644 --- a/c/src/librtems++/preinstall.am +++ b/c/src/librtems++/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/ftpd/preinstall.am b/cpukit/ftpd/preinstall.am index 85ae87d..abeefb3 100644 --- a/cpukit/ftpd/preinstall.am +++ b/cpukit/ftpd/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/cpukit/mghttpd/preinstall.am b/cpukit/mghttpd/preinstall.am index 305a914..b63c988 100644 --- a/cpukit/mghttpd/preinstall.am +++ b/cpukit/mghttpd/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/posix/preinstall.am b/cpukit/posix/preinstall.am index 6e3f2a2..beb6d58 100644 --- a/cpukit/posix/preinstall.am +++ b/cpukit/posix/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/preinstall.am b/cpukit/preinstall.am index 70923f0..b2f88a9 100644 --- a/cpukit/preinstall.am +++ b/cpukit/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/score/cpu/bfin/preinstall.am b/cpukit/score/cpu/bfin/preinstall.am index a16a047..c5f501c 100644 --- a/cpukit/score/cpu/bfin/preinstall.am +++ b/cpukit/score/cpu/bfin/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/h8300/preinstall.am b/cpukit/score/cpu/h8300/preinstall.am index f3c1681..0f89b1c 100644 --- a/cpukit/score/cpu/h8300/preinstall.am +++ b/cpukit/score/cpu/h8300/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/i386/preinstall.am b/cpukit/score/cpu/i386/preinstall.am index 060176b..2d29558 100644 --- a/cpukit/score/cpu/i386/preinstall.am +++ b/cpukit/score/cpu/i386/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/m32r/preinstall.am b/cpukit/score/cpu/m32r/preinstall.am index 3d76b74..044514a 100644 --- a/cpukit/score/cpu/m32r/preinstall.am +++ b/cpukit/score/cpu/m32r/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/score/cpu/mips/preinstall.am b/cpukit/score/cpu/mips/preinstall.am index 2385f8c..bca004a 100644 --- a/cpukit/score/cpu/mips/preinstall.am +++ b/cpukit/score/cpu/mips/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/powerpc/preinstall.am b/cpukit/score/cpu/powerpc/preinstall.am index 3293498..ccc4cbe 100644 --- a/cpukit/score/cpu/powerpc/preinstall.am +++ b/cpukit/score/cpu/powerpc/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/sparc64/preinstall.am b/cpukit/score/cpu/sparc64/preinstall.am index 00af891..3f53e73 100644 --- a/cpukit/score/cpu/sparc64/preinstall.am +++ b/cpukit/score/cpu/sparc64/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/preinstall.am b/cpukit/score/preinstall.am index 891c21e..a1e4583 100644 --- a/cpukit/score/preinstall.am +++ b/cpukit/score/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/telnetd/preinstall.am b/cpukit/telnetd/preinstall.am index 68bf81f..9acb287 100644 --- a/cpukit/telnetd/preinstall.am +++ b/cpukit/telnetd/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/zlib/preinstall.am b/cpukit/zlib/preinstall.am index ea2f248..27b3248 100644 --- a/cpukit/zlib/preinstall.am +++ b/cpukit/zlib/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = From chrisj at rtems.org Fri Aug 29 01:43:10 2014 From: chrisj at rtems.org (Chris Johns) Date: Thu, 28 Aug 2014 20:43:10 -0500 Subject: [rtems-source-builder commit] Fix bug of uncompressing zip files. Message-ID: <20140829014310.89820700852@git.rtems.org> Module: rtems-source-builder Branch: master Commit: e7a6292cb590ec5629abaa94e17a38bd6a368ad1 Changeset: http://git.rtems.org/rtems-source-builder/commit/?id=e7a6292cb590ec5629abaa94e17a38bd6a368ad1 Author: Hesham ALMatary Date: Thu Aug 28 19:14:05 2014 +0200 Fix bug of uncompressing zip files. This patch uses __unzip macro for uncompressing zip files instead of the wrong __zip macro which is not defined in defaults.mc file. --- source-builder/sb/download.py | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/source-builder/sb/download.py b/source-builder/sb/download.py index fbf9ce0..fdc834a 100644 --- a/source-builder/sb/download.py +++ b/source-builder/sb/download.py @@ -110,7 +110,7 @@ def _http_parser(source, config, opts): source['compressed'] = '%{__bzip2} -dc' elif esl[-1:][0] == 'zip': source['compressed-type'] = 'zip' - source['compressed'] = '%{__zip} -u' + source['compressed'] = '%{__unzip} -u' elif esl[-1:][0] == 'xz': source['compressed-type'] = 'xz' source['compressed'] = '%{__xz} -dc' From chrisj at rtems.org Fri Aug 29 01:43:10 2014 From: chrisj at rtems.org (Chris Johns) Date: Thu, 28 Aug 2014 20:43:10 -0500 Subject: [rtems-source-builder commit] Add support for building bare-metal or1ksim. Message-ID: <20140829014310.C7F6970064D@git.rtems.org> Module: rtems-source-builder Branch: master Commit: 183626a1d4c88bd5e2a829154b1db72642240729 Changeset: http://git.rtems.org/rtems-source-builder/commit/?id=183626a1d4c88bd5e2a829154b1db72642240729 Author: Hesham ALMatary Date: Thu Aug 28 19:14:34 2014 +0200 Add support for building bare-metal or1ksim. This patch adds support to enable RSB to build or1ksim emulator (the main OpenRISC 1000 simulator) from latest or1ksim github repo. --- bare/config/devel/or1ksim-1.1.0.cfg | 16 +++++++++ bare/config/devel/or1ksim.bset | 7 ++++ source-builder/config/or1ksim-1-1.cfg | 57 +++++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+), 0 deletions(-) diff --git a/bare/config/devel/or1ksim-1.1.0.cfg b/bare/config/devel/or1ksim-1.1.0.cfg new file mode 100644 index 0000000..bfd1a44 --- /dev/null +++ b/bare/config/devel/or1ksim-1.1.0.cfg @@ -0,0 +1,16 @@ +# +# or1ksim emulator 1.1.0 +# + +%if %{release} == %{nil} +%define release 1 +%endif + +%include %{_configdir}/base.cfg + +%define or1ksim_version 1.1.0 + +# +# The or1ksim build instructions. We use 1.x.x Release 1. +# +%include %{_configdir}/or1ksim-1-1.cfg diff --git a/bare/config/devel/or1ksim.bset b/bare/config/devel/or1ksim.bset new file mode 100644 index 0000000..2941553 --- /dev/null +++ b/bare/config/devel/or1ksim.bset @@ -0,0 +1,7 @@ +# +# Build set for or1ksim emulator +# + +%define release 1 + +devel/or1ksim-1.1.0 diff --git a/source-builder/config/or1ksim-1-1.cfg b/source-builder/config/or1ksim-1-1.cfg new file mode 100644 index 0000000..30dfe13 --- /dev/null +++ b/source-builder/config/or1ksim-1-1.cfg @@ -0,0 +1,57 @@ +# +# or1ksim 1.x.x Version 1. +# +# This configuration file configure's, make's and install's or1ksim. +# + +%if %{release} == %{nil} +%define release 1 +%endif + +Name: or1ksim-1.1.0 +Summary: or1ksim-github +Version: %{or1ksim_version} +Release: %{release} +URL: https://github.com/openrisc/or1ksim +BuildRoot: %{_tmppath}/%{name}-root-%(%{__id_u} -n) + +# +# Source +# +%source set or1ksim https://github.com/openrisc/or1ksim/archive/or1k-master.zip + +# +# Prepare the source code. +# +%prep + build_top=$(pwd) + + %source setup or1ksim -q -n or1ksim-or1k-master + + cd ${build_top} + +%build + build_top=$(pwd) + + cd or1ksim-or1k-master/ + + ../or1ksim-or1k-master/configure \ + --target=or1k-elf \ + --prefix=%{_prefix} \ + CFLAGS="-O0 -DINLINE=static -DNO_SOFTFLOAT_UNUSED" + + + %{__make} %{?_smp_mflags} all$ + + + cd ${build_top} + +%install + build_top=$(pwd) + + rm -rf $SB_BUILD_ROOT + + cd or1ksim-or1k-master + %{__make} DESTDIR=$SB_BUILD_ROOT PREFIX=%{_prefix} install + + cd ${build_top} From joel at rtems.org Fri Aug 29 18:24:58 2014 From: joel at rtems.org (Joel Sherrill) Date: Fri, 29 Aug 2014 13:24:58 -0500 Subject: [examples-v2 commit] example-v2 patch for RPi B+ (led) Message-ID: <20140829182459.3811C70025E@git.rtems.org> Module: examples-v2 Branch: master Commit: 944b4f1f73e8f173fd9c3efaaf79a4b542375106 Changeset: http://git.rtems.org/examples-v2/commit/?id=944b4f1f73e8f173fd9c3efaaf79a4b542375106 Author: Pierre Ficheux Date: Fri Aug 29 08:16:23 2014 -0500 example-v2 patch for RPi B+ (led) Hi, Here is the patch for "example-v2" project to support Raspberry Pi B+ as led number is now 47 instead of 16 on RPi B. regards -- Pierre FICHEUX -/- CTO OW/OWI, France -\- pierre.ficheux at openwide.fr http://ingenierie.openwide.fr http://www.linuxembedded.fr I would love to change the world, but they won't give me the source code >From e4d8edfb8650207641bc8e2716cf15ce958ede0f Mon Sep 17 00:00:00 2001 From: Pierre FICHEUX Date: Fri, 29 Aug 2014 15:11:41 +0200 Subject: [PATCH] Added led blink support for RPi B+ --- led/led.h | 16 ++++++++++++---- 1 files changed, 12 insertions(+), 4 deletions(-) diff --git a/led/led.h b/led/led.h index 152b76a..3fee684 100644 --- a/led/led.h +++ b/led/led.h @@ -67,10 +67,18 @@ uint8_t MPC8313_LED_Count; #define OUT_GPIO(g) *(gpio+((g)/10)) |= (1<<(((g)%10)*3)) #define GPIO_SET *(gpio+7) // sets bits which are 1 ignores bits which are 0 #define GPIO_CLR *(gpio+10) // clears bits which are 1 ignores bits which are 0 - -#define LED_INIT() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; OUT_GPIO(16);} while(0) -#define LED_ON() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_CLR = 1 << 16;} while(0) -#define LED_OFF() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_SET = 1 << 16;} while(0) +// For GPIO# >= 32 (RPi B+) +#define GPIO_SET_EXT *(gpio+8) // sets bits which are 1 ignores bits which are 0 +#define GPIO_CLR_EXT *(gpio+11) // clears bits which are 1 ignores bits which are 0 + +// RPi B +//#define LED_INIT() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; OUT_GPIO(16);} while(0) +//#define LED_ON() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_CLR = 1 << 16;} while(0) +//#define LED_OFF() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_SET = 1 << 16;} while(0) +// RPi B+ => led 47 +#define LED_INIT() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; OUT_GPIO(47);} while(0) +#define LED_ON() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_CLR_EXT = 1 << (47 % 32);} while(0) +#define LED_OFF() do { unsigned int *gpio = (unsigned int *)BCM2835_GPIO_REGS_BASE; GPIO_SET_EXT = 1 << (47 % 32);} while(0) #else /* default case is to print */ From joel at rtems.org Fri Aug 29 18:24:58 2014 From: joel at rtems.org (Joel Sherrill) Date: Fri, 29 Aug 2014 13:24:58 -0500 Subject: [examples-v2 commit] Miscellaneous clean up and warning removal Message-ID: <20140829182458.DD57E70080E@git.rtems.org> Module: examples-v2 Branch: master Commit: 61d2a1f2e8ddb992f98e80cd503879226730eeec Changeset: http://git.rtems.org/examples-v2/commit/?id=61d2a1f2e8ddb992f98e80cd503879226730eeec Author: Joel Sherrill Date: Fri Aug 29 13:17:40 2014 -0500 Miscellaneous clean up and warning removal --- cxx/cxx_throw/init.cc | 6 ++++++ hello/hello_world_c/test.c | 7 +++++-- hello/wscript | 1 + led/event_server/init.c | 13 ++++++------- led/msg_server/init.c | 33 +++++++++++++++------------------ led/ratemon1/init.c | 7 +++---- led/ratemon2/init.c | 19 ++++++++----------- led/timeout_event/init.c | 14 ++++++++------ led/timer/init.c | 22 ++++++---------------- led/timer_server/init.c | 25 +++++++------------------ ticker/ticker/init.c | 36 +++++++++++++++--------------------- 11 files changed, 80 insertions(+), 103 deletions(-) diff --git a/cxx/cxx_throw/init.cc b/cxx/cxx_throw/init.cc index 041a73f..b001015 100644 --- a/cxx/cxx_throw/init.cc +++ b/cxx/cxx_throw/init.cc @@ -164,6 +164,12 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE #define CONFIGURE_MAXIMUM_TASKS 1 +/* + * GCC C++ support requires Classic Semaphores but this could change to + * POSIX mutexes at some point in the future. When that happens, this will + * need to change. + */ +#define CONFIGURE_MAXIMUM_SEMAPHORES 1 #define CONFIGURE_INIT diff --git a/hello/hello_world_c/test.c b/hello/hello_world_c/test.c index 67ca6b1..04a55fe 100644 --- a/hello/hello_world_c/test.c +++ b/hello/hello_world_c/test.c @@ -1,8 +1,8 @@ /* - * Simple test program -- simplified version of sample test hello. + * Classic API Hello World */ -#include +#include #include #include @@ -18,9 +18,12 @@ rtems_task Init( /* configuration information */ +#include + /* NOTICE: the clock driver is explicitly disabled */ #define CONFIGURE_APPLICATION_DOES_NOT_NEED_CLOCK_DRIVER #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER +#define CONFIGURE_USE_DEVFS_AS_BASE_FILESYSTEM #define CONFIGURE_RTEMS_INIT_TASKS_TABLE #define CONFIGURE_MAXIMUM_TASKS 1 diff --git a/hello/wscript b/hello/wscript index ca09158..d03283e 100644 --- a/hello/wscript +++ b/hello/wscript @@ -7,6 +7,7 @@ import rtems_waf.rtems as rtems def build(bld): bld.recurse('hello_world_c') + bld.recurse('main') if rtems.check_posix(bld): bld.recurse('posix_hello_world') bld.recurse('both_hello') diff --git a/led/event_server/init.c b/led/event_server/init.c index 5aa82df..90b0360 100644 --- a/led/event_server/init.c +++ b/led/event_server/init.c @@ -17,12 +17,11 @@ rtems_task Test_task( rtems_task_argument unused ) { - rtems_event_set events; - rtems_status_code status; + rtems_event_set events; for ( ; ; ) { events = 0; - status = rtems_event_receive( + (void) rtems_event_receive( (RTEMS_EVENT_1 | RTEMS_EVENT_2), RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, @@ -55,12 +54,12 @@ rtems_task Init( task_name = rtems_build_name( 'T', 'A', '1', ' ' ); - status = rtems_task_create( + (void) rtems_task_create( task_name, 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_MODES, RTEMS_DEFAULT_ATTRIBUTES, &task_id ); - status = rtems_task_start( task_id, Test_task, 1 ); + (void) rtems_task_start( task_id, Test_task, 1 ); for (count=0; ; count++) { @@ -69,10 +68,10 @@ rtems_task Init( if ( status != RTEMS_SUCCESSFUL ) fputs( "send did not work\n", stderr ); - status = rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); + (void) rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ diff --git a/led/msg_server/init.c b/led/msg_server/init.c index 5389d93..4974dea 100644 --- a/led/msg_server/init.c +++ b/led/msg_server/init.c @@ -20,11 +20,10 @@ rtems_task Test_task( { uint32_t count; size_t received; - rtems_status_code status; for ( ; ; ) { count = 0xFFFFFFFF; - status = rtems_message_queue_receive( + (void) rtems_message_queue_receive( Queue_id, (void *) &count, &received, @@ -44,16 +43,15 @@ rtems_task Init( rtems_task_argument argument ) { - uint32_t count = 0; - rtems_status_code status; + uint32_t count; rtems_id task_id; - rtems_name task_name; + rtems_status_code status; puts( "\n\n*** LED BLINKER -- message receive server ***" ); LED_INIT(); - status = rtems_message_queue_create( + (void) rtems_message_queue_create( rtems_build_name( 'Q', '1', ' ', ' ' ), 1, sizeof(uint32_t), @@ -61,14 +59,16 @@ rtems_task Init( &Queue_id ); - task_name = rtems_build_name( 'T', 'A', '1', ' ' ); - - status = rtems_task_create( - task_name, 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_MODES, - RTEMS_DEFAULT_ATTRIBUTES, &task_id + (void) rtems_task_create( + rtems_build_name( 'T', 'A', '1', ' ' ), + 1, + RTEMS_MINIMUM_STACK_SIZE, + RTEMS_DEFAULT_MODES, + RTEMS_DEFAULT_ATTRIBUTES, + &task_id ); - status = rtems_task_start( task_id, Test_task, 1 ); + (void) rtems_task_start( task_id, Test_task, 1 ); for (count=0; ; count++) { @@ -77,16 +77,14 @@ rtems_task Init( if ( status != RTEMS_SUCCESSFUL ) fputs( "send did not work\n", stderr ); - status = rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); + (void) rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ -#define CONFIGURE_INIT - #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER @@ -95,8 +93,7 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE -#define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE) - +#define CONFIGURE_INIT #include /**************** END OF CONFIGURATION INFORMATION ****************/ diff --git a/led/ratemon1/init.c b/led/ratemon1/init.c index 13d977c..4e587f4 100644 --- a/led/ratemon1/init.c +++ b/led/ratemon1/init.c @@ -16,7 +16,6 @@ rtems_task Init( rtems_task_argument argument ) { - rtems_status_code status; rtems_id period_id; rtems_interval ticks; uint32_t count; @@ -25,7 +24,7 @@ rtems_task Init( LED_INIT(); - status = rtems_rate_monotonic_create( + (void) rtems_rate_monotonic_create( rtems_build_name( 'P', 'E', 'R', '1' ), &period_id ); @@ -33,14 +32,14 @@ rtems_task Init( ticks = rtems_clock_get_ticks_per_second(); for (count=0; ; count++) { - status = rtems_rate_monotonic_period( period_id, ticks ); + (void) rtems_rate_monotonic_period( period_id, ticks ); if ( (count % 2) == 0 ) LED_OFF(); else LED_ON(); } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ diff --git a/led/ratemon2/init.c b/led/ratemon2/init.c index c27150b..33aa542 100644 --- a/led/ratemon2/init.c +++ b/led/ratemon2/init.c @@ -16,7 +16,6 @@ rtems_task Init( rtems_task_argument argument ) { - rtems_status_code status; rtems_id period_id1; rtems_id period_id2; rtems_interval ticks; @@ -25,39 +24,38 @@ rtems_task Init( LED_INIT(); - status = rtems_rate_monotonic_create( + (void) rtems_rate_monotonic_create( rtems_build_name( 'P', 'E', 'R', '1' ), &period_id1 ); - status = rtems_rate_monotonic_create( + (void) rtems_rate_monotonic_create( rtems_build_name( 'P', 'E', 'R', '2' ), &period_id2 ); ticks = rtems_clock_get_ticks_per_second(); - status = rtems_rate_monotonic_period( period_id1, 2 * ticks ); + (void) rtems_rate_monotonic_period( period_id1, 2 * ticks ); LED_OFF(); (void) rtems_task_wake_after( ticks ); - status = rtems_rate_monotonic_period( period_id2, 2 * ticks ); + (void) rtems_rate_monotonic_period( period_id2, 2 * ticks ); LED_ON(); while (1) { - status = rtems_rate_monotonic_period( period_id1, 2 * ticks ); + (void) rtems_rate_monotonic_period( period_id1, 2 * ticks ); LED_OFF(); - status = rtems_rate_monotonic_period( period_id2, 2 * ticks ); + (void) rtems_rate_monotonic_period( period_id2, 2 * ticks ); LED_ON(); } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ -#define CONFIGURE_INIT #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER @@ -66,8 +64,7 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE -#define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE) - +#define CONFIGURE_INIT #include /**************** END OF CONFIGURATION INFORMATION ****************/ diff --git a/led/timeout_event/init.c b/led/timeout_event/init.c index b7c35f7..b9e2c77 100644 --- a/led/timeout_event/init.c +++ b/led/timeout_event/init.c @@ -27,8 +27,12 @@ rtems_task Init( for (count=0; ; count++) { - status = rtems_event_receive( RTEMS_EVENT_1, - RTEMS_DEFAULT_OPTIONS, rtems_clock_get_ticks_per_second(), &events ); + status = rtems_event_receive( + RTEMS_EVENT_1, + RTEMS_DEFAULT_OPTIONS, + rtems_clock_get_ticks_per_second(), + &events + ); if ( status != RTEMS_TIMEOUT ) fputs( "receive did not timeout\n", stderr ); @@ -39,12 +43,11 @@ rtems_task Init( } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ -#define CONFIGURE_INIT #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER @@ -52,8 +55,7 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE -#define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE) - +#define CONFIGURE_INIT #include /**************** END OF CONFIGURATION INFORMATION ****************/ diff --git a/led/timer/init.c b/led/timer/init.c index cc44dae..70364ad 100644 --- a/led/timer/init.c +++ b/led/timer/init.c @@ -37,15 +37,13 @@ void LED_Change_Routine( void ) { rtems_timer_service_routine Timer_Routine( rtems_id id, void *ignored ) { - rtems_status_code status; - if ( id == Timer1 ) led_value = 1; else led_value = 2; led_do_print = 1; - status = rtems_timer_fire_after( + (void) rtems_timer_fire_after( id, 2 * rtems_clock_get_ticks_per_second(), Timer_Routine, @@ -57,34 +55,28 @@ rtems_task Init( rtems_task_argument argument ) { - rtems_status_code status; - puts( "\n\n*** LED BLINKER -- timer ***" ); LED_INIT(); - status = rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '1' ), &Timer1); - if ( status != RTEMS_SUCCESSFUL ) - fputs( "Timer1 create failed\n", stderr ); + (void) rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '1' ), &Timer1); - status = rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '2' ), &Timer2); - if ( status != RTEMS_SUCCESSFUL ) - fputs( "Timer2 create failed\n", stderr ); + (void) rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '2' ), &Timer2); Timer_Routine(Timer1, NULL); LED_Change_Routine(); - status = rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); + (void) rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); Timer_Routine(Timer2, NULL); LED_Change_Routine(); while (1) { - status = rtems_task_wake_after( 10 ); + (void) rtems_task_wake_after( 10 ); LED_Change_Routine(); } - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } @@ -98,8 +90,6 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE -#define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE) - #define CONFIGURE_INIT #include /**************** END OF CONFIGURATION INFORMATION ****************/ diff --git a/led/timer_server/init.c b/led/timer_server/init.c index 29d63af..69ec0cb 100644 --- a/led/timer_server/init.c +++ b/led/timer_server/init.c @@ -17,14 +17,12 @@ rtems_id Timer2; rtems_timer_service_routine Timer_Routine( rtems_id id, void *ignored ) { - rtems_status_code status; - if ( id == Timer1 ) LED_OFF(); else LED_ON(); - status = rtems_timer_server_fire_after( + (void) rtems_timer_server_fire_after( id, 2 * rtems_clock_get_ticks_per_second(), Timer_Routine, @@ -36,36 +34,27 @@ rtems_task Init( rtems_task_argument argument ) { - rtems_status_code status; - puts( "\n\n*** LED BLINKER -- timer_server ***" ); LED_INIT(); - status = rtems_timer_initiate_server( + (void) rtems_timer_initiate_server( 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_ATTRIBUTES ); - if ( status != RTEMS_SUCCESSFUL ) - fputs( "timer create server failed\n", stderr ); - - status = rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '1' ), &Timer1); - if ( status != RTEMS_SUCCESSFUL ) - fputs( "Timer1 create failed\n", stderr ); + (void) rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '1' ), &Timer1); - status = rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '2' ), &Timer2); - if ( status != RTEMS_SUCCESSFUL ) - fputs( "Timer2 create failed\n", stderr ); + (void) rtems_timer_create(rtems_build_name( 'T', 'M', 'R', '2' ), &Timer2); Timer_Routine(Timer1, NULL); - status = rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); + (void) rtems_task_wake_after( rtems_clock_get_ticks_per_second() ); Timer_Routine(Timer2, NULL); - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } @@ -79,7 +68,7 @@ rtems_task Init( #define CONFIGURE_RTEMS_INIT_TASKS_TABLE -#define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE) +#define CONFIGURE_EXTRA_TASK_STACKS (RTEMS_MINIMUM_STACK_SIZE) #define CONFIGURE_INIT #include diff --git a/ticker/ticker/init.c b/ticker/ticker/init.c index 4d3d129..4d86cf6 100644 --- a/ticker/ticker/init.c +++ b/ticker/ticker/init.c @@ -18,27 +18,23 @@ rtems_id Task_id[ 4 ]; /* array of task ids */ rtems_name Task_name[ 4 ]; /* array of task names */ rtems_task Test_task( - rtems_task_argument unused + rtems_task_argument task_index ) { - rtems_id tid; rtems_time_of_day time; - uint32_t task_index; - rtems_status_code status; + rtems_interval ticks; + + ticks = task_index * 5 * rtems_clock_get_ticks_per_second(); - status = rtems_task_ident( RTEMS_SELF, RTEMS_SEARCH_ALL_NODES, &tid ); - task_index = task_number( tid ); for ( ; ; ) { - status = rtems_clock_get_tod( &time ); + (void) rtems_clock_get_tod( &time ); if ( time.second >= 35 ) { puts( "*** END OF CLOCK TICK TEST ***" ); exit( 0 ); } put_name( Task_name[ task_index ], FALSE ); print_time( " - rtems_clock_get_tod - ", &time, "\n" ); - status = rtems_task_wake_after( - task_index * 5 * rtems_clock_get_ticks_per_second() - ); + (void) rtems_task_wake_after( ticks ); } } @@ -46,7 +42,6 @@ rtems_task Init( rtems_task_argument argument ) { - rtems_status_code status; rtems_time_of_day time; puts( "\n\n*** CLOCK TICK TEST ***" ); @@ -59,36 +54,34 @@ rtems_task Init( time.second = 0; time.ticks = 0; - status = rtems_clock_set( &time ); + (void) rtems_clock_set( &time ); Task_name[ 1 ] = rtems_build_name( 'T', 'A', '1', ' ' ); Task_name[ 2 ] = rtems_build_name( 'T', 'A', '2', ' ' ); Task_name[ 3 ] = rtems_build_name( 'T', 'A', '3', ' ' ); - status = rtems_task_create( + (void) rtems_task_create( Task_name[ 1 ], 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_MODES, RTEMS_DEFAULT_ATTRIBUTES, &Task_id[ 1 ] ); - status = rtems_task_create( + (void) rtems_task_create( Task_name[ 2 ], 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_MODES, RTEMS_DEFAULT_ATTRIBUTES, &Task_id[ 2 ] ); - status = rtems_task_create( + (void) rtems_task_create( Task_name[ 3 ], 1, RTEMS_MINIMUM_STACK_SIZE * 2, RTEMS_DEFAULT_MODES, RTEMS_DEFAULT_ATTRIBUTES, &Task_id[ 3 ] ); - status = rtems_task_start( Task_id[ 1 ], Test_task, 1 ); - status = rtems_task_start( Task_id[ 2 ], Test_task, 2 ); - status = rtems_task_start( Task_id[ 3 ], Test_task, 3 ); + (void) rtems_task_start( Task_id[ 1 ], Test_task, 1 ); + (void) rtems_task_start( Task_id[ 2 ], Test_task, 2 ); + (void) rtems_task_start( Task_id[ 3 ], Test_task, 3 ); - status = rtems_task_delete( RTEMS_SELF ); + (void) rtems_task_delete( RTEMS_SELF ); } /**************** START OF CONFIGURATION INFORMATION ****************/ -#define CONFIGURE_INIT - #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER @@ -99,6 +92,7 @@ rtems_task Init( #define CONFIGURE_EXTRA_TASK_STACKS (4 * RTEMS_MINIMUM_STACK_SIZE) +#define CONFIGURE_INIT #include /**************** END OF CONFIGURATION INFORMATION ****************/ From chrisj at rtems.org Sat Aug 30 22:37:22 2014 From: chrisj at rtems.org (Chris Johns) Date: Sat, 30 Aug 2014 17:37:22 -0500 Subject: [rtems commit] bootstrap: Sort the various hash keys used in generating preinstall.am. Message-ID: <20140830223723.5D7777006A2@git.rtems.org> Module: rtems Branch: master Commit: 93d0ddd41b6eec7e250eaad1f799cab6cdfb27f8 Changeset: http://git.rtems.org/rtems/commit/?id=93d0ddd41b6eec7e250eaad1f799cab6cdfb27f8 Author: Chris Johns Date: Fri Aug 29 11:39:29 2014 +1000 bootstrap: Sort the various hash keys used in generating preinstall.am. Something must have changed in perl to change the way the keys are ordered by default. --- ampolish3 | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/ampolish3 b/ampolish3 index 69bbf7b..aaa9757 100755 --- a/ampolish3 +++ b/ampolish3 @@ -9,7 +9,7 @@ # # Usage: ampolish3 Makefile.am > preinstall.am # -# Reads a Makefile.am from stdin and writes corresponding +# Reads a Makefile.am from stdin and writes corresponding # pre/tmpinstall rules to stdout. sub replace($); @@ -85,7 +85,7 @@ foreach my $l ( @buffer1 ) { push @buffer2, "$l"; $dirmap{"\$\($1\)"} = replace($2); } elsif ( $l =~ /^\s*noinst_(.*)\s*[\+]?\=(.*)$/o ) - { + { #ignore: noinst_* are not relevant here. } elsif ( $l =~ /^\s*(nodist_|dist_|)(project_|)([a-zA-Z0-9_]+)_(HEADERS|LIBRARIES|DATA|SCRIPTS|PROGRAMS)\s*([\+]?\=)\s*(.*)/o ) { @@ -217,7 +217,7 @@ $output .= "\$(srcdir)/preinstall.am: Makefile.am\n"; $output .= "\t\$(AMPOLISH3) \$(srcdir)/Makefile.am > \$(srcdir)/preinstall.am\n"; $output .= "endif\n\n"; -foreach my $k ( keys %seen ) +foreach my $k ( sort keys %seen ) { if ( $k =~ /PREINSTALL_FILES/o ) { $output .= "all-am: \$(PREINSTALL_FILES)\n\n"; @@ -258,7 +258,7 @@ exit 0; sub replace($) { my ($v) = @_; - foreach my $i ( keys %dirmap ) + foreach my $i ( sort keys %dirmap ) { $v =~ s/\Q$i/$dirmap{$i}/g; } From chrisj at rtems.org Sat Aug 30 22:37:22 2014 From: chrisj at rtems.org (Chris Johns) Date: Sat, 30 Aug 2014 17:37:22 -0500 Subject: [rtems commit] Regenerate all preinstall.am files. Message-ID: <20140830223723.1EBE87006F7@git.rtems.org> Module: rtems Branch: master Commit: 59990cc9752c892dffed6ac0e074d3876c2f663f Changeset: http://git.rtems.org/rtems/commit/?id=59990cc9752c892dffed6ac0e074d3876c2f663f Author: Chris Johns Date: Fri Aug 29 12:48:01 2014 +1000 Regenerate all preinstall.am files. With this patch the preinstall.am files are in a set order and not dependent on now perl implements a hash. --- .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/csb336/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/csb337/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/edb7312/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/gba/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/gdbarmsim/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/gumstix/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/lpc176x/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/lpc24xx/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/lpc32xx/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/rtl22xx/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/smdk2410/preinstall.am | 12 ++++++------ c/src/lib/libbsp/arm/stm32f4/preinstall.am | 14 +++++++------- c/src/lib/libbsp/arm/tms570/preinstall.am | 6 +++--- c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am | 6 +++--- c/src/lib/libbsp/avr/avrtest/preinstall.am | 12 ++++++------ c/src/lib/libbsp/bfin/TLL6527M/preinstall.am | 12 ++++++------ c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am | 6 +++--- c/src/lib/libbsp/bfin/eZKit533/preinstall.am | 6 +++--- c/src/lib/libbsp/h8300/h8sim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/i386/pc386/preinstall.am | 10 +++++----- c/src/lib/libbsp/lm32/lm32_evr/preinstall.am | 12 ++++++------ c/src/lib/libbsp/lm32/milkymist/preinstall.am | 6 +++--- c/src/lib/libbsp/m32c/m32cbsp/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m32r/m32rsim/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/av5282/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/csb360/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/gen68302/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/gen68340/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/gen68360/preinstall.am | 14 +++++++------- c/src/lib/libbsp/m68k/genmcf548x/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/idp/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mcf5206elite/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/mcf52235/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/mcf5225x/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/mcf5329/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mrm332/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mvme136/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mvme147/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mvme147s/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mvme162/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/mvme167/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/ods68302/preinstall.am | 6 +++--- c/src/lib/libbsp/m68k/sim68000/preinstall.am | 12 ++++++------ c/src/lib/libbsp/m68k/uC5282/preinstall.am | 6 +++--- c/src/lib/libbsp/mips/genmongoosev/preinstall.am | 6 +++--- c/src/lib/libbsp/mips/hurricane/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/jmr3904/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/malta/preinstall.am | 6 +++--- c/src/lib/libbsp/mips/rbtx4925/preinstall.am | 12 ++++++------ c/src/lib/libbsp/mips/rbtx4938/preinstall.am | 6 +++--- c/src/lib/libbsp/nios2/nios2_iss/preinstall.am | 14 +++++++------- c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/beatnik/preinstall.am | 10 +++++----- c/src/lib/libbsp/powerpc/gen5200/preinstall.am | 14 +++++++------- c/src/lib/libbsp/powerpc/gen83xx/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/haleakala/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/mvme3100/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/mvme5500/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/psim/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/qemuppc/preinstall.am | 14 +++++++------- c/src/lib/libbsp/powerpc/qoriq/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/score603e/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/ss555/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/t32mppc/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/tqm8xx/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/virtex/preinstall.am | 6 +++--- c/src/lib/libbsp/powerpc/virtex4/preinstall.am | 12 ++++++------ c/src/lib/libbsp/powerpc/virtex5/preinstall.am | 6 +++--- c/src/lib/libbsp/sh/gensh4/preinstall.am | 12 ++++++------ c/src/lib/libbsp/sh/shsim/preinstall.am | 6 +++--- c/src/lib/libbsp/sparc/erc32/preinstall.am | 6 +++--- c/src/lib/libbsp/sparc/leon3/preinstall.am | 14 +++++++------- c/src/lib/libbsp/sparc64/niagara/preinstall.am | 12 ++++++------ c/src/lib/libbsp/sparc64/usiii/preinstall.am | 12 ++++++------ c/src/lib/libbsp/v850/gdbv850sim/preinstall.am | 12 ++++++------ c/src/lib/libcpu/arm/preinstall.am | 6 +++--- c/src/lib/libcpu/bfin/preinstall.am | 6 +++--- c/src/lib/libcpu/lm32/preinstall.am | 6 +++--- c/src/lib/libcpu/mips/preinstall.am | 6 +++--- c/src/lib/libcpu/powerpc/preinstall.am | 6 +++--- c/src/lib/libcpu/sparc64/preinstall.am | 6 +++--- c/src/libchip/preinstall.am | 12 ++++++------ c/src/librtems++/preinstall.am | 6 +++--- cpukit/ftpd/preinstall.am | 6 +++--- cpukit/libfs/src/nfsclient/preinstall.am | 12 ++++++------ cpukit/posix/preinstall.am | 6 +++--- cpukit/pppd/preinstall.am | 12 ++++++------ cpukit/preinstall.am | 6 +++--- cpukit/sapi/preinstall.am | 12 ++++++------ cpukit/score/cpu/bfin/preinstall.am | 6 +++--- cpukit/score/cpu/h8300/preinstall.am | 6 +++--- cpukit/score/cpu/i386/preinstall.am | 6 +++--- cpukit/score/cpu/m32r/preinstall.am | 6 +++--- cpukit/score/cpu/mips/preinstall.am | 6 +++--- cpukit/score/cpu/powerpc/preinstall.am | 6 +++--- cpukit/score/cpu/sparc64/preinstall.am | 6 +++--- cpukit/score/preinstall.am | 6 +++--- cpukit/zlib/preinstall.am | 10 +++++----- 101 files changed, 447 insertions(+), 447 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 2627812..a3e897c 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/csb336/preinstall.am b/c/src/lib/libbsp/arm/csb336/preinstall.am index 9fdcef7..8d27fcc 100644 --- a/c/src/lib/libbsp/arm/csb336/preinstall.am +++ b/c/src/lib/libbsp/arm/csb336/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/csb337/preinstall.am b/c/src/lib/libbsp/arm/csb337/preinstall.am index 33eaa98..1330f04 100644 --- a/c/src/lib/libbsp/arm/csb337/preinstall.am +++ b/c/src/lib/libbsp/arm/csb337/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/arm/edb7312/preinstall.am b/c/src/lib/libbsp/arm/edb7312/preinstall.am index 7b0639f..911f461 100644 --- a/c/src/lib/libbsp/arm/edb7312/preinstall.am +++ b/c/src/lib/libbsp/arm/edb7312/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/gba/preinstall.am b/c/src/lib/libbsp/arm/gba/preinstall.am index 460ba1a..78c7b89 100644 --- a/c/src/lib/libbsp/arm/gba/preinstall.am +++ b/c/src/lib/libbsp/arm/gba/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am b/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am index 53ad826..de1cec0 100644 --- a/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am +++ b/c/src/lib/libbsp/arm/gdbarmsim/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/gumstix/preinstall.am b/c/src/lib/libbsp/arm/gumstix/preinstall.am index 2188049..f08e6a8 100644 --- a/c/src/lib/libbsp/arm/gumstix/preinstall.am +++ b/c/src/lib/libbsp/arm/gumstix/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/lpc176x/preinstall.am b/c/src/lib/libbsp/arm/lpc176x/preinstall.am index cea255b..17a27c3 100644 --- a/c/src/lib/libbsp/arm/lpc176x/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc176x/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am index 0e65c58..4c5e993 100644 --- a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am index 6ba42de..73120d4 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am b/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am index 5f72122..36f9c5e 100644 --- a/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am +++ b/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/rtl22xx/preinstall.am b/c/src/lib/libbsp/arm/rtl22xx/preinstall.am index d721095..6529f3c 100644 --- a/c/src/lib/libbsp/arm/rtl22xx/preinstall.am +++ b/c/src/lib/libbsp/arm/rtl22xx/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/smdk2410/preinstall.am b/c/src/lib/libbsp/arm/smdk2410/preinstall.am index 2de69b2..01d4e66 100644 --- a/c/src/lib/libbsp/arm/smdk2410/preinstall.am +++ b/c/src/lib/libbsp/arm/smdk2410/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/stm32f4/preinstall.am b/c/src/lib/libbsp/arm/stm32f4/preinstall.am index a081a88..6b342d1 100644 --- a/c/src/lib/libbsp/arm/stm32f4/preinstall.am +++ b/c/src/lib/libbsp/arm/stm32f4/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am b/c/src/lib/libbsp/arm/tms570/preinstall.am index f88c7fd..d9a0bd9 100644 --- a/c/src/lib/libbsp/arm/tms570/preinstall.am +++ b/c/src/lib/libbsp/arm/tms570/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am index c079c07..f5367b6 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/avr/avrtest/preinstall.am b/c/src/lib/libbsp/avr/avrtest/preinstall.am index bdd3a3e..347e43d 100644 --- a/c/src/lib/libbsp/avr/avrtest/preinstall.am +++ b/c/src/lib/libbsp/avr/avrtest/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am b/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am index 525f222..3091c71 100644 --- a/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am +++ b/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am b/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am index 0142ef7..347e43d 100644 --- a/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am +++ b/c/src/lib/libbsp/bfin/bf537Stamp/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/bfin/eZKit533/preinstall.am b/c/src/lib/libbsp/bfin/eZKit533/preinstall.am index e25c8d7..3091c71 100644 --- a/c/src/lib/libbsp/bfin/eZKit533/preinstall.am +++ b/c/src/lib/libbsp/bfin/eZKit533/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/h8300/h8sim/preinstall.am b/c/src/lib/libbsp/h8300/h8sim/preinstall.am index bdd3a3e..347e43d 100644 --- a/c/src/lib/libbsp/h8300/h8sim/preinstall.am +++ b/c/src/lib/libbsp/h8300/h8sim/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/i386/pc386/preinstall.am b/c/src/lib/libbsp/i386/pc386/preinstall.am index 5b592f4..182f564 100644 --- a/c/src/lib/libbsp/i386/pc386/preinstall.am +++ b/c/src/lib/libbsp/i386/pc386/preinstall.am @@ -8,16 +8,16 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am b/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am index 981d677..5191609 100644 --- a/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am +++ b/c/src/lib/libbsp/lm32/lm32_evr/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/lm32/milkymist/preinstall.am b/c/src/lib/libbsp/lm32/milkymist/preinstall.am index 0ee384d..e3d6f7e 100644 --- a/c/src/lib/libbsp/lm32/milkymist/preinstall.am +++ b/c/src/lib/libbsp/lm32/milkymist/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/m32c/m32cbsp/preinstall.am b/c/src/lib/libbsp/m32c/m32cbsp/preinstall.am index bdd3a3e..347e43d 100644 --- a/c/src/lib/libbsp/m32c/m32cbsp/preinstall.am +++ b/c/src/lib/libbsp/m32c/m32cbsp/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m32r/m32rsim/preinstall.am b/c/src/lib/libbsp/m32r/m32rsim/preinstall.am index 67ceb2b..5092254 100644 --- a/c/src/lib/libbsp/m32r/m32rsim/preinstall.am +++ b/c/src/lib/libbsp/m32r/m32rsim/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/av5282/preinstall.am b/c/src/lib/libbsp/m68k/av5282/preinstall.am index e3970ec..5092254 100644 --- a/c/src/lib/libbsp/m68k/av5282/preinstall.am +++ b/c/src/lib/libbsp/m68k/av5282/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/csb360/preinstall.am b/c/src/lib/libbsp/m68k/csb360/preinstall.am index 1c64e4f..647b809 100644 --- a/c/src/lib/libbsp/m68k/csb360/preinstall.am +++ b/c/src/lib/libbsp/m68k/csb360/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/gen68302/preinstall.am b/c/src/lib/libbsp/m68k/gen68302/preinstall.am index a63094d..9d1687e 100644 --- a/c/src/lib/libbsp/m68k/gen68302/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68302/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/gen68340/preinstall.am b/c/src/lib/libbsp/m68k/gen68340/preinstall.am index 298545c..b56f659 100644 --- a/c/src/lib/libbsp/m68k/gen68340/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68340/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/gen68360/preinstall.am b/c/src/lib/libbsp/m68k/gen68360/preinstall.am index 0a6c6d6..6f2e69f 100644 --- a/c/src/lib/libbsp/m68k/gen68360/preinstall.am +++ b/c/src/lib/libbsp/m68k/gen68360/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am b/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am index 331f0b5..505a3ad 100644 --- a/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am +++ b/c/src/lib/libbsp/m68k/genmcf548x/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/idp/preinstall.am b/c/src/lib/libbsp/m68k/idp/preinstall.am index 73bd6bd..0a548ff 100644 --- a/c/src/lib/libbsp/m68k/idp/preinstall.am +++ b/c/src/lib/libbsp/m68k/idp/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mcf5206elite/preinstall.am b/c/src/lib/libbsp/m68k/mcf5206elite/preinstall.am index 5454d9d..5ccfba8 100644 --- a/c/src/lib/libbsp/m68k/mcf5206elite/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf5206elite/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mcf52235/preinstall.am b/c/src/lib/libbsp/m68k/mcf52235/preinstall.am index 67ceb2b..5092254 100644 --- a/c/src/lib/libbsp/m68k/mcf52235/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf52235/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mcf5225x/preinstall.am b/c/src/lib/libbsp/m68k/mcf5225x/preinstall.am index 73323b5..5092254 100644 --- a/c/src/lib/libbsp/m68k/mcf5225x/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf5225x/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/mcf5329/preinstall.am b/c/src/lib/libbsp/m68k/mcf5329/preinstall.am index 24be79a..db2b32c 100644 --- a/c/src/lib/libbsp/m68k/mcf5329/preinstall.am +++ b/c/src/lib/libbsp/m68k/mcf5329/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mrm332/preinstall.am b/c/src/lib/libbsp/m68k/mrm332/preinstall.am index e8ddde2..aadebf7 100644 --- a/c/src/lib/libbsp/m68k/mrm332/preinstall.am +++ b/c/src/lib/libbsp/m68k/mrm332/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mvme136/preinstall.am b/c/src/lib/libbsp/m68k/mvme136/preinstall.am index 312b0f4..647b809 100644 --- a/c/src/lib/libbsp/m68k/mvme136/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme136/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mvme147/preinstall.am b/c/src/lib/libbsp/m68k/mvme147/preinstall.am index 312b0f4..647b809 100644 --- a/c/src/lib/libbsp/m68k/mvme147/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme147/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mvme147s/preinstall.am b/c/src/lib/libbsp/m68k/mvme147s/preinstall.am index 312b0f4..647b809 100644 --- a/c/src/lib/libbsp/m68k/mvme147s/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme147s/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/mvme162/preinstall.am b/c/src/lib/libbsp/m68k/mvme162/preinstall.am index 59198f3..309fa5c 100644 --- a/c/src/lib/libbsp/m68k/mvme162/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme162/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/m68k/mvme167/preinstall.am b/c/src/lib/libbsp/m68k/mvme167/preinstall.am index ea1d67d..4681b20 100644 --- a/c/src/lib/libbsp/m68k/mvme167/preinstall.am +++ b/c/src/lib/libbsp/m68k/mvme167/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/ods68302/preinstall.am b/c/src/lib/libbsp/m68k/ods68302/preinstall.am index 7f0436f..7640e08 100644 --- a/c/src/lib/libbsp/m68k/ods68302/preinstall.am +++ b/c/src/lib/libbsp/m68k/ods68302/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/m68k/sim68000/preinstall.am b/c/src/lib/libbsp/m68k/sim68000/preinstall.am index bdd3a3e..347e43d 100644 --- a/c/src/lib/libbsp/m68k/sim68000/preinstall.am +++ b/c/src/lib/libbsp/m68k/sim68000/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/m68k/uC5282/preinstall.am b/c/src/lib/libbsp/m68k/uC5282/preinstall.am index e3970ec..5092254 100644 --- a/c/src/lib/libbsp/m68k/uC5282/preinstall.am +++ b/c/src/lib/libbsp/m68k/uC5282/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/mips/genmongoosev/preinstall.am b/c/src/lib/libbsp/mips/genmongoosev/preinstall.am index a6505c0..f11c87a 100644 --- a/c/src/lib/libbsp/mips/genmongoosev/preinstall.am +++ b/c/src/lib/libbsp/mips/genmongoosev/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/mips/hurricane/preinstall.am b/c/src/lib/libbsp/mips/hurricane/preinstall.am index ae6cd49..7755bef 100644 --- a/c/src/lib/libbsp/mips/hurricane/preinstall.am +++ b/c/src/lib/libbsp/mips/hurricane/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/jmr3904/preinstall.am b/c/src/lib/libbsp/mips/jmr3904/preinstall.am index 244a228..d05c802 100644 --- a/c/src/lib/libbsp/mips/jmr3904/preinstall.am +++ b/c/src/lib/libbsp/mips/jmr3904/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/malta/preinstall.am b/c/src/lib/libbsp/mips/malta/preinstall.am index 091e11b..fc103c5 100644 --- a/c/src/lib/libbsp/mips/malta/preinstall.am +++ b/c/src/lib/libbsp/mips/malta/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/mips/rbtx4925/preinstall.am b/c/src/lib/libbsp/mips/rbtx4925/preinstall.am index b2d7806..de464aa 100644 --- a/c/src/lib/libbsp/mips/rbtx4925/preinstall.am +++ b/c/src/lib/libbsp/mips/rbtx4925/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/mips/rbtx4938/preinstall.am b/c/src/lib/libbsp/mips/rbtx4938/preinstall.am index 11efecd..de464aa 100644 --- a/c/src/lib/libbsp/mips/rbtx4938/preinstall.am +++ b/c/src/lib/libbsp/mips/rbtx4938/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am b/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am index 87f904e..eaeeefe 100644 --- a/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am +++ b/c/src/lib/libbsp/nios2/nios2_iss/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am b/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am index a6a238d..72d079a 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am +++ b/c/src/lib/libbsp/no_cpu/no_bsp/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/beatnik/preinstall.am b/c/src/lib/libbsp/powerpc/beatnik/preinstall.am index 10efa55..b3093ab 100644 --- a/c/src/lib/libbsp/powerpc/beatnik/preinstall.am +++ b/c/src/lib/libbsp/powerpc/beatnik/preinstall.am @@ -5,11 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) @@ -18,6 +13,11 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/gen5200/preinstall.am b/c/src/lib/libbsp/powerpc/gen5200/preinstall.am index 9f5d146..75a41ea 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/preinstall.am +++ b/c/src/lib/libbsp/powerpc/gen5200/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am index ab9dd65..8b06af2 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am +++ b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/haleakala/preinstall.am b/c/src/lib/libbsp/powerpc/haleakala/preinstall.am index 8f70554..0e65b26 100644 --- a/c/src/lib/libbsp/powerpc/haleakala/preinstall.am +++ b/c/src/lib/libbsp/powerpc/haleakala/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am b/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am index aa78beb..dd192b0 100644 --- a/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am b/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am index 6edf483..5865adf 100644 --- a/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am b/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am index a4017e8..796f977 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/psim/preinstall.am b/c/src/lib/libbsp/powerpc/psim/preinstall.am index ecf4a2b..9a133c4 100644 --- a/c/src/lib/libbsp/powerpc/psim/preinstall.am +++ b/c/src/lib/libbsp/powerpc/psim/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am b/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am index 4fa463d..e5e2ab2 100644 --- a/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am +++ b/c/src/lib/libbsp/powerpc/qemuppc/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/qoriq/preinstall.am b/c/src/lib/libbsp/powerpc/qoriq/preinstall.am index 8adee61..0843a7a 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/preinstall.am +++ b/c/src/lib/libbsp/powerpc/qoriq/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/score603e/preinstall.am b/c/src/lib/libbsp/powerpc/score603e/preinstall.am index 036f227..2756fa1 100644 --- a/c/src/lib/libbsp/powerpc/score603e/preinstall.am +++ b/c/src/lib/libbsp/powerpc/score603e/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/ss555/preinstall.am b/c/src/lib/libbsp/powerpc/ss555/preinstall.am index 6d7cb01..5eb0a1e 100644 --- a/c/src/lib/libbsp/powerpc/ss555/preinstall.am +++ b/c/src/lib/libbsp/powerpc/ss555/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am b/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am index d3bec9c..8a404f8 100644 --- a/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am +++ b/c/src/lib/libbsp/powerpc/t32mppc/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/preinstall.am b/c/src/lib/libbsp/powerpc/tqm8xx/preinstall.am index 7960684..cfe6ebd 100644 --- a/c/src/lib/libbsp/powerpc/tqm8xx/preinstall.am +++ b/c/src/lib/libbsp/powerpc/tqm8xx/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/virtex/preinstall.am b/c/src/lib/libbsp/powerpc/virtex/preinstall.am index e8b4481..ed98676 100644 --- a/c/src/lib/libbsp/powerpc/virtex/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/powerpc/virtex4/preinstall.am b/c/src/lib/libbsp/powerpc/virtex4/preinstall.am index f507474..f7a73c4 100644 --- a/c/src/lib/libbsp/powerpc/virtex4/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex4/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/powerpc/virtex5/preinstall.am b/c/src/lib/libbsp/powerpc/virtex5/preinstall.am index b0155fc..f7a73c4 100644 --- a/c/src/lib/libbsp/powerpc/virtex5/preinstall.am +++ b/c/src/lib/libbsp/powerpc/virtex5/preinstall.am @@ -5,6 +5,9 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = @@ -15,9 +18,6 @@ all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES += $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/c/src/lib/libbsp/sh/gensh4/preinstall.am b/c/src/lib/libbsp/sh/gensh4/preinstall.am index b7d09e5..8dd0653 100644 --- a/c/src/lib/libbsp/sh/gensh4/preinstall.am +++ b/c/src/lib/libbsp/sh/gensh4/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sh/shsim/preinstall.am b/c/src/lib/libbsp/sh/shsim/preinstall.am index 202e051..fa84c38 100644 --- a/c/src/lib/libbsp/sh/shsim/preinstall.am +++ b/c/src/lib/libbsp/sh/shsim/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/sparc/erc32/preinstall.am b/c/src/lib/libbsp/sparc/erc32/preinstall.am index 7bae1e1..00e9487 100644 --- a/c/src/lib/libbsp/sparc/erc32/preinstall.am +++ b/c/src/lib/libbsp/sparc/erc32/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/c/src/lib/libbsp/sparc/leon3/preinstall.am b/c/src/lib/libbsp/sparc/leon3/preinstall.am index 443400d..d7b28e4 100644 --- a/c/src/lib/libbsp/sparc/leon3/preinstall.am +++ b/c/src/lib/libbsp/sparc/leon3/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sparc64/niagara/preinstall.am b/c/src/lib/libbsp/sparc64/niagara/preinstall.am index 722ccdd..7725e49 100644 --- a/c/src/lib/libbsp/sparc64/niagara/preinstall.am +++ b/c/src/lib/libbsp/sparc64/niagara/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/sparc64/usiii/preinstall.am b/c/src/lib/libbsp/sparc64/usiii/preinstall.am index 2122b19..3546fc4 100644 --- a/c/src/lib/libbsp/sparc64/usiii/preinstall.am +++ b/c/src/lib/libbsp/sparc64/usiii/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libbsp/v850/gdbv850sim/preinstall.am b/c/src/lib/libbsp/v850/gdbv850sim/preinstall.am index 1fc9abe..38d42ac 100644 --- a/c/src/lib/libbsp/v850/gdbv850sim/preinstall.am +++ b/c/src/lib/libbsp/v850/gdbv850sim/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/lib/libcpu/arm/preinstall.am b/c/src/lib/libcpu/arm/preinstall.am index c756d19..751a085 100644 --- a/c/src/lib/libcpu/arm/preinstall.am +++ b/c/src/lib/libcpu/arm/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/bfin/preinstall.am b/c/src/lib/libcpu/bfin/preinstall.am index 36f6ca9..a8b2fa9 100644 --- a/c/src/lib/libcpu/bfin/preinstall.am +++ b/c/src/lib/libcpu/bfin/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/lm32/preinstall.am b/c/src/lib/libcpu/lm32/preinstall.am index 9667d9c..0516c2c 100644 --- a/c/src/lib/libcpu/lm32/preinstall.am +++ b/c/src/lib/libcpu/lm32/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - if shared $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu diff --git a/c/src/lib/libcpu/mips/preinstall.am b/c/src/lib/libcpu/mips/preinstall.am index 0f5a379..4a83d60 100644 --- a/c/src/lib/libcpu/mips/preinstall.am +++ b/c/src/lib/libcpu/mips/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) diff --git a/c/src/lib/libcpu/powerpc/preinstall.am b/c/src/lib/libcpu/powerpc/preinstall.am index 33d79d9..129855e 100644 --- a/c/src/lib/libcpu/powerpc/preinstall.am +++ b/c/src/lib/libcpu/powerpc/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/c/src/lib/libcpu/sparc64/preinstall.am b/c/src/lib/libcpu/sparc64/preinstall.am index ab9d46e..83b9153 100644 --- a/c/src/lib/libcpu/sparc64/preinstall.am +++ b/c/src/lib/libcpu/sparc64/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - if shared $(PROJECT_INCLUDE)/libcpu/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu diff --git a/c/src/libchip/preinstall.am b/c/src/libchip/preinstall.am index 452818f..2f95e6c 100644 --- a/c/src/libchip/preinstall.am +++ b/c/src/libchip/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/c/src/librtems++/preinstall.am b/c/src/librtems++/preinstall.am index 55d3cbf..2111689 100644 --- a/c/src/librtems++/preinstall.am +++ b/c/src/librtems++/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = diff --git a/cpukit/ftpd/preinstall.am b/cpukit/ftpd/preinstall.am index abeefb3..85ae87d 100644 --- a/cpukit/ftpd/preinstall.am +++ b/cpukit/ftpd/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = CLEANFILES = $(TMPINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) diff --git a/cpukit/libfs/src/nfsclient/preinstall.am b/cpukit/libfs/src/nfsclient/preinstall.am index c65f7f7..593fc03 100644 --- a/cpukit/libfs/src/nfsclient/preinstall.am +++ b/cpukit/libfs/src/nfsclient/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/posix/preinstall.am b/cpukit/posix/preinstall.am index beb6d58..6e3f2a2 100644 --- a/cpukit/posix/preinstall.am +++ b/cpukit/posix/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/pppd/preinstall.am b/cpukit/pppd/preinstall.am index 9479a04..19f4bc1 100644 --- a/cpukit/pppd/preinstall.am +++ b/cpukit/pppd/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/preinstall.am b/cpukit/preinstall.am index b2f88a9..70923f0 100644 --- a/cpukit/preinstall.am +++ b/cpukit/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/sapi/preinstall.am b/cpukit/sapi/preinstall.am index 57c5b97..40eafdd 100644 --- a/cpukit/sapi/preinstall.am +++ b/cpukit/sapi/preinstall.am @@ -8,15 +8,15 @@ endif PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES = $(PREINSTALL_FILES) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) diff --git a/cpukit/score/cpu/bfin/preinstall.am b/cpukit/score/cpu/bfin/preinstall.am index c5f501c..a16a047 100644 --- a/cpukit/score/cpu/bfin/preinstall.am +++ b/cpukit/score/cpu/bfin/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/h8300/preinstall.am b/cpukit/score/cpu/h8300/preinstall.am index 0f89b1c..f3c1681 100644 --- a/cpukit/score/cpu/h8300/preinstall.am +++ b/cpukit/score/cpu/h8300/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/i386/preinstall.am b/cpukit/score/cpu/i386/preinstall.am index 2d29558..060176b 100644 --- a/cpukit/score/cpu/i386/preinstall.am +++ b/cpukit/score/cpu/i386/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/m32r/preinstall.am b/cpukit/score/cpu/m32r/preinstall.am index 044514a..3d76b74 100644 --- a/cpukit/score/cpu/m32r/preinstall.am +++ b/cpukit/score/cpu/m32r/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE) @: > $(PROJECT_INCLUDE)/$(dirstamp) diff --git a/cpukit/score/cpu/mips/preinstall.am b/cpukit/score/cpu/mips/preinstall.am index bca004a..2385f8c 100644 --- a/cpukit/score/cpu/mips/preinstall.am +++ b/cpukit/score/cpu/mips/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/powerpc/preinstall.am b/cpukit/score/cpu/powerpc/preinstall.am index ccc4cbe..3293498 100644 --- a/cpukit/score/cpu/powerpc/preinstall.am +++ b/cpukit/score/cpu/powerpc/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/cpu/sparc64/preinstall.am b/cpukit/score/cpu/sparc64/preinstall.am index 3f53e73..00af891 100644 --- a/cpukit/score/cpu/sparc64/preinstall.am +++ b/cpukit/score/cpu/sparc64/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/score/preinstall.am b/cpukit/score/preinstall.am index a1e4583..891c21e 100644 --- a/cpukit/score/preinstall.am +++ b/cpukit/score/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - $(PROJECT_INCLUDE)/rtems/$(dirstamp): @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) diff --git a/cpukit/zlib/preinstall.am b/cpukit/zlib/preinstall.am index 27b3248..7eb8f7b 100644 --- a/cpukit/zlib/preinstall.am +++ b/cpukit/zlib/preinstall.am @@ -5,11 +5,6 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - PREINSTALL_DIRS = DISTCLEANFILES = $(PREINSTALL_DIRS) @@ -18,6 +13,11 @@ all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES += $(PREINSTALL_FILES) +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES += $(TMPINSTALL_FILES) + $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @: > $(PROJECT_LIB)/$(dirstamp) From chrisj at rtems.org Sat Aug 30 22:58:52 2014 From: chrisj at rtems.org (Chris Johns) Date: Sat, 30 Aug 2014 17:58:52 -0500 Subject: [rtems-source-builder commit] sb: Add support for the standard git protocols for the %source command. Message-ID: <20140830225852.B8B4E7006A2@git.rtems.org> Module: rtems-source-builder Branch: master Commit: d790668e390357c4c5fca82704806b9453151a42 Changeset: http://git.rtems.org/rtems-source-builder/commit/?id=d790668e390357c4c5fca82704806b9453151a42 Author: Chris Johns Date: Fri Aug 29 13:14:14 2014 +1000 sb: Add support for the standard git protocols for the %source command. The source selector 'git://' now supports a protocol option that lets you set the specific protocol git is to use to access a remote repository. --- doc/source-builder.txt | 6 ++++++ source-builder/sb/download.py | 26 ++++++++++++++++++++++++-- source-builder/sb/git.py | 5 ++++- 3 files changed, 34 insertions(+), 3 deletions(-) diff --git a/doc/source-builder.txt b/doc/source-builder.txt index 3f80503..1d9a474 100644 --- a/doc/source-builder.txt +++ b/doc/source-builder.txt @@ -1413,6 +1413,8 @@ the repository via the URL by appending options and arguments to the GIT path. The options are delimited by `?` and option arguments are delimited from the options with `=`. The options are: +`protocol`:: Use a specific protocol. The supported values are _ssh_, _git_, +_http_, _https_, _ftp_, _ftps_, _rsync_, and _none_. `branch`:: Checkout the specified branch. `pull`:: Perform a pull to update the repository. `fetch`:: Perform a fetch to get any remote updates. @@ -1428,6 +1430,10 @@ a hard reset. You can select specific branches and apply patches. The repository is cleaned up before each build to avoid various version control errors that can arise. +The protocol option lets you set a specific protocol. The 'git://' prefix used +by the RSB to select a git repository can be removed using _none_ or replaced +with one of the standard git protcols. + CVS ^^^ diff --git a/source-builder/sb/download.py b/source-builder/sb/download.py index fdc834a..dc1def6 100644 --- a/source-builder/sb/download.py +++ b/source-builder/sb/download.py @@ -201,7 +201,7 @@ def parse_url(url, pathkey, config, opts): source['url'] = url colon = url.find(':') if url[colon + 1:colon + 3] != '//': - raise error.general('malforned URL: %s' % (url)) + raise error.general('malforned URL (no protocol prefix): %s' % (url)) source['path'] = url[:colon + 3] + path.dirname(url[colon + 3:]) source['file'] = path.basename(url) source['name'], source['ext'] = path.splitext(source['file']) @@ -310,9 +310,27 @@ def _http_downloader(url, local, config, opts): return not failed def _git_downloader(url, local, config, opts): + repo = git.repo(local, opts, config.macros) rlp = os.path.relpath(path.host(local)) us = url.split('?') - repo = git.repo(local, opts, config.macros) + # + # Handle the various git protocols. + # + # remove 'git' from 'git://xxxx/xxxx?protocol=...' + # + url_base = us[0][len('git'):] + for a in us[1:]: + _as = a.split('=') + if _as[0] == 'protocol': + if len(_as) != 2: + raise error.general('invalid git protocol option: %s' % (_as)) + if _as[1] == 'none': + # remove the rest of the protocol header leaving nothing. + us[0] = url_base[len('://'):] + else: + if _as[1] not in ['ssh', 'git', 'http', 'https', 'ftp', 'ftps', 'rsync']: + raise error.general('unknown git protocol: %s' % (_as[1])) + us[0] = _as[1] + url_base if not repo.valid(): log.notice('git: clone: %s -> %s' % (us[0], rlp)) if not opts.dry_run(): @@ -350,6 +368,10 @@ def _git_downloader(url, local, config, opts): log.notice('git: reset: %s' % (us[0])) if not opts.dry_run(): repo.reset(arg) + elif _as[0] == 'protocol': + pass + else: + raise error.general('invalid git option: %s' % (_as)) return True def _cvs_downloader(url, local, config, opts): diff --git a/source-builder/sb/git.py b/source-builder/sb/git.py index 093c443..d115845 100644 --- a/source-builder/sb/git.py +++ b/source-builder/sb/git.py @@ -57,7 +57,10 @@ class repo: self.macros = opts.defaults else: self.macros = macros - self.git = self.macros.expand('%{__git}') + if self.macros is None: + self.git = 'git' + else: + self.git = self.macros.expand('%{__git}') def git_version(self): ec, output = self._run(['--version'], True) From sebh at rtems.org Mon Aug 11 06:11:34 2014 From: sebh at rtems.org (Sebastian Huber) Date: Mon, 11 Aug 2014 06:11:34 -0000 Subject: [rtems commit] bsp/altera-cyclone-v: Add a simple I2C driver. Message-ID: <20140811060245.A39DE70084A@git.rtems.org> Module: rtems Branch: master Commit: 3f9cd87d76740db4efdd28d3112a3cc8dce3dfc4 Changeset: http://git.rtems.org/rtems/commit/?id=3f9cd87d76740db4efdd28d3112a3cc8dce3dfc4 Author: Christian Mauderer Date: Mon Jul 14 16:33:52 2014 +0200 bsp/altera-cyclone-v: Add a simple I2C driver. --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 7 + c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac | 8 + .../libbsp/arm/altera-cyclone-v/hwlib/README.txt | 41 +- .../arm/altera-cyclone-v/hwlib/include/alt_i2c.h | 2024 +++++++ .../altera-cyclone-v/hwlib/include/socal/alt_i2c.h | 5940 ++++++++++++++++++++ .../arm/altera-cyclone-v/hwlib/src/hwmgr/alt_i2c.c | 2004 +++++++ .../arm/altera-cyclone-v/i2c/i2cdrv-config.c | 24 + .../arm/altera-cyclone-v/i2c/i2cdrv-config.h | 37 + c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv.c | 215 + .../libbsp/arm/altera-cyclone-v/include/i2cdrv.h | 76 + .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 20 +- 11 files changed, 10389 insertions(+), 7 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index e92e728..01b0272 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -56,6 +56,7 @@ include_bsp_HEADERS += hwlib/include/alt_clock_group.h include_bsp_HEADERS += hwlib/include/alt_clock_manager.h include_bsp_HEADERS += hwlib/include/alt_generalpurpose_io.h include_bsp_HEADERS += hwlib/include/alt_hwlibs_ver.h +include_bsp_HEADERS += hwlib/include/alt_i2c.h include_bsp_HEADERS += hwlib/include/alt_interrupt_common.h include_bsp_HEADERS += hwlib/include/alt_mpu_registers.h include_bsp_HEADERS += hwlib/include/alt_reset_manager.h @@ -125,6 +126,7 @@ CFLAGS += -Wno-missing-prototypes libbsp_a_SOURCES += hwlib/src/hwmgr/alt_address_space.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_clock_manager.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_generalpurpose_io.c +libbsp_a_SOURCES += hwlib/src/hwmgr/alt_i2c.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_reset_manager.c #The following Altera hwlib source files have been left out because so far #they are not required: @@ -193,6 +195,11 @@ libbsp_a_SOURCES += console/console-config.c libbsp_a_SOURCES += ../../shared/clockdrv_shell.h libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c +# I2C +libbsp_a_SOURCES += i2c/i2cdrv.c +libbsp_a_SOURCES += i2c/i2cdrv-config.c +include_bsp_HEADERS += include/i2cdrv.h + # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac b/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac index 561a192..bad9a2a 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac @@ -46,6 +46,14 @@ RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_UART_1],[configuration for UART 1]) RTEMS_BSPOPTS_SET([CYCLONE_V_UART_BAUD],[*],[115200U]) RTEMS_BSPOPTS_HELP([CYCLONE_V_UART_BAUD],[baud for UARTs]) +RTEMS_BSPOPTS_SET([CYCLONE_V_NO_I2C],[*],[1]) +RTEMS_BSPOPTS_HELP([CYCLONE_V_NO_I2C], +[Number of configured I2C buses. Note that each bus has to be configured in an +apropriate i2cdrv_config array.]) + +RTEMS_BSPOPTS_SET([CYCLONE_V_I2C0_SPEED],[*],[100000]) +RTEMS_BSPOPTS_HELP([CYCLONE_V_I2C0_SPEED],[speed for I2C0 in HZ]) + RTEMS_CHECK_SMP AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"]) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt index f19d387..154b343 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt @@ -10,4 +10,43 @@ The hwlib directory contains only those files from Alteras hwlib which are required by the BSP (the whole hwlib was considered too big). The directory structure within the hwlib directory is equivalent to Alteras hwlib directory structure. For easy maintenance only whole files have been -left out. \ No newline at end of file +left out. + +Altera provides the hwlib with their SoC Embedded Design Suite (EDS). + +HWLIB Version: +-------------- +The files have been taken from the following hwlib versions: + +|======================================== +| Version | File +| | +| 13.0SP1 | include/alt_address_space.h +| 13.0SP1 | include/alt_clock_group.h +| 13.0SP1 | include/alt_clock_manager.h +| 13.0SP1 | include/alt_generalpurpose_io.h +| 13.0SP1 | include/alt_hwlibs_ver.h +| 13.1 | include/alt_i2c.h +| 13.0SP1 | include/alt_interrupt_common.h +| 13.0SP1 | include/alt_mpu_registers.h +| 13.0SP1 | include/alt_reset_manager.h +| 13.0SP1 | include/hwlib.h +| 13.0SP1 | include/socal/alt_clkmgr.h +| 13.0SP1 | include/socal/alt_gpio.h +| 13.1 | include/socal/alt_i2c.h +| 13.0SP1 | include/socal/alt_l3.h +| 13.0SP1 | include/socal/alt_rstmgr.h +| 13.0SP1 | include/socal/alt_sdr.h +| 13.0SP1 | include/socal/alt_sysmgr.h +| 13.0SP1 | include/socal/alt_uart.h +| 13.0SP1 | include/socal/hps.h +| 13.0SP1 | include/socal/socal.h +| 13.0SP1 | src/hwmgr/alt_address_space.c +| 13.0SP1 | src/hwmgr/alt_clock_manager.c +| 13.0SP1 | src/hwmgr/alt_generalpurpose_io.c +| 13.1 | src/hwmgr/alt_i2c.c +| 13.0SP1 | src/hwmgr/alt_reset_manager.c +|======================================== + +hwlib 13.0SP1 is from SoC EDS 13.0.1.232 +hwlib 13.1 is from SoC EDS 14.0.0.200 diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_i2c.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_i2c.h new file mode 100644 index 0000000..7af55cf --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_i2c.h @@ -0,0 +1,2024 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/*! \file + * Altera - I2C Controller API + */ + +#ifndef __ALT_I2C_H__ +#define __ALT_I2C_H__ + +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "socal/alt_i2c.h" +#include "socal/alt_rstmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C I2C Controller API + * + * This module defines an API for configuring and managing the HPS I2C controllers. + * + * The I2C controller provides support for a communication link between integrated + * circuits on a board. It is a simple two-wire bus which consists of a serial + * data line (SDA) and a serial clock (SCL) for use in applications such as + * temperature sensors and voltage level translators to EEPROMs, A/D and D/A + * converters, CODECs, and many types of microprocessors. + * + * The Hard Processor System (HPS) provides four I2C controllers to enable system + * software to communicate serially with I2C buses. Each I2C controller can + * operate in master or slave mode, and support standard mode of up to 100 + * kilobits per second (Kbps) or fast mode of up to 400 Kbps. These I2C + * controllers are instances of the Synopsys DesignWare APB I2C (DW_apb_i2c) + * controller. + * + * NOTE: Each I2C controller must be programmed to operate in either master or + * slave mode only. Operating as a master and slave simultaneously is not + * supported. + * + * Features of the I2C Controller: + * * Support both 100 KBps and 400 KBps modes + * * One of the following I2C operations: master or slave + * * Support both 7-bit and 10-bit addressing modes + * * Mixed read and write combined-format transactions + * * Bulk transmit mode + * * DMA handshaking interface + * + * For a complete details on the configuration and operation of I2C controller, + * consult the following references: + * * Cyclone V Device Handbook Volume 3: Hard Processor System Technical + * Reference Manual, Chapter 20. I2C Controller (cv_54020-1.2) + * * Synopsys DesignWare DW_apb_i2c Databook DW_apb_i2c, Version 1.15a + * * The I2C-Bus Specification Version 2.1 + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the operational state of I2C by + * transfer operation. + */ +typedef enum ALT_I2C_TRANSFER_TYPE_e +{ + ALT_I2C_TRANSFER_NONE = 0, /*!< No transfer operation */ + ALT_I2C_TRANSFER_START = 1, /*!< Start detect */ + ALT_I2C_TRANSFER_COMPLETE = 2, /*!< All operations done */ + ALT_I2C_TRANSFER_READ = 3, /*!< Read operation is active */ + ALT_I2C_TRANSFER_WRITE = 4, /*!< Write operation is active */ +} +ALT_I2C_TRANSFER_TYPE_t; + + +/* + * A pointer or handle to the I2C controller device instance. The ALT_I2C_DEV_t is + * initialized by a call to alt_i2c_init() and subsequently used by the other I2C + * controller API functions as a reference to a specific device. + * + * \internal + * ALT_I2C_DEV_t may be a struct or reference to an opaque data + * structure. Whatever "internal" type is suited to the needs of the + * implementation. + * \endinternal + */ +typedef struct ALT_I2C_DEV_s +{ + void * location; /*!< HPS address of I2C instance. */ + alt_freq_t clock_freq; /*!< Input clock frequency. */ + uint32_t last_target; /*!< Last issued target address. */ +} +ALT_I2C_DEV_t; + +/*! + * This type enumerates the HPS I2C controller instances. + */ +typedef enum ALT_I2C_CTLR_e +{ + ALT_I2C_I2C0 = (int)ALT_I2C0_OFST, /*!< I2C0 instance. */ + ALT_I2C_I2C1 = (int)ALT_I2C1_OFST, /*!< I2C1 instance. */ + ALT_I2C_I2C2 = (int)ALT_I2C2_OFST, /*!< I2C2 instance. */ + ALT_I2C_I2C3 = (int)ALT_I2C3_OFST, /*!< I2C3 instance. */ +} ALT_I2C_CTLR_t; + +/*! + * This type enumerates the modes that the I2C controller may operate in. + * + * NOTE: Each I2C controller must be programmed to operate in either master or + * slave mode only. Operating as a master and slave simultaneously is not + * supported. + */ +typedef enum ALT_I2C_MODE_e +{ + ALT_I2C_MODE_SLAVE = ALT_I2C_CON_MST_MOD_E_DIS, /*!< Slave Mode */ + ALT_I2C_MODE_MASTER = ALT_I2C_CON_MST_MOD_E_EN /*!< Master Mode */ +} ALT_I2C_MODE_t; + +/*! + * This type enumerates the I2C controller operational speed modes. + * + * The I2C controller can operate in standard mode (with data rates 0 to 100 Kbps) + * or fast mode (with data rates less than or equal to 400 Kbps). Additionally, + * fast mode devices are downward compatible. For instance, fast mode devices can + * communicate with standard mode devices in 0 to 100 Kbps I2C bus + * system. However, standard mode devices are not upward compatible and should not + * be incorporated in a fast-mode I2C bus system as they cannot follow the higher + * transfer rate and therefore unpredictable states would occur. + * + * This setting is relevant only if one is operating the I2C in master mode. + */ +typedef enum ALT_I2C_SPEED_e +{ + ALT_I2C_SPEED_STANDARD = ALT_I2C_CON_SPEED_E_STANDARD, + /*!< Standard mode (0 to 100 Kbps) */ + ALT_I2C_SPEED_FAST = ALT_I2C_CON_SPEED_E_FAST + /*!< Fast mode (<= 400 Kbps) */ +} ALT_I2C_SPEED_t; + +/*! + * This type enumerates the two addressing modes formats supported by the I2C + * controller. + * + * The I2C controller does not support mixed address format - that is, a 7-bit + * address transaction followed by a 10-bit address transaction or vice versa - + * combined format transactions. + */ +typedef enum ALT_I2C_ADDR_MODE_e +{ + ALT_I2C_ADDR_MODE_7_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START7, + /*!< 7-Bit Address Format */ + ALT_I2C_ADDR_MODE_10_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 + /*!< 10-Bit Address Format */ +} ALT_I2C_ADDR_MODE_t; + +/*! + * This type enumerates interrupt status conditions for the I2C controller. + */ +typedef enum ALT_I2C_STATUS_e +{ + ALT_I2C_STATUS_RX_UNDER = 1UL << 0, + /*!< Set if the processor attempts to read the + * receive buffer when it is empty. If the I2C + * controller is disabled, this status keeps + * maintains its state until the master or slave + * state machines go into idle, then this + * interrupt is cleared. + */ + ALT_I2C_STATUS_RX_OVER = 1UL << 1, + /*!< Set if the receive buffer is completely + * filled to capacity and an additional byte is + * received from an external I2C device. The I2C + * controller acknowledges this, but any data + * bytes received after the FIFO is full are + * discarded. If the I2C controller is disabled, + * this status maintains its statue until the + * master or slave state machines go into idle, + * then this interrupt is cleared. + */ + ALT_I2C_STATUS_RX_FULL = 1UL << 2, + /*!< Set when the receive buffer reaches or goes + * above the RX_TL threshold. It is + * automatically cleared by hardware when buffer + * level goes below the threshold. If the I2C + * controller is disabled, the RX FIFO is + * flushed and held in reset; therefore the RX + * FIFO is not full. So this bit is cleared once + * the I2C controller is disabled, regardless of + * the activity that continues. + */ + ALT_I2C_STATUS_TX_OVER = 1UL << 3, + /*!< Set during transmit if the transmit buffer is + * filled to capacity and the processor attempts + * to issue another I2C command. When the I2C + * controller is disabled, this bit maintains + * its state until the master or slave state + * machines go into idle, then this interrupt is + * cleared. + */ + ALT_I2C_STATUS_TX_EMPTY = 1UL << 4, + /*!< This bit is set to 1 when the transmit buffer + * is at or below the configured threshold + * value. It is automatically cleared by + * hardware when the buffer level goes above the + * threshold. When the I2C controller is + * disabled, the TX FIFO is flushed and held in + * reset. The TX FIFO appears as if it has no + * data in it, so this bit is set to 1, provided + * there is activity in the master or slave + * state machines. When there is no longer + * activity, then this bit is set to 0. + * + */ + ALT_I2C_STATUS_RD_REQ = 1UL << 5, + /*!< This bit is set to 1 when I2C is acting as a + * slave and another I2C master is attempting to + * read data from the I2C. The I2C holds the bus + * in a wait state until this interrupt is + * serviced, which means that the slave has been + * addressed by a remote master that is asking + * for data to be transferred. The processor + * must respond to this interrupt and then write + * the requested data. This bit is set to 0 just + * after the processor by calling + * alt_i2c_int_clear() with + * ALT_I2C_STATUS_RD_REQ in the mask.. + */ + ALT_I2C_STATUS_TX_ABORT = 1UL << 6, + /*!< This bit indicates if I2C, as an I2C + * transmitter, is unable to complete the + * intended actions on the contents of the + * transmit FIFO. This situation can occur both + * as an I2C master or an I2C slave, and is + * referred to as a 'transmit abort'. When this + * bit is set to 1, the IC_TX_ABRT_SOURCE + * register indicates the reason why the + * transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX + * FIFO whenever this bit is set. The TX FIFO + * remains in this flushed state until the + * register alt_i2c_int_clear() with + * ALT_I2C_STATUS_TX_ABORT in the mask is + * called. Once this happens, the TX FIFO is + * then ready to accept more data bytes from the + * APB interface. + */ + ALT_I2C_STATUS_RX_DONE = 1UL << 7, + /*!< When the I2C is acting as a + * slave-transmitter, this bit is set to 1 if + * the master does not acknowledge a transmitted + * byte. This occurs on the last byte of the + * transmission, indicating that the + * transmission is done. + */ + ALT_I2C_STATUS_ACTIVITY = 1UL << 8, + /*!< This bit captures I2C activity and stays set + * until it is cleared. There are four ways to + * clear it: + * * Disabling the I2C controller + * * Calling alt_i2c_int_clear() with + * ALT_I2C_STATUS_ACTIVITY in the mask. + * * Calling alt_i2c_int_clear() with + * ALT_I2C_STATUS_ALL in the mask. + * * System reset + * + * Once this bit is set, it stays set unless one + * of the four methods is used to clear it. Even + * if the I2C module is idle, this bit remains + * set until cleared, indicating that there was + * activity on the bus. + */ + ALT_I2C_STATUS_STOP_DET = 1UL << 9, + /*!< Indicates whether a STOP condition has + * occurred on the I2C interface regardless of + * whether I2C is operating in slave or master + * mode. + */ + ALT_I2C_STATUS_START_DET = 1UL << 10, + /*!< Indicates whether a START or RESTART + * condition has occurred on the I2C interface + * regardless of whether I2C is operating in + * slave or master mode. + */ + ALT_I2C_STATUS_INT_CALL = 1UL << 11, + /*!< Set only when a General Call address is + * received and it is acknowledged. It stays set + * until it is cleared either by disabling I2C + * or when alt_i2c_int_clear() with + * ALT_I2C_STATUS_CALL in the mask is + * called. I2C stores the received data in the + * Rx buffer. + */ + ALT_I2C_STATUS_INT_ALL = 0xFFF, + /*!< All Combined and Individual Interrupts. This + * enumeration value can be used to clear, + * disable, and enable the combined interrupt + * and all individual interrupt status + * conditions. As a side effect, when passed to + * alt_i2c_int_clear(), clears the source causes + * (\ref ALT_I2C_TX_ABORT_CAUSE_t) of the + * ALT_I2C_STATUS_TX_ABORT condition. + */ +} ALT_I2C_STATUS_t; + +/*! + * This type enumerates the source causes of a ALT_I2C_STATUS_TX_ABORT condition. + * + * The active ALT_I2C_TX_ABORT_CAUSE_t source conditions are cleared when + * alt_i2c_int_clear() with is called ALT_I2C_STATUS_TX_ABORT in the mask or + * alt_i2c_int_clear() is called with ALT_I2C_STATUS_ALL in the mask. + * + * \internal + * Discuss special handling of abrt_sbyte_norstrt TX_ABRT source required in ???() function. + * \endinternal + */ +typedef enum ALT_I2C_TX_ABORT_CAUSE_e +{ + ALT_I2C_TX_ABORT_CAUSE_7B_ADDR_NOACK = 1UL << 0, + /*!< Master Abort 7 Bit Address - If set (1), + * Master is in 7-bit addressing mode and the + * address sent was not acknowledged by any + * slave. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_10ADDR1_NOACK = 1UL << 1, + /*!< Master Abort 10 Bit Address Byte 1 - If set + * (1), Master is in 10-bit address mode and the + * first 10-bit address byte was not + * acknowledged by any slave. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_10ADDR2_NOACK = 1UL << 2, + /*!< Master Abort 10 Bit Address Byte 2 - If set + * (1), Master is in 10-bit address mode and the + * second address byte of the 10-bit address was + * not acknowledged by any slave + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_TXDATA_NOACK = 1UL << 3, + /*!< Master Abort TX NOACK Bit - If set (1), + * Master has received an acknowledgement for + * the address, but when it sent data byte(s) + * following the address, it did not receive an + * acknowledge from the remote slave(s). This is + * a master-mode only bit. + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_GCALL_NOACK = 1UL << 4, + /*!< Master Abort GC Noack Bit - If set (1), I2C + * controller in master mode sent a General Call + * and no slave on the bus acknowledged the + * General Call. + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_GCALL_RD = 1UL << 5, + /*!< Master Abort GC Read Bit - If set (1), I2C + * controller in master mode sent a General Call + * but the user programmed the byte following + * the General Call to be a read from the bus + * (IC_DATA_CMD[9] is set to 1). + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_HS_ACKDET = 1UL << 6, + /*!< Master HS MC Ack - If set (1), Master is in + * High Speed mode and the High Speed Master + * code was acknowledged (wrong behavior). + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_SBYTE_ACKDET = 1UL << 7, + /*!< Master Abort START Byte - If set (1), Master + * has sent a START Byte and the START Byte was + * acknowledged (wrong behavior). + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_HS_NORSTRT = 1UL << 8, + /*!< Master HS Restart Disabled - If set (1), the + * restart is disabled (IC_RESTART_EN bit + * (IC_CON[5]) = 0) and the user is trying to + * use the master to transfer data in High Speed + * mode. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_SBYTE_NORSTRT = 1UL << 9, + /*!< Master Abort START No Restart - To clear, the + * source of the ABRT_SBYTE_NORSTRT must be + * fixed first; restart must be enabled + * (IC_CON[5]=1), the SPECIAL bit must be + * cleared (IC_TAR[11]), or the GC_OR_START bit + * must be cleared (IC_TAR[10]). Once the source + * of the ABRT_SBYTE_NORSTRT is fixed, then this + * bit can be cleared in the same manner as + * other bits in this register. If the source of + * the ABRT_SBYTE_NORSTRT is not fixed before + * attempting to clear this bit, bit 9 clears + * for one cycle and then gets re-asserted. + * + * If set (1), the restart is disabled + * (IC_RESTART_EN bit (IC_CON[5]) = 0) and the + * user is trying to send a START Byte. + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_10B_RD_NORSTRT = 1UL << 10, + /*!< Master Abort 10 Bit No Restart - If set (1), + * the restart is disabled (IC_RESTART_EN bit + * (IC_CON[5]) = 0) and the master sends a read + * command in 10-bit addressing mode. + * + * Role of I2C: Master Receiver. + */ + ALT_I2C_TX_ABORT_CAUSE_MST_DIS = 1UL << 11, + /*!< Master Operation with Master Disabled - If set + * (1), user tries to initiate a Master + * operation with the Master mode disabled. + * + * Role of I2C: Master or Slave-Receiver. + */ + ALT_I2C_TX_ABORT_CAUSE_ARB_LOST = 1UL << 12, + /*!< Master Abort Arbitration Lost - If set (1), + * master has lost arbitration, or if + * IC_TX_ABRT_SOURCE[14] is also set, then the + * slave transmitter has lost arbitration. Note: + * I2C can be both master and slave at the same + * time. + * + * Role of I2C: Master or Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLVFLUSH_TXFIFO = 1UL << 13, + /*!< Slave Abort Flush TXFIFO - If set (1), Slave + * has received a read command and some data + * exists in the TX FIFO so the slave issues a + * TX_ABRT interrupt to flush old data in TX + * FIFO. + * + * Role of I2C: Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLV_ARBLOST = 1UL << 14, + /*!< Slave Abort Arbitration Lost - If set (1), + * Slave lost the bus while transmitting data to + * a remote master. IC_TX_ABRT_SOURCE[12] is set + * at the same time. + * + * Note: Even though the slave never owns the + * bus, something could go wrong on the + * bus. This is a fail safe check. For instance, + * during a data transmission at the low-to-high + * transition of SCL, if what is on the data bus + * is not what is supposed to be transmitted, + * then DW_apb_i2c no longer own the bus. + * + * Role of I2C: Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLVRD_INTX = 1UL << 15 + /*!< Slave Abort Read TX - If set (1), + * when the processor side responds to a + * slave mode request for data to be transmitted + * to a remote master and user writes a 1 in CMD + * (bit 8) of IC_DATA_CMD register. + * + * Role of I2C: Slave-Transmitter. + */ +} ALT_I2C_TX_ABORT_CAUSE_t; + +/*! + * This type defines a structure for configuration of the SCL high and low counts + * to ensure proper I/O timing with the device interface. + * + * The SCL count values are only relevant if the I2C controller is enabled to as + * an I2C master. The SCL count values are ignored when the I2C controller is + * enabled as an I2C slave. + * + * See: Clock Frequency Configuration section of Chapter 20. I2C + * Controller in the Cyclone V Device Handbook Volume 3: Hard + * Processor System Technical Reference Manual for a complete discussion + * of calculation of the proper SCL clock high and low times. + */ +typedef struct ALT_I2C_MASTER_CONFIG_s +{ + ALT_I2C_ADDR_MODE_t addr_mode; + /*!< The address mode (7 or 10 bit) when + * acting as a master. + */ + bool restart_enable; + /*!< This setting determines whether RESTART + * conditions may be sent when acting as a + * master. When the \e restart_enable is + * false, the I2C controller master is + * incapable of performing the following + * functions: + * * Sending a START BYTE + * * Performing any high-speed mode + * operation + * * Performing direction changes in + * combined format mode + * * Performing a read operation with a + * 10-bit address + */ + ALT_I2C_SPEED_t speed_mode; + /*!< The speed mode of the I2C operation. + */ + uint16_t ss_scl_hcnt; + /*!< The SCL clock high-period count for + * standard speed. + */ + uint16_t ss_scl_lcnt; + /*!< The SCL clock low-period count for + * standard speed. + */ + uint16_t fs_scl_hcnt; + /*!< The SCL clock high-period count for fast + * speed. + */ + uint16_t fs_scl_lcnt; + /*!< The SCL clock low-period count for fast + * speed. + */ + uint8_t fs_spklen; + /*!< The duration, measured in ic_clk cycles, + * of the longest spike that is filtered out + * by the spike suppression logic when the + * component is operating in SS or FS modes. + */ +} ALT_I2C_MASTER_CONFIG_t; + +/*! + * This type defines a structure for configuration of the I2C controller when it + * is operating in slave mode. + */ +typedef struct ALT_I2C_SLAVE_CONFIG_s +{ + ALT_I2C_ADDR_MODE_t addr_mode; /*!< The address mode (7 or 10 bit) when + * acting as a slave. + */ + uint32_t addr; /*!< The slave address to which the I2C + * controller responds when acting as a + * slave. + */ + bool nack_enable; /*!< Enable generation of a NACK. when the + * I2C controller is a + * slave-receiver. If \b true, it can + * only generate a NACK after a data + * byte is received; hence, the data + * transfer is aborted and the data + * received is not pushed onto the + * receive buffer. When \b false, it + * generates NACK/ACK, depending on + * normal criteria. + * * \b true = generate NACK after data + * byte received + * * \b false = generate NACK/ACK normally + */ +} ALT_I2C_SLAVE_CONFIG_t; + +/*! + * Initialize the specified I2C controller instance for use and return a device + * handle referencing it. + * + * \param i2c + * The HPS I2C controller instance to initialize. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Initialization process: + * * Initialize internal driver state + * * Check clock setup (ALT_CLK_L4_SP) + * * Take I2C instance out of reset (System Manager) + * * Disable and clear all interrupts and status conditions + * * Setup and initialize any expected initial I2C controller state + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_init(const ALT_I2C_CTLR_t i2c, ALT_I2C_DEV_t *i2c_dev); + +/*! + * Reset the specified I2C controller instance for use. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Reset process: + * * Disable controller + * * Initialize internal driver state + * * Check clock setup (ALT_CLK_L4_SP) + * * Take I2C instance out of reset (System Manager) + * * Disable and clear all interrupts and status conditions + * * Setup and initialize any expected initial I2C controller state + * * Enable controller + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_reset(ALT_I2C_DEV_t * i2c_dev); + +/*! + * Uninitialize the I2C controller referenced by the \e i2c_dev handle. + * + * This function attempts to gracefully shutdown the I2C controller by waiting for + * any inpcomplete transactions to finish and then putting the I2C controller into + * reset. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_uninit(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Disables the I2C controller. + * + * When the I2C controller is disabled, the following occurs: + * * The TX FIFO and RX FIFO get flushed. + * * The I2C interrupt status conditions remain active until the I2C controller + * goes into IDLE state. + * + * If the controller is transmitting, it stops as well as deletes the contents of + * the transmit buffer after the current transfer is complete. If the module is + * receiving, the controller stops the current transfer at the end of the current + * byte and does not acknowledge the transfer. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE = 0 + * Follow the procedure in section 3.8.3 Disabling DW_apb_i2c of the DW Databook. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_disable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Enables the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_enable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE if the I2C controller is enabled. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_is_enabled(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Gets the current configuration of the I2C controller when operating in master + * mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_I2C_MASTER_CONFIG_t structure for holding + * the returned I2C master mode configuration parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t* cfg); + +/*! + * Sets the configuration of the I2C controller with operational parameters for + * operating in master mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * Pointer to a ALT_I2C_MASTER_CONFIG_t structure holding the desired + * I2C master mode operational parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg); + +/*! + * This is a utility function that returns the speed based on parameters of the + * I2C master configuration. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * A pointer to the master confugurations. + * + * \param speed_in_hz + * [out] Speed (Hz) of the I2C bus currently configured at. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_master_config_speed_get(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg, + uint32_t * speed_in_hz); + +/*! + * This is a utility function that computes parameters for the I2C master + * configuration that best matches the speed requested. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * A pointer to the master confugurations. + * + * \param speed_in_hz + * Speed (Hz) of the I2C bus to configure. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_speed_set(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t * cfg, + uint32_t speed_in_hz); + +/*! + * Definition included for backwards compatibility. + */ +#define alt_i2c_cfg_to_speed(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_get((i2c_dev), (cfg), (speed_in_hz)) + +/*! + * Definition included for backwards compatibility. + */ +#define alt_i2c_speed_to_cfg(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_set((i2c_dev), (cfg), (speed_in_hz)) + +/*! + * Gets the current configuration of the I2C controller when operating in slave + * mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_I2C_SLAVE_CONFIG_t structure for holding + * the returned I2C slave mode configuration parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_SLAVE_CONFIG_t* cfg); + +/*! + * Sets the configuration of the I2C controller with operational parameters for + * operating in slave mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * Pointer to a ALT_I2C_SLAVE_CONFIG_t structure holding the desired + * I2C slave mode operational parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_SLAVE_CONFIG_t* cfg); + +/*! \addtogroup ALT_I2C_SDA_HOLD SDA Hold Time Configuration + * + * The I2C protocol specification requires 300ns of hold time on the SDA signal in + * standard and fast speed modes. Board delays on the SCL and SDA signals can mean + * that the hold-time requirement is met at the I2C master, but not at the I2C + * slave (or vice-versa). Because each system may encounter differing board signal + * delays, the I2C controller provides the capability to adjust of the SDA + * hold-time. + * + * The functions in this section provide software configuration of SDA hold time + * for the I2C controller. + * + * @{ + */ + +/*! + * Gets the currently configured value for the SDA hold time in I2C controller + * clock (\ref ALT_CLK_L4_SP) clock ticks. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param hold_time + * [out] The configured SDA hold time in \ref ALT_CLK_L4_SP clock + * ticks. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_sda_hold_time_get(ALT_I2C_DEV_t *i2c_dev, + uint16_t *hold_time); + +/*! + * Sets the configured value for the SDA hold time in terms of I2C controller + * clock (\ref ALT_CLK_L4_SP) clock ticks. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param hold_time + * The SDA hold time in \ref ALT_CLK_L4_SP clock ticks. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_SDA_HOLD is 16 bits wide. hold_time must be in range 0..65535. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_sda_hold_time_set(ALT_I2C_DEV_t *i2c_dev, + const uint16_t hold_time); + +/*! @} */ + +/*! + * Gets the current operational mode of the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mode + * [out] The current operational mode enabled for the I2C + * controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_op_mode_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MODE_t* mode); + +/*! + * Sets the operational mode of the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mode + * The operational mode to enable for the I2C controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_op_mode_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MODE_t mode); + +/*! + * Returns ALT_E_TRUE if the I2C controller is busy. The I2C controller is busy if + * either the Slave Finite State Machine (FSM) is not in the IDLE state or the + * Master Finite State Machine (FSM) is not in the IDLE state. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.ACTIVITY == 1 + * NOTE: IC_STATUS[0] that is, the ACTIVITY bit is the OR of SLV_ACTIVITY and + * MST_ACTIVITY bits. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_is_busy(ALT_I2C_DEV_t *i2c_dev); + +/*! + * This function reads a single data byte from the receive FIFO. + * + * This function is used to perform low level access to the data bytes + * received by the I2C controller and buffered in the receive FIFO. It + * may be used by master-receivers or slave receivers. + * + * This function does not check for valid data in the receive FIFO + * beforehand and may cause an underflow if improperly used. It is + * meant to be called from a context where preconditions have been + * previously asserted such as in the implementation of the + * alt_i2c_slave_receive() or alt_i2c_master_receive() function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param val + * [out] The single data byte read from the receive FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_read(ALT_I2C_DEV_t *i2c_dev, uint8_t *val); + +/*! + * This function writes a single data byte to the transmit FIFO. + * + * This function is used to perform low level writes of data to the + * transmit FIFO for transmission by the I2C controller. It may be + * used by slave receivers. + * + * This function does not check whether the transmit FIFO is full or + * not beforehand and may cause an overflow if improperly used. It is + * meant to be called from a context where preconditions have been + * previously asserted such as in the implementation of the + * alt_i2c_slave_transmit() function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param val + * The data byte to write to the transmission FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_write(ALT_I2C_DEV_t *i2c_dev, const uint8_t val); + +/*! + * This function acts in the role of a slave-receiver by receiving a single data + * byte from the I2C bus in response to a write command from the master. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is data in the RX FIFO to + * accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * [out] A pointer to a buffer to contain the received data byte. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_receive(ALT_I2C_DEV_t *i2c_dev, + uint8_t *data); + +/*! + * This function acts in the role of a slave-transmitter by transmitting a single + * data byte to the I2C bus in response to a read request from the master. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO to accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * The data byte to transmit. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_transmit(ALT_I2C_DEV_t *i2c_dev, + const uint8_t data); + +/*! + * This function acts in the role of a slave-transmitter by transmitting data in + * bulk to the I2C bus in response to a series of read requests from a master. + * + * In the standard I2C protocol, all transactions are single byte transactions and + * the slave responds to a remote master read request by writing one byte into the + * slave's TX FIFO. When a slave (slave-transmitter) is issued with a read request + * from the remote master (master-receiver), at a minimum there should be at least + * one entry placed into the slave-transmitter's TX FIFO. The I2C controller is + * capable of handling more data in the TX FIFO so that subsequent read requests + * can receive that data without raising an interrupt or software having to poll + * to request more data. This eliminates overhead latencies from being incurred by + * servicing the interrupt or polling for data requests each time had there been a + * restriction of having only one entry placed in the TX FIFO. + * + * If the remote master acknowledges the data sent by the slave-transmitter and + * there is no data in the slave's TX FIFO, the I2C controller raises the read + * request interrupt and waits for data to be written into the TX FIFO before it + * can be sent to the remote master. + * + * If the programmer knows in advance that the master is requesting a packet of \e + * n bytes, then when another master request for data is received, the TX FIFO + * could be written with \e n number bytes and the master receives it as a + * continuous stream of data. For example, the slave continues to send data to the + * master as long as the master is acknowledging the data sent and there is data + * available in the TX FIFO. There is no need to hold the SCL line low or to issue + * READ request again. + * + * If the remote master is to receive \e n bytes from the slave but the programmer + * wrote a number of bytes larger than \e n to the TX FIFO, then when the slave + * finishes sending the requested \e n bytes, it clears the TX FIFO and ignores + * any excess bytes. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO to accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * A pointer to the data buffer to transmit. + * + * \param size + * The size of the data buffer in bytes to place in the TX FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * See: Section Slave-Transfer Operation for Bulk Transfers of the DW + * Databook for details of implementation and error conditions that may occur. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_bulk_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size); + +/*! + * This function returns the current target address. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param target_addr + * [out] The 7 or 10 bit slave target address. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_i2c_master_target_get(ALT_I2C_DEV_t * i2c_dev, uint32_t * target_addr); + +/*! + * This function updates the target slave address for any upcoming I2C bus IO. + * + * This API is not suitlabe for being called in an interrupt context as it + * will wait for the TX FIFO to flush before applying the changes. If the TX + * FIFO is known to be empty and the controller idle, then it can be safely + * called. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param target_addr + * The 7 or 10 bit slave target address. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_i2c_master_target_set(ALT_I2C_DEV_t * i2c_dev, uint32_t target_addr); + +/*! + * This function acts in the role of a master-transmitter by issuing a write + * command and transmitting data to the I2C bus. + * + * This API is not suitable for being called in an interrupt context as it may + * wait for certain controller states before completing. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * A pointer to a data buffer to transmit + * + * \param size + * The size of the data buffer in bytes to place in the TX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function acts in the role of a master-receiver by receiving one or more + * data bytes transmitted from a slave in response to read requests issued from + * this master. + * + * This function causes the master to issue the required number of read requests + * to the slave and read the received data bytes from the Rx FIFO. + * + * The \e issue_restart and \e issue_stop parameters apply to the final read + * request transaction in the \e num_data_entries sequence required to fulfill the + * aggregate receive request. + * + * This API is not suitable for being called in an interrupt context as it may + * wait for certain controller states before completing. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * [out] The data buffer to receive the requested \e size bytes. + * + * \param size + * The size of the data buffer to read from the RX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_receive(ALT_I2C_DEV_t *i2c_dev, + void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function causes the I2C controller master to issue a READ request on the + * bus. This function is typically used during master-receiver transfers. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Write IC_DATA_CMD.CMD = 1 (read request). IC_DATA_CMD.DAT is + * written with "don't care" values as these bits are ignored by the + * I2C controller . + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_issue_read(ALT_I2C_DEV_t *i2c_dev, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function causes the I2C controller master to issue a send byte on the + * bus. This function is typically used during master-transmitter/slave-transmitter + * transfers. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param value + * The data item to be transmitted. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Write IC_DATA_CMD.CMD = 0 (write request). + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_issue_write(ALT_I2C_DEV_t *i2c_dev, + const uint8_t value, + const bool issue_restart, + const bool issue_stop); + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_GEN_CALL General Call + * + * The functions in this group support General Call addresses. + * + * The general call address is for addressing every device connected to the I2C + * bus at the same time. However, if a device does not need any of the data + * supplied within the general call structure, it can ignore this address by not + * issuing an acknowledgment. If a device does require data from a general call + * address, it acknowledges this address and behaves as a slave-receiver. The + * master does not actually know how many devices acknowledged if one or more + * devices respond. The second and following bytes are acknowledged by every + * slave-receiver capable of handling this data. A slave who cannot process one of + * these bytes must ignore it by not-acknowledging. If one or more slaves + * acknowledge, the not-acknowledge will not be seen by the master. + * + * The functions in this group do not provide any general call functional command + * interpretation or implementation (e.g. software reset). + * + * @{ + */ + +/*! + * This function acts in the role of a master-transmitter by issuing a general + * call command to all devices connected to the I2C bus. + * + * The \e issue_restart and \e issue_stop parameters apply to the final write + * transaction in the \e num_data_entries byte transmission sequence. + * + * The I2C controller must be in master mode before calling this function. + * + * The target slave address will be modified by this function. Call + * alt_i2c_master_target_set() to reset the slave target address for + * subsequent IO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * An array of data byte(s) to transmit. + * + * \param num_data_entries + * The number of entries (bytes) in \e data to place in the TX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_general_call(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * Disables the I2C controller from responding to a General Call address. The + * controller will respond with a NACK and no General Call status conditions or + * interrupts are generated. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_disable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Enables the I2C controller to respond with an ACK when it receives a General + * Call address. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_enable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE if the I2C controller is enabled to respond to General Call + * addresses. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_is_enabled(ALT_I2C_DEV_t *i2c_dev); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_INT Interrupt and Status Conditions + * + * The functions in this group provide management for the I2C controller status + * conditions and interrupts. + * + * Each I2C controller has a single combined interrupt output (\b + * ALT_INT_INTERRUPT_I2Cn_IRQ). The following events can generate an + * interrupt: + * * General Call Address Received + * * Start or Restart Condition Occurred + * * Stop Condition Occurred + * * I2C Controller Activity + * * Receive Done + * * Transmit Abort + * * Read Request + * * Transmit Buffer Empty + * * Transmit Overflow + * * Receive Buffer Full + * * Receive Overflow + * * Receive Underflow + * + * These interrupt status conditions may be monitored either by polling their + * status or by configuring interrupt handlers using the HWLIB Interrupt + * Controller API. + * + * Functions to get the current status, enable or disable (i.e. mass or unmask), + * and clear interrupt status conditions for the I2C controller are defined in + * this section. + * + * @{ + */ + +/*! + * Returns the current I2C controller interrupt status conditions. + * + * This function returns the current value of the I2C controller interrupt status + * register value which reflects the current I2C controller status conditions that + * are not disabled (i.e. masked). + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_INTR_STAT + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status); + +/*! + * Returns the I2C controller raw interrupt status conditions irrespective of + * the interrupt status condition enablement state. + * + * This function returns the current value of the I2C controller raw interrupt + * status register value which reflects the current I2C controller status + * conditions regardless of whether they are disabled (i.e. masked) or not. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_INTR_STAT + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_raw_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status); + +/*! + * Clears the specified I2C controller interrupt status conditions identified + * in the mask. + * + * This function clears one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the QSPI interrupt status conditions to clear. \e mask + * is a mask of logically OR'ed \ref ALT_I2C_STATUS_t values that + * designate the status conditions to clear. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_clear(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Disable the specified I2C controller interrupt status conditions identified in + * the mask. + * + * This function disables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of enabling it as a contributor to the \b + * ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. The function + * alt_i2c_int_enable() is used to enable status source conditions. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_I2C_STATUS_t values that designate the status conditions to + * disable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_disable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Enable the specified I2C controller interrupt status conditions identified in + * the mask. + * + * This function enables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of disabling it as a contributor to the \b + * ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. The function + * alt_i2c_int_disable() is used to disable status source conditions. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_I2C_STATUS_t values that designate the status conditions to + * enable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_enable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Gets the cause of I2C transmission abort. A I2C transmission abort indicates + * that the I2C transmitter is unable to complete the intended actions on the + * contents of the transmit FIFO. This situation can occur both as an I2C master + * or an I2C slave, and is referred to as a "transmit abort". + * + * The returned value of this function is the value of the IC_TX_ABRT_SOURCE + * register which indicates the cause why the transmit abort occurred. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cause + * [out] A pointer to a bit mask of the \ref ALT_I2C_TX_ABORT_CAUSE_t + * causes of the transmission abort. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_ABRT_SOURCE + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_abort_cause_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_TX_ABORT_CAUSE_t *cause); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_RX_FIFO RX FIFO Management + * + * The receive FIFO has a configurable threshold value that controls the level of + * entries (or above) that sets the RX_FULL status condition and triggers an + * interrupt. The valid range is 0 - (ALT_I2C_RX_FIFO_NUM_ENTRIES-1), with the + * additional restriction that I2C controller does not allow this value to be set + * to a value larger than the depth of the buffer. If an attempt is made to do + * that, the actual value set will be the maximum depth of the buffer. A value of + * 0 sets the threshold for 1 entry, and a value of (ALT_I2C_RX_FIFO_NUM_ENTRIES-1) + * sets the threshold for ALT_I2C_RX_FIFO_NUM_ENTRIES entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the I2C controller receive FIFO. + */ +#define ALT_I2C_RX_FIFO_NUM_ENTRIES 64 + +/*! + * Returns ALT_E_TRUE when the receive FIFO is empty. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.RFNE == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE when the receive FIFO is completely full. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.RFF == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns the number of valid entries in the receive FIFO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param num_entries + * [out] The number of entries in the receive FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RXFLR.RXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries); + +/*! + * Gets the current receive FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold); + +/*! + * Sets the current receive FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_TX_FIFO TX FIFO Management + * + * The transmit FIFO has a configurable threshold value that controls the level of + * entries (or below) that sets the TX_EMPTY status condition and triggers an + * interrupt. The valid range is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES-1), with the + * additional restriction that I2C controller does not allow this value to be set + * to a value larger than the depth of the buffer. If an attempt is made to do + * that, the actual value set will be the maximum depth of the buffer. A value of + * 0 sets the threshold for 0 entries, and a value of (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) + * sets the threshold for (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the I2C controller transmit FIFO. + */ +#define ALT_I2C_TX_FIFO_NUM_ENTRIES 64 + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is empty. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.TFE == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is completely full. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.TFNF == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns the number of valid entries in the transmit FIFO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param num_entries + * [out] The number of entries in the transmit FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TXFLR.TXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries); + +/*! + * Gets the current transmit FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold); + +/*! + * Sets the current transmit FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_DMA DMA Interface + * + * The DMA interface has a configurable threshold value that controls the + * level of entries that triggers the burst handshaking request used for DMA + * integration. + * + * For the TX threshold, if the number of entries in the TX FIFO is at or + * below the set threshold, a DMA handshaking request will be made. The valid + * range for the TX threshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). + * + * For the RX threshold, if the number of entries in the RX FIFO is above the + * set threshold, a DMA handshaking request will be made. The valid range for + * the RX treshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). + * + * Having a higher threshold can improve the AXI bus utilization at the + * expense of the likelyhoold of overflow / underflow conditions. + * @{ + */ + +/*! + * Gets the current RX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); + +/*! + * Sets the current RX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); + +/*! + * Gets the current TX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); + +/*! + * Sets the current TX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_I2C_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_i2c.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_i2c.h new file mode 100644 index 0000000..b50543a --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_i2c.h @@ -0,0 +1,5940 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_I2C */ + +#ifndef __ALTERA_ALT_I2C_H__ +#define __ALTERA_ALT_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : I2C Module - ALT_I2C + * I2C Module + * + * Registers in the I2C module + * + */ +/* + * Register : Control Register - ic_con + * + * This register can be written only when the I2C is disabled, which corresponds to + * the Bit [0] of the Enable Register being set to 0. Writes at other times have no + * effect. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | Master Enable + * [2:1] | RW | 0x2 | Master Speed Control + * [3] | RW | 0x1 | Slave Address Size + * [4] | RW | 0x1 | Master Address Size + * [5] | RW | 0x1 | Restart Enable + * [6] | RW | 0x1 | Slave Disable + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Enable - master_mode + * + * This bit controls whether the i2c master is enabled. + * + * NOTE: Software should ensure that if this bit is written with '1', then bit 6 + * should also be written with a '1'. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------- + * ALT_I2C_CON_MST_MOD_E_DIS | 0x0 | master disabled + * ALT_I2C_CON_MST_MOD_E_EN | 0x1 | master enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_MST_MOD + * + * master disabled + */ +#define ALT_I2C_CON_MST_MOD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_MST_MOD + * + * master enabled + */ +#define ALT_I2C_CON_MST_MOD_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_MSB 0 +/* The width in bits of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_MST_MOD register field value. */ +#define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CON_MST_MOD register field value. */ +#define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_RESET 0x1 +/* Extracts the ALT_I2C_CON_MST_MOD field value from a register. */ +#define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CON_MST_MOD register field value suitable for setting the register. */ +#define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Master Speed Control - speed + * + * These bits control at which speed the I2C operates, its setting is relevant only + * if one is operating the I2C in master mode. Hardware protects against illegal + * values being programmed by software. This field should be programmed only with + * standard or fast speed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:--------------------------- + * ALT_I2C_CON_SPEED_E_STANDARD | 0x1 | standard mode (100 kbit/s) + * ALT_I2C_CON_SPEED_E_FAST | 0x2 | fast mode (400 kbit/s) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_SPEED + * + * standard mode (100 kbit/s) + */ +#define ALT_I2C_CON_SPEED_E_STANDARD 0x1 +/* + * Enumerated value for register field ALT_I2C_CON_SPEED + * + * fast mode (400 kbit/s) + */ +#define ALT_I2C_CON_SPEED_E_FAST 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_MSB 2 +/* The width in bits of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_WIDTH 2 +/* The mask used to set the ALT_I2C_CON_SPEED register field value. */ +#define ALT_I2C_CON_SPEED_SET_MSK 0x00000006 +/* The mask used to clear the ALT_I2C_CON_SPEED register field value. */ +#define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_RESET 0x2 +/* Extracts the ALT_I2C_CON_SPEED field value from a register. */ +#define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_I2C_CON_SPEED register field value suitable for setting the register. */ +#define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006) + +/* + * Field : Slave Address Size - ic_10bitaddr_slave + * + * When acting as a slave, this bit controls whether the I2C responds to 7- or + * 10-bit addresses. In 7-bit addressing, only the lower 7 bits of the Slave + * Address Register are compared. The I2C responds will only respond to 10-bit + * addressing transfers that match the full 10 bits of the Slave Address register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT | 0x0 | 7-bit addressing + * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT | 0x1 | 10-bit addressing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV + * + * 7-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV + * + * 10-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3 +/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_10BITADDR_SLV field value from a register. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_CON_IC_10BITADDR_SLV register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Master Address Size - ic_10bitaddr_master + * + * This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing + * mode when acting as a master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT | 0x0 | 7-bit addressing + * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT | 0x1 | 10-bit addressing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST + * + * 7-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST + * + * 10-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4 +/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_10BITADDR_MST field value from a register. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_CON_IC_10BITADDR_MST register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Restart Enable - ic_restart_en + * + * Determines whether RESTART conditions may be sent when acting as a master. Some + * older slaves do not support handling RESTART conditions; however, RESTART + * conditions are used in several I2C operations. When RESTART is disabled, the + * master is prohibited from performing the following functions + * + * * Changing direction within a transfer (split), + * + * * Sending a START BYTE, + * + * * High-speed mode operation, + * + * * Combined format transfers in 7-bit addressing modes, + * + * * Read operation with a 10-bit address, + * + * * Sending multiple bytes per transfer, + * + * By replacing RESTART condition followed by a STOP and a subsequent START + * condition, split operations are broken down into multiple I2C transfers. If the + * above operations are performed, it will result in setting bit [6](tx_abort) of + * the Raw Interrupt Status Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------- + * ALT_I2C_CON_IC_RESTART_EN_E_DIS | 0x0 | restart master disable + * ALT_I2C_CON_IC_RESTART_EN_E_EN | 0x1 | restart master enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN + * + * restart master disable + */ +#define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN + * + * restart master enable + */ +#define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_MSB 5 +/* The width in bits of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_RESTART_EN register field value. */ +#define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_CON_IC_RESTART_EN register field value. */ +#define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_RESTART_EN field value from a register. */ +#define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_CON_IC_RESTART_EN register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Slave Disable - ic_slave_disable + * + * This bit controls whether I2C has its slave disabled. The slave will be + * disabled, after reset. + * + * NOTE: Software should ensure that if this bit is written with 0, then bit [0] of + * this register should also be written with a 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------- + * ALT_I2C_CON_IC_SLV_DIS_E_DIS | 0x1 | slave disable + * ALT_I2C_CON_IC_SLV_DIS_E_EN | 0x0 | slave enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS + * + * slave disable + */ +#define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1 +/* + * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS + * + * slave enable + */ +#define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_MSB 6 +/* The width in bits of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_SLV_DIS register field value. */ +#define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_CON_IC_SLV_DIS register field value. */ +#define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_SLV_DIS field value from a register. */ +#define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_CON_IC_SLV_DIS register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CON. + */ +struct ALT_I2C_CON_s +{ + uint32_t master_mode : 1; /* Master Enable */ + uint32_t speed : 2; /* Master Speed Control */ + uint32_t ic_10bitaddr_slave : 1; /* Slave Address Size */ + uint32_t ic_10bitaddr_master : 1; /* Master Address Size */ + uint32_t ic_restart_en : 1; /* Restart Enable */ + uint32_t ic_slave_disable : 1; /* Slave Disable */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CON. */ +typedef volatile struct ALT_I2C_CON_s ALT_I2C_CON_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CON register from the beginning of the component. */ +#define ALT_I2C_CON_OFST 0x0 +/* The address of the ALT_I2C_CON register. */ +#define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST)) + +/* + * Register : Target Address Register - ic_tar + * + * This register can be written to only when the ic_enable register is set to 0. + * This register is 13 bits wide. All bits can be dynamically updated as long as + * any set of the following conditions are true, + * + * (Enable Register bit 0 is set to 0) or (Enable Register bit 0 is set to 1 AND + * (I2C is NOT engaged in any Master [tx, rx] operation [ic_status register + * mst_activity bit 5 is set to 0]) AND (I2C is enabled to operate in Master + * mode[ic_con bit[0] is set to one]) AND (there are NO entries in the TX FIFO + * Register [IC_STATUS bit [2] is set to 1]) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [9:0] | RW | 0x55 | Master Target Address + * [10] | RW | 0x0 | General Call OR Start + * [11] | RW | 0x0 | Special + * [12] | RW | 0x1 | Master Addressing Bit Control + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Target Address - ic_tar + * + * This is the target address for any master transaction. When transmitting a + * General Call, these bits are ignored. To generate a START BYTE, the CPU needs to + * write only once into these bits. If the ic_tar and ic_sar are the same, loopback + * exists but the FIFOs are shared between master and slave, so full loopback is + * not feasible. Only one direction loopback mode is supported (simplex), not + * duplex. A master cannot transmit to itself; it can transmit to only a slave. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_MSB 9 +/* The width in bits of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_WIDTH 10 +/* The mask used to set the ALT_I2C_TAR_IC_TAR register field value. */ +#define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff +/* The mask used to clear the ALT_I2C_TAR_IC_TAR register field value. */ +#define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_RESET 0x55 +/* Extracts the ALT_I2C_TAR_IC_TAR field value from a register. */ +#define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_I2C_TAR_IC_TAR register field value suitable for setting the register. */ +#define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff) + +/* + * Field : General Call OR Start - gc_or_start + * + * If bit 11 (SPECIAL) of this Register is set to 1, then this bit indicates + * whether a General Call or START byte command is to be performed by the I2C or + * General Call Address after issuing a General Call, only writes may be performed. + * Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the Raw + * Interrupt_Status register. The I2C remains in General Call mode until the + * special bit value (bit 11) is cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------- + * ALT_I2C_TAR_GC_OR_START_E_GENCALL | 0x0 | General Call + * ALT_I2C_TAR_GC_OR_START_E_STARTBYTE | 0x1 | START Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_GC_OR_START + * + * General Call + */ +#define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_GC_OR_START + * + * START Byte + */ +#define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_MSB 10 +/* The width in bits of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_GC_OR_START register field value. */ +#define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_TAR_GC_OR_START register field value. */ +#define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_RESET 0x0 +/* Extracts the ALT_I2C_TAR_GC_OR_START field value from a register. */ +#define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_TAR_GC_OR_START register field value suitable for setting the register. */ +#define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Special - special + * + * This bit indicates whether software performs a General Call or START BYTE + * command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:-------------------------------------------- + * ALT_I2C_TAR_SPECIAL_E_GENCALL | 0x0 | Ignore bit 10 gc_or_start and use ic_tar + * : | | normally + * ALT_I2C_TAR_SPECIAL_E_STARTBYTE | 0x1 | Perform special I2C command as specified in + * : | | gc_or_start + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_SPECIAL + * + * Ignore bit 10 gc_or_start and use ic_tar normally + */ +#define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_SPECIAL + * + * Perform special I2C command as specified in gc_or_start + */ +#define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_MSB 11 +/* The width in bits of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_SPECIAL register field value. */ +#define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_TAR_SPECIAL register field value. */ +#define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_RESET 0x0 +/* Extracts the ALT_I2C_TAR_SPECIAL field value from a register. */ +#define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_TAR_SPECIAL register field value suitable for setting the register. */ +#define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Master Addressing Bit Control - ic_10bitaddr_master + * + * This bit controls whether the i2c starts its transfers in 7-bit or 10-bit + * addressing mode when acting as a master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------- + * ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 | 0x0 | Master Address, 7bit + * ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 | 0x1 | Master Address, 10bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST + * + * Master Address, 7bit + */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST + * + * Master Address, 10bit + */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12 +/* The width in bits of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff +/* The reset value of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1 +/* Extracts the ALT_I2C_TAR_IC_10BITADDR_MST field value from a register. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_I2C_TAR_IC_10BITADDR_MST register field value suitable for setting the register. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TAR. + */ +struct ALT_I2C_TAR_s +{ + uint32_t ic_tar : 10; /* Master Target Address */ + uint32_t gc_or_start : 1; /* General Call OR Start */ + uint32_t special : 1; /* Special */ + uint32_t ic_10bitaddr_master : 1; /* Master Addressing Bit Control */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TAR. */ +typedef volatile struct ALT_I2C_TAR_s ALT_I2C_TAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TAR register from the beginning of the component. */ +#define ALT_I2C_TAR_OFST 0x4 +/* The address of the ALT_I2C_TAR register. */ +#define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST)) + +/* + * Register : Slave Address Register - ic_sar + * + * Holds Address of Slave + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [9:0] | RW | 0x55 | Slave Address + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Slave Address - ic_sar + * + * The Slave Address register holds the slave address when the I2C is operating as + * a slave. For 7-bit addressing, only Field Bits [6:0] of the Slave Address + * Register are used. This register can be written only when the I2C interface is + * disabled, which corresponds to field bit 0 of the Enable Register being set to + * 0. Writes at other times have no effect. + * + * Note, the default values cannot be any of the reserved address locations: that + * is, + * + * 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not + * guaranteed if you program the Slave Address Register or Target Address Register + * to a reserved value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_MSB 9 +/* The width in bits of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_WIDTH 10 +/* The mask used to set the ALT_I2C_SAR_IC_SAR register field value. */ +#define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff +/* The mask used to clear the ALT_I2C_SAR_IC_SAR register field value. */ +#define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_RESET 0x55 +/* Extracts the ALT_I2C_SAR_IC_SAR field value from a register. */ +#define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_I2C_SAR_IC_SAR register field value suitable for setting the register. */ +#define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SAR. + */ +struct ALT_I2C_SAR_s +{ + uint32_t ic_sar : 10; /* Slave Address */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SAR. */ +typedef volatile struct ALT_I2C_SAR_s ALT_I2C_SAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SAR register from the beginning of the component. */ +#define ALT_I2C_SAR_OFST 0x8 +/* The address of the ALT_I2C_SAR register. */ +#define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST)) + +/* + * Register : Tx Rx Data and Command Register - ic_data_cmd + * + * This is the register the CPU writes to when filling the TX FIFO. Reading from + * this register returns bytes from RX FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------- + * [7:0] | RW | 0x0 | Tx Rx Data + * [8] | W | 0x0 | Master Read Write Control + * [9] | W | 0x0 | Generate Stop + * [10] | W | 0x0 | Generate Restart + * [31:11] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Tx Rx Data - dat + * + * This Field contains the data to be transmitted or received on the I2C bus. If + * you are writing to these bits and want to perform a read, bits 7:0 (dat) are + * ignored by the I2C. However, when you read from this register, these bits return + * the value of data received on the I2C interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_MSB 7 +/* The width in bits of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_WIDTH 8 +/* The mask used to set the ALT_I2C_DATA_CMD_DAT register field value. */ +#define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_DATA_CMD_DAT register field value. */ +#define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_DAT field value from a register. */ +#define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_DATA_CMD_DAT register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Master Read Write Control - cmd + * + * This bit controls whether a read or a write is performed. This bit does not + * control the direction when the I2C acts as a slave. It controls only the + * direction when it acts as a master. When a command is entered in the TX FIFO, + * this bit distinguishes the write and read commands. In slave-receiver mode, this + * bit is a 'don't care' because writes to this register are not required. In + * slave-transmitter mode, a '0' indicates that the CPU data is to be transmitted. + * When programming this bit, you should remember the following: attempting to + * perform a read operation after a General Call command has been sent results in a + * tx_abrt interrupt (bit 6 of the Raw Intr Status Register), unless bit 11 special + * in the Target Address Register has been cleared. If a '1' is written to this bit + * after receiving a RD_REQ interrupt, then a tx_abrt interrupt occurs. + * + * NOTE: It is possible that while attempting a master I2C read transfer on I2C, a + * RD_REQ interrupt may have occurred simultaneously due to a remote I2C master + * addressing I2C. In this type of scenario, I2C ignores the Data Cmd write, + * generates a tx_abrt interrupt, and waits to service the RD_REQ interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------- + * ALT_I2C_DATA_CMD_CMD_E_RD | 0x1 | Master Read + * ALT_I2C_DATA_CMD_CMD_E_WR | 0x0 | Master Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_CMD + * + * Master Read + */ +#define ALT_I2C_DATA_CMD_CMD_E_RD 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_CMD + * + * Master Write + */ +#define ALT_I2C_DATA_CMD_CMD_E_WR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_MSB 8 +/* The width in bits of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_CMD register field value. */ +#define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_DATA_CMD_CMD register field value. */ +#define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_CMD field value from a register. */ +#define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_DATA_CMD_CMD register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Generate Stop - stop + * + * This bit controls whether a STOP is issued after the byte is sent or received. + * + * 1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is + * empty. If the Tx FIFO is not empty, the master immediately tries to start a new + * transfer by issuing a START and arbitrating for the bus. + * + * 0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO + * is empty. If the Tx FIFO is not empty, the master continues the current transfer + * by sending/receiving data bytes according to the value of the CMD bit. If the Tx + * FIFO is empty, the master holds the SCL line low and stalls the bus until a new + * command is available in the Tx FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------ + * ALT_I2C_DATA_CMD_STOP_E_STOP | 0x1 | Issue Stop + * ALT_I2C_DATA_CMD_STOP_E_NO_STOP | 0x0 | Do Not Issue Stop + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_STOP + * + * Issue Stop + */ +#define ALT_I2C_DATA_CMD_STOP_E_STOP 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_STOP + * + * Do Not Issue Stop + */ +#define ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_MSB 9 +/* The width in bits of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_STOP register field value. */ +#define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_DATA_CMD_STOP register field value. */ +#define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_STOP field value from a register. */ +#define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_DATA_CMD_STOP register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Generate Restart - restart + * + * This bit controls whether a RESTART is issued before the byte is sent or + * received. + * + * 1 = A RESTART is issued before the data is sent/received (according to the value + * of CMD), regardless of whether or not the transfer direction is changing from + * the previous command. + * + * 0 = A RESTART is issued only if the transfer direction is changing from the + * previous command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:---------------------------------- + * ALT_I2C_DATA_CMD_RESTART_E_RESTART | 0x1 | Issue Restart + * ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE | 0x0 | Issue Restart On Direction Change + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART + * + * Issue Restart + */ +#define ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART + * + * Issue Restart On Direction Change + */ +#define ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_MSB 10 +/* The width in bits of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_RESTART register field value. */ +#define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_DATA_CMD_RESTART register field value. */ +#define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_RESTART field value from a register. */ +#define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_DATA_CMD_RESTART register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DATA_CMD. + */ +struct ALT_I2C_DATA_CMD_s +{ + uint32_t dat : 8; /* Tx Rx Data */ + uint32_t cmd : 1; /* Master Read Write Control */ + uint32_t stop : 1; /* Generate Stop */ + uint32_t restart : 1; /* Generate Restart */ + uint32_t : 21; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DATA_CMD. */ +typedef volatile struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DATA_CMD register from the beginning of the component. */ +#define ALT_I2C_DATA_CMD_OFST 0x10 +/* The address of the ALT_I2C_DATA_CMD register. */ +#define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST)) + +/* + * Register : Std Spd Clock SCL HCNT Register - ic_ss_scl_hcnt + * + * This register sets the SCL clock high-period count for standard speed. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [15:0] | RW | 0x190 | Std Spd SCL High Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Std Spd SCL High Period - ic_ss_scl_hcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock high-period count for + * standard speed. This register can be written only when the I2C interface is + * disabled which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect. The minimum valid value is 6; hardware prevents + * values less than this being written, and if attempted results in 6 being set. It + * is readable and writeable. + * + * NOTE: This register must not be programmed to a value higher than 65525, because + * I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter + * reaches a value of IC_SS_SCL_HCNT + 10. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15 +/* The width in bits of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190 +/* Extracts the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT field value from a register. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value suitable for setting the register. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SS_SCL_HCNT. + */ +struct ALT_I2C_SS_SCL_HCNT_s +{ + uint32_t ic_ss_scl_hcnt : 16; /* Std Spd SCL High Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SS_SCL_HCNT. */ +typedef volatile struct ALT_I2C_SS_SCL_HCNT_s ALT_I2C_SS_SCL_HCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SS_SCL_HCNT register from the beginning of the component. */ +#define ALT_I2C_SS_SCL_HCNT_OFST 0x14 +/* The address of the ALT_I2C_SS_SCL_HCNT register. */ +#define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST)) + +/* + * Register : Std Spd Clock SCL LCNT Register - ic_ss_scl_lcnt + * + * This register sets the SCL clock low-period count for standard speed + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [15:0] | RW | 0x1d6 | Std Spd SCL Low Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Std Spd SCL Low Period - ic_ss_scl_lcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock low period count for + * standard speed. This register can be written only when the I2C interface is + * disabled which corresponds to the Enable Register register being set to 0. + * Writes at other times have no effect. The minimum valid value is 8; hardware + * prevents values less than this from being written, and if attempted, results in + * 8 being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15 +/* The width in bits of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6 +/* Extracts the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT field value from a register. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value suitable for setting the register. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SS_SCL_LCNT. + */ +struct ALT_I2C_SS_SCL_LCNT_s +{ + uint32_t ic_ss_scl_lcnt : 16; /* Std Spd SCL Low Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SS_SCL_LCNT. */ +typedef volatile struct ALT_I2C_SS_SCL_LCNT_s ALT_I2C_SS_SCL_LCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SS_SCL_LCNT register from the beginning of the component. */ +#define ALT_I2C_SS_SCL_LCNT_OFST 0x18 +/* The address of the ALT_I2C_SS_SCL_LCNT register. */ +#define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST)) + +/* + * Register : Fast Spd Clock SCL HCNT Register - ic_fs_scl_hcnt + * + * This register sets the SCL clock high-period count for fast speed + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [15:0] | RW | 0x3c | Fast Spd SCL High Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Fast Spd SCL High Period - ic_fs_scl_hcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This register sets the SCL clock high-period count for + * fast speed. It is used in high-speed mode to send the Master Code and START BYTE + * or General CALL. This register goes away and becomes read-only returning 0s if + * in Standard Speed Mode. This register can be written only when the I2C interface + * is disabled, which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect. The minimum valid value is 6; hardware prevents + * values less than this from being written, and if attempted results in 6 being + * set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15 +/* The width in bits of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c +/* Extracts the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT field value from a register. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value suitable for setting the register. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SCL_HCNT. + */ +struct ALT_I2C_FS_SCL_HCNT_s +{ + uint32_t ic_fs_scl_hcnt : 16; /* Fast Spd SCL High Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SCL_HCNT. */ +typedef volatile struct ALT_I2C_FS_SCL_HCNT_s ALT_I2C_FS_SCL_HCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SCL_HCNT register from the beginning of the component. */ +#define ALT_I2C_FS_SCL_HCNT_OFST 0x1c +/* The address of the ALT_I2C_FS_SCL_HCNT register. */ +#define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST)) + +/* + * Register : Fast Spd Clock SCL LCNT Register - ic_fs_scl_lcnt + * + * This register sets the SCL clock low period count + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [15:0] | RW | 0x82 | Fast Spd SCL Low Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Fast Spd SCL Low Period - ic_fs_scl_lcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock low period count for + * fast speed. It is used in high-speed mode to send the Master Code and START BYTE + * or General CALL. This register can be written only when the I2C interface is + * disabled, which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect.The minimum valid value is 8; hardware prevents + * values less than this being written, and if attempted results in 8 being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15 +/* The width in bits of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82 +/* Extracts the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT field value from a register. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value suitable for setting the register. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SCL_LCNT. + */ +struct ALT_I2C_FS_SCL_LCNT_s +{ + uint32_t ic_fs_scl_lcnt : 16; /* Fast Spd SCL Low Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SCL_LCNT. */ +typedef volatile struct ALT_I2C_FS_SCL_LCNT_s ALT_I2C_FS_SCL_LCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SCL_LCNT register from the beginning of the component. */ +#define ALT_I2C_FS_SCL_LCNT_OFST 0x20 +/* The address of the ALT_I2C_FS_SCL_LCNT register. */ +#define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST)) + +/* + * Register : Interrupt Status Register - ic_intr_stat + * + * Each bit in this register has a corresponding mask bit in the Interrupt Mask + * Register. These bits are cleared by reading the matching Interrupt Clear + * Register. The unmasked raw versions of these bits are available in the Raw + * Interrupt Status Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [0] | R | 0x0 | Receiver Under + * [1] | R | 0x0 | Receiver Over + * [2] | R | 0x0 | Receive Full + * [3] | R | 0x0 | Interrupt Transmit Over + * [4] | R | 0x0 | Interrupt Transmit Empty + * [5] | R | 0x0 | Interrupt Read Request + * [6] | R | 0x0 | Interrupt TX Abort + * [7] | R | 0x0 | Interrupt RX Done + * [8] | R | 0x0 | Interrupt R_activity + * [9] | R | 0x0 | Interrupt Stop Detect + * [10] | R | 0x0 | Interrupt Start Detect + * [11] | R | 0x0 | Interrupt General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receiver Under - r_rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the Tx Rx Data and Command Register. If the module is disabled, + * Enable Register is set to 0, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_UNDER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_INTR_STAT_R_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Receiver Over - r_rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled, + * Enable Register bit[0] is set to 0 this bit keeps its level until the master or + * slave state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_OVER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_INTR_STAT_R_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive Full - r_rx_full + * + * Set when the receive buffer reaches or goes above the Receive FIFO Threshold + * Value(rx_tl). It is automatically cleared by hardware when buffer level goes + * below the threshold. If the module is disabled, Bit [0] of the Enable Register + * set to 0, the RX FIFO is flushed and held in reset; therefore the RX FIFO is not + * full. So this bit is cleared once the Enable Register Bit 0 is programmed with a + * 0, regardless of the activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_FULL field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_INTR_STAT_R_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Interrupt Transmit Over - r_tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the Data and Command + * Register. When the module is disabled, this bit keeps its level until the master + * or slave state machines goes into idle, then interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_OVER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_INTR_STAT_R_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Interrupt Transmit Empty - r_tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, this bit is set to 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_EMPTY field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_INTR_STAT_R_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Interrupt Read Request - r_rd_req + * + * This bit is set to 1 when i2c is acting as a slave and another I2C master is + * attempting to read data from I2C. The I2C holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the IC_DATA_CMD register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RD_REQ field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_INTR_STAT_R_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Interrupt TX Abort - r_tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit + * abort'.When this bit is set to 1, the ic_tx_abrt_source register indicates the + * reason why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_ABRT field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_INTR_STAT_R_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Interrupt RX Done - r_rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_DONE field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_INTR_STAT_R_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Interrupt R_activity - r_activity + * + * This bit captures I2C activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the I2C + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * I2C reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the I2C module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_ACTIVITY field value from a register. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_INTR_STAT_R_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Interrupt Stop Detect - r_stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_STOP_DET field value from a register. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_INTR_STAT_R_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Interrupt Start Detect - r_start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_START_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_START_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_START_DET field value from a register. */ +#define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_INTR_STAT_R_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Interrupt General Call - r_gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_GEN_CALL field value from a register. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_INTR_STAT_R_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_INTR_STAT. + */ +struct ALT_I2C_INTR_STAT_s +{ + const uint32_t r_rx_under : 1; /* Receiver Under */ + const uint32_t r_rx_over : 1; /* Receiver Over */ + const uint32_t r_rx_full : 1; /* Receive Full */ + const uint32_t r_tx_over : 1; /* Interrupt Transmit Over */ + const uint32_t r_tx_empty : 1; /* Interrupt Transmit Empty */ + const uint32_t r_rd_req : 1; /* Interrupt Read Request */ + const uint32_t r_tx_abrt : 1; /* Interrupt TX Abort */ + const uint32_t r_rx_done : 1; /* Interrupt RX Done */ + const uint32_t r_activity : 1; /* Interrupt R_activity */ + const uint32_t r_stop_det : 1; /* Interrupt Stop Detect */ + const uint32_t r_start_det : 1; /* Interrupt Start Detect */ + const uint32_t r_gen_call : 1; /* Interrupt General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_INTR_STAT. */ +typedef volatile struct ALT_I2C_INTR_STAT_s ALT_I2C_INTR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_INTR_STAT register from the beginning of the component. */ +#define ALT_I2C_INTR_STAT_OFST 0x2c +/* The address of the ALT_I2C_INTR_STAT register. */ +#define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST)) + +/* + * Register : Interrupt Mask Register - ic_intr_mask + * + * These bits mask their corresponding interrupt status bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------- + * [0] | RW | 0x1 | Mask RX Under + * [1] | RW | 0x1 | RX Buffer Over + * [2] | RW | 0x1 | RX Buffer Full + * [3] | RW | 0x1 | TX Buffer Over + * [4] | RW | 0x1 | TX Buffer Empty + * [5] | RW | 0x1 | Read Request + * [6] | RW | 0x1 | TX Abort + * [7] | RW | 0x1 | RX Done + * [8] | RW | 0x0 | Activity Bit + * [9] | RW | 0x0 | Stop Detect + * [10] | RW | 0x0 | Start Detect + * [11] | RW | 0x1 | General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mask RX Under - m_rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, + * this bit keeps its level until the master or slave state machines go into idle, + * and then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_UNDER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_INTR_MSK_M_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : RX Buffer Over - m_rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled + * ic_enable[0]=0, this bit keeps its level until the master or slave state + * machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_OVER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_INTR_MSK_M_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : RX Buffer Full - m_rx_full + * + * Set when the receive buffer reaches or goes above the RX_TL threshold in the + * ic_rx_tl register. It is automatically cleared by hardware when buffer level + * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is + * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the + * activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_FULL field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_INTR_MSK_M_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : TX Buffer Over - m_tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the ic_data_cmd register. + * When the module is disabled, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_OVER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_INTR_MSK_M_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : TX Buffer Empty - m_tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, then this bit is set to + * 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_EMPTY field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_INTR_MSK_M_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Read Request - m_rd_req + * + * This bit is set to 1 when I2C is acting as a slave and another I2C master is + * attempting to read data from I2C. The I2C holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the ic_data_cmd register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RD_REQ field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_INTR_MSK_M_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : TX Abort - m_tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. + * When this bit is set to 1, the ic_tx_abrt_source register indicates the reason + * why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_ABRT field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_INTR_MSK_M_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : RX Done - m_rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_DONE field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_INTR_MSK_M_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Activity Bit - m_activity + * + * This bit captures i2c activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the i2c + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * System reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the I2C module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_ACTIVITY field value from a register. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_INTR_MSK_M_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Stop Detect - m_stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether i2c is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_STOP_DET field value from a register. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_INTR_MSK_M_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Start Detect - m_start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_START_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_START_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_START_DET field value from a register. */ +#define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_INTR_MSK_M_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : General Call - m_gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_GEN_CALL field value from a register. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_INTR_MSK_M_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_INTR_MSK. + */ +struct ALT_I2C_INTR_MSK_s +{ + uint32_t m_rx_under : 1; /* Mask RX Under */ + uint32_t m_rx_over : 1; /* RX Buffer Over */ + uint32_t m_rx_full : 1; /* RX Buffer Full */ + uint32_t m_tx_over : 1; /* TX Buffer Over */ + uint32_t m_tx_empty : 1; /* TX Buffer Empty */ + uint32_t m_rd_req : 1; /* Read Request */ + uint32_t m_tx_abrt : 1; /* TX Abort */ + uint32_t m_rx_done : 1; /* RX Done */ + uint32_t m_activity : 1; /* Activity Bit */ + uint32_t m_stop_det : 1; /* Stop Detect */ + uint32_t m_start_det : 1; /* Start Detect */ + uint32_t m_gen_call : 1; /* General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_INTR_MSK. */ +typedef volatile struct ALT_I2C_INTR_MSK_s ALT_I2C_INTR_MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_INTR_MSK register from the beginning of the component. */ +#define ALT_I2C_INTR_MSK_OFST 0x30 +/* The address of the ALT_I2C_INTR_MSK register. */ +#define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST)) + +/* + * Register : Raw Interrupt Status Register - ic_raw_intr_stat + * + * Unlike the ic_intr_stat register, these bits are not masked so they always show + * the true status of the I2C. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | R | 0x0 | I2C Raw Interrupt RX Under + * [1] | R | 0x0 | Raw Interrupt RX Over + * [2] | R | 0x0 | Raw Interrupt RX Full + * [3] | R | 0x0 | Raw Interrupt TX Over + * [4] | R | 0x0 | Raw Interrupt TX Empty + * [5] | R | 0x0 | Raw Interrupt Read Request + * [6] | R | 0x0 | Raw Interrupt TX Abort + * [7] | R | 0x0 | Raw Interrupt RX Done + * [8] | R | 0x0 | Raw Interrupt Activity + * [9] | R | 0x0 | Raw Interrupt Stop Detect + * [10] | R | 0x0 | Raw Interrupt Start Detect + * [11] | R | 0x0 | Raw Interrupt General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : I2C Raw Interrupt RX Under - rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, + * this bit keeps its level until the master or slave state machines go into idle, + * then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_UNDER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Raw Interrupt RX Over - rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled + * ic_enable[0]=0), this bit keeps its level until the master or slave state + * machines go into then, this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_OVER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Raw Interrupt RX Full - rx_full + * + * Set when the receive buffer reaches or goes above the RX_TL threshold in the + * ic_rx_tl register. It is automatically cleared by hardware when buffer level + * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is + * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the + * activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_FULL field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Raw Interrupt TX Over - tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the ic_data_cmd register. + * When the module is disabled, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_OVER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Raw Interrupt TX Empty - tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, then this bit is set to + * 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_EMPTY field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Raw Interrupt Read Request - rd_req + * + * This bit is set to 1 when I2C is acting as a slave and another I2C master is + * attempting to read data from I2C. The i2c holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the ic_data_cmd register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RD_REQ field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_RAW_INTR_STAT_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Raw Interrupt TX Abort - tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. + * When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason + * why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_ABRT field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Raw Interrupt RX Done - rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1 if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_DONE field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Raw Interrupt Activity - activity + * + * This bit captures i2c activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the I2C + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * System reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the i2c module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_ACTIVITY field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Raw Interrupt Stop Detect - stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_STOP_DET field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_RAW_INTR_STAT_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Raw Interrupt Start Detect - start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_START_DET field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_RAW_INTR_STAT_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Raw Interrupt General Call - gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_GEN_CALL field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RAW_INTR_STAT. + */ +struct ALT_I2C_RAW_INTR_STAT_s +{ + const uint32_t rx_under : 1; /* I2C Raw Interrupt RX Under */ + const uint32_t rx_over : 1; /* Raw Interrupt RX Over */ + const uint32_t rx_full : 1; /* Raw Interrupt RX Full */ + const uint32_t tx_over : 1; /* Raw Interrupt TX Over */ + const uint32_t tx_empty : 1; /* Raw Interrupt TX Empty */ + const uint32_t rd_req : 1; /* Raw Interrupt Read Request */ + const uint32_t tx_abrt : 1; /* Raw Interrupt TX Abort */ + const uint32_t rx_done : 1; /* Raw Interrupt RX Done */ + const uint32_t activity : 1; /* Raw Interrupt Activity */ + const uint32_t stop_det : 1; /* Raw Interrupt Stop Detect */ + const uint32_t start_det : 1; /* Raw Interrupt Start Detect */ + const uint32_t gen_call : 1; /* Raw Interrupt General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RAW_INTR_STAT. */ +typedef volatile struct ALT_I2C_RAW_INTR_STAT_s ALT_I2C_RAW_INTR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RAW_INTR_STAT register from the beginning of the component. */ +#define ALT_I2C_RAW_INTR_STAT_OFST 0x34 +/* The address of the ALT_I2C_RAW_INTR_STAT register. */ +#define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST)) + +/* + * Register : Receive FIFO Threshold Register - ic_rx_tl + * + * I2C Receive FIFO Threshold Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [7:0] | RW | 0x0 | Receive FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Threshold Level - rx_tl + * + * Controls the level of entries (or above) that triggers the RX_FULL interrupt + * (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the + * additional restriction that hardware does not allow this value to be set to a + * value larger than the depth of the buffer. If an attempt is made to do that, the + * actual value set will be the maximum depth of the buffer. A value of 0 sets the + * threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_MSB 7 +/* The width in bits of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_WIDTH 8 +/* The mask used to set the ALT_I2C_RX_TL_RX_TL register field value. */ +#define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_RX_TL_RX_TL register field value. */ +#define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_RESET 0x0 +/* Extracts the ALT_I2C_RX_TL_RX_TL field value from a register. */ +#define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_RX_TL_RX_TL register field value suitable for setting the register. */ +#define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RX_TL. + */ +struct ALT_I2C_RX_TL_s +{ + uint32_t rx_tl : 8; /* Receive FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RX_TL. */ +typedef volatile struct ALT_I2C_RX_TL_s ALT_I2C_RX_TL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RX_TL register from the beginning of the component. */ +#define ALT_I2C_RX_TL_OFST 0x38 +/* The address of the ALT_I2C_RX_TL register. */ +#define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST)) + +/* + * Register : Transmit FIFO Threshold Level Register - ic_tx_tl + * + * Sets FIFO depth for Interrupt. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [7:0] | RW | 0x0 | Transmit FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Threshold Level - tx_tl + * + * Controls the level of entries (or below) that trigger the TX_EMPTY interrupt + * (bit 4 in ic_raw_intr_stat register). The valid range is 0-255, with the + * additional restriction that it may not be set to value larger than the depth of + * the buffer. If an attempt is made to do that, the actual value set will be the + * maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and + * a value of 255 sets the threshold for 255 entries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_MSB 7 +/* The width in bits of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_WIDTH 8 +/* The mask used to set the ALT_I2C_TX_TL_TX_TL register field value. */ +#define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_TX_TL_TX_TL register field value. */ +#define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_RESET 0x0 +/* Extracts the ALT_I2C_TX_TL_TX_TL field value from a register. */ +#define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_TX_TL_TX_TL register field value suitable for setting the register. */ +#define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TX_TL. + */ +struct ALT_I2C_TX_TL_s +{ + uint32_t tx_tl : 8; /* Transmit FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TX_TL. */ +typedef volatile struct ALT_I2C_TX_TL_s ALT_I2C_TX_TL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TX_TL register from the beginning of the component. */ +#define ALT_I2C_TX_TL_OFST 0x3c +/* The address of the ALT_I2C_TX_TL register. */ +#define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST)) + +/* + * Register : Combined and Individual Interrupt Register - ic_clr_intr + * + * Controls Interrupts + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Combined and Individual Interrupt Bits + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Combined and Individual Interrupt Bits - clr_intr + * + * Read this register to clear the combined interrupt, all individual interrupts, + * and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable + * interrupts but software clearable interrupts. Refer to Bit 9 of the + * ic_tx_abrt_source register for an exception to clearing ic_tx_abrt_source. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0 +/* The width in bits of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0 +/* Extracts the ALT_I2C_CLR_INTR_CLR_INTR field value from a register. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_INTR_CLR_INTR register field value suitable for setting the register. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_INTR. + */ +struct ALT_I2C_CLR_INTR_s +{ + const uint32_t clr_intr : 1; /* Combined and Individual Interrupt Bits */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_INTR. */ +typedef volatile struct ALT_I2C_CLR_INTR_s ALT_I2C_CLR_INTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_INTR register from the beginning of the component. */ +#define ALT_I2C_CLR_INTR_OFST 0x40 +/* The address of the ALT_I2C_CLR_INTR register. */ +#define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST)) + +/* + * Register : Rx Under Interrupt Register - ic_clr_rx_under + * + * Rx Under Interrupt Bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | R | 0x0 | Clear Rx Under Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Rx Under Interrupt Bit - clr_rx_under + * + * Read this register to clear the RX_UNDER interrupt bit 0 of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER field value from a register. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_UNDER. + */ +struct ALT_I2C_CLR_RX_UNDER_s +{ + const uint32_t clr_rx_under : 1; /* Clear Rx Under Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_UNDER. */ +typedef volatile struct ALT_I2C_CLR_RX_UNDER_s ALT_I2C_CLR_RX_UNDER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_UNDER register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_UNDER_OFST 0x44 +/* The address of the ALT_I2C_CLR_RX_UNDER register. */ +#define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST)) + +/* + * Register : RX Over Interrupt Register - ic_clr_rx_over + * + * Clears Rx over Interrupt Bit + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | RX Over Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RX Over Interrupt Bit - clr_rx_over + * + * Read this register to clear the RX_OVER interrupt bit 1 of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER field value from a register. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_OVER. + */ +struct ALT_I2C_CLR_RX_OVER_s +{ + const uint32_t clr_rx_over : 1; /* RX Over Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_OVER. */ +typedef volatile struct ALT_I2C_CLR_RX_OVER_s ALT_I2C_CLR_RX_OVER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_OVER register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_OVER_OFST 0x48 +/* The address of the ALT_I2C_CLR_RX_OVER register. */ +#define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST)) + +/* + * Register : TX Over Interrupt Register - ic_clr_tx_over + * + * Clears Over Interrupts + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | TX Over Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : TX Over Interrupt Bit - clr_tx_over + * + * Read this register to clear the TX_OVER interrupt (bit 3) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER field value from a register. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_TX_OVER. + */ +struct ALT_I2C_CLR_TX_OVER_s +{ + const uint32_t clr_tx_over : 1; /* TX Over Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_TX_OVER. */ +typedef volatile struct ALT_I2C_CLR_TX_OVER_s ALT_I2C_CLR_TX_OVER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_TX_OVER register from the beginning of the component. */ +#define ALT_I2C_CLR_TX_OVER_OFST 0x4c +/* The address of the ALT_I2C_CLR_TX_OVER register. */ +#define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST)) + +/* + * Register : Interrupt Read Request Register - ic_clr_rd_req + * + * Clear RD_REQ Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | R | 0x0 | Interrupt Register Read Request Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Register Read Request Bit - clr_rd_req + * + * Read this register to clear the RD_REQ interrupt (bit 5) of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ field value from a register. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RD_REQ. + */ +struct ALT_I2C_CLR_RD_REQ_s +{ + const uint32_t clr_rd_req : 1; /* Interrupt Register Read Request Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RD_REQ. */ +typedef volatile struct ALT_I2C_CLR_RD_REQ_s ALT_I2C_CLR_RD_REQ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RD_REQ register from the beginning of the component. */ +#define ALT_I2C_CLR_RD_REQ_OFST 0x50 +/* The address of the ALT_I2C_CLR_RD_REQ register. */ +#define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST)) + +/* + * Register : Tx Abort Interrupt Register - ic_clr_tx_abrt + * + * Clear TX_ABRT Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | Tx Abort Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Tx Abort Interrupt Bit - clr_tx_abort + * + * Read this register to clear the TX_ABRT interrupt (bit 6) of the + * ic_raw_intr_stat register, and the ic_tx_abrt_source register. This also + * releases the TX FIFO from the flushed/reset state, allowing more writes to the + * TX FIFO. Refer to Bit 9 of the ic_tx_abrt_source register for an exception to + * clearing ic_tx_abrt_source. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0 +/* The width in bits of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0 +/* Extracts the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT field value from a register. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value suitable for setting the register. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_TX_ABRT. + */ +struct ALT_I2C_CLR_TX_ABRT_s +{ + const uint32_t clr_tx_abort : 1; /* Tx Abort Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_TX_ABRT. */ +typedef volatile struct ALT_I2C_CLR_TX_ABRT_s ALT_I2C_CLR_TX_ABRT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_TX_ABRT register from the beginning of the component. */ +#define ALT_I2C_CLR_TX_ABRT_OFST 0x54 +/* The address of the ALT_I2C_CLR_TX_ABRT register. */ +#define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST)) + +/* + * Register : Rx Done Interrupt Register - ic_clr_rx_done + * + * Clear RX_DONE Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | RX_DONE Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RX_DONE Interrupt Bit - clr_rx_done + * + * Read this register to clear the RX_DONE interrupt (bit 7) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE field value from a register. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_DONE. + */ +struct ALT_I2C_CLR_RX_DONE_s +{ + const uint32_t clr_rx_done : 1; /* RX_DONE Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_DONE. */ +typedef volatile struct ALT_I2C_CLR_RX_DONE_s ALT_I2C_CLR_RX_DONE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_DONE register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_DONE_OFST 0x58 +/* The address of the ALT_I2C_CLR_RX_DONE register. */ +#define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST)) + +/* + * Register : Activity Interrupt Register - ic_clr_activity + * + * Clears ACTIVITY Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | Activity Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Activity Interrupt Bit - clr_activity + * + * Reading this register clears the ACTIVITY interrupt if the I2C is not active + * anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt + * bit continues to be set. It is automatically cleared by hardware if the module + * is disabled and if there is no further activity on the bus. The value read from + * this register to get status of the ACTIVITY interrupt (bit 8) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0 +/* The width in bits of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY field value from a register. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_ACTIVITY. + */ +struct ALT_I2C_CLR_ACTIVITY_s +{ + const uint32_t clr_activity : 1; /* Activity Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_ACTIVITY. */ +typedef volatile struct ALT_I2C_CLR_ACTIVITY_s ALT_I2C_CLR_ACTIVITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_ACTIVITY register from the beginning of the component. */ +#define ALT_I2C_CLR_ACTIVITY_OFST 0x5c +/* The address of the ALT_I2C_CLR_ACTIVITY register. */ +#define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST)) + +/* + * Register : Stop Detect Interrupt Register - ic_clr_stop_det + * + * Clear Interrupts. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [0] | R | 0x0 | Stop Detect Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Stop Detect Interrupt Bit - clr_stop_det + * + * Read this register to clear the clr_stop_det interrupt (bit 9) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0 +/* The width in bits of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET field value from a register. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_STOP_DET. + */ +struct ALT_I2C_CLR_STOP_DET_s +{ + const uint32_t clr_stop_det : 1; /* Stop Detect Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_STOP_DET. */ +typedef volatile struct ALT_I2C_CLR_STOP_DET_s ALT_I2C_CLR_STOP_DET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_STOP_DET register from the beginning of the component. */ +#define ALT_I2C_CLR_STOP_DET_OFST 0x60 +/* The address of the ALT_I2C_CLR_STOP_DET register. */ +#define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST)) + +/* + * Register : Start Detect Interrupt Register - ic_clr_start_det + * + * Clears START_DET Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | R | 0x0 | Start Detect Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Detect Interrupt Bit - clr_start_det + * + * Read this register to clear the start_det interrupt (bit 10) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0 +/* The width in bits of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_CLR_START_DET_CLR_START_DET field value from a register. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_START_DET_CLR_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_START_DET. + */ +struct ALT_I2C_CLR_START_DET_s +{ + const uint32_t clr_start_det : 1; /* Start Detect Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_START_DET. */ +typedef volatile struct ALT_I2C_CLR_START_DET_s ALT_I2C_CLR_START_DET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_START_DET register from the beginning of the component. */ +#define ALT_I2C_CLR_START_DET_OFST 0x64 +/* The address of the ALT_I2C_CLR_START_DET register. */ +#define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST)) + +/* + * Register : GEN CALL Interrupt Register - ic_clr_gen_call + * + * Clear GEN_CALL Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | GEN CALL Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GEN CALL Interrupt Bit - clr_gen_call + * + * Read this register to clear the GEN_CALL interrupt (bit 11) of ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0 +/* The width in bits of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL field value from a register. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_GEN_CALL. + */ +struct ALT_I2C_CLR_GEN_CALL_s +{ + const uint32_t clr_gen_call : 1; /* GEN CALL Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_GEN_CALL. */ +typedef volatile struct ALT_I2C_CLR_GEN_CALL_s ALT_I2C_CLR_GEN_CALL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_GEN_CALL register from the beginning of the component. */ +#define ALT_I2C_CLR_GEN_CALL_OFST 0x68 +/* The address of the ALT_I2C_CLR_GEN_CALL register. */ +#define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST)) + +/* + * Register : Enable Register - ic_enable + * + * Enable and disable i2c operation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Enable Bit + * [1] | RW | 0x0 | TX abort Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable Bit - enable + * + * Controls whether the I2C is enabled. Software can disable I2C while it is + * active. However, it is important that care be taken to ensure that I2C is + * disabled properly. When the I2C is disabled, the following occurs: + * + * The TX FIFO and RX FIFO get flushed. Status bits in the IC_INTR_STAT register + * are still active until I2C goes into IDLE state. If the module is transmitting, + * it stops as well as deletes the contents of the transmit buffer after the + * current transfer is complete. If the module is receiving, the I2C stops the + * current transfer at the end of the current byte and does not acknowledge the + * transfer. The l4_sp_clk synchronizes pclk and ic_clk. The register + * ic_enable_status is added to allow software to determine when the hardware has + * completely shutdown in response to the IC_ENABLE register being set from 1 to 0. + * Only one register is required to be monitored. Procedure for Disabling I2C + * + * 1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling + * period for the highest I2C transfer speed used in the system and supported by + * I2C. For example, if the highest I2C transfer mode is 400 kb/s, then this + * ti2c_poll is 25us. + * + * 2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any + * repeated polling operation exceeds this maximum value, an error is reported. 3. + * Execute a blocking thread/process/function that prevents any further I2C master + * transactions to be started by software, but allows any pending transfers to be + * completed. + * + * 4. The variable POLL_COUNT is initialized to zero. 5. Set IC_ENABLE to 0. + * + * 6. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment + * POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant + * error code. + * + * 7. If IC_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the + * previous step. Otherwise, exit with a relevant success code. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------|:------|:----------------------------------------------- + * ALT_I2C_EN_EN_E_DIS | 0x0 | Disables i2c. TX and RX FIFOs are held in an + * : | | erased state + * ALT_I2C_EN_EN_E_EN | 0x1 | Enables i2c. Software can disable i2c while it + * : | | is active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_EN_EN + * + * Disables i2c. TX and RX FIFOs are held in an erased state + */ +#define ALT_I2C_EN_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_EN_EN + * + * Enables i2c. Software can disable i2c while it is active + */ +#define ALT_I2C_EN_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_MSB 0 +/* The width in bits of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_EN register field value. */ +#define ALT_I2C_EN_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_EN_EN register field value. */ +#define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_RESET 0x0 +/* Extracts the ALT_I2C_EN_EN field value from a register. */ +#define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_EN_EN register field value suitable for setting the register. */ +#define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TX abort Bit - txabort + * + * Write 1 does a TX abort. Self cleared on abort completion + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_MSB 1 +/* The width in bits of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_TXABT register field value. */ +#define ALT_I2C_EN_TXABT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_EN_TXABT register field value. */ +#define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_RESET 0x0 +/* Extracts the ALT_I2C_EN_TXABT field value from a register. */ +#define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_EN_TXABT register field value suitable for setting the register. */ +#define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_EN. + */ +struct ALT_I2C_EN_s +{ + uint32_t enable : 1; /* Enable Bit */ + uint32_t txabort : 1; /* TX abort Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_EN. */ +typedef volatile struct ALT_I2C_EN_s ALT_I2C_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_EN register from the beginning of the component. */ +#define ALT_I2C_EN_OFST 0x6c +/* The address of the ALT_I2C_EN register. */ +#define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST)) + +/* + * Register : Status Register - ic_status + * + * This is a read-only register used to indicate the current transfer status and + * FIFO status. The status register may be read at any time. None of the bits in + * this register request an interrupt.When the I2C is disabled by writing 0 in bit + * 0 of the ic_enable register: + * + * * Bits 1 and 2 are set to 1 + * + * * Bits 3 and 4 are set to 0 + * + * When the master or slave state machines goes to idle + * + * * Bits 5 and 6 are set to 0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | R | 0x0 | Activity Status Bit + * [1] | R | 0x1 | TX FIFO Not Full Bit + * [2] | R | 0x1 | TX FIFO Empty Bit + * [3] | R | 0x0 | RX FIFO Empty Bit + * [4] | R | 0x0 | RX FIFO Full Bit + * [5] | R | 0x0 | Master FSM Activity Status Bit + * [6] | R | 0x0 | Slave FSM Activity Status Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Activity Status Bit - activity + * + * I2C Activity. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_MSB 0 +/* The width in bits of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_ACTIVITY register field value. */ +#define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_STAT_ACTIVITY register field value. */ +#define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_STAT_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TX FIFO Not Full Bit - tfnf + * + * Transmit Fifo Full + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------------------- + * ALT_I2C_STAT_TFNF_E_FULL | 0x0 | Transmit FIFO is full + * ALT_I2C_STAT_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_TFNF + * + * Transmit FIFO is full + */ +#define ALT_I2C_STAT_TFNF_E_FULL 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_TFNF + * + * Transmit FIFO is not full + */ +#define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_MSB 1 +/* The width in bits of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_TFNF register field value. */ +#define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_STAT_TFNF register field value. */ +#define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_RESET 0x1 +/* Extracts the ALT_I2C_STAT_TFNF field value from a register. */ +#define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_STAT_TFNF register field value suitable for setting the register. */ +#define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : TX FIFO Empty Bit - tfe + * + * Transmit FIFO Empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_I2C_STAT_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty + * ALT_I2C_STAT_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_TFE + * + * Transmit FIFO is not empty + */ +#define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_TFE + * + * Transmit FIFO is empty + */ +#define ALT_I2C_STAT_TFE_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_MSB 2 +/* The width in bits of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_TFE register field value. */ +#define ALT_I2C_STAT_TFE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_STAT_TFE register field value. */ +#define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_RESET 0x1 +/* Extracts the ALT_I2C_STAT_TFE field value from a register. */ +#define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_STAT_TFE register field value suitable for setting the register. */ +#define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : RX FIFO Empty Bit - rfne + * + * Receive FIFO Not Empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------- + * ALT_I2C_STAT_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty + * ALT_I2C_STAT_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_RFNE + * + * Receive FIFO is empty + */ +#define ALT_I2C_STAT_RFNE_E_EMPTY 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_RFNE + * + * Receive FIFO is not empty + */ +#define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_MSB 3 +/* The width in bits of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_RFNE register field value. */ +#define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_STAT_RFNE register field value. */ +#define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_RESET 0x0 +/* Extracts the ALT_I2C_STAT_RFNE field value from a register. */ +#define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_STAT_RFNE register field value suitable for setting the register. */ +#define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : RX FIFO Full Bit - rff + * + * Receive FIFO Completely Full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:------------------------- + * ALT_I2C_STAT_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full + * ALT_I2C_STAT_RFF_E_FULL | 0x1 | Receive FIFO is full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_RFF + * + * Receive FIFO is not full + */ +#define ALT_I2C_STAT_RFF_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_RFF + * + * Receive FIFO is full + */ +#define ALT_I2C_STAT_RFF_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_MSB 4 +/* The width in bits of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_RFF register field value. */ +#define ALT_I2C_STAT_RFF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_STAT_RFF register field value. */ +#define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_RESET 0x0 +/* Extracts the ALT_I2C_STAT_RFF field value from a register. */ +#define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_STAT_RFF register field value suitable for setting the register. */ +#define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Master FSM Activity Status Bit - mst_activity + * + * When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is + * set. Note:IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and + * MST_ACTIVITY bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------ + * ALT_I2C_STAT_MST_ACTIVITY_E_IDLE | 0x0 | Master FSM is in IDLE state. Master part of i2c + * : | | is not Active + * ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE | 0x1 | Master FSM is not in IDLE state. Master part of + * : | | i2c is Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY + * + * Master FSM is in IDLE state. Master part of i2c is not Active + */ +#define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY + * + * Master FSM is not in IDLE state. Master part of i2c is Active + */ +#define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_MSB 5 +/* The width in bits of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_MST_ACTIVITY register field value. */ +#define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_STAT_MST_ACTIVITY register field value. */ +#define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_MST_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_STAT_MST_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Slave FSM Activity Status Bit - slv_activity + * + * Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in + * the IDLE state, this bit is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE | 0x0 | Slave FSM is in IDLE state so the Slave part of + * : | | i2c is not Active + * ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE | 0x1 | Slave FSM is not in IDLE state so the Slave part + * : | | of i2c is Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY + * + * Slave FSM is in IDLE state so the Slave part of i2c is not Active + */ +#define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY + * + * Slave FSM is not in IDLE state so the Slave part of i2c is Active + */ +#define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6 +/* The width in bits of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_SLV_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_STAT_SLV_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_STAT. + */ +struct ALT_I2C_STAT_s +{ + const uint32_t activity : 1; /* Activity Status Bit */ + const uint32_t tfnf : 1; /* TX FIFO Not Full Bit */ + const uint32_t tfe : 1; /* TX FIFO Empty Bit */ + const uint32_t rfne : 1; /* RX FIFO Empty Bit */ + const uint32_t rff : 1; /* RX FIFO Full Bit */ + const uint32_t mst_activity : 1; /* Master FSM Activity Status Bit */ + const uint32_t slv_activity : 1; /* Slave FSM Activity Status Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_STAT. */ +typedef volatile struct ALT_I2C_STAT_s ALT_I2C_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_STAT register from the beginning of the component. */ +#define ALT_I2C_STAT_OFST 0x70 +/* The address of the ALT_I2C_STAT register. */ +#define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST)) + +/* + * Register : Transmit FIFO Level Register - ic_txflr + * + * This register contains the number of valid data entries in the transmit FIFO + * buffer. It is cleared whenever: + * + * * The I2C is disabled + * + * * There is a transmit abort that is, TX_ABRT bit is set in the ic_raw_intr_stat + * register. The slave bulk transmit mode is aborted The register increments + * whenever data is placed into the transmit FIFO and decrements when data is + * taken from the transmit FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [6:0] | R | 0x0 | Transmit FIFO Level Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Level Bit - txflr + * + * Transmit FIFO Level.Contains the number of valid data entries in the transmit + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_MSB 6 +/* The width in bits of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_WIDTH 7 +/* The mask used to set the ALT_I2C_TXFLR_TXFLR register field value. */ +#define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_I2C_TXFLR_TXFLR register field value. */ +#define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_RESET 0x0 +/* Extracts the ALT_I2C_TXFLR_TXFLR field value from a register. */ +#define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_I2C_TXFLR_TXFLR register field value suitable for setting the register. */ +#define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TXFLR. + */ +struct ALT_I2C_TXFLR_s +{ + const uint32_t txflr : 7; /* Transmit FIFO Level Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TXFLR. */ +typedef volatile struct ALT_I2C_TXFLR_s ALT_I2C_TXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TXFLR register from the beginning of the component. */ +#define ALT_I2C_TXFLR_OFST 0x74 +/* The address of the ALT_I2C_TXFLR register. */ +#define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST)) + +/* + * Register : Receive FIFO Level Register - ic_rxflr + * + * This register contains the number of valid data entries in the receive FIFO + * buffer. It is cleared whenever: + * + * * The I2C is disabled + * + * * Whenever there is a transmit abort caused by any of the events tracked in + * ic_tx_abrt_source The register increments whenever data is placed into the + * receive FIFO and decrements when data is taken from the receive FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [6:0] | R | 0x0 | Receive FIFO Level Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Level Bit - rxflr + * + * Receive FIFO Level. Contains the number of valid data entries in the receive + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_MSB 6 +/* The width in bits of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_WIDTH 7 +/* The mask used to set the ALT_I2C_RXFLR_RXFLR register field value. */ +#define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_I2C_RXFLR_RXFLR register field value. */ +#define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_RESET 0x0 +/* Extracts the ALT_I2C_RXFLR_RXFLR field value from a register. */ +#define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_I2C_RXFLR_RXFLR register field value suitable for setting the register. */ +#define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RXFLR. + */ +struct ALT_I2C_RXFLR_s +{ + const uint32_t rxflr : 7; /* Receive FIFO Level Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RXFLR. */ +typedef volatile struct ALT_I2C_RXFLR_s ALT_I2C_RXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RXFLR register from the beginning of the component. */ +#define ALT_I2C_RXFLR_OFST 0x78 +/* The address of the ALT_I2C_RXFLR register. */ +#define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST)) + +/* + * Register : SDA Hold Register - ic_sda_hold + * + * This register controls the amount of time delay (in terms of number of l4_sp_clk + * clock periods) introduced in the falling edge of SCL, relative to SDA changing, + * when I2C services a read request in a slave-transmitter operation. The relevant + * I2C requirement is thd:DAT as detailed in the I2C Bus Specification. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------- + * [15:0] | RW | 0x1 | SDA Hold Bit + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDA Hold Bit - ic_sda_hold + * + * Program to a minimum 0f 300ns. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_MSB 15 +/* The width in bits of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_WIDTH 16 +/* The mask used to set the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_RESET 0x1 +/* Extracts the ALT_I2C_SDA_HOLD_IC_SDA_HOLD field value from a register. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value suitable for setting the register. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SDA_HOLD. + */ +struct ALT_I2C_SDA_HOLD_s +{ + uint32_t ic_sda_hold : 16; /* SDA Hold Bit */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SDA_HOLD. */ +typedef volatile struct ALT_I2C_SDA_HOLD_s ALT_I2C_SDA_HOLD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SDA_HOLD register from the beginning of the component. */ +#define ALT_I2C_SDA_HOLD_OFST 0x7c +/* The address of the ALT_I2C_SDA_HOLD register. */ +#define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST)) + +/* + * Register : Transmit Abort Source Register - ic_tx_abrt_source + * + * This register has 16 bits that indicate the source of the TX_ABRT bit. Except + * for Bit 9, this register is cleared whenever the ic_clr_tx_abrt register or the + * ic_clr_intr register is read. To clear Bit 9, the source of the + * abrt_sbyte_norstrt must be fixed first; RESTART must be enabled (ic_con[5]=1), + * the special bit must be cleared (ic_tar[11]), or the gc_or_start bit must be + * cleared (ic_tar[10]). Once the source of the abrt_sbyte_norstrt is fixed, then + * this bit can be cleared in the same manner as other bits in this register. If + * the source of the abrt_sbyte_norstrt is not fixed before attempting to clear + * this bit, Bit 9 clears for one cycle and is then re-asserted. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | Master Abort 7 Bit Address + * [1] | RW | 0x0 | Master Abort 10 Bit Address Byte 1 + * [2] | RW | 0x0 | Master Abort 10 Bit Address Byte 2 + * [3] | RW | 0x0 | Master Abort TX Noack Bit + * [4] | RW | 0x0 | Master Abort GC Noack Bit + * [5] | RW | 0x0 | Master Abort GC Read Bit + * [6] | RW | 0x0 | Master HS MC Ack + * [7] | RW | 0x0 | Master Abort START Byte + * [8] | RW | 0x0 | Master HS Restart Disabled + * [9] | RW | 0x0 | Master Abort START No Restart + * [10] | RW | 0x0 | Master Abort 10 Bit No Restart + * [11] | RW | 0x0 | Master Oper Master Dis + * [12] | RW | 0x0 | Master Abort Arbitration Lost + * [13] | RW | 0x0 | Slave Abort Flush TXFIFO + * [14] | RW | 0x0 | Slave Abort Arbitration Lost + * [15] | RW | 0x0 | Slave Abort Read TX + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Abort 7 Bit Address - abrt_7b_addr_noack + * + * Master is in 7-bit addressing mode and the address sent was not acknowledged by + * any slave. Role of i2c: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Master Abort 10 Bit Address Byte 1 - abrt_10addr1_noack + * + * Master is in 10-bit address mode and the first 10-bit address byte was not + * acknowledged by any slave. Role of i2c: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Master Abort 10 Bit Address Byte 2 - abrt_10addr2_noack + * + * Master is in 10-bit address mode and the second address byte of the 10-bit + * address was not acknowledged by any slave. Role of i2c: Master-Transmitter or + * Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Master Abort TX Noack Bit - abrt_txdata_noack + * + * This is a master-mode only bit. Master has received an acknowledgement for the + * address, but when it sent data byte(s) following the address, it did not receive + * an acknowledge from the remote slave(s). Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Master Abort GC Noack Bit - abrt_gcall_noack + * + * i2c in master mode sent a General Call and no slave on the bus acknowledged the + * General Call. Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Master Abort GC Read Bit - abrt_gcall_read + * + * i2c in master mode sent a General Call but the user programmed the byte + * following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to + * 1). Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Master HS MC Ack - abrt_hs_ackdet + * + * Master is in High Speed mode and the High Speed Master code was acknowledged + * (wrong behavior). Role of i2c: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Master Abort START Byte - abrt_sbyte_ackdet + * + * Master has sent a START Byte and the START Byte was acknowledged (wrong + * behavior). Role of i2c: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Master HS Restart Disabled - abrt_hs_norstrt + * + * The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is + * trying to use the master to transfer data in High Speed mode. Role of i2c: + * Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Master Abort START No Restart - abrt_sbyte_norstrt + * + * To clear Bit 9, the source of then abrt_sbyte_norstrt must be fixed first; + * restart must be enabled (ic_con[5]=1), the SPECIAL bit must be cleared + * (ic_tar[11]), or the GC_OR_START bit must be cleared (ic_tar[10]). Once the + * source of the abrt_sbyte_norstrt is fixed, then this bit can be cleared in the + * same manner as other bits in this register. If the source of the + * abrt_sbyte_norstrt is not fixed before attempting to clear this bit, bit 9 + * clears for one cycle and then gets reasserted. 1: The restart is disabled + * (IC_RESTART_EN bit (ic_con[5]) =0) and the user is trying to send a START Byte. + * Role of I2C: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Master Abort 10 Bit No Restart - abrt_10b_rd_norstrt + * + * The restart is disabled (ic_restart_en bit (ic_con[5]) =0) and the master sends + * a read command in 10-bit addressing mode. Role of I2C: Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Master Oper Master Dis - abrt_master_dis + * + * User tries to initiate a Master operation with the Master mode disabled. Role of + * I2C: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Master Abort Arbitration Lost - arb_lost + * + * Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the + * slave transmitter has lost arbitration. Note: I2C can be both master and slave + * at the same time. Role of i2c: Master-Transmitter or Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ARB_LOST field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Slave Abort Flush TXFIFO - abrt_slvflush_txfifo + * + * Slave has received a read command and some data exists in the TX FIFO so the + * slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Role of I2C: + * Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Slave Abort Arbitration Lost - abrt_slv_arblost + * + * Slave lost the bus while transmitting data to a remote master. + * IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never + * 'owns' the bus, something could go wrong on the bus. This is a fail safe check. + * For instance, during a data transmission at the low-to-high transition of SCL, + * if what is on the data bus is not what is supposed to be transmitted, then i2c + * no longer own the bus. Role of I2C: Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Slave Abort Read TX - abrt_slvrd_intx + * + * When the processor side responds to a slave mode request for data to be + * transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD + * register. Role of I2C: Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TX_ABRT_SRC. + */ +struct ALT_I2C_TX_ABRT_SRC_s +{ + uint32_t abrt_7b_addr_noack : 1; /* Master Abort 7 Bit Address */ + uint32_t abrt_10addr1_noack : 1; /* Master Abort 10 Bit Address Byte 1 */ + uint32_t abrt_10addr2_noack : 1; /* Master Abort 10 Bit Address Byte 2 */ + uint32_t abrt_txdata_noack : 1; /* Master Abort TX Noack Bit */ + uint32_t abrt_gcall_noack : 1; /* Master Abort GC Noack Bit */ + uint32_t abrt_gcall_read : 1; /* Master Abort GC Read Bit */ + uint32_t abrt_hs_ackdet : 1; /* Master HS MC Ack */ + uint32_t abrt_sbyte_ackdet : 1; /* Master Abort START Byte */ + uint32_t abrt_hs_norstrt : 1; /* Master HS Restart Disabled */ + uint32_t abrt_sbyte_norstrt : 1; /* Master Abort START No Restart */ + uint32_t abrt_10b_rd_norstrt : 1; /* Master Abort 10 Bit No Restart */ + uint32_t abrt_master_dis : 1; /* Master Oper Master Dis */ + uint32_t arb_lost : 1; /* Master Abort Arbitration Lost */ + uint32_t abrt_slvflush_txfifo : 1; /* Slave Abort Flush TXFIFO */ + uint32_t abrt_slv_arblost : 1; /* Slave Abort Arbitration Lost */ + uint32_t abrt_slvrd_intx : 1; /* Slave Abort Read TX */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TX_ABRT_SRC. */ +typedef volatile struct ALT_I2C_TX_ABRT_SRC_s ALT_I2C_TX_ABRT_SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TX_ABRT_SRC register from the beginning of the component. */ +#define ALT_I2C_TX_ABRT_SRC_OFST 0x80 +/* The address of the ALT_I2C_TX_ABRT_SRC register. */ +#define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST)) + +/* + * Register : Generate Slave Data NACK - ic_slv_data_nack_only + * + * The register is used to generate a NACK for the data part of a transfer when i2c + * is acting as a slave-receiver. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [0] | RW | 0x0 | Generate Nack Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Generate Nack Bit - nack + * + * This Bit control Nack generation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:-------------------------------------- + * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE | 0x1 | Generate NACK after data byte receive + * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM | 0x0 | Generate NACK/ACK normally + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK + * + * Generate NACK after data byte receive + */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1 +/* + * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK + * + * Generate NACK/ACK normally + */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0 +/* The width in bits of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1 +/* The mask used to set the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0 +/* Extracts the ALT_I2C_SLV_DATA_NACK_ONLY_NACK field value from a register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value suitable for setting the register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. + */ +struct ALT_I2C_SLV_DATA_NACK_ONLY_s +{ + uint32_t nack : 1; /* Generate Nack Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. */ +typedef volatile struct ALT_I2C_SLV_DATA_NACK_ONLY_s ALT_I2C_SLV_DATA_NACK_ONLY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SLV_DATA_NACK_ONLY register from the beginning of the component. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84 +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST)) + +/* + * Register : DMA Control - ic_dma_cr + * + * The register is used to enable the DMA Controller interface operation. There is + * a separate bit for transmit and receive. This can be programmed regardless of + * the state of IC_ENABLE. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | Receive DMA Enable Bit + * [1] | RW | 0x0 | Transmit DMA Enable Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive DMA Enable Bit - rdmae + * + * This bit enables/disables the receive FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------- + * ALT_I2C_DMA_CR_RDMAE_E_DIS | 0x0 | Receive DMA disable + * ALT_I2C_DMA_CR_RDMAE_E_EN | 0x1 | Receive DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE + * + * Receive DMA disable + */ +#define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE + * + * Receive DMA enabled + */ +#define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_MSB 0 +/* The width in bits of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_WIDTH 1 +/* The mask used to set the ALT_I2C_DMA_CR_RDMAE register field value. */ +#define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_DMA_CR_RDMAE register field value. */ +#define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_RESET 0x0 +/* Extracts the ALT_I2C_DMA_CR_RDMAE field value from a register. */ +#define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_DMA_CR_RDMAE register field value suitable for setting the register. */ +#define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit DMA Enable Bit - tdmae + * + * This bit enables/disables the transmit FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------- + * ALT_I2C_DMA_CR_TDMAE_E_DIS | 0x0 | Transmit DMA disable + * ALT_I2C_DMA_CR_TDMAE_E_EN | 0x1 | Transmit DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE + * + * Transmit DMA disable + */ +#define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE + * + * Transmit DMA enabled + */ +#define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_MSB 1 +/* The width in bits of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_WIDTH 1 +/* The mask used to set the ALT_I2C_DMA_CR_TDMAE register field value. */ +#define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_DMA_CR_TDMAE register field value. */ +#define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_RESET 0x0 +/* Extracts the ALT_I2C_DMA_CR_TDMAE field value from a register. */ +#define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_DMA_CR_TDMAE register field value suitable for setting the register. */ +#define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_CR. + */ +struct ALT_I2C_DMA_CR_s +{ + uint32_t rdmae : 1; /* Receive DMA Enable Bit */ + uint32_t tdmae : 1; /* Transmit DMA Enable Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_CR. */ +typedef volatile struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_CR register from the beginning of the component. */ +#define ALT_I2C_DMA_CR_OFST 0x88 +/* The address of the ALT_I2C_DMA_CR register. */ +#define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST)) + +/* + * Register : DMA Transmit Data Level - ic_dma_tdlr + * + * This register supports DMA Transmit Operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [5:0] | RW | 0x0 | DMA Transmit Data Level Bit + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DMA Transmit Data Level Bit - dmatdl + * + * This bit field controls the level at which a DMA request is made by the transmit + * logic. It is equal to the watermark level; that is, the i2c_dma_tx_req signal is + * generated when the number of valid data entries in the transmit FIFO is equal to + * or below this field value, and TDMAE = 1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_MSB 5 +/* The width in bits of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6 +/* The mask used to set the ALT_I2C_DMA_TDLR_DMATDL register field value. */ +#define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f +/* The mask used to clear the ALT_I2C_DMA_TDLR_DMATDL register field value. */ +#define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0 +/* Extracts the ALT_I2C_DMA_TDLR_DMATDL field value from a register. */ +#define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_I2C_DMA_TDLR_DMATDL register field value suitable for setting the register. */ +#define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_TDLR. + */ +struct ALT_I2C_DMA_TDLR_s +{ + uint32_t dmatdl : 6; /* DMA Transmit Data Level Bit */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_TDLR. */ +typedef volatile struct ALT_I2C_DMA_TDLR_s ALT_I2C_DMA_TDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_TDLR register from the beginning of the component. */ +#define ALT_I2C_DMA_TDLR_OFST 0x8c +/* The address of the ALT_I2C_DMA_TDLR register. */ +#define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST)) + +/* + * Register : Receive Data Level - ic_dma_rdlr + * + * DMA Control Signals Interface. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [5:0] | RW | 0x0 | Receive Data Level Bits + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive Data Level Bits - dmardl + * + * This bit field controls the level at which a DMA request is made by the receive + * logic. The watermark level \= DMARDL+1; that is, dma_rx_req is generated when + * the number of valid data entries in the receive FIFO is equal to or more than + * this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then + * dma_rx_req is asserted when or more data entries are present in the receive + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_MSB 5 +/* The width in bits of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6 +/* The mask used to set the ALT_I2C_DMA_RDLR_DMARDL register field value. */ +#define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f +/* The mask used to clear the ALT_I2C_DMA_RDLR_DMARDL register field value. */ +#define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0 +/* Extracts the ALT_I2C_DMA_RDLR_DMARDL field value from a register. */ +#define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_I2C_DMA_RDLR_DMARDL register field value suitable for setting the register. */ +#define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_RDLR. + */ +struct ALT_I2C_DMA_RDLR_s +{ + uint32_t dmardl : 6; /* Receive Data Level Bits */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_RDLR. */ +typedef volatile struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_RDLR register from the beginning of the component. */ +#define ALT_I2C_DMA_RDLR_OFST 0x90 +/* The address of the ALT_I2C_DMA_RDLR register. */ +#define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST)) + +/* + * Register : SDA Setup Register - ic_sda_setup + * + * This register controls the amount of time delay (in terms of number of l4_sp_clk + * clock periods) introduced in the rising edge of SCL relative to SDA changing by + * holding SCL low when I2C services a read request while operating as a slave- + * transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the + * I2C Bus Specification. This register must be programmed with a value equal to or + * greater than 2. + * + * Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * + * (l4_sp_clk)], so if the user requires 10 l4_sp_clk periods of setup time, they + * should program a value of 11. The IC_SDA_SETUP register is only used by the I2C + * when operating as a slave transmitter. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [7:0] | RW | 0x64 | SDA Setup Value + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDA Setup Value - sda_setup + * + * It is recommended that if the required delay is 1000ns, then for an l4_sp_clk + * frequency of 10 MHz, ic_sda_setup should be programmed to a value of 11. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7 +/* The width in bits of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8 +/* The mask used to set the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64 +/* Extracts the ALT_I2C_SDA_SETUP_SDA_SETUP field value from a register. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_SDA_SETUP_SDA_SETUP register field value suitable for setting the register. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SDA_SETUP. + */ +struct ALT_I2C_SDA_SETUP_s +{ + uint32_t sda_setup : 8; /* SDA Setup Value */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SDA_SETUP. */ +typedef volatile struct ALT_I2C_SDA_SETUP_s ALT_I2C_SDA_SETUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SDA_SETUP register from the beginning of the component. */ +#define ALT_I2C_SDA_SETUP_OFST 0x94 +/* The address of the ALT_I2C_SDA_SETUP register. */ +#define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST)) + +/* + * Register : ACK General Call - ic_ack_general_call + * + * The register controls whether i2c responds with a ACK or NACK when it receives + * an I2C General Call address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | ACK General Call Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ACK General Call Bit - ack_gen_call + * + * When an ACK is asserted, (by asserting i2c_out_data) when it receives a General + * call. Otherwise, i2c responds with a NACK (by negating i2c_out_data). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------- + * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK | 0x0 | I2C responds with a NACK + * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK | 0x1 | I2C responds with an ACK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL + * + * I2C responds with a NACK + */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0 +/* + * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL + * + * I2C responds with an ACK + */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0 +/* The width in bits of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1 +/* Extracts the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL field value from a register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_ACK_GENERAL_CALL. + */ +struct ALT_I2C_ACK_GENERAL_CALL_s +{ + uint32_t ack_gen_call : 1; /* ACK General Call Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_ACK_GENERAL_CALL. */ +typedef volatile struct ALT_I2C_ACK_GENERAL_CALL_s ALT_I2C_ACK_GENERAL_CALL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_ACK_GENERAL_CALL register from the beginning of the component. */ +#define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98 +/* The address of the ALT_I2C_ACK_GENERAL_CALL register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST)) + +/* + * Register : Enable Status Register - ic_enable_status + * + * This register is used to report the i2c hardware status when the IC_ENABLE + * register is set from 1 to 0; that is, when i2c is disabled. If IC_ENABLE has + * been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE + * has been set to 0, bits 2:1 are only valid as soon as bit 0 is read as '0'. + * + * Note: When ic_enable has been written with '0' a delay occurs for bit 0 to be + * read as '0' because disabling the i2c depends on I2C bus activities. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | R | 0x0 | Enable Status Bit + * [1] | R | 0x0 | Slave Disabled While Busy Bit + * [2] | R | 0x0 | Slave Received Data Lost Bit + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable Status Bit - ic_en + * + * This bit always reflects the value driven on the output port ic_en. Not used in + * current application. When read as 1, i2c is deemed to be in an enabled state. + * When read as 0, i2c is deemed completely inactive. NOTE: The CPU can safely read + * this bit anytime. When this bit is read as 0, the CPU can safely read + * slv_rx_data_lost (bit 2) and slv_disabled_while_busy (bit 1). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_MSB 0 +/* The width in bits of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_IC_EN register field value. */ +#define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_EN_STAT_IC_EN register field value. */ +#define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_IC_EN field value from a register. */ +#define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_EN_STAT_IC_EN register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Slave Disabled While Busy Bit - slv_disabled_while_busy + * + * This bit indicates if a potential or active Slave operation has been aborted due + * to the setting of the ic_enable register from 1 to 0. This bit is set when the + * CPU writes a 0 to the ic_enable register while: (a) I2C is receiving the address + * byte of the Slave-Transmitter operation from a remote master; OR, (b) address + * and data bytes of the Slave-Receiver operation from a remote master. When read + * as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, + * irrespective of whether the I2C address matches the slave address set in i2c + * (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 + * but has not taken effect. NOTE: If the remote I2C master terminates the transfer + * with a STOP condition before the i2c has a chance to NACK a transfer, and + * IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as + * 0, i2c is deemed to have been disabled when there is master activity, or when + * the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) + * is read as 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1 +/* The width in bits of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY field value from a register. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Slave Received Data Lost Bit - slv_rx_data_lost + * + * This bit indicates if a Slave-Receiver operation has been aborted with at least + * one data byte received from an I2C transfer due to the setting of IC ENABLE from + * 1 to 0. When read as 1, i2c is deemed to have been actively engaged in an + * aborted I2C transfer (with matching address) and the data phase of the I2C + * transfer has been entered, even though a data byte has been responded with a + * NACK. NOTE: If the remote I2C master terminates the transfer with a STOP + * condition before the i2c has a chance to NACK a transfer, and ic_enable has been + * set to 0, then this bit is also set to 1. When read as 0, i2c is deemed to have + * been disabled without being actively involved in the data phase of a Slave- + * Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is + * read as 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2 +/* The width in bits of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST field value from a register. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_EN_STAT. + */ +struct ALT_I2C_EN_STAT_s +{ + const uint32_t ic_en : 1; /* Enable Status Bit */ + const uint32_t slv_disabled_while_busy : 1; /* Slave Disabled While Busy Bit */ + const uint32_t slv_rx_data_lost : 1; /* Slave Received Data Lost Bit */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_EN_STAT. */ +typedef volatile struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_EN_STAT register from the beginning of the component. */ +#define ALT_I2C_EN_STAT_OFST 0x9c +/* The address of the ALT_I2C_EN_STAT register. */ +#define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST)) + +/* + * Register : SS and FS Spike Suppression Limit Register - ic_fs_spklen + * + * This register is used to store the duration, measured in ic_clk cycles, of the + * longest spike that is filtered out by the spike suppression logic when the + * component is operating in SS or FS modes. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [7:0] | RW | 0x2 | Spike Suppression Limit Register + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Spike Suppression Limit Register - spklen + * + * This register must be set before any I2C bus transaction can take place to + * ensure stable operation. This register sets the duration, measured in ic_clk + * cycles, of the longest spike in the SCL or SDA lines that are filtered out by + * the spike suppression logic. This register can be written only when the I2C + * interface is disabled, which corresponds to the IC_ENABLE register being set to + * 0. Writes at other times have no effect. The minimum valid value is 1; hardware + * prevents values less than this being written, and if attempted results in 2 + * being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_MSB 7 +/* The width in bits of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_WIDTH 8 +/* The mask used to set the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_RESET 0x2 +/* Extracts the ALT_I2C_FS_SPKLEN_SPKLEN field value from a register. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_FS_SPKLEN_SPKLEN register field value suitable for setting the register. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SPKLEN. + */ +struct ALT_I2C_FS_SPKLEN_s +{ + uint32_t spklen : 8; /* Spike Suppression Limit Register */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SPKLEN. */ +typedef volatile struct ALT_I2C_FS_SPKLEN_s ALT_I2C_FS_SPKLEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SPKLEN register from the beginning of the component. */ +#define ALT_I2C_FS_SPKLEN_OFST 0xa0 +/* The address of the ALT_I2C_FS_SPKLEN register. */ +#define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST)) + +/* + * Register : Component Parameter Register 1 - ic_comp_param_1 + * + * This is a constant read-only register that contains encoded information about + * the component's parameter settings. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [1:0] | R | 0x2 | APB Data Width Register + * [3:2] | R | 0x2 | Max Speed Mode + * [4] | R | 0x0 | CNT Registers Access + * [5] | R | 0x1 | Intr IO + * [6] | R | 0x1 | Has DMA + * [7] | R | 0x1 | Add Encoded Params + * [15:8] | R | 0x3f | Rx Buffer Depth + * [23:16] | R | 0x3f | Tx Buffer Depth + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB Data Width Register - apb_data_width + * + * Sets the APB Data Width. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH + * + * APB Data Width is 32 Bits + */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2 +/* Extracts the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Max Speed Mode - max_speed_mode + * + * The value of this field determines the maximum i2c bus interface speed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------- + * ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST | 0x2 | Fast Mode (400 kbit/s) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD + * + * Fast Mode (400 kbit/s) + */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2 +/* Extracts the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : CNT Registers Access - hc_count_values + * + * This makes the *CNT registers readable and writable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR | 0x0 | *CNT registers read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES + * + * * CNT registers read/write + */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0 +/* Extracts the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Intr IO - intr_io + * + * All interrupt sources are combined in to a single output. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED | 0x1 | Combined Interrupt Output + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_INTR_IO + * + * Combined Interrupt Output + */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_INTR_IO field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_COMP_PARAM_1_INTR_IO register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Has DMA - has_dma + * + * This configures the inclusion of DMA handshaking interface signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------ + * ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT | 0x1 | Has DMA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HAS_DMA + * + * Has DMA + */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_HAS_DMA field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_COMP_PARAM_1_HAS_DMA register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Add Encoded Params - add_encoded_params + * + * By adding in the encoded parameters, this gives firmware an easy and quick way + * of identifying the DesignWare component within an I/O memory map. Some critical + * design-time options determine how a driver should interact with the peripheral. + * There is a minimal area overhead by including these parameters. Allows a single + * driver to be developed for each component which will be self-configurable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------- + * ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Add Encoded Params + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS + * + * Add Encoded Params + */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Rx Buffer Depth - rx_buffer_depth + * + * Sets Rx FIFO Depth. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------------- + * ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Rx Fifo Depth 64 Entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH + * + * Rx Fifo Depth 64 Entries + */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff +/* The reset value of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f +/* Extracts the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Tx Buffer Depth - tx_buffer_depth + * + * Sets Tx FIFO Depth. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Tx Buffer Depth 64 Entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH + * + * Tx Buffer Depth 64 Entries + */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff +/* The reset value of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f +/* Extracts the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_PARAM_1. + */ +struct ALT_I2C_COMP_PARAM_1_s +{ + const uint32_t apb_data_width : 2; /* APB Data Width Register */ + const uint32_t max_speed_mode : 2; /* Max Speed Mode */ + const uint32_t hc_count_values : 1; /* CNT Registers Access */ + const uint32_t intr_io : 1; /* Intr IO */ + const uint32_t has_dma : 1; /* Has DMA */ + const uint32_t add_encoded_params : 1; /* Add Encoded Params */ + const uint32_t rx_buffer_depth : 8; /* Rx Buffer Depth */ + const uint32_t tx_buffer_depth : 8; /* Tx Buffer Depth */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_PARAM_1. */ +typedef volatile struct ALT_I2C_COMP_PARAM_1_s ALT_I2C_COMP_PARAM_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_PARAM_1 register from the beginning of the component. */ +#define ALT_I2C_COMP_PARAM_1_OFST 0xf4 +/* The address of the ALT_I2C_COMP_PARAM_1 register. */ +#define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST)) + +/* + * Register : Component Version Register - ic_comp_version + * + * Describes the version of the I2C + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------------- + * [31:0] | R | 0x3132302a | Component Parameter Value + * + */ +/* + * Field : Component Parameter Value - ic_comp_version + * + * Specifies I2C release number (encoded as 4 ASCII characters) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:-----------|:-------------- + * ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A | 0x3132302a | Version 1.20a + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_VER_IC_COMP_VER + * + * Version 1.20a + */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A 0x3132302a + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31 +/* The width in bits of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32 +/* The mask used to set the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff +/* The mask used to clear the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000 +/* The reset value of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132302a +/* Extracts the ALT_I2C_COMP_VER_IC_COMP_VER field value from a register. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_I2C_COMP_VER_IC_COMP_VER register field value suitable for setting the register. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_VER. + */ +struct ALT_I2C_COMP_VER_s +{ + const uint32_t ic_comp_version : 32; /* Component Parameter Value */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_VER. */ +typedef volatile struct ALT_I2C_COMP_VER_s ALT_I2C_COMP_VER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_VER register from the beginning of the component. */ +#define ALT_I2C_COMP_VER_OFST 0xf8 +/* The address of the ALT_I2C_COMP_VER register. */ +#define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST)) + +/* + * Register : Component Type Register - ic_comp_type + * + * Describes a unique ASCII value + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | R | 0x44570140 | Component Type Number + * + */ +/* + * Field : Component Type Number - ic_comp_type + * + * Designware Component Type number = 0x44_57_01_40. This assigned unique hex value + * is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit + * unsigned number. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31 +/* The width in bits of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32 +/* The mask used to set the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000 +/* The reset value of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140 +/* Extracts the ALT_I2C_COMP_TYPE_IC_COMP_TYPE field value from a register. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value suitable for setting the register. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_TYPE. + */ +struct ALT_I2C_COMP_TYPE_s +{ + const uint32_t ic_comp_type : 32; /* Component Type Number */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_TYPE. */ +typedef volatile struct ALT_I2C_COMP_TYPE_s ALT_I2C_COMP_TYPE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_TYPE register from the beginning of the component. */ +#define ALT_I2C_COMP_TYPE_OFST 0xfc +/* The address of the ALT_I2C_COMP_TYPE register. */ +#define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_I2C. + */ +struct ALT_I2C_s +{ + volatile ALT_I2C_CON_t ic_con; /* ALT_I2C_CON */ + volatile ALT_I2C_TAR_t ic_tar; /* ALT_I2C_TAR */ + volatile ALT_I2C_SAR_t ic_sar; /* ALT_I2C_SAR */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_I2C_DATA_CMD_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ + volatile ALT_I2C_SS_SCL_HCNT_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ + volatile ALT_I2C_SS_SCL_LCNT_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ + volatile ALT_I2C_FS_SCL_HCNT_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ + volatile ALT_I2C_FS_SCL_LCNT_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ + volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ + volatile ALT_I2C_INTR_STAT_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ + volatile ALT_I2C_INTR_MSK_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ + volatile ALT_I2C_RAW_INTR_STAT_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ + volatile ALT_I2C_RX_TL_t ic_rx_tl; /* ALT_I2C_RX_TL */ + volatile ALT_I2C_TX_TL_t ic_tx_tl; /* ALT_I2C_TX_TL */ + volatile ALT_I2C_CLR_INTR_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ + volatile ALT_I2C_CLR_RX_UNDER_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ + volatile ALT_I2C_CLR_RX_OVER_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ + volatile ALT_I2C_CLR_TX_OVER_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ + volatile ALT_I2C_CLR_RD_REQ_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ + volatile ALT_I2C_CLR_TX_ABRT_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ + volatile ALT_I2C_CLR_RX_DONE_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ + volatile ALT_I2C_CLR_ACTIVITY_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ + volatile ALT_I2C_CLR_STOP_DET_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ + volatile ALT_I2C_CLR_START_DET_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ + volatile ALT_I2C_CLR_GEN_CALL_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ + volatile ALT_I2C_EN_t ic_enable; /* ALT_I2C_EN */ + volatile ALT_I2C_STAT_t ic_status; /* ALT_I2C_STAT */ + volatile ALT_I2C_TXFLR_t ic_txflr; /* ALT_I2C_TXFLR */ + volatile ALT_I2C_RXFLR_t ic_rxflr; /* ALT_I2C_RXFLR */ + volatile ALT_I2C_SDA_HOLD_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ + volatile ALT_I2C_TX_ABRT_SRC_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ + volatile ALT_I2C_SLV_DATA_NACK_ONLY_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ + volatile ALT_I2C_DMA_CR_t ic_dma_cr; /* ALT_I2C_DMA_CR */ + volatile ALT_I2C_DMA_TDLR_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ + volatile ALT_I2C_DMA_RDLR_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ + volatile ALT_I2C_SDA_SETUP_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ + volatile ALT_I2C_ACK_GENERAL_CALL_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ + volatile ALT_I2C_EN_STAT_t ic_enable_status; /* ALT_I2C_EN_STAT */ + volatile ALT_I2C_FS_SPKLEN_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ + volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ + volatile ALT_I2C_COMP_PARAM_1_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ + volatile ALT_I2C_COMP_VER_t ic_comp_version; /* ALT_I2C_COMP_VER */ + volatile ALT_I2C_COMP_TYPE_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ +}; + +/* The typedef declaration for register group ALT_I2C. */ +typedef volatile struct ALT_I2C_s ALT_I2C_t; +/* The struct declaration for the raw register contents of register group ALT_I2C. */ +struct ALT_I2C_raw_s +{ + volatile uint32_t ic_con; /* ALT_I2C_CON */ + volatile uint32_t ic_tar; /* ALT_I2C_TAR */ + volatile uint32_t ic_sar; /* ALT_I2C_SAR */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ + volatile uint32_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ + volatile uint32_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ + volatile uint32_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ + volatile uint32_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ + volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ + volatile uint32_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ + volatile uint32_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ + volatile uint32_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ + volatile uint32_t ic_rx_tl; /* ALT_I2C_RX_TL */ + volatile uint32_t ic_tx_tl; /* ALT_I2C_TX_TL */ + volatile uint32_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ + volatile uint32_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ + volatile uint32_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ + volatile uint32_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ + volatile uint32_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ + volatile uint32_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ + volatile uint32_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ + volatile uint32_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ + volatile uint32_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ + volatile uint32_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ + volatile uint32_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ + volatile uint32_t ic_enable; /* ALT_I2C_EN */ + volatile uint32_t ic_status; /* ALT_I2C_STAT */ + volatile uint32_t ic_txflr; /* ALT_I2C_TXFLR */ + volatile uint32_t ic_rxflr; /* ALT_I2C_RXFLR */ + volatile uint32_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ + volatile uint32_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ + volatile uint32_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ + volatile uint32_t ic_dma_cr; /* ALT_I2C_DMA_CR */ + volatile uint32_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ + volatile uint32_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ + volatile uint32_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ + volatile uint32_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ + volatile uint32_t ic_enable_status; /* ALT_I2C_EN_STAT */ + volatile uint32_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ + volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ + volatile uint32_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ + volatile uint32_t ic_comp_version; /* ALT_I2C_COMP_VER */ + volatile uint32_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_I2C. */ +typedef volatile struct ALT_I2C_raw_s ALT_I2C_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_I2C_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_i2c.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_i2c.c new file mode 100644 index 0000000..1519f4f --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_i2c.c @@ -0,0 +1,2004 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_i2c.h" +#include "alt_reset_manager.h" +#include + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) + +///// + +#define MIN(a, b) ((a) > (b) ? (b) : (a)) + +///// + +// Timeout for reset manager +#define ALT_I2C_RESET_TMO_INIT 8192 +// Timeout for disable device +#define ALT_I2C_MAX_T_POLL_COUNT 8192 +// Timeout for waiting interrupt +#define ALT_I2C_TMO_WAITER 2500000 + +// Min frequency during standard speed +#define ALT_I2C_SS_MIN_SPEED 8000 +// Max frequency during standard speed +#define ALT_I2C_SS_MAX_SPEED 100000 +// Min frequency during fast speed +#define ALT_I2C_FS_MIN_SPEED 100000 +// Max frequency during fast speed +#define ALT_I2C_FS_MAX_SPEED 400000 +// Default spike suppression limit during standard speed +#define ALT_I2C_SS_DEFAULT_SPKLEN 11 +// Default spike suppression limit during fast speed +#define ALT_I2C_FS_DEFAULT_SPKLEN 4 + +// Diff between SCL LCNT and SCL HCNT +#define ALT_I2C_DIFF_LCNT_HCNT 70 + +// Reserved address from 0x00 to 0x07 +#define ALT_I2C_SLV_RESERVE_ADDR_S_1 0x00 +#define ALT_I2C_SLV_RESERVE_ADDR_F_1 0x07 +// Reserved address from 0x78 to 0x7F +#define ALT_I2C_SLV_RESERVE_ADDR_S_2 0x78 +#define ALT_I2C_SLV_RESERVE_ADDR_F_2 0x7F + +static ALT_STATUS_CODE alt_i2c_is_enabled_helper(ALT_I2C_DEV_t * i2c_dev); + +// +// Check whether i2c space is correct. +// +static ALT_STATUS_CODE alt_i2c_checking(ALT_I2C_DEV_t * i2c_dev) +{ + if ( (i2c_dev->location != (void *)ALT_I2C_I2C0) + && (i2c_dev->location != (void *)ALT_I2C_I2C1) + && (i2c_dev->location != (void *)ALT_I2C_I2C2) + && (i2c_dev->location != (void *)ALT_I2C_I2C3)) + { + // Incorrect device + return ALT_E_FALSE; + } + + // Reset i2c module + return ALT_E_TRUE; +} + +static ALT_STATUS_CODE alt_i2c_rstmgr_set(ALT_I2C_DEV_t * i2c_dev) +{ + uint32_t rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + + // Assert the appropriate I2C module reset signal via the Reset Manager Peripheral Reset register. + switch ((ALT_I2C_CTLR_t)i2c_dev->location) + { + case ALT_I2C_I2C0: + rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + break; + case ALT_I2C_I2C1: + rst_mask = ALT_RSTMGR_PERMODRST_I2C1_SET_MSK; + break; + case ALT_I2C_I2C2: + rst_mask = ALT_RSTMGR_PERMODRST_I2C2_SET_MSK; + break; + case ALT_I2C_I2C3: + rst_mask = ALT_RSTMGR_PERMODRST_I2C3_SET_MSK; + break; + default: + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + return ALT_E_SUCCESS; +} + +// +// Reset i2c module by reset manager +// +static ALT_STATUS_CODE alt_i2c_rstmgr_strobe(ALT_I2C_DEV_t * i2c_dev) +{ + uint32_t rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + + // Assert the appropriate I2C module reset signal via the Reset Manager Peripheral Reset register. + switch ((ALT_I2C_CTLR_t)i2c_dev->location) + { + case ALT_I2C_I2C0: + rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + break; + case ALT_I2C_I2C1: + rst_mask = ALT_RSTMGR_PERMODRST_I2C1_SET_MSK; + break; + case ALT_I2C_I2C2: + rst_mask = ALT_RSTMGR_PERMODRST_I2C2_SET_MSK; + break; + case ALT_I2C_I2C3: + rst_mask = ALT_RSTMGR_PERMODRST_I2C3_SET_MSK; + break; + default: + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + volatile uint32_t timeout = ALT_I2C_RESET_TMO_INIT; + + // Wait while i2c modure is reseting + while (--timeout) + ; + + // Deassert the appropriate I2C module reset signal via the Reset Manager Peripheral Reset register. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + return ALT_E_SUCCESS; +} + +// +// Initialize the specified I2C controller instance for use and return a device +// handle referencing it. +// +ALT_STATUS_CODE alt_i2c_init(const ALT_I2C_CTLR_t i2c, + ALT_I2C_DEV_t * i2c_dev) +{ + // Save i2c start address to the instance + i2c_dev->location = (void *)i2c; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_clk_is_enabled(ALT_CLK_L4_SP) != ALT_E_TRUE) + { + return ALT_E_BAD_CLK; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_clk_freq_get(ALT_CLK_L4_SP, &i2c_dev->clock_freq); + } + + // Reset i2c module + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_reset(i2c_dev); + } + + return status; +} + +// +// Reset i2c module +// +ALT_STATUS_CODE alt_i2c_reset(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + // Reset i2c module by reset manager + alt_i2c_rstmgr_strobe(i2c_dev); + + // Set optimal parameters for all i2c devices on the bus + ALT_I2C_MASTER_CONFIG_t cfg; + cfg.addr_mode = ALT_I2C_ADDR_MODE_7_BIT; + cfg.speed_mode = ALT_I2C_SPEED_STANDARD; + cfg.fs_spklen = ALT_I2C_SS_DEFAULT_SPKLEN; + cfg.restart_enable = ALT_E_TRUE; + cfg.ss_scl_lcnt = cfg.fs_scl_lcnt = 0x2FB; + cfg.ss_scl_hcnt = cfg.fs_scl_hcnt = 0x341; + + alt_i2c_master_config_set(i2c_dev, &cfg); + + // Active master mode + alt_i2c_op_mode_set(i2c_dev, ALT_I2C_MODE_MASTER); + + // Reset the last target address cache. + i2c_dev->last_target = 0xffffffff; + + // Clear interrupts mask and clear interrupt status. + // Interrupts are unmasked by default. + alt_i2c_int_disable(i2c_dev, ALT_I2C_STATUS_INT_ALL); + alt_i2c_int_clear(i2c_dev, ALT_I2C_STATUS_INT_ALL); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Uninitialize the I2C controller referenced by the i2c_dev handle. +// +ALT_STATUS_CODE alt_i2c_uninit(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Disable i2c controller + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_disable(i2c_dev); + } + + // Reset i2c module by reset manager + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_rstmgr_set(i2c_dev); + } + + return status; +} + +// +// Enables the I2C controller. +// +ALT_STATUS_CODE alt_i2c_enable(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // Enable DMA by default. + alt_write_word(ALT_I2C_DMA_CR_ADDR(i2c_dev->location), + ALT_I2C_DMA_CR_TDMAE_SET_MSK | ALT_I2C_DMA_CR_RDMAE_SET_MSK); + + alt_setbits_word(ALT_I2C_EN_ADDR(i2c_dev->location), ALT_I2C_EN_EN_SET_MSK); + + return ALT_E_SUCCESS; +} + +// +// Disables the I2C controller +// +ALT_STATUS_CODE alt_i2c_disable(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // If i2c controller is enabled, return with sucess + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_SUCCESS; + } + + // Else clear enable bit of i2c_enable register + alt_clrbits_word(ALT_I2C_EN_ADDR(i2c_dev->location), ALT_I2C_EN_EN_SET_MSK); + + uint32_t timeout = ALT_I2C_MAX_T_POLL_COUNT; + + // Wait to complete all transfer operations or timeout + while (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE) + { + // If controller still are active, return timeout error + if (--timeout == 0) + { + return ALT_E_TMO; + } + } + + // Clear interrupt status + alt_i2c_int_clear(i2c_dev, ALT_I2C_STATUS_INT_ALL); + + return ALT_E_SUCCESS; +} + +// +// Check whether i2c controller is enable +// +static ALT_STATUS_CODE alt_i2c_is_enabled_helper(ALT_I2C_DEV_t * i2c_dev) +{ + if (ALT_I2C_EN_STAT_IC_EN_GET(alt_read_word(ALT_I2C_EN_STAT_ADDR(i2c_dev->location)))) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +ALT_STATUS_CODE alt_i2c_is_enabled(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + return alt_i2c_is_enabled_helper(i2c_dev); +} + +// +// Get config parameters from appropriate registers for master mode. +// +ALT_STATUS_CODE alt_i2c_master_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t cfg_register = alt_read_word(ALT_I2C_CON_ADDR(i2c_dev->location)); + uint32_t tar_register = alt_read_word(ALT_I2C_TAR_ADDR(i2c_dev->location)); + uint32_t spkl_register = alt_read_word(ALT_I2C_FS_SPKLEN_ADDR(i2c_dev->location)); + + cfg->speed_mode = (ALT_I2C_SPEED_t)ALT_I2C_CON_SPEED_GET(cfg_register); + cfg->fs_spklen = ALT_I2C_FS_SPKLEN_SPKLEN_GET(spkl_register); + cfg->restart_enable = ALT_I2C_CON_IC_RESTART_EN_GET(cfg_register); + cfg->addr_mode = (ALT_I2C_ADDR_MODE_t)ALT_I2C_TAR_IC_10BITADDR_MST_GET(tar_register); + + cfg->ss_scl_lcnt = alt_read_word(ALT_I2C_SS_SCL_LCNT_ADDR(i2c_dev->location)); + cfg->ss_scl_hcnt = alt_read_word(ALT_I2C_SS_SCL_HCNT_ADDR(i2c_dev->location)); + cfg->fs_scl_lcnt = alt_read_word(ALT_I2C_FS_SCL_LCNT_ADDR(i2c_dev->location)); + cfg->fs_scl_hcnt = alt_read_word(ALT_I2C_FS_SCL_HCNT_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +// +// Set config parameters to appropriate registers for master mode. +// +ALT_STATUS_CODE alt_i2c_master_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->speed_mode != ALT_I2C_SPEED_STANDARD) + && (cfg->speed_mode != ALT_I2C_SPEED_FAST)) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->addr_mode != ALT_I2C_ADDR_MODE_7_BIT) + && (cfg->addr_mode != ALT_I2C_ADDR_MODE_10_BIT)) + { + return ALT_E_ARG_RANGE; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + // Set config parameters to appropriate registers + + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_SPEED_SET_MSK | ALT_I2C_CON_IC_RESTART_EN_SET_MSK, + ALT_I2C_CON_SPEED_SET(cfg->speed_mode) | ALT_I2C_CON_IC_RESTART_EN_SET(cfg->restart_enable)); + + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK, + ALT_I2C_TAR_IC_10BITADDR_MST_SET(cfg->addr_mode)); + + alt_replbits_word(ALT_I2C_FS_SPKLEN_ADDR(i2c_dev->location), + ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK, + ALT_I2C_FS_SPKLEN_SPKLEN_SET(cfg->fs_spklen)); + + alt_replbits_word(ALT_I2C_SS_SCL_LCNT_ADDR(i2c_dev->location), + ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK, + ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(cfg->ss_scl_lcnt)); + alt_replbits_word(ALT_I2C_SS_SCL_HCNT_ADDR(i2c_dev->location), + ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK, + ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(cfg->ss_scl_hcnt)); + alt_replbits_word(ALT_I2C_FS_SCL_LCNT_ADDR(i2c_dev->location), + ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK, + ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(cfg->fs_scl_lcnt)); + alt_replbits_word(ALT_I2C_FS_SCL_HCNT_ADDR(i2c_dev->location), + ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK, + ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(cfg->fs_scl_hcnt)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Return bus speed by configuration of i2c controller for master mode. +// +ALT_STATUS_CODE alt_i2c_master_config_speed_get(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t * cfg, + uint32_t * speed_in_hz) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t scl_lcnt = (cfg->speed_mode == ALT_I2C_SPEED_STANDARD) ? cfg->ss_scl_lcnt : cfg->fs_scl_lcnt; + + if (scl_lcnt == 0) + { + return ALT_E_BAD_ARG; + } + + *speed_in_hz = i2c_dev->clock_freq / (scl_lcnt << 1); + + return ALT_E_SUCCESS; +} + +// +// Fill struct with configuration of i2c controller for master mode by bus speed +// +ALT_STATUS_CODE alt_i2c_master_config_speed_set(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t * cfg, + uint32_t speed_in_hz) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // If speed is not standard or fast return range error + if ((speed_in_hz > ALT_I2C_FS_MAX_SPEED) || (speed_in_hz < ALT_I2C_SS_MIN_SPEED)) + { + return ALT_E_ARG_RANGE; + } + + if (speed_in_hz > ALT_I2C_FS_MIN_SPEED) + { + cfg->speed_mode = ALT_I2C_SPEED_FAST; + cfg->fs_spklen = ALT_I2C_FS_DEFAULT_SPKLEN; + } + else + { + cfg->speed_mode = ALT_I2C_SPEED_STANDARD; + cfg->fs_spklen = ALT_I2C_SS_DEFAULT_SPKLEN; + } + + // = / 2 * + uint32_t scl_lcnt = i2c_dev->clock_freq / (speed_in_hz << 1); + + cfg->ss_scl_lcnt = cfg->fs_scl_lcnt = scl_lcnt; + // hcount = + 70 + cfg->ss_scl_hcnt = cfg->fs_scl_hcnt = scl_lcnt - ALT_I2C_DIFF_LCNT_HCNT; + + // lcount = / 2 * + + return ALT_E_SUCCESS; +} + +// +// Get config parameters from appropriate registers for slave mode. +// +ALT_STATUS_CODE alt_i2c_slave_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_SLAVE_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t cfg_register = alt_read_word(ALT_I2C_CON_ADDR(i2c_dev->location)); + uint32_t sar_register = alt_read_word(ALT_I2C_SAR_ADDR(i2c_dev->location)); + uint32_t nack_register = alt_read_word(ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(i2c_dev->location)); + + cfg->addr_mode = (ALT_I2C_ADDR_MODE_t)ALT_I2C_CON_IC_10BITADDR_SLV_GET(cfg_register); + cfg->addr = ALT_I2C_SAR_IC_SAR_GET(sar_register); + cfg->nack_enable = ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(nack_register); + + return ALT_E_SUCCESS; +} + +// +// Set config parameters to appropriate registers for slave mode. +// +ALT_STATUS_CODE alt_i2c_slave_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_SLAVE_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->addr_mode != ALT_I2C_ADDR_MODE_7_BIT) + && (cfg->addr_mode != ALT_I2C_ADDR_MODE_10_BIT)) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->addr > ALT_I2C_SAR_IC_SAR_SET_MSK) + || (cfg->addr < ALT_I2C_SLV_RESERVE_ADDR_F_1) + || ((cfg->addr > ALT_I2C_SLV_RESERVE_ADDR_S_2) && (cfg->addr < ALT_I2C_SLV_RESERVE_ADDR_F_2)) + ) + { + return ALT_E_ARG_RANGE; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK, + ALT_I2C_CON_IC_10BITADDR_SLV_SET(cfg->addr_mode)); + + alt_replbits_word(ALT_I2C_SAR_ADDR(i2c_dev->location), + ALT_I2C_SAR_IC_SAR_SET_MSK, + ALT_I2C_SAR_IC_SAR_SET(cfg->addr)); + alt_replbits_word(ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(i2c_dev->location), + ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK, + ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(cfg->nack_enable)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Get hold time (use during slave mode) +// +ALT_STATUS_CODE alt_i2c_sda_hold_time_get(ALT_I2C_DEV_t *i2c_dev, + uint16_t *hold_time) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t sda_register = alt_read_word(ALT_I2C_SDA_HOLD_ADDR(i2c_dev->location)); + *hold_time = ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(sda_register); + + return ALT_E_SUCCESS; +} + +// +// Set hold time (use during slave mode) +// +ALT_STATUS_CODE alt_i2c_sda_hold_time_set(ALT_I2C_DEV_t *i2c_dev, + const uint16_t hold_time) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_SDA_HOLD_ADDR(i2c_dev->location), + ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK, + ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(hold_time)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Gets the current operational mode of the I2C controller. +// +ALT_STATUS_CODE alt_i2c_op_mode_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MODE_t* mode) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t cfg_register = alt_read_word(ALT_I2C_CON_ADDR(i2c_dev->location)); + uint32_t mst_mod_stat = ALT_I2C_CON_MST_MOD_GET(cfg_register); + uint32_t slv_mod_stat = ALT_I2C_CON_IC_SLV_DIS_GET(cfg_register); + + // Return error if master and slave modes enable or disable at the same time + if ( (mst_mod_stat == ALT_I2C_CON_MST_MOD_E_EN && slv_mod_stat == ALT_I2C_CON_IC_SLV_DIS_E_EN) + || (mst_mod_stat == ALT_I2C_CON_MST_MOD_E_DIS && slv_mod_stat == ALT_I2C_CON_IC_SLV_DIS_E_DIS)) + { + return ALT_E_ERROR; + } + + *mode = (ALT_I2C_MODE_t)mst_mod_stat; + + return ALT_E_SUCCESS; +} + +// +// Sets the operational mode of the I2C controller. +// +ALT_STATUS_CODE alt_i2c_op_mode_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MODE_t mode) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( (mode != ALT_I2C_MODE_MASTER) + && (mode != ALT_I2C_MODE_SLAVE)) + { + return ALT_E_ARG_RANGE; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + if (mode == ALT_I2C_MODE_MASTER) + { + // Enable master, disable slave + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_IC_SLV_DIS_SET_MSK | ALT_I2C_CON_MST_MOD_SET_MSK, + ALT_I2C_CON_IC_SLV_DIS_SET(ALT_I2C_CON_IC_SLV_DIS_E_DIS) | ALT_I2C_CON_MST_MOD_SET(ALT_I2C_CON_MST_MOD_E_EN)); + } + else if (mode == ALT_I2C_MODE_SLAVE) + { + // Enable slave, disable master + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_IC_SLV_DIS_SET_MSK | ALT_I2C_CON_MST_MOD_SET_MSK, + ALT_I2C_CON_IC_SLV_DIS_SET(ALT_I2C_CON_IC_SLV_DIS_E_EN) | ALT_I2C_CON_MST_MOD_SET(ALT_I2C_CON_MST_MOD_E_DIS)); + } + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Returns ALT_E_TRUE if the I2C controller is busy +// +ALT_STATUS_CODE alt_i2c_is_busy(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( ALT_I2C_STAT_ACTIVITY_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location)))) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// This function reads a single data byte from the receive FIFO. +// +ALT_STATUS_CODE alt_i2c_read(ALT_I2C_DEV_t *i2c_dev, uint8_t *value) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + *value = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + + return ALT_E_SUCCESS; +} + +// +// This function writes a single data byte to the transmit FIFO. +// +ALT_STATUS_CODE alt_i2c_write(ALT_I2C_DEV_t *i2c_dev, const uint8_t value) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(value)); + + return ALT_E_SUCCESS; +} + +// +// This function acts in the role of a slave-receiver by receiving a single data +// byte from the I2C bus in response to a write command from the master. +// +ALT_STATUS_CODE alt_i2c_slave_receive(ALT_I2C_DEV_t * i2c_dev, + uint8_t * data) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + // alt_i2c_read(). + *data = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + + return ALT_E_SUCCESS; +} + +// +// This function acts in the role of a slave-transmitter by transmitting a single +// data byte to the I2C bus in response to a read request from the master. +// +ALT_STATUS_CODE alt_i2c_slave_transmit(ALT_I2C_DEV_t *i2c_dev, + const uint8_t data) +{ + // Send bulk of data with one value + return alt_i2c_slave_bulk_transmit(i2c_dev, &data, 1); +} + +// +// This function acts in the role of a slave-transmitter by transmitting data in +// bulk to the I2C bus in response to a series of read requests from a master. +// +ALT_STATUS_CODE alt_i2c_slave_bulk_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + const char * buffer = data; + for (size_t i = 0; i < size; ++i) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(*buffer) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + + ++buffer; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_master_target_get(ALT_I2C_DEV_t * i2c_dev, uint32_t * target_addr) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *target_addr = i2c_dev->last_target; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_master_target_set(ALT_I2C_DEV_t * i2c_dev, uint32_t target_addr) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Wait until the TX FIFO flushes. This is needed because TAR can only be + // updated under specific conditions. + + if (target_addr != i2c_dev->last_target) + { + uint32_t timeout = 10000; + + while (alt_i2c_tx_fifo_is_empty(i2c_dev) == ALT_E_FALSE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + + // Update target address + if (status == ALT_E_SUCCESS) + { + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_IC_TAR_SET_MSK, + ALT_I2C_TAR_IC_TAR_SET(target_addr)); + + i2c_dev->last_target = target_addr; + } + } + + return status; +} + +// +// Write bulk of data or read requests to tx fifo +// +static ALT_STATUS_CODE alt_i2c_master_transmit_helper(ALT_I2C_DEV_t * i2c_dev, + const uint8_t * buffer, + size_t size, + bool issue_restart, + bool issue_stop) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the rested size is 1, the restart and stop may need to be sent in the + // same frame. + if (size == 1) + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_issue_write(i2c_dev, + *buffer, + issue_restart, + issue_stop); + + ++buffer; + --size; + } + } + else + { + // First byte + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_issue_write(i2c_dev, + *buffer, + issue_restart, + false); + + ++buffer; + --size; + } + + ///// + + // Middle byte(s) + + if (status == ALT_E_SUCCESS) + { + uint32_t timeout = size * 10000; + + while (size > 1) + { + uint32_t level = 0; + status = alt_i2c_tx_fifo_level_get(i2c_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t space = ALT_I2C_TX_FIFO_NUM_ENTRIES - level; + if (space == 0) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + + continue; + } + + // Subtract 1 because the last byte may need to issue_stop + space = MIN(space, size - 1); + + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(*buffer) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + + ++buffer; + } + + size -= space; + } + } + + ///// + + // Last byte + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_issue_write(i2c_dev, + *buffer, + false, + issue_stop); + + ++buffer; + --size; + } + } + + return status; +} + +// +// This function acts in the role of a master-transmitter by issuing a write +// command and transmitting data to the I2C bus. +// +ALT_STATUS_CODE alt_i2c_master_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_transmit_helper(i2c_dev, + data, + size, + issue_restart, + issue_stop); + } + + // Need reset for set i2c bus in idle state + if (status == ALT_E_TMO) + { + alt_i2c_reset(i2c_dev); + } + + return status; +} + +ALT_STATUS_CODE alt_i2c_master_receive_helper(ALT_I2C_DEV_t *i2c_dev, + uint8_t * buffer, + size_t size, + bool issue_restart, + bool issue_stop) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t issue_left = size; + uint32_t data_left = size; + + uint32_t timeout = size * 10000; + + // Wait for space in the TX FIFO to send the first read request. + // This is needed because the issue restart need to be set. + + if (issue_restart == true) + { + if (status == ALT_E_SUCCESS) + { + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + } + + // Now send the first request. + + if (status == ALT_E_SUCCESS) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + --issue_left; + } + } + + // For the rest of the data ... + + while (data_left > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + // Top up the TX FIFO with read issues + // Special consideration must be made for the last read issue, as it may be necessary to "issue_stop". + + if (issue_left > 0) + { + uint32_t level = 0; + status = alt_i2c_tx_fifo_level_get(i2c_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t space = ALT_I2C_TX_FIFO_NUM_ENTRIES - level; + + if (issue_left == 1) + { + if (space > 0) + { + space = 1; + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + } + } + else + { + // Send up to issue_left - 1, as the last issue has special considerations. + space = MIN(issue_left - 1, space); + + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + } + } + + issue_left -= space; + } + + // Read out the resulting received data as they come in. + + if (data_left > 0) + { + uint32_t level = 0; + status = alt_i2c_rx_fifo_level_get(i2c_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + if (level == 0) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + + level = MIN(data_left, level); + + for (uint32_t i = 0; i < level; ++i) + { + // alt_i2c_read(i2c_dev, &value); + *buffer = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + ++buffer; + } + + data_left -= level; + } + } + + + return status; +} + +// +// This function acts in the role of a master-receiver by receiving one or more +// data bytes transmitted from a slave in response to read requests issued from +// this master. +// +ALT_STATUS_CODE alt_i2c_master_receive(ALT_I2C_DEV_t *i2c_dev, + void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // This I2C controller requires that a read issue be performed for each byte requested. + // Read issue takes space in the TX FIFO, which may asynchronously handling a previous request. + + if (size == 1) + { + uint32_t timeout = 10000; + + // Wait for space in the TX FIFO to send the read request. + + if (status == ALT_E_SUCCESS) + { + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + } + + // Issue the read request in the TX FIFO. + + if (status == ALT_E_SUCCESS) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + } + + // Wait for data to become available in the RX FIFO. + + if (status == ALT_E_SUCCESS) + { + while (alt_i2c_rx_fifo_is_empty(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + } + + // Read the RX FIFO. + + if (status == ALT_E_SUCCESS) + { + uint8_t * buffer = data; + *buffer = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + } + } + else if (size <= 64) + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + data, + size, + issue_restart, + issue_stop); + } + } + else + { + uint8_t * buffer = data; + size_t size_left = size; + + // Send the first ALT_I2C_RX_FIFO_NUM_ENTRIES items + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + buffer, + ALT_I2C_RX_FIFO_NUM_ENTRIES, + issue_restart, + false); + } + + buffer += ALT_I2C_RX_FIFO_NUM_ENTRIES; + size_left -= ALT_I2C_RX_FIFO_NUM_ENTRIES; + + while (size_left > 0) + { + if (size_left > ALT_I2C_RX_FIFO_NUM_ENTRIES) + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + buffer, + ALT_I2C_RX_FIFO_NUM_ENTRIES, + false, + false); + } + + buffer += ALT_I2C_RX_FIFO_NUM_ENTRIES; + size_left -= ALT_I2C_RX_FIFO_NUM_ENTRIES; + } + else + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + buffer, + size_left, + false, + issue_stop); + } + + size_left = 0; + } + + if (status != ALT_E_SUCCESS) + { + break; + } + } + } + + // Need reset for set i2c bus in idle state + if (status == ALT_E_TMO) + { + alt_i2c_reset(i2c_dev); + } + + return status; +} + +// +// This function causes the I2C controller master to send data to the bus. +// +ALT_STATUS_CODE alt_i2c_issue_write(ALT_I2C_DEV_t *i2c_dev, + const uint8_t value, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + // Wait until there is a FIFO spot + uint32_t timeout = 10000; + + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + return ALT_E_TMO; + } + } + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(value) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + return ALT_E_SUCCESS; +} + +// +// This function causes the I2C controller master to issue a READ request on the bus. +// +ALT_STATUS_CODE alt_i2c_issue_read(ALT_I2C_DEV_t *i2c_dev, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + // Wait until there is a FIFO spot + uint32_t timeout = 10000; + + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + return ALT_E_TMO; + } + } + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + return ALT_E_SUCCESS; +} + +// +// This function acts in the role of a master-transmitter by issuing a general +// call command to all devices connected to the I2C bus. +// +ALT_STATUS_CODE alt_i2c_master_general_call(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_target_set(i2c_dev, 0); + } + + // General call is a transmit in master mode (target address are not used during it) + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_transmit(i2c_dev, data, size, issue_restart, issue_stop); + } + + return status; +} + +///// + +ALT_STATUS_CODE alt_i2c_general_call_ack_disable(ALT_I2C_DEV_t *i2c_dev) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_SPECIAL_SET_MSK | ALT_I2C_TAR_GC_OR_START_SET_MSK, + ALT_I2C_TAR_SPECIAL_SET(ALT_I2C_TAR_SPECIAL_E_STARTBYTE) | ALT_I2C_TAR_GC_OR_START_SET(ALT_I2C_TAR_GC_OR_START_E_STARTBYTE)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Enables the I2C controller to respond with an ACK when it receives a General +// Call address. +// +ALT_STATUS_CODE alt_i2c_general_call_ack_enable(ALT_I2C_DEV_t *i2c_dev) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_SPECIAL_SET_MSK | ALT_I2C_TAR_GC_OR_START_SET_MSK, + ALT_I2C_TAR_SPECIAL_SET(ALT_I2C_TAR_SPECIAL_E_GENCALL) | ALT_I2C_TAR_GC_OR_START_SET(ALT_I2C_TAR_GC_OR_START_E_GENCALL)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Returns ALT_E_TRUE if the I2C controller is enabled to respond to General Call +// addresses. +// +ALT_STATUS_CODE alt_i2c_general_call_ack_is_enabled(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t tar_register = alt_read_word(ALT_I2C_TAR_ADDR(i2c_dev->location)); + + if ( (ALT_I2C_TAR_SPECIAL_GET(tar_register) == ALT_I2C_TAR_SPECIAL_E_GENCALL) + && (ALT_I2C_TAR_GC_OR_START_GET(tar_register) == ALT_I2C_TAR_GC_OR_START_E_GENCALL) + ) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns the current I2C controller interrupt status conditions. +// +ALT_STATUS_CODE alt_i2c_int_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *status = alt_read_word(ALT_I2C_INTR_STAT_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +// +// Returns the I2C controller raw interrupt status conditions irrespective of +// the interrupt status condition enablement state. +// +ALT_STATUS_CODE alt_i2c_int_raw_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *status = alt_read_word(ALT_I2C_RAW_INTR_STAT_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +// +// Clears the specified I2C controller interrupt status conditions identified +// in the mask. +// +ALT_STATUS_CODE alt_i2c_int_clear(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (mask == ALT_I2C_STATUS_INT_ALL) + { + alt_read_word(ALT_I2C_CLR_INTR_ADDR(i2c_dev->location)); + return ALT_E_SUCCESS; + } + + // For different status clear different register + + if (mask & ALT_I2C_STATUS_RX_UNDER) + { + alt_read_word(ALT_I2C_CLR_RX_UNDER_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_RX_OVER) + { + alt_read_word(ALT_I2C_CLR_RX_OVER_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_TX_OVER) + { + alt_read_word(ALT_I2C_CLR_TX_OVER_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_RD_REQ) + { + alt_read_word(ALT_I2C_CLR_RD_REQ_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_TX_ABORT) + { + alt_read_word(ALT_I2C_CLR_TX_ABRT_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_RX_DONE) + { + alt_read_word(ALT_I2C_CLR_RX_DONE_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_ACTIVITY) + { + alt_read_word(ALT_I2C_CLR_ACTIVITY_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_STOP_DET) + { + alt_read_word(ALT_I2C_CLR_STOP_DET_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_START_DET) + { + alt_read_word(ALT_I2C_CLR_START_DET_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_INT_CALL) + { + alt_read_word(ALT_I2C_CLR_GEN_CALL_ADDR(i2c_dev->location)); + } + + return ALT_E_SUCCESS; +} + +// +// Disable the specified I2C controller interrupt status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_i2c_int_disable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + alt_clrbits_word(ALT_I2C_INTR_MSK_ADDR(i2c_dev->location), mask); + + return ALT_E_SUCCESS; +} + +// +// Enable the specified I2C controller interrupt status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_i2c_int_enable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_I2C_INTR_MSK_ADDR(i2c_dev->location), mask); + + return ALT_E_SUCCESS; +} + +///// + +// +// Gets the cause of I2C transmission abort. +// +ALT_STATUS_CODE alt_i2c_tx_abort_cause_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_TX_ABORT_CAUSE_t *cause) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *cause = (ALT_I2C_TX_ABORT_CAUSE_t)alt_read_word(ALT_I2C_TX_ABRT_SRC_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +///// + +// +// Returns ALT_E_TRUE when the receive FIFO is empty. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_RFNE_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_RFNE_E_EMPTY) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns ALT_E_TRUE when the receive FIFO is completely full. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_RFF_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_RFF_E_FULL) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns the number of valid entries in the receive FIFO. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *num_entries = ALT_I2C_RXFLR_RXFLR_GET(alt_read_word(ALT_I2C_RXFLR_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Gets the current receive FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_RX_TL_RX_TL_GET(alt_read_word(ALT_I2C_RX_TL_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Sets the current receive FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_RX_TL_ADDR(i2c_dev->location), + ALT_I2C_RX_TL_RX_TL_SET_MSK, + ALT_I2C_RX_TL_RX_TL_SET(threshold)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Returns ALT_E_TRUE when the transmit FIFO is empty. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_TFE_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_TFE_E_EMPTY) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns ALT_E_TRUE when the transmit FIFO is completely full. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_TFNF_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_TFNF_E_FULL) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns the number of valid entries in the transmit FIFO. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *num_entries = ALT_I2C_TXFLR_TXFLR_GET(alt_read_word(ALT_I2C_TXFLR_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Sets the current transmit FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_TX_TL_TX_TL_GET(alt_read_word(ALT_I2C_TX_TL_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Sets the current transmit FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_TX_TL_ADDR(i2c_dev->location), + ALT_I2C_TX_TL_TX_TL_SET_MSK, + ALT_I2C_TX_TL_TX_TL_SET(threshold)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +///// + +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_DMA_RDLR_DMARDL_GET(alt_read_word(ALT_I2C_DMA_RDLR_ADDR(i2c_dev->location))); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (threshold > ALT_I2C_DMA_RDLR_DMARDL_SET_MSK) + { + return ALT_E_ARG_RANGE; + } + + alt_write_word(ALT_I2C_DMA_RDLR_ADDR(i2c_dev->location), threshold); + return ALT_E_SUCCESS; + +} + +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_DMA_TDLR_DMATDL_GET(alt_read_word(ALT_I2C_DMA_TDLR_ADDR(i2c_dev->location))); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (threshold > ALT_I2C_DMA_TDLR_DMATDL_SET_MSK) + { + return ALT_E_ARG_RANGE; + } + + alt_write_word(ALT_I2C_DMA_TDLR_ADDR(i2c_dev->location), threshold); + return ALT_E_SUCCESS; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.c b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.c new file mode 100644 index 0000000..3c29b61 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include "i2cdrv-config.h" + +const i2cdrv_configuration i2cdrv_config[CYCLONE_V_NO_I2C] = { + { + .controller = ALT_I2C_I2C0, + .device_name = "/dev/i2c0", + .speed = CYCLONE_V_I2C0_SPEED, + } +}; diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.h b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.h new file mode 100644 index 0000000..6509747 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv-config.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef XXX_H +#define XXX_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + ALT_I2C_CTLR_t controller; + char *device_name; + uint32_t speed; +} i2cdrv_configuration; + +extern const i2cdrv_configuration i2cdrv_config[]; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XXX_H */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv.c b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv.c new file mode 100644 index 0000000..3ea2355 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/i2c/i2cdrv.c @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include +#include +#include "i2cdrv-config.h" + +typedef struct { + ALT_I2C_DEV_t i2c_dev; + rtems_id mutex; +} i2cdrv_entry; + +i2cdrv_entry i2cdrv_table[CYCLONE_V_NO_I2C]; + +static ALT_I2C_DEV_t *get_device(i2cdrv_entry *e) +{ + return &e->i2c_dev; +} + +static rtems_status_code init_i2c_module( + i2cdrv_entry *e, + const i2cdrv_configuration *cfg +) +{ + ALT_STATUS_CODE asc = ALT_E_SUCCESS; + ALT_I2C_CTLR_t controller = cfg->controller; + ALT_I2C_DEV_t *dev = get_device(e); + ALT_I2C_MASTER_CONFIG_t i2c_cfg = { + .addr_mode = ALT_I2C_ADDR_MODE_7_BIT, + .restart_enable = false, + }; + + asc = alt_i2c_init(controller, dev); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + asc = alt_i2c_op_mode_set(dev, ALT_I2C_MODE_MASTER); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + asc = alt_i2c_master_config_speed_set(dev, &i2c_cfg, cfg->speed); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + asc = alt_i2c_master_config_set(dev, &i2c_cfg); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + asc = alt_i2c_enable(dev); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver i2cdrv_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + for ( size_t i = 0; i < CYCLONE_V_NO_I2C; ++i ) { + i2cdrv_entry *e = &i2cdrv_table[i]; + const i2cdrv_configuration *cfg = &i2cdrv_config[i]; + + sc = rtems_io_register_name(cfg->device_name, major, i); + assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_semaphore_create( + rtems_build_name ('I', '2', 'C', '0' + i), + 0, + RTEMS_BINARY_SEMAPHORE | RTEMS_PRIORITY | RTEMS_INHERIT_PRIORITY, + 0, + &e->mutex + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = init_i2c_module(e, cfg); + if ( sc != RTEMS_SUCCESSFUL ) { + /* I2C is not usable at this point. Releasing the mutex would allow the + * usage which could lead to undefined behaviour. */ + return sc; + } + + sc = rtems_semaphore_release(e->mutex); + assert(sc == RTEMS_SUCCESSFUL); + } + + return sc; +} + +rtems_device_driver i2cdrv_open( + rtems_device_major_number major, + rtems_device_major_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + i2cdrv_entry *e = &i2cdrv_table[minor]; + + sc = rtems_semaphore_obtain(e->mutex, RTEMS_WAIT, RTEMS_NO_TIMEOUT); + return sc; +} + +rtems_device_driver i2cdrv_close( + rtems_device_major_number major, + rtems_device_major_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + i2cdrv_entry *e = &i2cdrv_table[minor]; + + sc = rtems_semaphore_release(e->mutex); + return sc; +} + +rtems_device_driver i2cdrv_read( + rtems_device_major_number major, + rtems_device_major_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + i2cdrv_entry *e = &i2cdrv_table[minor]; + rtems_libio_rw_args_t *rw = arg; + ALT_I2C_DEV_t *dev = get_device(e); + ALT_STATUS_CODE asc = ALT_E_SUCCESS; + + asc = alt_i2c_master_receive(dev, rw->buffer, rw->count, true, true); + if ( asc == ALT_E_SUCCESS ) { + rw->bytes_moved = rw->count; + } else { + sc = RTEMS_IO_ERROR; + } + + return sc; +} + +rtems_device_driver i2cdrv_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + i2cdrv_entry *e = &i2cdrv_table[minor]; + rtems_libio_rw_args_t *rw = arg; + ALT_I2C_DEV_t *dev = get_device(e); + ALT_STATUS_CODE asc = ALT_E_SUCCESS; + + asc = alt_i2c_master_transmit(dev, rw->buffer, rw->count, true, true); + if ( asc == ALT_E_SUCCESS ) { + rw->bytes_moved = rw->count; + } else { + sc = RTEMS_IO_ERROR; + } + + return sc; +} + +static rtems_status_code ioctl_set_slave_address( + i2cdrv_entry *e, + rtems_libio_ioctl_args_t *args +) +{ + ALT_I2C_DEV_t *dev = get_device(e); + ALT_STATUS_CODE asc = ALT_E_SUCCESS; + uint32_t address = (uint32_t) args->buffer; + + asc = alt_i2c_master_target_set(dev, address); + if ( asc != ALT_E_SUCCESS ) { + return RTEMS_IO_ERROR; + } + + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver i2cdrv_ioctl( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + i2cdrv_entry *e = &i2cdrv_table[minor]; + rtems_libio_ioctl_args_t *args = arg; + + switch (args->command) { + case I2C_IOC_SET_SLAVE_ADDRESS: + sc = ioctl_set_slave_address(e, args); + break; + default: + sc = RTEMS_INVALID_NUMBER; + break; + } + + return sc; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/include/i2cdrv.h b/c/src/lib/libbsp/arm/altera-cyclone-v/include/i2cdrv.h new file mode 100644 index 0000000..9a4411d --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/include/i2cdrv.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef I2CDRV_H +#define I2CDRV_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +rtems_device_driver i2cdrv_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_ioctl( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define I2C_DRIVER_TABLE_ENTRY \ + { \ + i2cdrv_initialize, \ + i2cdrv_open, \ + i2cdrv_close, \ + i2cdrv_read, \ + i2cdrv_write, \ + i2cdrv_ioctl \ + } + +#define I2C_IOC_SET_SLAVE_ADDRESS 1 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* I2CDRV_H */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 8873d31..c13ef6a 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,18 +5,18 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + PREINSTALL_DIRS = DISTCLEANFILES += $(PREINSTALL_DIRS) all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = -CLEANFILES = $(TMPINSTALL_FILES) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) +CLEANFILES += $(TMPINSTALL_FILES) $(PROJECT_LIB)/$(dirstamp): @$(MKDIR_P) $(PROJECT_LIB) @@ -163,6 +163,10 @@ $(PROJECT_INCLUDE)/bsp/alt_hwlibs_ver.h: hwlib/include/alt_hwlibs_ver.h $(PROJEC $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_hwlibs_ver.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_hwlibs_ver.h +$(PROJECT_INCLUDE)/bsp/alt_i2c.h: hwlib/include/alt_i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_i2c.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_i2c.h + $(PROJECT_INCLUDE)/bsp/alt_interrupt_common.h: hwlib/include/alt_interrupt_common.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_interrupt_common.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_interrupt_common.h @@ -243,3 +247,7 @@ $(PROJECT_LIB)/linkcmds.altcycv_devkit_smp: startup/linkcmds.altcycv_devkit_smp $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.altcycv_devkit_smp TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.altcycv_devkit_smp +$(PROJECT_INCLUDE)/bsp/i2cdrv.h: include/i2cdrv.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/i2cdrv.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/i2cdrv.h + From joel.sherrill at oarcorp.com Mon Aug 25 15:34:49 2014 From: joel.sherrill at oarcorp.com (Joel Sherrill) Date: Mon, 25 Aug 2014 15:34:49 -0000 Subject: [rtems commit] score: Add missing define to cache manager In-Reply-To: <20140825065014.F3D3C70080E@git.rtems.org> References: <20140825065014.F3D3C70080E@git.rtems.org> Message-ID: <53FB5797.9080208@oarcorp.com> Do we want these methods provided with empty implementations on targets without CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS? We have always aimed for a consistent API. This propagates the use of a conditional into drivers and other code. --joel On 8/25/2014 1:50 AM, Sebastian Huber wrote: > Module: rtems > Branch: master > Commit: e7a42a0cfbafc2311888780b086010aef6556311 > Changeset: http://git.rtems.org/rtems/commit/?id=e7a42a0cfbafc2311888780b086010aef6556311 > > Author: Daniel Cederman > Date: Mon Aug 25 08:48:17 2014 +0200 > > score: Add missing define to cache manager > > --- > > c/src/lib/libcpu/shared/src/cache_manager.c | 2 ++ > 1 files changed, 2 insertions(+), 0 deletions(-) > > diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c > index 7dd408f..7ff1166 100644 > --- a/c/src/lib/libcpu/shared/src/cache_manager.c > +++ b/c/src/lib/libcpu/shared/src/cache_manager.c > @@ -435,6 +435,7 @@ rtems_cache_disable_data( void ) > * and then perform the invalidations. > */ > > +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) > #if !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) > static void > _invalidate_multiple_instruction_lines_no_range_functions( > @@ -462,6 +463,7 @@ _invalidate_multiple_instruction_lines_no_range_functions( > } > } > #endif > +#endif > > void > rtems_cache_invalidate_multiple_instruction_lines( > > _______________________________________________ > vc mailing list > vc at rtems.org > http://lists.rtems.org/mailman/listinfo/vc -- Joel Sherrill, Ph.D. Director of Research & Development joel.sherrill at OARcorp.com On-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available (256) 722-9985 From sebh at rtems.org Tue Aug 26 15:12:22 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 26 Aug 2014 15:12:22 -0000 Subject: [rtems commit] bsp/altera-cyclone-v: Add DMA support hwlib files Message-ID: <20140826150327.B0CF6700683@git.rtems.org> Module: rtems Branch: master Commit: 76386c1047ea15a05965adcab371bba2147831ba Changeset: http://git.rtems.org/rtems/commit/?id=76386c1047ea15a05965adcab371bba2147831ba Author: Sebastian Huber Date: Tue Aug 26 16:00:44 2014 +0200 bsp/altera-cyclone-v: Add DMA support hwlib files --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 21 +- .../hwlib/include/alt_16550_uart.h | 1555 +++++ .../arm/altera-cyclone-v/hwlib/include/alt_cache.h | 964 ++++ .../arm/altera-cyclone-v/hwlib/include/alt_dma.h | 1007 ++++ .../hwlib/include/alt_dma_common.h | 162 + .../hwlib/include/alt_dma_program.h | 951 ++++ .../arm/altera-cyclone-v/hwlib/include/alt_qspi.h | 1535 +++++ .../hwlib/include/alt_qspi_private.h | 167 + .../hwlib/include/socal/alt_dmanonsecure.h | 144 + .../hwlib/include/socal/alt_dmasecure.h | 144 + .../hwlib/include/socal/alt_qspi.h | 5951 ++++++++++++++++++++ .../hwlib/include/socal/alt_qspidata.h | 52 + .../hwlib/src/hwmgr/alt_16550_uart.c | 1179 ++++ .../arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma.c | 3749 ++++++++++++ .../hwlib/src/hwmgr/alt_dma_program.c | 1064 ++++ .../altera-cyclone-v/hwlib/src/hwmgr/alt_qspi.c | 2619 +++++++++ .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 40 + 17 files changed, 21297 insertions(+), 7 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index a581dee..aad1db1 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -51,23 +51,25 @@ include_bsp_HEADERS += include/irq.h include_bsp_HEADERS += include/nocache-heap.h # Altera hwlib +include_bsp_HEADERS += hwlib/include/alt_16550_uart.h include_bsp_HEADERS += hwlib/include/alt_address_space.h +include_bsp_HEADERS += hwlib/include/alt_cache.h include_bsp_HEADERS += hwlib/include/alt_clock_group.h include_bsp_HEADERS += hwlib/include/alt_clock_manager.h +include_bsp_HEADERS += hwlib/include/alt_dma_common.h +include_bsp_HEADERS += hwlib/include/alt_dma.h +include_bsp_HEADERS += hwlib/include/alt_dma_program.h include_bsp_HEADERS += hwlib/include/alt_generalpurpose_io.h include_bsp_HEADERS += hwlib/include/alt_hwlibs_ver.h include_bsp_HEADERS += hwlib/include/alt_i2c.h include_bsp_HEADERS += hwlib/include/alt_interrupt_common.h include_bsp_HEADERS += hwlib/include/alt_mpu_registers.h +include_bsp_HEADERS += hwlib/include/alt_qspi_private.h include_bsp_HEADERS += hwlib/include/alt_reset_manager.h include_bsp_HEADERS += hwlib/include/hwlib.h #The following Altera hwlib header files have been left out because so far #they are not required: -#include_bsp_HEADERS += hwlib/include/alt_16550_uart.h #include_bsp_HEADERS += hwlib/include/alt_bridge_manager.h -#include_bsp_HEADERS += hwlib/include/alt_dma_common.h -#include_bsp_HEADERS += hwlib/include/alt_dma_program.h -#include_bsp_HEADERS += hwlib/include/alt_dma.h #include_bsp_HEADERS += hwlib/include/alt_fpga_manager.h #include_bsp_HEADERS += hwlib/include/alt_globaltmr.h #include_bsp_HEADERS += hwlib/include/alt_system_manager.h @@ -79,9 +81,13 @@ include_bsp_HEADERS += hwlib/include/hwlib.h # Some of the headers from hwlib need the files from socal. Install them. include_bsp_socal_HEADERS += hwlib/include/socal/alt_acpidmap.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_clkmgr.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_dmanonsecure.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_dmasecure.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_gpio.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_i2c.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_l3.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_qspidata.h +include_bsp_socal_HEADERS += hwlib/include/socal/alt_qspi.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_rstmgr.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_sdr.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_sysmgr.h @@ -124,17 +130,18 @@ libbsp_a_CPPFLAGS += -std=gnu99 CFLAGS += -Wno-missing-prototypes # hwlib from Altera +libbsp_a_SOURCES += hwlib/src/hwmgr/alt_16550_uart.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_address_space.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_clock_manager.c +libbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma.c +libbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma_program.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_generalpurpose_io.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_i2c.c +libbsp_a_SOURCES += hwlib/src/hwmgr/alt_qspi.c libbsp_a_SOURCES += hwlib/src/hwmgr/alt_reset_manager.c #The following Altera hwlib source files have been left out because so far #they are not required: -#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_16550_uart.c #libbsp_a_SOURCES += hwlib/src/hwmgr/alt_bridge_manager.c -#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma_program.c -#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma.c #libbsp_a_SOURCES += hwlib/src/hwmgr/alt_fpga_manager.c #libbsp_a_SOURCES += hwlib/src/hwmgr/alt_globaltmr.c #libbsp_a_SOURCES += hwlib/src/hwmgr/alt_system_manager.c diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h new file mode 100644 index 0000000..bca6f63 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h @@ -0,0 +1,1555 @@ +/* + * Altera - SoC UART Manager + */ + +/***************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ALT_16550_UART_H__ +#define __ALT_16550_UART_H__ + +#include "hwlib.h" +#include "alt_clock_manager.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup UART UART Driver API + * + * This module defines the Universal Asynchronous Receiver/Transmitter (UART) + * API for accessing and using the UART resources. The API allows for general + * control of a 16550 compatible UART controller. + * + * This implementation can control the following UARTs: + * * SoCFPGA On-board UARTs + * * Altera 16550 Compatible Soft IP UART + * + * The following reference materials were used in the design of this API: + * * Synopsys® DesignWare DW_apb_uart Databook v3.10a + * + * @{ + */ + +/*! + * \addtogroup UART_BASIC UART Basic + * + * This group of APIs provides basic access to the UART to initialize, + * uninitialize, read, write, and reset the UART. + * + * @{ + */ + +/*! + * This type definition enumerates the list of UARTs available on the system. + */ +typedef enum ALT_16550_DEVICE_e +{ + /*! + * This option selects UART0 in the SoC FPGA. + */ + ALT_16550_DEVICE_SOCFPGA_UART0 = 0, + + /*! + * This option selects UART1 in the SoC FPGA. + */ + ALT_16550_DEVICE_SOCFPGA_UART1 = 1, + + /*! + * This option selects an Altera 16550 Compatible soft IP UART. The memory + * location of the device must be provided as part of the initialization. + */ + ALT_16550_DEVICE_ALTERA_16550_UART = 0x100 +} +ALT_16550_DEVICE_t; + +/*! + * This structure is used to represent a handle to a specific UART on the + * system. The internal members are undocumented and should be not altered + * outside of this API. + */ +typedef struct ALT_16550_HANDLE_s +{ + ALT_16550_DEVICE_t device; + void * location; + alt_freq_t clock_freq; + uint32_t data; + uint32_t fcr; +} +ALT_16550_HANDLE_t; + +/*! + * Performs the initialization steps needed by the UART. This should be the + * first API call made when accessing a particular UART + * + * The default UART setting is 8 databits, no parity, 1 stopbit, and 57600 + * baud. + * + * For the SoCFPGA UARTs, The ALT_CLK_L4_SP clock needs to be setup before + * initialization. + * + * \param device + * The UART device identifier. + * + * \param location + * The memory of the location for the given UART. For SoCFPGA + * UARTs, this parameter is ignored. + * + * \param clock_freq + * The clock frequency of the serial clock for the given UART. + * For SoCFPGA UARTs, this paramter is ignored. + * + * \param handle + * [out] A pointer to a handle that will represent the UART. This + * handle should subsequently be used when calling other UART + * APIs. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device identifier is invalid. + * \retval ALT_E_BAD_CLK The required clock is not yet setup. + */ +ALT_STATUS_CODE alt_16550_init(ALT_16550_DEVICE_t device, + void * location, + alt_freq_t clock_freq, + ALT_16550_HANDLE_t * handle); + +/*! + * Performs the uninitialization steps for the UART. This should be the last + * API call made to cleanup the UART. + * + * After calling this function, the handle will need to be initialized again + * before being used by calling alt_16550_init(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_uninit(ALT_16550_HANDLE_t * handle); + +/*! + * Resets the UART to the default configuration. The UART will be reset and + * reinitialized. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_reset(ALT_16550_HANDLE_t * handle); + +/*! + * Starts the UART after all configuration has been completed. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Stops the UART. While UART configuration can be done while enabled, it is + * not recommended. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads a single character from the UART receiver buffer. This API should + * only be used when FIFOs are disabled. + * + * \param handle + * The UART device handle. + * + * \param item + * [out] Pointer to an output parameter that contains the in + * receiver buffer of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_read(ALT_16550_HANDLE_t * handle, + char * item); + +/*! + * Writes a single character to the UART transmitter buffer. This API should + * only be used when FIFOs are disabled. + * + * \param handle + * The UART device handle. + * + * \param item + * The character to write to the transmitter buffer of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_write(ALT_16550_HANDLE_t * handle, + char item); + +/*! + * @} + */ + +/*! + * \addtogroup UART_FIFO UART FIFO Interface + * + * This group of APIs provides access, configuration, and control of the UART + * FIFO. The FIFO allows the UART to buffer received data and data to be + * transmitted. + * + * @{ + */ + +/*! + * This type definition enumerates the receiver FIFO level conditions that + * will trigger the receiver FIFO to issue a receiver FIFO full event. + */ +typedef enum ALT_16550_FIFO_TRIGGER_RX_e +{ + /*! + * 1 or more character(s) in the receiver FIFO will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_RX_ANY = 0, + + /*! + * 25% or higher capacity usage in the receiver FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL = 1, + + /*! + * 50% or higher capacity usage in the receiver FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_HALF_FULL = 2, + + /*! + * 2 characters less than the receiver FIFO capacity will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL = 3 +} +ALT_16550_FIFO_TRIGGER_RX_t; + +/*! + * This type definition enumerates the transmitter FIFO level conditions that + * will trigger the transmitter FIFO to issue a transmitter FIFO empty event. + */ +typedef enum ALT_16550_FIFO_TRIGGER_TX_e +{ + /*! + * Transmitter FIFO being completely empty will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_TX_EMPTY = 0, + + /*! + * 2 or less character(s) in the transmitter FIFO will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY = 1, + + /*! + * 25% or less capacity usage in the transmitter FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL = 2, + + /*! + * 50% or less capacity usage in the transmitter FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_TX_HALF_FULL = 3 +} +ALT_16550_FIFO_TRIGGER_TX_t; + +/*! + * Enables FIFO on the UART. This will enable both the receiver FIFO and + * transmitter FIFO. Both FIFOs will be cleared. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Disables FIFOs on the UART. This will disable both the receiver FIFO and + * transmitter FIFO. Any data left in the FIFOs will be lost. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the given buffer from the receiver FIFO in the UART. + * + * The available characters in the FIFO can be determined by a few ways. Users + * can determine the number of items by calling alt_16550_fifo_level_get_rx(). + * + * Another way is by using the RX trigger and RX interrupt. First determine the + * RX FIFO size by calling alt_16550_fifo_size_get_rx(). Then set the desired + * trigger level by calling alt_16550_fifo_trigger_set_rx(). Calculate the + * triggering point by applying trigger description on the FIFO size. Enable RX + * interrupts by calling alt_16550_int_enable_rx(). When the RX interrupt fires + * due to the ALT_16550_INT_STATUS_RX_DATA condition, the calculated triggering + * point value can be used to determine the RX FIFO level. If the interrupt + * fires due to the ALT_16550_INT_STATUS_RX_TIMEOUT, the RX FIFO can be + * completely emptied by repeatedly polling the Line Status + * ALT_16550_LINE_STATUS_DR condition by calling alt_16550_line_status_get(). + * These steps are necessary if the UART does not implement FIFO level query + * functionality. As of 13.0sp1, this applies to the Altera 16550 Compatible + * Soft UART. + * + * Reading more data than that which is available can result in invalid data + * appearing like valid data. + * + * The FIFO must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param buffer + * [out] Pointer to a buffer where the specified count of + * characters from the receiver FIFO will be copied to. + * + * \param count + * The count of characters from the receiver FIFO to be copied. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_read(ALT_16550_HANDLE_t * handle, + char * buffer, + size_t count); + +/*! + * Writes the given buffer to the transmitter FIFO in the UART. + * + * The available space in the FIFO can be determined by a few ways. Users can + * determine the number of items by calculating the FIFO capacity minus the + * FIFO level. This can be done by calling alt_16550_fifo_size_get_tx() and + * alt_16550_fifo_level_get_tx() respectively. + * + * Another way is by using the TX trigger and TX interrupt. First determine the + * TX FIFO size by calling alt_16550_fifo_size_get_tx(). The set the desired + * trigger level by calling alt_16550_fifo_trigger_set_tx(). Calculate the + * triggering point by applying the trigger description on the FIFO size. + * Enable TX interrupts by calling alt_16550_int_enable_tx(). When the TX + * interrupt fires, calculate the empty entries in the FIFO by subtracting the + * TX FIFO size and the calculated value. These steps are necessary if the UART + * does not implement FIFO level query functionality. As of 13.0sp1, this + * applies to the Altera 16550 Compatible Soft UART. + * + * Writing more data that there is space can result in data lost due to + * overflowing. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param buffer + * Pointer to a buffer from where the specified count of + * characters will be copied to the transmitter FIFO. + * + * \param count + * The count of characters from the given buffer to be copied. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_write(ALT_16550_HANDLE_t * handle, + const char * buffer, + size_t count); + +/*! + * Clears the contents of the receiver FIFO. Any characters which were + * previously contained in that FIFO will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Clears the contents of the transmitter FIFO. Any characters which were + * previously contained in that FIFO will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Clears the contents of the receiver and transmitter FIFO. Any characters + * which were previously contained on those FIFOs will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_all(ALT_16550_HANDLE_t * handle); + +/*! + * Queries the size of the receiver FIFO. + * + * \param handle + * The UART device handle. + * + * \param size + * [out] Pointer to an output parameter that contains the size of + * the receiver FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_size_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * size); + +/*! + * Queries the size of the transmitter FIFO. + * + * \param handle + * The UART device handle. + * + * \param size + * [out] Pointer to an output parameter that contains the size of + * the transmitter FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_size_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * size); + +/*! + * Queries the current level of the receiver FIFO. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * For the Altera 16550 Compatible UART, it may not be possible to read the + * FIFO level and this function may always report 0. For more information on + * interacting with the FIFO in this situation, see documentation for + * alt_16550_fifo_read(). + * + * \param handle + * The UART device handle. + * + * \param level + * [out] Pointer to an output parameter that contains the level + * or number of characters in the receiver FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_level_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * level); + +/*! + * Queries the current level of the transmitter FIFO. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * For the Altera 16550 Compatible UART, it may not be possible to read the + * FIFO level and this function may always report 0. For more information on + * interacting with the FIFO in this situation, see documentation for + * alt_16550_fifo_write(). + * + * \param handle + * The UART device handle. + * + * \param level + * [out] Pointer to an output parameter that contains the level + * or number of characters in the transmitter FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_level_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * level); + +/*! + * Sets the receiver FIFO level which will trigger the receiver FIFO to issue + * receiver FIFO full event. For the list of available receiver FIFO trigger + * levels, see the documentation for ALT_16550_FIFO_TRIGGER_RX_t. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param trigger + * The level of the receiver FIFO which is needed to trigger a + * receiver FIFO full event. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_trigger_set_rx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_RX_t trigger); + +/*! + * Sets the transmitter FIFO level which will trigger the transmitter FIFO to + * transmitter FIFO empty event. For the list of available transmitter FIFO + * trigger levels, see the documentation for ALT_16550_FIFO_TRIGGER_TX_t. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param trigger + * The level of the transmitter FIFO which is needed to trigger a + * transmitter FIFO empty event. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_trigger_set_tx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_TX_t trigger); + +/*! + * @} + */ + +/*! + * \addtogroup UART_BAUD UART Baudrate Interface + * + * This group of APIs allows for the configuration of the UART's baudrate + * generation related functions. + * + * The UART baudrate is determined by dividing the ALT_CLK_L4_SP clock with + * the configured divisor. + * + * @{ + */ + +/*! + * This enumeration lists out the common baudrates used with modem and serial + * ports. Not every baudrate is available for the UART due to the limits of + * the serial clock frequency and divisor value. + */ +typedef enum ALT_16550_BAUDRATE_e +{ + ALT_16550_BAUDRATE_50 = 50, /*!< 50 bps baudrate. */ + ALT_16550_BAUDRATE_75 = 75, /*!< 75 bps baudrate. */ + ALT_16550_BAUDRATE_150 = 150, /*!< 150 bps baudrate. */ + ALT_16550_BAUDRATE_300 = 300, /*!< 300 bps baudrate. */ + ALT_16550_BAUDRATE_600 = 600, /*!< 600 bps baudrate. */ + ALT_16550_BAUDRATE_900 = 900, /*!< 900 bps baudrate. */ + ALT_16550_BAUDRATE_1200 = 1200, /*!< 1200 bps baudrate. */ + ALT_16550_BAUDRATE_1800 = 1800, /*!< 1800 bps baudrate. */ + ALT_16550_BAUDRATE_2400 = 2400, /*!< 2400 bps baudrate. */ + ALT_16550_BAUDRATE_3600 = 3600, /*!< 3600 bps baudrate. */ + ALT_16550_BAUDRATE_4800 = 4800, /*!< 4800 bps baudrate. */ + ALT_16550_BAUDRATE_7200 = 7200, /*!< 7200 bps baudrate. */ + ALT_16550_BAUDRATE_9600 = 9600, /*!< 9600 bps baudrate. */ + ALT_16550_BAUDRATE_14400 = 14400, /*!< 14400 bps baudrate. */ + ALT_16550_BAUDRATE_19200 = 19200, /*!< 19200 bps baudrate. */ + ALT_16550_BAUDRATE_28800 = 28800, /*!< 28800 bps baudrate. */ + ALT_16550_BAUDRATE_38400 = 38400, /*!< 38400 bps baudrate. */ + ALT_16550_BAUDRATE_57600 = 57600, /*!< 57600 bps baudrate. */ + ALT_16550_BAUDRATE_115200 = 115200 /*!< 115200 bps baudrate. */ +} +ALT_16550_BAUDRATE_t; + +/*! + * Gets the baudrate for the UART. + * + * This is done by calculating the baudrate from the divisor and the serial + * clock. The reported baudrate may not correspond exactly to the request + * baudrate. + * + * \param handle + * The UART device handle. + * + * \param baudrate + * [out] Pointer to an output paramter that contains the current + * baudrate of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_baudrate_get(ALT_16550_HANDLE_t * handle, + uint32_t * baudrate); + +/*! + * Sets the baudrate for the UART. This change will take effect when the UART + * moves from disabled to enabled. + * + * This is done by calculating the correct divisor using the request baudrate + * and the known serial clock. + * + * \param handle + * The UART device handle. + * + * \param baudrate + * The requested baudrate for the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + * \retval ALT_E_ARG_RANGE The given baudrate is not possible due to + * limitations of the baudrate divisor and/or + * serial clock. + */ +ALT_STATUS_CODE alt_16550_baudrate_set(ALT_16550_HANDLE_t * handle, + uint32_t baudrate); + +/*! + * Gets the baudrate divisor for the UART. + * + * The baudrate is determined by the following formula: + * * Baudrate = (serial clock frequency) / (16 * divisor) + * + * \param handle + * The UART device handle. + * + * \param divisor + * [out] Pointer to an output parameter that contains the current + * divisor used for baudrate generation. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_divisor_get(ALT_16550_HANDLE_t * handle, + uint32_t * divisor); + +/*! + * Sets the baudrate divisor for the UART. This change will take effect when + * the UART moves from disabled to enabled. + * + * The baudrate is determined by the following formula: + * * Baudrate = (serial clock frequency) / (16 * divisor) + * + * \param handle + * The UART device handle. + * + * \param divisor + * The specified divisor value to use for baudrate generation. + * Valid values are 1 - 65535. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART identifier is invalid or the + * specified divisor is not supported by the + * UART. + */ +ALT_STATUS_CODE alt_16550_divisor_set(ALT_16550_HANDLE_t * handle, + uint32_t divisor); + +/*! + * @} + */ + +/*! + * \addtogroup UART_INT UART Interrupt Interface + * + * This group of APIs provides access, configuration, and control of the + * UART interrupts. + * + * @{ + */ + +/*! + * This type definition enumerates the different interrupt conditions that can + * be generated by the UART controller. + * + * Interrupts are listed in highest to lowest priority order. + */ +typedef enum ALT_16550_INT_STATUS_e +{ + /*! + * This interrupt signals that a overrun, parity, or framing error + * occurred, or a break event occured. The interrupt is cleared by reading + * the line status by calling alt_16550_line_status_get() or by disabling + * line status interrupts by calling alt_16550_int_disable_line(). + */ + ALT_16550_INT_STATUS_LINE = 0x6, + + /*! + * This interrupt signals that some data is available to be read from the + * UART. The definition of some depends on whether FIFOs are enabled or + * not. + * + * If FIFOs are disabled, this interrupt signals that the receiver + * contains data. In this case, the interrupt is cleared by reading the + * data from the UART by calling alt_16550_read(). + * + * If FIFOs are enabled, this interrupt signals that the receiver FIFO + * level is above the receiver trigger level specified. In this case, the + * interrupt is cleared by reading a sufficiently large buffer from the + * receiver FIFO such that the FIFO is filled below the receiver trigger + * level specified by calling alt_16550_fifo_read() or by adjusting the + * receiver trigger level appropriately by calling + * alt_16550_fifo_trigger_set_rx(). + * + * In either case, this interrupt can also be cleared by disabling + * receiver interrupts by calling alt_16550_int_disable_rx(). + */ + ALT_16550_INT_STATUS_RX_DATA = 0x4, + + /*! + * This interrupt signals that data is available in the receiver FIFO and + * that there has been no activity with the receiver FIFO for the last 4 + * character frames. In essence, the receiver FIFO has temporarily settled + * thus it may be a good time to empty the receiver FIFO. This interrupt + * is only available if FIFOs are enabled. The interrupt is cleared by + * reading from the receiver FIFO by calling alt_16550_fifo_read() or by + * disabling receiver interrupts by calling alt_16550_int_disable_rx(). + */ + ALT_16550_INT_STATUS_RX_TIMEOUT = 0xC, + + /*! + * This interrupt signals that the transmitter is idling. The definition + * of idling depends on whether FIFOs are enabled or not. + * + * If FIFOs are disabled, this interrupt signals that the transmitter + * shift register is empty. In this case, the interrupt is cleared by + * writing data to the UART by calling alt_16550_write(). + * + * If FIFO are enabled, this interrupt signals that the transmitter FIFO + * level is below the transmitter trigger level specified. In this case, + * the interrupt is cleared by writing a sufficiently large buffer to the + * transmitter FIFO such that the FIFO is filled above the transmitter + * trigger level specified by calling alt_16550_fifo_write() or by + * adjusting the transmitter trigger level appropriately by calling + * alt_16550_fifo_trigger_set_tx(). + * + * In either case, this interrupt can also be cleared by disabling + * transmitter interrupts by calling alt_16550_int_disable_tx(). + */ + ALT_16550_INT_STATUS_TX_IDLE = 0x2, + + /*! + * Modem status interrupt pending. The interrupt is cleared by reading the + * modem status by calling alt_16550_modem_status_get() or by disabling + * modem status interrupts by calling alt_16550_int_disable_modem(). + */ + ALT_16550_INT_STATUS_MODEM = 0x0, + + /*! + * No interrupts pending. + */ + ALT_16550_INT_STATUS_NONE = 0x1 +} +ALT_16550_INT_STATUS_t; + +/*! + * Enables the receiver FIFO to generate interrupts. Enabling this interrupt + * allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_RX_DATA + * * ALT_16550_INT_STATUS_RX_TIMEOUT + * + * This interrupt is disabled by default. + * + * The FIFOs must also be enabled for this interrupt to actually be generated. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the receiver FIFO from generating interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the transmitter FIFO to generate interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_TX_IDLE + * + * This interrupt is disabled by default. + * + * The FIFOs must also be enabled for this interrupt to actually be generated. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the transmitter FIFO from generating interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the receiver to generate line status interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_LINE + * + * This interrupt is disabled by default. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_line(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the receiver from generating line status interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_line(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the UART to generate modem status interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_MODEM + * + * This interrupt is disabled by default. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_modem(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the UART from generate modem status interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_modem(ALT_16550_HANDLE_t * handle); + +/*! + * Disables all interrupts on the UART. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_all(ALT_16550_HANDLE_t * handle); + +/*! + * Queries the interrupt status of the UART. This returns the highest priority + * interrupt pending. The appropriate interrupts must be enabled for them be + * generated in the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * interrupt status of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_status_get(ALT_16550_HANDLE_t * handle, + ALT_16550_INT_STATUS_t * status); + +/*! + * @} + */ + +/*! + * \addtogroup UART_MODEM UART Modem Interface + * + * This group of APIs provides access, configuration, and control of the UART + * Modem interface. + * + * @{ + */ + +/*! + * This type definition enumerates the set of UART modem status conditions as + * register mask values. + */ +typedef enum ALT_16550_MODEM_STATUS_e +{ + /*! + * Data Carrier Detect. This status indicates that the carrier has been + * detected by the modem. It corresponds to an inverted dcd_n input. DCD + * is unasserted when dcd_n is logic 1 and asserted when dcd_n is logic 0. + */ + ALT_16550_MODEM_STATUS_DCD = 1 << 7, + + /*! + * Ring Indicator. This status indicates that the telephone ringing signal + * has been redeived by the modem. It corresponds to an inverted ri_n + * input. RI is unasserted when ri_n is logic 1 and asserted when ri_n is + * logic 0. + */ + ALT_16550_MODEM_STATUS_RI = 1 << 6, + + /*! + * Data Set Ready. This status indicates that the modem is ready to + * establish communications with the UART. It corresponds to an inverted + * dsr_n input. DSR is unasserted when dsr_n is logic 1 and asserted when + * dsr_n is logic 0. + */ + ALT_16550_MODEM_STATUS_DSR = 1 << 5, + + /*! + * Clear To Send. This status indicates the current state of the modem + * cts_n line. It corresponds to an inverted cts_n input. CTS is + * unasserted when cts_n is logic 1 and asserted when cts_n is logic 0. + */ + ALT_16550_MODEM_STATUS_CTS = 1 << 4, + + /*! + * Delta Data Carrier Detect. This status condition indicates that the + * Data Carrier Detect has changed since the last time the modem status + * was read. Reading the modem status clears this status. For more + * information about the Data Carrier Detect status, see + * ALT_16550_MODEM_STATUS_DCD. + */ + ALT_16550_MODEM_STATUS_DDCD = 1 << 3, + + /*! + * Trailing Edge of Ring Indicator. This status indicates that the Ring + * Indicator has changed from asserted to unasserted. Reading the modem + * status will clear this status. For more information about the Ring + * Indicator status, reference ALT_16550_MODEM_STATUS_RI. + */ + ALT_16550_MODEM_STATUS_TERI = 1 << 2, + + /*! + * Delta Data Set Ready. This status condition indicates that the Data Set + * Ready has changed since the last time the modem status was read. + * Reading the modem status will clear this status. For more information + * about the Data Set Ready status, see ALT_16550_MODEM_STATUS_DSR. + */ + ALT_16550_MODEM_STATUS_DDSR = 1 << 1, + + /*! + * Delta Clear To Send. This status condition indicates that the Clear To + * Send has changed since the last time the modem status was read. Reading + * the modem status will clear this status. For more information about the + * Clear To Send status, see ALT_16550_MODEM_STATUS_CTS. + */ + ALT_16550_MODEM_STATUS_DCTS = 1 << 0 +} +ALT_16550_MODEM_STATUS_t; + +/*! + * Enables automatic flow control in the UART modem. When in this mode, the + * rts_n is gated with the threshold trigger condition of the receiver FIFO. + * + * The Altera 16550 Compatible Soft IP UART may not have this option enabled. + * + * The FIFOs must be enabled for flow control to be used. + * + * The recommended bring up for flow control is as follows: + * * Enable automatic flow control by calling alt_16550_flowcontrol_enable(). + * This will allow both the receiver FIFO and user RTS to control the rts_n + * output. Because the user RTS is not enabled, the rts_n will be inactive + * high. + * * Enable RTS by calling alt_16550_modem_enable_rts(). This will give the + * receiver FIFO to have full control of the rts_n output. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_flowcontrol_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Disables automatic flow control in the UART modem. + * + * The recommended bring down for flow control is as follows: + * * Disable RTS by calling alt_16550_modem_disable_rts(). This will disable + * generation of the rts_n ouput. + * * Disable automatic flow control by calling + * alt_16550_flowcontrol_disable(). + * + * The receiver FIFO will still be active after these steps. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_flowcontrol_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Puts the UART in loopback mode. This is used for diagnostic and test + * purposes. + * + * The SoCFPGA UARTs does not support automatic flow control when in loopback + * mode. + * + * The Altera 16550 Compatible Soft IP UART implements this in 13.0sp1 and + * later. Setting this has no effect with 13.0. + * + * When in this mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are + * disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) + * are held inactive high externally and internally looped back to the inputs. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_loopback_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Takes the UART out of loopback mode. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_loopback_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the OUT1 output. OUT1 is inverted then driven out to out1_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_out1(ALT_16550_HANDLE_t * handle); + +/*! + * Unasserts the OUT1 output. OUT1 is inverted then driven out to out1_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_out1(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the OUT2 output. OUT2 is inverted then driven out to out2_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_out2(ALT_16550_HANDLE_t * handle); + +/*! + * Unasserts the OUT2 output. OUT2 is inverted then driven out to out2_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_out2(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the RTS (Request To Send) output. RTS is inverted then driven out + * to rts_n. RTS is used to inform the modem that the UART is ready to receive + * data. + * + * There are special considerations when the UART is in automatic flow control + * mode. See alt_16550_flowcontrol_enable() for more information. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_rts(ALT_16550_HANDLE_t * handle); + +/*! + * Deaserts the RTS (Request To Send) output. RTS is inverted then driven out + * to rts_n. + * + * There are special considerations when the UART is in automatic flow control + * mode. See alt_16550_flowcontrol_enable() for more information. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_rts(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the DTR (Data Terminal Ready) output. DTR is inverted then driven + * out to dtr_n. DTR is used to inform the modem that UART is ready to + * establish communications. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_dtr(ALT_16550_HANDLE_t * handle); + +/*! + * Deasserts the DTR (Data Terminal Ready) output. DTR is inverted then driven + * out to dtr_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_dtr(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the modem status from the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * modem status of the UART as a register mask. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status); + +/*! + * @} + */ + +/*! + * \addtogroup UART_LINE UART Line Interface + * + * This group of APIs provides access, configuration, and control of the UART + * Line interface. + * + * @{ + */ + +/*! + * This type definition enumerates the supported databits per frame. + */ +typedef enum ALT_16550_DATABITS_e +{ + /*! + * This option selects 5 databits per frame. + */ + ALT_16550_DATABITS_5 = 0, + + /*! + * This option selects 6 databits per frame. + */ + ALT_16550_DATABITS_6 = 1, + + /*! + * This option selects 7 databits per frame. + */ + ALT_16550_DATABITS_7 = 2, + + /*! + * This option selects 8 databits per frame. + */ + ALT_16550_DATABITS_8 = 3 +} +ALT_16550_DATABITS_t; + +/*! + * This type definition enumerates the supported stopbits per frame. + */ +typedef enum ALT_16550_STOPBITS_e +{ + /*! + * This options specifies 1 stopbit per frame. + */ + ALT_16550_STOPBITS_1 = 0, + + /*! + * This options specifies 2 stopbits per frame. If the frame is + * configured with 5 databits, 1.5 stopbits is used instead. + */ + ALT_16550_STOPBITS_2 = 1 +} +ALT_16550_STOPBITS_t; + +/*! + * This type definition enumerates the possible parity to use per frame. + */ +typedef enum ALT_16550_PARITY_e +{ + /*! + * This option disables the parity error detection bit in the data frame. + */ + ALT_16550_PARITY_DISABLE = 0, + + /*! + * This option enables the odd parity error detection bit in the data + * frame. + */ + ALT_16550_PARITY_ODD = 1, + + /*! + * This option enables the even parity error detection bit in the data + * frame. + */ + ALT_16550_PARITY_EVEN = 2 +} +ALT_16550_PARITY_t; + +/*! + * This type definition enumerates the set of UART line status conditions as + * register mask values. + */ +typedef enum ALT_16550_LINE_STATUS_e +{ + /*! + * Receiver FIFO Error. This status indicates that one or more parity + * error, framing error, or break indication exists in the receiver FIFO. + * It is only set when FIFO is enabled. This status cleared when line + * status is read, the character with the issue is at the top of the FIFO, + * and when no other issues exist in the FIFO. + */ + ALT_16550_LINE_STATUS_RFE = 1 << 7, + + /*! + * Transmitter EMpTy (Empty). This status indicates that transmitter shift + * register is empty. If FIFOs are enabled, the status is set when the + * transmitter FIFO is also empty. This status is cleared when the + * transmitter shift registers is loaded by writing to the UART + * transmitter buffer or transmitter FIFO if FIFOs are enabled. This is + * done by calling alt_16550_write() and alt_16550_fifo_write() + * respectively. + */ + ALT_16550_LINE_STATUS_TEMT = 1 << 6, + + /*! + * Transmitter Holding Register Empty. This status indicates that the + * transmitter will run out of data soon. The definition of soon depends + * on whether the FIFOs are enabled. + * + * If FIFOs are disabled, this status indicates that the transmitter will + * run out of data to send after the current transmit shift register + * completes. In this case, this status is cleared when the data is + * written to the UART. This can be done by calling alt_16550_write(). + * + * If FIFOs are enabled, this status indicates that the transmitter FIFO + * level is below the transmitter trigger level specified. In this case, + * this status is cleared by writing a sufficiently large buffer to the + * transmitter FIFO such that the FIFO is filled above the transmitter + * trigger level specified by calling alt_16550_fifo_write() or by + * adjusting the transmitter trigger level appropriately by calling + * alt_16550_fifo_trigger_set_tx(). + * + * \internal + * The implementation of the UART driver always ensures that IER[7] is + * set. This means that the UART always has Programmable THRE (Transmitter + * Holding Register Empty) Interrupt Mode Enable (PTIME) enabled. + * \endinternal + */ + ALT_16550_LINE_STATUS_THRE = 1 << 5, + + /*! + * Break Interrupt. This status indicates that a break interrupt sequence + * is detected in the incoming serial data. This happens when the the data + * is 0 for longer than a frame would normally be transmitted. The break + * interrupt status is cleared by reading the line status by calling + * alt_16550_line_status_get(). + * + * If FIFOs are enabled, this status will be set when the character with + * the break interrupt status is at the top of the receiver FIFO. + */ + ALT_16550_LINE_STATUS_BI = 1 << 4, + + /*! + * Framing Error. This status indicates that a framing error occurred in + * the receiver. This happens when the receiver detects a missing or + * incorrect number of stopbit(s). + * + * If FIFOs are enabled, this status will be set when the character with + * the framing error is at the top of the FIFO. When a framing error + * occurs, the UART attempts to resynchronize with the transmitting UART. + * This status is also set if break interrupt occurred. + */ + ALT_16550_LINE_STATUS_FE = 1 << 3, + + /*! + * Parity Error. This status indicates that a parity error occurred in the + * receiver. + * + * If FIFOs are enabled, this status will be set when the character with + * the parity error is at the top of the receiver FIFO. This status is + * also set if a break interrupt occurred. + */ + ALT_16550_LINE_STATUS_PE = 1 << 2, + + /*! + * Overrun Error. This status indicates that an overrun occurred in the + * receiver. + * + * If FIFOs are disabled, the arriving character will overwrite the + * existing character in the receiver. Any previously existing + * character(s) will be lost. + * + * If FIFOs are disabled, the arriving character will be discarded. The + * buffer will continue to contain the preexisting characters. + */ + ALT_16550_LINE_STATUS_OE = 1 << 1, + + /*! + * Data Ready. This status indicates that the receiver or receiver FIFO + * contains at least one character. + */ + ALT_16550_LINE_STATUS_DR = 1 << 0 +} +ALT_16550_LINE_STATUS_t; + +/*! + * Sets the configuration for a given character frame. + * + * \param handle + * The UART device handle. + * + * \param databits + * The number of databits for each character frame. + * + * \param parity + * The parity to use for each character frame. + * + * \param stopbits + * The number of stopbits for each character frame. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_config_set(ALT_16550_HANDLE_t * handle, + ALT_16550_DATABITS_t databits, + ALT_16550_PARITY_t parity, + ALT_16550_STOPBITS_t stopbits); + +/*! + * Starts transmitting a break condition by transmitting a logic 0 state + * longer than a frame would normally be transmitted. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_break_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Stops transmitting a break condition. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_break_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the line status from the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * line status of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_16550_UART_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_cache.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_cache.h new file mode 100644 index 0000000..8d088ab --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_cache.h @@ -0,0 +1,964 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_CACHE_H__ +#define __ALT_CACHE_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup CACHE_MGR Cache Management API + * + * This module defines the cache management API for enabling and disabling L1 + * data cache, L1 instruction cache, L1 dynamic branch prediction caches, L1 + * TLB cache, and L2 cache in the SoC. As well, many it allows users to perform + * cache maintenance operations on these caches. This includes the following + * operations: + * * Invalidate: Marks the cache line as being invalid, freeing up the space + * to cache other data. All APIs which enable caches invalidates the memory + * before being enabling the cache. + * * Clean: If the cache line is dirty, it synchronizes the cache line data + * with the upper level memory system and marks that line as clean. All APIs + * which disable caches cleans the memory before disabling the cache. + * * Purge: A term used in this API as a short form for clean and invalidate. + * This operation cleans and invalidates a cache line in that order, as a + * single command to the cache controller. + * + * The following reference materials were used in the design of this API: + * * ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition + * * Cortex™-A9 Technical Reference Manual + * * Cortex™-A9 MPCore Technical Reference Manual + * * CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference + * Manual + * + * @{ + */ + +/*! + * \addtogroup CACHE_SYS System Level Cache Management API + * + * This API group provides cache maintenance operations which affects multiple + * cache levels. + * + * The enable and disable functions enables and disables all caches in the + * system respectively. For caches shared by the CPU core(s), particularly the + * L2 cache, once that cache is enabled or disabled it will not be invalidated + * or cleaned again respectively. This allows the safe system-wide enable and + * disable to be used in single-core and multi-core scenarios. + * + * For cache maintenance operations, this API implements the procedures + * outlined in the L2C-310 Technical Reference Manual, section 3.3.10, + * subsection "System cache maintenance considerations". This allows for a + * convenient way to invalidate, clean, or clean and invalidate cache data from + * the L1 to L2 to L3 while avoiding any potential race conditions in + * mutli-core or multi-master scenarios. It assumes that the L1 and L2 cache is + * set in "non-exclusive" mode. This means a segment of data can reside in both + * the L1 and L2 simultaneously. This is the default mode for caches in the + * system. + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * @{ + */ + +/*! + * Enables support for a non-flat virtual memory. A flat virtual memory is + * where every virtual address matches exactly to the physical address, making + * the virtual to physical translation trivial. Adding support for non-flat + * adds some overhead for the VA to PA translation and error detection. + * + * To enable non-flat virtual memory support, defined + * ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY=1 in your Makefile when compiling + * HWLibs. + */ +#ifndef ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY +#define ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY (0) +#endif + +/*! + * This is the system wide cache line size, given in bytes. + */ +#define ALT_CACHE_LINE_SIZE 32 + +/*! + * Enables all caches and features which improve reliability and speed on all + * cache controllers visible to the current CPU core. This includes parity + * error detection. Cache controllers visible to multiple CPU cores, for + * example the L2, will first be checked to be disabled before being enabled. + * All necessary cache maintenance operations will be done automatically. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_system_enable(void); + +/*! + * Disables all cache controllers visible to the current CPU core. Cache + * controllers visible to multiple CPU cores, for example the L2, will first + * be checked to be enabled before being disabled. All necessary cache + * maintenance operations will be done automatically. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_system_disable(void); + +/*! + * Invalidates the specified contents of all cache levels visible to the + * current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L2 invalidate address(es) + * -# L2 cache sync + * -# L1 invalidate address(es) + * -# DSB instruction + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_invalidate(void * vaddress, size_t length); + +/*! + * Cleans the specified contents of all cache levels visible to the current + * CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L1 clean address(es) + * -# DSB instruction + * -# L2 clean address(es) + * -# L2 cache sync + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_clean(void * vaddress, size_t length); + +/*! + * Cleans and invalidates the specified contents of all cache levels visible + * to the current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L1 clean address(es) + * -# DSB instruction + * -# L2 clean and invalidate address(es) + * -# L2 cache sync + * -# L1 invalidate address(es) + * -# DSB instruction + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_purge(void * vaddress, size_t length); + +/*! + * @} + */ + +/*! + * \addtogroup CACHE_L1 L1 Cache Management API + * + * This API group provides functions to interact with various components of the + * L1 cache on the SoCFPGA. This includes the following cache components: + * * Instruction Cache + * * Data Cache + * * Parity error detection + * * Dynamic branch prediction + * * Data prefetching + * + * The API within this group only affects the L1 cache on the current CPU. To + * interact the L1 cache on another CPU, the API must be called from that other + * CPU. + * + * With respect to bring-up, the L1 and L2 cache controller setups are fully + * independent. The L2 can be setup at any time, before or after the L1 is setup. + * \internal + * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". + * \endinternal + * + * @{ + */ + +/*! + * Enables all L1 caches and features on the current CPU core. This includes + * the instruction cache, data cache, parity error detection, branch target + * address cache, global history buffer, and data prefetching. All necessary + * maintenance tasks will be taken care of. + * + * This function should not be mixed with other L1 cache related functions + * which enable or disable caches individually. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_enable_all(void); + +/*! + * Disables all L1 caches and features on the current CPU core. This includes + * the instruction cache, data cache, parity error detection, branch target + * address cache, global history buffer, and data prefetching. All necessary + * maintenance tasks will be taken care of. + * + * This function should not be mixed with other L1 cache related functions + * which enable or disable caches individually. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_disable_all(void); + +/*! + * Enables the L1 instruction cache on the current CPU core. If the cache is + * already enabled, nothing is done. Otherwise the instruction cache is first + * invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_enable(void); + +/*! + * Disables the L1 instruction cache on the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_disable(void); + +/*! + * Returns \b true when the L1 instruction cache is enabled and \b false when + * it is disabled on the current CPU core. + * + * \retval true The L1 instruction cache is enabled. + * \retval false The L1 instruction cache is disabled. + */ +bool alt_cache_l1_instruction_is_enabled(void); + +/*! + * Invalidates the contents of the L1 instruction cache on the current CPU + * core. + * + * Normally this is done automatically as part of + * alt_cache_l1_instruction_enable(), but in certain circumstances it may be + * necessary to invalidate it manually. An example of this situation is when + * the address space is remapped and the processor executes instructions from + * the new memory area. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_invalidate(void); + +/*! + * Enables the L1 data cache on the current CPU core. + * + * If the cache is already enabled nothing is done. Otherwise the data cache is + * first invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_enable(void); + +/*! + * Disables the L1 data cache on the current CPU core. + * + * If the cache is already disabled nothing is done. Otherwise the data cache + * is first cleaned before being disabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_disable(void); + +/*! + * Returns \b true when the L1 data cache is enabled and \b false when it is + * disabled on the current CPU core. + * + * \retval true The L1 data cache is enabled. + * \retval false The L1 data cache is disabled. + */ +bool alt_cache_l1_data_is_enabled(void); + +/*! + * Invalidates the specified contents of the L1 data cache on the current CPU + * core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param vaddress + * The virtual address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_invalidate(void * vaddress, size_t length); + +/*! + * Invalidates the entire contents of the L1 data cache on the current CPU + * core. + * + * Normally this is done automatically as part of alt_cache_l1_data_enable(), + * but in certain circumstances it may be necessary to invalidate it manually. + * An example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_invalidate_all(void); + +/*! + * Cleans the specified contents of the L1 data cache on the current CPU core + * for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param vaddress + * The virtual address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_clean(void * vaddress, size_t length); + +/*! + * Cleans the entire L1 data cache for the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_clean_all(void); + +/*! + * Cleans and invalidates the specified contents of the L1 data cache on the + * current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * Normally this is done automatically as part of alt_cache_l1_data_disable(), + * but in certain circumstances it may be necessary to purged it manually. + * An example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + * + * \param vaddress + * The virtual address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_purge(void * vaddress, size_t length); + +/*! + * Cleans and invalidates the entire L1 data cache for the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_purge_all(void); + +/*! + * Enables the parity error detection feature in the L1 caches on the current + * CPU core. + * + * Ideally parity should be enabled before any L1 caches are enabled. If the + * instruction, data, and / or dynamic branch predictor caches are already + * enabled, they will first be cleaned (if needed) and disabled before parity + * is enabled in hardware. Afterwards, the affected caches will be invalidated + * and enabled. + * + * Parity and TLB interaction deserves special attention. The TLB is considered + * to be a L1 cache but is enabled when the MMU, which is grouped in another + * API, is enabled. Due to the system-wide influence of the MMU, it cannot be + * disabled and enabled with impunity as the other L1 caches, which are + * designed to operate as transparently as possible. Thus parity error + * detection must be enabled before the L1 TLB cache, and by extension the MMU, + * is enabled. + * + * For a parity error to be reported, the appropriate CPU PARITYFAIL interrupt + * for the current CPU core must be enabled using the interrupt controller API. + * For CPU0, ALT_INT_INTERRUPT_CPU0_PARITYFAIL is asserted if any parity error + * is detected while the other PARITYFAIL interrupts are for parity errors in a + * specific memory. Refer to the interrupt controller API for more details + * about programming the interrupt controller. + * + * In the event of a parity error is detected, the appropriate CPU parity + * interrupt will be raised. CPU parity interrupts are all edge triggered and + * are cleared by acknowledging them in the interrupt controller API. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_parity_enable(void); + +/*! + * Disables parity error detection in the L1 caches. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_parity_disable(void); + +/*! + * Returns \b true when parity error detection is enabled and \b false when it + * is disabled on the current CPU core. + * + * \retval true Parity error detection for L1 caches is + * enabled. + * \retval false Parity error detection for L1 caches is + * disabled. + */ +bool alt_cache_l1_parity_is_enabled(void); + +/*! + * Enables the dynamic branch predictor features on the current CPU core. + * + * This operation enables both the Branch Target Address Cache (BTAC) and + * the Global History Buffer (GHB). Affected caches are automatically + * invalidated before use. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_enable(void); + +/*! + * Disables the dynamic branch predictor features on the current CPU core. + * + * This operation disables both the Branch Target Address Cache (BTAC) and + * the Global History Buffer (GHB). + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_disable(void); + +/*! + * Returns \b true when both the dynamic predictor features are enabled and + * \b false when they are disabled on the current CPU core. + * + * \retval true The L1 branch predictor caches are all enabled. + * \retval false Some or all L1 branch predictor caches are + * disabled. + */ +bool alt_cache_l1_branch_is_enabled(void); + +/*! + * Invalidates the dynamic branch predictor feature caches on the current CPU + * core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_invalidate(void); + +/*! + * Enables the L1 cache data prefetch feature on the current CPU core. + * + * This allows data to be prefetched into the data cache before it is to be + * used. For example in a loop the current iteration may want to preload the + * data which will be used in the next teration. This is done by using the PLD + * instructions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_prefetch_enable(void); + +/*! + * Disables the L1 cache data prefetch feature on the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_prefetch_disable(void); + +/*! + * Returns \b true if the L1 cache data prefetch feature is enabled and + * \b false if it is disabled on the current CPU core. + * + * \retval true The L1 data cache prefetch feature is enabled. + * \retval false The L1 data cache prefetch feature is disabled. + */ +bool alt_cache_l1_prefetch_is_enabled(void); + +/*! + * @} + */ + +/*! + * \addtogroup CACHE_L2 L2 Cache Management API + * + * This API group provides functions to interact with various features of the + * L2 cache on the SoCFPGA. This includes the following features: + * * L2 cache + * * Parity error detection + * * Data prefetching + * * Interrupt Management + * + * \internal + * Additional features that may be implemented in the future: + * * Lockdown + * * Event counter + * \endinternal + * + * The API within this group affects the L2 cache which is visible to all CPUs + * on the system. + * + * With respect to bring-up, the L1 and L2 cache controller setups are fully + * independent. The L2 can be setup at any time, before or after the L1 is setup. + * \internal + * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". + * \endinternal + * + * @{ + */ + +/*! + * Initializes the L2 cache controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_cache_l2_init(void); + +/*! + * Uninitializes the L2 cache controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_cache_l2_uninit(void); + +/*! + * Enables the L2 cache features for data and instruction prefetching. + * + * Prefetching can be enabled or disabled while the L2 cache is enabled. + * \internal + * Source: Use the Prefetch Control Register. + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_prefetch_enable(void); + +/*! + * Disables the L2 cache features for data and instruction prefetching. + * + * Prefetching can be enabled or disabled while the L2 cache is enabled. + * \internal + * Source: Use the Prefetch Control Register. + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_prefetch_disable(void); + +/*! + * Returns \b true if either L2 cache data or instruction prefetch features are + * enabled and \b false if no prefetching features are enabled. + * + * \retval true The L2 data and instruction prefetch features + * are enabled. + * \retval false Some L2 data and instruction prefetch features + * are disabled. + */ +bool alt_cache_l2_prefetch_is_enabled(void); + +/*! + * Enables parity error detection in the L2 cache. + * + * Ideally parity should be enabled before the L2 cache is enabled. If the + * cache is already enabled, it will first be cleaned and disabled before + * parity is enabled in hardware. Afterwards, the cache will be invalidated and + * enabled. + * + * For a parity error to be reported, the ALT_CACHE_L2_INTERRUPT_PARRD and / or + * ALT_CACHE_L2_INTERRUPT_PARRT interrupt condition(s) must be enabled. This is + * done by calling alt_cache_l2_int_enable(). As well, the L2 cache interrupt + * must be enabled using the interrupt controller API. Refer to the interrupt + * controller API for more details about programming the interrupt controller. + * + * In the event of a parity error is detected, the appropriate L2 cache parity + * interrupt will be raised. To clear the parity interrupt(s), the appropriate + * L2 cache parity interrupt must be cleared by calling + * alt_cache_l2_int_status_clear(). + * + * For ECC support, refer to the ECC related API documentation for more + * information. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_parity_enable(void); + +/*! + * Disables parity error detection in the L2 cache. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_parity_disable(void); + +/*! + * Returns \b true when parity error detection is enabled and \b false when it + * is disabled. + * + * \retval true The L2 cache parity error detection feature is + * enabled. + * \retval false The L2 cache parity error detection feature is + * disabled. + */ +bool alt_cache_l2_parity_is_enabled(void); + +/*! + * Enables the L2 cache. + * + * If the L2 cache is already enabled, nothing is done. Otherwise the entire + * contents of the cache is first invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_enable(void); + +/*! + * Disables the L2 cache. + * + * If the L2 cache is already disabled, nothing is done. Otherwise the entire + * contents of the cache is first cleaned before being disabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_disable(void); + +/*! + * Returns \b true when the L2 cache is enabled and \b false when it is + * disabled. + * + * \retval true The L2 cache is enabled. + * \retval false The L2 cache is disabled. + */ +bool alt_cache_l2_is_enabled(void); + +/*! + * Flushes the L2 cache controller hardware buffers. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_sync(void); + +/*! + * Invalidates the specified contents of the L2 cache for the given memory + * segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_invalidate(void * paddress, size_t length); + +/*! + * Invalidates th entire contents of the L2 cache. + * + * Normally this is done automatically as part of alt_cache_l2_enable(), but + * in certain circumstances it may be necessary to invalidate it manually. An + * example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_invalidate_all(void); + +/*! + * Cleans the specified contents of the L2 cache for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_clean(void * paddress, size_t length); + +/*! + * Cleans the entire L2 cache. All L2 cache controller interrupts will be + * temporarily disabled while the clean operation is in progress and restored + * once the it is finished. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_clean_all(void); + +/*! + * Cleans and invalidates the specified contents of the L2 cache for the + * given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l2_purge(void * paddress, size_t length); + +/*! + * Cleans and invalidates the entire L2 cache. All L2 cache controller + * interrupts will be temporarily disabled while the clean and invalidate + * operation is in progress and restored once the it is finished. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_purge_all(void); + +/*! + * This type definition enumerates all the interrupt conditions that can be + * generated by the L2 cache controller as register mask values. + */ +enum ALT_CACHE_L2_INTERRUPT_e +{ + /*! Decode error received on the master ports from L3. */ + ALT_CACHE_L2_INTERRUPT_DECERR = 1 << 8, + + /*! Slave error received on the master ports from L3. */ + ALT_CACHE_L2_INTERRUPT_SLVERR = 1 << 7, + + /*! Error on the L2 data RAM read. */ + ALT_CACHE_L2_INTERRUPT_ERRRD = 1 << 6, + + /*! Error on the L2 tag RAM read. */ + ALT_CACHE_L2_INTERRUPT_ERRRT = 1 << 5, + + /*! Error on the L2 data RAM write. */ + ALT_CACHE_L2_INTERRUPT_ERRWD = 1 << 4, + + /*! Error on the L2 tag RAM write. */ + ALT_CACHE_L2_INTERRUPT_ERRWT = 1 << 3, + + /*! Parity error on the L2 data RAM read. */ + ALT_CACHE_L2_INTERRUPT_PARRD = 1 << 2, + + /*! Parity error on the L2 tag RAM read. */ + ALT_CACHE_L2_INTERRUPT_PARRT = 1 << 1, + + /*! Event counter overflow or increment. */ + ALT_CACHE_L2_INTERRUPT_ECNTR = 1 << 0 +}; +typedef enum ALT_CACHE_L2_INTERRUPT_e ALT_CACHE_L2_INTERRUPT_t; + +/*! + * Enables the L2 cache controller interrupts for the specified set of + * condition(s). + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_enable(uint32_t interrupt); + +/*! + * Disables the L2 cache controller interrupts for the specified set of + * condition(s). + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_disable(uint32_t interrupt); + +/*! + * Gets the condition(s) causing the L2 cache controller to interrupt as a + * register mask. + * + * \returns A register mask of the currently asserted and enabled + * conditions resulting in an interrupt being generated. + */ +uint32_t alt_cache_l2_int_status_get(void); + +/*! + * Clears the specified conditon(s) causing the L2 cache controller to + * interrupt as a mask. Condition(s) specified which are not causing an + * interrupt or condition(s) specified which are not enabled are ignored. + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_status_clear(uint32_t interrupt); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_CACHE_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h new file mode 100644 index 0000000..6be93fb --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h @@ -0,0 +1,1007 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_DMA_H__ +#define __ALT_DMA_H__ + +#include "hwlib.h" +#include "alt_dma_common.h" +#include "alt_dma_program.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_DMA DMA Controller API + * + * This module defines the API for configuration and use of the general purpose + * DMA controller for the SoC. The DMA controller is an instance of the ARM + * Corelink DMA Controller (DMA-330). + * + * References: + * * ARM DDI 0424C, CoreLink DMA Controller DMA-330 Technical Reference + * Manual. + * * ARM DAI 0239A, Application Note 239 Example Programs for the CoreLink + * DMA Controller DMA-330. + * * Altera, Cyclone V Device Handbook Volume 3: Hard Processor System + * Technical Reference Manual, DMA Controller. + * + * @{ + */ + +/*! + * \addtogroup ALT_DMA_COMPILE DMA API Compile Options + * + * This API provides control over the compile time inclusion of selected + * modules. This can allow for a smaller resulting binary. + * + * @{ + */ + +#ifndef ALT_DMA_PERIPH_PROVISION_16550_SUPPORT +#define ALT_DMA_PERIPH_PROVISION_16550_SUPPORT (1) +#endif + +#ifndef ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT +#define ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT (1) +#endif + +/*! + * @} + */ + +/*! + * \addtogroup ALT_DMA_CSR DMA API for Configuration, Control, and Status + * + * This API provides functions for configuration, control, and status queries + * of the DMA controller. + * + * @{ + */ + +/*! + * This type definition enumerates the operational states that the DMA manager + * may have. + */ +typedef enum ALT_DMA_MANAGER_STATE_e +{ + ALT_DMA_MANAGER_STATE_STOPPED = 0, /*!< Stopped */ + ALT_DMA_MANAGER_STATE_EXECUTING = 1, /*!< Executing */ + ALT_DMA_MANAGER_STATE_CACHE_MISS = 2, /*!< Cache Miss */ + ALT_DMA_MANAGER_STATE_UPDATING_PC = 3, /*!< Updating PC */ + ALT_DMA_MANAGER_STATE_WFE = 4, /*!< Waiting for Event */ + ALT_DMA_MANAGER_STATE_FAULTING = 15 /*!< Faulting */ +} +ALT_DMA_MANAGER_STATE_t; + +/*! + * This type definition enumerates the operational states that a DMA channel + * may have. + */ +typedef enum ALT_DMA_CHANNEL_STATE_e +{ + ALT_DMA_CHANNEL_STATE_STOPPED = 0, /*!< Stopped */ + ALT_DMA_CHANNEL_STATE_EXECUTING = 1, /*!< Executing */ + ALT_DMA_CHANNEL_STATE_CACHE_MISS = 2, /*!< Cache Miss */ + ALT_DMA_CHANNEL_STATE_UPDATING_PC = 3, /*!< Updating PC */ + ALT_DMA_CHANNEL_STATE_WFE = 4, /*!< Waiting for Event */ + ALT_DMA_CHANNEL_STATE_AT_BARRIER = 5, /*!< At Barrier */ + ALT_DMA_CHANNEL_STATE_WFP = 7, /*!< Waiting for Peripheral */ + ALT_DMA_CHANNEL_STATE_KILLING = 8, /*!< Killing */ + ALT_DMA_CHANNEL_STATE_COMPLETING = 9, /*!< Completing */ + ALT_DMA_CHANNEL_STATE_FAULTING_COMPLETING = 14, /*!< Faulting Completing */ + ALT_DMA_CHANNEL_STATE_FAULTING = 15 /*!< Faulting */ +} +ALT_DMA_CHANNEL_STATE_t; + +/*! + * This type definition enumerates the possible fault status that the DMA + * manager can have as a register mask. + */ +typedef enum ALT_DMA_MANAGER_FAULT_e +{ + /*! + * The DMA manager abort occured because of an instruction issued through + * the debug interface. + */ + ALT_DMA_MANAGER_FAULT_DBG_INSTR = (int32_t)(1UL << 30), + + /*! + * The DMA manager instruction fetch AXI bus response was not OKAY. + */ + ALT_DMA_MANAGER_FAULT_INSTR_FETCH_ERR = (int32_t)(1UL << 16), + + /*! + * The DMA manager attempted to execute DMAWFE or DMASEV with + * inappropriate security permissions. + */ + ALT_DMA_MANAGER_FAULT_MGR_EVNT_ERR = (int32_t)(1UL << 5), + + /*! + * The DMA manager attempted to execute DMAGO with inappropriate security + * permissions. + */ + ALT_DMA_MANAGER_FAULT_DMAGO_ERR = (int32_t)(1UL << 4), + + /*! + * The DMA manager attempted to execute an instruction operand that was + * not valid for the DMA configuration. + */ + ALT_DMA_MANAGER_FAULT_OPERAND_INVALID = (int32_t)(1UL << 1), + + /*! + * The DMA manager attempted to execute an undefined instruction. + */ + ALT_DMA_MANAGER_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0) +} +ALT_DMA_MANAGER_FAULT_t; + +/*! + * This type definition enumerates the possible fault status that a channel + * may have as a register mask. + */ +typedef enum ALT_DMA_CHANNEL_FAULT_e +{ + /*! + * The DMA channel has locked up due to resource starvation. + */ + ALT_DMA_CHANNEL_FAULT_LOCKUP_ERR = (int32_t)(1UL << 31), + + /*! + * The DMA channel abort occured because of an instruction issued through + * the debug interface. + */ + ALT_DMA_CHANNEL_FAULT_DBG_INSTR = (int32_t)(1UL << 30), + + /*! + * The DMA channel data read AXI bus reponse was not OKAY. + */ + ALT_DMA_CHANNEL_FAULT_DATA_READ_ERR = (int32_t)(1UL << 18), + + /*! + * The DMA channel data write AXI bus response was not OKAY. + */ + ALT_DMA_CHANNEL_FAULT_DATA_WRITE_ERR = (int32_t)(1UL << 17), + + /*! + * The DMA channel instruction fetch AXI bus response was not OKAY. + */ + ALT_DMA_CHANNEL_FAULT_INSTR_FETCH_ERR = (int32_t)(1UL << 16), + + /*! + * The DMA channel MFIFO did not have the data for the DMAST instruction. + */ + ALT_DMA_CHANNEL_FAULT_ST_DATA_UNAVAILABLE = (int32_t)(1UL << 13), + + /*! + * The DMA channel MFIFO is too small to hold the DMALD instruction data, + * or too small to servic the DMAST instruction request. + */ + ALT_DMA_CHANNEL_FAULT_MFIFO_ERR = (int32_t)(1UL << 12), + + /*! + * The DMA channel in non-secure state attempted to perform a secure read + * or write. + */ + ALT_DMA_CHANNEL_FAULT_CH_RDWR_ERR = (int32_t)(1UL << 7), + + /*! + * The DMA channel in non-secure state attempted to execute the DMAWFP, + * DMALDP, DMASTP, or DMAFLUSHP instruction involving a secure peripheral. + */ + ALT_DMA_CHANNEL_FAULT_CH_PERIPH_ERR = (int32_t)(1UL << 6), + + /*! + * The DMA channel in non-secure state attempted to execute the DMAWFE or + * DMASEV instruction for a secure event or secure interrupt (if + * applicable). + */ + ALT_DMA_CHANNEL_FAULT_CH_EVNT_ERR = (int32_t)(1UL << 5), + + /*! + * The DMA channel attempted to execute an instruction operand that was + * not valid for the DMA configuration. + */ + ALT_DMA_CHANNEL_FAULT_OPERAND_INVALID = (int32_t)(1UL << 1), + + /*! + * The DMA channel attempted to execute an undefined instruction. + */ + ALT_DMA_CHANNEL_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0) +} +ALT_DMA_CHANNEL_FAULT_t; + +/*! + * This type definition enumerates the possible DMA event-interrupt behavior + * option selections when a DMASEV instruction is executed. + */ +typedef enum ALT_DMA_EVENT_SELECT_e +{ + /*! + * If the DMA controller executes DMASEV for the event-interrupt resource + * then the DMA sends the event to all of the channel threads. + */ + ALT_DMA_EVENT_SELECT_SEND_EVT, + + /*! + * If the DMA controller executes DMASEV for the event-interrupt resource + * then the DMA sets the \b irq[N] HIGH. + */ + ALT_DMA_EVENT_SELECT_SIG_IRQ +} +ALT_DMA_EVENT_SELECT_t; + +/*! + * This type enumerates the DMA peripheral interface MUX selection options + * available. + */ +typedef enum ALT_DMA_PERIPH_MUX_e +{ + /*! + * Accept the reset default MUX selection + */ + ALT_DMA_PERIPH_MUX_DEFAULT = 0, + + /*! + * Select FPGA as the peripheral interface + */ + ALT_DMA_PERIPH_MUX_FPGA = 1, + + /*! + * Select CAN as the peripheral interface + */ + ALT_DMA_PERIPH_MUX_CAN = 2 +} +ALT_DMA_PERIPH_MUX_t; + +/*! + * This type defines the structure used to specify the configuration of the + * security states and peripheral interface MUX selections for the DMA + * controller. + */ +typedef struct ALT_DMA_CFG_s +{ + /*! + * DMA Manager security state configuration. + */ + ALT_DMA_SECURITY_t manager_sec; + + /*! + * DMA interrupt output security state configurations. Security state + * configurations are 0-based index-aligned with the enumeration values + * ALT_DMA_EVENT_0 through ALT_DMA_EVENT_7 of the ALT_DMA_EVENT_t type. + */ + ALT_DMA_SECURITY_t irq_sec[8]; + + /*! + * Peripheral request interface security state configurations. Security + * state configurations are 0-based index-aligned with the enumeration + * values of the ALT_DMA_PERIPH_t type. + */ + ALT_DMA_SECURITY_t periph_sec[32]; + + /*! + * DMA Peripheral Register Interface MUX Selections. MUX selections are + * 0-based index-aligned with the enumeration values + * ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 through + * ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 of the ALT_DMA_PERIPH_t type. + */ + ALT_DMA_PERIPH_MUX_t periph_mux[4]; +} +ALT_DMA_CFG_t; + +/*! + * Initialize the DMA controller. + * + * Initializes the DMA controller by setting the necessary control values to + * establish the security state and MUXed peripheral request interface selection + * configurations before taking the DMA controller out of reset. + * + * After the DMA is initialized, the following conditions hold true: + * * All DMA channel threads are in the Stopped state. + * * All DMA channel threads are available for allocation. + * * DMA Manager thread is waiting for an instruction from either APB + * interface. + * * The security state configurations of the DMA Manager, interrupt outputs, + * and peripheral request interfaces are established and immutable until the + * DMA is reset. + * * The MUXed peripheral request interface selection configurations are + * established and immutable until the DMA is reset. + * + * \param dma_cfg + * A pointer to a ALT_DMA_CFG_t structure containing the desired + * DMA controller security state and peripheral request interface + * MUX selections. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_init(const ALT_DMA_CFG_t * dma_cfg); + +/*! + * Uninitializes the DMA controller. + * + * Uninitializes the DMA controller by killing any running channel threads and + * putting the DMA controller into reset. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_uninit(void); + +/*! + * Allocate a DMA channel resource for use. + * + * \param channel + * A DMA controller channel. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_channel_alloc(ALT_DMA_CHANNEL_t channel); + +/*! + * Allocate a free DMA channel resource for use if there are any. + * + * \param allocated + * [out] A pointer to an output parameter that will contain the + * channel allocated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. An unallocated channel + * may not be available at the time of the API + * call. + */ +ALT_STATUS_CODE alt_dma_channel_alloc_any(ALT_DMA_CHANNEL_t * allocated); + +/*! + * Free a DMA channel resource for reuse. + * + * \param channel + * The DMA controller channel resource to free. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. The channel may not be in + * the STOPPED state. + */ +ALT_STATUS_CODE alt_dma_channel_free(ALT_DMA_CHANNEL_t channel); + +/*! + * Start execution of a DMA microcode program on the specified DMA channel + * thread resource. + * + * \param channel + * The DMA channel thread used to execute the microcode program. + * + * \param pgm + * The DMA microcode program. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_channel_exec(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * pgm); + +/*! + * Kill (abort) execution of any microcode program executing on the specified + * DMA channel thread resource. + * + * Terminates the channel thread of execution by issuing a DMAKILL instruction + * using the DMA APB slave interface. + * + * \param channel + * The DMA channel thread to abort any executing microcode program + * on. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO Timeout waiting for the channel to change into + * KILLING or STOPPED state. + */ +ALT_STATUS_CODE alt_dma_channel_kill(ALT_DMA_CHANNEL_t channel); + +/*! + * Returns the current register value for the given DMA channel. + * + * \param channel + * The DMA channel thread to abort any executing microcode program + * on. + * + * \param reg + * Register to get the value for. + * + * \param val + * [out] The current value of the requested register. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The specified channel or register is invalid. + */ +ALT_STATUS_CODE alt_dma_channel_reg_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_REG_t reg, uint32_t * val); + +/*! + * Signals the occurrence of an event or interrupt, using the specified event + * number. + * + * Causes the CPU to issue a DMASEV instruction using the DMA APB slave + * interface. + * + * The Interrupt Enable Register (INTEN) register is used to control if each + * event-interrupt resource is either an event or an interrupt. The INTEN + * register sets the event-interrupt resource to function as an: + * * Event - The DMAC generates an event for the specified event-interrupt + * resource. When the DMAC executes a DMAWFE instruction for the + * same event-interrupt resource then it clears the event. + * * Interrupt - The DMAC sets the \b IRQ[N] signal high, where + * \e evt_num is the number of the specified event + * resource. The interrupt must be cleared after being handled. + * + * When the configured to generate an event, this function may be used to + * restart one or more waiting DMA channels (i.e. having executed a DMAWFE + * instruction). + * + * See the following sections from the \e ARM DDI 0424C, CoreLink DMA Controller + * DMA-330 Technical Reference Manual for implementation details and use cases: + * * 2.5.1, Issuing Instructions to the DMAC using a Slave Interface + * * 2.7, Using Events and Interrupts + * + * \param evt_num + * A DMA event-interrupt resource. Allowable event values may be + * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 but ALT_DMA_EVENT_ABORT is + * not. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given event number is invalid. + */ +ALT_STATUS_CODE alt_dma_send_event(ALT_DMA_EVENT_t evt_num); + +/*! + * Returns the current operational state of the DMA manager thread. + * + * \param state + * [out] Pointer to an output parameter to contain the DMA + * channel thread state. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_manager_state_get(ALT_DMA_MANAGER_STATE_t * state); + +/*! + * Returns the current operational state of the specified DMA channel thread. + * + * \param channel + * The DMA channel thread to return the operational state of. + * + * \param state + * [out] Pointer to an output parameter to contain the DMA + * channel thread state. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_channel_state_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_CHANNEL_STATE_t * state); + +/*! + * Return the current fault status of the DMA manager thread. + * + * \param fault + * [out] Pointer to an output parameter to contain the DMA + * manager fault status. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_dma_manager_fault_status_get(ALT_DMA_MANAGER_FAULT_t * fault); + +/*! + * Return the current fault status of the specified DMA channel thread. + * + * \param channel + * The DMA channel thread to return the fault status of. + * + * \param fault + * [out] Pointer to an output parameter to contain the DMA + * channel fault status. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_channel_fault_status_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_CHANNEL_FAULT_t * fault); + +/*! + * Select whether the DMA controller sends the specific event to all channel + * threads or signals an interrupt using the corressponding \b irq when a DMASEV + * instruction is executed for the specified event-interrupt resource number. + * + * \param evt_num + * The event-interrupt resource number. Valid values are + * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. + * + * \param opt + * The desired behavior selection for \e evt_num when a DMASEV is + * executed. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given selection identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_event_int_select(ALT_DMA_EVENT_t evt_num, + ALT_DMA_EVENT_SELECT_t opt); + +/*! + * Returns the status of the specified event-interrupt resource. + * + * Returns ALT_E_TRUE if event is active or \b irq[N] is HIGH and returns + * ALT_E_FALSE if event is inactive or \b irq[N] is LOW. + * + * \param evt_num + * The event-interrupt resource number. Valid values are + * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. + * + * \retval ALT_E_TRUE Event is active or \b irq[N] is HIGH. + * \retval ALT_E_FALSE Event is inactive or \b irq[N] is LOW. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given event identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_event_int_status_get_raw(ALT_DMA_EVENT_t evt_num); + +/*! + * Returns the status of the specified interrupt resource. + * + * Returns ALT_E_TRUE if interrupt is active and therfore \b irq[N] is HIGH and + * returns ALT_E_FALSE if interrupt is inactive and therfore \b irq[N] is LOW. + * + * \param irq_num + * The interrupt resource number. Valid values are + * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. + * + * \retval ALT_E_TRUE Event is active or \b irq[N] is HIGH. + * \retval ALT_E_FALSE Event is inactive or \b irq[N] is LOW. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given event identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_int_status_get(ALT_DMA_EVENT_t irq_num); + +/*! + * Clear the active (HIGH) status of the specified interrupt resource. + * + * If the specified interrupt is HIGH, then sets \b irq[N] to LOW if the + * event-interrupt resource is configured (see: alt_dma_event_int_enable()) + * to signal an interrupt. Otherwise, the status of \b irq[N] does not change. + * + * \param irq_num + * The interrupt resource number. Valid values are + * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given event identifier is invalid. + */ +ALT_STATUS_CODE alt_dma_int_clear(ALT_DMA_EVENT_t irq_num); + +/*! + * @} + */ + +/*! + * \addtogroup ALT_DMA_STD_OPS DMA API for Standard Operations + * + * The functions in this group provide common DMA operations for common bulk + * data transfers between: + * * Memory to Memory + * * Zero to Memory + * * Memory to Peripheral + * * Peripheral to Memory + * + * All DMA operations are asynchronous. The following are the ways to receive + * notification of a DMA transfer complete operation: + * * Use alt_dma_channel_state_get() and poll for the + * ALT_DMA_CHANNEL_STATE_STOPPED status. + * * In conjunction with the interrupt API, use DMA events to signal an + * interrupt. The event first must be configured to signal an interrupt + * using alt_dma_event_int_select(). Configure the DMA program to send an + * event. + * * Construct a custom program which waits for a particular event number by + * assemblying a DMAWFE using alt_dma_program_DMAWFE(). Then run the custom + * program on a different channel. The custom program will wait until the + * DMA program sends the event. Configure the DMA program to send an event. + * + * Cache related maintenance on the source and/or destinatino buffer are not + * handled the DMA API and are the responsibility of the programmer. This is + * because the DMA API does not have visibility into the current configuration + * of the MMU or know about any special considerations regarding the source + * and/or destination memory. The following are some example scenarios and + * cache maintenance related precautions that may need to be taken: + * * alt_dma_memory_to_memory(): Source buffer should be cleaned or purged, + * destination buffer should be invalidated. + * * alt_dma_zero_to_memory(): Destination buffer should be invalidated. + * * alt_dma_memory_to_register(): Source buffer should be cleaned or purged. + * * alt_dma_register_to_memory(): Destination buffer should be invalidated. + * * alt_dma_memory_to_periph(): Source buffer should be cleaned or purged. + * * alt_dma_periph_to_memory(): Destination buffer should be invalidated. + * + * @{ + */ + +/*! + * Uses the DMA engine to asynchronously copy the specified memory from the + * given source address to the given destination address. + * + * Overlapping memory regions are not supported. + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param dest + * The destination memory address to copy to. + * + * \param src + * The source memory address to copy from. + * + * \param size + * The size of the transfer in bytes. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel or event identifier (if + * used) is invalid, or the memory regions + * specified are overlapping. + */ +ALT_STATUS_CODE alt_dma_memory_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dest, + const void * src, + size_t size, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * Uses the DMA engine to asynchronously zero out the specified memory buffer. + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param buf + * The buffer memory address to zero out. + * + * \param size + * The size of the buffer in bytes. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel or event identifier (if + * used) is invalid. + */ +ALT_STATUS_CODE alt_dma_zero_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * buf, + size_t size, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * Uses the DMA engine to asynchronously transfer the contents of a memory + * buffer to a keyhole register. + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param dst_reg + * The address of the register to write buffer to. + * + * \param src_buf + * The address of the memory buffer for the data. + * + * \param count + * The number of transfers to make. + * + * \param register_width_bits + * The width of the register to transfer to in bits. Valid values + * are 8, 16, 32, and 64. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel, event identifier (if used), + * or register width are invalid, or if the + * destination register or source buffer is + * unaligned to the register width. + */ +ALT_STATUS_CODE alt_dma_memory_to_register(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst_reg, + const void * src_buf, + size_t count, + uint32_t register_width_bits, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * Uses the DMA engine to asynchronously transfer the contents of a keyhole + * register to a memory buffer. + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param dst_buf + * The address of the memory buffer to copy to. + * + * \param src_reg + * The address of the keyhole register to read from. + * + * \param count + * The number of transfers to make. + * + * \param register_width_bits + * The width of the register to transfer to in bits. Valid values + * are 8, 16, 32, and 64. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel, event identifier (if used), + * or register width are invalid, or if the + * destination buffer or source register is + * unaligned to the register width. + */ +ALT_STATUS_CODE alt_dma_register_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst_buf, + const void * src_reg, + size_t count, + uint32_t register_width_bits, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * Uses the DMA engine to asynchronously copy memory from the given source + * address to the specified peripheral. Because different peripheral has + * different characteristics, individual peripherals need to be explicitly + * supported. + * + * The following lists the peripheral IDs supported by this API: + * * ALT_DMA_PERIPH_QSPI_FLASH_TX + * * ALT_DMA_PERIPH_UART0_TX + * * ALT_DMA_PERIPH_UART1_TX + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param dest + * The destination peripheral to copy memory to. + * + * \param src + * The source memory address to copy from. + * + * \param size + * The size of the transfer in bytes. + * + * \param periph_info + * A pointer to a peripheral specific data structure. The + * following list shows what data structure should be used for + * peripherals: + * * ALT_DMA_PERIPH_QSPI_FLASH_TX: This parameter is ignored. + * * ALT_DMA_PERIPH_UART0_TX: Use a pointer to the + * ALT_16550_HANDLE_t used to interact with that UART. + * * ALT_DMA_PERIPH_UART1_TX: Use a pointer to the + * ALT_16550_HANDLE_t used to interact with that UART. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel, peripheral, or event + * identifier (if used) is invalid. + * + * \internal + * Priority peripheral IDs to be supported: + * * ALT_DMA_PERIPH_FPGA_0 + * * ALT_DMA_PERIPH_FPGA_1 + * * ALT_DMA_PERIPH_FPGA_2 + * * ALT_DMA_PERIPH_FPGA_3 + * * ALT_DMA_PERIPH_FPGA_4 + * * ALT_DMA_PERIPH_FPGA_5 + * * ALT_DMA_PERIPH_FPGA_6 + * * ALT_DMA_PERIPH_FPGA_7 + * * ALT_DMA_PERIPH_I2C0_TX + * * ALT_DMA_PERIPH_I2C1_TX + * * ALT_DMA_PERIPH_I2C2_TX + * * ALT_DMA_PERIPH_I2C3_TX + * * ALT_DMA_PERIPH_SPI0_MASTER_TX + * * ALT_DMA_PERIPH_SPI0_SLAVE_TX + * * ALT_DMA_PERIPH_SPI1_MASTER_TX + * * ALT_DMA_PERIPH_SPI1_SLAVE_TX + * \endinternal + */ +ALT_STATUS_CODE alt_dma_memory_to_periph(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t dest, + const void * src, + size_t size, + void * periph_info, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * Uses the DMA engine to copy memory from the specified peripheral to the + * given destination address. Because different peripheral has different + * characteristics, individual peripherals need to be explicitly supported. + * + * The following lists the peripheral IDs supported by this API: + * * ALT_DMA_PERIPH_QSPI_FLASH_RX + * * ALT_DMA_PERIPH_UART0_RX + * * ALT_DMA_PERIPH_UART1_RX + * + * \param channel + * The DMA channel thread to use for the transfer. + * + * \param program + * An allocated DMA program buffer to use for the life of the + * transfer. + * + * \param dest + * The destination memory address to copy to. + * + * \param src + * The source peripheral to copy memory from. + * + * \param size + * The size of the transfer in bytes. + * + * \param periph_info + * A pointer to a peripheral specific data structure. The + * following list shows what data structure should be used for + * peripherals: + * * ALT_DMA_PERIPH_QSPI_FLASH_RX: This parameter is ignored. + * * ALT_DMA_PERIPH_UART0_RX: Use a pointer to the + * ALT_16550_HANDLE_t used to interact with that UART. + * * ALT_DMA_PERIPH_UART1_RX: Use a pointer to the + * ALT_16550_HANDLE_t used to interact with that UART. + * + * \param send_evt + * If set to true, the DMA engine will be instructed to send an + * event upon completion or fault. + * + * \param evt + * If send_evt is true, the event specified will be sent. + * Otherwise the parameter is ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given channel, peripheral, or event + * identifier (if used) is invalid. +* + * \internal + * Priority peripheral IDs to be supported: + * * ALT_DMA_PERIPH_FPGA_0 + * * ALT_DMA_PERIPH_FPGA_1 + * * ALT_DMA_PERIPH_FPGA_2 + * * ALT_DMA_PERIPH_FPGA_3 + * * ALT_DMA_PERIPH_FPGA_4 + * * ALT_DMA_PERIPH_FPGA_5 + * * ALT_DMA_PERIPH_FPGA_6 + * * ALT_DMA_PERIPH_FPGA_7 + * * ALT_DMA_PERIPH_I2C0_RX + * * ALT_DMA_PERIPH_I2C1_RX + * * ALT_DMA_PERIPH_I2C2_RX + * * ALT_DMA_PERIPH_I2C3_RX + * * ALT_DMA_PERIPH_SPI0_MASTER_RX + * * ALT_DMA_PERIPH_SPI0_SLAVE_RX + * * ALT_DMA_PERIPH_SPI1_MASTER_RX + * * ALT_DMA_PERIPH_SPI1_SLAVE_RX + * \endinternal + */ +ALT_STATUS_CODE alt_dma_periph_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dest, + ALT_DMA_PERIPH_t src, + size_t size, + void * periph_info, + bool send_evt, + ALT_DMA_EVENT_t evt); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h new file mode 100644 index 0000000..e82bc1a --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h @@ -0,0 +1,162 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_DMA_COMMON_H__ +#define __ALT_DMA_COMMON_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions + * + * This module contains the common definitions for the DMA controller related + * APIs. + * + * @{ + */ + +/*! + * This type definition enumerates the DMA controller channel threads. + */ +typedef enum ALT_DMA_CHANNEL_e +{ + ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */ + ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */ + ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */ + ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */ + ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */ + ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */ + ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */ + ALT_DMA_CHANNEL_7 = 7 /*!< DMA Channel Thread 7 */ +} +ALT_DMA_CHANNEL_t; + +/*! + * This type definition enumerates the SoC system peripherals implementing the + * required request interface that enables direct DMA transfers to/from the + * device. + * + * FPGA soft IP interface to the DMA are required to comply with the Synopsys + * protocol. + * + * Request interface numbers 4 through 7 are multiplexed between the CAN + * controllers and soft logic implemented in the FPGA fabric. The selection + * between the CAN controller and FPGA interfaces is determined at DMA + * initialization. + */ +typedef enum ALT_DMA_PERIPH_e +{ + ALT_DMA_PERIPH_FPGA_0 = 0, /*!< FPGA soft IP interface 0 */ + ALT_DMA_PERIPH_FPGA_1 = 1, /*!< FPGA soft IP interface 1 */ + ALT_DMA_PERIPH_FPGA_2 = 2, /*!< FPGA soft IP interface 2 */ + ALT_DMA_PERIPH_FPGA_3 = 3, /*!< FPGA soft IP interface 3 */ + + ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4, /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */ + ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5, /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */ + ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6, /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */ + ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7, /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */ + + ALT_DMA_PERIPH_FPGA_4 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */ + ALT_DMA_PERIPH_FPGA_5 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */ + ALT_DMA_PERIPH_FPGA_6 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */ + ALT_DMA_PERIPH_FPGA_7 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */ + + ALT_DMA_PERIPH_CAN0_IF1 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */ + ALT_DMA_PERIPH_CAN0_IF2 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */ + ALT_DMA_PERIPH_CAN1_IF1 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */ + ALT_DMA_PERIPH_CAN1_IF2 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */ + + ALT_DMA_PERIPH_I2C0_TX = 8, /*!< I2C 0 TX */ + ALT_DMA_PERIPH_I2C0_RX = 9, /*!< I2C 0 RX */ + ALT_DMA_PERIPH_I2C1_TX = 10, /*!< I2C 1 TX */ + ALT_DMA_PERIPH_I2C1_RX = 11, /*!< I2C 1 RX */ + ALT_DMA_PERIPH_I2C2_TX = 12, /*!< I2C 2 TX */ + ALT_DMA_PERIPH_I2C2_RX = 13, /*!< I2C 2 RX */ + ALT_DMA_PERIPH_I2C3_TX = 14, /*!< I2C 3 TX */ + ALT_DMA_PERIPH_I2C3_RX = 15, /*!< I2C 3 RX */ + ALT_DMA_PERIPH_SPI0_MASTER_TX = 16, /*!< SPI 0 Master TX */ + ALT_DMA_PERIPH_SPI0_MASTER_RX = 17, /*!< SPI 0 Master RX */ + ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18, /*!< SPI 0 Slave TX */ + ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19, /*!< SPI 0 Slave RX */ + ALT_DMA_PERIPH_SPI1_MASTER_TX = 20, /*!< SPI 1 Master TX */ + ALT_DMA_PERIPH_SPI1_MASTER_RX = 21, /*!< SPI 1 Master RX */ + ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22, /*!< SPI 1 Slave TX */ + ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23, /*!< SPI 1 Slave RX */ + ALT_DMA_PERIPH_QSPI_FLASH_TX = 24, /*!< QSPI Flash TX */ + ALT_DMA_PERIPH_QSPI_FLASH_RX = 25, /*!< QSPI Flash RX */ + ALT_DMA_PERIPH_STM = 26, /*!< System Trace Macrocell */ + ALT_DMA_PERIPH_RESERVED = 27, /*!< Reserved */ + ALT_DMA_PERIPH_UART0_TX = 28, /*!< UART 0 TX */ + ALT_DMA_PERIPH_UART0_RX = 29, /*!< UART 0 RX */ + ALT_DMA_PERIPH_UART1_TX = 30, /*!< UART 1 TX */ + ALT_DMA_PERIPH_UART1_RX = 31 /*!< UART 1 RX */ +} +ALT_DMA_PERIPH_t; + +/*! + * This type enumerates the DMA security state options available. + */ +typedef enum ALT_DMA_SECURITY_e +{ + ALT_DMA_SECURITY_DEFAULT = 0, /*!< Use the default security value (e.g. reset default) */ + ALT_DMA_SECURITY_SECURE = 1, /*!< Secure */ + ALT_DMA_SECURITY_NONSECURE = 2 /*!< Non-secure */ +} +ALT_DMA_SECURITY_t; + +/*! + * This type definition enumerates the DMA event-interrupt resources. + */ +typedef enum ALT_DMA_EVENT_e +{ + ALT_DMA_EVENT_0 = 0, /*!< DMA Event 0 */ + ALT_DMA_EVENT_1 = 1, /*!< DMA Event 1 */ + ALT_DMA_EVENT_2 = 2, /*!< DMA Event 2 */ + ALT_DMA_EVENT_3 = 3, /*!< DMA Event 3 */ + ALT_DMA_EVENT_4 = 4, /*!< DMA Event 4 */ + ALT_DMA_EVENT_5 = 5, /*!< DMA Event 5 */ + ALT_DMA_EVENT_6 = 6, /*!< DMA Event 6 */ + ALT_DMA_EVENT_7 = 7, /*!< DMA Event 7 */ + ALT_DMA_EVENT_ABORT = 8 /*!< DMA Abort Event */ +} +ALT_DMA_EVENT_t; + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_COMMON_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h new file mode 100644 index 0000000..5fa876f --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h @@ -0,0 +1,951 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_DMA_PROGRAM_H__ +#define __ALT_DMA_PROGRAM_H__ + +#include "hwlib.h" +#include "alt_dma_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_DMA_PRG DMA Controller Programming API + * + * This API provides functions for dynamically defining and assembling microcode + * programs for execution on the DMA controller. + * + * The microcode program assembly API provides users with the ability to develop + * highly optimized and tailored algorithms for data transfer between SoC FPGA + * IP blocks and/or system memory. + * + * The same microcode program assembly facilities are also used to implement the + * functions found in the HWLIB Common DMA Operations functional API. + * + * An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA + * microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated + * from used specified system memory. Once a microcode program has been + * assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA + * channel thread. The microcode program may be rerun on any DMA channel thread + * whenever required as long as the integrity of the ALT_DMA_PROGRAM_t + * containing the program is maintained. + * + * @{ + */ + +/*! + * This preprocessor declares the DMA channel thread microcode instruction + * cache line width in bytes. It is recommended that the program buffers be + * sized to a multiple of the cache line size. This will allow for the most + * efficient microcode speed and space utilization. + */ +#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32) + +/*! + * This preprocessor declares the DMA channel thread microcode instruction + * cache line count. Thus the total size of the cache is the cache line size + * multipled by the cache line count. Programs larger than the cache size risk + * having a cache miss while executing. + */ +#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16) + +/*! + * This preprocessor definition determines the size of the program buffer + * within the ALT_DMA_PROGRAM_t structure. This size should provide adequate + * size for most DMA microcode programs. If calls within this API are + * reporting out of memory response codes, consider increasing the provisioned + * program buffersize. + * + * To specify another DMA microcode program buffer size, redefine the macro + * below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in + * your Makefile. It is recommended that the size be a multiple of the + * microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for + * more information. The largest supported buffer size is 65536 bytes. + */ +#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE +#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT) +#endif + +/*! + * This type defines the structure used to assemble and contain a microcode + * program which can be executed by the DMA controller. The internal members + * are undocumented and should not be altered outside of this API. + */ +typedef struct ALT_DMA_PROGRAM_s +{ + uint32_t flag; + + uint16_t buffer_start; + uint16_t code_size; + + uint16_t loop0; + uint16_t loop1; + + uint16_t sar; + uint16_t dar; + + /* + * Add a little extra space so that regardless of where this structure + * sits in memory, a suitable start address can be aligned to the cache + * line stride while providing the requested buffer space. + */ + uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE + + ALT_DMA_PROGRAM_CACHE_LINE_SIZE]; +} +ALT_DMA_PROGRAM_t; + +/*! + * This type definition enumerates the DMA controller register names for use in + * microcode program definition. + */ +typedef enum ALT_DMA_PROGRAM_REG_e +{ + /*! Source Address Register */ + ALT_DMA_PROGRAM_REG_SAR = 0x0, + + /*! Destination Address Register */ + ALT_DMA_PROGRAM_REG_DAR = 0x2, + + /*! Channel Control Register */ + ALT_DMA_PROGRAM_REG_CCR = 0x1 +} +ALT_DMA_PROGRAM_REG_t; + +/*! + * This type definition enumerates the instruction modifier options available + * for use with selected DMA microcode instructions. + * + * The enumerations values are context dependent upon the instruction being + * modified. + * + * For the DMALD[S|B], DMALDP\, DMAST[S|B], and + * DMASTP\ microcode instructions, the enumeration + * ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the S option modifier + * while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the B + * option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies + * that no modifier is present for instructions where use of [S|B] is + * optional. + * + * For the DMAWFP microcode instruction, the enumerations + * ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or + * ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding + * options \. + */ +typedef enum ALT_DMA_PROGRAM_INST_MOD_e +{ + /*! + * This DMA instruction modifier specifies that no special modifier is + * added to the instruction. + */ + ALT_DMA_PROGRAM_INST_MOD_NONE, + + /*! + * Depending on the DMA microcode instruction modified, this modifier + * specifies S case for a [S|B] or a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_SINGLE, + + /*! + * Depending on the DMA microcode instruction modified, this modifier + * specifies B case for a [S|B] or a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_BURST, + + /*! + * This DMA instruction modifier specifies a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_PERIPH +} +ALT_DMA_PROGRAM_INST_MOD_t; + +/*! + * This function initializes a system memory buffer for use as a DMA microcode + * program buffer. This should be the first API call made on the program + * buffer type. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function verifies that the DMA microcode program buffer is no longer + * in use and performs any needed uninitialization steps. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function clears the existing DMA microcode program in the given + * program buffer. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function validate that the given DMA microcode program buffer contains + * a well formed program. If caches are enabled, the program buffer contents + * will be cleaned to RAM. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The given program is well formed. + * \retval ALT_E_ERROR The given program is not well formed. + * \retval ALT_E_TMO The cache operation timed out. + */ +ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function reports the number bytes incremented for the register + * specified. The purpose is to determine the progress of an ongoing DMA + * transfer. + * + * It is implemented by calculating the difference of the programmed SAR or DAR + * with the current channel SAR or DAR register value. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \param channel + * The channel that the program is running on. + * + * \param reg + * Register to change the value for. Valid for only + * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. + * + * \param current + * The current snapshot value of the register read from the DMA + * channel. + * + * \param progress + * [out] A pointer to a memory location that will be used to store + * the number of bytes transfered. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + * \retval ALT_E_BAD_ARG The specified channel is invalid, the specified + * register is invalid, or the DMAMOV for the + * specified register has not yet been assembled + * in the current program buffer. + */ +ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, + uint32_t current, uint32_t * progress); + +/*! + * This function updates a pre-existing DMAMOV value affecting the SAR or DAR + * registers. This allows for pre-assembled programs that can be used on + * different source and destination addresses. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \param reg + * Register to change the value for. Valid for only + * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. + * + * \param val + * The value to update to. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + * \retval ALT_E_BAD_ARG The specified register is invalid or the DMAMOV + * for the specified register has not yet been + * assembled in the current program buffer. + */ +ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, uint32_t val); + +/*! + */ + +/*! + * Assembles a DMAADDH (Add Halfword) instruction into the microcode program + * buffer. This instruction uses 3 bytes of buffer space. + * + * \param pgm + * The DMA program buffer to contain the assembled instruction. + * + * \param addr_reg + * The channel address register (ALT_DMA_PROGRAM_REG_DAR or + * ALT_DMA_PROGRAM_REG_SAR) to add the value to. + * + * \param val + * The 16-bit unsigned value to add to the channel address + * register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAADDH , <16-bit immediate> +ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); + +/*! + * Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode + * program buffer. This instruction uses 3 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param addr_reg + * The channel address register (ALT_DMA_PROGRAM_REG_DAR or + * ALT_DMA_PROGRAM_REG_SAR) to add the value to. + * + * \param val + * The 16-bit unsigned value to add to the channel address + * register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAADNH , <16-bit immediate> +ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); + +/*! + * Assembles a DMAEND (End) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAEND +ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode + * program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param periph + * The peripheral to flush. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid peripheral specified. + */ +// Assembler Syntax: DMAFLUSHP +ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMAGO (Go) instruction into the microcode program buffer. This + * instruction uses 6 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param channel + * The stopped channel to act upon. + * + * \param val + * The value to write to the channel program counter register. + * + * \param sec + * The security state for the operation. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel or security specified. + */ +// Assembler Syntax: DMAGO , <32-bit_immediate> [, ns] +ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_CHANNEL_t channel, uint32_t val, + ALT_DMA_SECURITY_t sec); + +/*! + * Assembles a DMAKILL (Kill) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAKILL +ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMALD (Load) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. + */ +// Assembler Syntax: DMALD[S|B] +ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMALDP (Load and notify Peripheral) instruction into the + * microcode program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \param periph + * The peripheral to notify. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral + * specified. + */ +// Assembler Syntax: DMALDP +ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMALP (Loop) instruction into the microcode program buffer. + * This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param iterations + * The number of iterations to run for. Valid values are 1 - 256. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid iterations specified. + * \retval ALT_E_BAD_OPERATION All loop registers are in use. + */ +// Assembler Syntax: DMALP [|] +ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm, + uint32_t iterations); + +/*! + * Assembles a DMALPEND (Loop End) instruction into the microcode program + * buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the loop terminator. Only + * ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE + * and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. + * \retval ALT_E_ARG_RANGE Loop size is too large to be supported. + * \retval ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to + * the program buffer before adding this + * DMALPEND instruction. + */ +// Assembler Syntax: DMALPEND[S|B] +ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMALPFE (Loop Forever) instruction into the microcode program + * buffer. No instruction is added to the buffer but a previous DMALPEND to + * create an infinite loop. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMALPFE +ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAMOV (Move) instruction into the microcode program buffer. + * This instruction uses 6 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param chan_reg + * The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR, + * ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy + * the value to. + * + * \param val + * The value to write to the specified register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAMOV , <32-bit_immediate> +ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val); + +/*! + * Assembles a DMANOP (No Operation) instruction into the microcode program + * buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMANOP +ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMARMB (Read Memory Barrier) instruction into the microcode + * program buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMARMB +ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMASEV (Send Event) instruction into the microcode program + * buffer. This instruction uses 2 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param evt + * The event to send. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid event specified. + */ +// Assembler Syntax: DMASEV +ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt); + +/*! + * Assembles a DMAST (Store) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAST[S|B] +ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMASTP (Store and notify Peripheral) instruction into the + * microcode program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \param periph + * The peripheral to notify. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral + * specified. + */ +// Assembler Syntax: DMASTP +ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMASTZ (Store Zero) instruction into the microcode program + * buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMASTZ +ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAWFE (Wait For Event) instruction into the microcode program + * buffer. This instruction uses 2 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param evt + * The event to wait for. + * + * \param invalid + * If invalid is set to true, the instruction will be configured + * to invalidate the instruction cache for the current DMA + * thread. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid event specified. + */ +// Assembler Syntax: DMAWFE [, invalid] +ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt, bool invalid); + +/*! + * Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode + * program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param periph + * The peripheral to wait on. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE, + * ALT_DMA_PROGRAM_INST_MOD_BURST, or + * ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid peripheral or instruction modifier + * specified. + */ +// Assembler Syntax: DMAWFP , +ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode + * program buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAWMB +ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm); + +/*! + * \addtogroup DMA_CCR Support for DMAMOV CCR + * + * The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the + * dynamic microcode programming of the assembler directive: +\verbatim + +DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA] + [SP] [SC] + [DB<1-16>] [DS<8|16|32|64|128>] [DA] + [DP] [DC] + [ES<8|16|32|64|128>] + +\endverbatim +* with a DMAMOV instruction (see: alt_dma_program_DMAMOV()). +* +* For example the assembler directive: +\verbatim +DMAMOV CCR SB1 SS32 DB1 DS32 +\endverbatim +* would be dynamically programmed with the following API call: +\verbatim +alt_dma_program_DMAMOV( pgm, + ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES8 + ) + ); +\endverbatim +* +* Each CCR option category should be specified regardless of whether it +* specifies a custom value or the normal default value (i.e. an +* ALT_DMA_CCR_OPT_*_DEFAULT. +* +* @{ +*/ + +/* + * Source Address {Fixed,Incrementing} + */ +/*! Source Address Fixed address burst. */ +#define ALT_DMA_CCR_OPT_SAF (0 << 0) +/*! Source Address Incrementing address burst. */ +#define ALT_DMA_CCR_OPT_SAI (1 << 0) +/*! Source Address Default value. */ +#define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI + +/* + * Source burst Size (in bits) + */ +/*! Source burst Size of 8 bits. */ +#define ALT_DMA_CCR_OPT_SS8 (0 << 1) +/*! Source burst Size of 16 bits. */ +#define ALT_DMA_CCR_OPT_SS16 (1 << 1) +/*! Source burst Size of 32 bits. */ +#define ALT_DMA_CCR_OPT_SS32 (2 << 1) +/*! Source burst Size of 64 bits. */ +#define ALT_DMA_CCR_OPT_SS64 (3 << 1) +/*! Source burst Size of 128 bits. */ +#define ALT_DMA_CCR_OPT_SS128 (4 << 1) +/*! Source burst Size default bits. */ +#define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8 + +/* + * Source burst Length (in transfer(s)) + */ +/*! Source Burst length of 1 transfer. */ +#define ALT_DMA_CCR_OPT_SB1 (0x0 << 4) +/*! Source Burst length of 2 transfers. */ +#define ALT_DMA_CCR_OPT_SB2 (0x1 << 4) +/*! Source Burst length of 3 transfers. */ +#define ALT_DMA_CCR_OPT_SB3 (0x2 << 4) +/*! Source Burst length of 4 transfers. */ +#define ALT_DMA_CCR_OPT_SB4 (0x3 << 4) +/*! Source Burst length of 5 transfers. */ +#define ALT_DMA_CCR_OPT_SB5 (0x4 << 4) +/*! Source Burst length of 6 transfers. */ +#define ALT_DMA_CCR_OPT_SB6 (0x5 << 4) +/*! Source Burst length of 7 transfers. */ +#define ALT_DMA_CCR_OPT_SB7 (0x6 << 4) +/*! Source Burst length of 8 transfers. */ +#define ALT_DMA_CCR_OPT_SB8 (0x7 << 4) +/*! Source Burst length of 9 transfers. */ +#define ALT_DMA_CCR_OPT_SB9 (0x8 << 4) +/*! Source Burst length of 10 transfers. */ +#define ALT_DMA_CCR_OPT_SB10 (0x9 << 4) +/*! Source Burst length of 11 transfers. */ +#define ALT_DMA_CCR_OPT_SB11 (0xa << 4) +/*! Source Burst length of 12 transfers. */ +#define ALT_DMA_CCR_OPT_SB12 (0xb << 4) +/*! Source Burst length of 13 transfers. */ +#define ALT_DMA_CCR_OPT_SB13 (0xc << 4) +/*! Source Burst length of 14 transfers. */ +#define ALT_DMA_CCR_OPT_SB14 (0xd << 4) +/*! Source Burst length of 15 transfers. */ +#define ALT_DMA_CCR_OPT_SB15 (0xe << 4) +/*! Source Burst length of 16 transfers. */ +#define ALT_DMA_CCR_OPT_SB16 (0xf << 4) +/*! Source Burst length default transfers. */ +#define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1 + +/* + * Source Protection + */ +/*! Source Protection bits for AXI bus ARPROT[2:0]. */ +#define ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8) +/*! Source Protection bits default value. */ +#define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0) + +/* + * Source cache + */ +/*! Source Cache bits for AXI bus ARCACHE[2:0]. */ +#define ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11) +/*! Source Cache bits default value. */ +#define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0) + +/* + * Destination Address {Fixed,Incrementing} + */ +/*! Destination Address Fixed address burst. */ +#define ALT_DMA_CCR_OPT_DAF (0 << 14) +/*! Destination Address Incrementing address burst. */ +#define ALT_DMA_CCR_OPT_DAI (1 << 14) +/*! Destination Address Default value. */ +#define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI + +/* + * Destination burst Size (in bits) + */ +/*! Destination burst Size of 8 bits. */ +#define ALT_DMA_CCR_OPT_DS8 (0 << 15) +/*! Destination burst Size of 16 bits. */ +#define ALT_DMA_CCR_OPT_DS16 (1 << 15) +/*! Destination burst Size of 32 bits. */ +#define ALT_DMA_CCR_OPT_DS32 (2 << 15) +/*! Destination burst Size of 64 bits. */ +#define ALT_DMA_CCR_OPT_DS64 (3 << 15) +/*! Destination burst Size of 128 bits. */ +#define ALT_DMA_CCR_OPT_DS128 (4 << 15) +/*! Destination burst Size default bits. */ +#define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8 + +/* + * Destination Burst length (in transfer(s)) + */ +/*! Destination Burst length of 1 transfer. */ +#define ALT_DMA_CCR_OPT_DB1 (0x0 << 18) +/*! Destination Burst length of 2 transfers. */ +#define ALT_DMA_CCR_OPT_DB2 (0x1 << 18) +/*! Destination Burst length of 3 transfers. */ +#define ALT_DMA_CCR_OPT_DB3 (0x2 << 18) +/*! Destination Burst length of 4 transfers. */ +#define ALT_DMA_CCR_OPT_DB4 (0x3 << 18) +/*! Destination Burst length of 5 transfers. */ +#define ALT_DMA_CCR_OPT_DB5 (0x4 << 18) +/*! Destination Burst length of 6 transfers. */ +#define ALT_DMA_CCR_OPT_DB6 (0x5 << 18) +/*! Destination Burst length of 7 transfers. */ +#define ALT_DMA_CCR_OPT_DB7 (0x6 << 18) +/*! Destination Burst length of 8 transfers. */ +#define ALT_DMA_CCR_OPT_DB8 (0x7 << 18) +/*! Destination Burst length of 9 transfers. */ +#define ALT_DMA_CCR_OPT_DB9 (0x8 << 18) +/*! Destination Burst length of 10 transfers. */ +#define ALT_DMA_CCR_OPT_DB10 (0x9 << 18) +/*! Destination Burst length of 11 transfers. */ +#define ALT_DMA_CCR_OPT_DB11 (0xa << 18) +/*! Destination Burst length of 12 transfers. */ +#define ALT_DMA_CCR_OPT_DB12 (0xb << 18) +/*! Destination Burst length of 13 transfers. */ +#define ALT_DMA_CCR_OPT_DB13 (0xc << 18) +/*! Destination Burst length of 14 transfers. */ +#define ALT_DMA_CCR_OPT_DB14 (0xd << 18) +/*! Destination Burst length of 15 transfers. */ +#define ALT_DMA_CCR_OPT_DB15 (0xe << 18) +/*! Destination Burst length of 16 transfers. */ +#define ALT_DMA_CCR_OPT_DB16 (0xf << 18) +/*! Destination Burst length default transfers. */ +#define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1 + +/* + * Destination Protection + */ +/*! Destination Protection bits for AXI bus AWPROT[2:0]. */ +#define ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22) +/*! Destination Protection bits default value. */ +#define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0) + +/* + * Destination Cache + */ +/*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */ +#define ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25) +/*! Destination Cache bits default value. */ +#define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0) + +/* + * Endian Swap size (in bits) + */ +/*! Endian Swap: No swap, 8-bit data. */ +#define ALT_DMA_CCR_OPT_ES8 (0 << 28) +/*! Endian Swap: Swap bytes within 16-bit data. */ +#define ALT_DMA_CCR_OPT_ES16 (1 << 28) +/*! Endian Swap: Swap bytes within 32-bit data. */ +#define ALT_DMA_CCR_OPT_ES32 (2 << 28) +/*! Endian Swap: Swap bytes within 64-bit data. */ +#define ALT_DMA_CCR_OPT_ES64 (3 << 28) +/*! Endian Swap: Swap bytes within 128-bit data. */ +#define ALT_DMA_CCR_OPT_ES128 (4 << 28) +/*! Endian Swap: Default byte swap. */ +#define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8 + +/*! Default CCR register options for a DMAMOV CCR assembler directive. */ +#define ALT_DMA_CCR_OPT_DEFAULT \ + (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \ + ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \ + ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \ + ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \ + ALT_DMA_CCR_OPT_ES8) + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_PROGRAM_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi.h new file mode 100644 index 0000000..d09ccf2 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi.h @@ -0,0 +1,1535 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/****************************************************************************** +* +* !!!! Customer Be Aware, Exception!!! +* +* 1. Qspi Direct Access Mode is not working! +* +* This is because the qspi flash memory installed on our DevKit board, Micro +* part N25Q00xx, 8 Gb, is not completely compatible with our embedded Synopsis +* QSPI controller IP. Therefore there is no viable direct access code offered +* in the lib. All the memory rea/write functionality is offered with indirect +* access only. +* +* Should you install a different flash memory part in your custom board, and +* wondering wether direct access mode works, please contact with us. +* +******************************************************************************/ + +/*! \file + * Altera - QSPI Flash Controller Module + */ + +#ifndef __ALT_QSPI_H__ +#define __ALT_QSPI_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI QSPI Flash Controller Module + * + * This module defines a low level driver API for the hardware processor system + * (HPS) quad serial peripheral interface (QSPI) flash controller for access to + * serial NOR flash devices. The quad SPI flash controller supports standard SPI + * flash devices as well as high-performance dual and quad SPI flash + * devices. + * + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_CSR General Control and Status Functions + * + * The declarations and functions in this group provide general purpose control + * and status functions for the QSPI Flash Controller. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Initialize the QSPI flash controller for use. + * + * \internal + * Implementation Notes: + * * The QSPI Controller has been designed to wake up in a state that is + * suitable for performing basic reads and writes using the direct access + * controller. + * * Bring out of reset + * * QSPI reference clock validation + * * See Programmer's Guide, Configuring the QSPI Controller for use after + * reset, in QSPI_FLASH_CTRL for full initialization details. + * \endinternal + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_init(void); + +/******************************************************************************/ +/*! + * Uninitialize the QSPI flash controller. + * + * Uninitialize the QSPI flash controller by cancelling any indirect transfers + * in progress and putting the QSPI controller into reset. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_uninit(void); + +/******************************************************************************/ +/*! + * Disable the QSPI Controller. + * + * Disable the QSPI once the current transfer of the data word (FF_W) is + * complete. All output enables are inactive and all pins are set to input + * mode. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_disable(void); + +/******************************************************************************/ +/*! + * Enable the QSPI Controller. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_enable(void); + +/******************************************************************************/ +/*! + * This type definition enumerates the interrupt status conditions for the QSPI + * controller. + * + * The enumerations serve as masks for the QSPI controller events that can be + * set when the designated conditions occur and the corresponding event is + * enabled. When any of these event source conditions are true, the \b + * ALT_INT_INTERRUPT_QSPI_IRQ interrupt output is asserted high. + * + * Interrupt sources are cleared when software calls alt_qspi_int_clear(). The + * interrupt sources are individually maskable using alt_qspi_int_disable() and + * alt_qspi_int_enable(). + */ +typedef enum ALT_QSPI_INT_STATUS_e +{ + /*! + * Mode fail M - indicates the voltage on pin n_ss_in is inconsistent with + * the SPI mode. Set = 1 if n_ss_in is low in master mode (multi-master + * contention). These conditions will clear the spi_enable bit and disable + * the SPI. + * * 0 = no mode fault has been detected. + * * 1 = a mode fault has occurred. + */ + ALT_QSPI_INT_STATUS_MODE_FAIL = (0x1 << 0), + + /*! + * Underflow Detected. + * * 0 = no underflow has been detected. + * * 1 = underflow is detected and an attempt to transfer data is made + * when the small TX FIFO is empty. This may occur when AHB write + * data is being supplied too slowly to keep up with the requested + * write operation. + */ + ALT_QSPI_INT_STATUS_UFL = (0x1 << 1), + + /*! + * Controller has completed last triggered indirect operation. + */ + ALT_QSPI_INT_STATUS_IDAC_OP_COMPLETE = (0x1 << 2), + + /*! + * Indirect operation was requested but could not be accepted. Two indirect + * operations already in storage. + */ + ALT_QSPI_INT_STATUS_IDAC_OP_REJECT = (0x1 << 3), + + /*! + * Write to protected area was attempted and rejected. + */ + ALT_QSPI_INT_STATUS_WR_PROT_VIOL = (0x1 << 4), + + /*! + * Illegal AHB Access Detected. AHB write wrapping bursts and the use of + * SPLIT/RETRY accesses will cause this interrupt to trigger. + */ + ALT_QSPI_INT_STATUS_ILL_AHB_ACCESS = (0x1 << 5), + + /*! + * Indirect Transfer Watermark Level Breached. + */ + ALT_QSPI_INT_STATUS_IDAC_WTRMK_TRIG = (0x1 << 6), + + /*! + * Receive Overflow. This should only occur in Legacy SPI mode. + * + * Set if an attempt is made to push the RX FIFO when it is full. This bit + * is reset only by a system reset and cleared only when this register is + * read. If a new push to the RX FIFO occurs coincident with a register read + * this flag will remain set. + * * 0 = no overflow has been detected. + * * 1 = an overflow has occurred. + */ + ALT_QSPI_INT_STATUS_RX_OVF = (0x1 << 7), + + /*! + * Small TX FIFO not full (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO has >= THRESHOLD entries. + * * 1 = FIFO has < THRESHOLD entries. + */ + ALT_QSPI_INT_STATUS_TX_FIFO_NOT_FULL = (0x1 << 8), + + /*! + * Small TX FIFO full (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO is not full. + * * 1 = FIFO is full. + */ + ALT_QSPI_INT_STATUS_TX_FIFO_FULL = (0x1 << 9), + + /*! + * Small RX FIFO not empty (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO has < RX THRESHOLD entries. + * * 1 = FIFO has >= THRESHOLD entries. + */ + ALT_QSPI_INT_STATUS_RX_FIFO_NOT_EMPTY = (0x1 << 10), + + /*! + * Small RX FIFO full (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO is not full. + * * 1 = FIFO is full. + */ + ALT_QSPI_INT_STATUS_RX_FIFO_FULL = (0x1 << 11), + + /*! + * Indirect Read partition of SRAM is full and unable to immediately + * complete indirect operation. + */ + ALT_QSPI_INT_STATUS_IDAC_RD_FULL = (0x1 << 12) + +} ALT_QSPI_INT_STATUS_t; + +/******************************************************************************/ +/*! + * Returns the QSPI controller interrupt status register value. + * + * This function returns the current value of the QSPI controller interrupt + * status register value which reflects the current QSPI controller status + * conditions. + * + * \returns The current value of the QSPI controller interrupt status + * register value which reflects the current QSPI controller status + * conditions as defined by the \ref ALT_QSPI_INT_STATUS_t mask. + * If the corresponding bit is set then the condition is asserted. + */ +uint32_t alt_qspi_int_status_get(void); + +/******************************************************************************/ +/*! + * Clears the specified QSPI controller interrupt status conditions identified + * in the mask. + * + * This function clears one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. + * + * \param mask + * Specifies the QSPI interrupt status conditions to clear. \e + * mask is a mask of logically OR'ed \ref ALT_QSPI_INT_STATUS_t + * values that designate the status conditions to clear. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_int_clear(const uint32_t mask); + +/******************************************************************************/ +/*! + * Disable the specified QSPI controller interrupt status conditions identified + * in the mask. + * + * This function disables one or more of the status conditions as contributors + * to the \b ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of enabling it as a contributor to the \b + * ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. The function + * alt_qspi_int_enable() is used to enable status source conditions. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed + * \ref ALT_QSPI_INT_STATUS_t values that designate the status + * conditions to disable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_int_disable(const uint32_t mask); + +/******************************************************************************/ +/*! + * Enable the specified QSPI controller interrupt status conditions identified + * in the mask. + * + * This function enables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of disabling it as a contributor to the \b + * ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. The function + * alt_qspi_int_disable() is used to disable status source conditions. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed + * \ref ALT_QSPI_INT_STATUS_t values that designate the status + * conditions to enable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_int_enable(const uint32_t mask); + +/******************************************************************************/ +/*! + * Returns true the serial interface and QSPI pipeline is IDLE. + * + * \returns Returns true the serial interface and QSPI pipeline is IDLE. + */ +bool alt_qspi_is_idle(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_GP_BLKIO General Purpose Block I/O + * + * The functions in this group provide general purpose block read and + * write flash functions. + * + * \internal + * These functions use Indirect Read/Write transfers to read and write block + * data to the flash device. An outline of the operational flow for these + * operations can be found in: + * //depot/soc/hhp_sw/baremetal_fw/drivers/qspi/qspi.c + * + * The general flow for an indirect block read is to call + * qspi_configure_mode_indirect_read_start() to initiate the read transfer from + * the flash device into the SRAM buffer and follow with a call to either + * qpsi_write_sram_fifo_poll() or qspi_read_sram_fifo_irq() to copy the data + * from SRAM into the user's buffer. + * + * The general flow for an indirect block write is to call + * qspi_configure_mode_indirect_write_start() to initiate the write transfer + * from the SRAM buffer to the flash device and follow with a call to either + * qpsi_write_sram_fifo_poll() or qspi_write_sram_fifo_irq() to fill the SRAM + * buffer with the user's data as space becomes available. + * \endinternal + * + * @{ + */ + +/******************************************************************************/ +/*! + * Read a block of data from the specified flash address. + * + * Reads a block of \e n data bytes from the flash \e src address into the user + * supplied \e dest buffer. The memory address, flash address, and size must be + * word aligned. + * + * \param dest + * The address of a caller supplied destination buffer large enough + * to contain the requested block of flash data. + * + * \param src + * The flash device address to start reading data from. + * + * \param size + * The requested number of data bytes to read from the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_read(void * dest, uint32_t src, size_t size); + +/******************************************************************************/ +/*! + * Write a block of data to the specified flash address. + * + * Writes a block of \e n data bytes to the flash \e dest address from the + * designated \e src buffer. The applicable destination flash address range + * should have been erased prior to calling this function. The flash address, + * memory address, and size must be word aligned. + * + * \param dest + * The destination flash address to begin writing data to. + * + * \param src + * The source address to start writing data from. + * + * \param size + * The requested number of data bytes to write to the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_write(uint32_t dest, const void * src, size_t size); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_DEV_CFG Flash Device Configuration + * + * The declarations and functions in this group are used to configure the QSPI + * controller interface to external flash devices. + * + * The following steps describe how to initialize and configure the + * QSPI controller to operate with a flash device. + * + * * Wait until any pending QSPI operations have completed. + * * Disable the QSPI controller using alt_qspi_disable(). + * * Configure the device for optimal read transaction performance using + * alt_qspi_device_read_config_set(). + * * Configure the device for optimal write transaction performance using + * alt_qspi_device_write_config_set(). + * * Enable (alt_qspi_mode_bit_disable()) or disable + * (alt_qspi_mode_bit_disable()) the mode bits per the device + * requirements. If mode bits are enabled, then configure the mode + * bit values using alt_qspi_mode_bit_config_set(). + * * Configure the device size and write protection information using + * alt_qspi_device_size_config_set(). + * * Configure the QSPI device delay and timing settings using + * alt_qspi_device_write_config_set(). + * * Configure the baud divisor setting to define the required clock frequency + * to the device using alt_qspi_baud_rate_div_set(). + * * Enable the QSPI controller using alt_qspi_enable(). + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type enumerates the operational modes the QSPI controller can be + * configured for. It may apply to instruction, address, and/or data width + * interactions between the QSPI controller and the flash device. + */ +typedef enum ALT_QSPI_MODE_e +{ + ALT_QSPI_MODE_SINGLE = 0, /*!< Use Standard Single SPI (SIO-SPI) mode (bits + * always transferred into the device on DQ0 + * only). Supported by all SPI flash devices. + */ + ALT_QSPI_MODE_DUAL = 1, /*!< Use Dual SPI (DIO-SPI) SPI mode where bits are + * transferred on DQ0 and DQ1. + */ + ALT_QSPI_MODE_QUAD = 2 /*!< Use Dual SPI (QIO-SPI) SPI mode where bits are + * transferred on DQ0, DQ1, DQ3, and DQ3. + */ +} ALT_QSPI_MODE_t; + +/******************************************************************************/ +/*! + * This type enumerates the mode configurations available for driving the + * ss_n[3:0] device chip selects. The chip selects may be controlled as either + * in a '1 of 4' or '4 to 16 decode' mode. + */ +typedef enum ALT_QSPI_CS_MODE_e +{ + ALT_QSPI_CS_MODE_SINGLE_SELECT = 0, /*!< Select 1 of 4 chip select ss_n[3:0] + */ + ALT_QSPI_CS_MODE_DECODE = 1 /*!< Select external 4 to 16 decode of + * ss_n[3:0]. + */ +} ALT_QSPI_CS_MODE_t; + +/******************************************************************************/ +/*! + * This type enumerates the QSPI controller master baud rate divisor selections. + */ +typedef enum ALT_QSPI_BAUD_DIV_e +{ + ALT_QSPI_BAUD_DIV_2 = 0x0, /*!< Divide by 2 */ + ALT_QSPI_BAUD_DIV_4 = 0x1, /*!< Divide by 4 */ + ALT_QSPI_BAUD_DIV_6 = 0x2, /*!< Divide by 6 */ + ALT_QSPI_BAUD_DIV_8 = 0x3, /*!< Divide by 8 */ + ALT_QSPI_BAUD_DIV_10 = 0x4, /*!< Divide by 10 */ + ALT_QSPI_BAUD_DIV_12 = 0x5, /*!< Divide by 12 */ + ALT_QSPI_BAUD_DIV_14 = 0x6, /*!< Divide by 14 */ + ALT_QSPI_BAUD_DIV_16 = 0x7, /*!< Divide by 16 */ + ALT_QSPI_BAUD_DIV_18 = 0x8, /*!< Divide by 18 */ + ALT_QSPI_BAUD_DIV_20 = 0x9, /*!< Divide by 20 */ + ALT_QSPI_BAUD_DIV_22 = 0xA, /*!< Divide by 22 */ + ALT_QSPI_BAUD_DIV_24 = 0xB, /*!< Divide by 24 */ + ALT_QSPI_BAUD_DIV_26 = 0xC, /*!< Divide by 26 */ + ALT_QSPI_BAUD_DIV_28 = 0xD, /*!< Divide by 28 */ + ALT_QSPI_BAUD_DIV_30 = 0xE, /*!< Divide by 30 */ + ALT_QSPI_BAUD_DIV_32 = 0xF /*!< Divide by 32 */ +} ALT_QSPI_BAUD_DIV_t; + +/******************************************************************************/ +/*! + * Device Size Configuration + * + * This type defines the structure used to specify flash device size and write + * protect regions. + */ +typedef struct ALT_QSPI_DEV_SIZE_CONFIG_s +{ + uint32_t block_size; /*!< Number of bytes per device block. The + * number is specified as a power of 2. + * That is 0 = 1 byte, 1 = 2 bytes, ... + * 16 = 65535 bytes, etc. + */ + uint32_t page_size; /*!< Number of bytes per device page. This + * is required by the controller for + * performing flash writes up to and + * across page boundaries. + */ + uint32_t addr_size; /*!< Number of bytes used for the flash + * address. The value is \e n + 1 + * based. That is 0 = 1 byte, 1 = 2 bytes, + * 2 = 3 bytes, 3 = 4 bytes. + */ + uint32_t lower_wrprot_block; /*!< The block number that defines the lower + * block in the range of blocks that is + * protected from writing. This field + * is ignored it write protection is + * disabled. + */ + uint32_t upper_wrprot_block; /*!< The block number that defines the upper + * block in the range of blocks that is + * protected from writing. This field + * is ignored it write protection is + * disabled. + */ + bool wrprot_enable; /*!< The write region enable value. A value + * of \b true enables write protection + * on the region specified by the + * \e lower_wrprot_block and + * \e upper_wrprot_block range. + */ +} ALT_QSPI_DEV_SIZE_CONFIG_t; + +/******************************************************************************/ +/*! + * This type enumerates the QSPI clock phase activity options outside the SPI + * word. + */ +typedef enum ALT_QSPI_CLK_PHASE_e +{ + ALT_QSPI_CLK_PHASE_ACTIVE = 0, /*!< The SPI clock is active outside the + * word + */ + ALT_QSPI_CLK_PHASE_INACTIVE = 1 /*!< The SPI clock is inactive outside the + * word + */ +} ALT_QSPI_CLK_PHASE_t; + +/******************************************************************************/ +/*! + * This type enumerates the QSPI clock polarity options outside the SPI word. + */ +typedef enum ALT_QSPI_CLK_POLARITY_e +{ + ALT_QSPI_CLK_POLARITY_LOW = 0, /*!< SPI clock is quiescent low outside the + * word. + */ + ALT_QSPI_CLK_POLARITY_HIGH = 1 /*!< SPI clock is quiescent high outside the + * word. + */ +} ALT_QSPI_CLK_POLARITY_t; + +/******************************************************************************/ +/*! + * QSPI Controller Timing Configuration + * + * This type defines the structure used to configure timing paramaters used by + * the QSPI controller to communicate with a target flash device. + * + * All timing values are defined in cycles of the SPI master ref clock. + */ +typedef struct ALT_QSPI_TIMING_CONFIG_s +{ + ALT_QSPI_CLK_PHASE_t clk_phase; /*!< Selects whether the clock is in an + * active or inactive phase outside the + * SPI word. + */ + + ALT_QSPI_CLK_POLARITY_t clk_pol; /*!< Selects whether the clock is quiescent + * low or high outside the SPI word. + */ + + uint32_t cs_da; /*!< Chip Select De-Assert. Added delay in + * master reference clocks for the length + * that the master mode chip select + * outputs are de-asserted between + * transactions. If CSDA = \e X, then the + * chip select de-assert time will be: 1 + * sclk_out + 1 ref_clk + \e X ref_clks. + */ + uint32_t cs_dads; /*!< Chip Select De-Assert Different + * Slaves. Delay in master reference + * clocks between one chip select being + * de-activated and the activation of + * another. This is used to ensure a quiet + * period between the selection of two + * different slaves. CSDADS is only + * relevant when switching between 2 + * different external flash devices. If + * CSDADS = \e X, then the delay will be: + * 1 sclk_out + 3 ref_clks + \e X + * ref_clks. + */ + uint32_t cs_eot; /*!< Chip Select End Of Transfer. Delay in + * master reference clocks between last + * bit of current transaction and + * de-asserting the device chip select + * (n_ss_out). By default (when CSEOT=0), + * the chip select will be de-asserted on + * the last falling edge of sclk_out at + * the completion of the current + * transaction. If CSEOT = \e X, then chip + * selected will de-assert \e X ref_clks + * after the last falling edge of + * sclk_out. + */ + uint32_t cs_sot; /*!< Chip Select Start Of Transfer. Delay in + * master reference clocks between setting + * n_ss_out low and first bit transfer. By + * default (CSSOT=0), chip select will be + * asserted half a SCLK period before the + * first rising edge of sclk_out. If CSSOT + * = \e X, chip select will be asserted + * half an sclk_out period before the + * first rising edge of sclk_out + \e X + * ref_clks. + */ + + uint32_t rd_datacap; /*!< The additional number of read data + * capture cycles (ref_clk) that should be + * applied to the internal read data + * capture circuit. The large + * clock-to-out delay of the flash memory + * together with trace delays as well as + * other device delays may impose a + * maximum flash clock frequency which is + * less than the flash memory device + * itself can operate at. To compensate, + * software should set this register to a + * value that guarantees robust data + * captures. + */ +} ALT_QSPI_TIMING_CONFIG_t; + +/******************************************************************************/ +/*! + * Device Instruction Configuration + * + * This type defines a structure for specifying the optimal instruction set + * configuration to use with a target flash device. + */ +typedef struct ALT_QSPI_DEV_INST_CONFIG_s +{ + uint32_t op_code; /*!< The read or write op code to use + * for the device transaction. + */ + ALT_QSPI_MODE_t inst_type; /*!< Instruction mode type for the + * controller to use with the + * device. The instruction type + * applies to all instructions + * (reads and writes) issued from + * either the Direct Access + * Controller or the Indirect + * Acces Controller. + */ + ALT_QSPI_MODE_t addr_xfer_type; /*!< Address transfer mode type. The + * value of this field is ignored + * if the \e inst_type data member + * is set to anything other than + * ALT_QSPI_MODE_SINGLE. In that + * case, the addr_xfer_type + * assumes the same mode as the \e + * inst_type. + */ + ALT_QSPI_MODE_t data_xfer_type; /*!< Data transfer mode type. The + * value of this field is ignored + * if the \e inst_type data member + * is set to anything other than + * ALT_QSPI_MODE_SINGLE. In that + * case, the data_xfer_type + * assumes the same mode as the \e + * inst_type. + */ + uint32_t dummy_cycles; /*!< Number of dummy clock cycles + * required by device for a read + * or write instruction. + */ + +} ALT_QSPI_DEV_INST_CONFIG_t; + +/******************************************************************************/ +/*! + * Get the current value of the QSPI master baud rate divisor. + * + * \returns The value of the QSPI master baud rate divisor. + */ +ALT_QSPI_BAUD_DIV_t alt_qspi_baud_rate_div_get(void); + +/******************************************************************************/ +/*! + * Set the current value of the QSPI master baud rate divisor. + * + * Sets the value of the QSPI master baud rate divisor. + * + * \param baud_rate_div + * The master baud rate divisor. Valid range includes + * even values 2 to 32. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_baud_rate_div_set(const ALT_QSPI_BAUD_DIV_t baud_rate_div); + +/******************************************************************************/ +/*! + * Get the current QSPI device peripheral chip select output and decode function + * configuration values. + * + * \param cs + * [out] The chip select line output values. + * + * \param cs_mode + * [out] The decode mode to use for the chip selects. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_chip_select_config_get(uint32_t* cs, ALT_QSPI_CS_MODE_t* cs_mode); + +/******************************************************************************/ +/*! + * Set the QSPI device peripheral chip select outputs and decode function + * configuration. + * + * The chip select lines output values operate according to the selected chip + * select decode mode. If \e cs_mode is ALT_QSPI_CS_MODE_SINGLE_SELECT then + * cs[3:0] are output thus: + * + * cs[3:0] | n_ss_out[3:0] + * :---------|:---------------------------- + * xxx0 | 1110 + * xx01 | 1101 + * x011 | 1011 + * 0111 | 0111 + * 1111 | 1111 (no peripheral selected) + * + * Otherwise if \e cs_mode is ALT_QSPI_CS_MODE_DECODE then cs[3:0] directly + * drives n_ss_out[3:0]. + * + * \param cs + * The chip select line output values. + * + * \param cs_mode + * The decode mode to use for the chip selects. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_chip_select_config_set(const uint32_t cs, + const ALT_QSPI_CS_MODE_t cs_mode); + +/******************************************************************************/ +/*! + * Disable the mode bits from being sent after the address bytes. + * + * Prevent the mode bits defined in the Mode Bit Configuration register from + * being sent following the address bytes. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_mode_bit_disable(void); + +/******************************************************************************/ +/*! + * Enable the mode bits to be sent after the address bytes. + * + * Ensure the mode bits defined in the Mode Bit Configuration register to + * be sent following the address bytes. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_mode_bit_enable(void); + +/******************************************************************************/ +/*! + * Get the current value of the Mode Bit Configuration register. + * + * \returns The 8 bit value that is sent to the device following the address + * bytes when the mode bit is enabled (see: alt_qspi_mode_bit_enable()) + */ +uint32_t alt_qspi_mode_bit_config_get(void); + +/******************************************************************************/ +/*! + * Set the value of the Mode Bit Configuration register. + * + * Set the value of the 8 bits that are sent to the device following the address + * bytes when the mode bit is enabled (see: alt_qspi_mode_bit_enable()) + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param mode_bits + * The 8 bit value sent to the device following the address bytes. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_mode_bit_config_set(const uint32_t mode_bits); + +/******************************************************************************/ +/*! + * Get the current flash device size and write protection configuration. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_DEV_SIZE_CONFIG_t structure to + * contain the returned flash device size and write protection + * configuration. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_size_config_get(ALT_QSPI_DEV_SIZE_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the flash device size and write protection configuration. + * + * \param cfg + * Pointer to a ALT_QSPI_DEV_SIZE_CONFIG_t structure containing the + * flash device size and write protection configuration. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_size_config_set(const ALT_QSPI_DEV_SIZE_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Get the current QSPI device read instruction configuration. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure to + * contain the returned QSPI controller instruction configuration + * used when performing read transactions with the device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_read_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the QSPI device read instruction configuration. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param cfg + * Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure specifying the + * desired op code, transfer widths, and dummy cycles for the QSPI + * controller to use when performing read transactions with the + * device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_read_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Get the current QSPI device write instruction configuration. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure to + * contain the returned QSPI controller instruction configuration + * used when performing write transactions with the device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_write_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the QSPI device write instruction configuration. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param cfg + * Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure specifying the + * desired op code, transfer widths, and dummy cycles for the QSPI + * controller to use when performing write transactions with the + * device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_write_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Get the QSPI device delay and timing configuration parameters. + * + * This function returns the settings of the chip select delay and timing + * configurations. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_TIMING_CONFIG_t structure to return + * the device timing and delay settings. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_timing_config_get(ALT_QSPI_TIMING_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the QSPI device delay and timing configuration parameters. + * + * This function allows the user to configure how the chip select is driven + * after each flash access. This is required as each device may have different + * timing requirements. As the serial clock frequency is increased, these + * timing parameters become more important and can be adjusted to meet the + * requirements of a specific flash device. All timings are defined in cycles + * of the SPI master ref clock. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param cfg + * Pointer to a ALT_QSPI_TIMING_CONFIG_t structure specifying the + * desired timing and delay settings. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_timing_config_set(const ALT_QSPI_TIMING_CONFIG_t * cfg); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_DAC Direct Access Mode + * + * In direct access mode, an access to the AHB data slave triggers a read or + * write command to the flash memory. To use the direct access mode, enable the + * direct access controller with the alt_qspi_direct_enable() function. An + * external master, for example a processor, triggers the direct access + * controller with a read or write operation to the AHB data slave + * interface. The data slave exposes a 1MB window into the flash device. You can + * remap this window to any 1MB location within the flash device address range. + * + * To remap the AHB data slave to access other 1MB regions of the flash device, + * enable address remapping by calling alt_qspi_ahb_address_remap_enable(). All + * incoming data slave accesses remap to the offset specified in the remap + * address register which is configured by alt_qspi_ahb_remap_address_set(). + * + * The 20 LSBs of incoming addresses are used for accessing the 1MB region and + * the higher bits are ignored. + * + * The quad SPI controller does not issue any error status for accesses that lie + * outside the connected flash memory space. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Disable the QSPI Direct Access Controller. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_direct_disable(void); + +/******************************************************************************/ +/*! + * Enable the QSPI Direct Access Controller. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_direct_enable(void); + +/******************************************************************************/ +/*! + * Get the current AHB address remap value. + * + * Returns the current value of the AHB remap address register. + * + * \returns The value used to remap an incoming AHB address to a + * different address used by the flash device. + */ +uint32_t alt_qspi_ahb_remap_address_get(void); + +/******************************************************************************/ +/*! + * Set the AHB address remap value. + * + * Sets the value of the AHB remap address register. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param ahb_remap_addr + * The value used to remap an incoming AHB address to a different + * address used by the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_ahb_remap_address_set(const uint32_t ahb_remap_addr); + +/******************************************************************************/ +/*! + * Disable AHB address remapping. + * + * Disables remapping of incoming AHB addresses so they are sent unmodified to + * the flash device. The incoming AHB address maps directly to the address + * serially sent to the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_ahb_address_remap_disable(void); + +/******************************************************************************/ +/*! + * Enable AHB address remapping. + * + * Enables remapping of incoming AHB addresses so they are modified to + * \ + \e N, where \e N is the configured remap address value. + * + * See: alt_qspi_ahb_remap_address_set(). + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_ahb_address_remap_enable(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_INDAC Indirect Access Mode + * + * In indirect access mode, flash data is temporarily buffered in the QSPI + * controller's SRAM. Software controls and triggers indirect accesses through + * the APB register slave interface. The controller transfers data through the + * AHB data slave interface. + * + * An indirect read operation reads data from the flash memory, places the data + * into the SRAM, and transfers the data to an external master through the AHB + * data slave interface. + * + * An indirect write operation programs data from the SRAM to the flash memory. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Starts an indirect read transfer. + * + * Initiates an indirect read transfer of the requested number of bytes from the + * designated flash address. + * + * After calling this function, flash data may be read from the QSPI SRAM buffer + * as it becomes available via one of the following methods: + * * Directly from the AHB data slave interface at the configured AHB trigger + * address. If the requested data is not immediately available in the SRAM + * buffer then AHB wait states will be applied until the data has been read + * from flash into the SRAM buffer. Alternatively, data may be read from the + * AHB data slave as the SRAM is filled. The availability of data in the SRAM + * buffer may be determined by an SRAM watermark interrupt notification or by + * polling the SRAM fill level. + * * Configuring and enabling the QSPI DMA peripheral controller. + * + * The following is a list of restrictions: + * * flash_addr must be word aligned. + * * num_bytes must be word aligned. + * * The transfer must not cross the 3-byte addressing boundary. This + * restriction may be device specific and may be lifted in the future. + * + * \param flash_addr + * The flash source address to read data from. + * + * \param num_bytes + * The number of bytes to read from the flash source address. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_start(const uint32_t flash_addr, + const size_t num_bytes); + +/******************************************************************************/ +/*! + * Finish the indirect read operation that was completed or canceled. This + * function should be called before another indirect read is started. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_finish(void); + +/******************************************************************************/ +/*! + * Cancel all indirect read transfers in progress. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_cancel(void); + +/******************************************************************************/ +/*! + * Get the current indirect read SRAM fill level value. + * + * Returns the SRAM fill level for the indirect read partition in units of SRAM + * words (4 bytes). + * + * \returns The SRAM fill level for the indirect read partition in units of + * SRAM words (4 bytes). + */ +uint32_t alt_qspi_indirect_read_fill_level(void); + +/******************************************************************************/ +/*! + * Get the current indirect read watermark value. + * + * The watermark value (in bytes) represents the minimum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level passes + * the watermark, an interrupt source is also generated. This can be disabled by + * writing a value of all zeroes. + * + * \returns The current indirect read watermark value. + */ +uint32_t alt_qspi_indirect_read_watermark_get(void); + +/******************************************************************************/ +/*! + * Set the indirect read watermark value. + * + * The watermark value (in bytes) represents the minimum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level passes + * the watermark, an interrupt source is also generated. This can be disabled by + * writing a value of all zeroes. The watermark can only be set when no indirect + * read is in progress. + * + * \param watermark + * The watermark value (in bytes). + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_watermark_set(const uint32_t watermark); + +/******************************************************************************/ +/*! + * Returns true when an indirect read has completed otherwise false. + * + * \internal + * Returns Indirect Read Transfer Control Register bit 5 "Indirect Completion Status". + * \endinternal + * + * \returns Returns true when an indirect read has completed otherwise false. + */ +bool alt_qspi_indirect_read_is_complete(void); + +/******************************************************************************/ +/*! + * Starts an indirect write transfer. + * + * Initiates an indirect write transfer of the requested number of bytes to the + * designated flash address. + * + * After calling this function, flash data may be written to the QSPI SRAM + * buffer there is space via one of the following methods: + * * Directly from the AHB data slave interface at the configured AHB trigger + * address. If the requested space is not immediately available in the SRAM + * buffer then AHB wait states will be applied until the space becomes + * available. Alternatively, the data may be written to the AHB data slave + * as the SRAM is drained. The space in the SRAM buffer may be determined by + * an SRAM watermark interrupt notification or by polling the SRAM fill + * level and subtracting that value from the SRAM space devoted to writes. + * * Configuring and enabling the QSPI DMA peripheral controller. + * + * The following is a list of restrictions: + * * flash_addr must be word aligned. + * * num_bytes must be word aligned. + * * num_bytes must be 256 or below. This is due to a device specific + * limitation and may be lifted in the future. + * * The transfer must not cross the page (256 byte) addressing boundary. This + * restriction may be device specific and may be lifted in the future. + * + * \param flash_addr + * The flash destination address to write data to. + * + * \param num_bytes + * The number of bytes to write to the flash. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_start(const uint32_t flash_addr, + const size_t num_bytes); + +/******************************************************************************/ +/*! + * Finish the indirect write operation that was completed or canceled. This + * function should be called before another indirect write is started. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_finish(void); + +/******************************************************************************/ +/*! + * Cancel all indirect write transfers in progress. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_cancel(void); + +/******************************************************************************/ +/*! + * Get the current indirect write SRAM fill level value. + * + * Returns the SRAM fill level for the indirect write partition in units of SRAM + * words (4 bytes). + * + * \returns The SRAM fill level for the indirect write partition in units of + * SRAM words (4 bytes). + */ +uint32_t alt_qspi_indirect_write_fill_level(void); + +/******************************************************************************/ +/*! + * Get the current indirect write watermark value. + * + * The watermark value (in bytes) represents the maximum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level falls + * below the watermark, an interrupt is also generated. This can be disabled by + * writing a value of all ones. + * + * \returns The current indirect write watermark value. + */ +uint32_t alt_qspi_indirect_write_watermark_get(void); + +/******************************************************************************/ +/*! + * Set the indirect write watermark value. + * + * The watermark value (in bytes) represents the maximum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level falls + * below the watermark, an interrupt is also generated. This can be disabled by + * writing a value of all ones. The watermark can only be set when no indirect + * write is in progress. + * + * \param watermark + * The watermark value (in bytes). + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_watermark_set(const uint32_t watermark); + +/******************************************************************************/ +/*! + * Returns true when an indirect write has completed otherwise false. + * + * \internal + * Returns Indirect Write Transfer Control Register bit 5 "Indirect Completion + * Status". + * \endinternal + * + * \returns Returns true when an indirect write has completed otherwise + * false. + */ +bool alt_qspi_indirect_write_is_complete(void); + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_CFG_SRAM SRAM Partition + * + * The SRAM local memory buffer is a 128 by 32-bit (512 total bytes) memory. The + * SRAM has two partitions, with the lower partition reserved for indirect read + * operations and the upper partition for indirect write operations. The size of + * the partitions is specified in the SRAM partition register, based on 32-bit + * word sizes. For example, to specify four bytes of storage, write the value 1. + * The value written to the indirect read partition size field ( addr ) defines + * the number of entries reserved for indirect read operations. For example, write + * the value 32 (0x20) to partition the 128-entry SRAM to 32 entries (25%) for + * read usage and 96 entries (75%) for write usage. + * + * The functions in this section provide accces to configure the SRAM read + * partition allocation. + * + * @{ + */ + +/*! + * The size of the onboard SRAM in bytes. + */ +#define ALT_QSPI_SRAM_FIFO_SIZE (512) + +/* + * The size of the onboard SRAM in entries. Each entry is word (32-bit) sized. + */ +#define ALT_QSPI_SRAM_FIFO_ENTRY_COUNT (512 / sizeof(uint32_t)) + +/******************************************************************************/ +/*! + * Get the entry count (words) of the indirect read partition in the QSPI + * controller SRAM. + * + * There is an additional word of read memory not in the SRAM but used to + * buffer the SRAM and the AHB. As such, the total on board memory buffer for + * indirect read is 1 more than the value reported by this function. + * + * \returns The count of 32-bit words of the indirect read partition in the + * QSPI controller SRAM. + * + * \internal + * The documentation states that the number of locations allocated to indirect + * read = SRAM_PARTITION_REG + 1. Cadence clarified that the +1 comes from an + * additional register slice for read's, implemented in FLOPs, which was done + * to avoid connection the SRAM directly to the AHB interface. This was done + * for performance / timing reasons. The +1 will not be included in the return + * value but documented as an additional entry. + * \endinternal + */ +uint32_t alt_qspi_sram_partition_get(void); + +/******************************************************************************/ +/*! + * Set the entry count (words) of the indirect read partition in the QSPI + * controller SRAM. + * + * Note: It is recommended that setting SRAM partition to 0 or 127 should be + * avoided although it is not prohibited. + * + * \param read_part_size + * The count of 32-bit words to allocate to the indirect read + * partition in the QSPI controller SRAM. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_sram_partition_set(const uint32_t read_part_size); + +/*! @} */ + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_ERASE Flash Erase + * + * The functions in this group are used to erase selected portions of a flash + * device. + * @{ + */ + +/******************************************************************************/ +/*! + * This function erases the designated flash device subsector. + * + * This function erases the flash device subsector containing the designated + * flash address. Any address within the subsector is valid. + * + * \param addr + * A flash address contained within the the subsector to be erased. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_erase_subsector(const uint32_t addr); + +/******************************************************************************/ +/*! + * This function erases the designated flash device sector. + * + * This function erases the flash device sector containing the designated flash + * address. Any address within the sector is valid. + * + * \param addr + * A flash address contained within the the sector to be erased. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_erase_sector(const uint32_t addr); + +/******************************************************************************/ +/*! + * This function erases the entire flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_erase_chip(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_DMA DMA Peripheral Interface + * + * The DMA peripheral request controller is only used for the indirect mode of + * operation where data is temporarily stored in the SRAM. The QSPI flash + * controller uses the DMA peripheral request interface to trigger the external + * DMA into performing data transfers between memory and the QSPI + * controller. + * + * There are two DMA peripheral request interfaces, one for indirect reads and + * one for indirect writes. The DMA peripheral request controller can issue two + * types of DMA requests, single or burst, to the external DMA. The number of + * bytes for each single or burst request is specified using the + * alt_qspi_dma_config_set(). The DMA peripheral request controller splits the + * total amount of data to be transferred into a number of DMA burst and single + * requests by dividing the total number of bytes by the number of bytes + * specified in the burst request, and then dividing the remainder by the number + * of bytes in a single request. + * + * When programming the DMA controller, the burst request size must match the + * burst request size set in the quad SPI controller to avoid quickly reaching + * an overflow or underflow condition. + * @{ + */ + +/******************************************************************************/ +/*! + * Disable the QSPI DMA peripheral interface. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_disable(void); + +/******************************************************************************/ +/*! + * Enable the QSPI DMA peripheral interface. + * + * Enable the QSPI DMA handshaking logic. When enabled the QSPI will trigger DMA + * transfer requests via the DMA peripheral interface. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_enable(void); + +/******************************************************************************/ +/*! + * Get the current DMA peripheral configuration. + * + * This function returns the QSPI DMA peripheral interface single and burst type + * transfer size configurations. + * + * \param single_type_sz + * [out] The number of bytes for each DMA single type + * request. Value must be a power of 2 between 1 and 32728. + * + * \param burst_type_sz + * [out] The number of bytes for each DMA burst type request. Value + * must be a power of 2 between 1 and 32728. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_config_get(uint32_t * single_type_sz, + uint32_t * burst_type_sz); + +/******************************************************************************/ +/*! + * Set the DMA peripheral configuration. + * + * This function configures the QSPI DMA peripheral interface single and burst + * type transfer sizes. The DMA configruation should be setup while the + * controller is idle. Because all transfers are required to be word aligned, + * the smallest DMA request is 4 bytes. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param single_type_sz + * The number of bytes for each DMA single type request. Value must + * be a power of 2 between 4 and 32768. + * + * \param burst_type_sz + * The number of bytes for each DMA burst type request. Value must + * be a power of 2 between 4 and 32768. Bursts must be equal or + * larger than single requests. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_config_set(const uint32_t single_type_sz, + const uint32_t burst_type_sz); + + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_QSPI_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi_private.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi_private.h new file mode 100644 index 0000000..21fd3a9 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi_private.h @@ -0,0 +1,167 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! \file + * Altera - QSPI Flash Controller Module + */ + +#ifndef __ALT_QSPI_PRIVATE_H__ +#define __ALT_QSPI_PRIVATE_H__ + +#include "socal/socal.h" + +// +// This section provisions support for various flash devices. +// + +#define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1 + +///// + +#define ALT_QSPI_PAGE_ADDR_MSK 0xFFFFFF00 +#define ALT_QSPI_PAGE_SIZE 0x00000100 // 256 B +#define ALT_QSPI_SUBSECTOR_ADDR_MSK 0xFFFFF000 +#define ALT_QSPI_SUBSECTOR_SIZE 0x00001000 // 4096 B +#define ALT_QSPI_SECTOR_ADDR_MSK 0xFFFF0000 +#define ALT_QSPI_SECTOR_SIZE 0x00010000 // 64 KiB +#define ALT_QSPI_BANK_ADDR_MSK 0xFF000000 +#define ALT_QSPI_BANK_SIZE 0x01000000 // 16 MiB + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +#define ALT_QSPI_N25Q_DIE_ADDR_MSK 0xFE000000 +#define ALT_QSPI_N25Q_DIE_SIZE 0x02000000 // 32 MiB +#endif + +///// + +// Default delay timing (in ns) for N25Q. +// These values are from the N25Q handbook. The timing correctness is difficult +// to test because the test setup does not feature mutliple chips. +#define ALT_QSPI_TSHSL_NS_DEF (50) +#define ALT_QSPI_TSD2D_NS_DEF (0) +#define ALT_QSPI_TCHSH_NS_DEF (4) +#define ALT_QSPI_TSLCH_NS_DEF (4) + +/* +// Default delay timing (in ns) +#define ALT_QSPI_TSHSL_NS_DEF (200) +#define ALT_QSPI_TSD2D_NS_DEF (255) +#define ALT_QSPI_TCHSH_NS_DEF (20) +#define ALT_QSPI_TSLCH_NS_DEF (20) +*/ + +// Flash commands +#define ALT_QSPI_STIG_OPCODE_READ (0x03) +#define ALT_QSPI_STIG_OPCODE_4BYTE_READ (0x13) +#define ALT_QSPI_STIG_OPCODE_FASTREAD (0x0B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO (0xBB) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO (0xEB) +#define ALT_QSPI_STIG_OPCODE_PP (0x02) +#define ALT_QSPI_STIG_OPCODE_DUAL_PP (0xA2) +#define ALT_QSPI_STIG_OPCODE_QUAD_PP (0x32) +#define ALT_QSPI_STIG_OPCODE_RDID (0x9F) +#define ALT_QSPI_STIG_OPCODE_WREN (0x06) +#define ALT_QSPI_STIG_OPCODE_WRDIS (0x04) +#define ALT_QSPI_STIG_OPCODE_RDSR (0x05) +#define ALT_QSPI_STIG_OPCODE_WRSR (0x01) +#define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE (0x20) +#define ALT_QSPI_STIG_OPCODE_SEC_ERASE (0xD8) +#define ALT_QSPI_STIG_OPCODE_BULK_ERASE (0xC7) +#define ALT_QSPI_STIG_OPCODE_DIE_ERASE (0xC4) +#define ALT_QSPI_STIG_OPCODE_CHIP_ERASE (0x60) +#define ALT_QSPI_STIG_OPCODE_RD_EXT_REG (0xC8) +#define ALT_QSPI_STIG_OPCODE_WR_EXT_REG (0xC5) +#define ALT_QSPI_STIG_OPCODE_RD_STAT_REG (0x05) +#define ALT_QSPI_STIG_OPCODE_WR_STAT_REG (0x01) +#define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE (0xB7) +#define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE (0xE9) + +// Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts. +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +#define ALT_QSPI_STIG_OPCODE_RESET_EN (0x66) +#define ALT_QSPI_STIG_OPCODE_RESET_MEM (0x99) +#define ALT_QSPI_STIG_OPCODE_RDFLGSR (0x70) +#define ALT_QSPI_STIG_OPCODE_CLRFLGSR (0x50) +#define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM (0x5A) +#endif + +// Spansion commands +// #define OPCODE_ECRM (0xFF) // Exit continuous read mode + +#define QSPI_READ_CLK_MHZ (50) +#define QSPI_FASTREAD_CLK_MHZ (100) + +// Manufacturer ID +#define ALT_QSPI_STIG_RDID_JEDECID_MICRON (0x20) +#define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX (0x20) // Same as Micron +#define ALT_QSPI_STIG_RDID_JEDECID_SPANSION (0xEF) +#define ALT_QSPI_STIG_RDID_JEDECID_WINBOND (0xEF) // Same as Spansion +#define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC (0xC2) +#define ALT_QSPI_STIG_RDID_JEDECID_ATMEL (0x1F) + +#define ALT_QSPI_STIG_RDID_JEDECID_GET(value) ((value >> 0) & 0xff) +#define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff) + +#define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value) ((value >> 5) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value) ((value >> 4) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value) ((value >> 1) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value) ((value >> 0) & 0x1) + +#define ALT_QSPI_STIG_SR_BUSY_GET(value) ((value >> 0) & 0x1) + +///// + +#define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff) + +ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size); + +ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy, + uint32_t num_bytes, uint32_t * output, + uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy, + uint32_t num_bytes, const uint32_t * input, + uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy, + uint32_t address, + uint32_t timeout); + +ALT_STATUS_CODE alt_qspi_device_wren(void); +ALT_STATUS_CODE alt_qspi_device_wrdis(void); +ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid); +ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param); +ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank); + +#endif // __ALT_PRIVATE_QSPI_H__ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmanonsecure.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmanonsecure.h new file mode 100644 index 0000000..1425708 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmanonsecure.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_DMANONSECURE */ + +#ifndef __ALTERA_ALT_DMANONSECURE_H__ +#define __ALTERA_ALT_DMANONSECURE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : nonsecure DMA Module Address Space - ALT_DMANONSECURE + * nonsecure DMA Module Address Space + * + * Address space allocated to the nonsecure DMA. For detailed information about the + * use of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click + * here[/url] to access the ARM documentation for the DMA-330. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_MSB 31 +/* The width in bits of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_DMANONSECURE_REG_FLD register field value. */ +#define ALT_DMANONSECURE_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_DMANONSECURE_REG_FLD register field value. */ +#define ALT_DMANONSECURE_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_DMANONSECURE_REG_FLD register field is UNKNOWN. */ +#define ALT_DMANONSECURE_REG_FLD_RESET 0x0 +/* Extracts the ALT_DMANONSECURE_REG_FLD field value from a register. */ +#define ALT_DMANONSECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_DMANONSECURE_REG_FLD register field value suitable for setting the register. */ +#define ALT_DMANONSECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_DMANONSECURE_REG. + */ +struct ALT_DMANONSECURE_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_DMANONSECURE_REG. */ +typedef volatile struct ALT_DMANONSECURE_REG_s ALT_DMANONSECURE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_DMANONSECURE_REG register from the beginning of the component. */ +#define ALT_DMANONSECURE_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_DMANONSECURE. + */ +struct ALT_DMANONSECURE_s +{ + volatile ALT_DMANONSECURE_REG_t reg; /* ALT_DMANONSECURE_REG */ +}; + +/* The typedef declaration for register group ALT_DMANONSECURE. */ +typedef volatile struct ALT_DMANONSECURE_s ALT_DMANONSECURE_t; +/* The struct declaration for the raw register contents of register group ALT_DMANONSECURE. */ +struct ALT_DMANONSECURE_raw_s +{ + volatile uint32_t reg; /* ALT_DMANONSECURE_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_DMANONSECURE. */ +typedef volatile struct ALT_DMANONSECURE_raw_s ALT_DMANONSECURE_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_DMANONSECURE_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmasecure.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmasecure.h new file mode 100644 index 0000000..5941433 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmasecure.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_DMASECURE */ + +#ifndef __ALTERA_ALT_DMASECURE_H__ +#define __ALTERA_ALT_DMASECURE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : secure DMA Module Address Space - ALT_DMASECURE + * secure DMA Module Address Space + * + * Address space allocated to the secure DMA. For detailed information about the + * use of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click + * here[/url] to access the ARM documentation for the DMA-330. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_MSB 31 +/* The width in bits of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_DMASECURE_REG_FLD register field value. */ +#define ALT_DMASECURE_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_DMASECURE_REG_FLD register field value. */ +#define ALT_DMASECURE_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_DMASECURE_REG_FLD register field is UNKNOWN. */ +#define ALT_DMASECURE_REG_FLD_RESET 0x0 +/* Extracts the ALT_DMASECURE_REG_FLD field value from a register. */ +#define ALT_DMASECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_DMASECURE_REG_FLD register field value suitable for setting the register. */ +#define ALT_DMASECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_DMASECURE_REG. + */ +struct ALT_DMASECURE_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_DMASECURE_REG. */ +typedef volatile struct ALT_DMASECURE_REG_s ALT_DMASECURE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_DMASECURE_REG register from the beginning of the component. */ +#define ALT_DMASECURE_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_DMASECURE. + */ +struct ALT_DMASECURE_s +{ + volatile ALT_DMASECURE_REG_t reg; /* ALT_DMASECURE_REG */ +}; + +/* The typedef declaration for register group ALT_DMASECURE. */ +typedef volatile struct ALT_DMASECURE_s ALT_DMASECURE_t; +/* The struct declaration for the raw register contents of register group ALT_DMASECURE. */ +struct ALT_DMASECURE_raw_s +{ + volatile uint32_t reg; /* ALT_DMASECURE_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_DMASECURE. */ +typedef volatile struct ALT_DMASECURE_raw_s ALT_DMASECURE_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_DMASECURE_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspi.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspi.h new file mode 100644 index 0000000..cbec31b --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspi.h @@ -0,0 +1,5951 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_QSPI */ + +#ifndef __ALTERA_ALT_QSPI_H__ +#define __ALTERA_ALT_QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : QSPI Flash Controller Module Registers - ALT_QSPI + * QSPI Flash Controller Module Registers + * + * Registers in the QSPI Flash Controller module accessible via its APB slave + * + */ +/* + * Register : QSPI Configuration Register - cfg + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------- + * [0] | RW | 0x0 | QSPI Enable + * [1] | RW | 0x0 | Clock Polarity + * [2] | RW | 0x0 | Select Clock Phase + * [6:3] | ??? | 0x0 | *UNDEFINED* + * [7] | RW | 0x0 | Enable Direct Access Controller + * [8] | RW | 0x0 | Legacy IP Mode Enable + * [9] | RW | 0x0 | Peripheral select decode + * [13:10] | RW | 0x0 | Peripheral Chip Select Lines + * [14] | RW | 0x0 | Write Protect Flash Pin + * [15] | RW | 0x0 | Enable DMA Peripheral Interface + * [16] | RW | 0x0 | Enable AHB Address Re-mapping + * [17] | RW | 0x0 | Enter XIP Mode on next READ + * [18] | RW | 0x0 | Enter XIP Mode Immediately + * [22:19] | RW | 0xf | Master Mode Baud Rate Divisor + * [30:23] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x0 | Serial interface and QSPI pipeline is IDLE + * + */ +/* + * Field : QSPI Enable - en + * + * If this bit is disabled, the QSPI will finish the current transfer of the data + * word (FF_W) and stop sending. When Enabled, and qspi_n_mo_en = 0, all output + * enables are inactive and all pins are set to input mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------|:------|:----------------- + * ALT_QSPI_CFG_EN_E_DIS | 0x0 | Disable the QSPI + * ALT_QSPI_CFG_EN_E_EN | 0x1 | Enable the QSPI + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_EN + * + * Disable the QSPI + */ +#define ALT_QSPI_CFG_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_EN + * + * Enable the QSPI + */ +#define ALT_QSPI_CFG_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_MSB 0 +/* The width in bits of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_EN register field value. */ +#define ALT_QSPI_CFG_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_CFG_EN register field value. */ +#define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_EN field value from a register. */ +#define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Clock Polarity - selclkpol + * + * Controls spiclk modes of operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------- + * ALT_QSPI_CFG_SELCLKPOL_E_LOW | 0x1 | SPI clock is quiescent low + * ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0 | SPI clock is quiescent high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL + * + * SPI clock is quiescent low + */ +#define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL + * + * SPI clock is quiescent high + */ +#define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_MSB 1 +/* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */ +#define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */ +#define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */ +#define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Select Clock Phase - selclkphase + * + * Selects whether the clock is in an active or inactive phase outside the SPI + * word. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:--------------------------- + * ALT_QSPI_CFG_SELCLKPHASE_E_ACT | 0x0 | SPI clock is quiescent low + * ALT_QSPI_CFG_SELCLKPHASE_E_INACT | 0x1 | Clock Inactive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE + * + * SPI clock is quiescent low + */ +#define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE + * + * Clock Inactive + */ +#define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_MSB 2 +/* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */ +#define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */ +#define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */ +#define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Enable Direct Access Controller - endiracc + * + * If disabled, the Direct Access Controller becomes inactive once the current + * transfer of the data word (FF_W) is complete. When the Direct Access Controller + * and Indirect Access Controller are both disabled, all AHB requests are completed + * with an error response. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_QSPI_CFG_ENDIRACC_E_DIS | 0x0 | Disable Direct Access Ctrl + * ALT_QSPI_CFG_ENDIRACC_E_EN | 0x1 | Enable Direct Access Ctrl + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC + * + * Disable Direct Access Ctrl + */ +#define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC + * + * Enable Direct Access Ctrl + */ +#define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_MSB 7 +/* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */ +#define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */ +#define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */ +#define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Legacy IP Mode Enable - enlegacyip + * + * This bit can select the Direct Access Controller/Indirect Access Controller or + * legacy mode.If legacy mode is selected, any write to the controller via the AHB + * interface is serialized and sent to the FLASH device. Any valid AHB read will + * pop the internal RX-FIFO, retrieving data that was forwarded by the external + * FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and + * controlled via the HSIZE input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------------------------------- + * ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD | 0x1 | Legacy Mode + * ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD | 0x0 | Use Direct/Indirect Access Controller + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP + * + * Legacy Mode + */ +#define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP + * + * Use Direct/Indirect Access Controller + */ +#define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_MSB 8 +/* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */ +#define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */ +#define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */ +#define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Peripheral select decode - perseldec + * + * Select between '1 of 4 selects' or 'external 4-to-16 decode'. The + * qspi_n_ss_out[3:0] output signals are controlled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------- + * ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1 | Select external 4-to-16 decode + * ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 | 0x0 | Selects 1 of 4 qspi_n_ss_out[3:0] + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC + * + * Select external 4-to-16 decode + */ +#define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC + * + * Selects 1 of 4 qspi_n_ss_out[3:0] + */ +#define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_MSB 9 +/* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */ +#define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */ +#define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */ +#define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Peripheral Chip Select Lines - percslines + * + * Peripheral chip select line output decode type. As per perseldec, if perseldec = + * 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The + * asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0] + * require an external 4 to 16 decoder. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_MSB 13 +/* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_WIDTH 4 +/* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */ +#define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00 +/* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */ +#define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff +/* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */ +#define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10) +/* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00) + +/* + * Field : Write Protect Flash Pin - wp + * + * This bit controls the write protect pin of the flash devices. The signal + * qspi_mo2_wpn needs to be resynchronized to the generated memory clock as + * necessary. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------- + * ALT_QSPI_CFG_WP_E_WRPROTON | 0x1 | Enable Write Protect + * ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0 | Disable Write Protect + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_WP + * + * Enable Write Protect + */ +#define ALT_QSPI_CFG_WP_E_WRPROTON 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_WP + * + * Disable Write Protect + */ +#define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_MSB 14 +/* The width in bits of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_WP register field value. */ +#define ALT_QSPI_CFG_WP_SET_MSK 0x00004000 +/* The mask used to clear the ALT_QSPI_CFG_WP register field value. */ +#define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff +/* The reset value of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_WP field value from a register. */ +#define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Enable DMA Peripheral Interface - endma + * + * Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer + * requests via the DMA peripheral interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------- + * ALT_QSPI_CFG_ENDMA_E_EN | 0x1 | Enable DMA Mode + * ALT_QSPI_CFG_ENDMA_E_DIS | 0x0 | Disable DMA Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDMA + * + * Enable DMA Mode + */ +#define ALT_QSPI_CFG_ENDMA_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDMA + * + * Disable DMA Mode + */ +#define ALT_QSPI_CFG_ENDMA_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_MSB 15 +/* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */ +#define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000 +/* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */ +#define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff +/* The reset value of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */ +#define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Enable AHB Address Re-mapping - enahbremap + * + * (Direct Access Mode Only) When enabled, the incoming AHB address will be adapted + * and sent to the FLASH device as (address + N), where N is the value stored in + * the remap address register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------- + * ALT_QSPI_CFG_ENAHBREMAP_E_EN | 0x1 | Enable AHB Re-mapping + * ALT_QSPI_CFG_ENAHBREMAP_E_DIS | 0x0 | Disable AHB Re-mapping + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP + * + * Enable AHB Re-mapping + */ +#define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP + * + * Disable AHB Re-mapping + */ +#define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_MSB 16 +/* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */ +#define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000 +/* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */ +#define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff +/* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */ +#define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Enter XIP Mode on next READ - enterxipnextrd + * + * If XIP is enabled, then setting to disabled will cause the controller to exit + * XIP mode on the next READ instruction. If XIP is disabled, then setting to + * enabled will inform the controller that the device is ready to enter XIP on the + * next READ instruction. The controller will therefore send the appropriate + * command sequence, including mode bits to cause the device to enter XIP mode. Use + * this register after the controller has ensured the FLASH device has been + * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit + * should be set to 0. This will take effect in the attached device only AFTER the + * next READ instruction is executed. Software should therefore ensure that at + * least one READ instruction is requested after resetting this bit before it can + * be sure XIP mode in the device is exited. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------- + * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN | 0x1 | Enter XIP Mode on next READ instruction + * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS | 0x0 | Exit XIP Mode on next READ instruction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD + * + * Enter XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD + * + * Exit XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17 +/* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000 +/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff +/* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Enter XIP Mode Immediately - enterxipimm + * + * If XIP is enabled, then setting to disabled will cause the controller to exit + * XIP mode on the next READ instruction. If XIP is disabled, then setting enable + * will operate the device in XIP mode immediately. Use this register when the + * external device wakes up in XIP mode (as per the contents of its non- volatile + * configuration register). The controller will assume the next READ instruction + * will be passed to the device as an XIP instruction, and therefore will not + * require the READ opcode to be transferred. Note: To exit XIP mode, this bit + * should be set to 0. This will take effect in the attached device only after the + * next READ instruction is executed. Software therefore should ensure that at + * least one READ instruction is requested after resetting this bit in order to be + * sure that XIP mode is exited. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:--------------------------------------- + * ALT_QSPI_CFG_ENTERXIPIMM_E_EN | 0x1 | Enter XIP Mode immediately + * ALT_QSPI_CFG_ENTERXIPIMM_E_DIS | 0x0 | Exit XIP Mode on next READ instruction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM + * + * Enter XIP Mode immediately + */ +#define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM + * + * Exit XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18 +/* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000 +/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff +/* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Master Mode Baud Rate Divisor - bauddiv + * + * SPI baud rate = ref_clk / (2 * baud_rate_divisor) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_QSPI_CFG_BAUDDIV_E_BAUD2 | 0x0 | Baud Rate Div/2 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD4 | 0x1 | Baud Rate Div/4 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD6 | 0x2 | Baud Rate Div/6 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD8 | 0x3 | Baud Rate Div/8 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4 | Baud Rate Div/10 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5 | Baud Rate Div/12 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6 | Baud Rate Div/14 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7 | Baud Rate Div/16 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8 | Baud Rate Div/18 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9 | Baud Rate Div/20 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa | Baud Rate Div/22 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb | Baud Rate Div/24 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc | Baud Rate Div/26 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd | Baud Rate Div/28 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe | Baud Rate Div/30 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf | Baud Rate Div/32 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/2 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/4 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/6 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/8 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/10 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/12 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/14 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/16 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/18 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/20 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/22 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/24 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/26 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/28 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/30 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/32 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_MSB 22 +/* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_WIDTH 4 +/* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */ +#define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000 +/* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */ +#define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff +/* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_RESET 0xf +/* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */ +#define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19) +/* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000) + +/* + * Field : Serial interface and QSPI pipeline is IDLE - idle + * + * This is a STATUS read-only bit. Note this is a retimed signal, so there will be + * some inherent delay on the generation of this status signal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------- + * ALT_QSPI_CFG_IDLE_E_SET | 0x1 | Idle Mode + * ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0 | Non-Idle Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_IDLE + * + * Idle Mode + */ +#define ALT_QSPI_CFG_IDLE_E_SET 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_IDLE + * + * Non-Idle Mode + */ +#define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_MSB 31 +/* The width in bits of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */ +#define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */ +#define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */ +#define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_CFG. + */ +struct ALT_QSPI_CFG_s +{ + uint32_t en : 1; /* QSPI Enable */ + uint32_t selclkpol : 1; /* Clock Polarity */ + uint32_t selclkphase : 1; /* Select Clock Phase */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t endiracc : 1; /* Enable Direct Access Controller */ + uint32_t enlegacyip : 1; /* Legacy IP Mode Enable */ + uint32_t perseldec : 1; /* Peripheral select decode */ + uint32_t percslines : 4; /* Peripheral Chip Select Lines */ + uint32_t wp : 1; /* Write Protect Flash Pin */ + uint32_t endma : 1; /* Enable DMA Peripheral Interface */ + uint32_t enahbremap : 1; /* Enable AHB Address Re-mapping */ + uint32_t enterxipnextrd : 1; /* Enter XIP Mode on next READ */ + uint32_t enterxipimm : 1; /* Enter XIP Mode Immediately */ + uint32_t bauddiv : 4; /* Master Mode Baud Rate Divisor */ + uint32_t : 8; /* *UNDEFINED* */ + const uint32_t idle : 1; /* Serial interface and QSPI pipeline is IDLE */ +}; + +/* The typedef declaration for register ALT_QSPI_CFG. */ +typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */ +#define ALT_QSPI_CFG_OFST 0x0 + +/* + * Register : Device Read Instruction Register - devrd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [7:0] | RW | 0x3 | Read Opcode in non-XIP mode + * [9:8] | RW | 0x0 | Instruction Transfer Width + * [11:10] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | Address Transfer Width + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [17:16] | RW | 0x0 | Data Transfer Width + * [19:18] | ??? | 0x0 | *UNDEFINED* + * [20] | RW | 0x0 | Mode Bit Enable + * [23:21] | ??? | 0x0 | *UNDEFINED* + * [28:24] | RW | 0x0 | Dummy Read Clock Cycles + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Read Opcode in non-XIP mode - rdopcode + * + * Read Opcode to use when not in XIP mode + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_QSPI_DEVRD_RDOPCODE_E_RD | 0x3 | Read Opcode in Non-XIP mode + * ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD | 0xb | Fast Read in Non-XIP mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE + * + * Read Opcode in Non-XIP mode + */ +#define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE + * + * Fast Read in Non-XIP mode + */ +#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_MSB 7 +/* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */ +#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */ +#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3 +/* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */ +#define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Instruction Transfer Width - instwidth + * + * Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions + * sent to SPI flash device (not just read instructions). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0 | Instruction transferred on DQ0. Supported by all + * : | | SPI flash devices. + * ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL | 0x1 | Instruction transferred on DQ0 and DQ1. + * : | | Supported by all SPI flash devices that support + * : | | the Dual SP (DIO-SPI) Protocol. + * ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD | 0x2 | Instruction transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by all SPI flash devices that + * : | | support the Quad SP (QIO-SPI) Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0. Supported by all SPI flash devices. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that + * support the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash + * devices that support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9 +/* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300 +/* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff +/* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : Address Transfer Width - addrwidth + * + * Sets read address transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0 | Read address transferred on DQ0. Supported by + * : | | all SPI flash devices + * ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by some SPI flash devices that + * : | | support the Extended SPI Protocol and by all SPI + * : | | flash devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices + * that support the Extended SPI Protocol and by all SPI flash devices that support + * the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13 +/* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000 +/* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff +/* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Data Transfer Width - datawidth + * + * Sets read data transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0 | Read data transferred on DQ0. Supported by all + * : | | SPI flash devices + * ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported + * : | | by some SPI flash devices that support the + * : | | Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that + * support the Extended SPI Protocol and by all SPI flash devices that support the + * Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17 +/* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Mode Bit Enable - enmodebits + * + * If this bit is set, the mode bits as defined in the Mode Bit Configuration + * register are sent following the address bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------- + * ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER | 0x0 | No Order + * ALT_QSPI_DEVRD_ENMODBITS_E_ORDER | 0x1 | Mode Bits follow address bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS + * + * No Order + */ +#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS + * + * Mode Bits follow address bytes + */ +#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_MSB 20 +/* The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1 +/* The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value. */ +#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000 +/* The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value. */ +#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff +/* The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register. */ +#define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Dummy Read Clock Cycles - dummyrdclks + * + * Number of dummy clock cycles required by device for read instruction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28 +/* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000 +/* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff +/* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24) +/* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVRD. + */ +struct ALT_QSPI_DEVRD_s +{ + uint32_t rdopcode : 8; /* Read Opcode in non-XIP mode */ + uint32_t instwidth : 2; /* Instruction Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t addrwidth : 2; /* Address Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t datawidth : 2; /* Data Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t enmodebits : 1; /* Mode Bit Enable */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t dummyrdclks : 5; /* Dummy Read Clock Cycles */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVRD. */ +typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */ +#define ALT_QSPI_DEVRD_OFST 0x4 + +/* + * Register : Device Write Instruction Register - devwr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [7:0] | RW | 0x2 | Write Opcode + * [11:8] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | Address Transfer Width + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [17:16] | RW | 0x0 | Data Transfer Width + * [23:18] | ??? | 0x0 | *UNDEFINED* + * [28:24] | RW | 0x0 | Dummy Write Clock Cycles + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write Opcode - wropcode + * + * Write Opcode + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_MSB 7 +/* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */ +#define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */ +#define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2 +/* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */ +#define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Address Transfer Width - addrwidth + * + * Sets write address transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0 | Write address transferred on DQ0. Supported by + * : | | all SPI flash devices + * ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by some SPI flash devices that + * : | | support the Extended SPI Protocol and by all SPI + * : | | flash devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Write address transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices + * that support the Extended SPI Protocol and by all SPI flash devices that support + * the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13 +/* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000 +/* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff +/* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Data Transfer Width - datawidth + * + * Sets write data transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0 | Write data transferred on DQ0. Supported by all + * : | | SPI flash devices + * ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported + * : | | by some SPI flash devices that support the + * : | | Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Write data transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that + * support the Extended SPI Protocol and by all SPI flash devices that support the + * Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17 +/* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Dummy Write Clock Cycles - dummywrclks + * + * Number of dummy clock cycles required by device for write instruction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28 +/* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000 +/* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff +/* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24) +/* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVWR. + */ +struct ALT_QSPI_DEVWR_s +{ + uint32_t wropcode : 8; /* Write Opcode */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t addrwidth : 2; /* Address Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t datawidth : 2; /* Data Transfer Width */ + uint32_t : 6; /* *UNDEFINED* */ + uint32_t dummywrclks : 5; /* Dummy Write Clock Cycles */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVWR. */ +typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */ +#define ALT_QSPI_DEVWR_OFST 0x8 + +/* + * Register : QSPI Device Delay Register - delay + * + * This register is used to introduce relative delays into the generation of the + * master output signals. All timings are defined in cycles of the qspi_clk. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------- + * [7:0] | RW | 0x0 | Clock Delay with qspi_n_ss_out + * [15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit + * [23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation + * [31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert + * + */ +/* + * Field : Clock Delay with qspi_n_ss_out - init + * + * Delay in master reference clocks between setting qspi_n_ss_out low and first bit + * transfer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_MSB 7 +/* The width in bits of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */ +#define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */ +#define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */ +#define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Clock Delay for Last Transaction Bit - after + * + * Delay in master reference clocks between last bit of current transaction and + * deasserting the device chip select (qspi_n_ss_out). By default, the chip select + * will be deasserted on the cycle following the completion of the current + * transaction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_MSB 15 +/* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */ +#define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */ +#define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff +/* The reset value of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */ +#define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Clock Delay for Chip Select Deactivation - btwn + * + * Delay in master reference clocks between one chip select being de-activated and + * the activation of another. This is used to ensure a quiet period between the + * selection of two different slaves and requires the transmit FIFO to be empty. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_MSB 23 +/* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */ +#define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */ +#define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff +/* The reset value of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */ +#define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000) + +/* + * Field : Clock Delay for Chip Select Deassert - nss + * + * Delay in master reference clocks for the length that the master mode chip select + * outputs are de-asserted between transactions. The minimum delay is always + * qspi_sck_out period to ensure the chip select is never re-asserted within an + * qspi_sck_out period. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_MSB 31 +/* The width in bits of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */ +#define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000 +/* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */ +#define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff +/* The reset value of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */ +#define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DELAY. + */ +struct ALT_QSPI_DELAY_s +{ + uint32_t init : 8; /* Clock Delay with qspi_n_ss_out */ + uint32_t after : 8; /* Clock Delay for Last Transaction Bit */ + uint32_t btwn : 8; /* Clock Delay for Chip Select Deactivation */ + uint32_t nss : 8; /* Clock Delay for Chip Select Deassert */ +}; + +/* The typedef declaration for register ALT_QSPI_DELAY. */ +typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */ +#define ALT_QSPI_DELAY_OFST 0xc + +/* + * Register : Read Data Capture Register - rddatacap + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | RW | 0x1 | Bypass + * [4:1] | RW | 0x0 | Read Delay + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bypass - byp + * + * Controls bypass of the adapted loopback clock circuit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------ + * ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x0 | No Bypass + * ALT_QSPI_RDDATACAP_BYP_E_BYPASS | 0x1 | Bypass loopback clock circuit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP + * + * No Bypass + */ +#define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0 +/* + * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP + * + * Bypass loopback clock circuit + */ +#define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_MSB 0 +/* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_WIDTH 1 +/* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */ +#define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */ +#define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_RESET 0x1 +/* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */ +#define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */ +#define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Read Delay - delay + * + * Delay the read data capturing logic by the programmed number of qspi_clk cycles + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_MSB 4 +/* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4 +/* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */ +#define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e +/* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */ +#define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1 +/* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0 +/* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */ +#define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1) +/* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */ +#define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_RDDATACAP. + */ +struct ALT_QSPI_RDDATACAP_s +{ + uint32_t byp : 1; /* Bypass */ + uint32_t delay : 4; /* Read Delay */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_RDDATACAP. */ +typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */ +#define ALT_QSPI_RDDATACAP_OFST 0x10 + +/* + * Register : Device Size Register - devsz + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [3:0] | RW | 0x2 | Number of address Bytes + * [15:4] | RW | 0x100 | Number of Bytes per Device Page + * [20:16] | RW | 0x10 | Number of Bytes per Block + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Number of address Bytes - numaddrbytes + * + * Number of address bytes. A value of 0 indicates 1 byte. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3 +/* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2 +/* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Number of Bytes per Device Page - bytesperdevicepage + * + * Number of bytes per device page. This is required by the controller for + * performing FLASH writes up to and across page boundaries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15 +/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12 +/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0 +/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f +/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100 +/* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4) +/* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0) + +/* + * Field : Number of Bytes per Block - bytespersubsector + * + * Number of bytes per Block. This is required by the controller for performing the + * write protection logic. The number of bytes per block must be a power of 2 + * number. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20 +/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000 +/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff +/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10 +/* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16) +/* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVSZ. + */ +struct ALT_QSPI_DEVSZ_s +{ + uint32_t numaddrbytes : 4; /* Number of address Bytes */ + uint32_t bytesperdevicepage : 12; /* Number of Bytes per Device Page */ + uint32_t bytespersubsector : 5; /* Number of Bytes per Block */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVSZ. */ +typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */ +#define ALT_QSPI_DEVSZ_OFST 0x14 + +/* + * Register : SRAM Partition Register - srampart + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [6:0] | RW | 0x40 | Indirect Read Partition Size + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Indirect Read Partition Size - addr + * + * Defines the size of the indirect read partition in the SRAM, in units of SRAM + * locations. By default, half of the SRAM is reserved for indirect read operations + * and half for indirect write operations. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_MSB 6 +/* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_WIDTH 7 +/* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */ +#define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */ +#define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_RESET 0x40 +/* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */ +#define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_SRAMPART. + */ +struct ALT_QSPI_SRAMPART_s +{ + uint32_t addr : 7; /* Indirect Read Partition Size */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_SRAMPART. */ +typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */ +#define ALT_QSPI_SRAMPART_OFST 0x18 + +/* + * Register : Indirect AHB Address Trigger Register - indaddrtrig + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Trigger Address + * + */ +/* + * Field : Trigger Address - addr + * + * This is the base address that will be used by the AHB controller. When the + * incoming AHB read access address matches a range of addresses from this trigger + * address to the trigger address + 15, then the AHB request will be completed by + * fetching data from the Indirect Controllers SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDADDRTRIG. + */ +struct ALT_QSPI_INDADDRTRIG_s +{ + uint32_t addr : 32; /* Trigger Address */ +}; + +/* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */ +typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */ +#define ALT_QSPI_INDADDRTRIG_OFST 0x1c + +/* + * Register : DMA Peripheral Register - dmaper + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [3:0] | RW | 0x0 | Number of Single Bytes + * [7:4] | ??? | 0x0 | *UNDEFINED* + * [11:8] | RW | 0x0 | Number of Burst Bytes + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Number of Single Bytes - numsglreqbytes + * + * Number of bytes in a single type request on the DMA peripheral request. A + * programmed value of 0 represents a single byte. This should be setup before + * starting the indirect read or write operation. The actual number of bytes used + * is 2**(value in this register) which will simplify implementation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3 +/* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Number of Burst Bytes - numburstreqbytes + * + * Number of bytes in a burst type request on the DMA peripheral request. A + * programmed value of 0 represents a single byte. This should be setup before + * starting the indirect read or write operation. The actual number of bytes used + * is 2**(value in this register) which will simplify implementation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11 +/* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00 +/* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff +/* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8) +/* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DMAPER. + */ +struct ALT_QSPI_DMAPER_s +{ + uint32_t numsglreqbytes : 4; /* Number of Single Bytes */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t numburstreqbytes : 4; /* Number of Burst Bytes */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DMAPER. */ +typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */ +#define ALT_QSPI_DMAPER_OFST 0x20 + +/* + * Register : Remap Address Register - remapaddr + * + * This register is used to remap an incoming AHB address to a different address + * used by the FLASH device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | RW | 0x0 | Remap Address Offset + * + */ +/* + * Field : Remap Address Offset - value + * + * This offset is added to the incoming AHB address to determine the address used + * by the FLASH device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */ +#define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */ +#define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */ +#define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_REMAPADDR. + */ +struct ALT_QSPI_REMAPADDR_s +{ + uint32_t value : 32; /* Remap Address Offset */ +}; + +/* The typedef declaration for register ALT_QSPI_REMAPADDR. */ +typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */ +#define ALT_QSPI_REMAPADDR_OFST 0x24 + +/* + * Register : Mode Bit Register - modebit + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Mode + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mode - mode + * + * These are the 8 mode bits that are sent to the device following the address + * bytes if mode bit transmission has been enabled. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_MSB 7 +/* The width in bits of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_WIDTH 8 +/* The mask used to set the ALT_QSPI_MODBIT_MOD register field value. */ +#define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_MODBIT_MOD register field value. */ +#define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_RESET 0x0 +/* Extracts the ALT_QSPI_MODBIT_MOD field value from a register. */ +#define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_MODBIT_MOD register field value suitable for setting the register. */ +#define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_MODBIT. + */ +struct ALT_QSPI_MODBIT_s +{ + uint32_t mode : 8; /* Mode */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_MODBIT. */ +typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_MODBIT register from the beginning of the component. */ +#define ALT_QSPI_MODBIT_OFST 0x28 + +/* + * Register : SRAM Fill Register - sramfill + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------------------------- + * [15:0] | R | 0x0 | SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS + * [31:16] | R | 0x0 | SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS + * + */ +/* + * Field : SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS - indrdpart + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15 +/* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16 +/* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000 +/* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0 +/* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS - indwrpart + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31 +/* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16 +/* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff +/* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0 +/* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_SRAMFILL. + */ +struct ALT_QSPI_SRAMFILL_s +{ + const uint32_t indrdpart : 16; /* SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS */ + const uint32_t indwrpart : 16; /* SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS */ +}; + +/* The typedef declaration for register ALT_QSPI_SRAMFILL. */ +typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */ +#define ALT_QSPI_SRAMFILL_OFST 0x2c + +/* + * Register : TX Threshold Register - txthresh + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x1 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Defines the level at which the transmit FIFO not full interrupt is generated + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_MSB 3 +/* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4 +/* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1 +/* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */ +#define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_TXTHRESH. + */ +struct ALT_QSPI_TXTHRESH_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_TXTHRESH. */ +typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */ +#define ALT_QSPI_TXTHRESH_OFST 0x30 + +/* + * Register : RX Threshold Register - rxthresh + * + * Device Instruction Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x1 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Defines the level at which the receive FIFO not empty interrupt is generated + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_MSB 3 +/* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4 +/* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1 +/* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */ +#define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_RXTHRESH. + */ +struct ALT_QSPI_RXTHRESH_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_RXTHRESH. */ +typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */ +#define ALT_QSPI_RXTHRESH_OFST 0x34 + +/* + * Register : Interrupt Status Register - irqstat + * + * The status fields in this register are set when the described event occurs and + * the interrupt is enabled in the mask register. When any of these bit fields are + * set, the interrupt output is asserted high. The fields are each cleared by + * writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when + * legacy SPI mode is active. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Underflow Detected + * [2] | RW | 0x0 | Indirect Operation Complete + * [3] | RW | 0x0 | Indirect Read Reject + * [4] | RW | 0x0 | Protected Area Write Attempt + * [5] | RW | 0x0 | Illegal AHB Access Detected + * [6] | RW | 0x0 | Transfer Watermark Reached + * [7] | RW | 0x0 | Receive Overflow + * [8] | RW | 0x1 | Transmit FIFO Compared to Threshold + * [9] | RW | 0x0 | Transmit FIFO Full + * [10] | RW | 0x0 | Receive FIFO Compared to Threshold + * [11] | RW | 0x0 | Receive FIFO Full + * [12] | RW | 0x0 | Indirect Read Partition overflow + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Underflow Detected - underflowdet + * + * An underflow is detected when an attempt to transfer data is made when the + * transmit FIFO is empty. This may occur when the AHB write data is being supplied + * too slowly to keep up with the requested write operation. This bit is reset only + * by a system reset and cleared only when the register is read. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW | 0x1 | Underflow + * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0 | No Underflow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET + * + * Underflow + */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET + * + * No Underflow + */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1 +/* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Operation Complete - indopdone + * + * Controller has completed last triggered indirect operation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP | 0x1 | Completed Indirect Operation + * ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0 | No Indirect Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE + * + * Completed Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE + * + * No Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Indirect Read Reject - indrdreject + * + * Indirect operation was requested but could not be accepted. Two indirect + * operations already in storage. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ | 0x1 | Indirect Operation Requested + * ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0 | No Indirect Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT + * + * Indirect Operation Requested + */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT + * + * No Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Protected Area Write Attempt - protwrattempt + * + * Write to protected area was attempted and rejected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------- + * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT | 0x1 | Write Attempt to protected area + * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT | 0x0 | No Write Attempt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT + * + * Write Attempt to protected area + */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT + * + * No Write Attempt + */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4 +/* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Illegal AHB Access Detected - illegalacc + * + * Illegal AHB access has been detected. AHB wrapping bursts and the use of + * SPLIT/RETRY accesses will cause this error interrupt to trigger. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB | 0x1 | Illegal AHB attempt + * ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0 | No Illegal AHB attempt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC + * + * Illegal AHB attempt + */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC + * + * No Illegal AHB attempt + */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5 +/* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transfer Watermark Reached - indxfrlvl + * + * Indirect Transfer Watermark Level Reached + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL | 0x1 | Water level reached + * ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0 | No water level reached + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL + * + * Water level reached + */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL + * + * No water level reached + */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Overflow - rxover + * + * This should only occur in Legacy SPI mode. Set if an attempt is made to push the + * RX FIFO when it is full. This bit is reset only by a system reset and cleared + * only when this register is read. If a new push to the RX FIFO occurs coincident + * with a register read this flag will remain set. 0 : no overflow has been + * detected. 1 : an overflow has occurred. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER | 0x1 | Receive Overflow + * ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0 | No Receive Overflow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER + * + * Receive Overflow + */ +#define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER + * + * No Receive Overflow + */ +#define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_MSB 7 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */ +#define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */ +#define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit FIFO Compared to Threshold - txthreshcmp + * + * Indicates the number of entries in the transmit FIFO with respect to the + * threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0 | FIFO has > TXTHRESH entries + * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1 | FIFO has <= TXTHRESH entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP + * + * FIFO has > TXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP + * + * FIFO has <= TXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8 +/* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1 +/* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Transmit FIFO Full - txfull + * + * Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy + * mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0 | Transmit FIFO Not Full + * ALT_QSPI_IRQSTAT_TXFULL_E_FULL | 0x1 | Transmit FIFO Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL + * + * Transmit FIFO Not Full + */ +#define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL + * + * Transmit FIFO Full + */ +#define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_MSB 9 +/* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive FIFO Compared to Threshold - rxthreshcmp + * + * Indicates the number of entries in the receive FIFO with respect to the + * threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0 | FIFO has <= RXTHRESH entries + * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1 | FIFO has > RXTHRESH entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP + * + * FIFO has <= RXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP + * + * FIFO has > RXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Receive FIFO Full - rxfull + * + * Indicates that the receive FIFO is full or not. Only relevant in SPI legacy + * mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------- + * ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0 | Receive FIFO Not Full + * ALT_QSPI_IRQSTAT_RXFULL_E_FULL | 0x1 | Receive FIFO Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL + * + * Receive FIFO Not Full + */ +#define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL + * + * Receive FIFO Full + */ +#define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_MSB 11 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Indirect Read Partition overflow - indsramfull + * + * Indirect Read Partition of SRAM is full and unable to immediately complete + * indirect operation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------- + * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL | 0x1 | SRAM is full + * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0 | SRAM is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL + * + * SRAM is full + */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL + * + * SRAM is not full + */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff +/* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_IRQSTAT. + */ +struct ALT_QSPI_IRQSTAT_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t underflowdet : 1; /* Underflow Detected */ + uint32_t indopdone : 1; /* Indirect Operation Complete */ + uint32_t indrdreject : 1; /* Indirect Read Reject */ + uint32_t protwrattempt : 1; /* Protected Area Write Attempt */ + uint32_t illegalacc : 1; /* Illegal AHB Access Detected */ + uint32_t indxfrlvl : 1; /* Transfer Watermark Reached */ + uint32_t rxover : 1; /* Receive Overflow */ + uint32_t txthreshcmp : 1; /* Transmit FIFO Compared to Threshold */ + uint32_t txfull : 1; /* Transmit FIFO Full */ + uint32_t rxthreshcmp : 1; /* Receive FIFO Compared to Threshold */ + uint32_t rxfull : 1; /* Receive FIFO Full */ + uint32_t indsramfull : 1; /* Indirect Read Partition overflow */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_IRQSTAT. */ +typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */ +#define ALT_QSPI_IRQSTAT_OFST 0x40 + +/* + * Register : Interrupt Mask - irqmask + * + * If disabled, the interrupt for the corresponding interrupt status register bit + * is disabled. If enabled, the interrupt for the corresponding interrupt status + * register bit is enabled. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Underflow Detected Mask + * [2] | RW | 0x0 | Mask + * [3] | RW | 0x0 | Indirect Read Reject Mask + * [4] | RW | 0x0 | Protected Area Write Attempt Mask + * [5] | RW | 0x0 | Illegal Access Detected Mask + * [6] | RW | 0x0 | Transfer Watermark Breach Mask + * [7] | RW | 0x0 | Receive Overflow Mask + * [8] | RW | 0x0 | Transmit FIFO Threshold Compare Mask + * [9] | RW | 0x0 | Transmit FIFO Full Mask + * [10] | RW | 0x0 | Receive FIFO Threshold Compare Mask + * [11] | RW | 0x0 | Receive FIFO full Mask + * [12] | RW | 0x0 | Indirect Read Partition overflow mask + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Underflow Detected Mask - underflowdet + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1 +/* The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Mask - indopdone + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDOPDONE_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDOPDONE_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2 +/* The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Indirect Read Reject Mask - indrdreject + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDRDREJECT_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3 +/* The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Protected Area Write Attempt Mask - protwrattempt + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4 +/* The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Illegal Access Detected Mask - illegalacc + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_ILLEGALACC_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5 +/* The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transfer Watermark Breach Mask - indxfrlvl + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDXFRLVL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6 +/* The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Overflow Mask - rxover + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXOVER_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXOVER_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_MSB 7 +/* The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value. */ +#define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value. */ +#define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register. */ +#define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit FIFO Threshold Compare Mask - txthreshcmp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8 +/* The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Transmit FIFO Full Mask - txfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_TXFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_TXFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_MSB 9 +/* The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value. */ +#define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value. */ +#define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive FIFO Threshold Compare Mask - rxthreshcmp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10 +/* The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Receive FIFO full Mask - rxfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_MSB 11 +/* The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value. */ +#define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value. */ +#define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Indirect Read Partition overflow mask - indsramfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDSRAMFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12 +/* The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff +/* The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_IRQMSK. + */ +struct ALT_QSPI_IRQMSK_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t underflowdet : 1; /* Underflow Detected Mask */ + uint32_t indopdone : 1; /* Mask */ + uint32_t indrdreject : 1; /* Indirect Read Reject Mask */ + uint32_t protwrattempt : 1; /* Protected Area Write Attempt Mask */ + uint32_t illegalacc : 1; /* Illegal Access Detected Mask */ + uint32_t indxfrlvl : 1; /* Transfer Watermark Breach Mask */ + uint32_t rxover : 1; /* Receive Overflow Mask */ + uint32_t txthreshcmp : 1; /* Transmit FIFO Threshold Compare Mask */ + uint32_t txfull : 1; /* Transmit FIFO Full Mask */ + uint32_t rxthreshcmp : 1; /* Receive FIFO Threshold Compare Mask */ + uint32_t rxfull : 1; /* Receive FIFO full Mask */ + uint32_t indsramfull : 1; /* Indirect Read Partition overflow mask */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_IRQMSK. */ +typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component. */ +#define ALT_QSPI_IRQMSK_OFST 0x44 + +/* + * Register : Lower Write Protection Register - lowwrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | RW | 0x0 | Block Number + * + */ +/* + * Field : Block Number - subsector + * + * The block number that defines the lower block in the range of blocks that is to + * be locked from writing. The definition of a block in terms of number of bytes is + * programmable via the Device Size Configuration register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31 +/* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32 +/* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0 +/* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_LOWWRPROT. + */ +struct ALT_QSPI_LOWWRPROT_s +{ + uint32_t subsector : 32; /* Block Number */ +}; + +/* The typedef declaration for register ALT_QSPI_LOWWRPROT. */ +typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */ +#define ALT_QSPI_LOWWRPROT_OFST 0x50 + +/* + * Register : Upper Write Protection Register - uppwrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | RW | 0x0 | Block Number + * + */ +/* + * Field : Block Number - subsector + * + * The block number that defines the upper block in the range of blocks that is to + * be locked from writing. The definition of a block in terms of number of bytes is + * programmable via the Device Size Configuration register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31 +/* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32 +/* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0 +/* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_UPPWRPROT. + */ +struct ALT_QSPI_UPPWRPROT_s +{ + uint32_t subsector : 32; /* Block Number */ +}; + +/* The typedef declaration for register ALT_QSPI_UPPWRPROT. */ +typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */ +#define ALT_QSPI_UPPWRPROT_OFST 0x54 + +/* + * Register : Write Protection Register - wrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | RW | 0x0 | Write Protection Inversion Bit + * [1] | RW | 0x0 | Write Protection Enable Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write Protection Inversion Bit - inv + * + * When enabled, the protection region defined in the lower and upper write + * protection registers is inverted meaning it is the region that the system is + * permitted to write to. When disabled, the protection region defined in the lower + * and upper write protection registers is the region that the system is not + * permitted to write to. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------- + * ALT_QSPI_WRPROT_INV_E_EN | 0x1 | Write Region allowed + * ALT_QSPI_WRPROT_INV_E_DIS | 0x0 | Write Region not allowed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_WRPROT_INV + * + * Write Region allowed + */ +#define ALT_QSPI_WRPROT_INV_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_WRPROT_INV + * + * Write Region not allowed + */ +#define ALT_QSPI_WRPROT_INV_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_MSB 0 +/* The width in bits of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_WIDTH 1 +/* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */ +#define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */ +#define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_RESET 0x0 +/* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */ +#define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */ +#define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Write Protection Enable Bit - en + * + * When enabled, any AHB write access with an address within the protection region + * defined in the lower and upper write protection registers is rejected. An AHB + * error response is generated and an interrupt source triggered. When disabled, + * the protection region is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:--------------------------- + * ALT_QSPI_WRPROT_EN_E_EN | 0x1 | AHB Write Access rejected + * ALT_QSPI_WRPROT_EN_E_DIS | 0x0 | Protection Region Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_WRPROT_EN + * + * AHB Write Access rejected + */ +#define ALT_QSPI_WRPROT_EN_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_WRPROT_EN + * + * Protection Region Disabled + */ +#define ALT_QSPI_WRPROT_EN_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_MSB 1 +/* The width in bits of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_WIDTH 1 +/* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */ +#define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */ +#define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_RESET 0x0 +/* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */ +#define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */ +#define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_WRPROT. + */ +struct ALT_QSPI_WRPROT_s +{ + uint32_t inv : 1; /* Write Protection Inversion Bit */ + uint32_t en : 1; /* Write Protection Enable Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_WRPROT. */ +typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */ +#define ALT_QSPI_WRPROT_OFST 0x58 + +/* + * Register : Indirect Read Transfer Register - indrd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------------- + * [0] | RW | 0x0 | Start Indirect Read + * [1] | RW | 0x0 | Cancel Indirect Read + * [2] | R | Unknown | Indirect Read Status + * [3] | RW | Unknown | SRAM Full + * [4] | R | Unknown | Queued Indirect Read Operations + * [5] | RW | Unknown | Indirect Completion Status + * [7:6] | R | Unknown | Completed Indirect Operations + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Indirect Read - start + * + * When this bit is enabled, it will trigger an indirect read operation. The + * assumption is that the indirect start address and the indirect number of bytes + * register is setup before triggering the indirect read operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------- + * ALT_QSPI_INDRD_START_E_END | 0x1 | Trigger Indirect Read + * ALT_QSPI_INDRD_START_E_DISD | 0x0 | No Indirect Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_START + * + * Trigger Indirect Read + */ +#define ALT_QSPI_INDRD_START_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_START + * + * No Indirect Read + */ +#define ALT_QSPI_INDRD_START_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_MSB 0 +/* The width in bits of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_START register field value. */ +#define ALT_QSPI_INDRD_START_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_INDRD_START register field value. */ +#define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_START field value from a register. */ +#define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Cancel Indirect Read - cancel + * + * This bit will cancel all ongoing indirect read operations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_QSPI_INDRD_CANCEL_E_CANCEL | 0x1 | Cancel Indirect Read + * ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0 | Do Not Cancel Indirect Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_CANCEL + * + * Cancel Indirect Read + */ +#define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_CANCEL + * + * Do Not Cancel Indirect Read + */ +#define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_MSB 1 +/* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */ +#define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */ +#define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */ +#define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Read Status - rd_status + * + * Indirect read operation in progress (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------ + * ALT_QSPI_INDRD_RD_STAT_E_RDOP | 0x1 | Read Operation in progress + * ALT_QSPI_INDRD_RD_STAT_E_NOACTION | 0x0 | No read operation in progress + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT + * + * Read Operation in progress + */ +#define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT + * + * No read operation in progress + */ +#define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_MSB 2 +/* The width in bits of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value. */ +#define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value. */ +#define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_INDRD_RD_STAT register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_RD_STAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register. */ +#define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SRAM Full - sram_full + * + * SRAM full and unable to immediately complete an indirect operation. Write a 1 to + * this field to clear it. ; indirect operation (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------- + * ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1 | Sram Full- Cant complete operation + * ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0 | SRram Not Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL + * + * Sram Full- Cant complete operation + */ +#define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL + * + * SRram Not Full + */ +#define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_MSB 3 +/* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */ +#define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */ +#define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */ +#define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Queued Indirect Read Operations - rd_queued + * + * Two indirect read operations have been queued + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1 | Queued Indirect Read + * ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION | 0x0 | No Queued Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED + * + * Queued Indirect Read + */ +#define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED + * + * No Queued Read + */ +#define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_MSB 4 +/* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */ +#define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */ +#define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */ +#define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Indirect Completion Status - ind_ops_done_status + * + * This field is set to 1 when an indirect operation has completed. Write a 1 to + * this field to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------- + * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP | 0x1 | Indirect Op Complete operation + * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION | 0x0 | Indirect Op Not Complete + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT + * + * Indirect Op Complete operation + */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT + * + * Indirect Op Not Complete + */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5 +/* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Completed Indirect Operations - num_ind_ops_done + * + * This field contains the number of indirect operations which have been completed. + * This is used in conjunction with the indirect completion status field (bit 5). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7 +/* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2 +/* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f +/* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRD. + */ +struct ALT_QSPI_INDRD_s +{ + uint32_t start : 1; /* Start Indirect Read */ + uint32_t cancel : 1; /* Cancel Indirect Read */ + const uint32_t rd_status : 1; /* Indirect Read Status */ + uint32_t sram_full : 1; /* SRAM Full */ + const uint32_t rd_queued : 1; /* Queued Indirect Read Operations */ + uint32_t ind_ops_done_status : 1; /* Indirect Completion Status */ + const uint32_t num_ind_ops_done : 2; /* Completed Indirect Operations */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRD. */ +typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */ +#define ALT_QSPI_INDRD_OFST 0x60 + +/* + * Register : Indirect Read Transfer Watermark Register - indrdwater + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Watermark Value + * + */ +/* + * Field : Watermark Value - level + * + * This represents the minimum fill level of the SRAM before a DMA peripheral + * access is permitted. When the SRAM fill level passes the watermark, an interrupt + * is also generated. This field can be disabled by writing a value of all zeroes. + * The units of this register are BYTES + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */ +#define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */ +#define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */ +#define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDWATER. + */ +struct ALT_QSPI_INDRDWATER_s +{ + uint32_t level : 32; /* Watermark Value */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDWATER. */ +typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */ +#define ALT_QSPI_INDRDWATER_OFST 0x64 + +/* + * Register : Indirect Read Transfer Start Address Register - indrdstaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [31:0] | RW | 0x0 | Start Address of Indirect Access + * + */ +/* + * Field : Start Address of Indirect Access - addr + * + * This is the start address from which the indirect access will commence its READ + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDSTADDR. + */ +struct ALT_QSPI_INDRDSTADDR_s +{ + uint32_t addr : 32; /* Start Address of Indirect Access */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */ +typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */ +#define ALT_QSPI_INDRDSTADDR_OFST 0x68 + +/* + * Register : Indirect Read Transfer Number Bytes Register - indrdcnt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | RW | 0x0 | Indirect Count + * + */ +/* + * Field : Indirect Count - value + * + * This is the number of bytes that the indirect access will consume. This can be + * bigger than the configured size of SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */ +#define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */ +#define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */ +#define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDCNT. + */ +struct ALT_QSPI_INDRDCNT_s +{ + uint32_t value : 32; /* Indirect Count */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDCNT. */ +typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */ +#define ALT_QSPI_INDRDCNT_OFST 0x6c + +/* + * Register : Indirect Write Transfer Register - indwr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------------- + * [0] | RW | 0x0 | Start Indirect Write + * [1] | RW | 0x0 | Cancel Indirect Write + * [2] | R | Unknown | Indirect Write Status + * [3] | R | 0x0 | Reserved + * [4] | R | Unknown | Queued Indirect Write Operations + * [5] | RW | Unknown | Indirect Completion Status + * [7:6] | R | Unknown | Completed Indirect Operations + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Indirect Write - start + * + * Writing a 1 to this bit will trigger an indirect write operation. The assumption + * is that the indirect start address and the indirect number of bytes register is + * setup before triggering the indirect write operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------------- + * ALT_QSPI_INDWR_START_E_END | 0x1 | Trigger indirect write operation + * ALT_QSPI_INDWR_START_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_START + * + * Trigger indirect write operation + */ +#define ALT_QSPI_INDWR_START_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_START + * + * No Action + */ +#define ALT_QSPI_INDWR_START_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_MSB 0 +/* The width in bits of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_START register field value. */ +#define ALT_QSPI_INDWR_START_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_INDWR_START register field value. */ +#define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_START field value from a register. */ +#define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Cancel Indirect Write - cancel + * + * Writing a 1 to this bit will cancel all ongoing indirect write operations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1 | Cancel Indirect write operation + * ALT_QSPI_INDWR_CANCEL_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_CANCEL + * + * Cancel Indirect write operation + */ +#define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_CANCEL + * + * No Action + */ +#define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_MSB 1 +/* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */ +#define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */ +#define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */ +#define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Write Status - rdstat + * + * Indirect write operation in progress (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------- + * ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1 | Indirect write operation + * ALT_QSPI_INDWR_RDSTAT_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT + * + * Indirect write operation + */ +#define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT + * + * No Action + */ +#define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_MSB 2 +/* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */ +#define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */ +#define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_INDWR_RDSTAT register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_RDSTAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */ +#define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Reserved - sramfull + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_MSB 3 +/* The width in bits of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_SRAMFULL register field value. */ +#define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_INDWR_SRAMFULL register field value. */ +#define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_SRAMFULL field value from a register. */ +#define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_INDWR_SRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Queued Indirect Write Operations - rdqueued + * + * Two indirect write operations have been queued + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_INDWR_RDQUEUED_E_INDWROP | 0x1 | Two Indirect write operation + * ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED + * + * Two Indirect write operation + */ +#define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED + * + * No Action + */ +#define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_MSB 4 +/* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */ +#define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */ +#define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */ +#define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Indirect Completion Status - inddone + * + * This field is set to 1 when an indirect operation has completed. Write a 1 to + * this field to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1 | Indirect operation completed + * ALT_QSPI_INDWR_INDDONE_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_INDDONE + * + * Indirect operation completed + */ +#define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_INDDONE + * + * No Action + */ +#define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_MSB 5 +/* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */ +#define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */ +#define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_INDWR_INDDONE register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_INDDONE_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */ +#define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Completed Indirect Operations - indcnt + * + * This field contains the count of indirect operations which have been completed. + * This is used in conjunction with the indirect completion status field (bit 5). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_MSB 7 +/* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_WIDTH 2 +/* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */ +#define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */ +#define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f +/* The reset value of the ALT_QSPI_INDWR_INDCNT register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_INDCNT_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */ +#define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWR. + */ +struct ALT_QSPI_INDWR_s +{ + uint32_t start : 1; /* Start Indirect Write */ + uint32_t cancel : 1; /* Cancel Indirect Write */ + const uint32_t rdstat : 1; /* Indirect Write Status */ + const uint32_t sramfull : 1; /* Reserved */ + const uint32_t rdqueued : 1; /* Queued Indirect Write Operations */ + uint32_t inddone : 1; /* Indirect Completion Status */ + const uint32_t indcnt : 2; /* Completed Indirect Operations */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWR. */ +typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */ +#define ALT_QSPI_INDWR_OFST 0x70 + +/* + * Register : Indirect Write Transfer Watermark Register - indwrwater + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------- + * [31:0] | RW | 0xffffffff | Watermark Value + * + */ +/* + * Field : Watermark Value - level + * + * This represents the maximum fill level of the SRAM before a DMA peripheral + * access is permitted. When the SRAM fill level falls below the watermark, an + * interrupt is also generated. This field can be disabled by writing a value of + * all ones. The units of this register are bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */ +#define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */ +#define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff +/* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */ +#define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRWATER. + */ +struct ALT_QSPI_INDWRWATER_s +{ + uint32_t level : 32; /* Watermark Value */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRWATER. */ +typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */ +#define ALT_QSPI_INDWRWATER_OFST 0x74 + +/* + * Register : Indirect Write Transfer Start Address Register - indwrstaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [31:0] | RW | 0x0 | Start of Indirect Access + * + */ +/* + * Field : Start of Indirect Access - addr + * + * This is the start address from which the indirect access will commence its write + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRSTADDR. + */ +struct ALT_QSPI_INDWRSTADDR_s +{ + uint32_t addr : 32; /* Start of Indirect Access */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */ +typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */ +#define ALT_QSPI_INDWRSTADDR_OFST 0x78 + +/* + * Register : Indirect Write Transfer Count Register - indwrcnt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [31:0] | RW | 0x0 | Indirect Number of Bytes + * + */ +/* + * Field : Indirect Number of Bytes - value + * + * This is the number of bytes that the indirect access will consume. This can be + * bigger than the configured size of SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */ +#define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */ +#define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */ +#define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRCNT. + */ +struct ALT_QSPI_INDWRCNT_s +{ + uint32_t value : 32; /* Indirect Number of Bytes */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRCNT. */ +typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */ +#define ALT_QSPI_INDWRCNT_OFST 0x7c + +/* + * Register : Flash Command Register - flashcmd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Execute Command + * [1] | R | 0x0 | Command Execution Status + * [6:2] | ??? | 0x0 | *UNDEFINED* + * [11:7] | RW | 0x0 | Number of Dummy Bytes + * [14:12] | RW | 0x0 | Number of Write Data Bytes + * [15] | RW | 0x0 | Write Data Enable + * [17:16] | RW | 0x0 | Number of Address Bytes + * [18] | RW | 0x0 | Mode Bit Enable + * [19] | RW | 0x0 | Command Address Enable + * [22:20] | RW | 0x0 | Number of Read Data Bytes + * [23] | RW | 0x0 | Read Data Enable + * [31:24] | RW | 0x0 | Command Opcode + * + */ +/* + * Field : Execute Command - execcmd + * + * Execute the command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE | 0x1 | Execute Command + * ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD + * + * Execute Command + */ +#define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0 +/* The width in bits of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_EXECCMD field value from a register. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_FLSHCMD_EXECCMD register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Command Execution Status - cmdexecstat + * + * Command execution in progress. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------- + * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1 | Command Execution Status + * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT + * + * Command Execution Status + */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1 +/* The width in bits of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_CMDEXECSTAT field value from a register. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Number of Dummy Bytes - numdummybytes + * + * Set to the number of dummy bytes required This should be setup before triggering + * the command via the execute field of this register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f +/* The reset value of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7) +/* Produces a ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80) + +/* + * Field : Number of Write Data Bytes - numwrdatabytes + * + * Up to 8 Data bytes may be written using this command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0 | Write 1 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1 | Write 2 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2 | Write 3 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3 | Write 4 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4 | Write 5 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5 | Write 6 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6 | Write 7 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7 | Write 8 Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 1 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 2 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 3 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 4 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 5 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 6 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 7 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 8 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMWRDATABYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12) +/* Produces a ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000) + +/* + * Field : Write Data Enable - enwrdata + * + * Set to 1 if the command specified in the command opcode field requires write + * data bytes to be sent to the device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------- + * ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES | 0x1 | Command requires write data bytes + * ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA + * + * Command requires write data bytes + */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff +/* The reset value of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENWRDATA field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_QSPI_FLSHCMD_ENWRDATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Number of Address Bytes - numaddrbytes + * + * Set to the number of address bytes required (the address itself is programmed in + * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the + * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address + * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------- + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0 | Write 1 Address Byte + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1 | Write 2 Address Bytes + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2 | Write 3 Address Bytes + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3 | Write 4 Address Bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 1 Address Byte + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 2 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 3 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 4 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMADDRBYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Mode Bit Enable - enmodebit + * + * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration + * register are sent following the address bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------- + * ALT_QSPI_FLSHCMD_ENMODBIT_E_END | 0x1 | Mode Bit follows address bytes + * ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT + * + * Mode Bit follows address bytes + */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENMODBIT field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_QSPI_FLSHCMD_ENMODBIT register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Command Address Enable - encmdaddr + * + * If enabled, the command specified in bits 31:24 requires an address. This should + * be setup before triggering the command via writing a 1 to the execute field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:--------------------------------------- + * ALT_QSPI_FLSHCMD_ENCMDADDR_E_END | 0x1 | Command in bits 31:24 requires address + * ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR + * + * Command in bits 31:24 requires address + */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENCMDADDR field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_QSPI_FLSHCMD_ENCMDADDR register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Number of Read Data Bytes - numrddatabytes + * + * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for + * 8 bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0 | Read 1 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1 | Read 2 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2 | Read 3 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3 | Read 4 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4 | Read 5 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5 | Read 6 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6 | Read 7 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7 | Read 8 Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 1 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 2 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 3 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 4 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 5 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 6 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 7 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 8 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMRDDATABYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20) +/* Produces a ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000) + +/* + * Field : Read Data Enable - enrddata + * + * If enabled, the command specified in the command opcode field (bits 31:24) + * requires read data bytes to be received from the device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------- + * ALT_QSPI_FLSHCMD_ENRDDATA_E_EN | 0x1 | Command Requires read data + * ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA + * + * Command Requires read data + */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENRDDATA field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_QSPI_FLSHCMD_ENRDDATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Command Opcode - cmdopcode + * + * The command opcode field should be setup before triggering the command. For + * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of + * this register launches the command. NOTE : Using this approach to issue commands + * to the device will make use of the instruction type of the device instruction + * configuration register. If this field is set to 2'b00, then the command opcode, + * command address, command dummy bytes and command data will all be transferred in + * a serial fashion. If this field is set to 2'b01, then the command opcode, + * command address, command dummy bytes and command data will all be transferred in + * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command + * opcode, command address, command dummy bytes and command data will all be + * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff +/* The reset value of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_CMDOPCODE field value from a register. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_QSPI_FLSHCMD_CMDOPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMD. + */ +struct ALT_QSPI_FLSHCMD_s +{ + uint32_t execcmd : 1; /* Execute Command */ + const uint32_t cmdexecstat : 1; /* Command Execution Status */ + uint32_t : 5; /* *UNDEFINED* */ + uint32_t numdummybytes : 5; /* Number of Dummy Bytes */ + uint32_t numwrdatabytes : 3; /* Number of Write Data Bytes */ + uint32_t enwrdata : 1; /* Write Data Enable */ + uint32_t numaddrbytes : 2; /* Number of Address Bytes */ + uint32_t enmodebit : 1; /* Mode Bit Enable */ + uint32_t encmdaddr : 1; /* Command Address Enable */ + uint32_t numrddatabytes : 3; /* Number of Read Data Bytes */ + uint32_t enrddata : 1; /* Read Data Enable */ + uint32_t cmdopcode : 8; /* Command Opcode */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMD. */ +typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMD register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMD_OFST 0x90 + +/* + * Register : Flash Command Address Registers - flashcmdaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Command Address + * + */ +/* + * Field : Command Address - addr + * + * This should be setup before triggering the command with execute field (bit 0) of + * the Flash Command Control register. It is the address used by the command + * specified in the opcode field (bits 31:24) of the Flash Command Control + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDADDR_ADDR field value from a register. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDADDR. + */ +struct ALT_QSPI_FLSHCMDADDR_s +{ + uint32_t addr : 32; /* Command Address */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDADDR. */ +typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDADDR register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDADDR_OFST 0x94 + +/* + * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [31:0] | RW | 0x0 | Command Read Data (Lower byte) + * + */ +/* + * Field : Command Read Data (Lower byte) - data + * + * This is the data that is returned by the flash device for any status or + * configuration read operation carried out by triggering the event in the control + * register. The register will be valid when the polling bit in the control + * register is low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDRDDATALO_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDRDDATALO_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDRDDATALO. + */ +struct ALT_QSPI_FLSHCMDRDDATALO_s +{ + uint32_t data : 32; /* Command Read Data (Lower byte) */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATALO. */ +typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDRDDATALO register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0 + +/* + * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup + * + * Device Instruction Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [31:0] | RW | 0x0 | Command Read Data (Upper byte) + * + */ +/* + * Field : Command Read Data (Upper byte) - data + * + * This is the data that is returned by the FLASH device for any status or + * configuration read operation carried out by triggering the event in the control + * register. The register will be valid when the polling bit in the control + * register is low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDRDDATAUP_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDRDDATAUP. + */ +struct ALT_QSPI_FLSHCMDRDDATAUP_s +{ + uint32_t data : 32; /* Command Read Data (Upper byte) */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATAUP. */ +typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDRDDATAUP register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4 + +/* + * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | Command Write Data Lower Byte + * + */ +/* + * Field : Command Write Data Lower Byte - data + * + * This is the command write data lower byte. This should be setup before + * triggering the command with execute field (bit 0) of the Flash Command Control + * register. It is the data that is to be written to the flash for any status or + * configuration write operation carried out by triggering the event in the Flash + * Command Control register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDWRDATALO_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDWRDATALO_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDWRDATALO. + */ +struct ALT_QSPI_FLSHCMDWRDATALO_s +{ + uint32_t data : 32; /* Command Write Data Lower Byte */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATALO. */ +typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDWRDATALO register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8 + +/* + * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | ALT_QSPI_FLSHCMDWRDATAUP_DATA + * + */ +/* + * Field : data + * + * This is the command write data upper byte. This should be setup before + * triggering the command with execute field (bit 0) of the Flash Command Control + * register. It is the data that is to be written to the flash for any status or + * configuration write operation carried out by triggering the event in the Flash + * Command Control register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDWRDATAUP_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDWRDATAUP. + */ +struct ALT_QSPI_FLSHCMDWRDATAUP_s +{ + uint32_t data : 32; /* ALT_QSPI_FLSHCMDWRDATAUP_DATA */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATAUP. */ +typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDWRDATAUP register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac + +/* + * Register : Module ID Register - moduleid + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------- + * [24:0] | R | 0x1001 | Module ID number + * [31:25] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Module ID number - value + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_MSB 24 +/* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_WIDTH 25 +/* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */ +#define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff +/* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */ +#define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000 +/* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_RESET 0x1001 +/* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */ +#define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0) +/* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_MODULEID. + */ +struct ALT_QSPI_MODULEID_s +{ + const uint32_t value : 25; /* Module ID number */ + uint32_t : 7; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_MODULEID. */ +typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */ +#define ALT_QSPI_MODULEID_OFST 0xfc + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_QSPI. + */ +struct ALT_QSPI_s +{ + volatile ALT_QSPI_CFG_t cfg; /* ALT_QSPI_CFG */ + volatile ALT_QSPI_DEVRD_t devrd; /* ALT_QSPI_DEVRD */ + volatile ALT_QSPI_DEVWR_t devwr; /* ALT_QSPI_DEVWR */ + volatile ALT_QSPI_DELAY_t delay; /* ALT_QSPI_DELAY */ + volatile ALT_QSPI_RDDATACAP_t rddatacap; /* ALT_QSPI_RDDATACAP */ + volatile ALT_QSPI_DEVSZ_t devsz; /* ALT_QSPI_DEVSZ */ + volatile ALT_QSPI_SRAMPART_t srampart; /* ALT_QSPI_SRAMPART */ + volatile ALT_QSPI_INDADDRTRIG_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ + volatile ALT_QSPI_DMAPER_t dmaper; /* ALT_QSPI_DMAPER */ + volatile ALT_QSPI_REMAPADDR_t remapaddr; /* ALT_QSPI_REMAPADDR */ + volatile ALT_QSPI_MODBIT_t modebit; /* ALT_QSPI_MODBIT */ + volatile ALT_QSPI_SRAMFILL_t sramfill; /* ALT_QSPI_SRAMFILL */ + volatile ALT_QSPI_TXTHRESH_t txthresh; /* ALT_QSPI_TXTHRESH */ + volatile ALT_QSPI_RXTHRESH_t rxthresh; /* ALT_QSPI_RXTHRESH */ + volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_IRQSTAT_t irqstat; /* ALT_QSPI_IRQSTAT */ + volatile ALT_QSPI_IRQMSK_t irqmask; /* ALT_QSPI_IRQMSK */ + volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_LOWWRPROT_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ + volatile ALT_QSPI_UPPWRPROT_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ + volatile ALT_QSPI_WRPROT_t wrprot; /* ALT_QSPI_WRPROT */ + volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ + volatile ALT_QSPI_INDRD_t indrd; /* ALT_QSPI_INDRD */ + volatile ALT_QSPI_INDRDWATER_t indrdwater; /* ALT_QSPI_INDRDWATER */ + volatile ALT_QSPI_INDRDSTADDR_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ + volatile ALT_QSPI_INDRDCNT_t indrdcnt; /* ALT_QSPI_INDRDCNT */ + volatile ALT_QSPI_INDWR_t indwr; /* ALT_QSPI_INDWR */ + volatile ALT_QSPI_INDWRWATER_t indwrwater; /* ALT_QSPI_INDWRWATER */ + volatile ALT_QSPI_INDWRSTADDR_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ + volatile ALT_QSPI_INDWRCNT_t indwrcnt; /* ALT_QSPI_INDWRCNT */ + volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ + volatile ALT_QSPI_FLSHCMD_t flashcmd; /* ALT_QSPI_FLSHCMD */ + volatile ALT_QSPI_FLSHCMDADDR_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ + volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ + volatile ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ + volatile ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ + volatile ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ + volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ + volatile ALT_QSPI_MODULEID_t moduleid; /* ALT_QSPI_MODULEID */ +}; + +/* The typedef declaration for register group ALT_QSPI. */ +typedef volatile struct ALT_QSPI_s ALT_QSPI_t; +/* The struct declaration for the raw register contents of register group ALT_QSPI. */ +struct ALT_QSPI_raw_s +{ + volatile uint32_t cfg; /* ALT_QSPI_CFG */ + volatile uint32_t devrd; /* ALT_QSPI_DEVRD */ + volatile uint32_t devwr; /* ALT_QSPI_DEVWR */ + volatile uint32_t delay; /* ALT_QSPI_DELAY */ + volatile uint32_t rddatacap; /* ALT_QSPI_RDDATACAP */ + volatile uint32_t devsz; /* ALT_QSPI_DEVSZ */ + volatile uint32_t srampart; /* ALT_QSPI_SRAMPART */ + volatile uint32_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ + volatile uint32_t dmaper; /* ALT_QSPI_DMAPER */ + volatile uint32_t remapaddr; /* ALT_QSPI_REMAPADDR */ + volatile uint32_t modebit; /* ALT_QSPI_MODBIT */ + volatile uint32_t sramfill; /* ALT_QSPI_SRAMFILL */ + volatile uint32_t txthresh; /* ALT_QSPI_TXTHRESH */ + volatile uint32_t rxthresh; /* ALT_QSPI_RXTHRESH */ + volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ + volatile uint32_t irqstat; /* ALT_QSPI_IRQSTAT */ + volatile uint32_t irqmask; /* ALT_QSPI_IRQMSK */ + volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ + volatile uint32_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ + volatile uint32_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ + volatile uint32_t wrprot; /* ALT_QSPI_WRPROT */ + volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ + volatile uint32_t indrd; /* ALT_QSPI_INDRD */ + volatile uint32_t indrdwater; /* ALT_QSPI_INDRDWATER */ + volatile uint32_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ + volatile uint32_t indrdcnt; /* ALT_QSPI_INDRDCNT */ + volatile uint32_t indwr; /* ALT_QSPI_INDWR */ + volatile uint32_t indwrwater; /* ALT_QSPI_INDWRWATER */ + volatile uint32_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ + volatile uint32_t indwrcnt; /* ALT_QSPI_INDWRCNT */ + volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ + volatile uint32_t flashcmd; /* ALT_QSPI_FLSHCMD */ + volatile uint32_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ + volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ + volatile uint32_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ + volatile uint32_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ + volatile uint32_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ + volatile uint32_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ + volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ + volatile uint32_t moduleid; /* ALT_QSPI_MODULEID */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_QSPI. */ +typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_QSPI_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspidata.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspidata.h new file mode 100644 index 0000000..19383ee --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspidata.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_QSPIDATA */ + +#ifndef __ALTERA_ALT_QSPIDATA_H__ +#define __ALTERA_ALT_QSPIDATA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : QSPI Flash Module Data (AHB Slave) - ALT_QSPIDATA + * QSPI Flash Module Data (AHB Slave) + * + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_QSPIDATA_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_16550_uart.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_16550_uart.c new file mode 100644 index 0000000..a5dfc5f --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_16550_uart.c @@ -0,0 +1,1179 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_16550_uart.h" +#include "alt_clock_manager.h" +#include "socal/alt_rstmgr.h" +#include "socal/alt_uart.h" +#include "socal/hps.h" +#include "socal/socal.h" + +///// + +#define ALT_16550_HANDLE_DATA_UART_ENABLED_MSK (1UL << 31) +#define ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(value) (value & 0xffff) + +#define ALT_ALTERA_16550_CPR_OFST (0xF4) +#define ALT_ALTERA_16550_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ALTERA_16550_CPR_OFST)) +#define ALT_ALTERA_16550_CPR_FIFO_MODE_GET(value) (((value) >> 16) & 0xff) +#define ALT_ALTERA_16550_CPR_AFCE_MODE_SET_MSK (1 << 4) + +///// + +// Remove these macros as part of case:123835. +#define ALT_UART_IER_DLH_VALUE_SET(value) ((value) & 0xff) +#define ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK + +///// + +// +// Helper function which resets the UART and if requested, initializes the UART +// to the default settings. Currently the default settings are: +// - 8 databits +// - no parity +// - 1 stopbit +// - 57600 baudrate +// The reset routines depends on the hardware implementation of the UART. +// + +// This helper is needed because the regular alt_read_word(src) essentially +// resolves to "*(volatile uint32_t *)src". As there is no assignment, this +// could potentially be optimized away. With the helper, the actual register +// read should occur and be returned (and subsequently discarded). +static inline uint32_t alt_read_word_helper(const void * addr) +{ + return alt_read_word(addr); +} + +// +// Helper function write the divisor in hardware. +// +static ALT_STATUS_CODE alt_16550_write_divisor_helper(ALT_16550_HANDLE_t * handle, + uint32_t divisor) +{ + // Validate the divisor parameter. + if (divisor > 0xffff) + { + // This should never happen as it is verified in divisor_set. + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set LCR::DLAB (Line Control Register :: Divisor Latch Access Bit) + alt_setbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_DLAB_SET_MSK); + + // Write DLL (Divisor Latch Low). + alt_write_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location), ALT_UART_RBR_THR_DLL_VALUE_SET(divisor)); + + // Write DLH (Divisor Latch High). + alt_write_word(ALT_UART_IER_DLH_ADDR(handle->location), ALT_UART_IER_DLH_VALUE_SET(divisor >> 8)); + + // Clear LCR::DLAB (Line Control Register :: Divisor Latch Access Bit) + alt_clrbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_DLAB_SET_MSK); + + break; + + default: + return ALT_E_ERROR; + } + + // Update the enabled state in the handle data. + if (divisor != 0) + { + handle->data |= ALT_16550_HANDLE_DATA_UART_ENABLED_MSK; + } + else + { + handle->data &= ~ALT_16550_HANDLE_DATA_UART_ENABLED_MSK; + } + + return ALT_E_SUCCESS; +} + +// +// Helper function to reset the UART. +// +static ALT_STATUS_CODE alt_16550_reset_helper(ALT_16550_HANDLE_t * handle, bool enable_init) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::UR (Shadow Reset Register :: UART Reset) + alt_write_word(ALT_UART_SRR_ADDR(handle->location), ALT_UART_SRR_UR_SET_MSK); + + // Read the MSR to work around case:119085. + alt_read_word_helper(ALT_UART_MSR_ADDR(handle->location)); + break; + + case ALT_16550_DEVICE_ALTERA_16550_UART: + alt_16550_write_divisor_helper(handle, 0); // Disable UART + alt_16550_int_disable_all(handle); // Disable interrupts + alt_16550_fifo_disable(handle); // Disable FIFOs + alt_write_word(ALT_UART_MCR_ADDR(handle->location), 0); // 0 -> MCR (AFCE, LP, OUT2, OUT1, RTS, DTR) + break; + + default: + return ALT_E_ERROR; + } + + // If we are initializing (as opposed to just uninitializing) + if (enable_init) + { + ALT_STATUS_CODE status; + + // Set bit IER::PTIME (Interrupt Enable Register :: Programmable THRE Mode Enable) + alt_setbits_word(ALT_UART_IER_DLH_ADDR(handle->location), ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK); + + // Set the line configuration to use 8-N-1. + status = alt_16550_line_config_set(handle, ALT_16550_DATABITS_8, + ALT_16550_PARITY_DISABLE, + ALT_16550_STOPBITS_1); + if (status != ALT_E_SUCCESS) + { + return status; + } + + uint32_t divisor = ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data); + if (divisor == 0) + { + // Set the default baudrate to 57600. + status = alt_16550_baudrate_set(handle, ALT_16550_BAUDRATE_57600); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_init(ALT_16550_DEVICE_t device, + void * location, + alt_freq_t clock_freq, + ALT_16550_HANDLE_t * handle) +{ + handle->device = device; + handle->data = 0; + handle->fcr = 0; + + switch (device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // The ALT_CLK_L4_SP is required for all SoCFPGA UARTs. Check that it's enabled. + if (alt_clk_is_enabled(ALT_CLK_L4_SP) != ALT_E_TRUE) + { + return ALT_E_BAD_CLK; + } + else + { + ALT_STATUS_CODE status; + status = alt_clk_freq_get(ALT_CLK_L4_SP, &handle->clock_freq); + if (status != ALT_E_SUCCESS) + { + return status; + } + + if (device == ALT_16550_DEVICE_SOCFPGA_UART0) + { + handle->location = ALT_UART0_ADDR; + + // Bring UART0 out of reset. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART0_SET_MSK); + } + else // device == ALT_16550_DEVICE_SOCFPGA_UART1 + { + handle->location = ALT_UART1_ADDR; + + // Bring UART1 out of reset. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART1_SET_MSK); + } + + // Verify the UCR (UART Component Version) + uint32_t ucr = alt_read_word(ALT_UART_UCV_ADDR(handle->location)); + if (ucr != ALT_UART_UCV_UART_COMPONENT_VER_RESET) + { + return ALT_E_ERROR; + } + } + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + handle->location = location; + handle->clock_freq = clock_freq; + break; + default: + return ALT_E_BAD_ARG; + } + + return alt_16550_reset_helper(handle, true); +} + +ALT_STATUS_CODE alt_16550_uninit(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART0_SET_MSK); + return ALT_E_SUCCESS; + case ALT_16550_DEVICE_SOCFPGA_UART1: + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART1_SET_MSK); + return ALT_E_SUCCESS; + case ALT_16550_DEVICE_ALTERA_16550_UART: + default: + return alt_16550_reset_helper(handle, false); + } +} + +ALT_STATUS_CODE alt_16550_reset(ALT_16550_HANDLE_t * handle) +{ + return alt_16550_reset_helper(handle, true); +} + +ALT_STATUS_CODE alt_16550_enable(ALT_16550_HANDLE_t * handle) +{ + // Write the divisor cached in the handle data to the divisor registers. + // This will effectively enable the UART. + return alt_16550_write_divisor_helper(handle, + ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data)); +} + +ALT_STATUS_CODE alt_16550_disable(ALT_16550_HANDLE_t * handle) +{ + // Write 0 to the divisor the divisor registers. This will effectively + // disable the UART. + return alt_16550_write_divisor_helper(handle, 0); +} + +ALT_STATUS_CODE alt_16550_read(ALT_16550_HANDLE_t * handle, + char * item) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is disabled + if (handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the RBR (Receive Buffer Register) into *item. + *item = ALT_UART_RBR_THR_DLL_VALUE_GET(alt_read_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location))); + break; + default: + return ALT_E_ERROR; + } + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_write(ALT_16550_HANDLE_t * handle, + char item) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is disabled + if (handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write the buffer into the THR (Transmit Holding Register) + alt_write_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location), item); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_16550_fifo_enable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set FCR::FIFOE (FIFO Control Register :: FIFO Enable) bit. + handle->fcr |= ALT_UART_FCR_FIFOE_SET_MSK; + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + // No need to reset / clear the FIFOs. This is done automatically when + // FCR::FIFOE is changed. + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_disable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear FCR::FIFOE (FIFO Control Register :: FIFO Enable) bit. + handle->fcr &= ~ALT_UART_FCR_FIFOE_SET_MSK; + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_read(ALT_16550_HANDLE_t * handle, + char * buffer, + size_t count) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the RBR (Receive Buffer Register) into the buffer + for (size_t i = 0; i < count; ++i) + { + buffer[i] = ALT_UART_RBR_THR_DLL_VALUE_GET(alt_read_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location))); + } + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_write(ALT_16550_HANDLE_t * handle, + const char * buffer, + size_t count) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write the buffer into the THR (Transmit Holding Register) + for (size_t i = 0; i < count; ++i) + { + alt_write_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location), buffer[i]); + } + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_clear_rx(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::RFR (Shadow Reset Register :: Receiver FIFO Reset) bit. + alt_write_word(ALT_UART_SRR_ADDR(handle->location), ALT_UART_SRR_RFR_SET_MSK); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write FCR::RFIFOR (FIFO Control Register :: Receiver FIFO Reset) bit. + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr | ALT_UART_FCR_RFIFOR_SET_MSK); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_clear_tx(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::XFR (Shadow Reset Register :: Xmitter FIFO Reset) bit. + alt_write_word(ALT_UART_SRR_ADDR(handle->location), ALT_UART_SRR_XFR_SET_MSK); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write FCR::XFIFOR (FIFO Control Register :: Xmitter FIFO Reset) bit. + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr | ALT_UART_FCR_XFIFOR_SET_MSK); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_clear_all(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::(RFR | XFR) + // (Shadow Reset Register :: (Receiver FIFO Reset | Xmitter FIFO Reset)) bits. + alt_write_word(ALT_UART_SRR_ADDR(handle->location), + ALT_UART_SRR_RFR_SET_MSK | ALT_UART_SRR_XFR_SET_MSK); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write FCR::(RFIFOR |XFIFOR) + // (FIFO Control Register :: (Receiver FIFO Reset | Xmitter FIFO Reset)) bits. + alt_write_word(ALT_UART_FCR_ADDR(handle->location), + handle->fcr | ALT_UART_FCR_RFIFOR_SET_MSK | ALT_UART_FCR_XFIFOR_SET_MSK); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_size_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * size) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read the CPR::FIFO_Mod (Component Parameter Register :: FIFO Mode). + // The FIFO size is 16x this value. + *size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Altera 16550 Compatible Soft UARTs have a configurable size and is + // stored in the CPR::FIFO_Mode (Component Parameter Register :: FIFO Depth). + *size = ALT_ALTERA_16550_CPR_FIFO_MODE_GET(alt_read_word(ALT_ALTERA_16550_CPR_ADDR(handle->location))) << 4; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_size_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * size) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read the CPR::FIFO_Mod (Component Parameter Register :: FIFO Mode). + // The FIFO size is 16x this value. + *size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Altera 16550 Compatible Soft UARTs have a configurable size and is + // stored in the CPR::FIFO_Mode (Component Parameter Register :: FIFO Depth). + // The FIFO size is 16x this value. + *size = ALT_ALTERA_16550_CPR_FIFO_MODE_GET(alt_read_word(ALT_ALTERA_16550_CPR_ADDR(handle->location))) << 4; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_level_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * level) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read RFL (Receive FIFO Level). + *level = alt_read_word(ALT_UART_RFL_ADDR(handle->location)); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // RFL not implemented. Return 0. + *level = 0; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_level_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * level) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read TFL (Transmit FIFO Level). + *level = alt_read_word(ALT_UART_TFL_ADDR(handle->location)); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // TFL not implemented. Return 0. + *level = 0; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_trigger_set_rx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_RX_t trigger) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + // Verify triggering parameter + switch (trigger) + { + case ALT_16550_FIFO_TRIGGER_RX_ANY: + case ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL: + case ALT_16550_FIFO_TRIGGER_RX_HALF_FULL: + case ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Update FCR::RT (FIFO Control Register :: Receiver Trigger) + handle->fcr &= ~ALT_UART_FCR_RT_SET_MSK; + handle->fcr |= ALT_UART_FCR_RT_SET(trigger); + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_trigger_set_tx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_TX_t trigger) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + // Verify triggering parameter + switch (trigger) + { + case ALT_16550_FIFO_TRIGGER_TX_EMPTY: + case ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY: + case ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL: + case ALT_16550_FIFO_TRIGGER_TX_HALF_FULL: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Update FCR::TET (FIFO Control Register :: Transmit Empty Trigger) + handle->fcr &= ~ALT_UART_FCR_TET_SET_MSK; + handle->fcr |= ALT_UART_FCR_TET_SET(trigger); + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_16550_baudrate_get(ALT_16550_HANDLE_t * handle, + uint32_t * baudrate) +{ + // Query the divisor cached in the handle data + uint32_t divisor = ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data); + + // The divisor should never be zero. It is set to allow for a baud of 57600 + // on initialization and a valid value is checked at + // alt_16550_divisor_set(). We do not check for users altering the data in + // the handle structure. + + // Formula for calculating the baudrate: + // baudrate = clock / (16 * divisor) + + *baudrate = (handle->clock_freq >> 4) / divisor; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_baudrate_set(ALT_16550_HANDLE_t * handle, + uint32_t baudrate) +{ + if (baudrate == 0) + { + return ALT_E_ARG_RANGE; + } + + // Formula for calculating the divisor: + // baudrate = clock / (16 * divisor) + // => baudrate * 16 * divisor = clock + // => divisor = clock / (baudrate * 16) + // => divisor = (clock / 16) / baudrate + + // Add half of the denominator to address rounding errors. + uint32_t divisor = ((handle->clock_freq + (8 * baudrate)) / (16 * baudrate)); + + // Check for divisor range is in alt_16550_divisor_set(). + return alt_16550_divisor_set(handle, divisor); +} + +ALT_STATUS_CODE alt_16550_divisor_get(ALT_16550_HANDLE_t * handle, + uint32_t * divisor) +{ + // Just read the divisor portion of the handle data. + *divisor = ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_divisor_set(ALT_16550_HANDLE_t * handle, + uint32_t divisor) +{ + // Verify divisor value is in range. + if ((divisor > 0xffff) || (divisor == 0)) + { + return ALT_E_ARG_RANGE; + } + + // Set the divisor portion of the handle data. + handle->data &= ~(0xffff); + handle->data |= divisor; + + // Even if the UART is enabled, don't do anything. It is documented that + // the change will take effect when the UART move to the enabled state. + + return ALT_E_SUCCESS; +} + +///// + +static ALT_STATUS_CODE alt_16550_ier_mask_set_helper(ALT_16550_HANDLE_t * handle, uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set bit in IER (Interrupt Enable Register) + alt_setbits_word(ALT_UART_IER_DLH_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +static ALT_STATUS_CODE alt_16550_ier_mask_clr_helper(ALT_16550_HANDLE_t * handle, uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear bit in IER (Interrupt Enable Register) + alt_clrbits_word(ALT_UART_IER_DLH_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_int_enable_rx(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::ERBFI (Interrupt Enable Register :: Enable Receive Buffer Full Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_rx(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::ERBFI (Interrupt Enable Register :: Enable Receive Buffer Full Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_enable_tx(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::ETBEI (Interrupt Enable Register :: Enable Transmit Buffer Empty Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_tx(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::ETBEI (Interrupt Enable Register :: Enable Transmit Buffer Empty Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_enable_line(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::ELSI (Interrupt Enable Register :: Enable Line Status Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_line(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::ELSI (Interrupt Enable Register :: Enable Line Status Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_enable_modem(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::EDSSI (Interrupt Enable Register :: Enable Modem Status Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_modem(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::EDSSI (Interrupt Enable Register :: Enable Modem Status Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_all(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::(ERBFI | ETBEI | ELSI | EDSSI) + // (Interrupt Enable Register :: (Enable Receive Buffer Full Interrupt | + // Enable Transmit Buffer Empty Interrupt | + // Enable Line Status Interrupt | + // Enable Modem Status Interrupt)) bits + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK | + ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK | + ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK | + ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_status_get(ALT_16550_HANDLE_t * handle, + ALT_16550_INT_STATUS_t * status) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read IIR::IID (Interrupt Identity Register :: Interrupt ID) + *status = (ALT_16550_INT_STATUS_t) ALT_UART_IIR_ID_GET(alt_read_word(ALT_UART_IIR_ADDR(handle->location))); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_16550_line_config_set(ALT_16550_HANDLE_t * handle, + ALT_16550_DATABITS_t databits, + ALT_16550_PARITY_t parity, + ALT_16550_STOPBITS_t stopbits) +{ + // Validate the databits parameter. + switch (databits) + { + case ALT_16550_DATABITS_5: + case ALT_16550_DATABITS_6: + case ALT_16550_DATABITS_7: + case ALT_16550_DATABITS_8: + break; + default: + return ALT_E_ERROR; + } + + // Validate the parity parameter. + switch (parity) + { + case ALT_16550_PARITY_DISABLE: + case ALT_16550_PARITY_ODD: + case ALT_16550_PARITY_EVEN: + break; + default: + return ALT_E_ERROR; + } + + // Validate the stopbits parameter. + switch (stopbits) + { + case ALT_16550_STOPBITS_1: + case ALT_16550_STOPBITS_2: + break; + default: + return ALT_E_ERROR; + } + + // LCR (Line Control Register) cache. + uint32_t lcr = 0; + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + + // Configure the number of databits + lcr |= ALT_UART_LCR_DLS_SET(databits); + + // Configure the number of stopbits + lcr |= ALT_UART_LCR_STOP_SET(stopbits); + + // Configure the parity + if (parity != ALT_16550_PARITY_DISABLE) + { + // Enable parity in LCR + lcr |= ALT_UART_LCR_PEN_SET_MSK; + + if (parity == ALT_16550_PARITY_EVEN) + { + // Enable even parity in LCR; otherwise it's odd parity. + lcr |= ALT_UART_LCR_EPS_SET_MSK; + } + } + + // Update LCR (Line Control Register) + alt_replbits_word(ALT_UART_LCR_ADDR(handle->location), + ALT_UART_LCR_DLS_SET_MSK + | ALT_UART_LCR_STOP_SET_MSK + | ALT_UART_LCR_PEN_SET_MSK + | ALT_UART_LCR_EPS_SET_MSK, + lcr); + + break; + + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_line_break_enable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set the LCR::Break (Line Control Register :: Break) bit. + alt_setbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_BREAK_SET_MSK); + break; + + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_line_break_disable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear the LCR::Break (Line Control Register :: Break) bit. + alt_clrbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_BREAK_SET_MSK); + break; + + default: + return ALT_E_ERROR; + } + + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_line_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the LSR (Line Status Register). + *status = alt_read_word(ALT_UART_LSR_ADDR(handle->location)); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +static ALT_STATUS_CODE alt_16550_mcr_mask_set_helper(ALT_16550_HANDLE_t * handle, + uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set the bit in MCR (Modem Control Register). + alt_setbits_word(ALT_UART_MCR_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +static ALT_STATUS_CODE alt_16550_mcr_mask_clr_helper(ALT_16550_HANDLE_t * handle, uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear the bit in MCR (Modem Control Register). + alt_clrbits_word(ALT_UART_MCR_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_flowcontrol_enable(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + // For the Altera 16550 Compatible Soft UART, check that Hardware Flowcontrol is enabled. + if (handle->device == ALT_16550_DEVICE_ALTERA_16550_UART) + { + // Read the CPR::AFCE_Mode (Component Parameter Register :: Auto Flow Control mode) bit. + uint32_t cpr = alt_read_word(ALT_ALTERA_16550_CPR_ADDR(handle->location)); + if (!(ALT_ALTERA_16550_CPR_AFCE_MODE_SET_MSK & cpr)) + { + return ALT_E_ERROR; + } + } + + // Set MCR::AFCE (Modem Control Register :: Automatic FlowControl Enable) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_AFCE_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_flowcontrol_disable(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::AFCE (Modem Control Register :: Automatic FlowControl Enable) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_AFCE_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_loopback_enable(ALT_16550_HANDLE_t * handle) +{ + // Loopback is not implemented in the Altera 16550 Compatible Soft UART. + if (handle->device == ALT_16550_DEVICE_ALTERA_16550_UART) + { + return ALT_E_ERROR; + } + + // Set MCR::Loopback (Modem Control Register :: Loopback) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_LOOPBACK_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_loopback_disable(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::Loopback (Modem Control Register :: Loopback) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_LOOPBACK_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_out1(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::Out1 (Modem Control Register :: Out1) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_OUT1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_out1(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::Out1 (Modem Control Register :: Out1) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_OUT1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_out2(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::Out2 (Modem Control Register :: Out2) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_OUT2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_out2(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::Out2 (Modem Control Register :: Out2) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_OUT2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_rts(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::RTS (Modem Control Register :: Request To Send) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_RTS_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_rts(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::RTS (Modem Control Register :: Request To Send) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_RTS_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_dtr(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::DTR (Modem Control Register :: Data Terminal Ready) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_DTR_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_dtr(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::DTR (Modem Control Register :: Data Terminal Ready) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_DTR_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the MSR (Modem Status Register). + *status = alt_read_word(ALT_UART_MSR_ADDR(handle->location)); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma.c new file mode 100644 index 0000000..2bdc519 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma.c @@ -0,0 +1,3749 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include +#include "alt_dma.h" +#include "socal/socal.h" +#include "socal/hps.h" +#include "socal/alt_rstmgr.h" +#include "socal/alt_sysmgr.h" + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT +#include "alt_16550_uart.h" +#include "socal/alt_uart.h" +#endif + +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT +#include "socal/alt_qspi.h" +#endif + +///// + +#ifndef MIN +#define MIN(a, b) ((a) > (b) ? (b) : (a)) +#endif // MIN + +#ifndef ARRAY_COUNT +#define ARRAY_COUNT(array) (sizeof(array) / sizeof(array[0])) +#endif + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) + +///// + +// +// SoCAL stand in for DMA Controller registers +// +// The base can be one of the following: +// - ALT_DMANONSECURE_ADDR +// - ALT_DMASECURE_ADDR +// +// Macros which have a channel parameter does no validation. +// + +// DMA Manager Status Register +#define ALT_DMA_DSR_OFST 0x0 +#define ALT_DMA_DSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DSR_OFST)) +#define ALT_DMA_DSR_DMASTATUS_SET_MSK 0x0000000f +#define ALT_DMA_DSR_DMASTATUS_GET(value) ((value) & 0x0000000f) + +// DMA Program Counter Register +#define ALT_DMA_DPC_OFST 0x4 +#define ALT_DMA_DPC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DPC_OFST)) + +// Interrupt Enable Register +#define ALT_DMA_INTEN_OFST 0x20 +#define ALT_DMA_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTEN_OFST)) + +// Event-Interrupt Raw Status Register +#define ALT_DMA_INT_EVENT_RIS_OFST 0x24 +#define ALT_DMA_INT_EVENT_RIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INT_EVENT_RIS_OFST)) + +// Interrupt Status Register +#define ALT_DMA_INTMIS_OFST 0x28 +#define ALT_DMA_INTMIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTMIS_OFST)) + +// Interrupt Clear Register +#define ALT_DMA_INTCLR_OFST 0x2c +#define ALT_DMA_INTCLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTCLR_OFST)) + +// Fault Status DMA Manager Register +#define ALT_DMA_FSRD_OFST 0x30 +#define ALT_DMA_FSRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRD_OFST)) + +// Fault Status DMA Channel Register +#define ALT_DMA_FSRC_OFST 0x34 +#define ALT_DMA_FSRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRC_OFST)) + +// Fault Type DMA Manager Register +#define ALT_DMA_FTRD_OFST 0x38 +#define ALT_DMA_FTRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRD_OFST)) + +// Fault Type DMA Channel Registers +#define ALT_DMA_FTRx_OFST(channel) (0x40 + 0x4 * (channel)) +#define ALT_DMA_FTRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FTRx_OFST(channel))) + +// Channel Status Registers +#define ALT_DMA_CSRx_OFST(channel) (0x100 + 0x8 * (channel)) +#define ALT_DMA_CSRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CSRx_OFST(channel))) +#define ALT_DMA_CSRx_CHANNELSTATUS_SET_MSK 0x0000000f +#define ALT_DMA_CSRx_CHANNELSTATUS_GET(value) ((value) & 0x0000000f) + +// Channel Program Counter Registers +#define ALT_DMA_CPCx_OFST(channel) (0x104 + 0x8 * (channel)) +#define ALT_DMA_CPCx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CPCx_OFST(channel))) + +// Source Address Registers +#define ALT_DMA_SARx_OFST(channel) (0x400 + 0x20 * (channel)) +#define ALT_DMA_SARx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_SARx_OFST(channel))) + +// Destination Address Registers +#define ALT_DMA_DARx_OFST(channel) (0x404 + 0x20 * (channel)) +#define ALT_DMA_DARx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DARx_OFST(channel))) + +// Channel Control Registers +#define ALT_DMA_CCRx_OFST(channel) (0x408 + 0x20 * (channel)) +#define ALT_DMA_CCRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CCRx_OFST(channel))) + +// Loop Counter 0 Registers +#define ALT_DMA_LC0_x_OFST(channel) (0x40c + 0x20 * (channel)) +#define ALT_DMA_LC0_x_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_LC0_x_OFST(channel))) + +// Loop Counter 1 Registers +#define ALT_DMA_LC1_x_OFST(channel) (0x410 + 0x20 * (channel)) +#define ALT_DMA_LC1_x_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_LC1_x_OFST(channel))) + +// Debug Status Register +#define ALT_DMA_DBGSTATUS_OFST 0xd00 +#define ALT_DMA_DBGSTATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGSTATUS_OFST)) + +// Debug Command Register +#define ALT_DMA_DBGCMD_OFST 0xd04 +#define ALT_DMA_DBGCMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGCMD_OFST)) + +// Debug Instruction-0 Register +#define ALT_DMA_DBGINST0_OFST 0xd08 +#define ALT_DMA_DBGINST0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGINST0_OFST)) +#define ALT_DMA_DBGINST0_CHANNELNUMBER_SET(value) (((value) & 0x7) << 8) +#define ALT_DMA_DBGINST0_DEBUGTHREAD_SET(value) ((value) & 0x1) +#define ALT_DMA_DBGINST0_DEBUGTHREAD_E_MANAGER 0 +#define ALT_DMA_DBGINST0_DEBUGTHREAD_E_CHANNEL 1 +#define ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(value) (((value) & 0xff) << 16) +#define ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(value) (((value) & 0xff) << 24) + +// Debug Instruction-1 Register +#define ALT_DMA_DBGINST1_OFST 0xd0c +#define ALT_DMA_DBGINST1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGINST1_OFST)) + +// Configuration Registers 0 - 4 +#define ALT_DMA_CR0_OFST 0xe00 +#define ALT_DMA_CR1_OFST 0xe04 +#define ALT_DMA_CR2_OFST 0xe08 +#define ALT_DMA_CR3_OFST 0xe0c +#define ALT_DMA_CR4_OFST 0xe10 +#define ALT_DMA_CR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR0_OFST)) +#define ALT_DMA_CR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR1_OFST)) +#define ALT_DMA_CR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR2_OFST)) +#define ALT_DMA_CR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR3_OFST)) +#define ALT_DMA_CR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR4_OFST)) + +// DMA Configuration Register +#define ALT_DMA_CRD_OFST 0xe14 +#define ALT_DMA_CRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CRD_OFST)) + +// Watchdog Register +#define ALT_DMA_WD_OFST 0xe80 +#define ALT_DMA_WD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_WD_OFST)) + +///// + +// +// Internal Data structures +// + +// This flag marks the channel as being allocated. +#define ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED (1 << 0) + +typedef struct ALT_DMA_CHANNEL_INFO_s +{ + uint8_t flag; +} +ALT_DMA_CHANNEL_INFO_t; + +static ALT_DMA_CHANNEL_INFO_t channel_info_array[8]; + +///// + +ALT_STATUS_CODE alt_dma_init(const ALT_DMA_CFG_t * dma_cfg) +{ + // Initialize the channel information array + for (int i = 0; i < 8; ++i) + { + channel_info_array[i].flag = 0; + } + + // Update the System Manager DMA configuration items + + uint32_t dmactrl = 0; + + // Handle FPGA / CAN muxing + for (int i = 0; i < 4; ++i) + { + // The default is FPGA. + switch (dma_cfg->periph_mux[i]) + { + case ALT_DMA_PERIPH_MUX_DEFAULT: + case ALT_DMA_PERIPH_MUX_FPGA: + break; + case ALT_DMA_PERIPH_MUX_CAN: + dmactrl |= (ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK << i); + break; + default: + return ALT_E_ERROR; + } + } + + // Handle Manager security + // Default is Secure state. + switch (dma_cfg->manager_sec) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + break; + case ALT_DMA_SECURITY_NONSECURE: + dmactrl |= ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK; + break; + default: + return ALT_E_ERROR; + } + + // Handle IRQ security + for (int i = 0; i < ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH; ++i) + { + // Default is Secure state. + switch (dma_cfg->irq_sec[i]) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + break; + case ALT_DMA_SECURITY_NONSECURE: + dmactrl |= (1 << (i + ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB)); + break; + default: + return ALT_E_ERROR; + } + } + + alt_write_word(ALT_SYSMGR_DMA_CTL_ADDR, dmactrl); + + // Update the System Manager DMA peripheral security items + + uint32_t dmapersecurity = 0; + + for (int i = 0; i < 32; ++i) + { + // Default is Secure state. + switch (dma_cfg->periph_sec[i]) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + break; + case ALT_DMA_SECURITY_NONSECURE: + dmapersecurity |= (1 << i); + break; + default: + return ALT_E_ERROR; + } + } + + alt_write_word(ALT_SYSMGR_DMA_PERSECURITY_ADDR, dmapersecurity); + + // Take DMA out of reset. + + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_DMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_uninit(void) +{ + // DMAKILL all channel and free all allocated channels. + for (int i = 0; i < 8; ++i) + { + if (channel_info_array[i].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED) + { + alt_dma_channel_kill((ALT_DMA_CHANNEL_t)i); + alt_dma_channel_free((ALT_DMA_CHANNEL_t)i); + } + } + + // Put DMA into reset. + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_DMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_alloc(ALT_DMA_CHANNEL_t channel) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is unallocated + + if (channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED) + { + return ALT_E_ERROR; + } + + // Mark channel as allocated + + channel_info_array[channel].flag |= ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_alloc_any(ALT_DMA_CHANNEL_t * allocated) +{ + // Sweep channel array for unallocated channel + + for (int i = 0; i < 8; ++i) + { + if (!(channel_info_array[i].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + // Allocate that free channel. + + ALT_STATUS_CODE status = alt_dma_channel_alloc((ALT_DMA_CHANNEL_t)i); + if (status == ALT_E_SUCCESS) + { + *allocated = (ALT_DMA_CHANNEL_t)i; + } + return status; + } + } + + // No free channels found. + + return ALT_E_ERROR; +} + +ALT_STATUS_CODE alt_dma_channel_free(ALT_DMA_CHANNEL_t channel) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is allocated + + if (!(channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + return ALT_E_ERROR; + } + + // Verify channel is stopped + + ALT_DMA_CHANNEL_STATE_t state; + ALT_STATUS_CODE status = alt_dma_channel_state_get(channel, &state); + if (status != ALT_E_SUCCESS) + { + return status; + } + if (state != ALT_DMA_CHANNEL_STATE_STOPPED) + { + return ALT_E_ERROR; + } + + // Mark channel as unallocated. + + channel_info_array[channel].flag &= ~ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_exec(ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_t * pgm) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is allocated + + if (!(channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + return ALT_E_ERROR; + } + + // Verify channel is stopped + + ALT_DMA_CHANNEL_STATE_t state; + ALT_STATUS_CODE status = alt_dma_channel_state_get(channel, &state); + if (status != ALT_E_SUCCESS) + { + return status; + } + if (state != ALT_DMA_CHANNEL_STATE_STOPPED) + { + return ALT_E_ERROR; + } + + // Validate the program + + if (alt_dma_program_validate(pgm) != ALT_E_SUCCESS) + { + return ALT_E_ERROR; + } + + // + // Execute the program + // + + // Get the start address + + uint32_t start = (uint32_t) &pgm->program[pgm->buffer_start]; + + dprintf("DMA[exec]: pgm->program = %p.\n", pgm->program); + dprintf("DMA[exec]: start = %p.\n", (void *)start); + + // Configure DBGINST0 and DBGINST1 to execute DMAGO targetting the requested channel. + + // For information on APB Interface, see PL330, section 2.5.1. + // For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21. + // For information on DMAGO, see PL330, section 4.3.5. + + alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR), + ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0xa0) | + ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(channel)); + + alt_write_word(ALT_DMA_DBGINST1_ADDR(ALT_DMASECURE_ADDR), start); + + // Execute the instruction held in DBGINST{0,1} + + // For information on DBGCMD, see PL330, section 3.3.19. + + alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_kill(ALT_DMA_CHANNEL_t channel) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is allocated + + if (!(channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + return ALT_E_ERROR; + } + + // NOTE: Don't worry about the current channel state. Just issue DMAKILL + // instruction. The channel state cannot move from from Stopped back to + // Killing. + + // Configure DBGINST0 to execute DMAKILL on the requested channel thread. + // DMAKILL is short enough not to use DBGINST1 register. + + // For information on APB Interface, see PL330, section 2.5.1. + // For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21. + // For information on DMAKILL, see PL330, section 4.3.6. + + alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR), + ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0x1) | + ALT_DMA_DBGINST0_CHANNELNUMBER_SET(channel) | + ALT_DMA_DBGINST0_DEBUGTHREAD_SET(ALT_DMA_DBGINST0_DEBUGTHREAD_E_CHANNEL)); + + // Execute the instruction held in DBGINST0 + + // For information on DBGCMD, see PL330, section 3.3.19. + + alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0); + + // Wait for channel to move to KILLING or STOPPED state. Do not wait for + // the STOPPED only. If the AXI transaction hangs permanently, it can be + // waiting indefinately. + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + ALT_DMA_CHANNEL_STATE_t current; + uint32_t i = 20000; + + while (--i) + { + status = alt_dma_channel_state_get(channel, ¤t); + if (status != ALT_E_SUCCESS) + { + break; + } + if ( (current == ALT_DMA_CHANNEL_STATE_KILLING) + || (current == ALT_DMA_CHANNEL_STATE_STOPPED)) + { + break; + } + } + + if (i == 0) + { + status = ALT_E_TMO; + } + + return status; +} + +ALT_STATUS_CODE alt_dma_channel_reg_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_REG_t reg, uint32_t * val) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on SAR, see PL330, section 3.3.13. + // For information on DAR, see PL330, section 3.3.14. + // For information on CCR, see PL330, section 3.3.15. + + switch (reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + *val = alt_read_word(ALT_DMA_SARx_ADDR(ALT_DMASECURE_ADDR, channel)); + break; + case ALT_DMA_PROGRAM_REG_DAR: + *val = alt_read_word(ALT_DMA_DARx_ADDR(ALT_DMASECURE_ADDR, channel)); + break; + case ALT_DMA_PROGRAM_REG_CCR: + *val = alt_read_word(ALT_DMA_CCRx_ADDR(ALT_DMASECURE_ADDR, channel)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_send_event(ALT_DMA_EVENT_t evt_num) +{ + // Validate evt_num + + switch (evt_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // Issue the DMASEV on the DMA manager thread. + // DMASEV is short enough not to use DBGINST1 register. + + // For information on APB Interface, see PL330, section 2.5.1. + // For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21. + // For information on DMASEV, see PL330, section 4.3.15. + + alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR), + ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0x34) | // opcode for DMASEV + ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(evt_num << 3) | + ALT_DMA_DBGINST0_DEBUGTHREAD_SET(ALT_DMA_DBGINST0_DEBUGTHREAD_E_MANAGER) + ); + + // Execute the instruction held in DBGINST0 + + // For information on DBGCMD, see PL330, section 3.3.19. + + alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_manager_state_get(ALT_DMA_MANAGER_STATE_t * state) +{ + // For information on DSR, see PL330, section 3.3.1. + + uint32_t raw_state = alt_read_word(ALT_DMA_DSR_ADDR(ALT_DMASECURE_ADDR)); + + *state = (ALT_DMA_MANAGER_STATE_t)ALT_DMA_DSR_DMASTATUS_GET(raw_state); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_state_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_CHANNEL_STATE_t * state) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on CSR, see PL330, section 3.3.11. + + uint32_t raw_state = alt_read_word(ALT_DMA_CSRx_ADDR(ALT_DMASECURE_ADDR, channel)); + + *state = (ALT_DMA_CHANNEL_STATE_t)ALT_DMA_CSRx_CHANNELSTATUS_GET(raw_state); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_manager_fault_status_get(ALT_DMA_MANAGER_FAULT_t * fault) +{ + // For information on FTRD, see PL330, section 3.3.9. + + *fault = (ALT_DMA_MANAGER_FAULT_t)alt_read_word(ALT_DMA_FTRD_ADDR(ALT_DMASECURE_ADDR)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_fault_status_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_CHANNEL_FAULT_t * fault) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on FTR, see PL330, section 3.3.10. + + *fault = (ALT_DMA_CHANNEL_FAULT_t)alt_read_word(ALT_DMA_FTRx_ADDR(ALT_DMASECURE_ADDR, channel)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_event_int_select(ALT_DMA_EVENT_t evt_num, + ALT_DMA_EVENT_SELECT_t opt) +{ + // Validate evt_num + switch (evt_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INTEN, see PL330, section 3.3.3. + + switch (opt) + { + case ALT_DMA_EVENT_SELECT_SEND_EVT: + alt_clrbits_word(ALT_DMA_INTEN_ADDR(ALT_DMASECURE_ADDR), 1 << evt_num); + break; + case ALT_DMA_EVENT_SELECT_SIG_IRQ: + alt_setbits_word(ALT_DMA_INTEN_ADDR(ALT_DMASECURE_ADDR), 1 << evt_num); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_event_int_status_get_raw(ALT_DMA_EVENT_t evt_num) +{ + // Validate evt_num + switch (evt_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INT_EVENT_RIS, see PL330, section 3.3.4. + + uint32_t status_raw = alt_read_word(ALT_DMA_INT_EVENT_RIS_ADDR(ALT_DMASECURE_ADDR)); + + if (status_raw & (1 << evt_num)) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +ALT_STATUS_CODE alt_dma_int_status_get(ALT_DMA_EVENT_t irq_num) +{ + // Validate evt_num + switch (irq_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INTMIS, see PL330, section 3.3.5. + + uint32_t int_status = alt_read_word(ALT_DMA_INTMIS_ADDR(ALT_DMASECURE_ADDR)); + + if (int_status & (1 << irq_num)) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +ALT_STATUS_CODE alt_dma_int_clear(ALT_DMA_EVENT_t irq_num) +{ + // Validate evt_num + switch (irq_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INTCLR, see PL330, section 3.3.6. + + alt_write_word(ALT_DMA_INTCLR_ADDR(ALT_DMASECURE_ADDR), 1 << irq_num); + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_dma_memory_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst, + const void * src, + size_t size, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the size is zero, and no event is requested, just return success. + if ((size == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (size != 0) + { + uintptr_t udst = (uintptr_t)dst; + uintptr_t usrc = (uintptr_t)src; + + dprintf("DMA[M->M]: dst = %p.\n", dst); + dprintf("DMA[M->M]: src = %p.\n", src); + dprintf("DMA[M->M]: size = 0x%x.\n", size); + + // Detect if memory regions overshoots the address space. + + if (udst + size - 1 < udst) + { + return ALT_E_BAD_ARG; + } + if (usrc + size - 1 < usrc) + { + return ALT_E_BAD_ARG; + } + + // Detect if memory regions overlaps. + + if (udst > usrc) + { + if (usrc + size - 1 > udst) + { + return ALT_E_BAD_ARG; + } + } + else + { + if (udst + size - 1 > usrc) + { + return ALT_E_BAD_ARG; + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, usrc); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, udst); + } + + size_t sizeleft = size; + + // + // The algorithm uses the strategy described in PL330 B.3.1. + // It is extended for 2-byte and 1-byte unaligned cases. + // + + // First see how many byte(s) we need to transfer to get src to be 8 byte aligned + if (usrc & 0x7) + { + uint32_t aligncount = MIN(8 - (usrc & 0x7), sizeleft); + sizeleft -= aligncount; + + dprintf("DMA[M->M]: Total pre-alignment 1-byte burst size tranfer(s): %lu.\n", aligncount); + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SBx (Source burst length of [aligncount] transfers) + // - DBx (Destination burst length of [aligncount] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ((aligncount - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((aligncount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + // This is the number of 8-byte bursts + uint32_t burstcount = sizeleft >> 3; + + bool correction = (burstcount != 0); + + // Update the size left to transfer + sizeleft &= 0x7; + + dprintf("DMA[M->M]: Total Main 8-byte burst size transfer(s): %lu.\n", burstcount); + dprintf("DMA[M->M]: Total Main 1-byte burst size transfer(s): %u.\n", sizeleft); + + // Determine how many 16 length bursts can be done + + if (burstcount >> 4) + { + uint32_t length16burstcount = burstcount >> 4; + burstcount &= 0xf; + + dprintf("DMA[M->M]: Number of 16 burst length 8-byte transfer(s): %lu.\n", length16burstcount); + dprintf("DMA[M->M]: Number of remaining 8-byte transfer(s): %lu.\n", burstcount); + + // Program in the following parameters: + // - SS64 (Source burst size of 8-byte) + // - DS64 (Destination burst size of 8-byte) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SS64 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (length16burstcount > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(length16burstcount, 256); + length16burstcount -= loopcount; + + dprintf("DMA[M->M]: Looping %lux 16 burst length 8-byte transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [burstcount] 8-byte transfer(s) + // remaining. [burstcount] should be less than 16. + + // Do one more burst with a SB / DB of length [burstcount]. + + if (burstcount) + { + // Program in the following parameters: + // - SS64 (Source burst size of 8-byte) + // - DS64 (Destination burst size of 8-byte) + // - SBx (Source burst length of [burstlength] transfers) + // - DBx (Destination burst length of [burstlength] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ((burstcount - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SS64 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((burstcount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + // This is where the last DMAMOV CCR and DMAST is done if an + // alignment correction required. + + if ( (correction == true) + && ((usrc & 0x7) != (udst & 0x7)) // If src and dst are mod-8 congruent, no correction is needed. + ) + { + if (status == ALT_E_SUCCESS) + { + // Determine what type of correction. + + // Set the source parameters to match that of the destination + // parameters. This way the SAR is increment in the same fashion as + // DAR. This will allow the non 8-byte transfers to copy correctly. + + uint32_t ccr; + + if ((usrc & 0x3) == (udst & 0x3)) + { + dprintf("DMA[M->M]: Single correction 4-byte burst size tranfer.\n"); + + // Program in the following parameters: + // - SS32 (Source burst size of 4-byte) + // - DS32 (Destination burst size of 4-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - All other options default. + + ccr = ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ); + } + else if ((usrc & 0x1) == (udst & 0x1)) + { + dprintf("DMA[M->M]: Single correction 2-byte burst size tranfer.\n"); + + // Program in the following parameters: + // - SS16 (Source burst size of 2-byte) + // - DS16 (Destination burst size of 2-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - All other options default. + + ccr = ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS16 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS16 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ); + } + else + { + dprintf("DMA[M->M]: Single correction 1-byte burst size tranfer.\n"); + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - All other options default. + + ccr = ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ); + } + + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ccr); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + // At this point, there should be 0 - 7 1-byte transfers remaining. + + if (sizeleft) + { + dprintf("DMA[M->M]: Total post 1-byte burst size tranfer(s): %u.\n", sizeleft); + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SBx (Source burst length of [sizeleft] transfers) + // - DBx (Destination burst length of [sizeleft] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ((sizeleft - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((sizeleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } // if (size != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->M]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_zero_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * buf, + size_t size, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the size is zero, and no event is requested, just return success. + if ((size == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (size != 0) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)buf); + } + + dprintf("DMA[Z->M]: buf = %p.\n", buf); + dprintf("DMA[Z->M]: size = 0x%x.\n", size); + + size_t sizeleft = size; + + // First see how many byte(s) we need to transfer to get dst to be 8 byte aligned. + if ((uint32_t)buf & 0x7) + { + uint32_t aligncount = MIN(8 - ((uint32_t)buf & 0x7), sizeleft); + sizeleft -= aligncount; + + dprintf("DMA[Z->M]: Total pre-alignment 1-byte burst size tranfer(s): %lu.\n", aligncount); + + // Program in the following parameters: + // - DS8 (Destination burst size of 1-byte) + // - DBx (Destination burst length of [aligncount] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((aligncount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + } + + // This is the number of 8-byte bursts left + uint32_t burstcount = sizeleft >> 3; + + // Update the size left to transfer + sizeleft &= 0x7; + + dprintf("DMA[Z->M]: Total Main 8-byte burst size transfer(s): %lu.\n", burstcount); + dprintf("DMA[Z->M]: Total Main 1-byte burst size transfer(s): %u.\n", sizeleft); + + // Determine how many 16 length bursts can be done + if (burstcount >> 4) + { + uint32_t length16burstcount = burstcount >> 4; + burstcount &= 0xf; + + dprintf("DMA[Z->M]: Number of 16 burst length 8-byte transfer(s): %lu.\n", length16burstcount); + dprintf("DMA[Z->M]: Number of remaining 8-byte transfer(s): %lu.\n", burstcount); + + // Program in the following parameters: + // - DS64 (Destination burst size of 8-byte) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (length16burstcount > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(length16burstcount, 256); + length16burstcount -= loopcount; + + dprintf("DMA[Z->M]: Looping %lux 16 burst length 8-byte transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [burstcount] 8-byte transfer(s) + // remaining. [burstcount] should be less than 16. + + // Do one more burst with a SB / DB of length [burstcount]. + + if (burstcount) + { + // Program in the following parameters: + // - DS64 (Destination burst size of 8-byte) + // - DBx (Destination burst length of [burstlength] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((burstcount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + } + + // At this point, there should be 0 - 7 1-byte transfers remaining. + + if (sizeleft) + { + dprintf("DMA[Z->M]: Total post 1-byte burst size tranfer(s): %u.\n", sizeleft); + + // Program in the following parameters: + // - DS8 (Destination burst size of 1-byte) + // - DBx (Destination burst length of [sizeleft] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((sizeleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + } + } // if (size != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[Z->M]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_memory_to_register(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst_reg, + const void * src_buf, + size_t count, + uint32_t register_width_bits, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the count is zero, and no event is requested, just return success. + if ((count == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (count != 0) + { + // Verify valid register_width_bits and construct the CCR SS and DS parameters. + uint32_t ccr_ss_ds_mask = 0; + + if (status == ALT_E_SUCCESS) + { + switch (register_width_bits) + { + case 8: + // Program in the following parameters: + // - SS8 (Source burst size of 8 bits) + // - DS8 (Destination burst size of 8 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_DS8; + break; + case 16: + // Program in the following parameters: + // - SS16 (Source burst size of 16 bits) + // - DS16 (Destination burst size of 16 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS16 | ALT_DMA_CCR_OPT_DS16; + break; + case 32: + // Program in the following parameters: + // - SS32 (Source burst size of 32 bits) + // - DS32 (Destination burst size of 32 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS32 | ALT_DMA_CCR_OPT_DS32; + break; + case 64: + // Program in the following parameters: + // - SS64 (Source burst size of 64 bits) + // - DS64 (Destination burst size of 64 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS64 | ALT_DMA_CCR_OPT_DS64; + break; + default: + status = ALT_E_BAD_ARG; + break; + } + } + + // Verify that the dst_reg and src_buf are aligned to the register width + if (status == ALT_E_SUCCESS) + { + if (((uintptr_t)dst_reg & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else if (((uintptr_t)src_buf & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else + { + dprintf("DMA[M->R]: dst_reg = %p.\n", dst_reg); + dprintf("DMA[M->R]: src_buf = %p.\n", src_buf); + dprintf("DMA[M->R]: count = 0x%x.\n", count); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, (uint32_t)src_buf); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)dst_reg); + } + + // This is the remaining count left to process. + uint32_t countleft = count; + + // See how many 16-length bursts we can use + if (countleft >> 4) + { + // Program in the following parameters: + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - DAF (Destination address fixed) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + uint32_t length16burst = countleft >> 4; + countleft &= 0xf; + + dprintf("DMA[M->R]: Number of 16 burst length transfer(s): %lu.\n", length16burst); + dprintf("DMA[M->R]: Number of remaining transfer(s): %lu.\n", countleft); + + // See how many 256x 16-length bursts we can use + if (length16burst >> 8) + { + uint32_t loop256length16burst = length16burst >> 8; + length16burst &= ((1 << 8) - 1); + + dprintf("DMA[M->R]: Number of 256-looped 16 burst length transfer(s): %lu.\n", loop256length16burst); + dprintf("DMA[M->R]: Number of remaining 16 burst length transfer(s): %lu.\n", length16burst); + + while (loop256length16burst > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(loop256length16burst, 256); + loop256length16burst -= loopcount; + + dprintf("DMA[M->R]: Looping %lux super loop transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // The super loop above ensures that the length16burst is below 256. + if (length16burst > 0) + { + uint32_t loopcount = length16burst; + length16burst = 0; + + dprintf("DMA[M->R]: Looping %lux 16 burst length transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [countleft] transfer(s) remaining. + // [countleft] should be less than 16. + + if (countleft) + { + // Program in the following parameters: + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - DAF (Destination address fixed) + // - SBx (Source burst length of [countleft] transfer(s)) + // - DBx (Destination burst length of [countleft] transfer(s)) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->R]: Tail end %lux transfer(s).\n", countleft); + + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ((countleft - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((countleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (count != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->R]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->R]: DMAEND program.\n"); + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_register_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst_buf, + const void * src_reg, + size_t count, + uint32_t register_width_bits, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the count is zero, and no event is requested, just return success. + if ((count == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (count != 0) + { + // Verify valid register_width_bits and construct the CCR SS and DS parameters. + uint32_t ccr_ss_ds_mask = 0; + + if (status == ALT_E_SUCCESS) + { + switch (register_width_bits) + { + case 8: + // Program in the following parameters: + // - SS8 (Source burst size of 8 bits) + // - DS8 (Destination burst size of 8 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_DS8; + break; + case 16: + // Program in the following parameters: + // - SS16 (Source burst size of 16 bits) + // - DS16 (Destination burst size of 16 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS16 | ALT_DMA_CCR_OPT_DS16; + break; + case 32: + // Program in the following parameters: + // - SS32 (Source burst size of 32 bits) + // - DS32 (Destination burst size of 32 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS32 | ALT_DMA_CCR_OPT_DS32; + break; + case 64: + // Program in the following parameters: + // - SS64 (Source burst size of 64 bits) + // - DS64 (Destination burst size of 64 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS64 | ALT_DMA_CCR_OPT_DS64; + break; + default: + dprintf("DMA[R->M]: Invalid register width.\n"); + status = ALT_E_BAD_ARG; + break; + } + } + + // Verify that the dst_buf and src_reg are aligned to the register width + if (status == ALT_E_SUCCESS) + { + if (((uintptr_t)dst_buf & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else if (((uintptr_t)src_reg & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else + { + dprintf("DMA[R->M]: dst_reg = %p.\n", dst_buf); + dprintf("DMA[R->M]: src_buf = %p.\n", src_reg); + dprintf("DMA[R->M]: count = 0x%x.\n", count); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, (uint32_t)src_reg); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)dst_buf); + } + + // This is the remaining count left to process. + uint32_t countleft = count; + + // See how many 16-length bursts we can use + if (countleft >> 4) + { + uint32_t length16burst = countleft >> 4; + countleft &= 0xf; + + dprintf("DMA[R->M]: Number of 16 burst length transfer(s): %lu.\n", length16burst); + dprintf("DMA[R->M]: Number of remaining transfer(s): %lu.\n", countleft); + + // + // The algorithm uses the strategy described in PL330 B.2.3. + // Not sure if registers will accept burst transfers so read the register in its own transfer. + // + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // See how many 256x 16-length bursts we can do + if (length16burst >> 8) + { + uint32_t loop256length16burst = length16burst >> 8; + length16burst &= ((1 << 8) - 1); + + dprintf("DMA[R->M]: Number of 256-looped 16 burst length transfer(s): %lu.\n", loop256length16burst); + dprintf("DMA[R->M]: Number of remaining 16 burst length transfer(s): %lu.\n", length16burst); + + while (loop256length16burst > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(loop256length16burst, 256); + loop256length16burst -= loopcount; + + dprintf("DMA[R->M]: Looping %lux super loop transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // The super loop above ensures that the length16burst is below 256. + if (length16burst > 0) + { + uint32_t loopcount = length16burst; + length16burst = 0; + + dprintf("DMA[R->M]: Looping %lux 16 burst length transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [countleft] transfer(s) remaining. + // [countleft] should be less than 16. + + if (countleft) + { + dprintf("DMA[R->M]: Tail end %lux transfer(s).\n", countleft); + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - SBx (Source burst length of [countleft] transfer(s)) + // - DBx (Destination burst length of [countleft] transfer(s)) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ((countleft - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((countleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (count != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[R->M]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT +static ALT_STATUS_CODE alt_dma_memory_to_qspi(ALT_DMA_PROGRAM_t * program, + const char * src, + size_t size) +{ + if ((uintptr_t)src & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, + (uint32_t)ALT_QSPIDATA_ADDR); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, + (uint32_t)src); + } + + ///// + + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + uint32_t qspi_single_size_log2 = ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(dmaper); + uint32_t qspi_burst_size_log2 = ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(dmaper); + uint32_t qspi_single_size = 1 << qspi_single_size_log2; + uint32_t qspi_burst_size = 1 << qspi_burst_size_log2; + + dprintf("DMA[M->P][QSPI]: QSPI Single = %lu; Burst = %lu.\n", qspi_single_size, qspi_burst_size); + + // Because single transfers are equal or smaller than burst (and in the + // smaller case, it is always a clean multiple), only the single size + // check is needed for transfer composability. + if (size & (qspi_single_size - 1)) + { + dprintf("DMA[M->P][QSPI]: QSPI DMA size configuration not suitable for transfer request.\n"); + return ALT_E_ERROR; + } + + ///// + + if ((uintptr_t)src & 0x7) + { + // Source address is not 8-byte aligned. Do 1x 32-bit transfer to get it 8-byte aligned. + + dprintf("DMA[M->P][QSPI]: Creating 1x 4-byte aligning transfer.\n"); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAI + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + size -= sizeof(uint32_t); + } + + uint32_t qspi_single_count = 0; + uint32_t qspi_burst_count = size >> qspi_burst_size_log2; + + // Use QSPI burst transfers if: + // - QSPI bursts are larger than QSPI singles [AND] + // - Size is large enough that at least 1 burst will be used. + + if ( (qspi_burst_size_log2 > qspi_single_size_log2) + && (qspi_burst_count != 0) + ) + { + // qspi_burst_count = size >> qspi_burst_size_log2; + qspi_single_count = (size & (qspi_burst_size - 1)) >> qspi_single_size_log2; + + dprintf("DMA[M->P][QSPI][B]: Burst size = %lu bytes, count = %lu.\n", qspi_burst_size, qspi_burst_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t src_size_log2 = MIN(3, qspi_burst_size_log2); + + uint32_t src_length = 0; + uint32_t src_multiple = 0; + + if ((qspi_burst_size >> src_size_log2) <= 16) + { + src_length = qspi_burst_size >> src_size_log2; + src_multiple = 1; + } + else + { + src_length = 16; + src_multiple = (qspi_burst_size >> src_size_log2) >> 4; // divide by 16 + + if (src_multiple == 0) + { + dprintf("DEBUG[QSPI][B]: src_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t dst_length = 1; // dst_length is always 1 because the address is fixed. + uint32_t dst_multiple = qspi_burst_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[M->P][QSPI][B]: dst_size = %u bits, dst_length = %u, dst_multiple = %lu.\n", + 32, 1, dst_multiple); + dprintf("DMA[M->P][QSPI][B]: src_size = %u bits, src_length = %lu, src_multiple = %lu.\n", + (1 << src_size_log2) * 8, src_length, src_multiple); + + ///// + + // Program in the following parameters: + // - SAI (Source address increment) + // - SSx (Source burst size of [1 << src_size_log2]-bytes) + // - SBx (Source burst length of [src_length] transfer(s)) + // - DAF (Destination address fixed) + // - DS32 (Destination burst size of 4-bytes) + // - DB1 (Destination burst length of 1 transfer) + // - All other parameters default + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAI + | (src_size_log2 << 1) // SS + | ((src_length - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // NOTE: We do not do the 256x bursts for M->P case because we only + // write up to 256 B at a time. + + while (qspi_burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_burst_count, 256); + qspi_burst_count -= loopcount; + + dprintf("DMA[M->P][QSPI][B]: Creating %lu burst-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + else + { + qspi_single_count = size >> qspi_single_size_log2; + } + + // Assemble the single portion of the DMA program. + if (qspi_single_count) + { + dprintf("DMA[M->P][QSPI][S]: Single size = %lu bytes, count = %lu.\n", qspi_single_size, qspi_single_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t src_size_log2 = MIN(3, qspi_single_size_log2); + + uint32_t src_length = 0; + uint32_t src_multiple = 0; + + if ((qspi_single_size >> src_size_log2) <= 16) + { + src_length = qspi_single_size >> src_size_log2; + src_multiple = 1; + } + else + { + src_length = 16; + src_multiple = (qspi_single_size >> src_size_log2) >> 4; // divide by 16 + + if (src_multiple == 0) + { + dprintf("DEBUG[QSPI][S]: src_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t dst_length = 1; // dst_length is always 1 becaus the address is fixed. + uint32_t dst_multiple = qspi_single_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[M->P][QSPI][S]: dst_size = %u bits, dst_length = %u, dst_multiple = %lu.\n", + 32, 1, dst_multiple); + dprintf("DMA[M->P][QSPI][S]: src_size = %u bits, src_length = %lu, src_multiple = %lu.\n", + (1 <P case because we only + // write up to 256 B at a time. + + while (qspi_single_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_single_count, 256); + qspi_single_count -= loopcount; + + dprintf("DMA[M->P][QSPI][S]: Creating %lu single-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (qspi_single_count != 0) + + return status; +} + +static ALT_STATUS_CODE alt_dma_qspi_to_memory(ALT_DMA_PROGRAM_t * program, + char * dst, + size_t size) +{ + if ((uintptr_t)dst & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, + (uint32_t)dst); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, + (uint32_t)ALT_QSPIDATA_ADDR); + } + + ///// + + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + uint32_t qspi_single_size_log2 = ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(dmaper); + uint32_t qspi_burst_size_log2 = ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(dmaper); + uint32_t qspi_single_size = 1 << qspi_single_size_log2; + uint32_t qspi_burst_size = 1 << qspi_burst_size_log2; + + dprintf("DMA[P->M][QSPI]: QSPI Single = %lu; Burst = %lu.\n", qspi_single_size, qspi_burst_size); + + // Because single transfers are equal or smaller than burst (and in the + // smaller case, it is always a clean multiple), only the single size + // check is needed for transfer composability. + if (size & (qspi_single_size - 1)) + { + dprintf("DMA[P->M][QSPI]: QSPI DMA size configuration not suitable for transfer request.\n"); + return ALT_E_ERROR; + } + + ///// + + if ((uintptr_t)dst & 0x7) + { + // Destination address is not 8-byte aligned. Do 1x 32-bit transfer to get it 8-byte aligned. + + dprintf("DMA[P->M][QSPI]: Creating 1x 4-byte aligning transfer.\n"); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAI + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + size -= sizeof(uint32_t); + } + + uint32_t qspi_single_count = 0; + uint32_t qspi_burst_count = size >> qspi_burst_size_log2; + + // Use QSPI burst transfers if: + // - QSPI bursts are larger than QSPI singles [AND] + // - Size is large enough that at least 1 burst will be used. + + if ( (qspi_burst_size_log2 > qspi_single_size_log2) + && (qspi_burst_count != 0) + ) + { + // qspi_burst_count = size >> qspi_burst_size_log2; + qspi_single_count = (size & (qspi_burst_size - 1)) >> qspi_single_size_log2; + + dprintf("DMA[P->M][QSPI][B]: Burst size = %lu bytes, count = %lu.\n", qspi_burst_size, qspi_burst_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t dst_size_log2 = MIN(3, qspi_burst_size_log2); + + uint32_t dst_length = 0; + uint32_t dst_multiple = 0; + + if ((qspi_burst_size >> dst_size_log2) <= 16) + { + dst_length = qspi_burst_size >> dst_size_log2; + dst_multiple = 1; + } + else + { + dst_length = 16; + dst_multiple = (qspi_burst_size >> dst_size_log2) >> 4; // divide by 16 + + if (dst_multiple == 0) + { + dprintf("DEBUG[QSPI][B]: dst_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t src_length = 1; // src_length is always 1 because the address is fixed. + uint32_t src_multiple = qspi_burst_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[P->M][QSPI][B]: dst_size = %u bits, dst_length = %lu, dst_multiple = %lu.\n", + (1 << dst_size_log2) * 8, dst_length, dst_multiple); + dprintf("DMA[P->M][QSPI][B]: src_size = %u bits, src_length = %u, src_multiple = %lu.\n", + 32, 1, src_multiple); + + ///// + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SS32 (Source burst size of 4-bytes) + // - SB1 (Source burst length of 1 transfer) + // - DAI (Destination address increment) + // - DSx (Destination burst size of [1 << dst_size_log2]-bytes]) + // - DBx (Destination burst length of [dst_length] transfer(s)) + // - All other parameters default + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAI + | (dst_size_log2 << 15) // DS + | ((dst_length - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // See how many 256x bursts we can construct. This will allow for extremely large requests. + + if (qspi_burst_count >> 8) + { + uint32_t qspi_burst256_count = qspi_burst_count >> 8; + qspi_burst_count &= (1 << 8) - 1; + + while (qspi_burst256_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_burst256_count, 256); + qspi_burst256_count -= loopcount; + + dprintf("DMA[P->M][QSPI][B]: Creating %lu 256x burst-type transfer(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + // Inner loop { + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Outer loop + } + } + + while (qspi_burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_burst_count, 256); + qspi_burst_count -= loopcount; + + dprintf("DMA[P->M][QSPI][B]: Creating %lu burst-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + else + { + qspi_single_count = size >> qspi_single_size_log2; + } + + // Assemble the single portion of the DMA program. + if (qspi_single_count) + { + dprintf("DMA[P->M][QSPI][S]: Single size = %lu bytes, count = %lu.\n", qspi_single_size, qspi_single_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t dst_size_log2 = MIN(3, qspi_single_size_log2); + + uint32_t dst_length = 0; + uint32_t dst_multiple = 0; + + if ((qspi_single_size >> dst_size_log2) <= 16) + { + dst_length = qspi_single_size >> dst_size_log2; + dst_multiple = 1; + } + else + { + dst_length = 16; + dst_multiple = (qspi_single_size >> dst_size_log2) >> 4; // divide by 16 + + if (dst_multiple == 0) + { + dprintf("DEBUG[QSPI][S]: dst_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t src_length = 1; // src_length is always 1 because the address is fixed. + uint32_t src_multiple = qspi_single_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[P->M][QSPI][S]: dst_size = %u bits, dst_length = %lu, dst_multiple = %lu.\n", + (1 << dst_size_log2) * 8, dst_length, dst_multiple); + dprintf("DMA[P->M][QSPI][S]: src_size = %u bits, src_length = %u, src_multiple = %lu.\n", + 32, 1, src_multiple); + + ///// + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SS32 (Source burst size of 4-bytes) + // - SB1 (Source burst length of 1 transfer) + // - DAI (Destination address increment) + // - DSx (Destination burst size of [1 << dst_size_log2]-bytes]) + // - DBx (Destination burst length of [dst_length] transfer(s)) + // - All other parameters default + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAI + | (dst_size_log2 << 15) // DS + | ((dst_length - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // See how many 256x bursts we can construct. This will allow for extremely large requests. + + if (qspi_single_count >> 8) + { + uint32_t qspi_single256_count = qspi_single_count >> 8; + qspi_single_count &= (1 << 8) - 1; + + while (qspi_single256_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_single256_count, 256); + qspi_single256_count -= loopcount; + + dprintf("DMA[P->M][QSPI][S]: Creating %lu 256x single-type transfer(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + // Inner loop { + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Outer loop + } + } + + while (qspi_single_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_single_count, 256); + qspi_single_count -= loopcount; + + dprintf("DMA[P->M][QSPI][S]: Creating %lu single-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (qspi_single_count != 0) + + return status; +} +#endif // ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT +static ALT_STATUS_CODE alt_dma_memory_to_16550_single(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - DAF (Destination address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + uint32_t sizeleft = size; + + while (sizeleft > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(sizeleft, 256); + sizeleft -= loopcount; + + dprintf("DMA[M->P][16550][S]: Creating %lu transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_memory_to_16550_burst(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t burst_size, + size_t burst_count) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - DAF (Source address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(burst_count, 256); + burst_count -= loopcount; + + dprintf("DMA[M->P][16550][B]: Creating outer %lu inner loop(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // Inner loop { + + // Loop [burst_size / 16] times. The burst_size was trimmed to the + // nearest multiple of 16 by the caller. Each burst does 16 transfers + // hence the need for the divide. + + dprintf("DMA[M->P][16550][B]: Creating inner %u transfer(s).\n", burst_size >> 4); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, burst_size >> 4); // divide by 16. + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Outer loop + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_memory_to_16550(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + ALT_16550_HANDLE_t * handle, + const void * src, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, + (uint32_t)ALT_UART_RBR_THR_DLL_ADDR(handle->location)); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, + (uint32_t)src); + } + + // Determine if FIFOs are enabled from the FCR cache + + if (ALT_UART_FCR_FIFOE_GET(handle->fcr) != 0) + { + dprintf("DMA[M->P][16550]: FIFOs enabled.\n"); + + // + // FIFOs are enabled. + // + + uint32_t tx_size; + uint32_t burst_size; + ALT_16550_FIFO_TRIGGER_TX_t trig_tx; + + // Get the TX FIFO Size + // Use the register interface to avoid coupling the 16550 and DMA. + tx_size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + + // Get the TX FIFO Trigger Level from the FCR cache + trig_tx = (ALT_16550_FIFO_TRIGGER_TX_t)ALT_UART_FCR_TET_GET(handle->fcr); + + switch (trig_tx) + { + case ALT_16550_FIFO_TRIGGER_TX_EMPTY: + burst_size = tx_size; + break; + case ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY: + burst_size = tx_size - 2; + break; + case ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL: + burst_size = 3 * (tx_size >> 2); + break; + case ALT_16550_FIFO_TRIGGER_TX_HALF_FULL: + burst_size = tx_size >> 1; + break; + default: + // This case should never happen. + return ALT_E_ERROR; + } + + if (burst_size < 16) + { + // There's no point bursting 1 byte at a time per notify, so just do single transfers. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_single(program, + periph, + size); + } + } + else + { + uint32_t sizeleft = size; + + // Now trip the burst size to a multiple of 16. + // This will optimize the bursting in the fewest possible commands. + dprintf("DMA[M->P][16550]: Untrimmed burst size = %lu.\n", burst_size); + burst_size &= ~0xf; + dprintf("DMA[M->P][16550]: Trimmed burst size = %lu.\n", burst_size); + + // Determine how many burst transfers can be done + uint32_t burst_count = 0; + + burst_count = sizeleft / burst_size; + sizeleft -= burst_count * burst_size; + + if (burst_count == 0) + { + // Do the transfer + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_single(program, + periph, + sizeleft); + } + } + else + { + // Do the burst transfers + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_burst(program, + periph, + burst_size, + burst_count); + } + + // Program the DMA engine to transfer the non-burstable items in single tranfers + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_single(program, + periph, + sizeleft); + } + + } // else if (burst_count == 0) + } + } + else + { + dprintf("DMA[M->P][16550]: FIFOs disabled.\n"); + + // + // FIFOs are disabled. + // + + status = alt_dma_memory_to_16550_single(program, + periph, + size); + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_16550_to_memory_single(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - SAF (Source address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + uint32_t sizeleft = size; + + while (sizeleft > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(sizeleft, 256); + sizeleft -= loopcount; + + dprintf("DMA[P->M][16550][S]: Creating %lu transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_16550_to_memory_burst(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t burst_size, + size_t burst_count) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - SAF (Source address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(burst_count, 256); + burst_count -= loopcount; + + dprintf("DMA[P->M][16550][B]: Creating outer %lu inner loop(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // Inner loop { + + // Loop [burst_size / 16] times. The burst_size was trimmed to the + // nearest multiple of 16 by the caller. Each burst does 16 transfers + // hence the need for the divide. + + dprintf("DMA[P->M][16550][B]: Creating inner %u transfer(s).\n", burst_size >> 4); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, burst_size >> 4); // divide by 16. + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Outer loop + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_16550_to_memory(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + ALT_16550_HANDLE_t * handle, + void * dst, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)dst); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, (uint32_t)ALT_UART_RBR_THR_DLL_ADDR(handle->location)); + } + + // Determine if FIFOs are enabled from the FCR cache + + if (ALT_UART_FCR_FIFOE_GET(handle->fcr) != 0) + { + dprintf("DMA[P->M][16550]: FIFOs enabled.\n"); + + // + // FIFOs are enabled. + // + + uint32_t rx_size; + uint32_t burst_size; + ALT_16550_FIFO_TRIGGER_RX_t trig_rx; + + // Get the RX FIFO Size + // Use the register interface to avoid coupling the 16550 and DMA. + rx_size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + + // Get the RX FIFO Trigger Level from the FCR cache + trig_rx = (ALT_16550_FIFO_TRIGGER_RX_t)ALT_UART_FCR_RT_GET(handle->fcr); + + switch (trig_rx) + { + case ALT_16550_FIFO_TRIGGER_RX_ANY: + burst_size = 1; + break; + case ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL: + burst_size = rx_size >> 2; // divide by 4 + break; + case ALT_16550_FIFO_TRIGGER_RX_HALF_FULL: + burst_size = rx_size >> 1; // divide by 2 + break; + case ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL: + burst_size = rx_size - 2; + break; + default: + // This case should never happen. + return ALT_E_ERROR; + } + + if (burst_size < 16) + { + // There's no point bursting 1 byte at a time per notify, so just do single transfers. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_single(program, + periph, + size); + } + } + else + { + uint32_t sizeleft = size; + + // Now trim the burst size to a multiple of 16. + // This will optimize the bursting in the fewest possible commands. + dprintf("DMA[P->M][16550]: Untrimmed burst size = %lu.\n", burst_size); + burst_size &= ~0xf; + dprintf("DMA[P->M][16550]: Trimmed burst size = %lu.\n", burst_size); + + // Determine how many burst transfers can be done + uint32_t burst_count = 0; + + burst_count = sizeleft / burst_size; + sizeleft -= burst_count * burst_size; + + if (burst_count == 0) + { + // Do the transfer. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_single(program, + periph, + sizeleft); + } + } + else + { + // Do the burst transfers + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_burst(program, + periph, + burst_size, + burst_count); + } + + // Program the DMA engine to transfer the non-burstable items in single transfers. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_single(program, + periph, + sizeleft); + } + + } // if (burst_count == 0) + } + } + else + { + dprintf("DMA[P->M][16550]: FIFOs disabled.\n"); + + // + // FIFOs are disabled. + // + + status = alt_dma_16550_to_memory_single(program, + periph, + size); + } + + return status; +} +#endif // ALT_DMA_PERIPH_PROVISION_16550_SUPPORT + +ALT_STATUS_CODE alt_dma_memory_to_periph(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t dstp, + const void * src, + size_t size, + void * periph_info, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if ((size == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->P]: Init Program.\n"); + status = alt_dma_program_init(program); + } + + if ((status == ALT_E_SUCCESS) && (size != 0)) + { + switch (dstp) + { +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT + case ALT_DMA_PERIPH_QSPI_FLASH_TX: + status = alt_dma_memory_to_qspi(program, src, size); + break; +#endif + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT + case ALT_DMA_PERIPH_UART0_TX: + case ALT_DMA_PERIPH_UART1_TX: + status = alt_dma_memory_to_16550(program, dstp, + (ALT_16550_HANDLE_t *)periph_info, src, size); + break; +#endif + + case ALT_DMA_PERIPH_FPGA_0: + case ALT_DMA_PERIPH_FPGA_1: + case ALT_DMA_PERIPH_FPGA_2: + case ALT_DMA_PERIPH_FPGA_3: + case ALT_DMA_PERIPH_FPGA_4: + case ALT_DMA_PERIPH_FPGA_5: + case ALT_DMA_PERIPH_FPGA_6: + case ALT_DMA_PERIPH_FPGA_7: + case ALT_DMA_PERIPH_I2C0_TX: + case ALT_DMA_PERIPH_I2C1_TX: + case ALT_DMA_PERIPH_I2C2_TX: + case ALT_DMA_PERIPH_I2C3_TX: + case ALT_DMA_PERIPH_SPI0_MASTER_TX: + case ALT_DMA_PERIPH_SPI0_SLAVE_TX: + case ALT_DMA_PERIPH_SPI1_MASTER_TX: + case ALT_DMA_PERIPH_SPI1_SLAVE_TX: + + default: + status = ALT_E_BAD_ARG; + break; + } + } + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->P]: Adding event.\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_periph_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst, + ALT_DMA_PERIPH_t srcp, + size_t size, + void * periph_info, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if ((size == 0) && (send_evt == false)) + { + return ALT_E_SUCCESS; + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[P->M]: Init Program.\n"); + status = alt_dma_program_init(program); + } + + if ((status == ALT_E_SUCCESS) && (size != 0)) + { + switch (srcp) + { +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT + case ALT_DMA_PERIPH_QSPI_FLASH_RX: + status = alt_dma_qspi_to_memory(program, dst, size); + break; +#endif + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT + case ALT_DMA_PERIPH_UART0_RX: + case ALT_DMA_PERIPH_UART1_RX: + status = alt_dma_16550_to_memory(program, srcp, + (ALT_16550_HANDLE_t *)periph_info, dst, size); + break; +#endif + + case ALT_DMA_PERIPH_FPGA_0: + case ALT_DMA_PERIPH_FPGA_1: + case ALT_DMA_PERIPH_FPGA_2: + case ALT_DMA_PERIPH_FPGA_3: + case ALT_DMA_PERIPH_FPGA_4: + case ALT_DMA_PERIPH_FPGA_5: + case ALT_DMA_PERIPH_FPGA_6: + case ALT_DMA_PERIPH_FPGA_7: + case ALT_DMA_PERIPH_I2C0_RX: + case ALT_DMA_PERIPH_I2C1_RX: + case ALT_DMA_PERIPH_I2C2_RX: + case ALT_DMA_PERIPH_I2C3_RX: + case ALT_DMA_PERIPH_SPI0_MASTER_RX: + case ALT_DMA_PERIPH_SPI0_SLAVE_RX: + case ALT_DMA_PERIPH_SPI1_MASTER_RX: + case ALT_DMA_PERIPH_SPI1_SLAVE_RX: + + default: + status = ALT_E_BAD_ARG; + break; + } + } + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[P->M]: Adding event.\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + + return alt_dma_channel_exec(channel, program); +} + +///// + +static bool alt_dma_is_init(void) +{ + uint32_t permodrst = alt_read_word(ALT_RSTMGR_PERMODRST_ADDR); + + if (permodrst & ALT_RSTMGR_PERMODRST_DMA_SET_MSK) + { + return false; + } + else + { + return true; + } +} + +ALT_STATUS_CODE alt_dma_ecc_start(void * block, size_t size) +{ + if (alt_dma_is_init() == false) + { + return ALT_E_ERROR; + } + + if ((uintptr_t)block & (sizeof(uint64_t) - 1)) + { + return ALT_E_ERROR; + } + + // Verify that all channels are either unallocated or allocated and idle. + + for (int i = 0; i < ARRAY_COUNT(channel_info_array); ++i) + { + if (channel_info_array[i].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED) + { + ALT_DMA_CHANNEL_STATE_t state; + alt_dma_channel_state_get((ALT_DMA_CHANNEL_t)i, &state); + + if (state != ALT_DMA_CHANNEL_STATE_STOPPED) + { + dprintf("DMA[ECC]: Error: Channel %d state is non-stopped (%d).\n", i, (int)state); + return ALT_E_ERROR; + } + } + } + + ///// + + // Enable ECC for DMA RAM + + dprintf("DEBUG[DMA][ECC]: Enable ECC in SysMgr.\n"); + alt_write_word(ALT_SYSMGR_ECC_DMA_ADDR, ALT_SYSMGR_ECC_DMA_EN_SET_MSK); + + // Clear any pending spurious DMA ECC interrupts. + + dprintf("DEBUG[DMA][ECC]: Clear any pending spurious ECC status in SysMgr.\n"); + alt_write_word(ALT_SYSMGR_ECC_DMA_ADDR, + ALT_SYSMGR_ECC_DMA_EN_SET_MSK + | ALT_SYSMGR_ECC_DMA_SERR_SET_MSK + | ALT_SYSMGR_ECC_DMA_DERR_SET_MSK); + + return ALT_E_SUCCESS; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma_program.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma_program.c new file mode 100644 index 0000000..26de4c7 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma_program.c @@ -0,0 +1,1064 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_dma_program.h" +#include "alt_cache.h" +#include + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) + +///// + +// +// The following section describes how the bits are used in the "flag" field: +// + +// [17:16] Which loop registers (LOOP0, LOOP1) are currently being used by a +// partially assembled program. LOOP0 is always used before LOOP1. LOOP1 is +// always ended before LOOP0. +#define ALT_DMA_PROGRAM_FLAG_LOOP0 (1UL << 16) +#define ALT_DMA_PROGRAM_FLAG_LOOP1 (1UL << 17) +#define ALT_DMA_PROGRAM_FLAG_LOOP_ALL (ALT_DMA_PROGRAM_FLAG_LOOP0 | ALT_DMA_PROGRAM_FLAG_LOOP1) + +// [18] Flag that marks LOOP0 as a forever loop. Said another way, LOOP0 is +// being used to execute the DMALPFE directive. +#define ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE (1UL << 18) +// [19] Flag that marks LOOP1 as a forever loop. Said another way, LOOP1 is +// being used to execute the DMALPFE directive. +#define ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE (1UL << 19) + +// [24] Flag that the first SAR has been programmed. The SAR field is valid and +// is the offset from the start of the buffer where SAR is located. +#define ALT_DMA_PROGRAM_FLAG_SAR (1UL << 24) +// [25] Flag that the first DAR has been programmed. The DAR field is valid and +// is the offset from the start of the buffer where DAR is located. +#define ALT_DMA_PROGRAM_FLAG_DAR (1UL << 25) + +// [31] Flag that marks the last assembled instruction as DMAEND. +#define ALT_DMA_PROGRAM_FLAG_ENDED (1UL << 31) + +///// + +ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm) +{ + // Clear the variables that matter. + pgm->flag = 0; + pgm->code_size = 0; + + // Calculate the cache aligned start location of the buffer. + size_t buffer = (size_t)pgm->program; + size_t offset = ((buffer + ALT_DMA_PROGRAM_CACHE_LINE_SIZE - 1) & ~(ALT_DMA_PROGRAM_CACHE_LINE_SIZE - 1)) - buffer; + + // It is safe to cast to uint16_t because the extra offset can only be up to + // (ALT_DMA_PROGRAM_CACHE_LINE_SIZE - 1) or 31, which is within range of the + // uint16_t. + pgm->buffer_start = (uint16_t)offset; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm) +{ + // Clear the variables that matter + pgm->flag = 0; + pgm->code_size = 0; + + return ALT_E_SUCCESS; +} + +__attribute__((weak)) ALT_STATUS_CODE alt_cache_system_clean(void * address, size_t length) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm) +{ + // Verify that at least one instruction is in the buffer + if (pgm->code_size == 0) + { + return ALT_E_ERROR; + } + + // Verify all loops are completed. + if (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + return ALT_E_ERROR; + } + + // Verify last item is DMAEND + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_ENDED)) + { + return ALT_E_ERROR; + } + + // Sync the DMA program to RAM. + void * vaddr = (void *)((uintptr_t)(pgm->program + pgm->buffer_start) & ~(ALT_CACHE_LINE_SIZE - 1)); + size_t length = (pgm->code_size + ALT_CACHE_LINE_SIZE) & ~(ALT_CACHE_LINE_SIZE - 1); + + dprintf("DEBUG[DMAP]: Program (real) @ %p, length = 0x%x.\n", pgm->program + pgm->buffer_start, pgm->code_size); + dprintf("DEBUG[DMAP]: Clean: addr = %p, length = 0x%x.\n", vaddr, length); + + return alt_cache_system_clean(vaddr, length); +} + +ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, + uint32_t current, uint32_t * progress) +{ + // Pointer to where the register is initialized in the program buffer. + uint8_t * buffer = NULL; + + switch (reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_SAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->sar; + break; + + case ALT_DMA_PROGRAM_REG_DAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_DAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->dar; + break; + + default: + return ALT_E_BAD_ARG; + } + + uint32_t initial = + (buffer[3] << 24) | + (buffer[2] << 16) | + (buffer[1] << 8) | + (buffer[0] << 0); + + *progress = current - initial; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, uint32_t val) +{ + uint8_t * buffer = NULL; + + switch (reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_SAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->sar; + break; + + case ALT_DMA_PROGRAM_REG_DAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_DAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->dar; + break; + + default: + return ALT_E_BAD_ARG; + } + + buffer[0] = (uint8_t)((val >> 0) & 0xff); + buffer[1] = (uint8_t)((val >> 8) & 0xff); + buffer[2] = (uint8_t)((val >> 16) & 0xff); + buffer[3] = (uint8_t)((val >> 24) & 0xff); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val) +{ + // For information on DMAADDH, see PL330, section 4.3.1. + + // Check for sufficient space in buffer + if ((pgm->code_size + 3) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid register; construct instruction modifier. + uint8_t ra_mask = 0; + switch (addr_reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + ra_mask = 0x0; + break; + case ALT_DMA_PROGRAM_REG_DAR: + ra_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAADDH + buffer[0] = 0x54 | ra_mask; + buffer[1] = (uint8_t)(val & 0xff); + buffer[2] = (uint8_t)(val >> 8); + + // Update the code size. + pgm->code_size += 3; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val) +{ + // For information on DMAADNH, see PL330, section 4.3.2. + + // Check for sufficient space in buffer + if ((pgm->code_size + 3) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid register; construct instruction modifier. + uint8_t ra_mask = 0; + switch (addr_reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + ra_mask = 0x0; + break; + case ALT_DMA_PROGRAM_REG_DAR: + ra_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAADNH + buffer[0] = 0x5c | ra_mask; + buffer[1] = (uint8_t)(val & 0xff); + buffer[2] = (uint8_t)(val >> 8); + + // Update the code size. + pgm->code_size += 3; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMAEND, see PL330, section 4.3.3. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAEND + buffer[0] = 0x00; + + // Update the code size. + pgm->code_size += 1; + + // Mark program as ended. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_ENDED; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph) +{ + // For information on DMAFLUSHP, see PL330, section 4.3.4. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAFLUSHP + buffer[0] = 0x35; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_CHANNEL_t channel, uint32_t val, + ALT_DMA_SECURITY_t sec) +{ + // For information on DMAGO, see PL330, section 4.3.5. + + // Check for sufficient space in buffer + if ((pgm->code_size + 6) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify security; construct ns mask value + uint8_t ns_mask = 0; + switch (sec) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + ns_mask = 0x0; + break; + case ALT_DMA_SECURITY_NONSECURE: + ns_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAGO + buffer[0] = 0xa0 | ns_mask; + buffer[1] = (uint8_t)channel; + buffer[2] = (uint8_t)((val >> 0) & 0xff); + buffer[3] = (uint8_t)((val >> 8) & 0xff); + buffer[4] = (uint8_t)((val >> 16) & 0xff); + buffer[5] = (uint8_t)((val >> 24) & 0xff); + + // Update the code size. + pgm->code_size += 6; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMAKILL, see PL330, section 4.3.6. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAKILL + buffer[0] = 0x01; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMALD, see PL330, section 4.3.7. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs, x mask value. + uint8_t bsx_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_NONE: + bsx_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsx_mask = 0x1; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsx_mask = 0x3; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALD + buffer[0] = 0x04 | bsx_mask; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph) +{ + // For information on DMALDP, see PL330, section 4.3.8. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs mask value. + uint8_t bs_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bs_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bs_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALDP + buffer[0] = 0x25 | bs_mask; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm, + uint32_t iterations) +{ + // For information on DMALP, see PL330, section 4.3.9. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify iterations in range + if ((iterations == 0) || (iterations > 256)) + { + return ALT_E_BAD_ARG; + } + + // Find suitable LOOPx register to use; construct lc mask value. + uint8_t lc_mask = 0; + switch (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + case 0: // No LOOPx in use. Use LOOP0. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP0; + pgm->loop0 = pgm->code_size + 2; // This is the first instruction after the DMALP + lc_mask = 0x0; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP0: // LOOP0 in use. Use LOOP1. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP1; + pgm->loop1 = pgm->code_size + 2; // This is the first instruction after the DMALP + lc_mask = 0x2; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP_ALL: // All LOOPx in use. Report error. + return ALT_E_BAD_OPERATION; + + default: // Catastrophic error !!! + return ALT_E_ERROR; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALP + buffer[0] = 0x20 | lc_mask; + buffer[1] = (uint8_t)(iterations - 1); + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMALPEND, see PL330, section 4.3.10. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs, x mask value. + uint8_t bsx_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_NONE: + bsx_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsx_mask = 0x1; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsx_mask = 0x3; + break; + default: + return ALT_E_BAD_ARG; + } + + // Determine the loop to end, if it is a forever loop; construct lc mask, nf mask, and backwards jump value. + uint8_t lc_mask = 0; + uint8_t nf_mask = 0; + uint16_t backwards_jump = 0; + switch (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + case ALT_DMA_PROGRAM_FLAG_LOOP0: // LOOP0 in use. End LOOP0. + + backwards_jump = pgm->code_size - pgm->loop0; + + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP0; + pgm->loop0 = 0; + + lc_mask = 0x0; + + if (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE) + { + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE; + } + else + { + nf_mask = 0x10; + } + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP_ALL: // All LOOPx in use. End LOOP1. + + backwards_jump = pgm->code_size - pgm->loop1; + + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP1; + pgm->loop1 = 0; + + lc_mask = 0x4; + + if (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE) + { + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE; + } + else + { + nf_mask = 0x10; + } + break; + + case 0: // No LOOPx in use. Report error! + return ALT_E_BAD_OPERATION; + + default: // Catastrophic error !!! + return ALT_E_ERROR; + } + + // Verify that the jump size is suitable + if (backwards_jump > 255) + { + return ALT_E_ARG_RANGE; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALPEND + buffer[0] = 0x28 | nf_mask | lc_mask | bsx_mask; + buffer[1] = (uint8_t)(backwards_jump); + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMALPFE, see PL330, section 4.3.11. + + // Find suitable LOOPx register to use; + switch (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + case 0: // No LOOPx in use. Use LOOP0. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP0; + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE; + pgm->loop0 = pgm->code_size; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP0: // LOOP0 in use. Use LOOP1. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP1; + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE; + pgm->loop1 = pgm->code_size; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP_ALL: // All LOOPx in use. Report error. + return ALT_E_BAD_OPERATION; + + default: // Catastrophic error !!! + return ALT_E_ERROR; + } + + // Nothing to assemble. + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val) +{ + // For information on DMAMOV, see PL330, section 4.3.12. + + // Check for sufficient space in buffer + if ((pgm->code_size + 6) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify channel register; construct rd mask value + uint8_t rd_mask = 0; + switch (chan_reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + rd_mask = 0; + // If SAR has not been set before, mark the location of where SAR is in the buffer. + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_SAR)) + { + pgm->flag |= ALT_DMA_PROGRAM_FLAG_SAR; + pgm->sar = pgm->code_size + 2; + } + break; + + case ALT_DMA_PROGRAM_REG_CCR: + rd_mask = 1; + break; + + case ALT_DMA_PROGRAM_REG_DAR: + rd_mask = 2; + // If DAR has not been set before, mark the location of where DAR is in the buffer. + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_DAR)) + { + pgm->flag |= ALT_DMA_PROGRAM_FLAG_DAR; + pgm->dar = pgm->code_size + 2; + } + break; + + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAMOV + buffer[0] = 0xbc;; + buffer[1] = rd_mask; + buffer[2] = (uint8_t)((val >> 0) & 0xff); + buffer[3] = (uint8_t)((val >> 8) & 0xff); + buffer[4] = (uint8_t)((val >> 16) & 0xff); + buffer[5] = (uint8_t)((val >> 24) & 0xff); + + // Update the code size. + pgm->code_size += 6; + + return ALT_E_SUCCESS; + +} + +ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMANOP, see PL330, section 4.3.13. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMANOP + buffer[0] = 0x18; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMARMB, see PL330, section 4.3.14. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMARMB + buffer[0] = 0x12; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt) +{ + // For information on DMA, see PL330, section 4.3.15. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Validate evt selection + switch (evt) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMASEV + buffer[0] = 0x34; + buffer[1] = (uint8_t)(evt) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMAST, see PL330, section 4.3.16. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs, x mask value. + uint8_t bsx_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_NONE: + bsx_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsx_mask = 0x1; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsx_mask = 0x3; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAST + buffer[0] = 0x08 | bsx_mask; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph) +{ + // For information on DMASTP, see PL330, section 4.3.17. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs mask value. + uint8_t bs_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bs_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bs_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMASTP + buffer[0] = 0x29 | bs_mask; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMASTZ, see PL330, section 4.3.18. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMASTZ + buffer[0] = 0x0c; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt, bool invalid) +{ + // For information on DMAWFE, see PL330, section 4.3.19. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Validate evt selection + switch (evt) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // Construct i mask value + uint8_t i_mask = 0; + if (invalid) + { + i_mask = 0x2; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAWFE + buffer[0] = 0x36; + buffer[1] = ((uint8_t)(evt) << 3) | i_mask; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMAWFP, see PL330, section 4.3.20. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Verify instruction modifier; construct bs, p mask value. + uint8_t bsp_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsp_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsp_mask = 0x2; + break; + case ALT_DMA_PROGRAM_INST_MOD_PERIPH: + bsp_mask = 0x1; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAWFP + buffer[0] = 0x30 | bsp_mask; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMAWMB, see PL330, section 4.3.21. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAWMB + buffer[0] = 0x13; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_qspi.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_qspi.c new file mode 100644 index 0000000..458ef71 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_qspi.c @@ -0,0 +1,2619 @@ +/****************************************************************************** +* +* alt_qspi.c - API for the Altera SoC FPGA QSPI device. +* +******************************************************************************/ + +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include +#include +#include +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "alt_qspi.h" +#include "alt_qspi_private.h" +#include "socal/alt_qspi.h" +#include "socal/alt_rstmgr.h" +#include "socal/alt_sysmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf printf + +///// + +#define MIN(a, b) ((a) > (b) ? (b) : (a)) + +// qspi_clk operating frequency range. +#define ALT_QSPI_CLK_FREQ_MIN ((alt_freq_t)0) +#define ALT_QSPI_CLK_FREQ_MAX ((alt_freq_t)432000000) + +// The set of all valid QSPI controller interrupt status mask values. +#define ALT_QSPI_INT_STATUS_ALL ( \ + ALT_QSPI_INT_STATUS_MODE_FAIL | \ + ALT_QSPI_INT_STATUS_UFL | \ + ALT_QSPI_INT_STATUS_IDAC_OP_COMPLETE | \ + ALT_QSPI_INT_STATUS_IDAC_OP_REJECT | \ + ALT_QSPI_INT_STATUS_WR_PROT_VIOL | \ + ALT_QSPI_INT_STATUS_ILL_AHB_ACCESS | \ + ALT_QSPI_INT_STATUS_IDAC_WTRMK_TRIG | \ + ALT_QSPI_INT_STATUS_RX_OVF | \ + ALT_QSPI_INT_STATUS_TX_FIFO_NOT_FULL | \ + ALT_QSPI_INT_STATUS_TX_FIFO_FULL | \ + ALT_QSPI_INT_STATUS_RX_FIFO_NOT_EMPTY | \ + ALT_QSPI_INT_STATUS_RX_FIFO_FULL | \ + ALT_QSPI_INT_STATUS_IDAC_RD_FULL \ + ) + +static uint32_t qspi_device_size = 0; + +///// + +static ALT_STATUS_CODE alt_qspi_device_status(uint32_t * status) +{ + // Read flag status register through STIG + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_RDSR, 0, 1, status, 10000); +} + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +static ALT_STATUS_CODE alt_qspi_N25Q_device_flag(uint32_t * flagsr) +{ + if (qspi_device_size < 0x4000000) + { + return ALT_E_SUCCESS; + } + + // Read flag status register through STIG + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_RDFLGSR, 0, 1, flagsr, 10000); +} + +// NOTE: This must be called after QSPI has been enabled. Communications with +// the device will not happen until QSPI is enabled. +static inline ALT_STATUS_CODE alt_qspi_N25Q_enable(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Reset the volatile memory on the N25Q + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_RESET_EN, 0, 10000); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_RESET_MEM, 0, 10000); + } + + ///// + + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_DEV_INST_CONFIG_t cfg = + { + .op_code = ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO, + .inst_type = ALT_QSPI_MODE_SINGLE, // RDID does not support QUAD. + .addr_xfer_type = ALT_QSPI_MODE_QUAD, + .data_xfer_type = ALT_QSPI_MODE_QUAD, + .dummy_cycles = 10 + }; + + status = alt_qspi_device_read_config_set(&cfg); + } + +/* + // CASE 157096: Investigate using QUAD for writes. + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_DEV_INST_CONFIG_t cfg = + { + .op_code = ALT_QSPI_STIG_OPCODE_PP, + .inst_type = ALT_QSPI_MODE_SINGLE, + .addr_xfer_type = ALT_QSPI_MODE_QUAD, + .data_xfer_type = ALT_QSPI_MODE_QUAD, + .dummy_cycles = 0 + }; + + status = alt_qspi_device_write_config_set(&cfg); + } +*/ + + return status; +} + +static ALT_STATUS_CODE alt_qspi_N25Q_flag_wait_for_program(uint32_t timeout) +{ + // The flag status register is only available on the 512 Mib and 1 Gib + // (64 MiB and 128 MiB) Micron parts. + if (qspi_device_size < 0x4000000) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t time_out = timeout; + uint32_t stat = 0; + bool infinite = (timeout == ALT_QSPI_TIMEOUT_INFINITE); + + do + { + status = alt_qspi_device_status(&stat); + if (status != ALT_E_SUCCESS) + { + break; + } + if (!ALT_QSPI_STIG_SR_BUSY_GET(stat)) + { + break; + } + } + while (time_out-- || infinite); + + if (time_out == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + uint32_t flagsr = 0; + + do + { + status = alt_qspi_N25Q_device_flag(&flagsr); + if (status != ALT_E_SUCCESS) + { + break; + } + if (ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(flagsr)) + { + break; + } + } + while (timeout-- || infinite); + + if (timeout == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + if (ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(flagsr)) + { + status = ALT_E_ERROR; + } + } + } + return status; +} + +static ALT_STATUS_CODE alt_qspi_N25Q_flag_wait_for_erase(uint32_t timeout) +{ + // The flag status register is only available on the 512 Mib and 1 Gib + // (64 MiB and 128 MiB) Micron parts. + if (qspi_device_size < 0x4000000) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t time_out = timeout; + uint32_t stat = 0; + bool infinite = (timeout == ALT_QSPI_TIMEOUT_INFINITE); + + do + { + status = alt_qspi_device_status(&stat); + if (status != ALT_E_SUCCESS) + { + break; + } + if (!ALT_QSPI_STIG_SR_BUSY_GET(stat)) + { + break; + } + } + while (time_out-- || infinite); + + if (time_out == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + + uint32_t flagsr = 0; + + do + { + status = alt_qspi_N25Q_device_flag(&flagsr); + if (status != ALT_E_SUCCESS) + { + break; + } + if (ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(flagsr)) + { + break; + } + } + while (timeout-- || infinite); + + if (timeout == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + if (ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(flagsr)) + { + status = ALT_E_ERROR; + } + } + } + + return status; +} +#endif + +// +// A helper function which converts a ns interval into a delay interval for a given MHz. +// The +999 is there to round up the result. +// +static inline int alt_qspi_ns_to_multiplier(int ns, int mhz) +{ + return ((ns * mhz) + 999) / 1000; +} + +ALT_STATUS_CODE alt_qspi_init(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + alt_freq_t qspi_clk_freq = 0; + + // Validate QSPI module input clocks. + // - pclk - l4_mp_clk + // - hclk - l4_mp_clk + // - ref_clk - qspi_clk + + // Check and validate the QSPI ref_clk which is connected to the HPS qspi_clk. + if (status == ALT_E_SUCCESS) + { + if (alt_clk_is_enabled(ALT_CLK_QSPI) != ALT_E_TRUE) + { + status = ALT_E_BAD_CLK; + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_clk_freq_get(ALT_CLK_QSPI, &qspi_clk_freq); + if (status == ALT_E_SUCCESS) + { + if (qspi_clk_freq > ALT_QSPI_CLK_FREQ_MAX) + { + return ALT_E_BAD_CLK; + } + } + } + + int qspi_clk_mhz = qspi_clk_freq / 1000000; + + ///// + + // Take QSPI controller out of reset. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_QSPI_SET_MSK); + + ///// + + // Configure the device timing + + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_TIMING_CONFIG_t timing_cfg = + { + .clk_phase = (ALT_QSPI_CLK_PHASE_t)ALT_QSPI_CFG_SELCLKPHASE_RESET, + .clk_pol = (ALT_QSPI_CLK_POLARITY_t)ALT_QSPI_CFG_SELCLKPOL_RESET, + .cs_da = alt_qspi_ns_to_multiplier(ALT_QSPI_TSHSL_NS_DEF, qspi_clk_mhz), + .cs_dads = alt_qspi_ns_to_multiplier(ALT_QSPI_TSD2D_NS_DEF, qspi_clk_mhz), + .cs_eot = alt_qspi_ns_to_multiplier(ALT_QSPI_TCHSH_NS_DEF, qspi_clk_mhz), + .cs_sot = alt_qspi_ns_to_multiplier(ALT_QSPI_TSLCH_NS_DEF, qspi_clk_mhz), + .rd_datacap = 1 + }; + + dprintf("DEBUG[QSPI]: cs_da = %" PRIu32 ".\n", timing_cfg.cs_da); + dprintf("DEBUG[QSPI]: cs_dads = %" PRIu32 ".\n", timing_cfg.cs_dads); + dprintf("DEBUG[QSPI]: cs_eot = %" PRIu32 ".\n", timing_cfg.cs_eot); + dprintf("DEBUG[QSPI]: cs_sot = %" PRIu32 ".\n", timing_cfg.cs_sot); + + status = alt_qspi_timing_config_set(&timing_cfg); + } + + ///// + + // Configure the remap address register, no remap + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_ahb_remap_address_set(0); + } + + // Configure the interrupt mask register, disabled all first + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_int_disable(ALT_QSPI_INT_STATUS_ALL); + } + + // Configure the baud rate divisor + // CASE 157095: Investigate using 108 MHz, and tweaking the rd_datacap param. + + if (status == ALT_E_SUCCESS) + { + uint32_t device_sclk_mhz = 54; + uint32_t div_actual = (qspi_clk_mhz + (device_sclk_mhz - 1)) / device_sclk_mhz; + dprintf("DEBUG[QSPI]: div_actual = %" PRIu32 ".\n", div_actual); + + ALT_QSPI_BAUD_DIV_t div_bits = (ALT_QSPI_BAUD_DIV_t)(((div_actual + 1) / 2) - 1); + status = alt_qspi_baud_rate_div_set(div_bits); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_uninit(void) +{ + // Put QSPI controller into reset. + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_QSPI_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_disable(void) +{ + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_EN_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_enable(void) +{ + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_EN_SET_MSK); + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + ///// + + // Device specific configuration + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_enable(); + } +#endif + + uint32_t rdid = 0; + + // Query device capabilities + // This requires QSPI to be enabled. + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_rdid(&rdid); + } + + if (status == ALT_E_SUCCESS) + { + // NOTE: The size code seems to be a form of BCD (binary coded decimal). + // The first nibble is the 10's digit and the second nibble is the 1's + // digit in the number of bytes. + + // Capacity ID samples: + // 0x15 : 16 Mb => 2 MiB => 1 << 21 ; BCD=15 + // 0x16 : 32 Mb => 4 MiB => 1 << 22 ; BCD=16 + // 0x17 : 64 Mb => 8 MiB => 1 << 23 ; BCD=17 + // 0x18 : 128 Mb => 16 MiB => 1 << 24 ; BCD=18 + // 0x19 : 256 Mb => 32 MiB => 1 << 25 ; BCD=19 + // 0x1a + // 0x1b + // 0x1c + // 0x1d + // 0x1e + // 0x1f + // 0x20 : 512 Mb => 64 MiB => 1 << 26 ; BCD=20 + // 0x21 : 1024 Mb => 128 MiB => 1 << 27 ; BCD=21 + + int cap_code = ALT_QSPI_STIG_RDID_CAPACITYID_GET(rdid); + + if ( ((cap_code >> 4) > 0x9) || ((cap_code & 0xf) > 0x9)) + { + // If a non-valid BCD value is detected at the top or bottom nibble, chances + // are that the chip has a problem. + + dprintf("DEBUG[QSPI]: Invalid CapacityID encountered: 0x%02x.\n", cap_code); + status = ALT_E_ERROR; + } + else + { + int cap_decoded = ((cap_code >> 4) * 10) + (cap_code & 0xf); + + qspi_device_size = 1 << (cap_decoded + 6); + + dprintf("DEBUG[QSPI]: Device size = 0x%" PRIx32 ".\n", qspi_device_size); + } + } + + // Configure the device size and address bytes + + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_DEV_SIZE_CONFIG_t size_cfg = + { + .block_size = ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET, // 0x10 => 2^16 = 64 KiB + .page_size = ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET, // 0x100 => 256 B + .addr_size = ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET, // 0x2 => 3 bytes or 0x00ffffff mask. + .lower_wrprot_block = 0, + .upper_wrprot_block = (qspi_device_size - 1) >> 16, + .wrprot_enable = ALT_QSPI_WRPROT_EN_RESET + }; + + status = alt_qspi_device_size_config_set(&size_cfg); + } + + ///// + + // Configure the DMA parameters + + // This will allow DMA to work well without much intervention by users. + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_dma_config_set(4, 32); + } + + ///// + + return status; +} + +///// + +uint32_t alt_qspi_int_status_get(void) +{ + // Read and return the value of the QSPI controller Interrupt Status + // Register (irqstat). + return alt_read_word(ALT_QSPI_IRQSTAT_ADDR); +} + +ALT_STATUS_CODE alt_qspi_int_clear(const uint32_t mask) +{ + // Check that the [mask] contains valid interrupt status conditions values. + if ((ALT_QSPI_INT_STATUS_ALL & mask) == 0) + { + return ALT_E_BAD_ARG; + } + + // Write 1's to clear the desired interrupt status condition(s). + alt_write_word(ALT_QSPI_IRQSTAT_ADDR, mask); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_int_disable(const uint32_t mask) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Check that the [mask] contains valid interrupt status conditions values. + if ((ALT_QSPI_INT_STATUS_ALL & mask) == 0) + { + return ALT_E_BAD_ARG; + } + + // Write 0's to disable the desired interrupt status condition(s). + alt_clrbits_word(ALT_QSPI_IRQMSK_ADDR, mask); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_int_enable(const uint32_t mask) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Check that the [mask] contains valid interrupt status conditions values. + if ((ALT_QSPI_INT_STATUS_ALL & mask) == 0) + { + return ALT_E_BAD_ARG; + } + + // Write 1's to enable the desired interrupt status condition(s). + alt_setbits_word(ALT_QSPI_IRQMSK_ADDR, mask); + + return ALT_E_SUCCESS; +} + +///// + +bool alt_qspi_is_idle(void) +{ + // If the idle field of the QSPI configuration register is 1 then the serial + // interface and QSPI pipeline is idle. + return ALT_QSPI_CFG_IDLE_GET(alt_read_word(ALT_QSPI_CFG_ADDR)) == 1; +} + +///// + +static ALT_STATUS_CODE alt_qspi_indirect_write_start_bank(uint32_t dst, size_t length); + +static ALT_STATUS_CODE alt_qspi_indirect_page_bound_write_helper(uint32_t dst, const char * src, size_t length) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_write_start_bank(dst, length); + } + + if (status == ALT_E_SUCCESS) + { + uint32_t write_count = 0; + uint32_t write_capacity = ALT_QSPI_SRAM_FIFO_ENTRY_COUNT - alt_qspi_sram_partition_get(); + + while (write_count < length) + { + uint32_t space = write_capacity - alt_qspi_indirect_write_fill_level(); + space = MIN(space, (length - write_count)/ sizeof(uint32_t)); + + const uint32_t * data = (const uint32_t *)(src + write_count); + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_QSPIDATA_ADDR, *data++); + } + + write_count += space * sizeof(uint32_t); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_write_finish(); + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_indirect_subsector_aligned_write_helper(const char * data, uint32_t subsec_addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + for (int i = 0; i < ALT_QSPI_SUBSECTOR_SIZE / ALT_QSPI_PAGE_SIZE; i++) + { + int offset = i * ALT_QSPI_PAGE_SIZE; + + status = alt_qspi_indirect_page_bound_write_helper(subsec_addr + offset, data + offset, ALT_QSPI_PAGE_SIZE); + if (status != ALT_E_SUCCESS) + { + break; + } + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_indirect_read_start_bank(uint32_t src, size_t size); + +// +// This helper function reads a segment of data, which is limited to 1 bank +// (24 bits of addressing). +// +static ALT_STATUS_CODE alt_qspi_read_bank(char * dst, uint32_t src, size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_read_start_bank(src, size); + } + + if (status == ALT_E_SUCCESS) + { + uint32_t read_count = 0; + + while (!alt_qspi_indirect_read_is_complete()) + { + uint32_t level = alt_qspi_indirect_read_fill_level(); +// level = MIN(level, (size - read_count) / sizeof(uint32_t)); + + uint32_t * data = (uint32_t *)(dst + read_count); + for (uint32_t i = 0; i < level; ++i) + { + *data++ = alt_read_word(ALT_QSPIDATA_ADDR); + } + + read_count += level * sizeof(uint32_t); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_read_finish(); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_read(void * dst, uint32_t src, size_t size) +{ + if (src >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (src + size - 1 >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + if ((uintptr_t)dst & 0x3) + { + return ALT_E_ERROR; + } + + if (src & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // + // bank_count : The number of bank(s) affected, including partial banks. + // bank_addr : The aligned address of the first affected bank, including partial bank(s). + // bank_ofst : The offset of the bank to read. Only used when reading the first bank. + // + uint32_t bank_count = ((src + size - 1) >> 24) - (src >> 24) + 1; + uint32_t bank_addr = src & ALT_QSPI_BANK_ADDR_MSK; + uint32_t bank_ofst = src & (ALT_QSPI_BANK_SIZE - 1); + + char * data = (char *)dst; + + uint32_t copy_length = MIN(size, ALT_QSPI_BANK_SIZE - bank_ofst); + + dprintf("DEBUG[QSPI]: read(): bulk: mem_addr = %p; flash_addr = 0x%" PRIx32 ".\n", data, src); + dprintf("DEBUG[QSPI]: read(): bulk: bank_count = 0x%" PRIx32 ", bank_ofst = 0x%" PRIx32 ".\n", bank_count, bank_ofst); + + for (uint32_t i = 0; i < bank_count; ++i) + { + dprintf("DEBUG[QSPI]: read(): bank 0x%" PRIx32 "; copy_length = 0x%" PRIx32 ".\n", bank_addr >> 24, copy_length); + + status = alt_qspi_device_bank_select(bank_addr >> 24); + if (status != ALT_E_SUCCESS) + { + break; + } + + status = alt_qspi_read_bank(dst, bank_ofst, copy_length); + if (status != ALT_E_SUCCESS) + { + break; + } + + bank_addr += ALT_QSPI_BANK_SIZE; + data += copy_length; + size -= copy_length; + + copy_length = MIN(size, ALT_QSPI_BANK_SIZE); + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_write_bank(uint32_t dst, const char * src, size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + ///// + + uint32_t page_ofst = dst & (ALT_QSPI_PAGE_SIZE - 1); + uint32_t write_size = MIN(size, ALT_QSPI_PAGE_SIZE - page_ofst); + + while (size) + { + dprintf("DEBUG[QSPI]: write(): flash dst = 0x%" PRIx32 ", mem src = %p, write size = 0x%" PRIx32 ", size left = 0x%x.\n", dst, src, write_size, size); + + status = alt_qspi_indirect_page_bound_write_helper(dst, src, write_size); + if (status != ALT_E_SUCCESS) + { + break; + } + + dst += write_size; + src += write_size; + size -= write_size; + + write_size = MIN(size, ALT_QSPI_PAGE_SIZE); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_write(uint32_t dst, const void * src, size_t size) +{ + if (dst >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (dst + size - 1 >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + if ((uintptr_t)src & 0x3) + { + return ALT_E_ERROR; + } + + if (dst & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t bank_count = ((dst + size - 1) >> 24) - (dst >> 24) + 1; + uint32_t bank_addr = dst & ALT_QSPI_BANK_ADDR_MSK; + uint32_t bank_ofst = dst & (ALT_QSPI_BANK_SIZE - 1); + + const char * data = src; + + uint32_t copy_length = MIN(size, ALT_QSPI_BANK_SIZE - bank_ofst); + + dprintf("DEBUG[QSPI]: write(): bulk: flash_addr = 0x%" PRIx32 "; mem_addr = %p.\n", dst, data); + dprintf("DEBUG[QSPI]: write(): bulk: bank_count = 0x%" PRIx32 ", bank_ofst = 0x%" PRIx32 ".\n", bank_count, bank_ofst); + + for (uint32_t i = 0; i < bank_count; ++i) + { + dprintf("DEBUG[QSPI]: write(): bank 0x%" PRIx32 "; copy_length = 0x%" PRIx32 ".\n", bank_addr >> 24, copy_length); + + status = alt_qspi_device_bank_select(bank_addr >> 24); + if (status != ALT_E_SUCCESS) + { + break; + } + + status = alt_qspi_write_bank(bank_ofst, data, copy_length); + if (status != ALT_E_SUCCESS) + { + break; + } + + bank_addr += ALT_QSPI_BANK_SIZE; + data += copy_length; + size -= copy_length; + + copy_length = MIN(size, ALT_QSPI_BANK_SIZE); + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_erase_subsector_bank(uint32_t addr); + +static ALT_STATUS_CODE alt_qspi_replace_bank(uint32_t dst, const char * src, size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // + // subsec_count : The total number of affected subsector(s), + // including partial subsector(s). + // subsec_addr : The aligned address of the next affected subsector, + // including partial subsector(s). + // subsec_partial_head : The number of subsector unaligned data to be + // written out at the start of the flash write + // request. This data ends at the end of the subsector + // or earlier depending on the number of data to be + // written. + // subsec_partial_tail : The number of subsector unaligned data to be + // written out at the end of the flash write request. + // This data starts at the start of the subsector. If + // only a single subsector is written (partial or + // full), this value will be zero. + // + + uint32_t subsec_count = ((dst + size - 1) >> 12) - (dst >> 12) + 1; + uint32_t subsec_addr = dst & ALT_QSPI_SUBSECTOR_ADDR_MSK; + + uint32_t subsec_partial_head = MIN(ALT_QSPI_SUBSECTOR_SIZE - (dst & (ALT_QSPI_SUBSECTOR_SIZE - 1)), size) & (ALT_QSPI_SUBSECTOR_SIZE - 1); + uint32_t subsec_partial_tail = (size - subsec_partial_head) & (ALT_QSPI_SUBSECTOR_SIZE - 1); + + dprintf("DEBUG[QSPI]: replace(): report: dst = 0x%" PRIx32 "; size = 0x%x.\n", + dst, size); + dprintf("DEBUG[QSPI]: replace(): report: subsec_count = 0x%" PRIx32 "; subsec_addr = 0x%" PRIx32 ".\n", + subsec_count, subsec_addr); + dprintf("DEBUG[QSPI]: replace(): report: partial_head = 0x%" PRIx32 "; partial_tail = 0x%" PRIx32 ".\n", + subsec_partial_head, subsec_partial_tail); + + // Write the first subsector, partial case. + + if (subsec_partial_head) + { + // The write request is not aligned to a subsector so we must do the + // Read-Modify-Write cycle to preserve the existing data at the head of + // the subsector not affected by the write. + + char subsec_buf[ALT_QSPI_SUBSECTOR_SIZE]; + + uint32_t subsec_ofst = dst & ~ALT_QSPI_SUBSECTOR_ADDR_MSK; + + // - Read the subsector into buffer + // - Erase that subsector + // - Copy in the user data into buffer + // - Write out buffer to subsector + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_read_bank(subsec_buf, subsec_addr, subsec_ofst); + } + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(subsec_addr); + } + if (status == ALT_E_SUCCESS) + { + memcpy(subsec_buf + subsec_ofst, src, subsec_partial_head); + status = alt_qspi_indirect_subsector_aligned_write_helper(subsec_buf, subsec_addr); + } + + // Do some bookkeeping on the user buffer information + src += subsec_partial_head; + size -= subsec_partial_head; + + // Do some bookkeeping on the subsector tracking + subsec_count--; + subsec_addr += ALT_QSPI_SUBSECTOR_SIZE; + + dprintf("DEBUG[QSPI]: replace(): partial head: subsec_ofst = 0x%" PRIx32 "; size left = 0x%x; status = %" PRIi32 ".\n", + subsec_ofst, size, status); + } + + // If there is a partial tail, then take 1 off the subsec_count. This way + // the following loop will write out all the complete subsectors. The tail + // will be written out afterwards. + + if (subsec_partial_tail) + { + subsec_count--; + } + + // Write the aligned subsectors following any partial subsectors. + + for (uint32_t i = 0; i < subsec_count; ++i) + { + // - Erase subsector + // - Write out buffer to subsector + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(subsec_addr); + } + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_subsector_aligned_write_helper(src, subsec_addr); + } + + src += ALT_QSPI_SUBSECTOR_SIZE; + size -= ALT_QSPI_SUBSECTOR_SIZE; + + // Don't modify subsec_count as it's being used by the loop. + subsec_addr += ALT_QSPI_SUBSECTOR_SIZE; + + dprintf("DEBUG[QSPI]: replace(): subsec aligned: size left = 0x%x, status = %" PRIi32 ".\n", + size, status); + } + + // Write the last subsector, partial case. + + if (subsec_partial_tail) + { + // The write request is not aligned to a subsector so we must do the + // Read-Modify-Write cycle to preserve the existing data at the end of + // the subsector not affected by the write. + + char subsec_buf[ALT_QSPI_SUBSECTOR_SIZE]; + + // - Read the subsector into buffer + // - Erase that subsector + // - Copy in the user data into buffer + // - Write out buffer to subsector + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_read_bank(subsec_buf + subsec_partial_tail, + subsec_addr + subsec_partial_tail, + ALT_QSPI_SUBSECTOR_SIZE - subsec_partial_tail); + } + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(subsec_addr); + } + if (status == ALT_E_SUCCESS) + { + memcpy(subsec_buf, src, subsec_partial_tail); + status = alt_qspi_indirect_subsector_aligned_write_helper(subsec_buf, subsec_addr); + } + + src += subsec_partial_tail; + size -= subsec_partial_tail; + + dprintf("DEBUG[QSPI]: replace(): partial tail: size left = 0x%x, status = %" PRIi32 ".\n", + size, status); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size) +{ + if (dst >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (dst + size - 1 >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + if ((uintptr_t)src & 0x3) + { + return ALT_E_ERROR; + } + + if (dst & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t bank_count = ((dst + size - 1) >> 24) - (dst >> 24) + 1; + uint32_t bank_addr = dst & ALT_QSPI_BANK_ADDR_MSK; + uint32_t bank_ofst = dst & (ALT_QSPI_BANK_SIZE - 1); + + const char * data = (const char *)src; + + uint32_t copy_length = MIN(size, ALT_QSPI_BANK_SIZE - bank_ofst); + + dprintf("DEBUG[QSPI]: replace(): bulk: flash_addr = 0x%" PRIx32 "; mem_addr = %p.\n", dst, data); + dprintf("DEBUG[QSPI]: replace(): bulk: bank_count = 0x%" PRIx32 ", bank_ofst = 0x%" PRIx32 ".\n", bank_count, bank_ofst); + + for (uint32_t i = 0; i < bank_count; ++i) + { + dprintf("DEBUG[QSPI]: replace(): bank 0x%" PRIx32 "; copy_length = 0x%" PRIx32 ".\n", bank_addr >> 24, copy_length); + + status = alt_qspi_device_bank_select(bank_addr >> 24); + if (status != ALT_E_SUCCESS) + { + break; + } + + status = alt_qspi_replace_bank(bank_ofst, data, copy_length); + if (status != ALT_E_SUCCESS) + { + break; + } + + bank_addr += ALT_QSPI_BANK_SIZE; + data += copy_length; + size -= copy_length; + + copy_length = MIN(size, ALT_QSPI_BANK_SIZE); + } + + return status; +} + +///// + +ALT_QSPI_BAUD_DIV_t alt_qspi_baud_rate_div_get(void) +{ + uint32_t baud_rate_div = ALT_QSPI_CFG_BAUDDIV_GET(alt_read_word(ALT_QSPI_CFG_ADDR)); + return (ALT_QSPI_BAUD_DIV_t) baud_rate_div; +} + +ALT_STATUS_CODE alt_qspi_baud_rate_div_set(const ALT_QSPI_BAUD_DIV_t baud_rate_div) +{ + if (0xf < (uint32_t)baud_rate_div) + { + // Invalid baud rate divisor value. + return ALT_E_BAD_ARG; + } + + // Set the Master Mode Baud Rate Divisor Field of the QSPI Configuration Register. + alt_replbits_word(ALT_QSPI_CFG_ADDR, + ALT_QSPI_CFG_BAUDDIV_SET_MSK, + ALT_QSPI_CFG_BAUDDIV_SET(baud_rate_div)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_chip_select_config_get(uint32_t* cs, + ALT_QSPI_CS_MODE_t* cs_mode) +{ + uint32_t cfg = alt_read_word(ALT_QSPI_CFG_ADDR); + + *cs = ALT_QSPI_CFG_PERCSLINES_GET(cfg); + *cs_mode = (ALT_QSPI_CS_MODE_t) ALT_QSPI_CFG_PERSELDEC_GET(cfg); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_chip_select_config_set(const uint32_t cs, + const ALT_QSPI_CS_MODE_t cs_mode) +{ + // chip select cs: + // four bit value, bit 0 = cs0, bit 1 = cs1, bit 2 = cs2, bit 3 = cs3 + // since cs is low true, the value of each bit should be zero if enable the cs. + // + // also allows multiple cs line enabled together. + + if (cs > ((1 << ALT_QSPI_CFG_PERCSLINES_WIDTH) - 1)) + { + // [cs] not within possible 4 bit chip select line value range. + return ALT_E_ARG_RANGE; + } + + if ((cs_mode != ALT_QSPI_CS_MODE_SINGLE_SELECT) && (cs_mode != ALT_QSPI_CS_MODE_DECODE)) + { + return ALT_E_INV_OPTION; + } + + // Update the Peripheral Chip Select Lines and Peripheral Select Decode + // Fields of the QSPI Configuration Register value with the chip select + // options. + uint32_t cfg = alt_read_word(ALT_QSPI_CFG_ADDR); + cfg &= ALT_QSPI_CFG_PERCSLINES_CLR_MSK & ALT_QSPI_CFG_PERSELDEC_CLR_MSK; + cfg |= ALT_QSPI_CFG_PERCSLINES_SET(cs) | ALT_QSPI_CFG_PERSELDEC_SET(cs_mode); + alt_write_word(ALT_QSPI_CFG_ADDR, cfg); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_mode_bit_disable(void) +{ + // Clear the Mode Bit Enable Field of the Device Read Instruction Register + // to disable mode bits from being sent after the address bytes. + alt_clrbits_word(ALT_QSPI_DEVRD_ADDR, ALT_QSPI_DEVRD_ENMODBITS_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_mode_bit_enable(void) +{ + // Set the Mode Bit Enable Field of the Device Read Instruction Register + // to enable mode bits to be sent after the address bytes. + alt_setbits_word(ALT_QSPI_DEVRD_ADDR, ALT_QSPI_DEVRD_ENMODBITS_SET_MSK); + + return ALT_E_SUCCESS; +} + +uint32_t alt_qspi_mode_bit_config_get(void) +{ + // Return the 8 bit value from the Mode Field of the Mode Bit Configuration + // Register. + return ALT_QSPI_MODBIT_MOD_GET(alt_read_word(ALT_QSPI_MODBIT_ADDR)); +} + +ALT_STATUS_CODE alt_qspi_mode_bit_config_set(const uint32_t mode_bits) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + if (mode_bits > ((1 << ALT_QSPI_MODBIT_MOD_WIDTH) - 1)) + { + // 'mode_bits' not within possible 8 bit mode value range. + return ALT_E_ARG_RANGE; + } + + // Set the 8 bit value in the Mode Field of the Mode Bit Configuration + // Register. + alt_replbits_word(ALT_QSPI_MODBIT_ADDR, + ALT_QSPI_MODBIT_MOD_SET_MSK, + ALT_QSPI_MODBIT_MOD_SET(mode_bits)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_size_config_get(ALT_QSPI_DEV_SIZE_CONFIG_t * cfg) +{ + // Although not required, it is recommended that the write protect feature + // be enabled prior to enabling the QSPI controller. This will block any AHB + // writes from taking effect. This also means the write protection registers + // (Lower Write Protection, Upper Write Protection, and Write Protection) + // should be setup and the number of bytes per device block in the device + // size configuration register should be setup prior to enabling the QSPI + // controller. + + // Read Device Size Register and get the Number of Bytes per Block, Number + // of Bytes per Device, and Number of Address Bytes Fields. + + uint32_t devsz = alt_read_word(ALT_QSPI_DEVSZ_ADDR); + + cfg->block_size = ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(devsz); + cfg->page_size = ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(devsz); + cfg->addr_size = ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(devsz); + + // Read Lower Write Protection, Upper Write Protection, and Write Protection + // Registers. + + cfg->lower_wrprot_block = ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(alt_read_word(ALT_QSPI_LOWWRPROT_ADDR)); + cfg->upper_wrprot_block = ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(alt_read_word(ALT_QSPI_UPPWRPROT_ADDR)); + cfg->wrprot_enable = ALT_QSPI_WRPROT_EN_GET(alt_read_word(ALT_QSPI_WRPROT_ADDR)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_size_config_set(const ALT_QSPI_DEV_SIZE_CONFIG_t * cfg) +{ + if (cfg->block_size > ((1 << ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + if (cfg->page_size > ((1 << ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + if (cfg->addr_size > ((1 << ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + if (cfg->lower_wrprot_block > cfg->upper_wrprot_block) + { + // Null write protection regions are not allowed. + return ALT_E_ARG_RANGE; + } + + ///// + + uint32_t value = ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(cfg->block_size) | + ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(cfg->page_size) | + ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(cfg->addr_size); + + alt_write_word(ALT_QSPI_DEVSZ_ADDR, value); + + if (cfg->wrprot_enable) + { + alt_write_word(ALT_QSPI_LOWWRPROT_ADDR, cfg->lower_wrprot_block); + alt_write_word(ALT_QSPI_UPPWRPROT_ADDR, cfg->upper_wrprot_block); + } + + // Read Upper Write Protection Register - uppwrprot. + // Set the Write Protection Enable Bit Field of the Write Protection + // Register accordingly. + if (cfg->wrprot_enable) + { + alt_setbits_word(ALT_QSPI_WRPROT_ADDR, ALT_QSPI_WRPROT_EN_SET(1)); + } + else + { + alt_clrbits_word(ALT_QSPI_WRPROT_ADDR, ALT_QSPI_WRPROT_EN_SET(1)); + } + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_read_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + // Read the Device Read Instruction Register - devrd. + uint32_t devrd = alt_read_word(ALT_QSPI_DEVRD_ADDR); + + cfg->op_code = ALT_QSPI_DEVRD_RDOPCODE_GET(devrd); + cfg->inst_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_INSTWIDTH_GET(devrd); + cfg->addr_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_ADDRWIDTH_GET(devrd); + cfg->data_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_DATAWIDTH_GET(devrd); + cfg->dummy_cycles = ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(devrd); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_read_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Validate input + + if (cfg->op_code > ((1 << ALT_QSPI_DEVRD_RDOPCODE_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + switch (cfg->inst_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->addr_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->data_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + if (cfg->dummy_cycles > ((1 << ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + ///// + + // Read the Device Read Instruction Register - devrd. + uint32_t devrd = alt_read_word(ALT_QSPI_DEVRD_ADDR); + + devrd &= ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK & + ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK & + ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK & + ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK & + ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK; + + devrd |= ALT_QSPI_DEVRD_RDOPCODE_SET(cfg->op_code) | + ALT_QSPI_DEVRD_INSTWIDTH_SET(cfg->inst_type) | + ALT_QSPI_DEVRD_ADDRWIDTH_SET(cfg->addr_xfer_type) | + ALT_QSPI_DEVRD_DATAWIDTH_SET(cfg->data_xfer_type) | + ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(cfg->dummy_cycles); + + alt_write_word(ALT_QSPI_DEVRD_ADDR, devrd); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_write_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + // Device Write Instruction Register - devwr. + uint32_t devwr = alt_read_word(ALT_QSPI_DEVWR_ADDR); + + cfg->op_code = ALT_QSPI_DEVWR_WROPCODE_GET(devwr); + // The Instruction Type field in the Device READ Instruction Register only appears + // once and applies to both READ and WRITE opertions. it is not included in the + // Device WRITE Instruction Register. + cfg->inst_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_INSTWIDTH_GET(alt_read_word(ALT_QSPI_DEVRD_ADDR)); + cfg->addr_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVWR_ADDRWIDTH_GET(devwr); + cfg->data_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVWR_DATAWIDTH_GET(devwr); + cfg->dummy_cycles = ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(devwr); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_write_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Validate input + + if (cfg->op_code > ((1 << ALT_QSPI_DEVWR_WROPCODE_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + switch (cfg->inst_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->addr_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->data_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + if (cfg->dummy_cycles > ((1 << ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + ///// + + // Read the Device Write Instruction Register - devwr. + uint32_t devwr = alt_read_word(ALT_QSPI_DEVWR_ADDR); + + devwr &= ALT_QSPI_DEVWR_WROPCODE_CLR_MSK & + ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK & + ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK & + ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK; + + devwr |= ALT_QSPI_DEVWR_WROPCODE_SET(cfg->op_code) | + ALT_QSPI_DEVWR_ADDRWIDTH_SET(cfg->addr_xfer_type) | + ALT_QSPI_DEVWR_DATAWIDTH_SET(cfg->data_xfer_type) | + ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(cfg->dummy_cycles); + + alt_write_word(ALT_QSPI_DEVWR_ADDR, devwr); + + // The Instruction Type field in the Device READ Instruction Register only appears + // once and applies to both READ and WRITE operations - it is not included in the + // Device WRITE Instruction Register. Therefore, modify the Instruction Type + // Field in the Device Read Register. + alt_replbits_word(ALT_QSPI_DEVRD_ADDR, + ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK, + ALT_QSPI_DEVRD_INSTWIDTH_SET((uint32_t) cfg->inst_type)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_timing_config_get(ALT_QSPI_TIMING_CONFIG_t * cfg) +{ + // QSPI Configuration Register - cfg + uint32_t cfgreg = alt_read_word(ALT_QSPI_CFG_ADDR); + cfg->clk_phase = (ALT_QSPI_CLK_PHASE_t) ALT_QSPI_CFG_SELCLKPHASE_GET(cfgreg); + cfg->clk_pol = (ALT_QSPI_CLK_POLARITY_t) ALT_QSPI_CFG_SELCLKPOL_GET(cfgreg); + + // QSPI Device Delay Register + uint32_t delayreg = alt_read_word(ALT_QSPI_DELAY_ADDR); + cfg->cs_sot = ALT_QSPI_DELAY_INIT_GET(delayreg); + cfg->cs_eot = ALT_QSPI_DELAY_AFTER_GET(delayreg); + cfg->cs_dads = ALT_QSPI_DELAY_BTWN_GET(delayreg); + cfg->cs_da = ALT_QSPI_DELAY_NSS_GET(delayreg); + + // Read Data Capture Register + cfg->rd_datacap = ALT_QSPI_RDDATACAP_DELAY_GET(alt_read_word(ALT_QSPI_RDDATACAP_ADDR)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_timing_config_set(const ALT_QSPI_TIMING_CONFIG_t * cfg) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Validate parameter(s) + + switch (cfg->clk_phase) + { + case ALT_QSPI_CLK_PHASE_ACTIVE: + case ALT_QSPI_CLK_PHASE_INACTIVE: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->clk_pol) + { + case ALT_QSPI_CLK_POLARITY_LOW: + case ALT_QSPI_CLK_POLARITY_HIGH: + break; + default: + return ALT_E_BAD_ARG; + } + + if (cfg->cs_da > ((1 << ALT_QSPI_DELAY_NSS_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + if (cfg->cs_dads > ((1 << ALT_QSPI_DELAY_BTWN_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + if (cfg->cs_eot > ((1 << ALT_QSPI_DELAY_AFTER_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + if (cfg->cs_sot > ((1 << ALT_QSPI_DELAY_INIT_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + if (cfg->rd_datacap > ((1 << ALT_QSPI_RDDATACAP_DELAY_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + ///// + + // QSPI Configuration Register - cfg + uint32_t cfgreg = alt_read_word(ALT_QSPI_CFG_ADDR); + cfgreg &= ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK & + ALT_QSPI_CFG_SELCLKPOL_CLR_MSK; + cfgreg |= ALT_QSPI_CFG_SELCLKPHASE_SET(cfg->clk_phase) | + ALT_QSPI_CFG_SELCLKPOL_SET(cfg->clk_pol); + alt_write_word(ALT_QSPI_CFG_ADDR, cfgreg); + + // QSPI Device Delay Register + uint32_t delayreg = ALT_QSPI_DELAY_INIT_SET(cfg->cs_sot) | + ALT_QSPI_DELAY_AFTER_SET(cfg->cs_eot) | + ALT_QSPI_DELAY_BTWN_SET(cfg->cs_dads) | + ALT_QSPI_DELAY_NSS_SET(cfg->cs_da); + alt_write_word(ALT_QSPI_DELAY_ADDR, delayreg); + + // Read Data Capture Register + + alt_write_word(ALT_QSPI_RDDATACAP_ADDR, + ALT_QSPI_RDDATACAP_BYP_SET(1) | + ALT_QSPI_RDDATACAP_DELAY_SET(cfg->rd_datacap)); + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_qspi_direct_disable(void) +{ + // Clear (set to 0) the Enable Direct Access Controller Field of the QSPI + // Configuration Register to disable the Direct Access Controller. + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDIRACC_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_direct_enable(void) +{ + // Set (set to 1) the Enable Direct Access Controller Field of the QSPI + // Configuration Register to enable the Direct Access Controller. + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDIRACC_SET_MSK); + + return ALT_E_SUCCESS; +} + +uint32_t alt_qspi_ahb_remap_address_get(void) +{ + // Read and return the value of the Remap Address Register. + return ALT_QSPI_REMAPADDR_VALUE_GET(alt_read_word(ALT_QSPI_REMAPADDR_ADDR)); +} + +ALT_STATUS_CODE alt_qspi_ahb_remap_address_set(const uint32_t ahb_remap_addr) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Read and return the value of the Remap Address Register. + alt_setbits_word(ALT_QSPI_REMAPADDR_ADDR, ALT_QSPI_REMAPADDR_VALUE_SET(ahb_remap_addr)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_ahb_address_remap_disable(void) +{ + // Clear (set to 0) the Enable AHB Address Remapping Field of the QSPI + // Configuration Register to disable AHB address remapping. + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENAHBREMAP_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_ahb_address_remap_enable(void) +{ + // Set (set to 1) the Enable AHB Address Remapping Field of the QSPI + // Configuration Register to enable AHB address remapping. + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENAHBREMAP_SET_MSK); + + return ALT_E_SUCCESS; +} + +///// + +static ALT_STATUS_CODE alt_qspi_indirect_read_start_bank(uint32_t flash_addr, + size_t num_bytes) +{ + alt_write_word(ALT_QSPI_INDRDSTADDR_ADDR, flash_addr); + alt_write_word(ALT_QSPI_INDRDCNT_ADDR, num_bytes); + alt_write_word(ALT_QSPI_INDRD_ADDR, ALT_QSPI_INDRD_START_SET_MSK | + ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_indirect_read_start(const uint32_t flash_addr, + const size_t num_bytes) +{ + // flash_addr and num_bytes restriction is to prevent possible unaligned + // exceptions. + + if (flash_addr & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes == 0) + { + // Do not report this as a success. If a indirect read was not + // previously completed, it may be cleared already, at which point + // alt_qspi_indirect_read_is_complete() will never report true. + return ALT_E_ERROR; + } + + if (flash_addr > qspi_device_size) + { + return ALT_E_ERROR; + } + + if (flash_addr + num_bytes > qspi_device_size) + { + return ALT_E_ERROR; + } + + // Verify request does not cross bank boundary. + // This limitation is due to the 3-byte addressing limitation. + if ((flash_addr & ALT_QSPI_BANK_ADDR_MSK) != ((flash_addr + num_bytes - 1) & ALT_QSPI_BANK_ADDR_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status; + status = alt_qspi_device_bank_select(flash_addr >> 24); + if (status != ALT_E_SUCCESS) + { + return status; + } + + ///// + + return alt_qspi_indirect_read_start_bank(flash_addr, + num_bytes); + +} + +ALT_STATUS_CODE alt_qspi_indirect_read_finish(void) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_indirect_read_cancel(void) +{ + // An indirect operation may be cancelled at any time by setting Indirect + // Transfer Control Register bit [1]. + alt_write_word(ALT_QSPI_INDRD_ADDR, ALT_QSPI_INDRD_CANCEL_SET_MSK); + + return ALT_E_SUCCESS; +} + +uint32_t alt_qspi_indirect_read_fill_level(void) +{ + // Return the SRAM Fill Level (Indirect Read Partition) Field of the SRAM + // Fill Register to get the SRAM Fill Level for the Indirect Read Partition + // in units of SRAM Words (4 bytes). + return ALT_QSPI_SRAMFILL_INDRDPART_GET(alt_read_word(ALT_QSPI_SRAMFILL_ADDR)); +} + +uint32_t alt_qspi_indirect_read_watermark_get(void) +{ + // Return the Watermark value in the Indirect Read Transfer Watermark Register. + return alt_read_word(ALT_QSPI_INDRDWATER_ADDR); +} + +ALT_STATUS_CODE alt_qspi_indirect_read_watermark_set(const uint32_t watermark) +{ + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + // Set the Watermark value in the Indirect Read Transfer Watermark Register. + alt_write_word(ALT_QSPI_INDRDWATER_ADDR, watermark); + + return ALT_E_SUCCESS; +} + +bool alt_qspi_indirect_read_is_complete(void) +{ + // The value of the Indirect Completion Status Field of the Indirect Read + // Transfer Control Register is set by hardware when an indirect read + // operation has completed. + return (alt_read_word(ALT_QSPI_INDRD_ADDR) & ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK) != 0; +} + +static ALT_STATUS_CODE alt_qspi_indirect_write_start_bank(uint32_t flash_addr, + size_t num_bytes) +{ + alt_write_word(ALT_QSPI_INDWRSTADDR_ADDR, flash_addr); + alt_write_word(ALT_QSPI_INDWRCNT_ADDR, num_bytes); + alt_write_word(ALT_QSPI_INDWR_ADDR, ALT_QSPI_INDWR_START_SET_MSK | + ALT_QSPI_INDWR_INDDONE_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_indirect_write_start(const uint32_t flash_addr, + const size_t num_bytes) +{ + // flash_addr and num_bytes restriction is to prevent possible unaligned + // exceptions. + + if (flash_addr & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes == 0) + { + // Do not report this as a success. If a indirect write was not + // previously completed, it may be cleared already, at which point + // alt_qspi_indirect_write_is_complete() will never report true. + return ALT_E_ERROR; + } + + if (num_bytes > 256) + { + // The Micron part can only write up to 256 bytes at a time. + return ALT_E_ERROR; + } + + if (flash_addr > qspi_device_size) + { + return ALT_E_ERROR; + } + + if (flash_addr + num_bytes > qspi_device_size) + { + return ALT_E_ERROR; + } + +/* + // Verify request does not cross bank boundary. + // This limitation is due to the 3-byte addressing limitation. + if ((flash_addr & ALT_QSPI_BANK_ADDR_MSK) != ((flash_addr + num_bytes - 1) & ALT_QSPI_BANK_ADDR_MSK)) + { + return ALT_E_ERROR; + } +*/ + // Verify request does not cross page boundary. + // This limitation is in place for the Micron part used. + if ((flash_addr & ALT_QSPI_PAGE_ADDR_MSK) != ((flash_addr + num_bytes - 1) & ALT_QSPI_PAGE_ADDR_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + status = alt_qspi_device_bank_select(flash_addr >> 24); + if (status != ALT_E_SUCCESS) + { + return status; + } + + ///// + + return alt_qspi_indirect_write_start_bank(flash_addr, + num_bytes); +} + +ALT_STATUS_CODE alt_qspi_indirect_write_finish(void) +{ +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + return alt_qspi_N25Q_flag_wait_for_program(ALT_QSPI_TIMEOUT_INFINITE); +#else + return ALT_E_SUCCESS; +#endif +} + +ALT_STATUS_CODE alt_qspi_indirect_write_cancel(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_program(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + + if (status == ALT_E_SUCCESS) + { + // An indirect operation may be cancelled at any time by setting Indirect + // Transfer Control Register bit [1]. + alt_write_word(ALT_QSPI_INDWR_ADDR, ALT_QSPI_INDWR_CANCEL_SET_MSK); + } + + return status; +} + +uint32_t alt_qspi_indirect_write_fill_level(void) +{ + // Return the SRAM Fill Level (Indirect Write Partition) Field of the SRAM + // Fill Register to get the SRAM Fill Level for the Indirect Write Partition + // in units of SRAM Words (4 bytes). + return ALT_QSPI_SRAMFILL_INDWRPART_GET(alt_read_word(ALT_QSPI_SRAMFILL_ADDR)); +} + +uint32_t alt_qspi_indirect_write_watermark_get(void) +{ + // Return the Watermark value in the Indirect Write Transfer Watermark Register. + return alt_read_word(ALT_QSPI_INDWRWATER_ADDR); +} + +ALT_STATUS_CODE alt_qspi_indirect_write_watermark_set(const uint32_t watermark) +{ + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + // Set the Watermark value in the Indirect Write Transfer Watermark Register. + alt_write_word(ALT_QSPI_INDWRWATER_ADDR, watermark); + + return ALT_E_SUCCESS; +} + +bool alt_qspi_indirect_write_is_complete(void) +{ + // The value of the Indirect Completion Status Field of the Indirect Write + // Transfer Control Register is set by hardware when an indirect write + // operation has completed. + return (alt_read_word(ALT_QSPI_INDWR_ADDR) & ALT_QSPI_INDWR_INDDONE_SET_MSK) != 0; +} + +///// + +uint32_t alt_qspi_sram_partition_get(void) +{ + // The number of locations allocated to indirect read is equal to the value + // of the SRAM partition register. See the documentation for this function + // regarding the + 1 in the IP documentation. This way the get() and set() + // will be symmetrical. + + return ALT_QSPI_SRAMPART_ADDR_GET(alt_read_word(ALT_QSPI_SRAMPART_ADDR)); +} + +ALT_STATUS_CODE alt_qspi_sram_partition_set(const uint32_t read_part_size) +{ + if (read_part_size > ((1 << ALT_QSPI_SRAMPART_ADDR_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + alt_replbits_word(ALT_QSPI_SRAMPART_ADDR, + ALT_QSPI_SRAMPART_ADDR_SET_MSK, + ALT_QSPI_SRAMPART_ADDR_SET(read_part_size)); + + return ALT_E_SUCCESS; +} + +///// + + +static ALT_STATUS_CODE alt_qspi_erase_subsector_bank(uint32_t addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE, 0, addr, 10000); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + + return status; +} + +ALT_STATUS_CODE alt_qspi_erase_subsector(const uint32_t addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(addr >> 24); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(addr); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_erase_sector(const uint32_t addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(addr >> 24); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_SEC_ERASE, 0, addr, ALT_QSPI_TIMEOUT_INFINITE); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + + return status; +} + +ALT_STATUS_CODE alt_qspi_erase_chip(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (qspi_device_size >= (2 * ALT_QSPI_N25Q_DIE_SIZE)) + { + // NOTE: This path is specifically for 512 Mib and 1 Gib Micron N25Q + // chips only. + + dprintf("DEBUG[QSPI]: erase[chip]: FYI, wait time is ~800s for 128 MiB.\n"); + + uint32_t die_count = qspi_device_size / ALT_QSPI_N25Q_DIE_SIZE; + + for (int i = 0; i < die_count; ++i) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + dprintf("DEBUG[QSPI]: Erase chip: die = %d, total = %" PRIu32 ".\n", i, die_count); + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(i * (ALT_QSPI_N25Q_DIE_SIZE / ALT_QSPI_BANK_SIZE)); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_DIE_ERASE, 0, + i * ALT_QSPI_N25Q_DIE_SIZE, + ALT_QSPI_TIMEOUT_INFINITE); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + } + } + else + { + // NOTE: Untested path. + + dprintf("DEBUG[QSPI]: Bulk erase.\n"); + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(0); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + // If BULK_ERASE is like other ERASE, it needs the address command. + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_BULK_ERASE, 0, + 0, + ALT_QSPI_TIMEOUT_INFINITE); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + } + + return status; +} + +///// + +ALT_STATUS_CODE alt_qspi_dma_disable(void) +{ + // Clear (set to 0) the Enable DMA Peripheral Interface Field of the QSPI + // Configuration Register to disable the DMA peripheral interface. + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_dma_enable(void) +{ + // Set (set to 1) the Enable DMA Peripheral Interface Field of the QSPI + // Configuration Register to enable the DMA peripheral interface. + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_dma_config_get(uint32_t * single_type_sz, + uint32_t * burst_type_sz) +{ + // Get the current value of the DMA Peripheral Register - dmaper + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + + // For both values, a programmed value of 0 represents a single byte. The + // actual number of bytes used is 2 ** (value in this register field). + *single_type_sz = 1 << ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(dmaper); + *burst_type_sz = 1 << ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(dmaper); + + return ALT_E_SUCCESS; +} + +// +// Returns true if [n] is a power of 2 value otherwise returns false. +// +static bool is_pow_2(uint32_t n) +{ + return ((n > 0) && ((n & (n - 1)) == 0)); +} + +// +// Return the log base 2 value of a number that is known to be a power of 2. +// +static uint32_t log2u(uint32_t value) +{ + uint32_t exp = 0; + while ((exp < 32) && (value != (1 << exp))) + { + ++exp; + } + return exp; +} + +ALT_STATUS_CODE alt_qspi_dma_config_set(const uint32_t single_type_sz, + const uint32_t burst_type_sz) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + if (single_type_sz < 4) + { + return ALT_E_ERROR; + } + + if (burst_type_sz < 4) + { + return ALT_E_ERROR; + } + + if (burst_type_sz < single_type_sz) + { + return ALT_E_ERROR; + } + + const uint32_t single_type_sz_max = 1 << ((1 << ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH) - 1); + const uint32_t burst_type_sz_max = 1 << ((1 << ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH) - 1); + + // Both parameter values must be a power of 2 between 1 and 32728. + if ( (single_type_sz > single_type_sz_max) || !is_pow_2(single_type_sz) + || (burst_type_sz > burst_type_sz_max) || !is_pow_2(burst_type_sz) + ) + { + return ALT_E_ARG_RANGE; + } + + // Get the current value of the DMA Peripheral Register - dmaper + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + dmaper &= ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK & + ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK; + dmaper |= ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(log2u(burst_type_sz)) | + ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(log2u(single_type_sz)); + alt_write_word(ALT_QSPI_DMAPER_ADDR, dmaper); + + return ALT_E_SUCCESS; +} + +///// + +// +// Private STIG and device commands +// + +static ALT_STATUS_CODE alt_qspi_stig_cmd_helper(uint32_t reg_value, uint32_t timeout) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + bool infinite = (timeout == ALT_QSPI_TIMEOUT_INFINITE); + + alt_write_word(ALT_QSPI_FLSHCMD_ADDR, reg_value); + alt_write_word(ALT_QSPI_FLSHCMD_ADDR, reg_value | ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE); + + do + { + reg_value = alt_read_word(ALT_QSPI_FLSHCMD_ADDR); + if (!(reg_value & ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK)) + { + break; + } + + } while (timeout-- || infinite); + + if (timeout == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + uint32_t reg = ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + return alt_qspi_stig_cmd_helper(reg, timeout); +} + +ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, + uint32_t dummy, + uint32_t num_bytes, + uint32_t * output, + uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + // STIG read can only return up to 8 bytes. + if ((num_bytes > 8) || (num_bytes == 0)) + { + return ALT_E_BAD_ARG; + } + + uint32_t reg_value = + ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_ENRDDATA_SET(ALT_QSPI_FLSHCMD_ENRDDATA_E_EN) | + ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(num_bytes - 1) | + ALT_QSPI_FLSHCMD_ENCMDADDR_SET(ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD) | + ALT_QSPI_FLSHCMD_ENMODBIT_SET(ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD) | + ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(0) | + ALT_QSPI_FLSHCMD_ENWRDATA_SET(ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION) | + ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(0) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + status = alt_qspi_stig_cmd_helper(reg_value, timeout); + if (status != ALT_E_SUCCESS) + { + return status; + } + + output[0] = alt_read_word(ALT_QSPI_FLSHCMDRDDATALO_ADDR); + + if (num_bytes > 4) + { + output[1] = alt_read_word(ALT_QSPI_FLSHCMDRDDATAUP_ADDR); + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, + uint32_t dummy, + uint32_t num_bytes, + const uint32_t * input, + uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + // STIG can only write up to 8 bytes. + if ((num_bytes > 8) || (num_bytes == 0)) + { + return ALT_E_BAD_ARG; + } + + uint32_t reg_value = + ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_ENRDDATA_SET(ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION) | + ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(0) | + ALT_QSPI_FLSHCMD_ENCMDADDR_SET(ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD) | + ALT_QSPI_FLSHCMD_ENMODBIT_SET(ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD) | + ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(0) | + ALT_QSPI_FLSHCMD_ENWRDATA_SET(ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES) | + ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(num_bytes - 1) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + alt_write_word(ALT_QSPI_FLSHCMDWRDATALO_ADDR, input[0]); + + if (num_bytes > 4) + { + alt_write_word(ALT_QSPI_FLSHCMDWRDATAUP_ADDR, input[1]); + } + + return alt_qspi_stig_cmd_helper(reg_value, timeout); +} + +ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, + uint32_t dummy, + uint32_t address, + uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + uint32_t reg = ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + reg |= ALT_QSPI_FLSHCMD_ENCMDADDR_SET(ALT_QSPI_FLSHCMD_ENCMDADDR_E_END); + reg |= ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3); + + alt_write_word(ALT_QSPI_FLSHCMDADDR_ADDR, address); + + return alt_qspi_stig_cmd_helper(reg, timeout); +} + +///// + +ALT_STATUS_CODE alt_qspi_device_wren(void) +{ + // Write enable through STIG (not required, auto send by controller during write) + return alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_WREN, 0, 10000); +} + +ALT_STATUS_CODE alt_qspi_device_wrdis(void) +{ + // Write disable through STIG (not required, auto send by controller during write) + return alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_WRDIS, 0, 10000); +} + +ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid) +{ + // Read flash device ID through STIG + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_RDID, 0, 4, rdid, 10000); +} + +ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param) +{ + // Read flash discovery parameters through STIG + + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_DISCVR_PARAM, 8, 8, param, 10000); +} + +ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + dprintf("DEBUG[QSPI]: bank_select(): switching to bank 0x%" PRIu32 ".\n", bank); + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_wr_cmd(ALT_QSPI_STIG_OPCODE_WR_EXT_REG, 0, 1, &bank, 10000); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wrdis(); + } + + return status; +} + +///// + +static bool alt_qspi_is_enabled(void) +{ + uint32_t cfg = alt_read_word(ALT_QSPI_CFG_ADDR); + + if (cfg & ALT_QSPI_CFG_EN_SET_MSK) + { + return true; + } + else + { + return false; + } +} + +ALT_STATUS_CODE alt_qspi_ecc_start(void * block, size_t size) +{ + if (size < (ALT_QSPI_PAGE_SIZE * 8)) + { + return ALT_E_ERROR; + } + + if (alt_qspi_is_enabled() == false) + { + return ALT_E_ERROR; + } + + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // 1. Configure SRAM Partition Register to 126 words for read, 2 words for write. + // 2. Enable ECC on QSPI RAM + // 3. Trigger an indirect read transfer that will fill up 126 words in FIFO by + // monitoring read FIFO fill level; Do not read out data through AHB. + // 4. Start AHB read and start indirect write operation to write back to the same + // device location, this will fill up and initilaize the write partition RAM. + // 5. To clear spurious interrupts, reset the QSPI controller. + + // Save the previous partition size + + uint32_t sram_orig = alt_qspi_sram_partition_get(); + dprintf("DEBUG[QSPI][ECC]: Save original SRAM as %" PRIu32 ".\n", sram_orig); + + // Step 1 + + uint32_t sram_fill = (1 << ALT_QSPI_SRAMPART_ADDR_WIDTH) - 2; + alt_qspi_sram_partition_set(sram_fill); + dprintf("DEBUG[QSPI][ECC]: Set new SRAM as %" PRIu32 ".\n", sram_fill); + + // Step 2 + + dprintf("DEBUG[QSPI][ECC]: Enable ECC in SysMgr.\n"); + alt_write_word(ALT_SYSMGR_ECC_QSPI_ADDR, ALT_SYSMGR_ECC_QSPI_EN_SET_MSK); + + // Step 3 + + // Issue a read ~ 2x larger than the read partition. We will read out 1 page, + // which will be used as the buffer to write back to QSPI. This way no data + // actually changes thus no erase will be needed. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Start indirect read PAGE * 8.\n"); + status = alt_qspi_indirect_read_start(0x0, ALT_QSPI_PAGE_SIZE * 8); + } + + // Read out 1 page for the write data + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Reading out 1 page ...\n"); + + uint32_t read_size = 0; + char * buffer = block; + while (read_size < ALT_QSPI_PAGE_SIZE) + { + uint32_t level = alt_qspi_indirect_read_fill_level(); + level = MIN(level, (ALT_QSPI_PAGE_SIZE - read_size) / sizeof(uint32_t)); + + uint32_t * data = (uint32_t *)(&buffer[read_size]); + for (uint32_t i = 0; i < level; ++i) + { + *data = alt_read_word(ALT_QSPIDATA_ADDR); + ++data; + } + + read_size += level * sizeof(uint32_t); + } + + if (read_size != ALT_QSPI_PAGE_SIZE) + { + status = ALT_E_ERROR; + } + } + + // Wait for read FIFO to report it is up to the specified fill level. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Waiting for read fill level ...\n"); + + uint32_t timeout = 10000; + + while (alt_qspi_indirect_read_fill_level() < sram_fill) + { + if (--timeout == 0) + { + dprintf("DEBUG[QSPI][ECC]: Waiting for read fill timeout !!!\n"); + status = ALT_E_TMO; + break; + } + } + } + + // Step 4 + + // Issue a write of 1 page of the same data from 0x0. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Start indirect write PAGE.\n"); + status = alt_qspi_indirect_write_start(0x0, ALT_QSPI_PAGE_SIZE); + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Writing in 1 page ...\n"); + + uint32_t write_size = 0; + char * buffer = block; + + while (write_size < ALT_QSPI_PAGE_SIZE) + { + uint32_t space = 2 - alt_qspi_indirect_write_fill_level(); + if (space == 0) + { + dprintf("DEBUG[QSPI][ECC]: Write FIFO filled at write_size = %" PRIu32 ".\n", write_size); + // Space = 0; which means all 2 positions in the write FIFO is filled, + // meaning it has been initialized with respect to ECC. + break; + } + + space = MIN(space, (ALT_QSPI_PAGE_SIZE - write_size) / sizeof(uint32_t)); + + uint32_t * data = (uint32_t *)(&buffer[write_size]); + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_QSPIDATA_ADDR, *data); + ++data; + } + + write_size += space * sizeof(uint32_t); + } + + if (write_size != ALT_QSPI_PAGE_SIZE) + { + dprintf("DEBUG[QSPI][ECC]: Cancel indirect write.\n"); + status = alt_qspi_indirect_write_cancel(); + } + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Finish indirect write.\n"); + status = alt_qspi_indirect_write_finish(); + } + + // Cancel the indirect read as it has initialized the read FIFO partition. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Cancel indirect read.\n"); + status = alt_qspi_indirect_read_cancel(); + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Finish indirect read.\n"); + status = alt_qspi_indirect_read_finish(); + } + + // Step 5 + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Clear any pending spurious QSPI ECC interrupts.\n"); + + alt_write_word(ALT_SYSMGR_ECC_QSPI_ADDR, + ALT_SYSMGR_ECC_QSPI_EN_SET_MSK + | ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK + | ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK); + } + + ///// + + // Restore original partition + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Restore original SRAM as %" PRIu32 ".\n", sram_orig); + status = alt_qspi_sram_partition_set(sram_orig); + } + + return status; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 4093831..768c01d 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -143,10 +143,18 @@ $(PROJECT_INCLUDE)/bsp/nocache-heap.h: include/nocache-heap.h $(PROJECT_INCLUDE) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/nocache-heap.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/nocache-heap.h +$(PROJECT_INCLUDE)/bsp/alt_16550_uart.h: hwlib/include/alt_16550_uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_16550_uart.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_16550_uart.h + $(PROJECT_INCLUDE)/bsp/alt_address_space.h: hwlib/include/alt_address_space.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_address_space.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_address_space.h +$(PROJECT_INCLUDE)/bsp/alt_cache.h: hwlib/include/alt_cache.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_cache.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_cache.h + $(PROJECT_INCLUDE)/bsp/alt_clock_group.h: hwlib/include/alt_clock_group.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_clock_group.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_clock_group.h @@ -155,6 +163,18 @@ $(PROJECT_INCLUDE)/bsp/alt_clock_manager.h: hwlib/include/alt_clock_manager.h $( $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_clock_manager.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_clock_manager.h +$(PROJECT_INCLUDE)/bsp/alt_dma_common.h: hwlib/include/alt_dma_common.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_dma_common.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_dma_common.h + +$(PROJECT_INCLUDE)/bsp/alt_dma.h: hwlib/include/alt_dma.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_dma.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_dma.h + +$(PROJECT_INCLUDE)/bsp/alt_dma_program.h: hwlib/include/alt_dma_program.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_dma_program.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_dma_program.h + $(PROJECT_INCLUDE)/bsp/alt_generalpurpose_io.h: hwlib/include/alt_generalpurpose_io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_generalpurpose_io.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_generalpurpose_io.h @@ -175,6 +195,10 @@ $(PROJECT_INCLUDE)/bsp/alt_mpu_registers.h: hwlib/include/alt_mpu_registers.h $( $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_mpu_registers.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_mpu_registers.h +$(PROJECT_INCLUDE)/bsp/alt_qspi_private.h: hwlib/include/alt_qspi_private.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_qspi_private.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_qspi_private.h + $(PROJECT_INCLUDE)/bsp/alt_reset_manager.h: hwlib/include/alt_reset_manager.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_reset_manager.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_reset_manager.h @@ -191,6 +215,14 @@ $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h: hwlib/include/socal/alt_clkmgr.h $(PR $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h +$(PROJECT_INCLUDE)/bsp/socal/alt_dmanonsecure.h: hwlib/include/socal/alt_dmanonsecure.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_dmanonsecure.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_dmanonsecure.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_dmasecure.h: hwlib/include/socal/alt_dmasecure.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_dmasecure.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_dmasecure.h + $(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h: hwlib/include/socal/alt_gpio.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_gpio.h @@ -203,6 +235,14 @@ $(PROJECT_INCLUDE)/bsp/socal/alt_l3.h: hwlib/include/socal/alt_l3.h $(PROJECT_IN $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_l3.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_l3.h +$(PROJECT_INCLUDE)/bsp/socal/alt_qspidata.h: hwlib/include/socal/alt_qspidata.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_qspidata.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_qspidata.h + +$(PROJECT_INCLUDE)/bsp/socal/alt_qspi.h: hwlib/include/socal/alt_qspi.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_qspi.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_qspi.h + $(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h: hwlib/include/socal/alt_rstmgr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_rstmgr.h From sebh at rtems.org Tue Aug 26 15:12:23 2014 From: sebh at rtems.org (Sebastian Huber) Date: Tue, 26 Aug 2014 15:12:23 -0000 Subject: [rtems commit] bsp/altera-cyclone-v: Update to hwlib 13.1 Message-ID: <20140826150327.75170700812@git.rtems.org> Module: rtems Branch: master Commit: 9907ddeb5a1e823129ab7aeeeed1ed4f7a60151c Changeset: http://git.rtems.org/rtems/commit/?id=9907ddeb5a1e823129ab7aeeeed1ed4f7a60151c Author: Sebastian Huber Date: Tue Aug 26 16:59:56 2014 +0200 bsp/altera-cyclone-v: Update to hwlib 13.1 This version is distributed with SoC EDS 14.0.0.200. --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 3 +- .../libbsp/arm/altera-cyclone-v/hwlib/README.txt | 35 +- .../hwlib/include/alt_address_space.h | 461 ++- .../hwlib/include/alt_clock_group.h | 143 +- .../hwlib/include/alt_clock_manager.h | 107 +- .../hwlib/include/alt_generalpurpose_io.h | 246 +- .../hwlib/include/alt_hwlibs_ver.h | 16 +- .../hwlib/include/alt_interrupt_common.h | 2 + .../hwlib/include/alt_reset_manager.h | 42 + .../arm/altera-cyclone-v/hwlib/include/hwlib.h | 1 - .../hwlib/include/socal/alt_acpidmap.h | 3569 ++++++++++ .../altera-cyclone-v/hwlib/include/socal/socal.h | 181 +- .../hwlib/src/hwmgr/alt_address_space.c | 393 +- .../hwlib/src/hwmgr/alt_clock_manager.c | 7386 +++++++++++--------- .../hwlib/src/hwmgr/alt_generalpurpose_io.c | 32 + .../lib/libbsp/arm/altera-cyclone-v/preinstall.am | 10 +- 16 files changed, 8786 insertions(+), 3841 deletions(-) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index 939ccc7..a581dee 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -77,6 +77,7 @@ include_bsp_HEADERS += hwlib/include/hwlib.h #include_bsp_HEADERS += hwlib/include/alt_interrupt.h # Some of the headers from hwlib need the files from socal. Install them. +include_bsp_socal_HEADERS += hwlib/include/socal/alt_acpidmap.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_clkmgr.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_gpio.h include_bsp_socal_HEADERS += hwlib/include/socal/alt_i2c.h @@ -118,7 +119,7 @@ libbsp_a_CPPFLAGS = libbsp_a_LIBADD = # for the Altera hwlib -libbsp_a_CPPFLAGS += -I ${srcdir}/hwlib/include +libbsp_a_CPPFLAGS += -I${srcdir}/hwlib/include libbsp_a_CPPFLAGS += -std=gnu99 CFLAGS += -Wno-missing-prototypes diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt index 154b343..d0f505d 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt @@ -16,37 +16,4 @@ Altera provides the hwlib with their SoC Embedded Design Suite (EDS). HWLIB Version: -------------- -The files have been taken from the following hwlib versions: - -|======================================== -| Version | File -| | -| 13.0SP1 | include/alt_address_space.h -| 13.0SP1 | include/alt_clock_group.h -| 13.0SP1 | include/alt_clock_manager.h -| 13.0SP1 | include/alt_generalpurpose_io.h -| 13.0SP1 | include/alt_hwlibs_ver.h -| 13.1 | include/alt_i2c.h -| 13.0SP1 | include/alt_interrupt_common.h -| 13.0SP1 | include/alt_mpu_registers.h -| 13.0SP1 | include/alt_reset_manager.h -| 13.0SP1 | include/hwlib.h -| 13.0SP1 | include/socal/alt_clkmgr.h -| 13.0SP1 | include/socal/alt_gpio.h -| 13.1 | include/socal/alt_i2c.h -| 13.0SP1 | include/socal/alt_l3.h -| 13.0SP1 | include/socal/alt_rstmgr.h -| 13.0SP1 | include/socal/alt_sdr.h -| 13.0SP1 | include/socal/alt_sysmgr.h -| 13.0SP1 | include/socal/alt_uart.h -| 13.0SP1 | include/socal/hps.h -| 13.0SP1 | include/socal/socal.h -| 13.0SP1 | src/hwmgr/alt_address_space.c -| 13.0SP1 | src/hwmgr/alt_clock_manager.c -| 13.0SP1 | src/hwmgr/alt_generalpurpose_io.c -| 13.1 | src/hwmgr/alt_i2c.c -| 13.0SP1 | src/hwmgr/alt_reset_manager.c -|======================================== - -hwlib 13.0SP1 is from SoC EDS 13.0.1.232 -hwlib 13.1 is from SoC EDS 14.0.0.200 +All files are from hwlib 13.1 distributed with SoC EDS 14.0.0.200. diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h index b66ccdf..781cc49 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h @@ -32,8 +32,8 @@ * ******************************************************************************/ -#ifndef __ALT_ADDR_SPACE_H__ -#define __ALT_ADDR_SPACE_H__ +#ifndef __ALT_ADDRESS_SPACE_H__ +#define __ALT_ADDRESS_SPACE_H__ #include #include "hwlib.h" @@ -82,7 +82,7 @@ extern "C" #define L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST) // Address Filtering End Register - End Value Mask #define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000 -// Address Filtering End Register - Reset End Address Value (3 GB) +// Address Filtering End Register - Reset End Address Value (3 GiB) #define L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000 #ifndef __ASSEMBLY__ @@ -192,10 +192,10 @@ typedef enum ALT_ADDR_SPACE_MPU_ATTR_e */ typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e { - ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM, /*!< Maps the SDRAM to address 0x0 + ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, /*!< Maps the SDRAM to address 0x0 * for the non-MPU L3 masters. */ - ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM /*!< Maps the On-chip RAM to address + ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address * 0x0 for the non-MPU L3 * masters. Note that the On-chip * RAM is also always mapped to @@ -276,12 +276,12 @@ ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, * * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest * 64KB of the boot region are accessible because the size of the Boot ROM and - * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MB) to - * 0xC0000000 (3GB) access SDRAM and addresses in the range 0xC0000000 (3GB) to - * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MB of SDRAM is not + * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MiB) to + * 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to + * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not * accessible to the MPU unless address 0 is remapped to SDRAM after reset. * - * This function remaps the addresses between 0x0 to 0x100000 (1MB) to access + * This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access * SDRAM. * * \internal @@ -332,13 +332,13 @@ ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void); * \param addr_filt_start * [out] An output parameter variable for the address filtering * start address for the range of physical addresses redirected to - * the SDRAM AXI master port. The value returned is always a 1 MB + * the SDRAM AXI master port. The value returned is always a 1 MiB * aligned address. * * \param addr_filt_end * [out] An output parameter variable for the address filtering * end address for the range of physical addresses redirected to - * the SDRAM AXI master port. The value returned is always a 1 MB + * the SDRAM AXI master port. The value returned is always a 1 MiB * aligned address. * * \retval ALT_E_SUCCESS The operation was successful. @@ -353,7 +353,7 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start, /*! * Set the L2 cache address filtering configuration settings. * - * Address filtering start and end values must be 1 MB aligned. + * Address filtering start and end values must be 1 MiB aligned. * * \param addr_filt_start * The address filtering start address for the range of physical @@ -380,6 +380,441 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, /*! @} */ +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping + * + * This API provides management of the ACP ID Mapper that enables data coherent + * access to the MPU address space by external masters. The set of external + * masters include L3 master peripherals and FPGA soft IP. + * + * The Accelerator Coherency Port (ACP) allows peripherals - including FPGA + * based soft IP - to maintain data coherency with the Cortex-A9 MPCore + * processors and the Snoop Control Unit (SCU). + * + * The ACP supports up to six masters. However, soft IP implemented in the FPGA + * fabric can have a larger number of masters that need to access the ACP. The + * ACP ID Mapper expands the number of masters able to access the ACP. The ACP + * ID Mapper is situated between the interconnect and the ACP of the MPU + * subsystem. It has the following characteristics: + * * Support for up to six concurrent ID mappings. + * * 1 GiB coherent window into 4 GiB MPU address space + * * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU) + * and L2 cache. + * + * The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller + * Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input + * identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output + * identifiers) required by the ACP slave port. + * + * The ACP ID Mapper supports the two ID mapping modes: + * * Dynamic Mapping - In this mode an input ID is automatically mapped to an + * available output ID. The dynamic mode is more flexible because the hardware + * handles the mapping. The hardware mapping allows an output ID to be used + * for more than one input ID. Output IDs are assigned to input IDs on a + * first-come, first-served basis. + * * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs + * to output IDs. + * + * Out of the total of eight ACP output ID values, only six are available to the + * ACP ID Mapper for remapping. The first two output IDs (0 and 1) are + * dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the + * last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6 + * support fixed and dynamic modes of operation while output ID 7 supports + * dynamic mode only. + * + * The following table summarizes the usage of the 3-bit ouput ID values by the + * ACP ID Mapper and their settings at reset. + * + * Output ID | Usage | Reset State + * :-----------|:--------------------------------------------------|:------------ + * 0 | Reserved for Cortex-A9 cores. | - + * 1 | Reserved for Cortex-A9 cores. | - + * 2 | Assigned to Debug Access Port (DAP) input ID at | Fixed + * : | reset. After reset, can be reconfigured to either | DAP Master + * : | fixed or dynamic. |: + * 3 | Configurable fixed or dynamic mode. | Dynamic + * 4 | Configurable fixed or dynamic mode. | Dynamic + * 5 | Configurable fixed or dynamic mode. | Dynamic + * 6 | Configurable fixed or dynamic mode. | Dynamic + * 7 | Dynamic mode only. | Dynamic + * + * Where Output ID is the ACP ID Mapper output value that goes to the ACP. + * + * Additionally, for masters unable to drive the AXI user sideband signals of + * incoming transactions, the ACP ID Mapper allows control of the AXI user + * sideband signal values. Not all masters drive these signals, so the ACP ID + * Mapper makes it possible to drive the 5-bit user sideband signal with either + * a default value (in dynamic mode) or specific values (in fixed mode). + * + * The ACP ID Mapper can also control which 1 GiB coherent window into memory is + * accessed by masters of the L3 interconnect. Each fixed mapping can be + * assigned a different user sideband signal and memory window to allow specific + * settings for different masters. All dynamic mappings share a common user + * sideband signal and memory window setting. One important exception, however, + * is that the ACP ID mapper always allows user sideband signals from the + * FPGA-to-HPS bridge to pass through to the ACP regardless of the configured + * user sideband value associated with the ID. + * + * The ACP ID Mapper has a 1 GiB address window into the MPU address space, which + * is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows + * transactions to be routed to different 1 GiB-sized memory views, called pages, + * in both dynamic and fixed modes. + * + * See: Chapter 6: Cortex-A9 Microprocessor Unit Subsystem in + * Volume 3: Hard Processor System Technical Reference Manual of the + * Arria V or Cyclone V Device Handbook for a complete discussion of + * the operation and restrictions on the ACP and the ACP ID Mapper. + * + * @{ + */ + +/******************************************************************************/ +/*! + * \name External Master ID Macros + * + * These macros define the HPS external master identifiers that are 12-bit input + * IDs to the ACP ID Mapper. Some of the masters have a range of identifier + * values assigned to them and are distinguished by taking a (var)\ + * argument. + * @{ + */ + +/*! Bit mask for the relevant 12 bits of an external master ID */ +#define ALT_ACP_ID_MAP_MASTER_ID_MASK 0xfff + +/*! Master ID for L2M0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var) (0x00000002 | (0x000007f8 & (var))) +/*! Master ID for DMA */ +#define ALT_ACP_ID_MAP_MASTER_ID_DMA(var) (0x00000001 | (0x00000078 & (var))) +/*! Master ID for EMAC0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var) (0x00000801 | (0x00000878 & (var))) +/*! Master ID for EMAC1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var) (0x00000802 | (0x00000878 & (var))) +/*! Master ID for USB0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB0 0x00000803 +/*! Master ID for USB1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB1 0x00000806 +/*! Master ID for NAND controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_NAND(var) (0x00000804 | (0x00000ff8 & (var))) +/*! Master ID for Embedded Trace Router (ETR) */ +#define ALT_ACP_ID_MAP_MASTER_ID_TMC 0x00000800 +/*! Master ID for Debug Access Port (DAP) */ +#define ALT_ACP_ID_MAP_MASTER_ID_DAP 0x00000004 +/*! Master ID for SD/MMC controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_SDMMC 0x00000805 +/*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */ +#define ALT_ACP_ID_MAP_MASTER_ID_F2H(var) (0x00000000 | (0x000007f8 & (var))) +/*! @} */ + +/******************************************************************************/ +/*! + * This type defines the enumerations 3-bit output ids to ACP ID mapper. + */ +typedef enum ALT_ACP_ID_OUTPUT_ID_e +{ + ALT_ACP_ID_OUT_FIXED_ID_2 = 2, /*!< Assigned to the input ID of the DAP at reset. + * After reset, can be either fixed or dynamic, + * programmed by software. + */ + ALT_ACP_ID_OUT_DYNAM_ID_3 = 3, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_4 = 4, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_5 = 5, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_6 = 6, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_7 = 7 /*!< Dynamic mapping only */ +} ALT_ACP_ID_OUTPUT_ID_t; + +/*! + * This type defines the enumerations used to specify the 1 GiB page view of the + * MPU address space used by an ACP ID mapping configuration. + */ +typedef enum ALT_ACP_ID_MAP_PAGE_e +{ + ALT_ACP_ID_MAP_PAGE_0 = 0, /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_1 = 1, /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_2 = 2, /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */ + ALT_ACP_ID_MAP_PAGE_3 = 3 /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */ +} ALT_ACP_ID_MAP_PAGE_t; + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for read transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating read transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates read + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for write transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating write transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates write + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e awuser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for read + * transactions. The \e output_id value is available for dynamic assignment to + * external master read transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_read_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for write + * transactions. The \e output_id value is available for dynamic assignment to + * external master write transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_write_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the page and user read sideband signal options that are applied to + * all read transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e aruser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure the page and user write sideband signal options that are applied to + * all write transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e awuser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Return the current read transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param aruser + * [out] The 5-bit AXI ARUSER read user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* aruser); + +/******************************************************************************/ +/*! + * Return the current write transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param awuser + * [out] The 5-bit AXI AWUSER write user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* awuser); + +/*! @} */ + /*! @} */ #endif /* __ASSEMBLY__ */ @@ -387,4 +822,4 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, #ifdef __cplusplus } #endif /* __cplusplus */ -#endif /* __ALT_ADDR_SPACE_H__ */ +#endif /* __ALT_ADDRESS_SPACE_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h index a5e8c92..a43608e 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h @@ -1,37 +1,39 @@ -/*! \file - * Contains the definition of an opaque data structure that contains raw - * configuration information for a clock group. - */ - /****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! + * \file + * + * Contains the definition of an opaque data structure that contains raw + * configuration information for a clock group. + */ #ifndef __ALT_CLK_GRP_H__ #define __ALT_CLK_GRP_H__ @@ -44,48 +46,65 @@ extern "C" { #endif /* __cplusplus */ - -/*! This type definition enumerates the clock groups -*/ +/*! + * This type definition enumerates the clock groups + */ typedef enum ALT_CLK_GRP_e { - ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ + ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ - ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ + ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ - ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ + ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ } ALT_CLK_GRP_t; - - -/*! This type definition defines an opaque data structure for holding the - * configuration settings for a complete clock group. +/*! + * This type definition defines an opaque data structure for holding the + * configuration settings for a complete clock group. */ typedef struct ALT_CLK_GROUP_RAW_CFG_s { - uint32_t verid; /*!< SoC FPGA version identifier. This field - * encapsulates the silicon identifier and - * version information associated with this - * clock group configuration. It is used to - * assert that this clock group configuration - * is valid for this device. - */ - uint32_t siliid2; /*!< Reserved register - reserved for future - * device IDs or capability flags/ - */ - ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator */ - - - /*! This union holds the raw register values for configuration of the set of - * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator - * identifies the valid clock group union data member. + uint32_t verid; /*!< SoC FPGA version identifier. This field + * encapsulates the silicon identifier and + * version information associated with this + * clock group configuration. It is used to + * assert that this clock group configuration + * is valid for this device. */ + + uint32_t siliid2; /*!< Reserved register - reserved for future + * device IDs or capability flags. */ + + ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */ + + /*! + * This union holds the register values for configuration of the set of + * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator + * identifies the valid clock group union data member. */ union ALT_CLK_GROUP_RAW_CFG_u { - ALT_CLKMGR_MAINPLL_t mainpllgrp; /*!< Raw clock group configuration for Main PLL group */ - ALT_CLKMGR_PERPLL_t perpllgrp; /*!< Raw clock group configuration for Peripheral PLL group */ - ALT_CLKMGR_SDRPLL_t sdrpllgrp; /*!< Raw clock group configuration for SDRAM PLL group */ + /*! Clock group configuration for Main PLL group. */ + union + { + ALT_CLKMGR_MAINPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */ + } mainpllgrp; + + /*! Clock group configuration for Peripheral PLL group. */ + union + { + ALT_CLKMGR_PERPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */ + } perpllgrp; + + /*! Clock group configuration for SDRAM PLL group. */ + union + { + ALT_CLKMGR_SDRPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */ + } sdrpllgrp; + } clkgrp; } ALT_CLK_GROUP_RAW_CFG_t; diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h index 7cf0e12..d6d9654 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h @@ -6,20 +6,20 @@ /****************************************************************************** * * Copyright 2013 Altera Corporation. All Rights Reserved. -* +* * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* +* * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* +* * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* +* * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. -* +* * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO @@ -30,7 +30,7 @@ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. -* +* ******************************************************************************/ #ifndef __ALT_CLK_MGR_H__ @@ -82,7 +82,7 @@ typedef enum ALT_CLK_e /*!< \b OSC_CLK_2_HPS * External Oscillator input: * * Input Pin - * * Optional clock source to SDRAM PLL + * * Optional clock source to SDRAM PLL * and Peripheral PLL if selected * * Typically used for Ethernet * reference clock @@ -132,7 +132,7 @@ typedef enum ALT_CLK_e * * Input Pin */ - + /* PLLs */ ALT_CLK_MAIN_PLL, /*!< \b main_pll_ref_clkin @@ -142,7 +142,7 @@ typedef enum ALT_CLK_e */ ALT_CLK_PERIPHERAL_PLL, - /*!< \b periph_pll_ref_clkin + /*!< \b periph_pll_ref_clkin * Peripheral PLL input reference * clock, used to designate the * Peripheral PLL in PLL clock @@ -236,7 +236,7 @@ typedef enum ALT_CLK_e ALT_CLK_L4_SP, /*!< \b l4_sp_clk - * Clock for L4 slave peripherals (SP) bus + * Clock for L4 slave peripherals (SP) bus */ ALT_CLK_DBG_BASE, @@ -279,14 +279,14 @@ typedef enum ALT_CLK_e */ ALT_CLK_MAIN_NAND_SDMMC, - /*!< \b main_nand_sdmmc_clk + /*!< \b main_nand_sdmmc_clk * Main PLL C4 Output. Input clock to * flash controller clocks block. * * Alias for \e ALT_CLK_MAIN_PLL_C4 */ ALT_CLK_CFG, - /*!< \b cfg_clk + /*!< \b cfg_clk * FPGA manager configuration clock. */ @@ -295,7 +295,7 @@ typedef enum ALT_CLK_e * Clock to FPGA fabric */ - + /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */ ALT_CLK_PERIPHERAL_PLL_C0, /*!< \b Peripheral PLL C0 Output */ @@ -556,7 +556,7 @@ typedef enum ALT_CLK_PLL_LOCK_STATUS_e * assertion conditions. * * \param lock_stat_mask - * Specifies the PLL lock status conditions to clear. \e lock_stat_mask + * Specifies the PLL lock status conditions to clear. \e lock_stat_mask * is a mask of logically OR'ed \ref ALT_CLK_PLL_LOCK_STATUS_t * values designating the PLL lock conditions to clear. * @@ -588,12 +588,12 @@ uint32_t alt_clk_lock_status_get(void); * * \retval ALT_E_TRUE The specified PLL is currently locked. * \retval ALT_E_FALSE The specified PLL is currently not locked. - * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock + * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock * value. * \internal * NOTE: This function uses the * * \b hps::clkmgr::inter::mainplllocked - * * \b hps::clkmgr::inter::perplllocked, + * * \b hps::clkmgr::inter::perplllocked, * * \b hps::clkmgr::inter::sdrplllocked * * bits to determine if the PLL is locked or not. @@ -612,30 +612,30 @@ ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll); * request from the reset manager sets the safe mode bit in the clock manager * control register. No other control register bits are affected by the safe * mode request from the reset manager. - * + * * While in safe mode, clock manager register settings which control clock * behavior are not changed. However, the output of the registers which control * the clock manager state are forced to the safe mode values such that the * following conditions occur: * * All PLLs are bypassed to the \b osc1_clk clock, including their counters. * * Clock dividers select their default reset values. - * * The flash controllers source clock selections are set to the peripheral + * * The flash controllers source clock selections are set to the peripheral * PLL. * * All clocks are enabled. * * Safe mode is optionally applied to debug clocks. - * + * * A write by software is the only way to clear the safe mode bit. All registers * and clocks need to be configured correctly and all software-managed clocks * need to be gated off before clearing safe mode. Software can then gate clocks * on as required. - * + * * On cold reset, all clocks are put in safe mode. - * + * * On warm reset, safe mode is optionally and independently applied to debug * clocks and normal (i.e.non-debug) clocks based on clock manager register * settings. The default response for warm reset is to put all clocks in safe * mode. - * + * * The APIs in this group provide control of the Clock Manager safe mode warm * reset response behavior. * @{ @@ -651,12 +651,12 @@ typedef enum ALT_CLK_SAFE_DOMAIN_e /*! * This enumeration literal specifies the normal safe mode domain. The * normal domain consists of all clocks except debug clocks. - */ + */ ALT_CLK_DOMAIN_NORMAL, /*! * This enumeration literal specifies the debug safe mode domain. The debug * domain consists of all debug clocks. - */ + */ ALT_CLK_DOMAIN_DEBUG } ALT_CLK_SAFE_DOMAIN_t; @@ -703,7 +703,7 @@ bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain); * * In summary, the PLL bypass controls permit: * * Each PLL to be individually bypassed. - * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs + * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs * reference clock input source reference clock selection. * * Isolation of a the PLL VCO frequency registers (multiplier and divider), phase shift registers (negative phase) , and post scale counters. @@ -720,7 +720,7 @@ bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL clock + * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL clock * value. */ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll); @@ -751,7 +751,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, /*! * Return whether the specified PLL is in bypass or not. * - * \internal + * \internal * This function must also test the \b clkmgr.ctrl.safemode bit in * addition to the PLLs bypass bit to tell whether the bypass mode is * effect or not. @@ -762,7 +762,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, * * \retval ALT_E_TRUE The PLL is in bypass mode. * \retval ALT_E_FALSE The PLL is not in bypass mode. - * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock + * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock * value. */ ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll); @@ -824,7 +824,7 @@ ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock + * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock * value. */ ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk); @@ -839,7 +839,7 @@ ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock + * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock * value. */ ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk); @@ -853,7 +853,7 @@ ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk); * * \retval ALT_E_TRUE The clock is enabled. * \retval ALT_E_FALSE The clock is not enabled. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock + * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock * value. */ ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk); @@ -912,12 +912,12 @@ ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk); * Get the input reference clock source selection value for the specified clock * or PLL. * - * NOTE: This function returns a clock value even though \e clk may specify a - * clock that does not have a selectable input reference clock source. In - * this case, the clock value returned is the static clock source for the + * NOTE: This function returns a clock value even though \e clk may specify a + * clock that does not have a selectable input reference clock source. In + * this case, the clock value returned is the static clock source for the * specified clock. For example calling alt_clk_source_get() with \e clk * set to \ref ALT_CLK_MAIN_PLL will return \ref ALT_CLK_OSC1. - * + * * \param clk * The clock or PLL to retrieve the input reference clock source * selection value for. @@ -939,14 +939,14 @@ ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk); * * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a clock that - * does not have a selectable input reference + * \retval ALT_E_BAD_ARG The \e clk argument designates a clock that + * does not have a selectable input reference * clock source. - * \retval ALT_E_INV_OPTION The \e ref_clk argument designates a clock that - * is an invalid reference clock source for the + * \retval ALT_E_INV_OPTION The \e ref_clk argument designates a clock that + * is an invalid reference clock source for the * specified clock. */ -ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, +ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk); /*! @} */ @@ -981,7 +981,7 @@ ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, * \retval ALT_E_SUCCESS The operation was succesful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG A bad argument value was passed. Either the \e clk - * argument is bad or not a valid external clock + * argument is bad or not a valid external clock * source * \retval ALT_E_ARG_RANGE The frequency value violates the range constraints * for the specified clock. @@ -1018,17 +1018,17 @@ alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk); typedef struct ALT_CLK_PLL_CFG_s { ALT_CLK_t ref_clk; /*!< PLL Reference Clock Source */ - uint32_t mult; /*!< VCO Frequency Configuration - + uint32_t mult; /*!< VCO Frequency Configuration - * Multiplier (M) value, range 1 to 4096 */ - uint32_t div; /*!< VCO Frequency Configuration - + uint32_t div; /*!< VCO Frequency Configuration - * Divider (N) value, range 1 to 64 */ uint32_t cntrs[6]; /*!< Post-Scale Counters (C0 - C5) - * range 1 to 512 */ uint32_t pshift[6]; /*!< Phase Shift - 1/8 (45 degrees) of - * negative phase shift per increment, + * negative phase shift per increment, * range 0 to 4096 */ } ALT_CLK_PLL_CFG_t; @@ -1262,7 +1262,7 @@ ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, * The following interrupt request (IRQ) signals are sourced from the Clock * Manager: * - * * \b clkmgr_IRQ - Clock Manager lock status interrupt output. The PLL lock + * * \b clkmgr_IRQ - Clock Manager lock status interrupt output. The PLL lock * status interrupt is the logical \e OR of six interrupt * sources defining the loss or achievement of lock status for * each PLL. The six PLL lock status conditions are: @@ -1275,7 +1275,7 @@ ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, * * They are enumeratated by the type \ref ALT_CLK_PLL_LOCK_STATUS_t. * - * Each PLL lock condition may be individually disabled/enabled + * Each PLL lock condition may be individually disabled/enabled * as a contributor to the determination of the \b clkmgr_IRQ * assertion status. * @@ -1283,7 +1283,7 @@ ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, * the PLL lock conditions causing the \b clkmgr_IRQ * assertion. * - * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the + * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the * MPU to "wake up" after a transition of the Main PLL into * or out of bypass mode has been safely achieved. The need * for the "wake up" notification is because the PLL clocks @@ -1368,14 +1368,14 @@ ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask); * * A known good clock group configuration may be generated by one of the * following methods: - * - * * As static design information generated by an ACDS clock configuration tool + * + * * As static design information generated by an ACDS clock configuration tool * and passed to embedded software for dynamic loading. - * + * * * By calling alt_clk_group_cfg_raw_get() at run-time from an SoC FPGA that has * programmatically established a known good clock group configuration using * the clock manager API configuration functions. - * + * * @{ */ @@ -1407,7 +1407,7 @@ ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, * * This function is used to safely set the configuration state of a clock * group from a raw clock group configuration specification. The raw clock - * group configuration specification may be a configuration previously + * group configuration specification may be a configuration previously * captured with alt_clk_group_cfg_raw_get() or a group clock configuration * generated by an external utility. * @@ -1422,10 +1422,13 @@ ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, */ ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg); +ALT_STATUS_CODE alt_clk_clkmgr_init(void); + /*! @} */ /*! @} */ #ifdef __cplusplus } + #endif /* __cplusplus */ #endif /* __ALT_CLK_MGR_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h index d8a38f5..0a7abae 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h @@ -5,20 +5,20 @@ /****************************************************************************** * * Copyright 2013 Altera Corporation. All Rights Reserved. -* +* * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* +* * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* +* * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* +* * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. -* +* * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO @@ -29,7 +29,7 @@ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. -* +* ******************************************************************************/ #ifndef __ALT_GPIO_H__ @@ -57,8 +57,8 @@ extern "C" { /******************************************************************************/ /*! \addtogroup ALT_GPIO_API The General Purpose Input/Output Manager API * - * This module defines the General Purpose Input/Output Manager API for - * accessing, configuring, and controlling the General Purpose Input/Output + * This module defines the General Purpose Input/Output Manager API for + * accessing, configuring, and controlling the General Purpose Input/Output * Manager resources. These include both the general-purpose GPIO signals and * the input-only GPI signals that are shared with the DDR interface.\n \n * The GPIO API presents two views or perspectives of the GPIO signals. The first @@ -100,7 +100,7 @@ extern "C" { */ /******************************************************************************/ /*! - * This type definition enumerates the data direction (input or output) of + * This type definition enumerates the data direction (input or output) of * the GPIO signals. */ @@ -114,7 +114,7 @@ typedef enum ALT_GPIO_PIN_DIR_e /******************************************************************************/ /*! - * This type definition enumerates the type of interrupt source + * This type definition enumerates the type of interrupt source * (level-triggered or edge-triggered) of the GPIO signals. */ @@ -128,7 +128,7 @@ typedef enum ALT_GPIO_PIN_TYPE_e /******************************************************************************/ /*! - * This type definition enumerates the polarity of the interrupt sources + * This type definition enumerates the polarity of the interrupt sources * (falling-edge or rising-edge for edge-triggered interrupts, active-low or * active-high for level-triggered interrupts) of the GPIO signals. */ @@ -193,7 +193,7 @@ typedef enum ALT_GPIO_PIN_DATA_e /******************************************************************************/ /*! - * This type definition enumerates the GPIO ports that the GPIO manager + * This type definition enumerates the GPIO ports that the GPIO manager * handles. */ @@ -208,7 +208,7 @@ typedef enum ALT_GPIO_PORT_e * \b Port \b B - 29-bit GPIO port B. */ ALT_GPIO_PORTB, - + /*! * \b Port \b C - 29-bit GPIO port C. \n 13 bits are used for GPIO signals, * 14 bits are used for GPI-only signals that are shared @@ -224,12 +224,12 @@ typedef enum ALT_GPIO_PORT_e ALT_GPIO_PORT_UNKNOWN } ALT_GPIO_PORT_t; - + /******************************************************************************/ /*! * This type definition enumerates the individual bits within the GPIO ports - * used by the GPIO manager. The bit-ordering must match the hardware - * bit-ordering. Since the ordering and packing of bitfields is not + * used by the GPIO manager. The bit-ordering must match the hardware + * bit-ordering. Since the ordering and packing of bitfields is not * standardized in C/C++, the following are defined as masks. \n * For example, to set bits 3 and 4 of GPIO port B outputs (assuming the bits * had previously been set to outputs), the user could use the syntax: \par @@ -310,20 +310,38 @@ typedef enum ALT_GPIO_PORTBIT_e /******************************************************************************/ /*! - * Sets the specified GPIO data bits to use the data direction(s) + * Initialize the GPIO modules before use + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_init(void); + +/******************************************************************************/ +/*! + * Uninitialize the GPIO modules & return to reset state + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_uninit(void); + +/******************************************************************************/ +/*! + * Sets the specified GPIO data bits to use the data direction(s) * specified. * * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this - * operation to. Other bits (where mask bits equal zero) are + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * configure all data direction bits of the port. * \param config * The data-directions of the bits to be set in this operation. - * Individual bits are: \n \b 0 - Use as an input (default). \n + * Individual bits are: \n \b 0 - Use as an input (default). \n * \b 1 - Use as an output. * * \retval ALT_E_SUCCESS The operation was successful. @@ -335,18 +353,18 @@ ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Returns the data direction configuration of selected bits of the + * Returns the data direction configuration of selected bits of the * specified GPIO module. * * \param gpio_pid * The GPIO port identifier. * \param mask * The group of bits (where mask bits equal one) to read and - * return. Other bits (where mask bits equal zero) are returned + * return. Other bits (where mask bits equal zero) are returned * as zero. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * return all data direction bits of the port. * - * \retval uint32_t \n Individual bits are: \n \b 0 - The signal is + * \retval uint32_t \n Individual bits are: \n \b 0 - The signal is * configured as an input. * \n \b 1 - The signal is configured as an output. * @@ -367,7 +385,7 @@ uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid, * operation to. Other bits (mask bits equal zero) are * not changed. * \param val - * The 32-bit word to write to the GPIO outputs. Only the 29 LSBs + * The 32-bit word to write to the GPIO outputs. Only the 29 LSBs * are used. Setting the three MSBs causes an error. * * \retval ALT_E_SUCCESS The operation was successful. @@ -387,8 +405,8 @@ ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all data bits of * the port. * @@ -408,21 +426,21 @@ uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask); */ /******************************************************************************/ /*! - * Sets edge-triggered or level-triggered interrupt configuration for the + * Sets edge-triggered or level-triggered interrupt configuration for the * specified signals of the specified GPIO module. * * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this + * The group of bits (where mask bits equal one) to apply this * operation to. Other bits (where mask bits equal zero) are * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * configure all interrupt type bits of the port. * \param config - * The interrupt configuration to write. Individual bits - * are: \n \b 0 - Set the - * interrupt for this bit to be level-sensitive (default). \n \b + * The interrupt configuration to write. Individual bits + * are: \n \b 0 - Set the + * interrupt for this bit to be level-sensitive (default). \n \b * 1 - Set the interrupt for this bit to be edge-sensitive. * * \retval ALT_E_SUCCESS The operation was successful. @@ -434,20 +452,20 @@ ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Returns the interrupt configuration (edge-triggered or level-triggered) for - * the specified bits of the specified GPIO module. + * Returns the interrupt configuration (edge-triggered or level-triggered) for + * the specified bits of the specified GPIO module. * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all configuration * bits of the port. * \retval uint32_t - * The current interrupt source configuration. Individual bits - * are: \n \b 0 - The interrupt for this bit is set to be - * level-sensitive. \n \b 1 - + * The current interrupt source configuration. Individual bits + * are: \n \b 0 - The interrupt for this bit is set to be + * level-sensitive. \n \b 1 - * The interrupt for this bit is set to be edge-sensitive. * */ @@ -463,12 +481,12 @@ uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this + * The group of bits (where mask bits equal one) to apply this * operation to. Other bits (where mask bits equal zero) are * not changed. * \param config - * The interrupt polarity configuration to set. Individual bits - * are: \n \b 0 - Set the interrupt polarity for this bit to + * The interrupt polarity configuration to set. Individual bits + * are: \n \b 0 - Set the interrupt polarity for this bit to * active-low or falling-edge mode (default). \n \b 1 - Set the * interrupt polarity for this bit to active-high or rising-edge mode. * @@ -481,21 +499,21 @@ ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Returns the active-high or active-low polarity configuration for the + * Returns the active-high or active-low polarity configuration for the * possible interrupt sources of the specified GPIO module. * * * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all the * configuration bits of the port. - * + * * \retval uint32_t - * The current polarity configuration. Individual bits are: \n - * \b 0 = The interrupt polarity for this bit is set to + * The current polarity configuration. Individual bits are: \n + * \b 0 = The interrupt polarity for this bit is set to * active-low or falling-edge mode. \n \b 1 = The interrupt * polarity for this bit is set to active-high or rising-edge mode. * @@ -512,7 +530,7 @@ uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid, */ /******************************************************************************/ /*! - * Sets the debounce configuration for input signals of the specified GPIO + * Sets the debounce configuration for input signals of the specified GPIO * module. If debounce is selected, metastability flip-flops are inserted to * debounce signals presented to the GPIO inputs. A signal must be steady for * two periods of the gpio_db_clk clock before it is considered valid. The @@ -521,13 +539,13 @@ uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to apply this + * The group of bits (where mask bits equal one) to apply this * operation to. Other bits (where mask bits equal zero) are * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to * configure the debounce setting for all bits of the port. * \param config * The debounce configuration to set. Individual bits are: \n - * \b 0 - Debounce is not selected for this signal (default). \n + * \b 0 - Debounce is not selected for this signal (default). \n * \b 1 - Debounce is selected for this signal. * * \retval ALT_E_SUCCESS The operation was successful. @@ -546,14 +564,14 @@ ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid, * \param gpio_pid * The GPIO port identifier. * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all debounce * configuration bits of the port. - * + * * \retval uint32_t - * The current debounce configuration.Individual bits are: \n - * \b 0 - Debounce is not selected for this signal. \n \b 1 - + * The current debounce configuration.Individual bits are: \n + * \b 0 - Debounce is not selected for this signal. \n \b 1 - * Debounce is selected for this signal. * */ @@ -562,8 +580,8 @@ uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! - * Sets the synchronization configuration for the signals of the specified - * GPIO register. This allows for synchronizing level-sensitive interrupts to + * Sets the synchronization configuration for the signals of the specified + * GPIO register. This allows for synchronizing level-sensitive interrupts to * an internal clock signal. This is a port-wide option that controls all * level-sensitive interrupt signals of that GPIO port. * @@ -572,7 +590,7 @@ uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid, * \param config * \n \b Any \b non-zero \b value - Synchronize to internal clock signal. * \n \b Zero - Do not synchronize to internal clock signal. - * + * * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. @@ -584,8 +602,8 @@ ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid, /******************************************************************************/ /*! * - * Returns the synchronization configuration for the signals of the - * specified GPIO register. This allows for synchronizing level-sensitive + * Returns the synchronization configuration for the signals of the + * specified GPIO register. This allows for synchronizing level-sensitive * interrupts to the internal clock signal. This is a port-wide option that * controls all level-sensitive interrupt signals of that GPIO port. * @@ -605,7 +623,7 @@ ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid); /*! * Configures a group of GPIO signals with identical setup parameters. Allows * for configuring all parameters of a given port at one time. - * + * * \param gpio_pid * The GPIO port identifier. * \param mask @@ -621,11 +639,11 @@ ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid); * Debounce signals or not. * \param data * Set the data output to this value. - * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid, uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, @@ -699,11 +717,11 @@ uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid); * \param gpio_pid * The GPIO port identifier. * \param mask - * Which bits to change among the port \n \b 0 = + * Which bits to change among the port \n \b 0 = * Do not change this bit. \n \b 1 = Allow this bit to change. * \param val - * The interrupt mask to write. Individual bits are: \n \b 0 = - * Do not mask the interrupt for this bit (default). \n \b 1 = + * The interrupt mask to write. Individual bits are: \n \b 0 = + * Do not mask the interrupt for this bit (default). \n \b 1 = * Mask the interrupt for this bit. * * \retval ALT_E_SUCCESS The operation was successful. @@ -720,10 +738,10 @@ ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid, * * \param gpio_pid * The GPIO port identifier. - * + * * \retval uint32_t - * The interrupt mask that was read. Individual bits are: \n - * \b 0 = The interrupt for this bit is not masked. \n \b 1 = The + * The interrupt mask that was read. Individual bits are: \n + * \b 0 = The interrupt for this bit is not masked. \n \b 1 = The * interrupt for this bit is masked. * */ @@ -731,16 +749,16 @@ uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid); /******************************************************************************/ /*! - * Returns the interrupt pending status of all signals of the specified GPIO + * Returns the interrupt pending status of all signals of the specified GPIO * register. * * * \param gpio_pid * The GPIO port identifier. - + * \retval uint32_t - * The current interrupt pending status. Individual bits are: \n - * \b 0 - The interrupt for this bit is not pending. \n \b 1 - + * The current interrupt pending status. Individual bits are: \n + * \b 0 - The interrupt for this bit is not pending. \n \b 1 - * The interrupt for this bit is pending. * */ @@ -748,15 +766,15 @@ uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid); /******************************************************************************/ /*! - * Clear the interrupt pending status of selected signals of the + * Clear the interrupt pending status of selected signals of the * specified GPIO register. * * * \param gpio_pid * The GPIO port identifier. * \param clrmask - * The interrupt bits to clear. Individual bits are: \n \b 0 - - * The interrupt for this bit will not be changed. \n \b 1 - + * The interrupt bits to clear. Individual bits are: \n \b 0 - + * The interrupt for this bit will not be changed. \n \b 1 - * The interrupt for this bit will be cleared. * * \retval ALT_E_SUCCESS The operation was successful. @@ -1029,7 +1047,7 @@ typedef struct ALT_GPIO_PIN_RECORD_s /******************************************************************************/ /*! * Configures all parameters for one bit (signal) of the GPIO ports. - * + * * \param signal_num * The GPIO port signal index. * \param dir @@ -1043,7 +1061,7 @@ typedef struct ALT_GPIO_PIN_RECORD_s * \param data * If the GPIO signal is set to be an output, set it to * this value - * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. @@ -1056,78 +1074,78 @@ ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num, /******************************************************************************/ /*! * Returns the configuration parameters of a given GPIO bit. - * + * * \param signal_num * The GPIO port signal index. * \param config * Pointer to a single GPIO_CONFIG_RECORD_s configuration record. * The fields of this configuration record are filled in - * by the function. - * + * by the function. + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num, ALT_GPIO_CONFIG_RECORD_t *config); /******************************************************************************/ /*! - * Configures a list of GPIO bits. The GPIO bits do not have to be - * configured the same, as was the case for the mask version of this function, + * Configures a list of GPIO bits. The GPIO bits do not have to be + * configured the same, as was the case for the mask version of this function, * alt_gpio_port_config(). Each bit may be configured differently and bits may * be listed in any order. - * + * * \param config_array * Pointer to an array of GPIO_CONFIG_RECORD_s configuration * records. These definitions contain all the parameters - * needed to set up the listed pins. All or - * any subset of the GPIO signals can be configured. Signals do - * not have to be listed in numerical order or be unique. If a - * signal number is listed multiple times, the last configuration + * needed to set up the listed pins. All or + * any subset of the GPIO signals can be configured. Signals do + * not have to be listed in numerical order or be unique. If a + * signal number is listed multiple times, the last configuration * listed is used. \n Configuration terminates either when \b len * signals have been configured or if the next signal number index * in the array is equal to \b ALT_END_OF_GPIO_SIGNALS (-1). - * + * * \param len - * Length of array to configure. - * + * Length of array to configure. + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array, uint32_t len); /******************************************************************************/ /*! - * Returns a list of the pin signal indices and the associated configuration + * Returns a list of the pin signal indices and the associated configuration * settings (data direction, interrupt type, polarity, and debounce) of that * list of signals. - * + * * \param config_array * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration * records. Only the signal indices in the first field of each * configuration record need be filled in. This function will * fill in all the other fields of the configuration record, * returning all configuration parameters in the array. - * Signals do not have to be listed in numerical order or be - * unique. If a signal number is listed multiple times, the + * Signals do not have to be listed in numerical order or be + * unique. If a signal number is listed multiple times, the * configuration record will contain multiple entries for * that signal. \n Configuration reading terminates either when * \b len signal configurations have been read or if the next * signal number index in the array is equal to * \b ALT_END_OF_GPIO_SIGNALS (-1). * \param len - * Length of configuration array to read and return. - * - * + * Length of configuration array to read and return. + * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - + */ ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len); @@ -1140,30 +1158,30 @@ ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array * alt_gpio_group_config_get() is this version follows a separate list of * signal indices instead of having the signal list provided in the first * field of the configuration records in the array. - * + * * \param pinid_array * Pointer to a list of signal index numbers. These indices * are copied to the first field of each configuration record * in the returned array. * \param config_array * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration - * records. This function will fill in the fields of the - * configuration record, returning all configuration parameters - * in the array. Signals do not have to be listed in numerical - * order or be unique. If a signal number is listed multiple - * times, the configuration record array will contain multiple + * records. This function will fill in the fields of the + * configuration record, returning all configuration parameters + * in the array. Signals do not have to be listed in numerical + * order or be unique. If a signal number is listed multiple + * times, the configuration record array will contain multiple * identical entries for that signal. \n Configuration reading * terminates either when \b len signal configurations have been * read or if the next signal number index in the array is equal * to \b ALT_END_OF_GPIO_SIGNALS (-1). * \param len - * Length of configuration array to read. - * - * + * Length of configuration array to read. + * + * * \retval ALT_E_SUCCESS The operation was successful. * \retval ALT_E_ERROR The operation failed. * \retval ALT_E_BAD_ARG Invalid input argument. - * + * */ ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array, ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len); @@ -1218,10 +1236,10 @@ ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num); /******************************************************************************/ /*! - * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and - * signal mask. If passed a bitmask composed of more than one signal, the + * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and + * signal mask. If passed a bitmask composed of more than one signal, the * signal number of the lowest bit in the bitmask presented is returned. - * + * */ ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid, uint32_t bitmask); diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h index 57f0f0d..7596d50 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h @@ -36,17 +36,21 @@ * ***********************************************************************/ -/* This is the major revision of the Altera ACDS Release */ +/* This is the major revision of the Altera ACDS Release */ #define ALTERA_ACDS_MAJOR_REV 13 -/* This is the minor revision of the Altera ACDS Release */ -#define ALTERA_ACDS_MINOR_REV 0 +/* This is the minor revision of the Altera ACDS Release */ +#define ALTERA_ACDS_MINOR_REV 1 -/* This is an internal HwLibs revision control code. */ -/* End-users should NOT depend upon the value of this field */ +/* This is an internal HwLibs revision/feature control code. */ +/* End-users should NOT depend upon the value of this field */ #define ALTERA_HWLIBS_REV 0 /* This is a text string containing the current release and service pack IDs */ -#define ALTERA_ACDS_REV_STR "13.0SP1" +#define ALTERA_ACDS_REV_STR "13.1" + +/* This is a text string containing the current SoC EDS ID */ +#define ALTERA_SOCEDS_REV_STR "Altera SoC Embedded Design Suite v13.1" + #endif /* __ALT_HWLIBS_VER_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h index db1e6dd..004fd31 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h @@ -343,6 +343,8 @@ typedef enum ALT_INT_INTERRUPT_e ALT_INT_INTERRUPT_SPI3_IRQ = 189, /*!< * Interrupts sourced from the SPI Controllers 0 - 3. + * SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1. + * SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1. * * All interrupts in this group are level triggered. */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h index 7b0da34..d719e3f 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h @@ -239,6 +239,48 @@ ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay, bool fpga_handshake, bool etr_stall); +#if 0 +/*! \addtogroup RST_MGR_MPU + * + * This functional group provides reset control for the Cortex-A9 MPU module. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_PERIPH + * + * This functional group provides inidividual reset control for the HPS + * peripheral modules. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_BRG + * + * This functional group provides inidividual reset control for the bridge + * interfaces between the HPS and FPGA. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_MISC + * + * This functional group provides inidividual reset control for miscellaneous + * HPS modules. + * + * @{ + */ + +/*! @} */ + +#endif + /*! @} */ /*! @} */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h index 7a3bbfd..aba7e87 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h @@ -91,7 +91,6 @@ typedef int32_t ALT_STATUS_CODE; /*! The buffer does not contain enough free space for the operation. */ #define ALT_E_BUF_OVF (-20) - /*! * Indicates a FALSE condition. */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h new file mode 100644 index 0000000..3a6bf0f --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h @@ -0,0 +1,3569 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_ACPIDMAP */ + +#ifndef __ALTERA_ALT_ACPIDMAP_H__ +#define __ALTERA_ALT_ACPIDMAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : ACP ID Mapper Registers - ALT_ACPIDMAP + * ACP ID Mapper Registers + * + * Registers in the ACP ID Mapper module + * + */ +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 2 - vid2rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | ARUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : ARUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD. + */ +struct ALT_ACPIDMAP_VID2RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_s ALT_ACPIDMAP_VID2RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_OFST 0x0 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 2 - vid2wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | AWUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : AWUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR. + */ +struct ALT_ACPIDMAP_VID2WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_s ALT_ACPIDMAP_VID2WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_OFST 0x4 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 3 - vid3rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD. + */ +struct ALT_ACPIDMAP_VID3RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_s ALT_ACPIDMAP_VID3RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_OFST 0x8 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 3 - vid3wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR. + */ +struct ALT_ACPIDMAP_VID3WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_s ALT_ACPIDMAP_VID3WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_OFST 0xc + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 4 - vid4rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD. + */ +struct ALT_ACPIDMAP_VID4RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_s ALT_ACPIDMAP_VID4RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_OFST 0x10 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 4 - vid4wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR. + */ +struct ALT_ACPIDMAP_VID4WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_s ALT_ACPIDMAP_VID4WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_OFST 0x14 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 5 - vid5rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD. + */ +struct ALT_ACPIDMAP_VID5RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_s ALT_ACPIDMAP_VID5RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_OFST 0x18 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 5 - vid5wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR. + */ +struct ALT_ACPIDMAP_VID5WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_s ALT_ACPIDMAP_VID5WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_OFST 0x1c + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 6 - vid6rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD. + */ +struct ALT_ACPIDMAP_VID6RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_s ALT_ACPIDMAP_VID6RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_OFST 0x20 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 6 - vid6wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR. + */ +struct ALT_ACPIDMAP_VID6WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_s ALT_ACPIDMAP_VID6WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_OFST 0x24 + +/* + * Register : Read AXI Master Mapping Register for Dynamic Virtual ID Remap - dynrd + * + * The Read AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD. + */ +struct ALT_ACPIDMAP_DYNRD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_s ALT_ACPIDMAP_DYNRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_OFST 0x28 + +/* + * Register : Write AXI Master Mapping Register for Dynamic Virtual ID Remap - dynwr + * + * The Write AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR. + */ +struct ALT_ACPIDMAP_DYNWR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_s ALT_ACPIDMAP_DYNWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_OFST 0x2c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | ARUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : ARUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD_S. + */ +struct ALT_ACPIDMAP_VID2RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_S_s ALT_ACPIDMAP_VID2RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_S_OFST 0x30 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | AWUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : AWUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR_S. + */ +struct ALT_ACPIDMAP_VID2WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_S_s ALT_ACPIDMAP_VID2WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_S_OFST 0x34 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD_S. + */ +struct ALT_ACPIDMAP_VID3RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_S_s ALT_ACPIDMAP_VID3RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_S_OFST 0x38 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR_S. + */ +struct ALT_ACPIDMAP_VID3WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_S_s ALT_ACPIDMAP_VID3WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_S_OFST 0x3c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD_S. + */ +struct ALT_ACPIDMAP_VID4RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_S_s ALT_ACPIDMAP_VID4RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_S_OFST 0x40 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR_S. + */ +struct ALT_ACPIDMAP_VID4WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_S_s ALT_ACPIDMAP_VID4WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_S_OFST 0x44 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD_S. + */ +struct ALT_ACPIDMAP_VID5RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_S_s ALT_ACPIDMAP_VID5RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_S_OFST 0x48 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR_S. + */ +struct ALT_ACPIDMAP_VID5WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_S_s ALT_ACPIDMAP_VID5WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_S_OFST 0x4c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD_S. + */ +struct ALT_ACPIDMAP_VID6RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_S_s ALT_ACPIDMAP_VID6RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_S_OFST 0x50 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR_S. + */ +struct ALT_ACPIDMAP_VID6WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_S_s ALT_ACPIDMAP_VID6WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_S_OFST 0x54 + +/* + * Register : Read AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynrd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD_S. + */ +struct ALT_ACPIDMAP_DYNRD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_S_s ALT_ACPIDMAP_DYNRD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_S_OFST 0x58 + +/* + * Register : Write AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynwr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR_S. + */ +struct ALT_ACPIDMAP_DYNWR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_S_s ALT_ACPIDMAP_DYNWR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_S_OFST 0x5c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_ACPIDMAP. + */ +struct ALT_ACPIDMAP_s +{ + volatile ALT_ACPIDMAP_VID2RD_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile ALT_ACPIDMAP_VID2WR_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile ALT_ACPIDMAP_VID3RD_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile ALT_ACPIDMAP_VID3WR_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile ALT_ACPIDMAP_VID4RD_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile ALT_ACPIDMAP_VID4WR_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile ALT_ACPIDMAP_VID5RD_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile ALT_ACPIDMAP_VID5WR_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile ALT_ACPIDMAP_VID6RD_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile ALT_ACPIDMAP_VID6WR_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile ALT_ACPIDMAP_DYNRD_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile ALT_ACPIDMAP_DYNWR_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile ALT_ACPIDMAP_VID2RD_S_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile ALT_ACPIDMAP_VID2WR_S_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile ALT_ACPIDMAP_VID3RD_S_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile ALT_ACPIDMAP_VID3WR_S_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile ALT_ACPIDMAP_VID4RD_S_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile ALT_ACPIDMAP_VID4WR_S_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile ALT_ACPIDMAP_VID5RD_S_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile ALT_ACPIDMAP_VID5WR_S_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile ALT_ACPIDMAP_VID6RD_S_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile ALT_ACPIDMAP_VID6WR_S_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile ALT_ACPIDMAP_DYNRD_S_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile ALT_ACPIDMAP_DYNWR_S_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_s ALT_ACPIDMAP_t; +/* The struct declaration for the raw register contents of register group ALT_ACPIDMAP. */ +struct ALT_ACPIDMAP_raw_s +{ + volatile uint32_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile uint32_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile uint32_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile uint32_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile uint32_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile uint32_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile uint32_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile uint32_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile uint32_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile uint32_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile uint32_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile uint32_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile uint32_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile uint32_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile uint32_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile uint32_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile uint32_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile uint32_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile uint32_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile uint32_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile uint32_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile uint32_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile uint32_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile uint32_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_raw_s ALT_ACPIDMAP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_ACPIDMAP_H__ */ + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h index b0375e5..f6090cd 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h @@ -1,39 +1,50 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + /*! \file Altera - ALT_SOCAL */ #ifndef __ALTERA_SOCAL_H__ #define __ALTERA_SOCAL_H__ -#include +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#include +#include +#include +#else /* __cplusplus */ +#include +#include +#include +#endif /* __cplusplus */ +#endif /* __ASSEMBLY__ */ #ifdef __cplusplus extern "C" @@ -61,7 +72,6 @@ extern "C" #define ALT_CAST(type, ptr) ((type) (ptr)) #endif /* __ASSEMBLY__ */ - /*! * \addtogroup ALT_SOCAL_UTIL_RW_FUNC SoCAL Memory Read/Write Utilities * @@ -239,117 +249,8 @@ extern "C" */ #define alt_replbits_dword(dest, msk, src) (alt_write_dword(dest,(alt_read_dword(dest) & ~(msk)) | ((src) & (msk)))) - - /*! @} */ -/*! - * \addtogroup ALT_SOCAL_TYPE_IND_FUNC SoCAL Indirect (pointer-based) Utilities - * - * This section implements two other useful forms of the alt_write_*() macros above that - * are preferable to use in some situations. These use an intermediate pointer (defined - * in the containing compile unit) to move data in an indirect manner. These compile to very - * tight ARM code, equivalent to the above versions. - * - * @{ - */ - -/*! Write the 8 bit byte to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to byte data - * \param src - 8 bit data value to write to memory - */ -#define alt_indwrite_byte(dest, tmptr, src) {(tmptr)=ALT_CAST(uint8_t*,(dest));(*ALT_CAST(volatile uint8_t*,(tmptr))=(src));} - -/*! Write the 8 bit byte to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to byte data - * \param src - Read destination pointer address - */ -#define alt_indread_byte(dest, tmptr, src) {(tmptr)=ALT_CAST(uint8_t*,(src));(*ALT_CAST(volatile uint8_t*,(dest))=*(tmptr));} - -/*! Write the 16 bit halfword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to halfword data - * \param src - 16 bit data value to write to memory - */ -#define alt_indwrite_hword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint16_t*,(dest));(*ALT_CAST(volatile uint16_t*,(tmptr))=(src));} - -/*! Write the 16 bit halfword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to halfword data - * \param src - Read destination pointer address - */ -#define alt_indread_hword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint16_t*,(src));(*ALT_CAST(volatile uint16_t*,(dest))=*(tmptr));} - -/*! Write the 32 bit word to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to word data - * \param src - 32 bit data value to write to memory - */ -#define alt_indwrite_word(dest, tmptr, src) {(tmptr)=ALT_CAST(uint32_t*,(dest));(*ALT_CAST(volatile uint32_t*,(tmptr))=(src));} - -/*! Write the 32 bit word to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to word data - * \param src - Read destination pointer address - */ -#define alt_indread_word(dest, tmptr, src) {(tmptr)=ALT_CAST(uint32_t*,(src));(*ALT_CAST(volatile uint32_t*,(dest))=*(tmptr));} - -/*! Write the 64 bit dword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to double-word data - * \param src - 64 bit data value to write to memory - */ -#define alt_indwrite_dword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint64_t*,(dest));(*ALT_CAST(volatile uint64_t*,(tmptr))=(src));} - -/*! Write the 64 bit dword to the destination address in device memory. - * \param dest - Write destination pointer address - * \param tmptr - Temporary pointer to double-word data - * \param src - Read destination pointer address - */ -#define alt_indread_dword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint64_t*,(src));(*ALT_CAST(volatile uint64_t*,(dest))=*(tmptr));} - - -/*! @} */ - -/*! - * \addtogroup ALT_SOCAL_CMPL_ASRT_FUNC SoCAL Compile Assert Utilities - * - * This section implements an assert-type functionality in the compiler rather than in the - * debug run-time code. Additional macros can be built on the basic structure and defined - * to test various conditions and throw a compile-time error if necessary. - * - * @{ - */ - -/*! alt_cat_compile_assert_text() concatenates text. - * \param txta - The first text fragment to be joined - * \param txtb - The second text fragment to be joined - */ -#define alt_cat_compile_assert_text(txta, txtb) txta##txtb - -/*! alt_form_compile_assert_line() is the basis of other functions that check various - * conditions and possibly throw a compile-time error in response, giving an - * assert equivalent that operates at compile time rather than at run-time. - * \param test - Any valid boolean expression - * \param file - The filename where this expression is located (ASCII string) - * \param line - The line number where this expression is located - */ -#define alt_form_compile_assert_line(test, file, line) \ -typedef char alt_cat_compile_assert_text(assertion_at_##file##_line_, line)[2*!!(test)-1] - -/*! alt_check_struct_size() throws a compile-time error if the structure size (a) is - * larger than the size of the reference (b). \n - * alt_check_struct_size() works with groups of bitfields up to much larger - * structure sizes. - * \param a - Structure to be evaluated - * \param b - Reference size - */ -#define alt_check_struct_size(a, b) RTEMS_STATIC_ASSERT((sizeof(a) <= sizeof(b)), Invalid_stuct_size) - - -/*! @} */ /*! @} */ #ifdef __cplusplus diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c index 43d7576..93b7f88 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c @@ -1,45 +1,49 @@ - /****************************************************************************** -* -* alt_address_space.c - API for the Altera SoC FPGA address space. -* -******************************************************************************/ + * + * alt_address_space.c - API for the Altera SoC FPGA address space. + * + ******************************************************************************/ /****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ #include #include "alt_address_space.h" #include "socal/alt_l3.h" #include "socal/socal.h" +#include "socal/alt_acpidmap.h" +#include "hwlib.h" + +#define ALT_ACP_ID_MAX_INPUT_ID 7 +#define ALT_ACP_ID_MAX_OUTPUT_ID 4096 /******************************************************************************/ ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, @@ -154,7 +158,7 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, { // Address filtering start and end values must be 1 MB aligned. if ( (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK) - || (addr_filt_end & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK) ) + || (addr_filt_end & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK) ) { return ALT_E_ARG_RANGE; } @@ -181,4 +185,325 @@ ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, } /******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser) +{ + if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + alt_write_word(ALT_ACPIDMAP_VID2RD_ADDR, + ALT_ACPIDMAP_VID2RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID2RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID2RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID2RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + alt_write_word(ALT_ACPIDMAP_VID3RD_ADDR, + ALT_ACPIDMAP_VID3RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID3RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID3RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID3RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + alt_write_word(ALT_ACPIDMAP_VID4RD_ADDR, + ALT_ACPIDMAP_VID4RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID4RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID4RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID4RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + alt_write_word(ALT_ACPIDMAP_VID5RD_ADDR, + ALT_ACPIDMAP_VID5RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID5RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID5RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID5RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + alt_write_word(ALT_ACPIDMAP_VID6RD_ADDR, + ALT_ACPIDMAP_VID6RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID6RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID6RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID6RD_FORCE_SET(1UL)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser) +{ + if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + alt_write_word(ALT_ACPIDMAP_VID2WR_ADDR, + ALT_ACPIDMAP_VID2WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID2WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID2WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID2WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + alt_write_word(ALT_ACPIDMAP_VID3WR_ADDR, + ALT_ACPIDMAP_VID3WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID3WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID3WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID3WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + alt_write_word(ALT_ACPIDMAP_VID4WR_ADDR, + ALT_ACPIDMAP_VID4WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID4WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID4WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID4WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + alt_write_word(ALT_ACPIDMAP_VID5WR_ADDR, + ALT_ACPIDMAP_VID5WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID5WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID5WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID5WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + alt_write_word(ALT_ACPIDMAP_VID6WR_ADDR, + ALT_ACPIDMAP_VID6WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID6WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID6WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID6WR_FORCE_SET(1UL) + ); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + uint32_t aruser, page; + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + aruser = ALT_ACPIDMAP_VID2RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR)); + page = ALT_ACPIDMAP_VID2RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + aruser = ALT_ACPIDMAP_VID3RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR)); + page = ALT_ACPIDMAP_VID3RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + aruser = ALT_ACPIDMAP_VID4RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR)); + page = ALT_ACPIDMAP_VID4RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + aruser = ALT_ACPIDMAP_VID5RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR)); + page = ALT_ACPIDMAP_VID5RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + aruser = ALT_ACPIDMAP_VID6RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR)); + page = ALT_ACPIDMAP_VID6RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR, + ALT_ACPIDMAP_DYNRD_PAGE_SET(page) + | ALT_ACPIDMAP_DYNRD_USER_SET(aruser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + uint32_t awuser, page; + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR)); + page = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR)); + page = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR)); + page = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR)); + page = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR)); + page = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR, + ALT_ACPIDMAP_DYNWR_PAGE_SET(page) + | ALT_ACPIDMAP_DYNWR_USER_SET(awuser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser) +{ + alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR, + ALT_ACPIDMAP_DYNRD_PAGE_SET(page) + | ALT_ACPIDMAP_DYNRD_USER_SET(aruser)); + return ALT_E_SUCCESS; +} + /******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser) +{ + alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR, + ALT_ACPIDMAP_DYNWR_PAGE_SET(page) + | ALT_ACPIDMAP_DYNWR_USER_SET(awuser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, + bool * fixed, + uint32_t * input_id, + ALT_ACP_ID_MAP_PAGE_t * page, + uint32_t * aruser) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + *aruser = ALT_ACPIDMAP_VID2RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID2RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID2RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + *aruser = ALT_ACPIDMAP_VID3RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID3RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID3RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + *aruser = ALT_ACPIDMAP_VID4RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID4RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID4RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + *aruser = ALT_ACPIDMAP_VID5RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID5RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID5RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + *aruser = ALT_ACPIDMAP_VID6RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID6RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID6RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_7: + *aruser = ALT_ACPIDMAP_DYNRD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNRD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, + bool * fixed, + uint32_t * input_id, + ALT_ACP_ID_MAP_PAGE_t * page, + uint32_t * awuser) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + *awuser = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + *awuser = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + *awuser = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + *awuser = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + *awuser = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_7: + *awuser = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c index c731ad3..1291243 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c @@ -1,46 +1,44 @@ /****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - - -#include -#include -#include -#include -#include - -#include "socal/hps.h" -#include "socal/socal.h" -#include "socal/alt_sysmgr.h" -#include "hwlib.h" -#include "alt_clock_manager.h" -#include "alt_mpu_registers.h" + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include +#include +#include +#include + +#include "socal/hps.h" +#include "socal/socal.h" +#include "socal/alt_sysmgr.h" +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "alt_mpu_registers.h" #define UINT12_MAX (4096) @@ -77,10 +75,13 @@ typedef struct ALT_EXT_CLK_PARAMBLOK_s /* contains the current activity state of the clock, 1=active, 0=inactive. */ /* Values taken from Section 2.3 and Section 2.7.1 of the HHP HPS-Clocking */ /* NPP specification. */ -static ALT_EXT_CLK_PARAMBLOK_t alt_ext_clk_paramblok = {{25000000, 10000000, 50000000, 0, 1}, - {25000000, 10000000, 50000000, 0, 1}, - {0, 10000000, 50000000, 0, 1}, - {0, 10000000, 50000000, 0, 1}}; +static ALT_EXT_CLK_PARAMBLOK_t alt_ext_clk_paramblok = +{ + { 25000000, 10000000, 50000000, 0, 1 }, + { 25000000, 10000000, 50000000, 0, 1 }, + { 0, 10000000, 50000000, 0, 1 }, + { 0, 10000000, 50000000, 0, 1 } +}; /* PLL frequency limits */ @@ -104,12 +105,15 @@ typedef struct ALT_PLL_CLK_PARAMBLOK_s #define ALT_ORIGINAL_GUARDBAND_VAL 20 #define ALT_GUARDBAND_LIMIT 20 -static ALT_PLL_CLK_PARAMBLOK_t alt_pll_clk_paramblok = {{0, 320000000, 1200000000, ALT_ORIGINAL_GUARDBAND_VAL, 0}, - {0, 320000000, 900000000, ALT_ORIGINAL_GUARDBAND_VAL, 0}, - {0, 320000000, 800000000, ALT_ORIGINAL_GUARDBAND_VAL, 0}, - {0, 320000000, 1600000000, ALT_ORIGINAL_GUARDBAND_VAL, 1}, - {0, 320000000, 1250000000, ALT_ORIGINAL_GUARDBAND_VAL, 1}, - {0, 320000000, 1066000000, ALT_ORIGINAL_GUARDBAND_VAL, 1}}; +static ALT_PLL_CLK_PARAMBLOK_t alt_pll_clk_paramblok = +{ + { 0, 320000000, 1200000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 900000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 800000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 1600000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 }, + { 0, 320000000, 1250000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 }, + { 0, 320000000, 1066000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 } +}; /* PLL counter frequency limits */ @@ -133,25 +137,69 @@ typedef struct ALT_PLL_CNTR_FREQMAX_s alt_freq_t SDRAMPLL_C5; // SDRAM PLL Counter 5 parameter block } ALT_PLL_CNTR_FREQMAX_t; +// +// The following pll max frequency array statically defined must be recalculated each time +// when powering up, by calling alt_clk_clkmgr_init() +// +// for 14.1 uboot preloader, the following values are calculated dynamically. +// +// Arrial 5 +// alt_pll_cntr_maxfreq.MainPLL_C0 = 1050000000 +// alt_pll_cntr_maxfreq.MainPLL_C1 = 350000000 +// alt_pll_cntr_maxfreq.MainPLL_C2 = 262500000 +// alt_pll_cntr_maxfreq.MainPLL_C3 = 350000000 +// alt_pll_cntr_maxfreq.MainPLL_C4 = 2050781 +// alt_pll_cntr_maxfreq.MainPLL_C5 = 116666666 +// alt_pll_cntr_maxfreq.PeriphPLL_C0 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C1 = 250000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C2 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C3 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C4 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C5 = 1953125 +// alt_pll_cntr_maxfreq.SDRAMPLL_C0 = 533333333 +// alt_pll_cntr_maxfreq.SDRAMPLL_C1 = 1066666666 +// alt_pll_cntr_maxfreq.SDRAMPLL_C2 = 533333333 +// alt_pll_cntr_maxfreq.SDRAMPLL_C5 = 177777777 + +// Cyclone V +// alt_pll_cntr_maxfreq.MainPLL_C0 = 925000000 +// alt_pll_cntr_maxfreq.MainPLL_C1 = 370000000 +// alt_pll_cntr_maxfreq.MainPLL_C2 = 462500000 +// alt_pll_cntr_maxfreq.MainPLL_C3 = 370000000 +// alt_pll_cntr_maxfreq.MainPLL_C4 = 3613281 +// alt_pll_cntr_maxfreq.MainPLL_C5 = 123333333 +// alt_pll_cntr_maxfreq.PeriphPLL_C0 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C1 = 250000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C2 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C3 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C4 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C5 = 1953125 +// alt_pll_cntr_maxfreq.SDRAMPLL_C0 = 400000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C1 = 800000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C2 = 400000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C5 = 133333333 /* Initializes the PLL Counter output maximum frequency block */ -static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = {800000000, /* Main PLL Outputs */ - 400000000, - 400000000, - 432000000, - 250000000, - 125000000, - 250000000, /* Peripheral PLL Outputs */ - 250000000, - 432000000, - 250000000, - 200000000, - 100000000, /* SDRAM PLL Outputs */ - 533000000, - 1066000000, - 533000000, - 200000000 }; +static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = +{ + 800000000, /* Main PLL Outputs */ + 400000000, + 400000000, + 432000000, + 250000000, + 125000000, + 250000000, /* Peripheral PLL Outputs */ + 250000000, + 432000000, + 250000000, + 200000000, + 100000000, /* SDRAM PLL Outputs */ + 533000000, + 1066000000, + 533000000, + 200000000 +}; @@ -181,6 +229,18 @@ static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = {800000000, /* Main PLL & ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK) +// Undocumented register which determines clock dividers for main PLL C0, C1, and C2. These should be considered RO. +#define ALT_CLKMGR_ALTERA_OFST 0xe0 +#define ALT_CLKMGR_ALTERA_MPUCLK_OFST 0x0 +#define ALT_CLKMGR_ALTERA_MAINCLK_OFST 0x4 +#define ALT_CLKMGR_ALTERA_DBGATCLK_OFST 0x8 +#define ALT_CLKMGR_ALTERA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_ALTERA_OFST)) +#define ALT_CLKMGR_ALTERA_MPUCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_MPUCLK_OFST)) +#define ALT_CLKMGR_ALTERA_MAINCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_MAINCLK_OFST)) +#define ALT_CLKMGR_ALTERA_DBGATCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_DBGATCLK_OFST)) +#define ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +#define ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +#define ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Utility functions ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ @@ -199,7 +259,7 @@ static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = {800000000, /* Main PLL /* minimum osc1 clock cycle delay. */ /****************************************************************************************/ -static void inline alt_clk_mgr_wait(void* reg, uint32_t cnt) +inline static void alt_clk_mgr_wait(void* reg, uint32_t cnt) { for (; cnt ; cnt--) { @@ -207,7 +267,6 @@ static void inline alt_clk_mgr_wait(void* reg, uint32_t cnt) } } - /* Wait time constants */ /* These values came from Section 4.9.4 of the HHP HPS-Clocking NPP document */ #define ALT_SW_MANAGED_CLK_WAIT_CTRDIV 30 /* 30 or more MPU clock cycles */ @@ -224,8 +283,7 @@ static void inline alt_clk_mgr_wait(void* reg, uint32_t cnt) // how many loops to wait for the SDRAM clock to come around // to zero and allow for writing a new divisor ratio to it - -static ALT_STATUS_CODE alt_clk_plls_settle_wait(void) +ALT_STATUS_CODE alt_clk_plls_settle_wait(void) { int32_t i = ALT_BYPASS_TIMEOUT_CNT; bool nofini; @@ -238,26 +296,30 @@ static ALT_STATUS_CODE alt_clk_plls_settle_wait(void) return (i > 0) ? ALT_E_SUCCESS : ALT_E_ERROR; } - - -static ALT_STATUS_CODE alt_clk_pll_lock_wait(ALT_CLK_t pll, uint32_t cnt) +static ALT_STATUS_CODE alt_clk_pll_lock_wait(ALT_CLK_t pll, uint32_t timeout) { - ALT_STATUS_CODE ret = ALT_E_ERROR; - uint32_t temp; - uint32_t mask = 0; + uint32_t locked_mask = 0; + + if (pll == ALT_CLK_MAIN_PLL) { locked_mask = ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK; } + else if (pll == ALT_CLK_PERIPHERAL_PLL) { locked_mask = ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK; } + else if (pll == ALT_CLK_SDRAM_PLL) { locked_mask = ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK; } + else + { + return ALT_E_BAD_ARG; + } - if (pll == ALT_CLK_MAIN_PLL) { mask = ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK; } - else if (pll == ALT_CLK_PERIPHERAL_PLL) { mask = ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK; } - else if (pll == ALT_CLK_SDRAM_PLL) { mask = ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK; } - else { return ret; } do { - temp = alt_read_word(ALT_CLKMGR_INTER_ADDR); - } while (!(temp & mask) && --cnt); - if (cnt > 0) { ret = ALT_E_SUCCESS; } - return ret; -} + uint32_t int_status = alt_read_word(ALT_CLKMGR_INTER_ADDR); + if (int_status & locked_mask) + { + return ALT_E_SUCCESS; + } + + } while (timeout--); + return ALT_E_TMO; +} /* Useful utility macro for checking if two values */ /* are within a certain percentage of each other */ @@ -321,25 +383,23 @@ static void alt_clk_pllcounter_write(void* vcoaddr, void* stataddr, void* cntrad /* conditions. */ /****************************************************************************************/ - ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) +ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) { - ALT_STATUS_CODE ret; - - if (lock_stat_mask & (ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK - & ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK - & ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK - & ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK - & ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK - & ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK)) + if (lock_stat_mask & ( ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK + & ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK + & ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK) + ) { - ret = ALT_E_BAD_ARG; + return ALT_E_BAD_ARG; } else { alt_setbits_word(ALT_CLKMGR_INTER_ADDR, lock_stat_mask); - ret = ALT_E_SUCCESS; + return ALT_E_SUCCESS; } - return ret; } @@ -349,15 +409,15 @@ static void alt_clk_pllcounter_write(void* vcoaddr, void* stataddr, void* cntrad uint32_t alt_clk_lock_status_get(void) { - return alt_read_word(ALT_CLKMGR_INTER_ADDR) & (ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK - | ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK - | ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK - | ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK - | ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK - | ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK - | ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK - | ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK - | ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK ); + return alt_read_word(ALT_CLKMGR_INTER_ADDR) & ( ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK + | ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK ); } @@ -368,24 +428,24 @@ uint32_t alt_clk_lock_status_get(void) ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; if (pll == ALT_CLK_MAIN_PLL) { - ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK) + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_PERIPHERAL_PLL) { - ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK) + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_SDRAM_PLL) { - ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK) + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK) ? ALT_E_TRUE : ALT_E_FALSE; } - return ret; + return status; } @@ -396,7 +456,7 @@ ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll) ALT_STATUS_CODE alt_clk_safe_mode_clear(void) { - ALT_STATUS_CODE ret = ALT_E_ERROR; + ALT_STATUS_CODE status = ALT_E_ERROR; #if ALT_PREVENT_GLITCH_EXSAFE uint32_t temp; @@ -407,7 +467,7 @@ ALT_STATUS_CODE alt_clk_safe_mode_clear(void) alt_setbits_word(ALT_CLKMGR_CTL_ADDR, ALT_CLKMGR_CTL_SAFEMOD_SET_MSK); // clear safe mode bit - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); alt_replbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK, temp); @@ -416,10 +476,10 @@ ALT_STATUS_CODE alt_clk_safe_mode_clear(void) #else alt_setbits_word(ALT_CLKMGR_CTL_ADDR, ALT_CLKMGR_CTL_SAFEMOD_SET_MSK); // clear safe mode bit - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #endif - return ret; + return status; } @@ -463,12 +523,12 @@ bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain) ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + uint32_t temp; #if ALT_PREVENT_GLITCH_BYP - uint32_t temp1; - bool restore_0 = false; - bool restore_1 = false; + uint32_t temp1; + bool restore_0 = false; + bool restore_1 = false; #endif // this function should only be called after the selected PLL is locked @@ -479,20 +539,20 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) #if ALT_PREVENT_GLITCH_BYP // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) { - restore_0 = true; + restore_0 = true; } if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) { - restore_1 = true; + restore_1 = true; } temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } #endif @@ -507,7 +567,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) // remove bypass alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #if ALT_PREVENT_GLITCH_BYP if (restore_0 || restore_1) @@ -551,7 +611,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) // remove bypass - don't think that there's any need to touch the bypass clock source alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_PERPLL_SET_MSK); - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #if ALT_PREVENT_GLITCH_BYP if (restore_0 || restore_1) @@ -575,12 +635,15 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) // remove bypass - don't think that there's any need to touch the bypass clock source alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK); - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); } } - else { ret = ALT_E_ERROR; } + else + { + status = ALT_E_ERROR; + } - return ret; + return status; } @@ -590,12 +653,12 @@ ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + uint32_t temp; #ifdef ALT_PREVENT_GLITCH_BYP - uint32_t temp1; - bool restore_0 = false; - bool restore_1 = false; + uint32_t temp1; + bool restore_0 = false; + bool restore_1 = false; #endif if (pll == ALT_CLK_MAIN_PLL) @@ -605,59 +668,61 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) #ifdef ALT_PREVENT_GLITCH_BYP // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) { - restore_0 = true; + restore_0 = true; } if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) { - restore_1 = true; + restore_1 = true; } temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } alt_setbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); // no input mux select on main PLL - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); // wait before reenabling the L4MP and L4SP clocks if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } #else alt_setbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); // no input mux select on main PLL - ret = alt_clk_plls_settle_wait(); + status = alt_clk_plls_settle_wait(); #endif - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_BAD_ARG; } - else { ret = ALT_E_BAD_ARG; } } - else if (pll == ALT_CLK_PERIPHERAL_PLL) { #ifdef ALT_PREVENT_GLITCH_BYP // if L4MP or L4SP source is set to Peripheral PLL C1, gate it off before changing // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK)) { - restore_0 = true; + restore_0 = true; } if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK)) { - restore_1 = true; + restore_1 = true; } temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } temp = alt_read_word(ALT_CLKMGR_BYPASS_ADDR) & @@ -678,7 +743,7 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK : ALT_CLKMGR_BYPASS_PERPLL_SET_MSK; // set bypass bit and optionally the source select bit #endif - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; } else if (pll == ALT_CLK_SDRAM_PLL) @@ -689,9 +754,9 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK : ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK; // set bypass bit and optionally the source select bit alt_write_word(ALT_CLKMGR_BYPASS_ADDR, temp); - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; } - return ret; + return status; } @@ -706,27 +771,27 @@ ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; if (pll == ALT_CLK_MAIN_PLL) { - ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) || ALT_CLKMGR_BYPASS_MAINPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_PERIPHERAL_PLL) { - ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) || ALT_CLKMGR_BYPASS_PERPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) ? ALT_E_TRUE : ALT_E_FALSE; } else if (pll == ALT_CLK_SDRAM_PLL) { - ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) || ALT_CLKMGR_BYPASS_SDRPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) ? ALT_E_TRUE : ALT_E_FALSE; } - return ret; + return status; } @@ -734,9 +799,9 @@ ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll) /* alt_clk_pll_source_get() returns the current input of the specified PLL. */ /****************************************************************************************/ -static ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) +ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) { - ALT_CLK_t ret = ALT_CLK_UNKNOWN; + ALT_CLK_t ret = ALT_CLK_UNKNOWN; uint32_t temp; @@ -777,962 +842,920 @@ static ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) { ret = ALT_CLK_F2H_SDRAM_REF; } - } + } return ret; } - -/****************************************************************************************/ -/* alt_clk_clock_disable() disables the specified clock. Once the clock is disabled, */ -/* its clock signal does not propagate to its clocked elements. */ -/****************************************************************************************/ - +// +// alt_clk_clock_disable() disables the specified clock. Once the clock is disabled, +// its clock signal does not propagate to its clocked elements. +// ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_SUCCESS; switch (clk) { - /* For PLLs, put them in bypass mode */ - case (ALT_CLK_MAIN_PLL): - case (ALT_CLK_PERIPHERAL_PLL): - case (ALT_CLK_SDRAM_PLL): - ret = alt_clk_pll_bypass_enable(clk, false); - break; - - /* Clocks that originate at the Main PLL */ - case (ALT_CLK_L4_MAIN): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L3_MP): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_MP): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_SP): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_AT): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TRACE): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TIMER): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CFG): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER0): - alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - /* Clocks that originate at the Peripheral PLL */ - case (ALT_CLK_EMAC0): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_EMAC1): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_USB_MP): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SPI_M): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN0): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN1): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_GPIO_DB): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER1): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SDMMC): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND_X): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - // gate nand_clk off before nand_x_clk - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - ret = ALT_E_SUCCESS; + // For PLLs, put them in bypass mode. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = alt_clk_pll_bypass_enable(clk, false); break; - case (ALT_CLK_QSPI): - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - /* Clocks that originate at the SDRAM PLL */ - case (ALT_CLK_DDR_DQS): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DDR_2X_DQS): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - case (ALT_CLK_DDR_DQ): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); + break; + case ALT_CLK_L3_MP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); + break; + case ALT_CLK_L4_MP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + break; + case ALT_CLK_L4_SP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + break; + case ALT_CLK_DBG_AT: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); + break; + case ALT_CLK_DBG: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); + break; + case ALT_CLK_DBG_TRACE: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); + break; + case ALT_CLK_DBG_TIMER: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); + break; + case ALT_CLK_CFG: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER0: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); + break; - case (ALT_CLK_H2F_USER2): - alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); + break; + case ALT_CLK_EMAC1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); + break; + case ALT_CLK_USB_MP: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); + break; + case ALT_CLK_SPI_M: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); + break; + case ALT_CLK_CAN0: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); + break; + case ALT_CLK_CAN1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); + break; + case ALT_CLK_GPIO_DB: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); + break; + case ALT_CLK_SDMMC: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + break; + case ALT_CLK_NAND_X: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_clk off before nand_x_clk. + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + break; + case ALT_CLK_NAND: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + break; + case ALT_CLK_QSPI: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + break; - default: - break; + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_2X_DQS: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_DQ: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER2: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); + break; + default: + status = ALT_E_BAD_ARG; + break; } - return ret; -} - -/****************************************************************************************/ -/* alt_clk_clock_enable() enables the specified clock. Once the clock is enabled, its */ -/* clock signal propagates to its elements. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_clock_enable() enables the specified clock. Once the clock is enabled, its +// clock signal propagates to its elements. +// ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_SUCCESS; switch (clk) { - /* For PLLs, take them out of bypass mode */ - case (ALT_CLK_MAIN_PLL): - case (ALT_CLK_PERIPHERAL_PLL): - case (ALT_CLK_SDRAM_PLL): - ret = alt_clk_pll_bypass_disable(clk); - break; - - - /* Clocks that originate at the Main PLL */ - case (ALT_CLK_L4_MAIN): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L3_MP): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_MP): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_L4_SP): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_AT): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TRACE): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_DBG_TIMER): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CFG): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER0): - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - - /* Clocks that originate at the Peripheral PLL */ - case (ALT_CLK_EMAC0): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_EMAC1): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_USB_MP): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SPI_M): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN0): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_CAN1): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_GPIO_DB): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_H2F_USER1): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_SDMMC): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND_X): - // implementation detail - should ALK_CLK_NAND be gated off here before enabling ALT_CLK_NAND_X? - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - // implementation detail - should this wait be enforced here? - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_NAND): - // enabling ALT_CLK_NAND always implies enabling ALT_CLK_NAND_X first - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - // gate nand_x_clk on at least 8 MCU clocks before nand_clk - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; - case (ALT_CLK_QSPI): - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // For PLLs, take them out of bypass mode. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = alt_clk_pll_bypass_disable(clk); + break; - /* Clocks that originate at the SDRAM PLL */ - case (ALT_CLK_DDR_DQS): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); + break; + case ALT_CLK_L3_MP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); + break; + case ALT_CLK_L4_MP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + break; + case ALT_CLK_L4_SP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + break; + case ALT_CLK_DBG_AT: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); + break; + case ALT_CLK_DBG: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); + break; + case ALT_CLK_DBG_TRACE: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); + break; + case ALT_CLK_DBG_TIMER: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); + break; + case ALT_CLK_CFG: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER0: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); + break; - case (ALT_CLK_DDR_2X_DQS): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); + break; + case ALT_CLK_EMAC1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); + break; + case ALT_CLK_USB_MP: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); + break; + case ALT_CLK_SPI_M: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); + break; + case ALT_CLK_CAN0: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); + break; + case ALT_CLK_CAN1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); + break; + case ALT_CLK_GPIO_DB: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); + break; + case ALT_CLK_SDMMC: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + break; + case ALT_CLK_NAND_X: + // implementation detail - should ALK_CLK_NAND be gated off here before enabling ALT_CLK_NAND_X? + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + // implementation detail - should this wait be enforced here? + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + break; + case ALT_CLK_NAND: + // enabling ALT_CLK_NAND always implies enabling ALT_CLK_NAND_X first + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_x_clk on at least 8 MCU clocks before nand_clk + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + break; + case ALT_CLK_QSPI: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + break; - case (ALT_CLK_DDR_DQ): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_2X_DQS: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_DQ: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER2: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); + break; - case (ALT_CLK_H2F_USER2): - alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); - ret = ALT_E_SUCCESS; - break; + default: + status = ALT_E_BAD_ARG; + break; + } - default: break; - } - return ret; + return status; } - -/****************************************************************************************/ -/* alt_clk_is_enabled() returns whether the specified clock is enabled or not. */ -/****************************************************************************************/ - +// +// alt_clk_is_enabled() returns whether the specified clock is enabled or not. +// ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - - switch (clk) // this should be more than enough cases to cause - { // the compiler to use a jump table implementation + ALT_STATUS_CODE status = ALT_E_BAD_ARG; - /* For PLLs, this function checks if the PLL is bypassed or not */ - case (ALT_CLK_MAIN_PLL): - case (ALT_CLK_PERIPHERAL_PLL): - case (ALT_CLK_SDRAM_PLL): - ret = (alt_clk_pll_is_bypassed(clk) != ALT_E_TRUE); - break; + switch (clk) + { + // For PLLs, this function checks if the PLL is bypassed or not. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = (alt_clk_pll_is_bypassed(clk) != ALT_E_TRUE); + break; - /* These clocks are not gated, so must return a ALT_E_BAD_ARG type error */ - case (ALT_CLK_MAIN_PLL_C0): - case (ALT_CLK_MAIN_PLL_C1): - case (ALT_CLK_MAIN_PLL_C2): - case (ALT_CLK_MAIN_PLL_C3): - case (ALT_CLK_MAIN_PLL_C4): - case (ALT_CLK_MAIN_PLL_C5): - case (ALT_CLK_MPU): - case (ALT_CLK_MPU_L2_RAM): - case (ALT_CLK_MPU_PERIPH): - case (ALT_CLK_L3_MAIN): - case (ALT_CLK_L3_SP): - case (ALT_CLK_DBG_BASE): - case (ALT_CLK_MAIN_QSPI): - case (ALT_CLK_MAIN_NAND_SDMMC): - case (ALT_CLK_PERIPHERAL_PLL_C0): - case (ALT_CLK_PERIPHERAL_PLL_C1): - case (ALT_CLK_PERIPHERAL_PLL_C2): - case (ALT_CLK_PERIPHERAL_PLL_C3): - case (ALT_CLK_PERIPHERAL_PLL_C4): - case (ALT_CLK_PERIPHERAL_PLL_C5): - case (ALT_CLK_SDRAM_PLL_C0): - case (ALT_CLK_SDRAM_PLL_C1): - case (ALT_CLK_SDRAM_PLL_C2): - case (ALT_CLK_SDRAM_PLL_C5): - ret = ALT_E_BAD_ARG; - break; + // These clocks are not gated, so must return a ALT_E_BAD_ARG type error. + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_MPU: + case ALT_CLK_MPU_L2_RAM: + case ALT_CLK_MPU_PERIPH: + case ALT_CLK_L3_MAIN: + case ALT_CLK_L3_SP: + case ALT_CLK_DBG_BASE: + case ALT_CLK_MAIN_QSPI: + case ALT_CLK_MAIN_NAND_SDMMC: + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_SDRAM_PLL_C5: + status = ALT_E_BAD_ARG; + break; - /* Clocks that originate at the Main PLL */ - case (ALT_CLK_L4_MAIN): - ret = (ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_L3_MP): - ret = (ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_L4_MP): - ret = (ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_L4_SP): - ret = (ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG_AT): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG_TRACE): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DBG_TIMER): - ret = (ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_CFG): - ret = (ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_H2F_USER0): - ret = (ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + status = (ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L3_MP: + status = (ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L4_MP: + status = (ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L4_SP: + status = (ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_AT: + status = (ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG: + status = (ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_TRACE: + status = (ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_TIMER: + status = (ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CFG: + status = (ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER0: + status = (ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - /* Clocks that originate at the Peripheral PLL */ - case (ALT_CLK_EMAC0): - ret = (ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_EMAC1): - ret = (ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_USB_MP): - ret = (ALT_CLKMGR_PERPLL_EN_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_SPI_M): - ret = (ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_CAN0): - ret = (ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_CAN1): - ret = (ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_GPIO_DB): - ret = (ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_H2F_USER1): - ret = (ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + status = (ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_EMAC1: + status = (ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_USB_MP: + status = (ALT_CLKMGR_PERPLL_EN_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_SPI_M: + status = (ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CAN0: + status = (ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CAN1: + status = (ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_GPIO_DB: + status = (ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER1: + status = (ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - /* Clocks that may originate at the Main PLL, the Peripheral PLL, or the FPGA */ - case (ALT_CLK_SDMMC): - ret = (ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_NAND_X): - ret = (ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_NAND): - ret = (ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_QSPI): - ret = (ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that may originate at the Main PLL, the Peripheral PLL, or the FPGA. + case ALT_CLK_SDMMC: + status = (ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_NAND_X: + status = (ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_NAND: + status = (ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_QSPI: + status = (ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - /* Clocks that originate at the SDRAM PLL */ - case (ALT_CLK_DDR_DQS): - ret = (ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DDR_2X_DQS): - ret = (ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_DDR_DQ): - ret = (ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; - case (ALT_CLK_H2F_USER2): - ret = (ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) - ? ALT_E_TRUE : ALT_E_FALSE; - break; + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + status = (ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DDR_2X_DQS: + status = (ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DDR_DQ: + status = (ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER2: + status = (ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; - default: - break; + default: + status = ALT_E_BAD_ARG; + break; } - return ret; -} - -/****************************************************************************************/ -/* alt_clk_source_get() gets the input reference clock source selection value for the */ -/* specified clock or PLL. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_source_get() gets the input reference clock source selection value for the +// specified clock or PLL. +// ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk) { - ALT_CLK_t ret = ALT_CLK_UNKNOWN; - uint32_t temp; + ALT_CLK_t ret = ALT_CLK_UNKNOWN; + uint32_t temp; switch (clk) { - /* Potential external clock sources */ - case ALT_CLK_IN_PIN_OSC1: - case ALT_CLK_IN_PIN_OSC2: - case ALT_CLK_F2H_PERIPH_REF: - case ALT_CLK_F2H_SDRAM_REF: - case ALT_CLK_IN_PIN_JTAG: - case ALT_CLK_IN_PIN_ULPI0: - case ALT_CLK_IN_PIN_ULPI1: - case ALT_CLK_IN_PIN_EMAC0_RX: - case ALT_CLK_IN_PIN_EMAC1_RX: - ret = clk; - break; // these clock entities are their own source - - /* Phase-Locked Loops */ - case ALT_CLK_MAIN_PLL: - case ALT_CLK_OSC1: - ret = ALT_CLK_IN_PIN_OSC1; - break; - case ALT_CLK_PERIPHERAL_PLL: - ret = alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL); - break; - case ALT_CLK_SDRAM_PLL: - ret = alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL); - break; + // Potential external clock sources. + // these clock entities are their own source + case ALT_CLK_IN_PIN_OSC1: + case ALT_CLK_IN_PIN_OSC2: + case ALT_CLK_F2H_PERIPH_REF: + case ALT_CLK_F2H_SDRAM_REF: + case ALT_CLK_IN_PIN_JTAG: + case ALT_CLK_IN_PIN_ULPI0: + case ALT_CLK_IN_PIN_ULPI1: + case ALT_CLK_IN_PIN_EMAC0_RX: + case ALT_CLK_IN_PIN_EMAC1_RX: + ret = clk; + break; - /* Main Clock Group */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_MAIN_PLL_C3: - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_PLL_C5: - // check bypass, return either osc1 or PLL ID - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL; - break; + // Phase-Locked Loops. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_OSC1: + ret = ALT_CLK_IN_PIN_OSC1; + break; + case ALT_CLK_PERIPHERAL_PLL: + ret = alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL); + break; + case ALT_CLK_SDRAM_PLL: + ret = alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL); + break; + + // Main Clock Group. + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + // check bypass, return either osc1 or PLL ID + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL; + break; + + case ALT_CLK_MPU_PERIPH: + case ALT_CLK_MPU_L2_RAM: + case ALT_CLK_MPU: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C0; + break; + + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + case ALT_CLK_L3_MP: + case ALT_CLK_L3_SP: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + break; - case ALT_CLK_MPU_PERIPH: - case ALT_CLK_MPU_L2_RAM: - case ALT_CLK_MPU: + case ALT_CLK_L4_MP: + // read the state of the L4_mp source bit + if ((ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) + == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C0; - break; + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + } + else + { + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + } + break; - case ALT_CLK_L4_MAIN: - case ALT_CLK_L3_MAIN: - case ALT_CLK_L3_MP: - case ALT_CLK_L3_SP: + case ALT_CLK_L4_SP: + // read the state of the source bit + if ((ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) + == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; - break; + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + } + else + { + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + } + break; - case ALT_CLK_L4_MP: - // read the state of the L4_mp source bit - if ((ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) - == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; - } - else - { - // if the clock comes from periph_base_clk - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; - } - break; + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_AT: + case ALT_CLK_DBG_TRACE: + case ALT_CLK_DBG_TIMER: + case ALT_CLK_DBG: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C2; + break; + case ALT_CLK_MAIN_QSPI: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C3; + break; + case ALT_CLK_MAIN_NAND_SDMMC: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C4; + break; + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C5; + break; - case ALT_CLK_L4_SP: - // read the state of the source bit - if ((ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) - == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; - } - else - { - // if the clock comes from periph_base_clk - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; - } - break; + // Peripherals Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL; + break; - case ALT_CLK_DBG_BASE: - case ALT_CLK_DBG_AT: - case ALT_CLK_DBG_TRACE: - case ALT_CLK_DBG_TIMER: - case ALT_CLK_DBG: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C2; - break; - case ALT_CLK_MAIN_QSPI: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C3; - break; - case ALT_CLK_MAIN_NAND_SDMMC: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C4; - break; - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C5; - break; + case ALT_CLK_EMAC0: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C0; + break; - /* Peripherals Clock Group */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_PERIPHERAL_PLL_C2: - case ALT_CLK_PERIPHERAL_PLL_C3: - case ALT_CLK_PERIPHERAL_PLL_C4: - case ALT_CLK_PERIPHERAL_PLL_C5: - // if the clock comes from periph_base_clk - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL; - break; + case ALT_CLK_EMAC1: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C1; + break; - case ALT_CLK_EMAC0: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C0; - break; + case ALT_CLK_USB_MP: + case ALT_CLK_SPI_M: + case ALT_CLK_CAN0: + case ALT_CLK_CAN1: + case ALT_CLK_GPIO_DB: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + break; - case ALT_CLK_EMAC1: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C1; - break; + case ALT_CLK_H2F_USER1: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C5; + break; - case ALT_CLK_USB_MP: - case ALT_CLK_SPI_M: - case ALT_CLK_CAN0: - case ALT_CLK_CAN1: - case ALT_CLK_GPIO_DB: + case ALT_CLK_SDMMC: + temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; - break; + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; + } + break; - case ALT_CLK_H2F_USER1: + case ALT_CLK_NAND_X: + case ALT_CLK_NAND: + temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) + { ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C5; - break; - - case ALT_CLK_SDMMC: - temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) - { - ret = ALT_CLK_F2H_PERIPH_REF; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; - } - break; + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; + } + break; - case ALT_CLK_NAND_X: - case ALT_CLK_NAND: - temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) - { - ret = ALT_CLK_F2H_PERIPH_REF; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; - } - break; + case ALT_CLK_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C3; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C2; + } + break; - case ALT_CLK_QSPI: - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) - { - ret = ALT_CLK_F2H_PERIPH_REF; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? - ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C3; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C2; - } - break; + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_SDRAM_PLL_C3: + case ALT_CLK_SDRAM_PLL_C4: + case ALT_CLK_SDRAM_PLL_C5: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL; + break; + case ALT_CLK_DDR_DQS: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C0; + break; + case ALT_CLK_DDR_2X_DQS: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C1; + break; + case ALT_CLK_DDR_DQ: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C2; + break; + case ALT_CLK_H2F_USER2: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C5; + break; - /* SDRAM Clock Group */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_SDRAM_PLL_C3: - case ALT_CLK_SDRAM_PLL_C4: - case ALT_CLK_SDRAM_PLL_C5: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL; - break; - case ALT_CLK_DDR_DQS: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C0; - break; - case ALT_CLK_DDR_2X_DQS: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C1; - break; - case ALT_CLK_DDR_DQ: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C2; - break; - case ALT_CLK_H2F_USER2: - ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? - alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C5; - break; + // Clock Output Pins + case ALT_CLK_OUT_PIN_EMAC0_TX: + case ALT_CLK_OUT_PIN_EMAC1_TX: + case ALT_CLK_OUT_PIN_SDMMC: + case ALT_CLK_OUT_PIN_I2C0_SCL: + case ALT_CLK_OUT_PIN_I2C1_SCL: + case ALT_CLK_OUT_PIN_I2C2_SCL: + case ALT_CLK_OUT_PIN_I2C3_SCL: + case ALT_CLK_OUT_PIN_SPIM0: + case ALT_CLK_OUT_PIN_SPIM1: + case ALT_CLK_OUT_PIN_QSPI: + ret = ALT_CLK_UNKNOWN; + break; - /* Clock Output Pins */ - case ALT_CLK_OUT_PIN_EMAC0_TX: - case ALT_CLK_OUT_PIN_EMAC1_TX: - case ALT_CLK_OUT_PIN_SDMMC: - case ALT_CLK_OUT_PIN_I2C0_SCL: - case ALT_CLK_OUT_PIN_I2C1_SCL: - case ALT_CLK_OUT_PIN_I2C2_SCL: - case ALT_CLK_OUT_PIN_I2C3_SCL: - case ALT_CLK_OUT_PIN_SPIM0: - case ALT_CLK_OUT_PIN_SPIM1: - case ALT_CLK_OUT_PIN_QSPI: - ret = ALT_CLK_UNKNOWN; - break; + default: + ret = ALT_CLK_UNKNOWN; + break; + } - default: - break; - } /* end big switch/case construct */ return ret; } - -/****************************************************************************************/ -/* alt_clk_source_set() sets the specified clock's input reference clock source */ -/* selection to the specified input. It does not handle gating the specified clock */ -/* off and back on, those are covered in other functions in this API, but it does */ -/* verify that the clock is off before changing the divider or PLL. Note that the PLL */ -/* must have regained phase-lock before being the bypass is disabled. */ -/****************************************************************************************/ - -ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk) +// +// alt_clk_source_set() sets the specified clock's input reference clock source +// selection to the specified input. It does not handle gating the specified clock +// off and back on, those are covered in other functions in this API, but it does +// verify that the clock is off before changing the divider or PLL. Note that the PLL +// must have regained phase-lock before being the bypass is disabled. +// +ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; if (ALT_CLK_MAIN_PLL == clk) { - if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) { ret = ALT_E_SUCCESS; } + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) + { + // ret = ALT_E_SUCCESS; + } + else + { + status = ALT_E_BAD_ARG; + } } else if (ALT_CLK_PERIPHERAL_PLL == clk) { - // the PLL must be bypassed before getting here - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + // the PLL must be bypassed before getting here + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); temp &= ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK; + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) { temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1); alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_IN_PIN_OSC2) { temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2); alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF); alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - else if ( ALT_CLK_SDRAM_PLL == clk) + else if (ALT_CLK_SDRAM_PLL == clk) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); temp &= ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK; + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) { temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1); alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_IN_PIN_OSC2) { temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2); alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_F2H_SDRAM_REF) { temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF); alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - else if ( ALT_CLK_L4_MP == clk) { - // clock is gated off + // clock is gated off if (ref_clk == ALT_CLK_MAIN_PLL_C1) { alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4) { alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - else if ( ALT_CLK_L4_SP == clk) { if (ref_clk == ALT_CLK_MAIN_PLL_C1) { alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4) { alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - - else if ( ALT_CLK_SDMMC == clk) + else if (ALT_CLK_SDMMC == clk) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); temp &= ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK; + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC)) { temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3) { temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - - else if (( ALT_CLK_NAND_X == clk) || ( ALT_CLK_NAND == clk)) + else if ((ALT_CLK_NAND_X == clk) || ( ALT_CLK_NAND == clk)) { temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); temp &= ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK; + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC)) { temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3) { temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - - else if ( ALT_CLK_QSPI == clk) + else if (ALT_CLK_QSPI == clk) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); temp &= ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK; + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) { temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if ((ref_clk == ALT_CLK_MAIN_PLL_C3) || (ref_clk == ALT_CLK_MAIN_QSPI)) { temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C2) { temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK); alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_INV_OPTION; } + else + { + status = ALT_E_INV_OPTION; + } } - return ret; -} - - -/****************************************************************************************/ -/* alt_clk_ext_clk_freq_set() specifies the frequency of the external clock source as */ -/* a measure of Hz. This value is stored in a static array and used for calculations. */ -/* The supplied frequency should be within the Fmin and Fmax values allowed for the */ -/* external clock source. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_ext_clk_freq_set() specifies the frequency of the external clock source as +// a measure of Hz. This value is stored in a static array and used for calculations. +// The supplied frequency should be within the Fmin and Fmax values allowed for the +// external clock source. +// ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk, alt_freq_t freq) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + ALT_STATUS_CODE status = ALT_E_BAD_ARG; if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1)) // two names for one input { if ((freq >= alt_ext_clk_paramblok.clkosc1.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc1.freqmax)) { alt_ext_clk_paramblok.clkosc1.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - else if (clk == ALT_CLK_IN_PIN_OSC2) // the other clock input pin { if ((freq >= alt_ext_clk_paramblok.clkosc2.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc2.freqmax)) { alt_ext_clk_paramblok.clkosc2.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - else if (clk == ALT_CLK_F2H_PERIPH_REF) // clock from the FPGA { if ((freq >= alt_ext_clk_paramblok.periph.freqmin) && (freq <= alt_ext_clk_paramblok.periph.freqmax)) { alt_ext_clk_paramblok.periph.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - else if (clk == ALT_CLK_F2H_SDRAM_REF) // clock from the FPGA SDRAM { if ((freq >= alt_ext_clk_paramblok.sdram.freqmin) && (freq <= alt_ext_clk_paramblok.sdram.freqmax)) { alt_ext_clk_paramblok.sdram.freqcur = freq; - ret = ALT_E_SUCCESS; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } } - return ret; -} - + else + { + status = ALT_E_BAD_ARG; + } -/****************************************************************************************/ -/* alt_clk_ext_clk_freq_get returns the frequency of the external clock source as */ -/* a measure of Hz. This value is stored in a static array. */ -/****************************************************************************************/ + return status; +} +// +// alt_clk_ext_clk_freq_get returns the frequency of the external clock source as +// a measure of Hz. This value is stored in a static array. +// alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk) { - uint32_t ret = 0; + uint32_t ret = 0; if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1)) // two names for one input { @@ -1754,323 +1777,341 @@ alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk) } -/****************************************************************************************/ -/* alt_clk_pll_cfg_get() returns the current PLL configuration. */ -/****************************************************************************************/ +// +// alt_clk_pll_cfg_get() returns the current PLL configuration. +// +ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll, ALT_CLK_PLL_CFG_t * pll_cfg) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // return value + uint32_t temp; // temp variable + + if (pll_cfg == NULL) + { + ret = ALT_E_BAD_ARG; + return ret; + } + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; + pll_cfg->mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + pll_cfg->div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); -ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll, ALT_CLK_PLL_CFG_t* pll_cfg) -{ - ALT_STATUS_CODE ret = ALT_E_ERROR; // return value - uint32_t temp; // temp variable - - if (pll_cfg != NULL) - { - if (pll == ALT_CLK_MAIN_PLL) - { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; - pll_cfg->mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); - pll_cfg->div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); - - // Get the C0-C5 divider values: - pll_cfg->cntrs[0] = ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)); - // C0 - mpu_clk - - pll_cfg->cntrs[1] = ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)); - // C1 - main_clk - - pll_cfg->cntrs[2] = ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)); - // C2 - dbg_base_clk - - pll_cfg->cntrs[3] = ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR)); - // C3 - main_qspi_clk - - pll_cfg->cntrs[4] = ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR)); - // C4 - main_nand_sdmmc_clk - - pll_cfg->cntrs[5] = ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR)); - // C5 - cfg_s2f_user0_clk aka cfg_h2f_user0_clk - - // The Main PLL C0-C5 outputs have no phase shift capabilities : - pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = - pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; - ret = ALT_E_SUCCESS; - } - else if (pll == ALT_CLK_PERIPHERAL_PLL) - { - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); - if (temp <= 2) - { - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { - pll_cfg->ref_clk = ALT_CLK_F2H_PERIPH_REF; - } - - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - pll_cfg->mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); - pll_cfg->div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - - // Get the C0-C5 divider values: - pll_cfg->cntrs[0] = ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR)); - // C0 - emac0_clk - - pll_cfg->cntrs[1] = ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR)); - // C1 - emac1_clk - - pll_cfg->cntrs[2] = ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR)); - // C2 - periph_qspi_clk - - pll_cfg->cntrs[3] = ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR)); - // C3 - periph_nand_sdmmc_clk - - pll_cfg->cntrs[4] = ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR)); - // C4 - periph_base_clk - - pll_cfg->cntrs[5] = ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR)); - // C5 - s2f_user1_clk - - // The Peripheral PLL C0-C5 outputs have no phase shift capabilities : - pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = - pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; - ret = ALT_E_SUCCESS; - } - } - else if (pll == ALT_CLK_SDRAM_PLL) - { - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - if (temp <= 2) - { - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { - pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { - pll_cfg->ref_clk = ALT_CLK_F2H_SDRAM_REF; - } - - pll_cfg->mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - pll_cfg->div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - - // Get the C0-C5 divider values: - pll_cfg->cntrs[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); - pll_cfg->pshift[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); - // C0 - ddr_dqs_clk - - pll_cfg->cntrs[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); - pll_cfg->pshift[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); - // C1 - ddr_2x_dqs_clk - - pll_cfg->cntrs[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); - pll_cfg->pshift[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); - // C2 - ddr_dq_clk - - pll_cfg->cntrs[3] = pll_cfg->cntrs[4] = pll_cfg->pshift[3] = pll_cfg->pshift[4] = 0; - // C3 & C4 outputs don't exist on the SDRAM PLL - - pll_cfg->cntrs[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); - pll_cfg->pshift[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); - // C5 - s2f_user2_clk or h2f_user2_clk - - ret = ALT_E_SUCCESS; - } - } - } - return ret; -} + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)); + // C0 - mpu_clk + pll_cfg->cntrs[1] = ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)); + // C1 - main_clk -/****************************************************************************************/ -/* alt_clk_pll_cfg_set() sets the PLL configuration using the configuration parameters */ -/* specified in pll_cfg. */ -/****************************************************************************************/ + pll_cfg->cntrs[2] = ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)); + // C2 - dbg_base_clk -ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll, const ALT_CLK_PLL_CFG_t* pll_cfg) -{ - ALT_STATUS_CODE ret = ALT_E_ERROR; - uint32_t temp; + pll_cfg->cntrs[3] = ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR)); + // C3 - main_qspi_clk + + pll_cfg->cntrs[4] = ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR)); + // C4 - main_nand_sdmmc_clk - if (pll_cfg != NULL) + pll_cfg->cntrs[5] = ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR)); + // C5 - cfg_s2f_user0_clk aka cfg_h2f_user0_clk + + // The Main PLL C0-C5 outputs have no phase shift capabilities : + pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = + pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) { - if (alt_clk_pll_is_bypassed(pll) == ALT_E_TRUE) // safe to write the PLL registers? + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + if (temp <= 2) { - if (pll == ALT_CLK_MAIN_PLL) + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) { - temp = (ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK) - & alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - temp |= ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(pll_cfg->mult) | - ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(pll_cfg->div); - alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp); - alt_write_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, pll_cfg->cntrs[0]); - alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, pll_cfg->cntrs[1]); - alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, pll_cfg->cntrs[2]); - alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, pll_cfg->cntrs[3]); - alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, pll_cfg->cntrs[4]); - alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, pll_cfg->cntrs[5]); - ret = ALT_E_SUCCESS; + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; } - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) { - temp = ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK - & ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK; - temp &= alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - temp |= ALT_CLKMGR_PERPLL_VCO_NUMER_SET(pll_cfg->mult) - | ALT_CLKMGR_PERPLL_VCO_DENOM_SET(pll_cfg->div); - if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) - { - temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1); - } - else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) - { - temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2); - } - else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) - { - temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF); - } - else { return ret; } - - alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); - alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, pll_cfg->cntrs[0]); - alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, pll_cfg->cntrs[1]); - alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, pll_cfg->cntrs[2]); - alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, pll_cfg->cntrs[3]); - alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, pll_cfg->cntrs[4]); - alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, pll_cfg->cntrs[5]); - ret = ALT_E_SUCCESS; + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; } - else if (pll == ALT_CLK_SDRAM_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) { - // write the SDRAM PLL VCO Counter ----------------------------- - temp = ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK - & ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK; // make a mask - temp &= alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - temp |= ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(pll_cfg->mult) - | ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(pll_cfg->div) - | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK; - // setting this bit aligns the output phase of the counters and prevents - // glitches and too-short clock periods when restarting. - // this bit is cleared at the end of this routine - - if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) - { - temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1); - } - else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) - { - temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2); - } - else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) - { - temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF); - } - else { return ret; } - alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); + pll_cfg->ref_clk = ALT_CLK_F2H_PERIPH_REF; + } - // write the SDRAM PLL C0 Divide Counter ----------------------------- - temp = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(pll_cfg->cntrs[0]) - | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(pll_cfg->pshift[0]); + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + pll_cfg->mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + pll_cfg->div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR)); + // C0 - emac0_clk - // write the SDRAM PLL C1 Divide Counter ----------------------------- - if (ret == ALT_E_SUCCESS) - { - temp = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(pll_cfg->cntrs[1]) - | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(pll_cfg->pshift[1]); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB); - } + pll_cfg->cntrs[1] = ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR)); + // C1 - emac1_clk - // write the SDRAM PLL C2 Divide Counter ----------------------------- - if (ret == ALT_E_SUCCESS) - { - temp = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(pll_cfg->cntrs[2]) - | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(pll_cfg->pshift[2]); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB); - } + pll_cfg->cntrs[2] = ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR)); + // C2 - periph_qspi_clk - // write the SDRAM PLL C5 Divide Counter ----------------------------- - if (ret == ALT_E_SUCCESS) - { - temp = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(pll_cfg->cntrs[2]) - | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(pll_cfg->pshift[2]); - alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, temp, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB); - } + pll_cfg->cntrs[3] = ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR)); + // C3 - periph_nand_sdmmc_clk - if (ret == ALT_E_SUCCESS) - { - alt_clrbits_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK); - // allow the phase multiplexer and output counter to leave reset - } + pll_cfg->cntrs[4] = ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR)); + // C4 - periph_base_clk + + pll_cfg->cntrs[5] = ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR)); + // C5 - s2f_user1_clk + + // The Peripheral PLL C0-C5 outputs have no phase shift capabilities : + pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = + pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; + ret = ALT_E_SUCCESS; + } + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + if (temp <= 2) + { + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + pll_cfg->ref_clk = ALT_CLK_F2H_SDRAM_REF; + } + + pll_cfg->mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + pll_cfg->div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); + pll_cfg->pshift[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); + // C0 - ddr_dqs_clk + + pll_cfg->cntrs[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); + pll_cfg->pshift[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); + // C1 - ddr_2x_dqs_clk + + pll_cfg->cntrs[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); + pll_cfg->pshift[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); + // C2 - ddr_dq_clk + + pll_cfg->cntrs[3] = pll_cfg->cntrs[4] = pll_cfg->pshift[3] = pll_cfg->pshift[4] = 0; + // C3 & C4 outputs don't exist on the SDRAM PLL + + pll_cfg->cntrs[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); + pll_cfg->pshift[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); + // C5 - s2f_user2_clk or h2f_user2_clk + + ret = ALT_E_SUCCESS; } } + return ret; } -/****************************************************************************************/ -/* alt_clk_pll_vco_cfg_get() returns the current PLL VCO frequency configuration. */ -/****************************************************************************************/ - -ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll, uint32_t* mult, uint32_t* div) +// +// alt_clk_pll_cfg_set() sets the PLL configuration using the configuration parameters +// specified in pll_cfg. +// +ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll, const ALT_CLK_PLL_CFG_t * pll_cfg) { - ALT_STATUS_CODE ret = ALT_E_ERROR; - uint32_t temp; + if (pll_cfg == NULL) + { + return ALT_E_BAD_ARG; + } - if ((mult != NULL) && (div != NULL)) + if (alt_clk_pll_is_bypassed(pll) != ALT_E_TRUE) // safe to write the PLL registers? { - if (pll == ALT_CLK_MAIN_PLL) + return ALT_E_ERROR; + } + + ALT_STATUS_CODE ret = ALT_E_ERROR; + uint32_t temp; + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = (ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK) + & alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + temp |= ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(pll_cfg->mult) | + ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(pll_cfg->div); + + alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp); + alt_write_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR, pll_cfg->cntrs[0]); + alt_write_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR, pll_cfg->cntrs[1]); + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, pll_cfg->cntrs[2]); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, pll_cfg->cntrs[3]); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, pll_cfg->cntrs[4]); + alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, pll_cfg->cntrs[5]); + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK + & ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK; + temp &= alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + temp |= ALT_CLKMGR_PERPLL_VCO_NUMER_SET(pll_cfg->mult) + | ALT_CLKMGR_PERPLL_VCO_DENOM_SET(pll_cfg->div); + + if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - *mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp) + 1; - *div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp) + 1; - ret = ALT_E_SUCCESS; + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1); } - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - *mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp) + 1; - *div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp) + 1; - ret = ALT_E_SUCCESS; + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2); } - else if (pll == ALT_CLK_SDRAM_PLL) + else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - *mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp) + 1; - *div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp) + 1; - ret = ALT_E_SUCCESS; + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF); + } + else + { + return ret; + } + + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, pll_cfg->cntrs[0]); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, pll_cfg->cntrs[1]); + alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, pll_cfg->cntrs[2]); + alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, pll_cfg->cntrs[3]); + alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, pll_cfg->cntrs[4]); + alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, pll_cfg->cntrs[5]); + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + // write the SDRAM PLL VCO Counter ----------------------------- + temp = ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK + & ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK; // make a mask + temp &= alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + temp |= ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(pll_cfg->mult) + | ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(pll_cfg->div) + | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK; + // setting this bit aligns the output phase of the counters and prevents + // glitches and too-short clock periods when restarting. + // this bit is cleared at the end of this routine + + if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1); + } + else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2); + } + else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF); + } + else + { + return ret; + } + + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); + + // write the SDRAM PLL C0 Divide Counter ----------------------------- + temp = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(pll_cfg->cntrs[0]) + | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(pll_cfg->pshift[0]); + + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); + + // write the SDRAM PLL C1 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(pll_cfg->cntrs[1]) + | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(pll_cfg->pshift[1]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB); + } + + // write the SDRAM PLL C2 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(pll_cfg->cntrs[2]) + | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(pll_cfg->pshift[2]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB); + } + + // write the SDRAM PLL C5 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(pll_cfg->cntrs[2]) + | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(pll_cfg->pshift[2]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB); + } + + if (ret == ALT_E_SUCCESS) + { + alt_clrbits_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK); + // allow the phase multiplexer and output counter to leave reset } } + return ret; } +// +// alt_clk_pll_vco_cfg_get() returns the current PLL VCO frequency configuration. +// +ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll, uint32_t * mult, uint32_t * div) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; + + if ( (mult == NULL) || (div == NULL) ) + { + return ALT_E_BAD_ARG; + } + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + *mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp) + 1; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + *mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp) + 1; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + *mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp) + 1; + } + else + { + status = ALT_E_ERROR; + } + + return status; +} + + /****************************************************************************************/ /* This enum enumerates a set of possible change methods that are available for use by */ /* alt_clk_pll_vco_cfg_set() to change VCO parameter settings. */ @@ -2123,10 +2164,20 @@ static ALT_CLK_PLL_VCO_CHG_METHOD_t alt_clk_pll_vco_chg_methods_get(ALT_CLK_t pl uint32_t mult, uint32_t div ) { #if ALT_CLK_PLL_VCO_CHG_METHOD_TEST_MODE + // used for testing - return ALT_VCO_CHG_NOCHANGE; + return ALT_VCO_CHG_NOCHANGE; + +#else + + // check PLL max value limits + if ( (mult == 0) || (mult > ALT_CLK_PLL_MULT_MAX) + || (div == 0) || (div > ALT_CLK_PLL_DIV_MAX) + ) + { + return ALT_VCO_CHG_NONE_VALID; + } -#endif ALT_CLK_PLL_VCO_CHG_METHOD_t ret = ALT_VCO_CHG_NONE_VALID; uint32_t temp; uint32_t numer; @@ -2139,124 +2190,148 @@ static ALT_CLK_PLL_VCO_CHG_METHOD_t alt_clk_pll_vco_chg_methods_get(ALT_CLK_t pl bool denomchg = false; bool within_gb; - if ((mult > 0) && (mult <= ALT_CLK_PLL_MULT_MAX) && (div > 0) - && (div <= ALT_CLK_PLL_DIV_MAX)) // check PLL max value limits + // gather data values according to PLL + if (pll == ALT_CLK_MAIN_PLL) { - // gather data values according to PLL - if (pll == ALT_CLK_MAIN_PLL) + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + + numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.MainPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.MainPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.MainPLL_800.guardband; + + inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; + } + + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + + numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.PeriphPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.PeriphPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.PeriphPLL_800.guardband; + + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); - freqmax = alt_pll_clk_paramblok.MainPLL_800.freqmax; - freqmin = alt_pll_clk_paramblok.MainPLL_800.freqmin; - guardband = alt_pll_clk_paramblok.MainPLL_800.guardband; inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; } - - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); - freqmax = alt_pll_clk_paramblok.PeriphPLL_800.freqmax; - freqmin = alt_pll_clk_paramblok.PeriphPLL_800.freqmin; - guardband = alt_pll_clk_paramblok.PeriphPLL_800.guardband; - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { - inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { - inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { - inputfreq = alt_ext_clk_paramblok.periph.freqcur; - } - else { return ret; } + inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; } - - else if (pll == ALT_CLK_SDRAM_PLL) + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); - freqmax = alt_pll_clk_paramblok.SDRAMPLL_800.freqmax; - freqmin = alt_pll_clk_paramblok.SDRAMPLL_800.freqmin; - guardband = alt_pll_clk_paramblok.SDRAMPLL_800.guardband; - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { - inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { - inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { - inputfreq = alt_ext_clk_paramblok.sdram.freqcur; - } - else { return ret; } + inputfreq = alt_ext_clk_paramblok.periph.freqcur; } - else { return ret; } + else + { + return ret; + } + } - temp = (mult * inputfreq) / div; - if ((temp <= freqmax) && (temp >= freqmin)) // are the final values within frequency limits? + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + + numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.SDRAMPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.SDRAMPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.SDRAMPLL_800.guardband; + + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) { - numer++; - denom++; - numerchg = (mult != numer); - denomchg = (div != denom); + inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + inputfreq = alt_ext_clk_paramblok.sdram.freqcur; + } + else + { + return ret; + } + } + else + { + return ret; + } - if (!numerchg && !denomchg) + temp = mult * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) // are the final values within frequency limits? + { + numer++; + denom++; + numerchg = (mult != numer); + denomchg = (div != denom); + + if (!numerchg && !denomchg) + { + ret = ALT_VCO_CHG_NOCHANGE; + } + else if (numerchg && !denomchg) + { + within_gb = alt_within_delta(numer, mult, guardband); + // check if change is within the guardband limits + temp = mult * (inputfreq / denom); + if ((temp <= freqmax) && (temp >= freqmin)) { - ret = ALT_VCO_CHG_NOCHANGE; + ret = ALT_VCO_CHG_NUM; + if (!within_gb) ret |= ALT_VCO_CHG_NUM_BYP; } - else if (numerchg && !denomchg) + } + else if (!numerchg && denomchg) + { + within_gb = alt_within_delta(denom, div, guardband); + temp = numer * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) { - within_gb = alt_within_delta(numer, mult, guardband); - // check if change is within the guardband limits - temp = (mult * inputfreq) / denom; - if ((temp <= freqmax) && (temp >= freqmin)) + ret = ALT_VCO_CHG_DENOM; + if (!within_gb) { - ret = ALT_VCO_CHG_NUM; - if (!within_gb) ret |= ALT_VCO_CHG_NUM_BYP; + ret |= ALT_VCO_CHG_DENOM_BYP; } } - else if (!numerchg && denomchg) + } + else //numerchg && denomchg + { + within_gb = alt_within_delta(numer, mult, guardband); + temp = mult * (inputfreq / denom); + if ((temp <= freqmax) && (temp >= freqmin)) { - within_gb = alt_within_delta(denom, div, guardband); - temp = (numer * inputfreq) / div; - if ((temp <= freqmax) && (temp >= freqmin)) + ret = ALT_VCO_CHG_NUM_DENOM; + if (!within_gb) { - ret = ALT_VCO_CHG_DENOM; - if (!within_gb) ret |= ALT_VCO_CHG_DENOM_BYP; + ret |= ALT_VCO_CHG_NUM_DENOM_BYP; } } - else //numerchg && denomchg + within_gb = alt_within_delta(denom, div, guardband); + temp = numer * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) { - within_gb = alt_within_delta(numer, mult, guardband); - temp = (mult * inputfreq) / denom; - if ((temp <= freqmax) && (temp >= freqmin)) + ret = ALT_VCO_CHG_DENOM_NUM; + if (!within_gb) { - ret = ALT_VCO_CHG_NUM_DENOM; - if (!within_gb) ret |= ALT_VCO_CHG_NUM_DENOM_BYP; - } - within_gb = alt_within_delta(denom, div, guardband); - temp = (numer * inputfreq) / div; - if ((temp <= freqmax) && (temp >= freqmin)) - { - ret = ALT_VCO_CHG_DENOM_NUM; - if (!within_gb) ret |= ALT_VCO_CHG_DENOM_NUM_BYP; + ret |= ALT_VCO_CHG_DENOM_NUM_BYP; } } } } return ret; +#endif } @@ -2387,15 +2462,13 @@ ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll, uint32_t mult, uint32_t d } -/****************************************************************************************/ -/* alt_clk_pll_vco_freq_get() gets the VCO frequency of the specified PLL. */ -/* Note that since there is at present no known way for software to obtain the speed */ -/* bin of the SoC or MPU that it is running on, the function below only deals with the */ -/* 800 MHz part. This may need to be revised in the future. */ -/****************************************************************************************/ - - -ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, alt_freq_t* freq) +// +// alt_clk_pll_vco_freq_get() gets the VCO frequency of the specified PLL. +// Note that since there is at present no known way for software to obtain the speed +// bin of the SoC or MPU that it is running on, the function below only deals with the +// 800 MHz part. This may need to be revised in the future. +// +ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, alt_freq_t * freq) { uint64_t temp1 = 0; uint32_t temp; @@ -2403,99 +2476,120 @@ ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, alt_freq_t* freq) uint32_t denom; ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - if (freq != NULL) + if (freq == NULL) { - if (pll == ALT_CLK_MAIN_PLL) + return ret; + } + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; + temp1 *= (numer + 1); + temp1 /= (denom + 1); + + if (temp1 <= UINT32_MAX) + { + temp = (alt_freq_t) temp1; + alt_pll_clk_paramblok.MainPLL_800.freqcur = temp; + // store this value in the parameter block table + *freq = temp; + // should NOT check value against PLL frequency limits + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ERROR; + } + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + } + + if (temp1 != 0) + { temp1 *= (numer + 1); temp1 /= (denom + 1); if (temp1 <= UINT32_MAX) { temp = (alt_freq_t) temp1; - alt_pll_clk_paramblok.MainPLL_800.freqcur = temp; - // store this value in the parameter block table + alt_pll_clk_paramblok.PeriphPLL_800.freqcur = temp; + // store this value in the parameter block table + *freq = temp; - // should NOT check value against PLL frequency limits ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ERROR; } + else + { + ret = ALT_E_ERROR; + } + } // this returns ALT_BAD_ARG if the source isn't known + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; } - else if (pll == ALT_CLK_PERIPHERAL_PLL) + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { temp1 = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; } - - if (temp1 != 0) - { - temp1 *= (numer + 1); - temp1 /= (denom + 1); - if (temp1 <= UINT32_MAX) - { - temp = (alt_freq_t) temp1; - alt_pll_clk_paramblok.PeriphPLL_800.freqcur = temp; - // store this value in the parameter block table - - *freq = temp; - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ERROR; } - } // this returns ALT_BAD_ARG if the source isn't known + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; } - else if (pll == ALT_CLK_SDRAM_PLL) + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) { - temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); - denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { temp1 = (uint64_t) alt_ext_clk_paramblok.sdram.freqcur; } + temp1 = (uint64_t) alt_ext_clk_paramblok.sdram.freqcur; + } - if (temp1 != 0) + if (temp1 != 0) + { + temp1 *= (numer + 1); + temp1 /= (denom + 1); + if (temp1 <= UINT32_MAX) { - temp1 *= (numer + 1); - temp1 /= (denom + 1); - if (temp1 <= UINT32_MAX) - { - temp = (alt_freq_t) temp1; - alt_pll_clk_paramblok.SDRAMPLL_800.freqcur = temp; - // store this value in the parameter block table + temp = (alt_freq_t) temp1; + alt_pll_clk_paramblok.SDRAMPLL_800.freqcur = temp; + // store this value in the parameter block table - *freq = temp; - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ERROR; } + *freq = temp; + ret = ALT_E_SUCCESS; } - } // which returns ALT_BAD_ARG if the source isn't known - } + else + { + ret = ALT_E_ERROR; + } + } + } // which returns ALT_BAD_ARG if the source isn't known + return ret; } - -/****************************************************************************************/ -/* Returns the current guard band range in effect for the PLL. */ -/****************************************************************************************/ - - +// +// Returns the current guard band range in effect for the PLL. +// uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll) { - int32_t ret = 0; + uint32_t ret = 0; if (pll == ALT_CLK_MAIN_PLL) { @@ -2512,297 +2606,315 @@ uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll) return ret; } - -/****************************************************************************************/ -/* clk_mgr_pll_guard_band_set() changes the guard band from its current value to permit */ -/* a more lenient or stringent policy to be in effect for the implementation of the */ -/* functions configuring PLL VCO frequency. */ -/****************************************************************************************/ - +// +// clk_mgr_pll_guard_band_set() changes the guard band from its current value to permit +// a more lenient or stringent policy to be in effect for the implementation of the +// functions configuring PLL VCO frequency. +// ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll, uint32_t guard_band) { - ALT_STATUS_CODE ret = ALT_E_ERROR; - - if ((guard_band <= UINT12_MAX) && (guard_band > 0) && (guard_band <= ALT_GUARDBAND_LIMIT)) + if ( (guard_band > UINT12_MAX) || (guard_band <= 0) + || (guard_band > ALT_GUARDBAND_LIMIT) + ) { - if (pll == ALT_CLK_MAIN_PLL) - { - alt_pll_clk_paramblok.MainPLL_800.guardband = guard_band; - //alt_pll_clk_paramblok.MainPLL_600.guardband = guard_band; - // ??? Don't know how to check the MPU speed bin yet, so only 800 MHz struct is used - ret = ALT_E_SUCCESS; - } - else if (pll == ALT_CLK_PERIPHERAL_PLL) - { - alt_pll_clk_paramblok.PeriphPLL_800.guardband = guard_band; - //alt_pll_clk_paramblok.PeriphPLL_600.guardband = guard_band; - ret = ALT_E_SUCCESS; - } - else if (pll == ALT_CLK_SDRAM_PLL) - { - alt_pll_clk_paramblok.SDRAMPLL_800.guardband = guard_band; - //alt_pll_clk_paramblok.SDRAMPLL_600.guardband = guard_band; - ret = ALT_E_SUCCESS; - } + return ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } - return ret; -} + ALT_STATUS_CODE status = ALT_E_SUCCESS; -/****************************************************************************************/ -/* alt_clk_divider_get() gets configured divider value for the specified clock. */ -/****************************************************************************************/ + if (pll == ALT_CLK_MAIN_PLL) + { + alt_pll_clk_paramblok.MainPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.MainPLL_600.guardband = guard_band; + // ??? Don't know how to check the MPU speed bin yet, so only 800 MHz struct is used + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + alt_pll_clk_paramblok.PeriphPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.PeriphPLL_600.guardband = guard_band; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + alt_pll_clk_paramblok.SDRAMPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.SDRAMPLL_600.guardband = guard_band; + } + else + { + status = ALT_E_ERROR; + } + + return status; +} -ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, uint32_t* div) +// +// alt_clk_divider_get() gets configured divider value for the specified clock. +// +ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, uint32_t * div) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; - if (div != NULL) + if (div == NULL) { - switch (clk) - { - /* Main PLL outputs */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MPU: - *div = (ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)) + 1) << 1; - // adjust for the additional divide-by-2 internal counter on C0 - ret = ALT_E_SUCCESS; - break; + return ALT_E_BAD_ARG; + } - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_L4_MAIN: - case ALT_CLK_L3_MAIN: - *div = (ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)) + 1) << 2; - // adjust for the additional divide-by-4 internal counter on C1 - ret = ALT_E_SUCCESS; - break; + switch (clk) + { + // Main PLL outputs + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MPU: + *div = (ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)) + 1); + break; - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_DBG_BASE: - case ALT_CLK_DBG_TIMER: - *div = (ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)) + 1) << 2; - // adjust for the additional divide-by-4 internal counter on C2 - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + *div = (ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)) + 1); + break; - case ALT_CLK_MAIN_PLL_C3: - case ALT_CLK_MAIN_QSPI: - *div = (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_TIMER: + *div = (ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_DBGATCLK_ADDR)) + 1); + break; - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_NAND_SDMMC: - *div = (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_QSPI: + *div = (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR))) + 1; + break; - case ALT_CLK_MAIN_PLL_C5: - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - *div = (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - - /* Peripheral PLL outputs */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_EMAC0: - *div = (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_EMAC1: - *div = (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C2: - *div = (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C3: - *div = (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C4: - *div = (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_PERIPHERAL_PLL_C5: - case ALT_CLK_H2F_USER1: - *div = (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - - /* SDRAM PLL outputs */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_DDR_DQS: - *div = (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_DDR_2X_DQS: - *div = (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_DDR_DQ: - *div = (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_SDRAM_PLL_C5: - case ALT_CLK_H2F_USER2: - *div = (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR))) + 1; - ret = ALT_E_SUCCESS; - break; - - - /* Other clock dividers */ - case ALT_CLK_L3_MP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2) - { - *div = temp + 1; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_NAND_SDMMC: + *div = (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR))) + 1; + break; - case ALT_CLK_L3_SP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2) - { - *div = temp + 1; - ret = ALT_E_SUCCESS; - } - // note that this value does not include the additional effect - // of the L3_MP divider that is upchain from this one - break; + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + *div = (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR))) + 1; + break; - case ALT_CLK_L4_MP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + ///// - case ALT_CLK_L4_SP: - temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + // Peripheral PLL outputs + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_EMAC0: + *div = (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR))) + 1; + break; - case ALT_CLK_DBG_AT: - temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_EMAC1: + *div = (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR))) + 1; + break; - case ALT_CLK_DBG: - temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - // note that this value does not include the value of the upstream dbg_at_clk divder - break; + case ALT_CLK_PERIPHERAL_PLL_C2: + *div = (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR))) + 1; + break; - case ALT_CLK_DBG_TRACE: - temp = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR)); - if (temp <= ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C3: + *div = (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR))) + 1; + break; - case ALT_CLK_USB_MP: - temp = ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C4: + *div = (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR))) + 1; + break; - case ALT_CLK_SPI_M: - temp = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_H2F_USER1: + *div = (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR))) + 1; + break; - case ALT_CLK_CAN0: - temp = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + ///// - case ALT_CLK_CAN1: - temp = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); - if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16) - { - *div = 1 << temp; - ret = ALT_E_SUCCESS; - } - break; + // SDRAM PLL outputs + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + *div = (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR))) + 1; + break; - case ALT_CLK_GPIO_DB: - temp = ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR)); - *div = temp + 1; - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + *div = (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR))) + 1; + break; - case ALT_CLK_MPU_PERIPH: - *div = 4; // set by hardware - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + *div = (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR))) + 1; + break; - case ALT_CLK_MPU_L2_RAM: - *div = 2; // set by hardware - ret = ALT_E_SUCCESS; - break; + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + *div = (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR))) + 1; + break; - case ALT_CLK_NAND: - *div = 4; // set by hardware - ret = ALT_E_SUCCESS; - break; + ///// - default: - break; - } - } - return ret; -} + // Other clock dividers + case ALT_CLK_L3_MP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2) + { + *div = temp + 1; + } + else + { + status = ALT_E_ERROR; + } + break; + case ALT_CLK_L3_SP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2) + { + *div = temp + 1; + } + else + { + status = ALT_E_ERROR; + } + // note that this value does not include the additional effect + // of the L3_MP divider that is upchain from this one + break; -/****************************************************************************************/ + case ALT_CLK_L4_MP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; -/****************************************************************************************/ + case ALT_CLK_L4_SP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_DBG_AT: + temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_DBG: + temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + // note that this value does not include the value of the upstream dbg_at_clk divder + break; + + case ALT_CLK_DBG_TRACE: + temp = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_USB_MP: + temp = ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_SPI_M: + temp = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_CAN0: + temp = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_CAN1: + temp = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_GPIO_DB: + temp = ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR)); + *div = temp + 1; + break; + + case ALT_CLK_MPU_PERIPH: + *div = 4; // set by hardware + break; + + case ALT_CLK_MPU_L2_RAM: + *div = 2; // set by hardware + break; + + case ALT_CLK_NAND: + *div = 4; // set by hardware + break; + + default: + status = ALT_E_BAD_ARG; + break; + } + + return status; +} + +///// #define ALT_CLK_WITHIN_FREQ_LIMITS_TEST_MODE false // used for testing writes to the the full range of counters without @@ -2811,143 +2923,156 @@ ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, uint32_t* div) static ALT_STATUS_CODE alt_clk_within_freq_limits(ALT_CLK_t clk, uint32_t div) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t numer; - uint32_t hilimit; - uint32_t lolimit; - #if ALT_CLK_WITHIN_FREQ_LIMITS_TEST_MODE return ALT_E_TRUE; -#endif +#else - if (div != 0) + if (div == 0) { - if (!ALT_CLK_WITHIN_FREQ_LIMITS_TEST_MODE) - { - // Normal mode - do the frequency check + return ALT_E_BAD_ARG; + } - /* Counters of the Main PLL */ - if (clk == ALT_CLK_MAIN_PLL_C0) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C0; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C1) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C1; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C2) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C2; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C3) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C3; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C4) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C4; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } - else if (clk == ALT_CLK_MAIN_PLL_C5) - { - hilimit = alt_pll_cntr_maxfreq.MainPLL_C5; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); - } + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t numer = 0; + uint32_t hilimit; + uint32_t lolimit; - /* Counters of the Peripheral PLL */ - else if (clk == ALT_CLK_PERIPHERAL_PLL_C0) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C0; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C1) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C1; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C2) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C2; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C3) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C3; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C4) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C4; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } - else if (clk == ALT_CLK_PERIPHERAL_PLL_C5) - { - hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C5; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); - } + switch (clk) + { + // Counters of the Main PLL + case ALT_CLK_MAIN_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C0; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C1; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C2; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C3: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C3; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C4: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C4; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; - /* Counters of the SDRAM PLL */ - else if (clk == ALT_CLK_SDRAM_PLL_C0) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C0; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else if (clk == ALT_CLK_SDRAM_PLL_C1) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C1; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else if (clk == ALT_CLK_SDRAM_PLL_C2) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C2; - lolimit = 0; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else if (clk == ALT_CLK_SDRAM_PLL_C5) - { - hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C5; - lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); - } - else { return ret; } + // Counters of the Peripheral PLL + case ALT_CLK_PERIPHERAL_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C0; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C1; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C2; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C3; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C4; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; - numer = numer / div; - if ((numer <= hilimit) && (numer >= lolimit)) - { - ret = ALT_E_TRUE; - } - else { ret = ALT_E_FALSE; } + // Counters of the SDRAM PLL + case ALT_CLK_SDRAM_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C0; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C1; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C2; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + + default: + status = ALT_E_BAD_ARG; + break; + } + + if (status == ALT_E_SUCCESS) + { + numer = numer / div; + if ((numer <= hilimit) && (numer >= lolimit)) + { + status = ALT_E_TRUE; + } + else + { + status = ALT_E_FALSE; } } - return ret; -} + return status; +#endif +} -/****************************************************************************************/ -/* alt_clk_divider_set() sets the divider value for the specified clock. */ -/* */ -/* See pages 38, 44, 45, and 46 of the HPS-Clocking NPP for a map of the */ -/* HPS clocking architecture and hierarchy of connections. */ -/****************************************************************************************/ +static bool alt_clkmgr_is_val_modulo_n(uint32_t div, uint32_t mod) +{ + if (mod == 1) + { + return true; + } + else if (mod == 2) + { + return (div & 0x1) == 0; + } + else if (mod == 4) + { + return (div & 0x3) == 0; + } + else + { + return (div % mod) == 0; + } +} +// +// alt_clk_divider_set() sets the divider value for the specified clock. +// +// See pages 38, 44, 45, and 46 of the HPS-Clocking NPP for a map of the +// HPS clocking architecture and hierarchy of connections. +// ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk, uint32_t div) { ALT_STATUS_CODE ret = ALT_E_BAD_ARG; @@ -2957,1974 +3082,2473 @@ ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk, uint32_t div) bool restore_1 = false; bool restore_2 = false; - switch (clk) + switch (clk) { - /* ------------ Main PLL outputs ------------ */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MPU: - if ((div <= ((ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK << 1) + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C0, div) == ALT_E_TRUE)) - { - wrval = (div >> 1) + 1; // adjust for the automatic divide-by-two internal counter on C0 - // HW managed clock, change by writing to the external counter, no need to gate clock - // or match phase or wait for transistion time. No other field in the register to mask off either. - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C0, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_L3_MAIN: - if ((div <= ((ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK << 2) + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C1, div) == ALT_E_TRUE)) - { - // HW managed clock, change by writing to the external counter, no need to gate clock - // or match phase or wait for transistion time. No other field in the register to mask off either. - - wrval = (div >> 2) + 1; // adjust for the automatic divide-by-four internal counter on C1 -#if ALT_PREVENT_GLITCH_CHGC1 - // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing - // bypass state, then gate clock back on. FogBugz #63778 - temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); - temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - - if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) - { - restore_0 = true; - } - if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) - { - restore_1 = true; - } - temp = temp1; - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } - if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } - - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - // wait a bit before reenabling the L4MP and L4SP clocks - if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } + // Main PLL outputs + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MPU: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)) + 1); + if ( (div <= ((ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C0, div) == ALT_E_TRUE) ) + { + wrval = (div / prediv) - 1; -#else - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, - div >> 2, // adjust for the automatic divide-by-four internal counter on C1 - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); -#endif + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. + alt_write_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, wrval); ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_DBG_BASE: - if ((div <= ((ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK << 2) + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C2, div) == ALT_E_TRUE)) - { - wrval = (div >> 2) + 1; // adjust for the automatic divide-by-four internal counter on C2 - // HW managed clock, change by writing to the external counter, no need to gate clock - // or match phase or wait for transistion time. No other field in the register to mask off either. - // The counter does have to be reset though, using a request-and-ack method. - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C3: - // The rest of the PLL outputs do not have external counters, but - // their internal counters are programmable rather than fixed - if ((div <= (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C3, div) == ALT_E_TRUE)) + } + else { - if (ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)) - == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - // if the main_qspi_clk input is selected for the qspi_clk - { - restore_0 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; - if (restore_0) // AND if the QSPI clock is enabled - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); - // gate off the QSPI clock - } - - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C3, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - // if the QSPI clock was gated on (enabled) before, return it to that state - } - ret = ALT_E_SUCCESS; - } + ret = ALT_E_ARG_RANGE; } - else { ret = ALT_E_ARG_RANGE; } - break; + } + break; - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_NAND_SDMMC: - if ((div <= (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C4, div) == ALT_E_TRUE)) + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_L3_MAIN: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)) + 1); + + if ( (div <= ((ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C1, div) == ALT_E_TRUE) ) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); - temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. - // do we need to gate off the SDMMC clock ? - if (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) - { - if (temp1 & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK) { restore_0 = true; } - } + wrval = (div / prediv) - 1; - // do we need to gate off the NAND clock and/or the NANDX clock? - if (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) - { - if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK) { restore_1 = true; } - if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK) { restore_2 = true; } - } +#if ALT_PREVENT_GLITCH_CHGC1 + // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing + // bypass state, then gate clock back on. FogBugz #63778 + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - temp = temp1; - if (restore_1 && restore_2) + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) { - temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - // gate nand_clk off at least 8 MPU clock cycles before before nand_x_clk + restore_0 = true; } - - if (restore_0 || restore_1) + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) { - if (restore_0) { temp &= ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; } - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - // gate off sdmmc_clk and/or nand_x_clk + restore_1 = true; } + temp = temp1; + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C4, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, wrval); - if (restore_0 || restore_1) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK); - // if the NANDX and/or SDMMC clock was gated on (enabled) before, return it to that state - if (restore_1 && restore_2) - { - // wait at least 8 clock cycles to turn the nand_clk on - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); - } - } + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + // wait a bit before reenabling the L4MP and L4SP clocks + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } +#else + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, wrval); +#endif ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_MAIN_PLL_C5: - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - if ((div <= (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C5, div) == ALT_E_TRUE)) + else { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - restore_0 = ((temp & ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK) - || (temp & ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK)); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & (ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK - & ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK)); // clear 'em both - } + ret = ALT_E_ARG_RANGE; + } + } + break; - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C5, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_DBG_BASE: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_DBGATCLK_ADDR)) + 1); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if ( (div <= ((ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C2, div) == ALT_E_TRUE) ) + { + wrval = (div / prediv) - 1; + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, wrval); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; - - - /* ------------ Peripheral PLL outputs ------------ */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_EMAC0: - if ((div <= (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C0, div) == ALT_E_TRUE)) + else { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK; + ret = ALT_E_ARG_RANGE; + } + } + break; - if (restore_0) + case ALT_CLK_MAIN_PLL_C3: + // The rest of the PLL outputs do not have external counters, but + // their internal counters are programmable rather than fixed + if ( (div <= (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C3, div) == ALT_E_TRUE) ) + { + // if the main_qspi_clk input is selected for the qspi_clk + if (ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)) == + ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + restore_0 = (temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; + if (restore_0) // AND if the QSPI clock is currently enabled { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); + // gate off the QSPI clock } - // now write the new divisor ratio wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C0, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + // the rest are software-managed clocks and require a reset sequence to write to + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // if the QSPI clock was gated on (enabled) before, return it to that state } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_EMAC1: - if ((div <= (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C1, div) == ALT_E_TRUE)) - { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK; + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_NAND_SDMMC: + if ( (div <= (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C4, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK); - } - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // do we need to gate off the SDMMC clock ? + if (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + if (temp1 & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK) { restore_0 = true; } } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_PERIPHERAL_PLL_C2: - if ((div <= (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C2, div) == ALT_E_TRUE)) + // do we need to gate off the NAND clock and/or the NANDX clock? + if (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) { - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - // if qspi source is set to Peripheral PLL C2 - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - // and if qspi_clk is enabled - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); - // gate it off - } - } - - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK) { restore_1 = true; } + if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK) { restore_2 = true; } + } - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - // if the clock was gated on (enabled) before, return it to that state - } - ret = ALT_E_SUCCESS; + temp = temp1; + if (restore_1 && restore_2) + { + temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_clk off at least 8 MPU clock cycles before before nand_x_clk } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_PERIPHERAL_PLL_C3: - if ((div <= (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C3, div) == ALT_E_TRUE)) + if (restore_0 || restore_1) { - // first, are the clock MUX input selections currently set to use the clock we want to change? - temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); - restore_0 = (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK); - restore_1 = restore_2 = (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK); - - // now AND those with the current state of the three gate enables - // to get the clocks which must be gated off and then back on - temp1 = temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = restore_0 && (temp & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); - restore_1 = restore_1 && (temp & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); - restore_2 = restore_2 && (temp & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); - - // gate off the clocks that depend on the clock divider that we want to change - if (restore_2) { temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; } if (restore_0) { temp &= ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; } alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // gate off sdmmc_clk and/or nand_x_clk + } - // the NAND clock must be gated off before the NANDX clock, - if (restore_1) - { - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); - temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C3, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C4, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - // NAND clock and NAND_X clock cannot be written together, must be a set sequence with a delay + if (restore_0 || restore_1) + { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK); - if (restore_2) + // if the NANDX and/or SDMMC clock was gated on (enabled) before, return it to that state + if (restore_1 && restore_2) { - // the NANDX clock must be gated on before the NAND clock. - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK ); + // wait at least 8 clock cycles to turn the nand_clk on + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); } - ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_PERIPHERAL_PLL_C4: - if ((div <= (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C4, div) == ALT_E_TRUE)) + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + if ( (div <= (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C5, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + restore_0 = ((temp & ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK) || + (temp & ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK)); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & (ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK & + ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK)); // clear both + } + + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + + if (restore_0) { - // look at the L4 set of clock gates first - temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); - restore_0 = (ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL); - restore_1 = (ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL); - temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = restore_0 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); - restore_1 = restore_1 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); - - // if the l4_sp and l4_mp clocks are not set to use the periph_base_clk - // from the Peripheral PLL C4 clock divider output, or if they are - // not currently gated on, don't change their gates - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } - if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - // now look at the C4 direct set of clock gates - // first, create a mask of the C4 direct set of clock gate enables - temp = (ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK - | ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); + ///// - // gate off all the C4 Direct set of clocks - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ~temp); + // Peripheral PLL outputs + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_EMAC0: + if ( (div <= (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C0, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK; - // change the clock divider ratio - the reason we're here - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C4, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - - // gate the affected clocks that were on before back on - both sets of gates - temp = (restore_0) ? ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK : 0; - if (restore_1) { temp |= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK; } - alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); - ret = ALT_E_SUCCESS; + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK); } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_PERIPHERAL_PLL_C5: - case ALT_CLK_H2F_USER1: - if ((div <= (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C5, div) == ALT_E_TRUE)) + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C0, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_EMAC1: + if ( (div <= (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C1, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK; + + if (restore_0) { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK); + } + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C1, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C2: + if ( (div <= (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C2, div) == ALT_E_TRUE) ) + { + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + // if qspi source is set to Peripheral PLL C2 temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - restore_0 = temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK; + // and if qspi_clk is enabled + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; if (restore_0) { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); + // gate it off } + } - // now write the new divisor ratio - wrval = div - 1; - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C5, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - if (restore_0) { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); } - ret = ALT_E_SUCCESS; + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // if the clock was gated on (enabled) before, return it to that state } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + if ( (div <= (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C3, div) == ALT_E_TRUE) ) + { + // first, are the clock MUX input selections currently set to use the clock we want to change? + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + restore_0 = (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK); + restore_1 = restore_2 = (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK); + + // now AND those with the current state of the three gate enables + // to get the clocks which must be gated off and then back on + temp1 = temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = restore_0 && (temp & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + restore_1 = restore_1 && (temp & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + restore_2 = restore_2 && (temp & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + + // gate off the clocks that depend on the clock divider that we want to change + if (restore_2) { temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK; } + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + + // the NAND clock must be gated off before the NANDX clock, + if (restore_1) + { + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } - /* ------------ SDRAM PLL outputs ------------ */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_DDR_DQS: - if ((div <= (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C0, div) == ALT_E_TRUE)) - { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK); - restore_0 = true; - } - - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C0, - ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_DDR_2X_DQS: - if ((div <= (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C1, div) == ALT_E_TRUE)) + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + + // NAND clock and NAND_X clock cannot be written together, must be a set sequence with a delay + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK); + if (restore_2) { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK); - restore_0 = true; - } + // the NANDX clock must be gated on before the NAND clock. + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK ); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C1, - ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + case ALT_CLK_PERIPHERAL_PLL_C4: + if ( (div <= (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C4, div) == ALT_E_TRUE) ) + { + // look at the L4 set of clock gates first + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + restore_0 = (ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL); + restore_1 = (ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL); + temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = restore_0 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + restore_1 = restore_1 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + + // if the l4_sp and l4_mp clocks are not set to use the periph_base_clk + // from the Peripheral PLL C4 clock divider output, or if they are + // not currently gated on, don't change their gates + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + + // now look at the C4 direct set of clock gates + // first, create a mask of the C4 direct set of clock gate enables + temp = ( ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK ); + + // gate off all the C4 Direct set of clocks + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ~temp); + + // change the clock divider ratio - the reason we're here + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C4, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + + // gate the affected clocks that were on before back on - both sets of gates + temp = (restore_0) ? ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK : 0; + if (restore_1) { temp |= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK; } + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_H2F_USER1: + if ( (div <= (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C5, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK; + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK); } - else { ret = ALT_E_ARG_RANGE; } - break; - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_DDR_DQ: - if ((div <= (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C2, div) == ALT_E_TRUE)) + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + if (restore_0) { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + ///// + + // SDRAM PLL outputs + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C0, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK) { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK); - restore_0 = true; - } + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK); + restore_0 = true; + } - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C0, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_SDRAM_PLL_C5: - case ALT_CLK_H2F_USER2: - if ((div <= (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK + 1)) - && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C5, div) == ALT_E_TRUE)) + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C1, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK) { - wrval = div - 1; - temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - if (temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK); - restore_0 = true; - } + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK); + restore_0 = true; + } + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C1, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - alt_clk_pllcounter_write( ALT_CLKMGR_SDRPLL_VCO_ADDR, - ALT_CLKMGR_SDRPLL_STAT_ADDR, - ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C5, - ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C2, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - /* ------------ Other clock dividers ------------ */ - case ALT_CLK_L3_MP: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2; } + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + if ( (div <= (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C5, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK); + restore_0 = true; + } - if (wrval != UINT32_MAX) + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set } - else { ret = ALT_E_ARG_RANGE; } - break; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + ///// - case ALT_CLK_L3_SP: - // note that the L3MP divider is upstream from the L3SP divider - // and any changes to the former will affect the output of both - if ( div <= (ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 + 1)) - { - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2; } - - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB); - // no clock gate to close and reopen - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_L4_MP: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16; } - - if (wrval != UINT32_MAX) + // Other clock dividers + case ALT_CLK_L3_MP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_L4_SP: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16; } + case ALT_CLK_L3_SP: + // note that the L3MP divider is upstream from the L3SP divider + // and any changes to the former will affect the output of both + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB); + // no clock gate to close and reopen + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_L4_MP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_DBG_AT: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4; } + case ALT_CLK_L4_SP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_DBG: - if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4; } - else + case ALT_CLK_DBG_AT: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK) { - ret = ALT_E_ARG_RANGE; - break; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK); + restore_0 = true; } + alt_replbits_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_DBG: + if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4; } + if (wrval != UINT32_MAX) + { temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); if (temp & ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK) { - // if clock is currently on, gate it off + // if clock is currently on, gate it off alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK); restore_0 = true; } alt_replbits_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK, - wrval << (ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB - 1)); - // account for the fact that the divisor ratios are 2x the value + wrval << (ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB - 1)); + // account for the fact that the divisor ratios are 2x the value alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } ret = ALT_E_SUCCESS; - break; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_DBG_TRACE: - if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16; } + case ALT_CLK_DBG_TRACE: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - if (temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK, - wrval << ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_USB_MP: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16; } + case ALT_CLK_USB_MP: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_SPI_M: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16; } + case ALT_CLK_SPI_M: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_CAN0: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16; } + case ALT_CLK_CAN0: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK) - { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); - } - ret = ALT_E_SUCCESS; + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK); + restore_0 = true; } - else { ret = ALT_E_ARG_RANGE; } - break; + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; - case ALT_CLK_CAN1: - if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1; } - else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2; } - else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4; } - else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8; } - else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16; } + case ALT_CLK_CAN1: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16; } - if (wrval != UINT32_MAX) + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK) { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK) + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_GPIO_DB: // GPIO debounce clock + if (div <= ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK); + restore_0 = true; + } + wrval = div - 1; + alt_replbits_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_MAIN_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + // get the QSPI clock source + restore_0 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; + // and the current enable state + wrval = div - 1; + + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { // if the main_qspi_clk (Main PLL C3 Ouput) input is selected + if (div <= ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK) + { + if (restore_0) { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK); - restore_0 = true; - } - alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + } // gate off the QSPI clock + + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + // if the QSPI clock was gated on (enabled) before, return it to that state } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; - - case ALT_CLK_GPIO_DB: // GPIO debounce clock - if ( div <= ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK) + else { - temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - if (temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK) + ret = ALT_E_ARG_RANGE; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + if (div <= ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK) + { + if (restore_0) { - // if clock is currently on, gate it off - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK); - restore_0 = true; - } - wrval = div - 1; - alt_replbits_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK, - wrval << ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB); - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + } // gate off the QSPI clock + + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); if (restore_0) { - alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + // if the QSPI clock was gated on (enabled) before, return it to that state } ret = ALT_E_SUCCESS; } - else { ret = ALT_E_ARG_RANGE; } - break; + else + { + ret = ALT_E_ARG_RANGE; + } + } + break; - case ALT_CLK_MAIN_QSPI: - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - // get the QSPI clock source - restore_0 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; - // and the current enable state - wrval = div - 1; - - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - { // if the main_qspi_clk (Main PLL C3 Ouput) input is selected - if (div <= ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK) - { - if (restore_0) - { - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - } // gate off the QSPI clock - - alt_clk_pllcounter_write( ALT_CLKMGR_MAINPLL_VCO_ADDR, - ALT_CLKMGR_MAINPLL_STAT_ADDR, - ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C3, - ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - // if the QSPI clock was gated on (enabled) before, return it to that state - } - } - else { ret = ALT_E_ARG_RANGE; } - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - if (div <= ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK) - { - if (restore_0) - { - alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - } // gate off the QSPI clock - - alt_clk_pllcounter_write( ALT_CLKMGR_PERPLL_VCO_ADDR, - ALT_CLKMGR_PERPLL_STAT_ADDR, - ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, - wrval, - ALT_CLK_PLL_RST_BIT_C2, - ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); - - alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); - if (restore_0) - { - alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); - // if the QSPI clock was gated on (enabled) before, return it to that state - } - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_ARG_RANGE; } - } - break; + ///// - default: - break; + default: + ret = ALT_E_BAD_ARG; + break; + } - } // end of switch-case construct return ret; -} // end of alt_clk_divider_set() - Hallelujah ! - - -/****************************************************************************************/ -/* alt_clk_freq_get() returns the output frequency of the specified clock. */ -/****************************************************************************************/ +} +// +// alt_clk_freq_get() returns the output frequency of the specified clock. +// ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, alt_freq_t* freq) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t temp; - uint64_t numer = 0; - uint64_t denom = 1; + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + uint32_t temp = 0; + uint64_t numer = 0; + uint64_t denom = 1; + if (freq == NULL) + { + return ret; + } - if (freq != NULL) + switch (clk) { - switch (clk) + // External Inputs + case ALT_CLK_IN_PIN_OSC1: + case ALT_CLK_OSC1: + numer = alt_ext_clk_paramblok.clkosc1.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_IN_PIN_OSC2: + numer = alt_ext_clk_paramblok.clkosc2.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_F2H_PERIPH_REF: + numer = alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_F2H_SDRAM_REF: + numer = alt_ext_clk_paramblok.sdram.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + ///// + + // PLLs + case ALT_CLK_MAIN_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) { - /* External Inputs */ - case ALT_CLK_IN_PIN_OSC1: - case ALT_CLK_OSC1: - numer = alt_ext_clk_paramblok.clkosc1.freqcur; - // denom = 1 by default - ret = ALT_E_SUCCESS; - break; + temp = alt_ext_clk_paramblok.clkosc1.freqcur; + ret = ALT_E_SUCCESS; + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; - case ALT_CLK_IN_PIN_OSC2: - numer = alt_ext_clk_paramblok.clkosc2.freqcur; - // denom = 1 by default + case ALT_CLK_PERIPHERAL_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) + { + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) + { + temp = alt_ext_clk_paramblok.clkosc1.freqcur; ret = ALT_E_SUCCESS; - break; - - case ALT_CLK_F2H_PERIPH_REF: - numer = alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 by default + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) + { + temp = alt_ext_clk_paramblok.clkosc2.freqcur; ret = ALT_E_SUCCESS; - break; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) + { + temp = alt_ext_clk_paramblok.periph.freqcur; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ERROR; + } + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; - case ALT_CLK_F2H_SDRAM_REF: - numer = alt_ext_clk_paramblok.sdram.freqcur; - // denom = 1 by default + case ALT_CLK_SDRAM_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) + { + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + temp = alt_ext_clk_paramblok.clkosc1.freqcur; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + temp = alt_ext_clk_paramblok.clkosc2.freqcur; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + temp = alt_ext_clk_paramblok.sdram.freqcur; ret = ALT_E_SUCCESS; - break; + } + else + { + ret = ALT_E_ERROR; + } + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; - /* PLLs */ - case ALT_CLK_MAIN_PLL: - if (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) - { - temp = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = ALT_E_SUCCESS; - } - else - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - } - numer = (uint64_t) temp; - // denom = 1 by default - break; + ///// - case ALT_CLK_PERIPHERAL_PLL: - if (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) - { - temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) - { - temp = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) - { - temp = alt_ext_clk_paramblok.clkosc2.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) - { - temp = alt_ext_clk_paramblok.periph.freqcur; - ret = ALT_E_SUCCESS; - } - } - else - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - } - numer = (uint64_t) temp; - // denom = 1 by default - break; + // Main Clock Group + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(clk, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_SDRAM_PLL: - if (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) - { - temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); - if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) - { - temp = alt_ext_clk_paramblok.clkosc1.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) - { - temp = alt_ext_clk_paramblok.clkosc2.freqcur; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) - { - temp = alt_ext_clk_paramblok.sdram.freqcur; - ret = ALT_E_SUCCESS; - } - } - else - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - } - numer = (uint64_t) temp; - // denom = 1 by default - break; - - /* Main Clock Group */ - case ALT_CLK_MAIN_PLL_C0: - case ALT_CLK_MAIN_PLL_C1: - case ALT_CLK_MAIN_PLL_C2: - case ALT_CLK_MAIN_PLL_C3: - case ALT_CLK_MAIN_PLL_C4: - case ALT_CLK_MAIN_PLL_C5: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(clk, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MPU: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_MPU: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MPU_PERIPH: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MPU_PERIPH, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_MPU_PERIPH: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MPU_PERIPH, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_MPU_L2_RAM: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MPU_L2_RAM, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_MPU_L2_RAM: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MPU_L2_RAM, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_L4_MAIN: - case ALT_CLK_L3_MAIN: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_L3_MP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_L3_MP: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_L3_SP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = denom * (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_SP, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_L3_SP: + case ALT_CLK_L4_MP: + ret = alt_clk_divider_get(ALT_CLK_L4_MP, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + temp = ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); + if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) + { ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) + if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = denom * (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_L3_SP, &temp); - denom = denom * (uint64_t) temp; - } - } + denom = denom * (uint64_t) temp; // no real harm if temp is garbage data } - break; - - case ALT_CLK_L4_MP: - ret = alt_clk_divider_get(ALT_CLK_L4_MP, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - temp = ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); - if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - denom = denom * (uint64_t) temp; // no real harm if temp is garbage data - } - } - else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - denom = denom * (uint64_t) temp; - } - } - } - break; - - case ALT_CLK_L4_SP: - ret = alt_clk_divider_get(ALT_CLK_L4_SP, &temp); - if (ret == ALT_E_SUCCESS ) - { - denom = (uint64_t) temp; - temp = ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); - if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); - denom = denom * (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL) // periph_base_clk - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS ) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - denom = denom * (uint64_t) temp; - } - } - } - break; - - case ALT_CLK_DBG_BASE: - case ALT_CLK_DBG_TIMER: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + } + else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + denom = denom * (uint64_t) temp; } - break; + } + } + break; - case ALT_CLK_DBG_AT: + case ALT_CLK_L4_SP: + ret = alt_clk_divider_get(ALT_CLK_L4_SP, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + temp = ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); + if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) + { ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); - denom = denom * (uint64_t) temp; - } + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + denom = denom * (uint64_t) temp; } - break; - - case ALT_CLK_DBG: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + } + else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL) // periph_base_clk + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); if (ret == ALT_E_SUCCESS) { numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = denom * (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG, &temp); - denom = denom * (uint64_t) temp; - } - } + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + denom = denom * (uint64_t) temp; } - break; + } + } + break; - case ALT_CLK_DBG_TRACE: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_DBG_TRACE, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_TIMER: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_MAIN_QSPI: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_DBG_AT: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_MAIN_NAND_SDMMC: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_DBG: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = denom * (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_CFG: - case ALT_CLK_H2F_USER0: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C5, &temp); - denom = (uint64_t) temp; - } - break; - - /* Peripheral Clock Group */ - case ALT_CLK_PERIPHERAL_PLL_C0: - case ALT_CLK_PERIPHERAL_PLL_C1: - case ALT_CLK_PERIPHERAL_PLL_C2: - case ALT_CLK_PERIPHERAL_PLL_C3: - case ALT_CLK_PERIPHERAL_PLL_C4: - case ALT_CLK_PERIPHERAL_PLL_C5: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(clk, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_DBG_TRACE: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_TRACE, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_EMAC0: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C0, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MAIN_QSPI: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_EMAC1: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C1, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_MAIN_NAND_SDMMC: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_USB_MP: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_USB_MP, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_SPI_M: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SPI_M, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + ///// - case ALT_CLK_CAN0: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_CAN0, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + // Peripheral Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(clk, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_CAN1: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_CAN1, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_EMAC0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_GPIO_DB: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); - if (ret == ALT_E_SUCCESS) - { - denom = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_GPIO_DB, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_EMAC1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_H2F_USER1: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C5, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_USB_MP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_USB_MP, &temp); + denom = denom * (uint64_t) temp; + } + } + break; - /* Clocks That Can Switch Between Different Clock Groups */ - case ALT_CLK_SDMMC: - temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) - { - numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 by default - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); - denom = (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); - denom = (uint64_t) temp; - } - } - break; + case ALT_CLK_SPI_M: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SPI_M, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_NAND: - denom = 4; // the absence of a break statement here is not a mistake - case ALT_CLK_NAND_X: - temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) - { - numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 or 4 by default; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); - denom = denom * (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); - denom = denom * (uint64_t) temp; - } - } - break; + case ALT_CLK_CAN0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_CAN0, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_QSPI: - temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); - if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) - { - numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; - // denom = 1 by default; - ret = ALT_E_SUCCESS; - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); - denom = (uint64_t) temp; - } - } - else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) - { - ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C2, &temp); - denom = (uint64_t) temp; - } - } - break; + case ALT_CLK_CAN1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_CAN1, &temp); + denom = denom * (uint64_t) temp; + } + break; - /* SDRAM Clock Group */ - case ALT_CLK_SDRAM_PLL_C0: - case ALT_CLK_DDR_DQS: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C0, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_GPIO_DB: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_GPIO_DB, &temp); + denom = denom * (uint64_t) temp; + } + break; - case ALT_CLK_SDRAM_PLL_C1: - case ALT_CLK_DDR_2X_DQS: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C1, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_H2F_USER1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; - case ALT_CLK_SDRAM_PLL_C2: - case ALT_CLK_DDR_DQ: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C2, &temp); - denom = (uint64_t) temp; - } - break; + /* Clocks That Can Switch Between Different Clock Groups */ + case ALT_CLK_SDMMC: + temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); + denom = (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; - case ALT_CLK_SDRAM_PLL_C5: - case ALT_CLK_H2F_USER2: - ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); - if (ret == ALT_E_SUCCESS) - { - numer = (uint64_t) temp; - ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C5, &temp); - denom = (uint64_t) temp; - } - break; + case ALT_CLK_NAND: + denom = 4; + // the absence of a break statement here is not a mistake + case ALT_CLK_NAND_X: + temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 or 4 by default; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = denom * (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); + denom = denom * (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; - default: - break; + case ALT_CLK_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); + denom = (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C2, &temp); + denom = (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; - } // end of switch-case construct + ///// + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); if (ret == ALT_E_SUCCESS) { - // will not get here if none of above cases match - if (denom > 0) + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C2, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; + + default: + ret = ALT_E_BAD_ARG; + break; + + } // end of switch-case construct + + if (ret == ALT_E_SUCCESS) + { + // will not get here if none of above cases match + if (denom > 0) + { + numer /= denom; + if (numer <= UINT32_MAX) { - numer /= denom; - if (numer <= UINT32_MAX) - { - *freq = (uint32_t) numer; - } - else { ret = ALT_E_ERROR; } + *freq = (uint32_t) numer; + } + else + { + ret = ALT_E_ERROR; } - else { ret = ALT_E_ERROR; } + } + else + { + ret = ALT_E_ERROR; } } + return ret; } - -/****************************************************************************************/ -/* alt_clk_irq_disable() disables one or more of the lock status conditions as */ -/* contributors to the clkmgr_IRQ interrupt signal state. */ -/****************************************************************************************/ - +// +// alt_clk_irq_disable() disables one or more of the lock status conditions as +// contributors to the clkmgr_IRQ interrupt signal state. +// ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - if (!(lock_stat_mask & ALT_CLK_MGR_PLL_LOCK_BITS)) { alt_clrbits_word(ALT_CLKMGR_INTREN_ADDR, lock_stat_mask); - ret = ALT_E_SUCCESS; + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; } - return ret; } - -/****************************************************************************************/ -/* alt_clk_irq_enable() enables one or more of the lock status conditions as */ -/* contributors to the clkmgr_IRQ interrupt signal state. */ -/****************************************************************************************/ - - +// +// alt_clk_irq_enable() enables one or more of the lock status conditions as +// contributors to the clkmgr_IRQ interrupt signal state. +// ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - if (!(lock_stat_mask & ALT_CLK_MGR_PLL_LOCK_BITS)) { alt_setbits_word(ALT_CLKMGR_INTREN_ADDR, lock_stat_mask); - ret = ALT_E_SUCCESS; + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; } - return ret; } +///// -/****************************************************************************************/ -/* alt_clk_group_cfg_raw_get() gets the raw configuration state of the designated */ -/* clock group. */ -/****************************************************************************************/ - +// +// alt_clk_group_cfg_raw_get() gets the raw configuration state of the designated +// clock group. +// ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, - ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg) + ALT_CLK_GROUP_RAW_CFG_t * clk_group_raw_cfg) { - ALT_STATUS_CODE ret = ALT_E_BAD_ARG; - uint32_t *tmp; + clk_group_raw_cfg->verid = alt_read_word(ALT_SYSMGR_SILICONID1_ADDR); + clk_group_raw_cfg->siliid2 = alt_read_word(ALT_SYSMGR_SILICONID2_ADDR); + clk_group_raw_cfg->clkgrpsel = clk_group; - if (clk_group_raw_cfg != NULL) + if (clk_group == ALT_MAIN_PLL_CLK_GRP) { - alt_write_word(&clk_group_raw_cfg->verid, alt_read_word(ALT_SYSMGR_SILICONID1_ADDR)); - alt_write_word(&clk_group_raw_cfg->siliid2, alt_read_word(ALT_SYSMGR_SILICONID2_ADDR)); - alt_indwrite_word(&clk_group_raw_cfg->clkgrpsel, tmp, clk_group); + // Main PLL VCO register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); - if (clk_group == ALT_MAIN_PLL_CLK_GRP) - { - /* Main PLL VCO register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.vco, uint32_t); // compile-time macro that - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.vco, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR)); + // Main PLL Misc register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.misc = alt_read_word(ALT_CLKMGR_MAINPLL_MISC_ADDR); - /* Main PLL Misc register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.misc, uint32_t); // disappears if size is OK - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.misc, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MISC_ADDR)); + // Main PLL C0-C5 Counter registers + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mpuclk = alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations - /* Main PLL C0-C5 Counter registers */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mpuclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mpuclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)); - // doing these as 32-bit reads and writes avoids unnecessary masking operations + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgatclk = alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainqspiclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainnandsdmmcclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.cfgs2fuser0clk = alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mainclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mainclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)); + // Main PLL Enable register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.en = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.dbgatclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.dbgatclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)); + // Main PLL Maindiv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.maindiv = alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mainqspiclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mainqspiclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR)); + // Main PLL Debugdiv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgdiv = alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.mainnandsdmmcclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.mainnandsdmmcclk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR)); + // Main PLL Tracediv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.tracediv = alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.cfgs2fuser0clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.cfgs2fuser0clk, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR)); + // Main PLL L4 Source register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.l4src = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); - /* Main PLL Enable register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.en, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.en, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)); + // Main PLL Status register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_MAINPLL_STAT_ADDR); + // clkgrp.mainpllgrp.stat.outresetack is defined in the ALT_CLKMGR_MAINPLL_STAT_s declaration + // as a const but alt_indwrite_word() overrides that restriction. - /* Main PLL Maindiv register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.maindiv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.maindiv, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + // padding ... + clk_group_raw_cfg->clkgrp.mainpllgrp.raw._pad_0x38_0x40[0] = 0; + clk_group_raw_cfg->clkgrp.mainpllgrp.raw._pad_0x38_0x40[1] = 0; - /* Main PLL Debugdiv register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.dbgdiv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.dbgdiv, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); + return ALT_E_SUCCESS; + } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) + { + // Peripheral PLL VCO register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); - /* Main PLL Tracediv register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.tracediv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.tracediv, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR)); + // Peripheral PLL Misc register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.misc = alt_read_word(ALT_CLKMGR_PERPLL_MISC_ADDR); - /* Main PLL L4 Source register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.l4src, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.l4src, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); + // Peripheral PLL C0-C5 Counters + clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac0clk = alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations - /* Main PLL Status register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.mainpllgrp.stat, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.mainpllgrp.stat, tmp, alt_read_word(ALT_CLKMGR_MAINPLL_STAT_ADDR)); - // clkgrp.mainpllgrp.stat.outresetack is defined in the ALT_CLKMGR_MAINPLL_STAT_s declaration - // as a const but alt_indwrite_word() overrides that restriction. + clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac1clk = alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.perqspiclk = alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.pernandsdmmcclk = alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.perbaseclk = alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.s2fuser1clk = alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR); - /* padding....... */ - clk_group_raw_cfg->clkgrp.mainpllgrp._pad_0x38_0x40[0] = 0; - clk_group_raw_cfg->clkgrp.mainpllgrp._pad_0x38_0x40[1] = 0; - ret = ALT_E_SUCCESS; - } + // Peripheral PLL Enable register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.en = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); - else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) - { - /* Peripheral PLL VCO register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.vco, uint32_t); // compile-time macro - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.vco, tmp, alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + // Peripheral PLL Divider register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.div = alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR); - /* Peripheral PLL Misc register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.misc, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.misc, tmp, alt_read_word(ALT_CLKMGR_PERPLL_MISC_ADDR)); + // Peripheral PLL GPIO Divider register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.gpiodiv = alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR); - /* Peripheral PLL C0-C5 Counters */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.emac0clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.emac0clk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR)); - // doing these as 32-bit reads and writes avoids unnecessary masking operations + // Peripheral PLL Source register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.src = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.emac1clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.emac1clk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR)); + // Peripheral PLL Status register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_PERPLL_STAT_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.perqspiclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.perqspiclk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR)); + // padding ... + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[0] = 0; + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[1] = 0; + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[2] = 0; - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.pernandsdmmcclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.pernandsdmmcclk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR)); + return ALT_E_SUCCESS; + } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) + { + // SDRAM PLL VCO register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.perbaseclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.perbaseclk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR)); + // SDRAM PLL Control register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ctrl = alt_read_word(ALT_CLKMGR_SDRPLL_CTL_ADDR); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.s2fuser1clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.s2fuser1clk, tmp, alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR)); + // SDRAM PLL C0-C2 & C5 Counters + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqsclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations - /* Peripheral PLL Enable register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.en, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.en, tmp, alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)); + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddr2xdqsclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR); + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR); + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.s2fuser2clk = alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR); - /* Peripheral PLL Divider register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.div, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.div, tmp, alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + // SDRAM PLL Enable register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.en = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); - /* Peripheral PLL GPIO Divider register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.gpiodiv, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.gpiodiv, tmp, alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR)); + // SDRAM PLL Status register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_SDRPLL_STAT_ADDR); - /* Peripheral PLL Source register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.src, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.src, tmp, alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} - /* Peripheral PLL Status register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.perpllgrp.stat, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.perpllgrp.stat, tmp, alt_read_word(ALT_CLKMGR_PERPLL_STAT_ADDR)); +// +// alt_clk_group_cfg_raw_set() sets the clock group configuration. +// +ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t * clk_group_raw_cfg) +{ + // test for matching silicon ID, but not for matching silicon revision number + if (ALT_SYSMGR_SILICONID1_ID_GET(alt_read_word(ALT_SYSMGR_SILICONID1_ADDR)) != + ALT_SYSMGR_SILICONID1_ID_GET(clk_group_raw_cfg->verid)) + { + return ALT_E_BAD_VERSION; + } - /* padding....... */ - clk_group_raw_cfg->clkgrp.perpllgrp._pad_0x34_0x40[0] = 0; - clk_group_raw_cfg->clkgrp.perpllgrp._pad_0x34_0x40[1] = 0; - clk_group_raw_cfg->clkgrp.perpllgrp._pad_0x34_0x40[2] = 0; - ret = ALT_E_SUCCESS; - } + // get the PLL ID + ALT_CLK_GRP_t clk_group = clk_group_raw_cfg->clkgrpsel; + ALT_CLK_t pll; - else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) + if (clk_group == ALT_MAIN_PLL_CLK_GRP) { pll = ALT_CLK_MAIN_PLL; } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) { pll = ALT_CLK_PERIPHERAL_PLL; } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) { pll = ALT_CLK_SDRAM_PLL; } + else + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // if the PLL isn't in bypass mode, put it in bypass mode + bool byp = false; + if (alt_clk_pll_is_bypassed(pll) == ALT_E_FALSE) + { + status = alt_clk_pll_bypass_enable(pll, false); + if (status != ALT_E_SUCCESS) { - /* SDRAM PLL VCO register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.vco, uint32_t); // compile-time macro - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.vco, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + return status; + } - /* SDRAM PLL Control register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ctrl, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ctrl, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_CTL_ADDR)); + byp = true; + } - /* SDRAM PLL C0-C2 & C5 Counters */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqsclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqsclk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); - // doing these as 32-bit reads and writes avoids unnecessary masking operations + // now write the values in the ALT_CLK_GROUP_RAW_CFG_t structure to the registers + if (clk_group == ALT_MAIN_PLL_CLK_GRP) + { + // Main PLL VCO register + alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.vco & + ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ddr2xdqsclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ddr2xdqsclk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); + // Main PLL Misc register + alt_write_word(ALT_CLKMGR_MAINPLL_MISC_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.misc); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqclk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqclk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); + // Main PLL C0-C5 Counter registers + alt_write_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mpuclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainclk); + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgatclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainqspiclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainnandsdmmcclk); + alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.cfgs2fuser0clk); - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.s2fuser2clk, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.s2fuser2clk, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); + // Main PLL Counter Enable register + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.en); - /* SDRAM PLL Enable register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.en, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.en, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR)); + // Main PLL Maindiv register + alt_write_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.maindiv); - /* SDRAM PLL Status register */ - alt_check_struct_size(clk_group_raw_cfg->clkgrp.sdrpllgrp.stat, uint32_t); - alt_indwrite_word(&clk_group_raw_cfg->clkgrp.sdrpllgrp.stat, tmp, alt_read_word(ALT_CLKMGR_SDRPLL_STAT_ADDR)); + // Main PLL Debugdiv register + alt_write_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgdiv); - ret = ALT_E_SUCCESS; - } - } - return ret; -} + // Main PLL Tracediv register + alt_write_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.tracediv); + // Main PLL L4 Source register + alt_write_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.l4src); + } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) + { + // Peripheral PLL VCO register + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.vco & + ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now + + // Peripheral PLL Misc register + alt_write_word(ALT_CLKMGR_PERPLL_MISC_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.misc); + + // Peripheral PLL C0-C5 Counters + alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac0clk); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac1clk); + alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.perqspiclk); + alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.pernandsdmmcclk); + alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.perbaseclk); + alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.s2fuser1clk); + + // Peripheral PLL Counter Enable register + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.en); + + // Peripheral PLL Divider register + alt_write_word(ALT_CLKMGR_PERPLL_DIV_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.div); + + // Peripheral PLL GPIO Divider register + alt_write_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.gpiodiv); + + // Peripheral PLL Source register + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.src); + } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) + { + // SDRAM PLL VCO register + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.vco & + ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now + + // SDRAM PLL Control register + alt_write_word(ALT_CLKMGR_SDRPLL_CTL_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ctrl); + + // SDRAM PLL C0-C2 & C5 Counters + alt_write_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqsclk); + alt_write_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddr2xdqsclk); + alt_write_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqclk); + alt_write_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.s2fuser2clk); + + // SDRAM PLL Counter Enable register + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.en); + } -/****************************************************************************************/ -/* alt_clk_group_cfg_raw_set() sets the clock group configuration. */ -/****************************************************************************************/ + // if PLL was not bypassed before, restore that state + if (byp) + { + status = alt_clk_pll_bypass_disable(pll); + } -ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg) -{ - ALT_STATUS_CODE ret = ALT_E_ERROR; - ALT_CLK_GRP_t clk_group; - ALT_CLK_t pll = ALT_CLK_UNKNOWN; - bool byp = false; - uint32_t *tmp; + return status; +} +// +// alt_clk_id_to_string() converts a clock ID to a text string. +// +ALT_STATUS_CODE alt_clk_id_to_string(ALT_CLK_t clk_id, char * output, size_t size) +{ + char * name = NULL; - if (clk_group_raw_cfg != NULL) + switch (clk_id) { - // test for matching silicon ID, but not for matching silicon revision number - if (ALT_SYSMGR_SILICONID1_ID_GET(alt_read_word(ALT_SYSMGR_SILICONID1_ADDR)) == - ALT_SYSMGR_SILICONID1_ID_GET(clk_group_raw_cfg->verid)) - { - // get the PLL ID - clk_group = clk_group_raw_cfg->clkgrpsel; - if (clk_group == ALT_MAIN_PLL_CLK_GRP) { pll = ALT_CLK_MAIN_PLL; } - else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) { pll = ALT_CLK_PERIPHERAL_PLL; } - else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) { pll = ALT_CLK_SDRAM_PLL; } - else { return ret; } - if (pll == ALT_CLK_UNKNOWN) { return ret; } - - // if the PLL isn't in bypass mode, put it in bypass mode - ret = alt_clk_pll_is_bypassed(pll); - if (ret == ALT_E_FALSE) - { - ret = alt_clk_pll_bypass_enable(pll, false); - byp = true; - } + case ALT_CLK_IN_PIN_OSC1: + name = "IN_PIN_OSC1"; + break; + case ALT_CLK_IN_PIN_OSC2: + name = "IN_PIN_OSC2"; + break; + // FPGA Clock Sources External to HPS + case ALT_CLK_F2H_PERIPH_REF: + name = "F2H_PERIPH_REF"; + break; + case ALT_CLK_F2H_SDRAM_REF: + name = "F2H_SDRAM_REF"; + break; - // now write the values in the ALT_CLK_GROUP_RAW_CFG_t structure to the registers - if (clk_group == ALT_MAIN_PLL_CLK_GRP) - { - /* Main PLL VCO register */ - tmp = (uint32_t *) &clk_group_raw_cfg->clkgrp.mainpllgrp.vco; - alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, *tmp & - (ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK)); - // the outreset and outresetall bits were probably clear when the - // state was saved, but make sure they're clear now - - /* Main PLL Misc register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_MISC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.misc); - - /* Main PLL C0-C5 Counter registers */ - alt_indread_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mpuclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mainclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.dbgatclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mainqspiclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.mainnandsdmmcclk); - alt_indread_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.cfgs2fuser0clk); - - /* Main PLL Counter Enable register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_EN_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.en); - /* Main PLL Maindiv register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.maindiv); - /* Main PLL Debugdiv register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.dbgdiv); - /* Main PLL Tracediv register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.tracediv); - /* Main PLL L4 Source register */ - alt_indread_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.mainpllgrp.l4src); - - // remove bypass - ret = ALT_E_SUCCESS; - } + // Other Clock Sources External to HPS + case ALT_CLK_IN_PIN_JTAG: + name = "IN_PIN_JTAG"; + break; + case ALT_CLK_IN_PIN_ULPI0: + name = "IN_PIN_ULPI0"; + break; + case ALT_CLK_IN_PIN_ULPI1: + name = "IN_PIN_ULPI1"; + break; + case ALT_CLK_IN_PIN_EMAC0_RX: + name = "IN_PIN_EMAC0_RX"; + break; + case ALT_CLK_IN_PIN_EMAC1_RX: + name = "IN_PIN_EMAC1_RX"; + break; - else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) - { - /* Peripheral PLL VCO register */ - tmp = (uint32_t *) &clk_group_raw_cfg->clkgrp.perpllgrp.vco; - alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, *tmp & (ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK)); - // the outreset and outresetall bits were probably clear when the - // state was saved, but make sure they're clear now + // PLLs + case ALT_CLK_MAIN_PLL: + name = "MAIN_PLL"; + break; + case ALT_CLK_PERIPHERAL_PLL: + name = "PERIPHERAL_PLL"; + break; + case ALT_CLK_SDRAM_PLL: + name = "SDRAM_PLL"; + break; - /* Peripheral PLL Misc register */ - alt_indread_word(ALT_CLKMGR_PERPLL_MISC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.misc); + // OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived + // directly from the osc_clk_1_HPS pin + case ALT_CLK_OSC1: + name = "OSC1"; + break; - /* Peripheral PLL C0-C5 Counters */ - alt_indread_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.emac0clk); - alt_indread_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.emac1clk); - alt_indread_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.perqspiclk); - alt_indread_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.pernandsdmmcclk); - alt_indread_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.perbaseclk); - alt_indread_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.s2fuser1clk); + // Main Clock Group - The following clocks are derived from the Main PLL. + case ALT_CLK_MAIN_PLL_C0: + name = "MAIN_PLL_C0"; + break; + case ALT_CLK_MAIN_PLL_C1: + name = "MAIN_PLL_C1"; + break; + case ALT_CLK_MAIN_PLL_C2: + name = "MAIN_PLL_C2"; + break; + case ALT_CLK_MAIN_PLL_C3: + name = "MAIN_PLL_C3"; + break; + case ALT_CLK_MAIN_PLL_C4: + name = "MAIN_PLL_C4"; + break; + case ALT_CLK_MAIN_PLL_C5: + name = "MAIN_PLL_C5"; + break; + case ALT_CLK_MPU: + name = "MPU"; + break; + case ALT_CLK_MPU_L2_RAM: + name = "MPU_L2_RAM"; + break; + case ALT_CLK_MPU_PERIPH: + name = "MPU_PERIPH"; + break; + case ALT_CLK_L3_MAIN: + name = "L3_MAIN"; + break; + case ALT_CLK_L3_MP: + name = "L3_MP"; + break; + case ALT_CLK_L3_SP: + name = "L3_SP"; + break; + case ALT_CLK_L4_MAIN: + name = "L4_MAIN"; + break; + case ALT_CLK_L4_MP: + name = "L4_MP"; + break; + case ALT_CLK_L4_SP: + name = "L4_SP"; + break; + case ALT_CLK_DBG_BASE: + name = "DBG_BASE"; + break; + case ALT_CLK_DBG_AT: + name = "DBG_AT"; + break; + case ALT_CLK_DBG_TRACE: + name = "DBG_TRACE"; + break; + case ALT_CLK_DBG_TIMER: + name = "DBG_TIMER"; + break; + case ALT_CLK_DBG: + name = "DBG"; + break; + case ALT_CLK_MAIN_QSPI: + name = "MAIN_QSPI"; + break; + case ALT_CLK_MAIN_NAND_SDMMC: + name = "MAIN_NAND_SDMMC"; + break; + case ALT_CLK_CFG: + name = "CFG"; + break; + case ALT_CLK_H2F_USER0: + name = "H2F_USER0"; + break; - /* Peripheral PLL Counter Enable register */ - alt_indread_word(ALT_CLKMGR_PERPLL_EN_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.en); + // Peripherals Clock Group - The following clocks are derived from the Peripheral PLL. + case ALT_CLK_PERIPHERAL_PLL_C0: + name = "PERIPHERAL_PLL_C0"; + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + name = "PERIPHERAL_PLL_C1"; + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + name = "PERIPHERAL_PLL_C2"; + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + name = "PERIPHERAL_PLL_C3"; + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + name = "PERIPHERAL_PLL_C4"; + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + name = "PERIPHERAL_PLL_C5"; + break; + case ALT_CLK_USB_MP: + name = "USB_MP"; + break; + case ALT_CLK_SPI_M: + name = "SPI_M"; + break; + case ALT_CLK_QSPI: + name = "QSPI"; + break; + case ALT_CLK_NAND_X: + name = "NAND_X"; + break; + case ALT_CLK_NAND: + name = "NAND"; + break; + case ALT_CLK_SDMMC: + name = "SDMMC"; + break; + case ALT_CLK_EMAC0: + name = "EMAC0"; + break; + case ALT_CLK_EMAC1: + name = "EMAC1"; + break; + case ALT_CLK_CAN0: + name = "CAN0"; + break; + case ALT_CLK_CAN1: + name = "CAN1"; + break; + case ALT_CLK_GPIO_DB: + name = "GPIO_DB"; + break; + case ALT_CLK_H2F_USER1: + name = "H2F_USER1"; + break; - /* Peripheral PLL Divider register */ - alt_indread_word(ALT_CLKMGR_PERPLL_DIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.div); + // SDRAM Clock Group - The following clocks are derived from the SDRAM PLL. + case ALT_CLK_SDRAM_PLL_C0: + name = "SDRAM_PLL_C0"; + break; + case ALT_CLK_SDRAM_PLL_C1: + name = "SDRAM_PLL_C1"; + break; + case ALT_CLK_SDRAM_PLL_C2: + name = "SDRAM_PLL_C2"; + break; + case ALT_CLK_SDRAM_PLL_C3: + name = "SDRAM_PLL_C3"; + break; + case ALT_CLK_SDRAM_PLL_C4: + name = "SDRAM_PLL_C4"; + break; + case ALT_CLK_SDRAM_PLL_C5: + name = "SDRAM_PLL_C5"; + break; + case ALT_CLK_DDR_DQS: + name = "DDR_DQS"; + break; + case ALT_CLK_DDR_2X_DQS: + name = "DDR_2X_DQS"; + break; + case ALT_CLK_DDR_DQ: + name = "DDR_DQ"; + break; + case ALT_CLK_H2F_USER2: + name = "H2F_USER2"; + break; - /* Peripheral PLL GPIO Divider register */ - alt_indread_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.gpiodiv); + // Clock Output Pins + case ALT_CLK_OUT_PIN_EMAC0_TX: + name = "OUT_PIN_EMAC0_TX"; + break; + case ALT_CLK_OUT_PIN_EMAC1_TX: + name = "OUT_PIN_EMAC1_TX"; + break; + case ALT_CLK_OUT_PIN_SDMMC: + name = "OUT_PIN_SDMMC"; + break; + case ALT_CLK_OUT_PIN_I2C0_SCL: + name = "OUT_PIN_I2C0_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C1_SCL: + name = "OUT_PIN_I2C1_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C2_SCL: + name = "OUT_PIN_I2C2_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C3_SCL: + name = "OUT_PIN_I2C3_SCL"; + break; + case ALT_CLK_OUT_PIN_SPIM0: + name = "OUT_PIN_SPIM0"; + break; + case ALT_CLK_OUT_PIN_SPIM1: + name = "OUT_PIN_SPIM1"; + break; + case ALT_CLK_OUT_PIN_QSPI: + name = "OUT_PIN_QSPI"; + break; + case ALT_CLK_UNKNOWN: + name = "UNKNOWN"; + break; - /* Peripheral PLL Source register */ - alt_indread_word(ALT_CLKMGR_PERPLL_SRC_ADDR, tmp, &clk_group_raw_cfg->clkgrp.perpllgrp.src); + // do *not* put a 'default' statement here. Then the compiler will throw + // an error if another clock id enum is added if the corresponding + // string is not added to this function. + } - ret = ALT_E_SUCCESS; - } - else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) - { - /* SDRAM PLL VCO register */ - tmp = (uint32_t *) &clk_group_raw_cfg->clkgrp.sdrpllgrp.vco; - alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, *tmp & (ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK)); - // the outreset and outresetall bits were probably clear when the - // state was saved, but make sure they're clear now + if (name != NULL) + { + snprintf(output, size, "ALT_CLK_%s", name); + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} - /* SDRAM PLL Control register */ - alt_indread_word(ALT_CLKMGR_SDRPLL_CTL_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ctrl); - /* SDRAM PLL C0-C2 & C5 Counters */ - alt_indread_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqsclk); - alt_indread_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ddr2xdqsclk); - alt_indread_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.ddrdqclk); - alt_indread_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.s2fuser2clk); +// +// alt_clk_pll_cntr_maxfreq_recalc() recalculate the maxmum frequency of the specified clock. +// +ALT_STATUS_CODE alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_t clk, ALT_PLL_CNTR_FREQMAX_t * maxfreq) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + alt_freq_t freq; - /* SDRAM PLL Counter Enable register */ - alt_indread_word(ALT_CLKMGR_SDRPLL_EN_ADDR, tmp, &clk_group_raw_cfg->clkgrp.sdrpllgrp.en); + ret = alt_clk_freq_get(clk, &freq); - ret = ALT_E_SUCCESS; - } - else { ret = ALT_E_BAD_ARG; } - } - else { ret = ALT_E_BAD_VERSION; } + if (ret == ALT_E_SUCCESS) + { + + switch (clk) + { + // Main Clock Group + case ALT_CLK_MAIN_PLL_C0: + maxfreq->MainPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C1: + maxfreq->MainPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C2: + maxfreq->MainPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C3: + maxfreq->MainPLL_C3 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C3 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C4: + maxfreq->MainPLL_C4 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C4 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C5: + maxfreq->MainPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C5 = %10d\n", (unsigned int)freq); + break; + + // Peripheral Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + maxfreq->PeriphPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + maxfreq->PeriphPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + maxfreq->PeriphPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + maxfreq->PeriphPLL_C3 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C3 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + maxfreq->PeriphPLL_C4 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C4 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + maxfreq->PeriphPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C5 = %10d\n", (unsigned int)freq); + break; + + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + maxfreq->SDRAMPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C1: + maxfreq->SDRAMPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C2: + maxfreq->SDRAMPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C5: + maxfreq->SDRAMPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C5 = %10d\n", (unsigned int)freq); + break; + default: + ret = ALT_E_BAD_ARG; + printf("bad max frequency parameter\n"); + break; + } // end of switch-case construct } - // if PLL was not bypassed before, restore that state - if (byp) { ret = alt_clk_pll_bypass_disable(pll); } return ret; } + +// +// u-boot preloader actually initialize clock manager circuitry +// +// alt_clk_clkmgr_init() attempt to fix the pll counter max frequencies, since +// thses frequencies are not known in advance until u-boot programmed clock manager. +// +ALT_STATUS_CODE alt_clk_clkmgr_init(void) +{ + ALT_STATUS_CODE ret = ALT_E_SUCCESS; + ALT_STATUS_CODE status ; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C3,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C4,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C3,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C4,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + + return ret; +} + diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c index e2b0135..d5b6afa 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c @@ -35,6 +35,7 @@ #include "socal/hps.h" #include "socal/socal.h" #include "socal/alt_gpio.h" +#include "socal/alt_rstmgr.h" #include "hwlib.h" #include "alt_generalpurpose_io.h" @@ -53,6 +54,37 @@ /****************************************************************************************/ +/* alt_gpio_init() initializes the GPIO modules */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_init(void) +{ + // put GPIO modules into system manager reset if not already there + alt_gpio_uninit(); + // release GPIO modules from system reset (w/ two-instruction delay) + alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK, 0); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_uninit() uninitializes the GPIO modules */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_uninit(void) +{ + // put all GPIO modules into system manager reset + alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK, + ALT_GPIO_BITMASK); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ /* alt_gpio_port_datadir_set() sets the specified GPIO data bits to use the data */ /* direction(s) specified. 0 = input (default). 1 = output. */ /****************************************************************************************/ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am index 4e3b586..4093831 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am @@ -5,14 +5,14 @@ $(srcdir)/preinstall.am: Makefile.am $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am endif -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - all-am: $(PREINSTALL_FILES) PREINSTALL_FILES = CLEANFILES = $(PREINSTALL_FILES) +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + all-local: $(TMPINSTALL_FILES) TMPINSTALL_FILES = @@ -183,6 +183,10 @@ $(PROJECT_INCLUDE)/bsp/hwlib.h: hwlib/include/hwlib.h $(PROJECT_INCLUDE)/bsp/$(d $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwlib.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwlib.h +$(PROJECT_INCLUDE)/bsp/socal/alt_acpidmap.h: hwlib/include/socal/alt_acpidmap.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_acpidmap.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_acpidmap.h + $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h: hwlib/include/socal/alt_clkmgr.h $(PROJECT_INCLUDE)/bsp/socal/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/socal/alt_clkmgr.h From sebastian.huber at embedded-brains.de Wed Aug 27 10:36:16 2014 From: sebastian.huber at embedded-brains.de (Sebastian Huber) Date: Wed, 27 Aug 2014 10:36:16 -0000 Subject: [rtems commit] arm/lm3s3749: Add tests that do not fit. In-Reply-To: <20140827095637.B08FD70080E@git.rtems.org> References: <20140827095637.B08FD70080E@git.rtems.org> Message-ID: <53FDB494.9010504@embedded-brains.de> On 27/08/14 11:56, Chris Johns wrote: > Module: rtems > Branch: master > Commit: 614a0889b664a9309c3a966e5f0f494d4b94b62f > Changeset:http://git.rtems.org/rtems/commit/?id=614a0889b664a9309c3a966e5f0f494d4b94b62f > > Author: Chris Johns > Date: Wed Aug 27 20:04:26 2014 +1000 > > arm/lm3s3749: Add tests that do not fit. > > You need --enable-c++ for the c++ tests. I think you need --enable-c++ only for the rtems++ stuff. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.huber at embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine gesch?ftliche Mitteilung im Sinne des EHUG.