[rtems-tools commit] Add cpu registers to task output.
Chris Johns
chrisj at rtems.org
Sun Aug 24 23:45:35 UTC 2014
Module: rtems-tools
Branch: master
Commit: bd0b98d55e4bcb29ce0631e6c717f873739bf80b
Changeset: http://git.rtems.org/rtems-tools/commit/?id=bd0b98d55e4bcb29ce0631e6c717f873739bf80b
Author: Dhananjay Balan <mb.dhananjay at gmail.com>
Date: Mon Aug 26 22:30:25 2013 +0530
Add cpu registers to task output.
---
tools/gdb/python/classic.py | 5 ++
tools/gdb/python/sparc.py | 135 ++++++++++++++++++++++++++-----------------
2 files changed, 86 insertions(+), 54 deletions(-)
diff --git a/tools/gdb/python/classic.py b/tools/gdb/python/classic.py
index 261f648..e492657 100644
--- a/tools/gdb/python/classic.py
+++ b/tools/gdb/python/classic.py
@@ -16,6 +16,7 @@ import threads
import watchdog
import heaps
import supercore
+import sparc
class attribute:
"""The Classic API attribute."""
@@ -155,6 +156,8 @@ class task:
self.task = \
threads.control(self.object)
self.wait_info = self.task.wait_info()
+ # ToDo: Insert platform dep. code here.
+ self.regs = sparc.register(self.object['Registers'])
def show(self, from_tty):
print ' Name:', self.task.name()
@@ -163,6 +166,8 @@ class task:
print ' Real:', self.task.real_priority()
print ' Preempt:', self.task.preemptible()
print ' T Budget:', self.task.cpu_time_budget()
+ print ' Regsters:'
+ self.regs.show()
class message_queue:
diff --git a/tools/gdb/python/sparc.py b/tools/gdb/python/sparc.py
index b0e251d..70ef5d3 100644
--- a/tools/gdb/python/sparc.py
+++ b/tools/gdb/python/sparc.py
@@ -4,72 +4,74 @@
from helper import test_bit
-class psr:
- '''status register'''
- sv_table = {
- 0 : 'user',
- 1 : 'superviser'
- }
+class register:
+ '''SPARC Registers'''
- def __init__(self, psr):
- self.psr = psr
+ class psr:
+ '''status register'''
- def current_window(self):
- return int(self.psr & 0xf)
+ sv_table = {
+ 0 : 'user',
+ 1 : 'superviser'
+ }
- def traps(self):
- return test_bit(self.psr, 5)
- def prev_superviser(self):
- return int(test_bit(self.psr,6))
+ def __init__(self, psr):
+ self.psr = psr
- def superviser(self):
- return int(test_bit(self.psr,7))
+ def current_window(self):
+ return int(self.psr & 0xf)
- def interrupt_level(self):
- # bits 8 to 11
- return (self.spr & 0x780) >> 7
+ def traps(self):
+ return test_bit(self.psr, 5)
- def floating_point_status(self):
- return test_bit(self.psr, 12)
+ def prev_superviser(self):
+ return int(test_bit(self.psr,6))
- def coproc_status(self):
- return test_bit(self.psr,13)
+ def superviser(self):
+ return int(test_bit(self.psr,7))
- def carry(self):
- return test_bit(self.psr, 20)
+ def interrupt_level(self):
+ # bits 8 to 11
+ return (self.spr & 0x780) >> 7
- def overflow(self):
- return test_bit(self.psr, 21)
+ def floating_point_status(self):
+ return test_bit(self.psr, 12)
- def zero(self):
- return test_bit(self.psr, 22)
+ def coproc_status(self):
+ return test_bit(self.psr,13)
- def icc(self):
- n = test_bit(self.psr,23)
- z = test_bit(self.psr,22)
- v = test_bit(self.psr,21)
- c = test_bit(self.psr,20)
- return (n,z,v,c)
+ def carry(self):
+ return test_bit(self.psr, 20)
- def to_string(self):
- val = " Status Register"
- val += "\n R Window : " + str(self.current_window())
- val += "\n Traps Enabled : " + str(self.traps())
- val += "\n Flaoting Point : " + str(self.floating_point_status())
- val += "\n Coprocessor : " + str(self.coproc_status())
- val += "\n Processor Mode : " + self.sv_table[self.superviser()]
- val += "\n Prev. Mode : " + self.sv_table[self.superviser()]
- val += "\n Carry : " + str(int(self.carry()))
- val += "\n Overflow : " + str(int(self.overflow()))
- val += "\n Zero : " + str(int(self.zero()))
+ def overflow(self):
+ return test_bit(self.psr, 21)
- return val
+ def zero(self):
+ return test_bit(self.psr, 22)
-class register:
- '''SPARC Registers'''
+ def icc(self):
+ n = test_bit(self.psr,23)
+ z = test_bit(self.psr,22)
+ v = test_bit(self.psr,21)
+ c = test_bit(self.psr,20)
+ return (n,z,v,c)
+
+ def to_string(self):
+ val = " Status Register"
+ val += "\n R Window : " + str(self.current_window())
+ val += "\n Traps Enabled : " + str(self.traps())
+ val += "\n Flaoting Point : " + str(self.floating_point_status())
+ val += "\n Coprocessor : " + str(self.coproc_status())
+ val += "\n Processor Mode : " + self.sv_table[self.superviser()]
+ val += "\n Prev. Mode : " + self.sv_table[self.superviser()]
+ val += "\n Carry : " + str(int(self.carry()))
+ val += "\n Overflow : " + str(int(self.overflow()))
+ val += "\n Zero : " + str(int(self.zero()))
+
+ return val
def __init__(self,reg):
self.reg = reg
@@ -108,8 +110,33 @@ class register:
val.append(self.reg['o'+str(i)])
return val
-
-
-
-
-
+ def status(self):
+ return self.psr(self.reg['psr'])
+
+ def show(self):
+ print ' Global Regs:',
+ print ' [',
+ for i in self.global_regs():
+ print str(i)+',',
+ print '\b\b ]'
+
+ print ' Local Regs:',
+ print ' [',
+ for i in self.local_regs():
+ print str(i)+',',
+ print '\b\b ]'
+
+ print ' In Regs:',
+ print ' [',
+ for i in self.in_regs():
+ print str(i)+',',
+ print '\b\b ]'
+
+ print ' Out Regs:',
+ print ' [',
+ for i in self.out_regs():
+ print str(i)+',',
+ print '\b\b ]'
+
+ sr = self.status()
+ print sr.to_string()
\ No newline at end of file
More information about the vc
mailing list