[rtems commit] bsps/sparc: Order load/store by increasing offsets

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    f715433ae9ee51d496d5c4a0e9b5a7f74bc14268
Changeset: http://git.rtems.org/rtems/commit/?id=f715433ae9ee51d496d5c4a0e9b5a7f74bc14268

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Tue Feb  4 16:44:50 2014 +0100

bsps/sparc: Order load/store by increasing offsets

This may increase the cache hit performance.

---

 c/src/lib/libbsp/sparc/shared/irq_asm.S |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S b/c/src/lib/libbsp/sparc/shared/irq_asm.S
index 773a8ea..de7ef90 100644
--- a/c/src/lib/libbsp/sparc/shared/irq_asm.S
+++ b/c/src/lib/libbsp/sparc/shared/irq_asm.S
@@ -422,15 +422,15 @@ save_isf:
 
 	GET_SELF_CPU_CONTROL %l5, %l7
 
-	ld       [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
-	ld       [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
-
-        add      %l6, 1, %l6
-        st       %l6, [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
+        ld       [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
+        ld       [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
 
         add      %l7, 1, %l7
         st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
 
+        add      %l6, 1, %l6
+        st       %l6, [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
+
         /*
          *  If ISR nest level was zero (now 1), then switch stack.
          */
@@ -581,11 +581,11 @@ dont_fix_pil2:
          *    l7 = _ISR_Nest_level value
          */
 
+        st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
+
         sub      %l6, 1, %l6
         st       %l6, [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
 
-        st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
-
         /*
          *  If dispatching is disabled (includes nested interrupt case),
          *  then do a "simple" exit.