[rtems commit] bsp/altera-cyclone-v: Enable unified L2 cache

Sebastian Huber sebh at rtems.org
Fri Jun 6 06:34:43 UTC 2014


Module:    rtems
Branch:    master
Commit:    1468d70f7938476f4eba65f7e4d322550ae1a7c9
Changeset: http://git.rtems.org/rtems/commit/?id=1468d70f7938476f4eba65f7e4d322550ae1a7c9

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Thu Jun  5 10:03:55 2014 +0200

bsp/altera-cyclone-v: Enable unified L2 cache

---

 .../libbsp/arm/altera-cyclone-v/startup/bspsmp.c   |    9 ++++++++-
 .../arm/altera-cyclone-v/startup/bspstarthooks.c   |    4 ++++
 2 files changed, 12 insertions(+), 1 deletions(-)

diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c
index 3b894b4..591e1cd 100644
--- a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c
@@ -55,7 +55,11 @@ bool _CPU_SMP_Start_processor(uint32_t cpu_index)
       ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK
     );
 
-    started = true;
+    /*
+     * Wait for secondary processor to complete its basic initialization so
+     * that we can enable the unified L2 cache.
+     */
+    started = _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0);
   } else {
     started = false;
   }
@@ -76,6 +80,9 @@ void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
       NULL
     );
     assert(sc == RTEMS_SUCCESSFUL);
+
+    /* Enable unified L2 cache */
+    rtems_cache_enable_data();
   }
 }
 
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c
index d913c8e..e543ea2 100644
--- a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c
@@ -104,5 +104,9 @@ BSP_START_TEXT_SECTION void bsp_start_hook_1( void )
   arm_a9mpcore_start_hook_1();
   bsp_start_copy_sections();
   setup_mmu_and_cache();
+#ifndef RTEMS_SMP
+  /* Enable unified L2 cache */
+  rtems_cache_enable_data();
+#endif
   bsp_start_clear_bss();
 }




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