[rtems commit] bsp/arm: Add SCU errata handling for L2C-310 cache
Sebastian Huber
sebh at rtems.org
Thu Mar 13 15:15:49 UTC 2014
Module: rtems
Branch: master
Commit: 0b74e10fff05de92b15bf29de8608951cb5370fa
Changeset: http://git.rtems.org/rtems/commit/?id=0b74e10fff05de92b15bf29de8608951cb5370fa
Author: Ralf Kirchner <ralf.kirchner at embedded-brains.de>
Date: Mon Feb 17 11:57:19 2014 +0100
bsp/arm: Add SCU errata handling for L2C-310 cache
---
.../libbsp/arm/shared/include/arm-a9mpcore-regs.h | 5 ++-
.../libbsp/arm/shared/include/arm-a9mpcore-start.h | 41 +++++++++++++++----
2 files changed, 36 insertions(+), 10 deletions(-)
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h
index 28640d2..861d1ae 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h
+++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h
@@ -58,7 +58,10 @@ typedef struct {
#define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15)
#define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */
#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
- uint32_t reserved_10[12];
+ uint32_t reserved_09[8];
+ uint32_t diagn_ctrl;
+#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0)
+ uint32_t reserved_10[3];
uint32_t fltstart;
uint32_t fltend;
uint32_t reserved_48[2];
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
index c89ca9d..2508bf4 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
+++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
@@ -30,6 +30,7 @@
#include <bsp.h>
#include <bsp/start.h>
#include <bsp/arm-a9mpcore-regs.h>
+#include <bsp/arm-errata.h>
#ifdef __cplusplus
extern "C" {
@@ -79,25 +80,45 @@ BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_scu_invalidate(
scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4);
}
-BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void)
+BSP_START_TEXT_SECTION static void inline
+arm_a9mpcore_start_errata_764369_handler(volatile a9mpcore_scu *scu)
{
#ifdef RTEMS_SMP
- volatile a9mpcore_scu *scu = (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
- uint32_t cpu_id;
- uint32_t actlr;
+ if (arm_errata_is_applicable_processor_errata_764369()) {
+ scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE;
+ }
+#endif
+}
- /* Enable Snoop Control Unit (SCU) */
+BSP_START_TEXT_SECTION static inline
+arm_a9mpcore_start_scu_enable(volatile a9mpcore_scu *scu)
+{
+ arm_a9mpcore_start_errata_764369_handler(scu);
scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN;
+}
+BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void)
+{
+ volatile a9mpcore_scu *scu =
+ (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
+ uint32_t cpu_id;
+
+ arm_a9mpcore_start_scu_enable(scu);
+
+#ifdef RTEMS_SMP
/* Enable cache coherency support for this processor */
- actlr = arm_cp15_get_auxiliary_control();
- actlr |= ARM_CORTEX_A9_ACTL_SMP;
- arm_cp15_set_auxiliary_control(actlr);
+ {
+ uint32_t actlr = arm_cp15_get_auxiliary_control();
+ actlr |= ARM_CORTEX_A9_ACTL_SMP;
+ arm_cp15_set_auxiliary_control(actlr);
+ }
+#endif
cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf);
+#ifdef RTEMS_SMP
if (cpu_id != 0) {
arm_a9mpcore_start_set_vector_base();
@@ -116,7 +137,9 @@ BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void)
);
/* FIXME: Sharing the translation table between processors is brittle */
- arm_cp15_set_translation_table_base((uint32_t *) bsp_translation_table_base);
+ arm_cp15_set_translation_table_base(
+ (uint32_t *) bsp_translation_table_base
+ );
ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
arm_cp15_set_control(ctrl);
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