[rtems commit] bsp/altera-cyclone-v: Add Alteras hwlib

Sebastian Huber sebh at rtems.org
Thu Mar 13 15:15:49 UTC 2014


Module:    rtems
Branch:    master
Commit:    0b03ca39a45bfa55b15208576f693162787c9281
Changeset: http://git.rtems.org/rtems/commit/?id=0b03ca39a45bfa55b15208576f693162787c9281

Author:    Ralf Kirchner <ralf.kirchner at embedded-brains.de>
Date:      Fri Feb 14 15:00:31 2014 +0100

bsp/altera-cyclone-v: Add Alteras hwlib

Add files from Alteras hwlib

---

 .../libbsp/arm/altera-cyclone-v/hwlib/README.txt   |   13 +
 .../hwlib/include/alt_address_space.h              |  390 +
 .../hwlib/include/alt_clock_group.h                |   95 +
 .../hwlib/include/alt_clock_manager.h              | 1431 ++
 .../hwlib/include/alt_generalpurpose_io.h          | 1236 +
 .../hwlib/include/alt_hwlibs_ver.h                 |   52 +
 .../hwlib/include/alt_interrupt_common.h           |  531 +
 .../hwlib/include/alt_mpu_registers.h              |  156 +
 .../hwlib/include/alt_reset_manager.h              |  249 +
 .../arm/altera-cyclone-v/hwlib/include/hwlib.h     |  190 +
 .../hwlib/include/socal/alt_clkmgr.h               | 6464 +++++
 .../hwlib/include/socal/alt_gpio.h                 | 1991 ++
 .../altera-cyclone-v/hwlib/include/socal/alt_l3.h  | 6299 +++++
 .../hwlib/include/socal/alt_rstmgr.h               | 3382 +++
 .../altera-cyclone-v/hwlib/include/socal/alt_sdr.h | 4149 ++++
 .../hwlib/include/socal/alt_sysmgr.h               |24810 ++++++++++++++++++++
 .../hwlib/include/socal/alt_uart.h                 | 5158 ++++
 .../arm/altera-cyclone-v/hwlib/include/socal/hps.h | 8026 +++++++
 .../altera-cyclone-v/hwlib/include/socal/socal.h   |  356 +
 .../hwlib/src/hwmgr/alt_address_space.c            |  184 +
 .../hwlib/src/hwmgr/alt_clock_manager.c            | 5208 ++++
 .../hwlib/src/hwmgr/alt_generalpurpose_io.c        |  745 +
 .../hwlib/src/hwmgr/alt_reset_manager.c            |  135 +
 23 files changed, 71250 insertions(+), 0 deletions(-)

diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt
new file mode 100644
index 0000000..f19d387
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt
@@ -0,0 +1,13 @@
+HWLIB
+=====
+Hwlib is a collection of sources provided by Altera for the Cyclone-V.
+
+As hwlib is third party software, please keep modifications and additions 
+to the sources to a minimum for easy maintenance. Otherwise updating to a 
+new version of hwlib released by Altera can become difficult.
+
+The hwlib directory contains only those files from Alteras hwlib which are
+required by the BSP (the whole hwlib was considered too big).
+The directory structure within the hwlib directory is equivalent to Alteras
+hwlib directory structure. For easy maintenance only whole files have been
+left out.
\ No newline at end of file
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h
new file mode 100644
index 0000000..b66ccdf
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h
@@ -0,0 +1,390 @@
+/*! \file
+ *  Altera - SoC FPGA Address Space Manager
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_ADDR_SPACE_H__
+#define __ALT_ADDR_SPACE_H__
+
+#include <stdbool.h>
+#include "hwlib.h"
+#include "socal/hps.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/******************************************************************************/
+// ARM Level 2 Cache Controller L2C-310 Register Interface
+
+// Address Filtering Start Register
+// The Address Filtering Start Register is a read and write register.
+// Bits     Field                       Description
+// :-------|:--------------------------|:-----------------------------------------
+// [31:20] | address_filtering_start   | Address filtering start address for
+//         |                           | bits [31:20] of the filtering address.
+// [19:1]  | Reserved                  | SBZ/RAZ
+// [0]     | address_filtering_enable  | 0 - address filtering disabled
+//         |                           | 1 - address filtering enabled.
+
+// Address Filtering Start Register Address
+#define L2_CACHE_ADDR_FILTERING_START_OFST      0xC00
+#define L2_CACHE_ADDR_FILTERING_START_ADDR      (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_START_OFST)
+// Address Filtering Start Register - Start Value Mask
+#define L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000
+// Address Filtering Start Register - Reset Start Address Value (1 MB)
+#define L2_CACHE_ADDR_FILTERING_START_RESET     0x100000
+// Address Filtering Start Register - Enable Flag Mask
+#define L2_CACHE_ADDR_FILTERING_ENABLE_MASK     0x00000001
+// Address Filtering Start Register - Reset Enable Flag Value (Enabled)
+#define L2_CACHE_ADDR_FILTERING_ENABLE_RESET    0x1
+
+// Address Filtering End Register
+// The Address Filtering End Register is a read and write register.
+// Bits     Field                       Description
+// :-------|:--------------------------|:-----------------------------------------
+// [31:20] | address_filtering_end     | Address filtering end address for bits
+//         |                           | [31:20] of the filtering address.
+// [19:0]  | Reserved                  | SBZ/RAZ
+
+// Address Filtering End Register Address
+#define L2_CACHE_ADDR_FILTERING_END_OFST        0xC04
+#define L2_CACHE_ADDR_FILTERING_END_ADDR        (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST)
+// Address Filtering End Register - End Value Mask
+#define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK   0xFFF00000
+// Address Filtering End Register - Reset End Address Value (3 GB)
+#define L2_CACHE_ADDR_FILTERING_END_RESET       0xC0000000
+
+#ifndef __ASSEMBLY__
+
+/******************************************************************************/
+/*! \addtogroup ADDR_SPACE_MGR The Address Space Manager
+ *
+ * This module contains group APIs for managing the HPS address space. This
+ * module contains group APIs to manage:
+ * * Memory Map Control
+ * * Memory Coherence
+ * * Cache Managment
+ * * MMU Managment
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*! \addtogroup ADDR_SPACE_MGR_REMAP Address Space Mapping Control
+ *
+ * This group API provides functions to map and remap selected address ranges
+ * into the accessible (visible) views of the MPU and non MPU address spaces.
+ *
+ * \b Caveats
+ *
+ * \b NOTE: Caution should be observed when remapping address 0 to different
+ * memory.  The code performing the remapping operation should not be executing
+ * in the address range being remapped to different memory.
+ *
+ * For example, if address 0 is presently mapped to OCRAM and the code is
+ * preparing to remap address 0 to SDRAM, then the code must not be executing in
+ * the range 0 to 64 KB as this address space is about to be remapped to
+ * different memory. If the code performing the remap operation is executing
+ * from OCRAM then it needs to be executing from its permanently mapped OCRAM
+ * address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR).
+ *
+ * \b NOTE: The MPU address space view is controlled by two disparate hardware
+ * control interfaces: the L3 remap register and the L2 cache address filtering
+ * registers. To complicate matters, the L3 remap register is write-only which
+ * means not only that current remap register state cannot be read but also that
+ * a read-modify-write operation cannot be performed on the register.
+ *
+ * This should not present a problem in most use case scenarios except for the
+ * case where a current MPU address space mapping of 0 to SDRAM is being changed
+ * to to a mapping of 0 to Boot ROM or OCRAM.
+ *
+ * In this case, a two step process whereby the L3 remap register is first set
+ * to the new desired MPU address 0 mapping and then the L2 cache address
+ * filtering registers have their address ranges adjusted accordingly must be
+ * followed. An example follows:
+\verbatim
+// 1 MB reset default value for address filtering start
+#define L2_CACHE_ADDR_FILTERING_START_RESET     0x100000
+uint32_t addr_filt_start;
+uint32_t addr_filt_end;
+
+// Perform L3 remap register programming first by setting the desired new MPU
+// address space 0 mapping. Assume OCRAM for the example.
+alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...);
+
+// Next, adjust the L2 cache address filtering range. Set the start address to
+// the default reset value and retain the existing end address configuration.
+alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end);
+if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET)
+{
+    alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end);
+}
+\endverbatim
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the MPU address space attributes.
+ *
+ * The MPU address space consists of the ARM Cortex A9 processors and associated
+ * processor peripherals (cache, MMU).
+ */
+typedef enum ALT_ADDR_SPACE_MPU_ATTR_e
+{
+    ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM,     /*!< Maps the Boot ROM to address
+                                             *   0x0 for the MPU L3 master. Note
+                                             *   that the Boot ROM is also
+                                             *   always mapped to address
+                                             *   0xfffd_0000 for the MPU L3
+                                             *   master independent of
+                                             *   attribute.
+                                             */
+
+    ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM        /*!< Maps the On-chip RAM to address
+                                             *   0x0 for the MPU L3 master. Note
+                                             *   that the On-chip RAM is also
+                                             *   always mapped to address
+                                             *   0xffff_0000 for the MPU L3
+                                             *   master independent of this
+                                             *   attribute.
+                                             */
+} ALT_ADDR_SPACE_MPU_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the non-MPU address space attributes.
+ *
+ * The non-MPU address space consists of the non-MPU L3 masters including the
+ * DMA controllers (standalone and those built into peripherals), the F2H AXI
+ * Bridge, and the DAP.
+ */
+typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e
+{
+    ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM,    /*!< Maps the SDRAM to address 0x0
+                                             *   for the non-MPU L3 masters.
+                                             */
+    ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM     /*!< Maps the On-chip RAM to address
+                                             *   0x0 for the non-MPU L3
+                                             *   masters. Note that the On-chip
+                                             *   RAM is also always mapped to
+                                             *   address 0xffff_0000 for the
+                                             *   non-MPU L3 masters independent
+                                             *   of this attribute.
+                                             */
+} ALT_ADDR_SPACE_NONMPU_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the HPS to FPGA bridge accessiblity
+ * attributes.
+ */
+typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e
+{
+    ALT_ADDR_SPACE_H2F_INACCESSIBLE,        /*!< The H2F AXI Bridge is not
+                                             *   visible to L3 masters. Accesses
+                                             *   to the associated address range
+                                             *   return an AXI decode error to
+                                             *   the master.
+                                             */
+    ALT_ADDR_SPACE_H2F_ACCESSIBLE           /*!< The H2F AXI Bridge is visible
+                                             *   to L3 masters.
+                                             */
+} ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the Lightweight HPS to FPGA bridge
+ * accessiblity attributes.
+ */
+typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e
+{
+    ALT_ADDR_SPACE_LWH2F_INACCESSIBLE,      /*!< The LWH2F AXI Bridge is not
+                                             *   visible to L3 masters. Accesses
+                                             *   to the associated address range
+                                             *   return an AXI decode error to
+                                             *   the master.
+                                             */
+    ALT_ADDR_SPACE_LWH2F_ACCESSIBLE         /*!< The LWH2F AXI Bridge is visible
+                                             *   to L3 masters.
+                                             */
+} ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * Configures the mapped and accessible (visible) address ranges for the HPS
+ * MPU, non-MPU, and Bridge address spaces.
+ *
+ * \param       mpu_attr
+ *              The MPU address space configuration attributes.
+ *              
+ * \param       nonmpu_attr
+ *              The non-MPU address space configuration attributes.
+ *              
+ * \param       h2f_attr
+ *              The H2F Bridge attribute mapping and accessibility attributes.
+ *              
+ * \param       lwh2f_attr
+ *              The Lightweight H2F Bridge attribute mapping and accessibility
+ *              attributes.
+ *              
+ * 
+ * \retval      ALT_E_SUCCESS       The operation was succesful.
+ * \retval      ALT_E_ERROR         The operation failed.
+ * \retval      ALT_E_INV_OPTION    One or more invalid attribute options were
+ *                                  specified.
+ */
+ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
+                                     ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
+                                     ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr,
+                                     ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr);
+
+/******************************************************************************/
+/*!
+ * Maps SDRAM to address 0x0 for the MPU address space view.
+ *
+ * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest
+ * 64KB of the boot region are accessible because the size of the Boot ROM and
+ * on-chip RAM are only 64KB.  Addresses in the range 0x100000 (1MB) to
+ * 0xC0000000 (3GB) access SDRAM and addresses in the range 0xC0000000 (3GB) to
+ * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MB of SDRAM is not
+ * accessible to the MPU unless address 0 is remapped to SDRAM after reset.
+ *
+ * This function remaps the addresses between 0x0 to 0x100000 (1MB) to access
+ * SDRAM.
+ *
+ * \internal
+ * The remap to address 0x0 is achieved by configuring the L2 cache Address
+ * Filtering Registers to redirect address 0x0 to \e sdram_end_addr to the SDRAM
+ * AXI (M1) master port by calling:
+ *
+ * alt_l2_addr_filter_cfg_set(0x0, <current_addr_filt_end_value>);
+ * 
+ * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
+ * Reference Manual, Section 3.3.12 Address Filtering </em>.
+ * \endinternal
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup L2_ADDR_FLTR L2 Cache Address Filter
+ *
+ * The L2 cache address filter controls where physical addresses within certain
+ * ranges of the MPU address space are directed.
+ *
+ * The L2 cache has master port connections to the L3 interconnect and the SDRAM
+ * controller. A programmable address filter controls which portions of the
+ * 32-bit physical address space use each master.
+ * 
+ * When l2 address filtering is configured and enabled, a physical address will
+ * be redirected to one master or the other based upon the address filter
+ * configuration.
+ *
+ * If \b address_filter_start <= \e physical_address < \b address_filter_end:
+ * * then redirect \e physical_address to AXI Master Port M1 (SDRAM controller)
+ * * else redirect \e physical_address to AXI Master Port M0 (L3 interconnect)
+ *
+ * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
+ * Reference Manual, Section 3.3.12 Address Filtering </em> for more information.
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Get the L2 cache address filtering configuration settings.
+ *
+ * \param       addr_filt_start
+ *              [out] An output parameter variable for the address filtering
+ *              start address for the range of physical addresses redirected to
+ *              the SDRAM AXI master port. The value returned is always a 1 MB
+ *              aligned address.
+ *              
+ * \param       addr_filt_end
+ *              [out] An output parameter variable for the address filtering
+ *              end address for the range of physical addresses redirected to
+ *              the SDRAM AXI master port. The value returned is always a 1 MB
+ *              aligned address.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   An bad argument was passed. Either \e addr_filt_start
+ *                              or \e addr_filt_end or both are invalid addresses.
+ */
+ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
+                                           uint32_t* addr_filt_end);
+
+/******************************************************************************/
+/*!
+ * Set the L2 cache address filtering configuration settings.
+ *
+ * Address filtering start and end values must be 1 MB aligned.
+ *
+ * \param       addr_filt_start
+ *              The address filtering start address for the range of physical
+ *              addresses redirected to the SDRAM AXI master port. Only bits
+ *              [31:20] of the address are valid. Any bits outside the range
+ *              [31:20] are invalid and will cause an error status to be
+ *              returned.
+ *              
+ * \param       addr_filt_end
+ *              The address filtering end address for the range of physical
+ *              addresses redirected to the SDRAM AXI master port. Only bits
+ *              [31:20] of the address are valid. Any bits outside the range
+ *              [31:20] are invalid and will cause an error status to be
+ *              returned.
+ *              
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. One or
+ *                              more address arguments do not satisfy the argument
+ *                              constraints.
+ */
+ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
+                                           uint32_t addr_filt_end);
+
+/*! @} */
+
+/*! @} */
+
+#endif  /* __ASSEMBLY__ */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_ADDR_SPACE_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h
new file mode 100644
index 0000000..a5e8c92
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h
@@ -0,0 +1,95 @@
+/*! \file
+ *  Contains the definition of an opaque data structure that contains raw
+ *  configuration information for a clock group.
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_CLK_GRP_H__
+#define __ALT_CLK_GRP_H__
+
+#include "hwlib.h"
+#include "socal/alt_clkmgr.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+
+/*! This type definition enumerates the clock groups
+*/
+typedef enum ALT_CLK_GRP_e
+{
+	ALT_MAIN_PLL_CLK_GRP,					/*!< Main PLL clock group */
+
+	ALT_PERIPH_PLL_CLK_GRP,					/*!< Peripheral PLL clock group */
+
+	ALT_SDRAM_PLL_CLK_GRP					/*!< SDRAM PLL clock group */
+
+} ALT_CLK_GRP_t;
+
+
+
+/*! This type definition defines an opaque data structure for holding the
+ *  configuration settings for a complete clock group.
+ */
+typedef struct ALT_CLK_GROUP_RAW_CFG_s
+{
+    uint32_t      			  verid;		/*!< SoC FPGA version identifier. This field
+											*   encapsulates the silicon identifier and
+											*   version information associated with this
+											*   clock group configuration. It is used to
+											*   assert that this clock group configuration
+											*   is valid for this device.
+											*/
+    uint32_t				  siliid2;		/*!< Reserved register - reserved for future
+     	 	 	 	 	 	 	 	 	 	*	 device IDs or capability flags/
+     	 	 	 	 	 	 	 	 	 	*/
+    ALT_CLK_GRP_t     		  clkgrpsel;	/*!< Clock group union discriminator */
+
+
+    /*! This union holds the raw register values for configuration of the set of
+     *  possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator
+     *  identifies the valid clock group union data member.
+     */
+    union ALT_CLK_GROUP_RAW_CFG_u
+    {
+        ALT_CLKMGR_MAINPLL_t  mainpllgrp;   /*!< Raw clock group configuration for Main PLL group */
+        ALT_CLKMGR_PERPLL_t   perpllgrp;    /*!< Raw clock group configuration for Peripheral PLL group */
+        ALT_CLKMGR_SDRPLL_t   sdrpllgrp;    /*!< Raw clock group configuration for SDRAM PLL group */
+    } clkgrp;
+} ALT_CLK_GROUP_RAW_CFG_t;
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_CLK_GRP_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h
new file mode 100644
index 0000000..7cf0e12
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h
@@ -0,0 +1,1431 @@
+/*! \file
+ *  Contains definitions for the Altera Hardware Libraries Clock Manager
+ *  Application Programming Interface
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_CLK_MGR_H__
+#define __ALT_CLK_MGR_H__
+
+#include "hwlib.h"
+#include "alt_clock_group.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*! \addtogroup CLK_MGR The Clock Manager API
+ *
+ * This module defines the Clock Manager API for accessing, configuring, and
+ * controlling the HPS clock resources.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition is an opaque type definition for clock frequency values
+ * in Hz.
+ */
+typedef uint32_t    alt_freq_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the names of the clock and PLL resources
+ * managed by the Clock Manager.
+ */
+typedef enum ALT_CLK_e
+{
+    /* Clock Input Pins */
+    ALT_CLK_IN_PIN_OSC1,
+                                        /*!< \b OSC_CLK_1_HPS
+                                         *   External oscillator input:
+                                         *   * Input Pin
+                                         *   * Clock source to Main PLL
+                                         *   * Clock source to SDRAM PLL
+                                         *     and Peripheral PLL if selected via
+                                         *     register write
+                                         *   * Clock source for clock in safe mode
+                                         */
+
+    ALT_CLK_IN_PIN_OSC2,
+                                        /*!< \b OSC_CLK_2_HPS
+                                         *   External Oscillator input:
+                                         *   * Input Pin
+                                         *   * Optional clock source to SDRAM PLL 
+                                         *     and Peripheral PLL if selected
+                                         *   * Typically used for Ethernet
+                                         *     reference clock
+                                         */
+
+
+    /* FPGA Clock Sources External to HPS */
+    ALT_CLK_F2H_PERIPH_REF,
+                                        /*<! Alternate clock source from FPGA
+                                         * for HPS Peripheral PLL. */
+
+    ALT_CLK_F2H_SDRAM_REF,
+                                        /*<! Alternate clock source from FPGA
+                                         * for HPS SDRAM PLL. */
+
+
+    /* Other Clock Sources External to HPS */
+    ALT_CLK_IN_PIN_JTAG,
+                                        /*!< \b JTAG_TCK_HPS
+                                         *   * Input Pin
+                                         *   * External HPS JTAG clock input.
+                                         */
+
+    ALT_CLK_IN_PIN_ULPI0,
+                                        /*!< \b ULPI0_CLK
+                                         *   ULPI Clock provided by external USB0
+                                         *   PHY
+                                         *   * Input Pin
+                                         */
+
+    ALT_CLK_IN_PIN_ULPI1,
+                                        /*!< \b ULPI1_CLK
+                                         *   ULPI Clock provided by external USB1
+                                         *   PHY
+                                         *   * Input Pin
+                                         */
+
+    ALT_CLK_IN_PIN_EMAC0_RX,
+                                        /*!< \b EMAC0:RX_CLK
+                                         *   Rx Reference Clock for EMAC0
+                                         *   * Input Pin
+                                         */
+
+    ALT_CLK_IN_PIN_EMAC1_RX,
+                                        /*!< \b EMAC1:RX_CLK
+                                         *   Rx Reference Clock for EMAC1
+                                         *   * Input Pin
+                                         */
+
+    
+    /* PLLs */
+    ALT_CLK_MAIN_PLL,
+                                        /*!< \b main_pll_ref_clkin
+                                         *   Main PLL input reference clock,
+                                         *   used to designate the Main PLL in
+                                         *   PLL clock selections.
+                                         */
+
+    ALT_CLK_PERIPHERAL_PLL,
+                                        /*!< \b periph_pll_ref_clkin 
+                                         *   Peripheral PLL input reference
+                                         *   clock, used to designate the
+                                         *   Peripheral PLL in PLL clock
+                                         *   selections.
+                                         */
+
+    ALT_CLK_SDRAM_PLL,
+                                        /*!< \b sdram_pll_ref_clkin
+                                         *   SDRAM PLL input reference clock,
+                                         *   used to designate the SDRAM PLL in
+                                         *   PLL clock selections.
+                                         */
+
+    /* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived
+     * directly from the osc_clk_1_HPS pin */
+    ALT_CLK_OSC1,
+                                        /*!< \b osc1_clk
+                                         *   OSC1 Clock Group - The
+                                         *   OSC1 clock group contains
+                                         *   those clocks which are
+                                         *   derived directly from the
+                                         *   osc_clk_1_HPS pin.
+                                         *   * alias for ALT_CLK_IN_PIN_OSC1
+                                         */
+
+    /* Main Clock Group - The following clocks are derived from the Main PLL. */
+    ALT_CLK_MAIN_PLL_C0,
+                                        /*!< \b Main PLL C0 Output */
+
+    ALT_CLK_MAIN_PLL_C1,
+                                        /*!< \b Main PLL C1 Output */
+
+    ALT_CLK_MAIN_PLL_C2,
+                                        /*!< \b Main PLL C2 Output */
+
+    ALT_CLK_MAIN_PLL_C3,
+                                        /*!< \b Main PLL C3 Output */
+
+    ALT_CLK_MAIN_PLL_C4,
+                                        /*!< \b Main PLL C4 Output */
+
+    ALT_CLK_MAIN_PLL_C5,
+                                        /*!< \b Main PLL C5 Output */
+
+    ALT_CLK_MPU,
+                                        /*!< \b mpu_clk
+                                         *   Main PLL C0 Output. Clock for MPU
+                                         *   subsystem, including CPU0 and CPU1.
+                                         *   * Alias for \e ALT_CLK_MAIN_PLL_C0
+                                         */
+
+    ALT_CLK_MPU_L2_RAM,
+                                        /*!< \b mpu_l2_ram_clk
+                                         *   Clock for MPU level 2 (L2) RAM
+                                         */
+
+    ALT_CLK_MPU_PERIPH,
+                                        /*!< \b mpu_periph_clk
+                                         *   Clock for MPU snoop control unit
+                                         *   (SCU) peripherals, such as the
+                                         *   general interrupt controller (GIC)
+                                         */
+
+    ALT_CLK_L3_MAIN,
+                                        /*!< \b main_clk
+                                         *   Main PLL C1 Output
+                                         *   * Alias for \e ALT_CLK_MAIN_PLL_C1
+                                         */
+
+    ALT_CLK_L3_MP,
+                                        /*!< \b l3_mp_clk
+                                         *   Clock for L3 Master Peripheral Switch
+                                         */
+
+    ALT_CLK_L3_SP,
+                                        /*!< \b l3_sp_clk
+                                         *   Clock for L3 Slave Peripheral Switch
+                                         */
+
+    ALT_CLK_L4_MAIN,
+                                        /*!< \b l4_main_clk
+                                         *   Clock for L4 main bus
+                                         *   * Clock for DMA
+                                         *   * Clock for SPI masters
+                                         */
+
+    ALT_CLK_L4_MP,
+                                        /*!< \b l4_mp_clk
+                                         *   Clock for L4 master peripherals (MP) bus
+                                         */
+
+    ALT_CLK_L4_SP,
+                                        /*!< \b l4_sp_clk
+                                         *   Clock for L4 slave peripherals (SP) bus 
+                                         */
+
+    ALT_CLK_DBG_BASE,
+                                        /*!< \b dbg_base_clk
+                                         *   Main PLL C2 Output
+                                         *   * Alias for \e ALT_CLK_MAIN_PLL_C2
+                                         */
+
+    ALT_CLK_DBG_AT,
+                                        /*!< \b dbg_at_clk
+                                         *   Clock for CoreSight debug Advanced
+                                         *   Microcontroller Bus Architecture
+                                         *   (AMBA) Trace Bus (ATB)
+                                         */
+
+    ALT_CLK_DBG_TRACE,
+                                        /*!< \b dbg_trace_clk
+                                         *   Clock for CoreSight debug Trace
+                                         *   Port Interface Unit (TPIU)
+                                         */
+
+    ALT_CLK_DBG_TIMER,
+                                        /*!< \b dbg_timer_clk
+                                         *   Clock for the trace timestamp
+                                         *   generator
+                                         */
+
+    ALT_CLK_DBG,
+                                        /*!< \b dbg_clk
+                                         *   Clock for Debug Access Port (DAP)
+                                         *   and debug Advanced Peripheral Bus
+                                         *   (APB)
+                                         */
+
+    ALT_CLK_MAIN_QSPI,
+                                        /*!< \b main_qspi_clk
+                                         *   Main PLL C3 Output. Quad SPI flash
+                                         *   internal logic clock.
+                                         *   * Alias for \e ALT_CLK_MAIN_PLL_C3
+                                         */
+
+    ALT_CLK_MAIN_NAND_SDMMC,
+                                        /*!< \b main_nand_sdmmc_clk 
+                                         *   Main PLL C4 Output. Input clock to
+                                         *   flash controller clocks block.
+                                         *   * Alias for \e ALT_CLK_MAIN_PLL_C4
+                                         */
+
+    ALT_CLK_CFG,
+                                        /*!< \b cfg_clk 
+                                         *   FPGA manager configuration clock.
+                                         */
+
+    ALT_CLK_H2F_USER0,
+                                        /*!< \b h2f_user0_clock
+                                         *   Clock to FPGA fabric
+                                         */
+
+    
+    /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */
+    ALT_CLK_PERIPHERAL_PLL_C0,
+                                        /*!< \b Peripheral PLL C0 Output */
+
+    ALT_CLK_PERIPHERAL_PLL_C1,
+                                        /*!< \b Peripheral PLL C1 Output */
+
+    ALT_CLK_PERIPHERAL_PLL_C2,
+                                        /*!< \b Peripheral PLL C2 Output */
+
+    ALT_CLK_PERIPHERAL_PLL_C3,
+                                        /*!< \b Peripheral PLL C3 Output */
+
+    ALT_CLK_PERIPHERAL_PLL_C4,
+                                        /*!< \b Peripheral PLL C4 Output */
+
+    ALT_CLK_PERIPHERAL_PLL_C5,
+                                        /*!< \b Peripheral PLL C5 Output */
+
+    ALT_CLK_USB_MP,
+                                        /*!< \b usb_mp_clk
+                                         *   Clock for USB
+                                         */
+
+    ALT_CLK_SPI_M,
+                                        /*!< \b spi_m_clk
+                                         *   Clock for L4 SPI master bus
+                                         */
+
+    ALT_CLK_QSPI,
+                                        /*!< \b qspi_clk
+                                         *   Clock for Quad SPI
+                                         */
+
+    ALT_CLK_NAND_X,
+                                        /*!< \b nand_x_clk
+                                         *   NAND flash controller master and
+                                         *   slave clock
+                                         */
+
+    ALT_CLK_NAND,
+                                        /*!< \b nand_clk
+                                         *   Main clock for NAND flash
+                                         *   controller
+                                         */
+
+    ALT_CLK_SDMMC,
+                                        /*!< \b sdmmc_clk
+                                         *   Clock for SD/MMC logic input clock
+                                         */
+
+    ALT_CLK_EMAC0,
+                                        /*!< \b emac0_clk
+                                         *   EMAC 0 clock - Peripheral PLL C0
+                                         *   Output
+                                         *   * Alias for \e ALT_CLK_PERIPHERAL_PLL_C0
+                                         */
+
+    ALT_CLK_EMAC1,
+                                        /*!< \b emac1_clk
+                                         *   EMAC 1 clock - Peripheral PLL C1
+                                         *   Output
+                                         *   * Alias for \e ALT_CLK_PERIPHERAL_PLL_C1
+                                         */
+
+    ALT_CLK_CAN0,
+                                        /*!< \b can0_clk
+                                         *   Controller area network (CAN)
+                                         *   controller 0 clock
+                                         */
+
+    ALT_CLK_CAN1,
+                                        /*!< \b can1_clk
+                                         *   Controller area network (CAN)
+                                         *   controller 1 clock
+                                         */
+
+    ALT_CLK_GPIO_DB,
+                                        /*!< \b gpio_db_clk
+                                         *   Debounce clock for GPIO0, GPIO1,
+                                         *   and GPIO2
+                                         */
+
+    ALT_CLK_H2F_USER1,
+                                        /*!< \b h2f_user1_clock
+                                         *   Clock to FPGA fabric - Peripheral
+                                         *   PLL C5 Output
+                                         *   * Alias for \e ALT_CLK_PERIPHERAL_PLL_C5
+                                         */
+
+
+    /* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */
+    ALT_CLK_SDRAM_PLL_C0,
+                                        /*!< \b SDRAM PLL C0 Output */
+
+    ALT_CLK_SDRAM_PLL_C1,
+                                        /*!< \b SDRAM PLL C1 Output */
+
+    ALT_CLK_SDRAM_PLL_C2,
+                                        /*!< \b SDRAM PLL C2 Output */
+
+    ALT_CLK_SDRAM_PLL_C3,
+                                        /*!< \b SDRAM PLL C3 Output */
+
+    ALT_CLK_SDRAM_PLL_C4,
+                                        /*!< \b SDRAM PLL C4 Output */
+
+    ALT_CLK_SDRAM_PLL_C5,
+                                        /*!< \b SDRAM PLL C5 Output */
+
+    ALT_CLK_DDR_DQS,
+                                        /*!< \b ddr_dqs_clk
+                                         *   Clock for MPFE, single-port
+                                         *   controller, CSR access, and PHY -
+                                         *   SDRAM PLL C0 Output
+                                         *   * Alias for \e ALT_CLK_SDRAM_PLL_C0
+                                         */
+
+    ALT_CLK_DDR_2X_DQS,
+                                        /*!< \b ddr_2x_dqs_clk
+                                         *    Clock for PHY - SDRAM PLL C1 Output
+                                         *   * Alias for \e ALT_CLK_SDRAM_PLL_C1
+                                         */
+
+    ALT_CLK_DDR_DQ,
+                                        /*!< \b ddr_dq_clk
+                                         *   Clock for PHY - SDRAM PLL C2 Output
+                                         *   * Alias for \e ALT_CLK_SDRAM_PLL_C2
+                                         */
+
+    ALT_CLK_H2F_USER2,
+                                        /*!< \b h2f_user2_clock
+                                         *   Clock to FPGA fabric - SDRAM PLL C5
+                                         *   Output
+                                         *   * Alias for \e ALT_CLK_SDRAM_PLL_C5
+                                         */
+
+    /* Clock Output Pins */
+    ALT_CLK_OUT_PIN_EMAC0_TX,
+                                       /*!< \b EMAC0:TX_CLK
+                                        *   Tx Reference Clock for EMAC0
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_EMAC1_TX,
+                                       /*!< \b EMAC1:TX_CLK
+                                        *   Tx Reference Clock for EMAC1
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_SDMMC,
+                                       /*!< \b SDMMC:CLK
+                                        *   SD/MMC Card Clock
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_I2C0_SCL,
+                                       /*!< \b I2C0:SCL
+                                        *   I2C Clock for I2C0
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_I2C1_SCL,
+                                       /*!< \b I2C1:SCL
+                                        *   I2C Clock for I2C1
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_I2C2_SCL,
+                                       /*!< \b I2C2:SCL
+                                        *   I2C Clock for I2C2/2 wire
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_I2C3_SCL,
+                                       /*!< \b I2C3:SCL
+                                        *   I2C Clock for I2C1/2 wire
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_SPIM0,
+                                       /*!< \b SPIM0:CLK
+                                        *   SPI Clock
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_SPIM1,
+                                       /*!< \b SPIM1:CLK
+                                        *   SPI Clock
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_QSPI,
+                                       /*!< \b QSPI:CLK
+                                        *   QSPI Flash Clock
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_UNKNOWN
+} ALT_CLK_t;
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_STATUS Clock Manager Status
+ *
+ * This functional group provides status information on various aspects and
+ * properties of the Clock Manager state.
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * This type definition defines the lock condition status codes for each of the
+ * PLLs. If the PLL lock status condition is enabled (See: alt_clk_irq_enable())
+ * then it contributes to the overall \b clkmgr_IRQ signal assertion state.
+ */
+typedef enum ALT_CLK_PLL_LOCK_STATUS_e
+{
+    ALT_MAIN_PLL_LOCK_ACHV    = 0x00000001, /*!< This condition is set if the Main
+                                             *   PLL has achieved lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+    ALT_PERIPH_PLL_LOCK_ACHV  = 0x00000002, /*!< This condition is set if the Peripheral
+                                             *   PLL has achieved lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+    ALT_SDR_PLL_LOCK_ACHV     = 0x00000004, /*!< This condition is set if the SDRAM
+                                             *   PLL has achieved lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+    ALT_MAIN_PLL_LOCK_LOST    = 0x00000008, /*!< This condition is set if the Main
+                                             *   PLL has lost lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+    ALT_PERIPH_PLL_LOCK_LOST  = 0x00000010, /*!< This condition is set if the Peripheral
+                                             *   PLL has lost lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+    ALT_SDR_PLL_LOCK_LOST     = 0x00000020  /*!< This condition is set if the SDRAM
+                                             *   PLL has lost lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+} ALT_CLK_PLL_LOCK_STATUS_t;
+
+/******************************************************************************/
+/*!
+ * Clear the selected PLL lock status conditions.
+ *
+ * This function clears assertions of one or more of the PLL lock status
+ * conditions.
+ *
+ * NOTE: This function is used to clear \b clkmgr_IRQ interrupt signal source
+ * assertion conditions.
+ *
+ * \param       lock_stat_mask
+ *              Specifies the PLL lock status conditions to clear. \e lock_stat_mask 
+ *              is a mask of logically OR'ed \ref ALT_CLK_PLL_LOCK_STATUS_t
+ *              values designating the PLL lock conditions to clear.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_BAD_ARG   The \e lock_stat_mask argument contains an
+ *                              unknown condition value.
+ */
+ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
+
+/******************************************************************************/
+/*!
+ * Returns the PLL lock status condition values.
+ *
+ * This function returns the value of the PLL lock status conditions.
+ *
+ * \returns The current values of the PLL lock status conditions as defined by
+ * the \ref ALT_CLK_PLL_LOCK_STATUS_t mask bits. If the corresponding bit is set
+ * then the condition is asserted.
+ */
+uint32_t alt_clk_lock_status_get(void);
+
+/******************************************************************************/
+/*!
+ * Returns ALT_E_TRUE if the designated PLL is currently locked and ALT_E_FALSE
+ * otherwise.
+ *
+ * \param       pll
+ *              The PLL to return the lock status of.
+ *
+ * \retval      ALT_E_TRUE      The specified PLL is currently locked.
+ * \retval      ALT_E_FALSE     The specified PLL is currently not locked.
+ * \retval      ALT_E_BAD_ARG   The \e pll argument designates a non PLL clock 
+ *                              value.
+ * \internal
+ * NOTE: This function uses the
+ *       * \b hps::clkmgr::inter::mainplllocked
+ *       * \b hps::clkmgr::inter::perplllocked, 
+ *       * \b hps::clkmgr::inter::sdrplllocked
+ *
+ *       bits to determine if the PLL is locked or not.
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_SAFE_MODE Safe Mode Options
+ *
+ * When safe mode is enabled, clocks in the HPS are directly generated from the
+ * \b osc1_clk clock. Safe mode is enabled by the assertion of a safe mode
+ * request from the reset manager or by a cold reset. Assertion of the safe mode
+ * request from the reset manager sets the safe mode bit in the clock manager
+ * control register. No other control register bits are affected by the safe
+ * mode request from the reset manager.
+ * 
+ * While in safe mode, clock manager register settings which control clock
+ * behavior are not changed. However, the output of the registers which control
+ * the clock manager state are forced to the safe mode values such that the
+ * following conditions occur:
+ * * All PLLs are bypassed to the \b osc1_clk clock, including their counters.
+ * * Clock dividers select their default reset values.
+ * * The flash controllers source clock selections are set to the peripheral 
+ *   PLL.
+ * * All clocks are enabled.
+ * * Safe mode is optionally applied to debug clocks.
+ * 
+ * A write by software is the only way to clear the safe mode bit. All registers
+ * and clocks need to be configured correctly and all software-managed clocks
+ * need to be gated off before clearing safe mode. Software can then gate clocks
+ * on as required.
+ * 
+ * On cold reset, all clocks are put in safe mode.
+ * 
+ * On warm reset, safe mode is optionally and independently applied to debug
+ * clocks and normal (i.e.non-debug) clocks based on clock manager register
+ * settings. The default response for warm reset is to put all clocks in safe
+ * mode.
+ * 
+ * The APIs in this group provide control of the Clock Manager safe mode warm
+ * reset response behavior.
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the safe mode clock domains under control of
+ * the Clock Manager.
+ */
+typedef enum ALT_CLK_SAFE_DOMAIN_e
+{
+    /*!
+     * This enumeration literal specifies the normal safe mode domain. The
+     * normal domain consists of all clocks except debug clocks.
+     */ 
+    ALT_CLK_DOMAIN_NORMAL,
+    /*!
+     * This enumeration literal specifies the debug safe mode domain. The debug
+     * domain consists of all debug clocks.
+     */ 
+    ALT_CLK_DOMAIN_DEBUG
+} ALT_CLK_SAFE_DOMAIN_t;
+
+/******************************************************************************/
+/*!
+ * Clear the safe mode status of the Clock Manager following a reset.
+ *
+ * NOTE: Safe mode should only be cleared once clocks have been correctly
+ * configured.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_safe_mode_clear(void);
+
+/******************************************************************************/
+/*!
+ * Return whether the specified safe mode clock domain is in safe mode or not.
+ *
+ * \param       clk_domain
+ *              The safe mode clock domain to check whether in safe mode or not.
+ *
+ * \retval      TRUE            The safe mode clock domain is in safe mode.
+ * \retval      FALSE           The safe mode clock domain is not in safe mode.
+ */
+bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_BYPASS PLL Bypass Control
+ *
+ * When a PLL is in bypass, the PLL clock logic is kept in reset. In this
+ * manner, the PLL clock can be free running while it stabilizes and achieves
+ * lock. The bypass logic isolates PLL configuration registers from the clock
+ * while changes are made to the PLL settings.
+ *
+ * The bypass controls are used by software to change the source clock input
+ * reference (for Peripheral and SDRAM PLLs) and is recommended when changing
+ * settings that may affect the ability of the VCO to maintain lock.  When a PLL
+ * is taken in or out of bypass the PLL output clocks will pause momentarily
+ * while the clocks are in transition, There will be no glitches or clocks
+ * shorter than the either the old or the new clock period.
+ *
+ * In summary, the PLL bypass controls permit:
+ * * Each PLL to be individually bypassed.
+ * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs 
+ *   reference clock input source reference clock selection.
+ * * Isolation of a the PLL VCO frequency registers (multiplier and divider),
+     phase shift registers (negative phase) , and post scale counters.
+ * * Glitch free clock transitions.
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Disable bypass mode for the specified PLL. This operation takes the PLL out
+ * of bypass mode.
+ *
+ * \param       pll
+ *              The PLL to take out of bypass mode.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The \e pll argument specified a non PLL clock 
+ *                              value.
+ */
+ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll);
+
+/******************************************************************************/
+/*!
+ * Enable bypass mode for the specified PLL.
+ *
+ * \param       pll
+ *              The PLL to put into bypass mode.
+ *
+ * \param       use_input_mux
+ *              If TRUE then use the PLLs reference clock input source selection
+ *              to directly drive the bypass clock. If FALSE then use bypass
+ *              clock directly driven by the \b osc1_clk.
+ *
+ * \retval      ALT_E_SUCCESS       The operation was succesful.
+ * \retval      ALT_E_ERROR         The operation failed.
+ * \retval      ALT_E_BAD_ARG       The \e pll argument specified a non PLL
+ *                                  clock value.
+ * \retval      ALT_E_INV_OPTION    TRUE is an invalid option for
+ *                                  \e use_input_mux with the \e pll selection.
+ */
+ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll,
+                                          bool use_input_mux);
+
+/******************************************************************************/
+/*!
+ * Return whether the specified PLL is in bypass or not.
+ *
+ * \internal 
+ * This function must also test the \b clkmgr.ctrl.safemode bit in
+ * addition to the PLLs bypass bit to tell whether the bypass mode is
+ * effect or not.
+ * \endinternal
+ *
+ * \param       pll
+ *              The PLL to check whether in bypass mode or not.
+ *
+ * \retval      ALT_E_TRUE      The PLL is in bypass mode.
+ * \retval      ALT_E_FALSE     The PLL is not in bypass mode.
+ * \retval      ALT_E_BAD_ARG   The \e pll argument designates a non PLL clock 
+ *                              value.
+ */
+ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_GATE Clock Gating Control
+ *
+ * This functional group provides gating control of selected clock signals.
+ *
+ * When a clock is enabled, then its clock signal propogates to its respective
+ * clocked IP block(s).  When a clock is disabled, then its clock signal is
+ * prevented from propogating to its respective clocked IP block(s).
+ *
+ * The following clocks may be gated:
+ *
+ * * Main PLL Group
+ *   - l4_main_clk
+ *   - l3_mp_clk
+ *   - l4_mp_clk
+ *   - l4_sp_clk
+ *   - dbg_at_clk
+ *   - dbg_clk
+ *   - dbg_trace_clk
+ *   - dbg_timer_clk
+ *   - cfg_clk
+ *   - s2f_user0_clk
+ *
+ * * SDRAM PLL Group
+ *   - ddr_dqs_clk
+ *   - ddr_2x_clk
+ *   - ddr_dq_clk
+ *   - s2f_user2_clk
+ *
+ * * Peripheral PLL Group
+ *   - emac0_clk
+ *   - emac1_clk
+ *   - usb_mp_clk
+ *   - spi_m_clk
+ *   - can0_clk
+ *   - can1_clk
+ *   - gpio_db_clk
+ *   - s2f_user1_clk
+ *   - sdmmc_clk
+ *   - nand_clk
+ *   - nand_x_clk
+ *   - qspi_clk
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Disable the specified clock. Once the clock is disabled, its clock signal does
+ * not propogate to its clocked elements.
+ *
+ * \param       clk
+ *              The clock to disable.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock 
+ *                              value.
+ */
+ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * Enable the specified clock. Once the clock is enabled, its clock signal
+ * propogates to its elements.
+ *
+ * \param       clk
+ *              The clock to enable.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock 
+ *                              value.
+ */
+ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * Return whether the specified clock is enabled or not.
+ *
+ * \param       clk
+ *              The clock to check whether enabled or not.
+ *
+ * \retval      ALT_E_TRUE      The clock is enabled.
+ * \retval      ALT_E_FALSE     The clock is not enabled.
+ * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock 
+ *                              value.
+ */
+ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_CLK_SEL Clock Source Selection
+ *
+ * This API group provide access and control to the input reference clock source
+ * selection for a clock or PLL.
+ *
+ * \internal
+ * These are the clocks that have software configurable input reference clock
+ * source selection available. Each clock below is listed with its valid
+ * input reference clock source selections.
+ *
+ * + Valid reference clock input selections for \b sdram_pll_ref_clkin
+ *   - osc_clk_1
+ *   - osc_clk_2
+ *   - f2h_sdram_ref_clk
+ *
+ * + Valid reference clock input selections for \b periph_pll_ref_clkin
+ *   - osc_clk_1
+ *   - osc_clk_2,
+ *   - f2h_periph_ref_clk
+ *
+ * + Valid reference clock input selections for \b l4_mp_clk
+ *   - periph_base_clk
+ *   - main_clk
+ *
+ * + Valid reference clock input selections for \b l4_sp_clk
+ *   - periph_base_clk
+ *   - main_clk
+ *
+ * + Valid reference clock input selections for \b sdmmc_clk
+ *   - f2h_periph_ref_clk
+ *   - main_nand_sdmmc_clk
+ *   - periph_nand_sdmmc_clk
+ *
+ * + Valid reference clock input selections for \b nand_clk
+ *   - f2h_periph_ref_clk
+ *   - main_nand_sdmmc_clk
+ *   - periph_nand_sdmmc_clk
+ *
+ * + Valid reference clock input selections for \b qspi_clk
+ *   - f2h_periph_ref_clk
+ *   - main_qspi_clk
+ *   - periph_qspi_clk
+ *
+ * \endinternal
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Get the input reference clock source selection value for the specified clock
+ * or PLL.
+ *
+ * NOTE: This function returns a clock value even though \e clk may specify a 
+ *       clock that does not have a selectable input reference clock source. In 
+ *       this case, the clock value returned is the static clock source for the 
+ *       specified clock. For example calling alt_clk_source_get() with \e clk
+ *       set to \ref ALT_CLK_MAIN_PLL will return \ref ALT_CLK_OSC1.
+ *       
+ * \param       clk
+ *              The clock or PLL to retrieve the input reference clock source
+ *              selection value for.
+ *
+ * \returns     The clock's currently selected input reference clock source.
+ */
+ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * Set the specified clock's input reference clock source selection.
+ *
+ * \param       clk
+ *              The clock or PLL to set the input reference clock source
+ *              selection for.
+ *
+ * \param       ref_clk
+ *              The input reference clock source selection value.
+ *
+ * \retval      ALT_E_SUCCESS       The operation was succesful.
+ * \retval      ALT_E_ERROR         The operation failed.
+ * \retval      ALT_E_BAD_ARG       The \e clk argument designates a clock that 
+ *                                  does not have a selectable input reference 
+ *                                  clock source.
+ * \retval      ALT_E_INV_OPTION    The \e ref_clk argument designates a clock that 
+ *                                  is an invalid reference clock source for the 
+ *                                  specified clock.
+ */
+ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, 
+                                   ALT_CLK_t ref_clk);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_FREQ Clock Frequency Control
+ *
+ * This API group provides access and control of the output frequency of a clock
+ * or PLL.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Set the external clock frequency value.
+ *
+ * The function is used to specify the frequency of the external clock source as
+ * a measure of Hz. The supplied frequency should be within the Fmin and Fmax
+ * values allowed for the external clock source.
+ *
+ * \param       clk
+ *              The external clock source. Valid external clocks are
+ *              * \e ALT_CLK_OSC1
+ *              * \e ALT_CLK_OSC2
+ *              * \e ALT_CLK_F2H_PERIPH_REF
+ *              * \e ALT_CLK_F2H_SDRAM_REF
+ *
+ * \param       freq
+ *              The frequency of the external clock in Hz.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   A bad argument value was passed. Either the \e clk
+ *                              argument is bad or not a valid external clock 
+ *                              source
+ * \retval      ALT_E_ARG_RANGE The frequency value violates the range constraints
+ *                              for the specified clock.
+
+ */
+ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk,
+                                         alt_freq_t freq);
+
+/******************************************************************************/
+/*!
+ * Get the external clock frequency value.
+ *
+ * This function returns the frequency of the external clock source as
+ * a measure of Hz.
+ *
+ * \param       clk
+ *              The external clock source. Valid external clocks are
+ *              * \e ALT_CLK_OSC1
+ *              * \e ALT_CLK_OSC2
+ *              * \e ALT_CLK_F2H_PERIPH_REF
+ *              * \e ALT_CLK_F2H_SDRAM_REF
+ *
+ * \retval      freq
+ *              The frequency of the external clock in Hz.
+ *
+ */
+alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * This type definition defines a structure to contain the generalized
+ * configuration settings for a PLL.
+ */
+typedef struct ALT_CLK_PLL_CFG_s
+{
+    ALT_CLK_t           ref_clk;        /*!< PLL Reference Clock Source */
+    uint32_t            mult;           /*!< VCO Frequency Configuration - 
+                                         *   Multiplier (M) value, range 1 to 4096
+                                         */
+    uint32_t            div;            /*!< VCO Frequency Configuration - 
+                                         *   Divider (N) value, range 1 to 64
+                                         */
+    uint32_t            cntrs[6];       /*!< Post-Scale Counters (C0 - C5) -
+                                         *   range 1 to 512
+                                         */
+    uint32_t            pshift[6];      /*!< Phase Shift - 1/8 (45 degrees) of
+    									 *   negative phase shift per increment,
+                                         *   range 0 to 4096
+                                         */
+} ALT_CLK_PLL_CFG_t;
+
+/******************************************************************************/
+/*!
+ * Get the current PLL configuration.
+ *
+ * \param       pll
+ *              The PLL to get the configuration from.
+ *
+ * \param       pll_cfg
+ *              [out] Pointer to an output parameter variable for the returned
+ *              PLL configuration.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll,
+                                    ALT_CLK_PLL_CFG_t* pll_cfg);
+
+/******************************************************************************/
+/*!
+ * Set the PLL configuration using the configuration parameters specified in
+ * \e pll_cfg.
+ *
+ * \param       pll
+ *              The PLL to set the configuration for.
+ *
+ * \param       pll_cfg
+ *              Pointer to a ALT_CLK_PLL_CFG_t structure specifying the desired
+ *              PLL configuration.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll,
+                                    const ALT_CLK_PLL_CFG_t* pll_cfg);
+
+/******************************************************************************/
+/*!
+ * Get the current PLL VCO frequency configuration.
+ *
+ * \param       pll
+ *              The PLL to get the VCO frequency configuration for.
+ *
+ * \param       mult
+ *              [out] Pointer to an output variable for the returned
+ *              configured PLL VCO multiplier (M) value.
+ *
+ * \param       div
+ *              [out] Pointer to an output variable for the returned
+ *              configured PLL VCO divider (N) value.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll,
+                                        uint32_t* mult,
+                                        uint32_t* div);
+
+/******************************************************************************/
+/*!
+ * Set the PLL VCO frequency configuration using the supplied multiplier and
+ * divider arguments.
+ *
+ * \param       pll
+ *              The PLL to set the VCO frequency configuration for.
+ *
+ * \param       mult
+ *              The PLL VCO multiplier (M). Expected argument range 1 to 4096.
+ *
+ * \param       div
+ *              The PLL VCO divider (N). Expected argument range 1 to 64.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll,
+                                        uint32_t mult,
+                                        uint32_t div);
+
+/******************************************************************************/
+/*!
+ * Get the VCO frequency of the specified PLL.
+ *
+ * \param       pll
+ *              The PLL to retrieve the VCO frequency from.
+ *
+ * \param       freq
+ *              [out] Pointer to the an output parameter variable to return the
+ *              PLL VCO frequency value. The frequency value is returned as a
+ *              measures of Hz.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   A bad argument value was passed. Either
+ *                              the \e pll argument is invalid or a bad
+ *                              \e freq pointer value was passed.
+ */
+ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll,
+                                         alt_freq_t* freq);
+
+/******************************************************************************/
+/*!
+ * Get the PLL frequency guard band value.
+ *
+ * \param       pll
+ *              The PLL from which to return the current guard band value.
+ *
+ * \returns     The current guard band range in effect for the PLL.
+ */
+uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll);
+
+/******************************************************************************/
+/*!
+ * Set the PLL frequency guard band value.
+ *
+ * Once a PLL has achieved lock, any changes to the PLL VCO frequency that are
+ * within a specific guard band range (default value 20%) of the reference
+ * period should not cause the PLL to lose lock.
+ *
+ * Programmatic changes to the PLL frequency within this guard band range are
+ * permitted to be made without the risk of breaking lock during the transition
+ * to the new frequency.
+ *
+ * The clk_mgr_pll_guard_band_set() function changes the guard band from its
+ * current value to permit a more lenient or stringent policy to be in effect in
+ * the implementation of the functions configuring PLL VCO frequency. The
+ * rationale for changing the default guard band value might be to accommodate
+ * unexpected environmental conditions (noise, temperature, and other
+ * instability factors) that may affect the PLLs ability to maintain lock during
+ * a frequency change.
+ *
+ * \param       pll
+ *              The PLL to set the guard band value for.
+ *
+ * \param       guard_band
+ *              The guard band value. Value should be 0 <= \e guard_band <= 100.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_ARG_RANGE The guard band value violates its range constraint.
+ */
+ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll,
+                                           uint32_t guard_band);
+
+/******************************************************************************/
+/*!
+ * Get the configured divider value for the specified clock.
+ *
+ * This function is used to get the configured values of both internal and
+ * external clock dividers.  The internal divider (PLL counters C0-C5) values
+ * are retrieved by specifying the clock name that is the divider output
+ * (e.g. ALT_CLK_MPU is used to get the Main PLL C0 counter value). \n
+ * It returns the actual divider value, not the encoded bitfield stored
+ * in the register, due to the variety of different encodings.
+ *
+ * \param       clk
+ *              The clock divider to get the value from.
+ *
+ * \param       div
+ *              [out] Pointer to an output variable for the returned clock
+ *              divider value.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   An invalid clock argument was specified or a
+ *                              clock that does not have a divider.
+ */
+ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk,
+                                    uint32_t* div);
+
+/******************************************************************************/
+/*!
+ * Set the divider value for the specified clock.
+ *
+ * This function is used to set the values of both internal and external clock
+ * dividers.  The internal divider (PLL counters C0-C5) values are set by
+ * specifying the clock name that is the divider output (e.g. ALT_CLK_MPU is
+ * used to set the Main PLL C0 counter value).
+ *
+ * \param       clk
+ *              The clock divider to set the value for.
+ *
+ * \param       div
+ *              The clock divider value. NOTE: The valid range of clock divider
+ *              values depends on the clock being configured. This is the
+ *              real divisor ratio, not how the divisor is coded into the
+ *              register, and is always one or greater.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   An invalid clock argument was specified or a
+ *                              clock that does not have a divider.
+ * \retval      ALT_E_ARG_RANGE The divider value violates the range constraints
+ *                              for the clock divider.
+ */
+ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk,
+                                    uint32_t div);
+
+/******************************************************************************/
+/*!
+ * Get the output frequency of the specified clock.
+ *
+ * \param       clk
+ *              The clock to retrieve the output frequency from.
+ *
+ * \param       freq
+ *              [out] Pointer to the an output parameter variable to return the
+ *              clock output frequency value. The frequency value is returned as
+ *              a measures of Hz.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   A bad argument value was passed. Either
+ *                              the \e clk argument is invalid or a bad
+ *                              \e freq pointer value was passed.
+ */
+ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk,
+                                 alt_freq_t* freq);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_INT Clock Manager Interrupt Management
+ *
+ * The functions in this group provide management of interrupts originating from
+ * the Clock Manager.
+ *
+ * The following interrupt request (IRQ) signals are sourced from the Clock
+ * Manager:
+ *
+ * * \b clkmgr_IRQ - Clock Manager lock status interrupt output.  The PLL lock 
+ *                   status interrupt is the logical \e OR of six interrupt
+ *                   sources defining the loss or achievement of lock status for
+ *                   each PLL. The six PLL lock status conditions are:
+ *                   - Main PLL Achieved Lock
+ *                   - Main PLL Lost Lock
+ *                   - Peripheral PLL Achieved Lock
+ *                   - Peripheral PLL Lost Lock
+ *                   - SDRAM PLL Achieved Lock
+ *                   - SDRAM PLL Lost Lock
+ *
+ *                   They are enumeratated by the type \ref ALT_CLK_PLL_LOCK_STATUS_t.
+ *
+ *                   Each PLL lock condition may be individually disabled/enabled 
+ *                   as a contributor to the determination of the \b clkmgr_IRQ
+ *                   assertion status.
+ *
+ *                   The alt_clk_lock_status_clear() function is used to clear
+ *                   the PLL lock conditions causing the \b clkmgr_IRQ
+ *                   assertion.
+ *
+ * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the 
+ *                      MPU to "wake up" after a transition of the Main PLL into
+ *                      or out of bypass mode has been safely achieved. The need
+ *                      for the "wake up" notification is because the PLL clocks
+ *                      pause for a short number of clock cycles during bypass
+ *                      state transition. ARM recommeds that the CPUs are placed
+ *                      in standby if the clocks are ever paused.
+ *
+ * NOTE: \b mpuwakeup_IRQ appears to be an Altera private interrupt and may not
+ *        be part of the public API although clearly it has important utility in
+ *        implementing safe changes to PLL settings and transitions into and out
+ *        of bypass mode.
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Disable the \b clkmgr_IRQ interrupt signal source lock status condition(s).
+ *
+ * This function disables one or more of the lock status conditions as
+ * contributors to the \b clkmgr_IRQ interrupt signal state.
+ *
+ * NOTE: A set bit for a PLL lock status condition in the mask value does not
+ * have the effect of enabling it as a contributor to the \b clkmgr_IRQ
+ * interrupt signal state. The function alt_clk_irq_enable is used to enable PLL
+ * lock status source condition(s).
+ *
+ * \param       lock_stat_mask
+ *              Specifies the PLL lock status conditions to disable as interrupt
+ *              source contributors. \e lock_stat_mask is a mask of logically
+ *              OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock
+ *              conditions to disable.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_BAD_ARG   The \e lock_stat_mask argument contains an
+ *                              unknown condition value.
+ */
+ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
+
+/******************************************************************************/
+/*!
+ * Enable the \b clkmgr_IRQ interrupt signal source lock status condition(s).
+ *
+ * This function enables one or more of the lock status conditions as
+ * contributors to the \b clkmgr_IRQ interrupt signal state.
+ *
+ * NOTE: A cleared bit for any PLL lock status condition in the mask value does
+ * not have the effect of disabling it as a contributor to the \b clkmgr_IRQ
+ * interrupt signal state. The function alt_clk_irq_disable is used to disable
+ * PLL lock status source condition(s).
+ *
+ * \param       lock_stat_mask
+ *              Specifies the PLL lock status conditions to enable as interrupt
+ *              source contributors. \e lock_stat_mask is a mask of logically
+ *              OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock
+ *              conditions to enable.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_BAD_ARG   The \e lock_stat_mask argument contains an
+ *                              unknown condition value.
+ */
+ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_GROUP_CFG Clock Group Configuration
+ *
+ * This API provides the ability to safely set the configuration of a clock
+ * group with a single function call.
+ *
+ * A clock group is defined as set of clocks and signals generated from a common
+ * PLL VCO. The PLL and its derived clocks are treated as a single clock
+ * group. The clocks sourced directly or indirectly from the PLL may or may not
+ * have these features:
+ * * Clock Gates
+ * * Clock Dividers
+ * * Clock Source Selection Options
+ *
+ * The use case for application of the Clock Group Configuration functions is the
+ * ability to safely configure an entire clock group from a known good clock
+ * group configuration using the run-time function alt_clk_group_cfg_raw_set().
+ *
+ * A known good clock group configuration may be generated by one of the
+ * following methods:
+ * 
+ * * As static design information generated by an ACDS clock configuration tool 
+ *   and passed to embedded software for dynamic loading.
+ * 
+ * * By calling alt_clk_group_cfg_raw_get() at run-time from an SoC FPGA that has
+ *   programmatically established a known good clock group configuration using
+ *   the clock manager API configuration functions.
+ * 
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Get the raw configuration state of the designated clock group.
+ *
+ * This function is used to capture the configuration state of the specified
+ * clock group in a private (raw) data structure.  The raw data structure may be
+ * saved and used later to restore the clock group configuration using
+ * alt_clk_group_cfg_raw_get().
+ *
+ * \param       clk_group
+ *              The clock group configuration to capture.
+ *
+ * \param       clk_group_raw_cfg
+ *              [out] A pointer to a private (raw) data structure to store the
+ *              captured clock group configuration.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_ERROR     Details about error status code
+ */
+ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group,
+                                          ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
+
+/******************************************************************************/
+/*!
+ * Set the clock group configuration.
+ *
+ * This function is used to safely set the configuration state of a clock
+ * group from a raw clock group configuration specification.  The raw clock
+ * group configuration specification may be a configuration previously 
+ * captured with alt_clk_group_cfg_raw_get() or a group clock configuration
+ * generated by an external utility.
+ *
+ * \param       clk_group_raw_cfg
+ *              A pointer to the specification to use in the configuration of
+ *              the clock group.
+ *
+ * \retval      ALT_E_SUCCESS       Successful status.
+ * \retval      ALT_E_ERROR         Details about error status code
+ * \retval      ALT_E_BAD_VERSION   The clock group configuration specification is
+ *                                  invalid for this device.
+ */
+ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
+
+/*! @} */
+
+/*! @} */
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_CLK_MGR_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h
new file mode 100644
index 0000000..d8a38f5
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h
@@ -0,0 +1,1236 @@
+/*! \file
+ *  Altera - GPIO Module
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_GPIO_H__
+#define __ALT_GPIO_H__
+
+#include <stdint.h>
+#include "hwlib.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /* __cplusplus */
+
+#define     ALT_GPIO_BITMASK                0x1FFFFFFF
+
+/* If the GPIO special test mode flag was not defined in the makefile,   */
+    /* set the ALT_GPIO_DATAREAD_TEST_MODE flag to false to specify that     */
+    /* the production code version of alt_gpio_port_data_read() is included. */
+    /* If the flag is defined as true in the makefile, then the test version */
+    /* located in the test code file is substituted instead of the version   */
+    /* in this file.                                                         */
+#ifndef     ALT_GPIO_DATAREAD_TEST_MODE
+#define     ALT_GPIO_DATAREAD_TEST_MODE     false
+#endif
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_API The General Purpose Input/Output Manager API
+ *
+ * This module defines the General Purpose Input/Output Manager API for 
+ * accessing, configuring, and controlling the General Purpose Input/Output 
+ * Manager resources. These include both the general-purpose GPIO signals and
+ * the input-only GPI signals that are shared with the DDR interface.\n \n
+ * The GPIO API presents two views or perspectives of the GPIO signals. The first
+ * is to view the GPIO signals in a traditional way, as separate GPIO ports
+ * each comprised of a number of GPIO bits. The second perspective is of a
+ * unified flat view that presents the GPIO and GPI signals as a set of indexed
+ * bits, a view that allows the programmer to mostly ignore the port and pin
+ * hardware configuration and read/write/configure the GPIO and GPI signals
+ * independently of the underlying hardware implementation.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions
+ *
+ * This functional group contains functions to control, configure and manage
+ * the general-purpose IO signals as individual signals or as groups of signals.
+ * This group of functions can operate on multiple bits within the same GPIO
+ * port and accepts a bit mask to specify which bits an operation will operate on.
+ * Other bits within the same GPIO port are not changed.
+ *
+ * This example shows how multiple drivers or applications can use this feature
+ * to easily prevent conflict while accessing the same GPIO port:
+ * \verbatim
+ #define DRIVER_0_GPIO_MSK   0x0010FF03;
+ #define DRIVER_1_GPIO_MSK   0x002000F8;
+ #define DRIVER_2_GPIO_MSK   0x03C00004;
+ #define DRIVER_3_GPIO_MSK   0x000F0000;
+
+    alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_0_GPIO_MSK, init_val0);
+    alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, init_val1);
+    alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_2_GPIO_MSK, init_val2);
+    alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_3_GPIO_MSK, init_val3);
+    alt_gpio_port_int_type_set(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, config_val1);
+ \endverbatim
+ *
+ *  @{
+ */
+/******************************************************************************/
+/*!
+ * This type definition enumerates the data direction (input or output) of 
+ * the GPIO signals.
+ */
+
+typedef enum ALT_GPIO_PIN_DIR_e
+{
+    /*! # */
+    ALT_GPIO_PIN_INPUT,
+    /*! # */
+    ALT_GPIO_PIN_OUTPUT
+} ALT_GPIO_PIN_DIR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the type of interrupt source 
+ * (level-triggered or edge-triggered) of the GPIO signals.
+ */
+
+typedef enum ALT_GPIO_PIN_TYPE_e
+{
+    /*! # */
+    ALT_GPIO_PIN_LEVEL_TRIG_INT,
+    /*! # */
+    ALT_GPIO_PIN_EDGE_TRIG_INT
+} ALT_GPIO_PIN_TYPE_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the polarity of the interrupt sources 
+ * (falling-edge or rising-edge for edge-triggered interrupts, active-low or
+ * active-high for level-triggered interrupts) of the GPIO signals.
+ */
+
+typedef enum ALT_GPIO_PIN_POL_e
+{
+    /*! Indicates active-low for level-triggered interrupts and
+     * falling-edge for edge-triggered interrupts */
+    ALT_GPIO_PIN_ACTIVE_LOW,
+
+    /*! Indicates active-high for level-triggered interrupts and
+     * rising-edge for edge-triggered interrupt */
+    ALT_GPIO_PIN_ACTIVE_HIGH
+} ALT_GPIO_PIN_POL_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates whether or not the debounce metastability
+ * flip-flops are inserted or not. These are used to debounce signals presented
+ * to the GPIO inputs. A signal must be steady for two periods of the
+ * gpio_db_clk clock before it is considered valid. The frequency of the
+ * gpio_db_clk clock may be set using the Clock Manager API.
+ */
+
+typedef enum ALT_GPIO_PIN_DEBOUNCE_e
+{
+    /*! # */
+    ALT_GPIO_PIN_NODEBOUNCE,
+    /*! # */
+    ALT_GPIO_PIN_DEBOUNCE
+} ALT_GPIO_PIN_DEBOUNCE_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates whether or not level-sensitive interrupts
+ * are synchronized to the internal pclk_intr clock. It has no effect for GPIO
+ * signals that are selected as outputs, or if the interrupt is not enabled,
+ * or if the interrupt is set to be edge-triggered. This is a port-wide option.
+ */
+
+typedef enum ALT_GPIO_PIN_SYNC_e
+{
+    /*! # */
+    ALT_GPIO_PIN_NOSYNC,
+    /*! # */
+    ALT_GPIO_PIN_SYNC
+} ALT_GPIO_PIN_SYNC_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the possible data states of the GPIO bits.
+ */
+
+typedef enum ALT_GPIO_PIN_DATA_e
+{
+    /*! # */
+    ALT_GPIO_PIN_DATAZERO,
+    /*! # */
+    ALT_GPIO_PIN_DATAONE
+} ALT_GPIO_PIN_DATA_t;
+
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the GPIO ports that the GPIO manager 
+ * handles.
+ */
+
+typedef enum ALT_GPIO_PORT_e
+{
+    /*!
+     * \b Port \b A - 29-bit GPIO port A.
+     */
+    ALT_GPIO_PORTA,
+
+    /*!
+     * \b Port \b B - 29-bit GPIO port B.
+     */
+    ALT_GPIO_PORTB,
+    
+    /*!
+     * \b Port \b C - 29-bit GPIO port C. \n 13 bits are used for GPIO signals,
+     *                14 bits are used for GPI-only signals that are shared
+     *                with the DDR interface, 2 bits are not used. Some signals
+     *                may not be connected on some versions. See the relevant
+     *                pin mux data.
+     */
+    ALT_GPIO_PORTC,
+
+    /*!
+     * \b Unknown \b Port - Used to indicate an error.
+     */
+    ALT_GPIO_PORT_UNKNOWN
+} ALT_GPIO_PORT_t;
+
+    
+/******************************************************************************/
+/*!
+ * This type definition enumerates the individual bits within the GPIO ports
+ * used by the GPIO manager. The bit-ordering must match the hardware 
+ * bit-ordering. Since the ordering and packing of bitfields is not 
+ * standardized in C/C++, the following are defined as masks. \n
+ * For example, to set bits 3 and 4 of GPIO port B outputs (assuming the bits
+ * had previously been set to outputs), the user could use the syntax: \par
+ * \b alt_gpio_port_data_write(\b ALT_GPIO_PORTB, \b ALT_GPIO_BIT3 \b | \b
+ * ALT_GPIO_BIT4);
+ */
+
+typedef enum ALT_GPIO_PORTBIT_e
+{
+    /*! # */
+    ALT_GPIO_BIT0 = ALT_TWO_TO_POW0,
+    /*! # */
+    ALT_GPIO_BIT1 = ALT_TWO_TO_POW1,
+    /*! # */
+    ALT_GPIO_BIT2 = ALT_TWO_TO_POW2,
+    /*! # */
+    ALT_GPIO_BIT3 = ALT_TWO_TO_POW3,
+    /*! # */
+    ALT_GPIO_BIT4 = ALT_TWO_TO_POW4,
+    /*! # */
+    ALT_GPIO_BIT5 = ALT_TWO_TO_POW5,
+    /*! # */
+    ALT_GPIO_BIT6 = ALT_TWO_TO_POW6,
+    /*! # */
+    ALT_GPIO_BIT7 = ALT_TWO_TO_POW7,
+    /*! #  */
+    ALT_GPIO_BIT8 = ALT_TWO_TO_POW8,
+    /*! # */
+    ALT_GPIO_BIT9 = ALT_TWO_TO_POW9,
+    /*! # */
+    ALT_GPIO_BIT10 = ALT_TWO_TO_POW10,
+    /*! # */
+    ALT_GPIO_BIT11 = ALT_TWO_TO_POW11,
+    /*! # */
+    ALT_GPIO_BIT12 = ALT_TWO_TO_POW12,
+    /*! # */
+    ALT_GPIO_BIT13 = ALT_TWO_TO_POW13,
+    /*! # */
+    ALT_GPIO_BIT14 = ALT_TWO_TO_POW14,
+    /*! # */
+    ALT_GPIO_BIT15 = ALT_TWO_TO_POW15,
+    /*! # */
+    ALT_GPIO_BIT16 = ALT_TWO_TO_POW16,
+    /*! # */
+    ALT_GPIO_BIT17 = ALT_TWO_TO_POW17,
+    /*! # */
+    ALT_GPIO_BIT18 = ALT_TWO_TO_POW18,
+    /*! # */
+    ALT_GPIO_BIT19 = ALT_TWO_TO_POW19,
+    /*! # */
+    ALT_GPIO_BIT20 = ALT_TWO_TO_POW20,
+    /*! # */
+    ALT_GPIO_BIT21 = ALT_TWO_TO_POW21,
+    /*! # */
+    ALT_GPIO_BIT22 = ALT_TWO_TO_POW22,
+    /*! # */
+    ALT_GPIO_BIT23 = ALT_TWO_TO_POW23,
+    /*! # */
+    ALT_GPIO_BIT24 = ALT_TWO_TO_POW24,
+    /*! # */
+    ALT_GPIO_BIT25 = ALT_TWO_TO_POW25,
+    /*! # */
+    ALT_GPIO_BIT26 = ALT_TWO_TO_POW26,
+    /*! # */
+    ALT_GPIO_BIT27 = ALT_TWO_TO_POW27,
+    /*! # */
+    ALT_GPIO_BIT28 = ALT_TWO_TO_POW28,
+    ALT_GPIO_BIT29 = ALT_TWO_TO_POW29,              /* Not currently used */
+    ALT_GPIO_BIT30 = ALT_TWO_TO_POW30,              /* Not currently used */
+    ALT_GPIO_BIT31 = (int32_t) (1UL<<31),           /* Not currently used */
+
+    ALT_GPIO_BITNUM_MAX = (28),
+    ALT_GPIO_BIT_MAX = (1 << ALT_GPIO_BITNUM_MAX),
+    ALT_END_OF_GPIO_PORT_SIGNALS = (32)
+} ALT_GPIO_PORTBIT_t;
+
+
+
+/******************************************************************************/
+/*!
+ * Sets the specified GPIO data bits to use the data direction(s) 
+ * specified.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to apply this 
+ *              operation to. Other bits (where mask bits equal zero) are 
+ *              not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ *              configure all data direction bits of the port.
+ * \param       config
+ *              The data-directions of the bits to be set in this operation.
+ *              Individual bits are: \n \b 0 - Use as an input (default). \n 
+ *              \b 1 - Use as an output.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the data direction configuration of selected bits of the 
+ * specified GPIO module.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to read and
+ *              return. Other bits (where mask bits equal zero) are returned 
+ *              as zero. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ *              return all data direction bits of the port.
+ *
+ * \retval      uint32_t \n Individual bits are: \n \b 0 - The signal is 
+ *              configured as an input.
+ *              \n \b 1 - The signal is configured as an output.
+ *
+ */
+uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask);
+
+/******************************************************************************/
+/*!
+ * Sets the GPIO data outputs of the specified GPIO module to a logic one or
+ * zero. Outputs are only set if the data direction for those bits is also
+ * set to configure them as outputs.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (mask bits equal one) to apply this
+ *              operation to. Other bits (mask bits equal zero) are
+ *              not changed.
+ * \param       val
+ *              The 32-bit word to write to the GPIO outputs. Only the 29 LSBs 
+ *              are used. Setting the three MSBs causes an error.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t val);
+
+/******************************************************************************/
+/*!
+ * Returns the value of the data inputs of the specified GPIO module. This is
+ * the current logic value of the pin, whether set to be an input or an output.
+ * \n If a given signal is set to be an output, this input value can be read to
+ * determine if the pin is grounded, pulled high, or is floating.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to return. Other 
+ *              bits (where mask bits equal zero) are returned as zero. Specify 
+ *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all data bits of
+ *              the port.
+ *
+ * \retval      uint32_t   The current value of the GPIO module input signals.
+ */
+uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask);
+
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions
+ *
+ * This functional group contains functions to control and manage the
+ * interrupts of the General-Purpose IO modules.
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Sets edge-triggered or level-triggered interrupt configuration for the 
+ * specified signals of the specified GPIO module.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to apply this 
+ *              operation to. Other bits (where mask bits equal zero) are
+ *              not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ *              configure all interrupt type bits of the port.
+ * \param       config
+ *              The interrupt configuration to write. Individual bits 
+ *              are: \n \b 0 - Set the 
+ *              interrupt for this bit to be level-sensitive (default). \n \b 
+ *              1 - Set the interrupt for this bit to be edge-sensitive.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the interrupt configuration (edge-triggered or level-triggered) for 
+ * the specified bits of the specified GPIO module. 
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to return. Other 
+ *              bits (where mask bits equal zero) are returned as zero. Specify 
+ *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all configuration
+ *              bits of the port.
+ * \retval      uint32_t
+ *              The current interrupt source configuration. Individual bits 
+ *              are: \n \b 0 - The interrupt for this bit is set to be 
+ *              level-sensitive. \n \b 1 - 
+ *              The interrupt for this bit is set to be edge-sensitive.
+ *
+ */
+uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask);
+
+/******************************************************************************/
+/*!
+ * Sets the interrupt polarity of the signals of the specified GPIO register
+ * (when used as inputs) to active-high or active-low (for level-sensitive
+ * interrupts) or to rising-edge or falling-edge (for edge-sensitive interrupts).
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to apply this 
+ *              operation to. Other bits (where mask bits equal zero) are
+ *              not changed.
+ * \param       config
+ *              The interrupt polarity configuration to set. Individual bits 
+ *              are: \n \b 0 - Set the interrupt polarity for this bit to 
+ *              active-low or falling-edge mode (default). \n \b 1 - Set the
+ *              interrupt polarity for this bit to active-high or rising-edge mode.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the active-high or active-low polarity configuration for the 
+ * possible interrupt sources of the specified GPIO module.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to return. Other 
+ *              bits (where mask bits equal zero) are returned as zero. Specify 
+ *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all the
+ *              configuration bits of the port.
+ *                 
+ * \retval      uint32_t
+ *              The current polarity configuration. Individual bits are: \n 
+ *              \b 0 = The interrupt polarity for this bit is set to 
+ *              active-low or falling-edge mode. \n \b 1 = The interrupt
+ *              polarity for this bit is set to active-high or rising-edge mode.
+ *
+ */
+uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask);
+
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Sets the debounce configuration for input signals of the specified GPIO 
+ * module. If debounce is selected, metastability flip-flops are inserted to
+ * debounce signals presented to the GPIO inputs. A signal must be steady for
+ * two periods of the gpio_db_clk clock before it is considered valid. The
+ * frequency of the gpio_db_clk clock may be set using the Clock Manager API.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to apply this 
+ *              operation to. Other bits (where mask bits equal zero) are
+ *              not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ *              configure the debounce setting for all bits of the port.
+ * \param       config
+ *              The debounce configuration to set. Individual bits are: \n
+ *              \b 0 - Debounce is not selected for this signal (default). \n 
+ *              \b 1 - Debounce is selected for this signal.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the debounce configuration for the input signals of the specified
+ * GPIO register. If debounce is selected, metastability flip-flops are
+ * inserted to debounce signals presented to the GPIO inputs.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to return. Other 
+ *              bits (where mask bits equal zero) are returned as zero. Specify 
+ *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all debounce
+ *              configuration bits of the port.
+ *                 
+ * \retval      uint32_t
+ *              The current debounce configuration.Individual bits are: \n 
+ *              \b 0 - Debounce is not selected for this signal. \n \b 1 - 
+ *              Debounce is selected for this signal.
+ *
+ */
+uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask);
+
+/******************************************************************************/
+/*!
+ * Sets the synchronization configuration for the signals of the specified 
+ * GPIO register. This allows for synchronizing level-sensitive interrupts to 
+ * an internal clock signal. This is a port-wide option that controls all
+ * level-sensitive interrupt signals of that GPIO port.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       config
+ *              \n \b Any \b non-zero \b value - Synchronize to internal clock signal.
+ *              \n \b Zero - Do not synchronize to internal clock signal.
+ * 
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t config);
+
+/******************************************************************************/
+/*!
+ *
+ * Returns the synchronization configuration for the signals of the 
+ * specified GPIO register. This allows for synchronizing level-sensitive 
+ * interrupts to the internal clock signal. This is a port-wide option that
+ * controls all level-sensitive interrupt signals of that GPIO port.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+
+
+ * \retval      ALT_E_TRUE      Synchronization to clock is enabled for
+ *                              level-sensitive interrupts.
+ * \retval      ALT_E_FALSE     Synchronization to clock is disabled for
+ *                              level-sensitive interrupts.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Configures a group of GPIO signals with identical setup parameters. Allows
+ * for configuring all parameters of a given port at one time.
+ * 
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits to apply this operation to. Other bits (mask
+ *              set to zero) are not changed.
+ * \param       dir
+ *              Data direction.
+ * \param       type
+ *              Edge-triggered or level-triggered interrupts.
+ * \param       pol
+ *              Active-high or active-low polarity.
+ * \param       debounc
+ *              Debounce signals or not.
+ * \param       data
+ *              Set the data output to this value.
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+        
+ */
+ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
+        ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounc,
+        uint32_t data);
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions
+ *
+ *  @{
+ */
+/******************************************************************************/
+/*!
+ * Enables the specified GPIO data input interrupts.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       config
+ *              Individual bit interrupt enables \n
+ *              \b 0 - Interrupt disabled. \n
+ *              \b 1 - Interrupt enabled.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_enable(ALT_GPIO_PORT_t gpio_pid, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Disables the specified GPIO data module interrupt.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       config
+ *              Individual bit interrupt enables \n
+ *              \b 0 - Interrupt disabled. \n
+ *              \b 1 - Interrupt enabled.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_disable(ALT_GPIO_PORT_t gpio_pid, uint32_t config);
+
+/******************************************************************************/
+/*!
+ *  Returns the current state of the specified GPIO port interrupts enables.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ *
+ * \retval      uint32_t
+ *              The interrupt enable configuration that was read. Individual bits
+ *              are: \n \b 0 = The interrupt for this bit is not enabled. \n \b
+ *              1 = The interrupt for this bit is enabled.
+ */
+uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid);
+
+
+/******************************************************************************/
+/*!
+ * Masks or unmasks selected interrupt source bits of the data register of
+ * the specified GPIO module. Uses a second bit mask to determine which
+ * signals may be changed by this call.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              Which bits to change among the port \n \b 0 = 
+ *              Do not change this bit. \n \b 1 = Allow this bit to change.
+ * \param       val
+ *              The interrupt mask to write. Individual bits are: \n \b 0 = 
+ *              Do not mask the interrupt for this bit (default). \n \b 1 = 
+ *              Mask the interrupt for this bit.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t val);
+
+/******************************************************************************/
+/*!
+ * Returns the interrupt mask of the specified GPIO module.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ *                 
+ * \retval      uint32_t
+ *              The interrupt mask that was read. Individual bits are: \n 
+ *              \b 0 = The interrupt for this bit is not masked. \n \b 1 = The 
+ *              interrupt for this bit is masked.
+ *
+ */
+uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Returns the interrupt pending status of all signals of the specified GPIO 
+ * register.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ 
+ * \retval      uint32_t
+ *              The current interrupt pending status. Individual bits are: \n 
+ *              \b 0 - The interrupt for this bit is not pending. \n \b 1 - 
+ *              The interrupt for this bit is pending.
+ *
+ */
+uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Clear the interrupt pending status of selected signals of the 
+ * specified GPIO register.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       clrmask
+ *              The interrupt bits to clear. Individual bits are: \n \b 0 - 
+ *              The interrupt for this bit will not be changed. \n \b 1 - 
+ *              The interrupt for this bit will be cleared.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_status_clear(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t clrmask);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index
+ *
+ * This functional group presents a perspective of the General-Purpose IO
+ * signals as individual GPIO and GPI bits spread across a number of signals
+ * across several GPIO ports. This allows the programmer the freedom to generally
+ * ignore the underlying port and signal structure of the GPIO hardware if
+ * desired.
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * This type definition enumerates the individual bits as one flat array spread
+ * across the multiple GPIO ports handled by the GPIO manager. The bit-ordering
+ * must match the hardware bit-ordering.
+ *
+ */
+typedef enum ALT_GPIO_1BIT_e
+{
+    /*! # */
+    ALT_GPIO_1BIT_0,
+    /*! # */
+    ALT_GPIO_1BIT_1,
+    /*! # */
+    ALT_GPIO_1BIT_2,
+    /*! # */
+    ALT_GPIO_1BIT_3,
+    /*! # */
+    ALT_GPIO_1BIT_4,
+    /*! # */
+    ALT_GPIO_1BIT_5,
+    /*! # */
+    ALT_GPIO_1BIT_6,
+    /*! # */
+    ALT_GPIO_1BIT_7,
+    /*! # */
+    ALT_GPIO_1BIT_8,
+    /*! # */
+    ALT_GPIO_1BIT_9,
+    /*! # */
+    ALT_GPIO_1BIT_10,
+    /*! # */
+    ALT_GPIO_1BIT_11,
+    /*! # */
+    ALT_GPIO_1BIT_12,
+    /*! # */
+    ALT_GPIO_1BIT_13,
+    /*! # */
+    ALT_GPIO_1BIT_14,
+    /*! # */
+    ALT_GPIO_1BIT_15,
+    /*! # */
+    ALT_GPIO_1BIT_16,
+    /*! # */
+    ALT_GPIO_1BIT_17,
+    /*! # */
+    ALT_GPIO_1BIT_18,
+    /*! # */
+    ALT_GPIO_1BIT_19,
+    /*! # */
+    ALT_GPIO_1BIT_20,
+    /*! # */
+    ALT_GPIO_1BIT_21,
+    /*! # */
+    ALT_GPIO_1BIT_22,
+    /*! # */
+    ALT_GPIO_1BIT_23,
+    /*! # */
+    ALT_GPIO_1BIT_24,
+    /*! # */
+    ALT_GPIO_1BIT_25,
+    /*! # */
+    ALT_GPIO_1BIT_26,
+    /*! # */
+    ALT_GPIO_1BIT_27,
+    /*! # */
+    ALT_GPIO_1BIT_28,
+    /*! # */
+    ALT_GPIO_1BIT_29,
+    /*! # */
+    ALT_GPIO_1BIT_30,
+    /*! # */
+    ALT_GPIO_1BIT_31,
+    /*! # */
+    ALT_GPIO_1BIT_32,
+    /*! # */
+    ALT_GPIO_1BIT_33,
+    /*! # */
+    ALT_GPIO_1BIT_34,
+    /*! # */
+    ALT_GPIO_1BIT_35,
+    /*! # */
+    ALT_GPIO_1BIT_36,
+    /*! # */
+    ALT_GPIO_1BIT_37,
+    /*! # */
+    ALT_GPIO_1BIT_38,
+    /*! # */
+    ALT_GPIO_1BIT_39,
+    /*! # */
+    ALT_GPIO_1BIT_40,
+    /*! # */
+    ALT_GPIO_1BIT_41,
+    /*! # */
+    ALT_GPIO_1BIT_42,
+    /*! # */
+    ALT_GPIO_1BIT_43,
+    /*! # */
+    ALT_GPIO_1BIT_44,
+    /*! # */
+    ALT_GPIO_1BIT_45,
+    /*! # */
+    ALT_GPIO_1BIT_46,
+    /*! # */
+    ALT_GPIO_1BIT_47,
+    /*! # */
+    ALT_GPIO_1BIT_48,
+    /*! # */
+    ALT_GPIO_1BIT_49,
+    /*! # */
+    ALT_GPIO_1BIT_50,
+    /*! # */
+    ALT_GPIO_1BIT_51,
+    /*! # */
+    ALT_GPIO_1BIT_52,
+    /*! # */
+    ALT_GPIO_1BIT_53,
+    /*! # */
+    ALT_GPIO_1BIT_54,
+    /*! # */
+    ALT_GPIO_1BIT_55,
+    /*! # */
+    ALT_GPIO_1BIT_56,
+    /*! # */
+    ALT_GPIO_1BIT_57,
+    /*! # */
+    ALT_GPIO_1BIT_58,
+    /*! # */
+    ALT_GPIO_1BIT_59,
+    /*! # */
+    ALT_GPIO_1BIT_60,
+    /*! # */
+    ALT_GPIO_1BIT_61,
+    /*! # */
+    ALT_GPIO_1BIT_62,
+    /*! # */
+    ALT_GPIO_1BIT_63,
+    /*! # */
+    ALT_GPIO_1BIT_64,
+    /*! # */
+    ALT_GPIO_1BIT_65,
+    /*! # */
+    ALT_GPIO_1BIT_66,
+    /*! # */
+    ALT_GPIO_1BIT_67,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_GPIO_1BIT_68,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_GPIO_1BIT_69,        /* Not bonded out on some versions */
+
+    /*! The last of the input/output bits */
+    ALT_GPIO_1BIT_70,        /* Not bonded out on some versions */
+
+
+    /*! This and the following signals are not present on all SoCs. \n
+     * If present, the selection between their use as 14 General-purpose inputs or
+     * use as 14 DDR interface signals is made in the IOCSR (IO Configuration Shift
+     * Register) and software to make this selection is in the IO Manager API. If
+     * they are present, they are restricted to using the same power supply voltage
+     * as the SDRAM module.*/
+    ALT_HLGPI_0,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_1,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_2,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_3,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_4,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_5,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_6,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_7,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_8,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_9,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_10,       /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_11,       /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_12,       /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_13,       /* Not bonded out on some versions */
+
+    ALT_HLGPI_14,       /* Not bonded out */
+
+    ALT_HLGPI_15,       /* Not bonded out */
+
+    ALT_GPIO_INVALID,
+    ALT_END_OF_GPIO_SIGNALS = -1,
+    ALT_LAST_VALID_GPIO_BIT = ALT_HLGPI_15
+} ALT_GPIO_1BIT_t;
+
+
+/******************************************************************************/
+/*!
+ * This configuration record definition is used for configuring bits and
+ * groups of bits of the GPIO interface.
+ */
+typedef struct ALT_GPIO_CONFIG_RECORD_s
+{
+    /*!
+     * The index number of the signal to configure. */
+    ALT_GPIO_1BIT_t             signal_number;
+    /*!
+     * The data direction of the signal. */
+    ALT_GPIO_PIN_DIR_t          direction;
+    /*!
+     * Edge-triggered or level triggered interrupts. */
+    ALT_GPIO_PIN_TYPE_t         type;
+    /*!
+     * Active-high or active-low trigger for the interrupt. */
+    ALT_GPIO_PIN_POL_t          polarity;
+    /*!
+     * Enable or disable GPIO debounce capability. */
+    ALT_GPIO_PIN_DEBOUNCE_t     debounce;
+    /*!
+     * If the signal is an output, the data value to be output. */
+    ALT_GPIO_PIN_DATA_t         data;
+} ALT_GPIO_CONFIG_RECORD_t;
+
+/******************************************************************************/
+/*!
+ * This pin record type definition is comprised of the signal index and
+ * associated input or output data.
+ */
+typedef struct ALT_GPIO_PIN_RECORD_s
+{
+    /*!
+     * The index number of the signal. */
+    ALT_GPIO_1BIT_t         signal_number;
+    /*!
+     * Data - zero or one. */
+    ALT_GPIO_PIN_DATA_t     val;
+} ALT_GPIO_PIN_RECORD_t;
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Configures all parameters for one bit (signal) of the GPIO ports.
+ * 
+ * \param       signal_num
+ *              The GPIO port signal index.
+ * \param       dir
+ *              The data direction for this signal.
+ * \param       type
+ *              Edge-triggered or Level-triggered interrupt for this signal.
+ * \param       pol
+ *              Active-high or active-low interrupt polarity for this signal.
+ * \param       debounce
+ *              Enable the debounce flip-flops for this signal or not.
+ * \param       data
+ *              If the GPIO signal is set to be an output, set it to
+ *              this value
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num,
+        ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
+        ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounce,
+        ALT_GPIO_PIN_DATA_t data);
+
+/******************************************************************************/
+/*!
+ * Returns the configuration parameters of a given GPIO bit.
+ * 
+ * \param       signal_num
+ *              The GPIO port signal index.
+ * \param       config
+ *              Pointer to a single GPIO_CONFIG_RECORD_s configuration record.
+ *              The fields of this configuration record are filled in
+ *              by the function.         
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+        
+ */
+ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num,
+        ALT_GPIO_CONFIG_RECORD_t *config);
+
+/******************************************************************************/
+/*!
+ * Configures a list of GPIO bits. The GPIO bits do not have to be 
+ * configured the same, as was the case for the mask version of this function, 
+ * alt_gpio_port_config(). Each bit may be configured differently and bits may
+ * be listed in any order.
+ * 
+ * \param       config_array
+ *              Pointer to an array of GPIO_CONFIG_RECORD_s configuration
+ *              records. These definitions contain all the parameters
+ *              needed to set up the listed pins. All or 
+ *              any subset of the GPIO signals can be configured. Signals do 
+ *              not have to be listed in numerical order or be unique. If a 
+ *              signal number is listed multiple times, the last configuration 
+ *              listed is used. \n Configuration terminates either when \b len
+ *              signals have been configured or if the next signal number index
+ *              in the array is equal to \b ALT_END_OF_GPIO_SIGNALS (-1).
+ *              
+ * \param       len
+ *              Length of array to configure. 
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+        
+ */
+ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array,
+        uint32_t len);
+
+/******************************************************************************/
+/*!
+ * Returns a list of the pin signal indices and the associated configuration 
+ * settings (data direction, interrupt type, polarity, and debounce) of that
+ * list of signals.
+ *  
+ * \param       config_array
+ *              Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration
+ *              records. Only the signal indices in the first field of each
+ *              configuration record need be filled in. This function will
+ *              fill in all the other fields of the configuration record,
+ *              returning all configuration parameters in the array.
+ *              Signals do not have to be listed in numerical order or be 
+ *              unique. If a signal number is listed multiple times, the 
+ *              configuration record will contain multiple entries for
+ *              that signal. \n Configuration reading terminates either when
+ *              \b len signal configurations have been read or if the next
+ *              signal number index in the array is equal to
+ *              \b ALT_END_OF_GPIO_SIGNALS (-1).
+ * \param       len
+ *              Length of configuration array to read and return. 
+ *                 
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+        
+ */
+ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array,
+        uint32_t len);
+
+/******************************************************************************/
+/*!
+ * Returns a list of the pin signal indices and the associated configuration
+ * settings (data direction, interrupt type, polarity, and debounce) of that
+ * list of signals. The difference between this version and
+ * alt_gpio_group_config_get() is this version follows a separate list of
+ * signal indices instead of having the signal list provided in the first
+ * field of the configuration records in the array.
+ *                
+ * \param       pinid_array
+ *              Pointer to a list of signal index numbers. These indices
+ *              are copied to the first field of each configuration record
+ *              in the returned array.
+ * \param       config_array
+ *              Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration
+ *              records. This function will fill in the fields of the 
+ *              configuration record, returning all configuration parameters 
+ *              in the array. Signals do not have to be listed in numerical 
+ *              order or be unique. If a signal number is listed multiple 
+ *              times, the configuration record array will contain multiple 
+ *              identical entries for that signal. \n Configuration reading
+ *              terminates either when \b len signal configurations have been
+ *              read or if the next signal number index in the array is equal
+ *              to \b ALT_END_OF_GPIO_SIGNALS (-1).
+ * \param       len
+ *              Length of configuration array to read. 
+ *                 
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ *         
+ */
+ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array,
+        ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len);
+
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_UTILITY General-Purpose IO Utility Functions
+ *
+ * These are useful utility functions for the general-purpose input & output
+ * module.
+ *
+ * @{ */
+/******************************************************************************/
+/*!
+ * Returns the ID code of the specified GPIO module.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ *
+ *
+ * \retval      uint32_t    The component code of the module, GPIO_MODULE_IDCODE.
+ */
+uint32_t alt_gpio_port_idcode_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Returns the version code of the specified GPIO module.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ *
+ *
+ * \retval      uint32_t      The encoded revision number of the module.
+ */
+uint32_t alt_gpio_port_ver_get(ALT_GPIO_PORT_t gpio_pid);
+
+
+/******************************************************************************/
+/*!
+ * Extracts the GPIO port ID from the supplied GPIO Signal Index Number.
+ */
+ALT_GPIO_PORT_t alt_gpio_bit_to_pid(ALT_GPIO_1BIT_t pin_num);
+
+
+/******************************************************************************/
+/*!
+ * Extracts the GPIO signal (pin) offset from the supplied GPIO Signal Index
+ * Number.
+ *  */
+ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num);
+
+/******************************************************************************/
+/*!
+ * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and 
+ * signal mask. If passed a bitmask composed of more than one signal, the 
+ * signal number of the lowest bit in the bitmask presented is returned.
+ * 
+ */
+ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid,
+        uint32_t bitmask);
+
+
+/*! @} */
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_GPIO_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h
new file mode 100644
index 0000000..57f0f0d
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h
@@ -0,0 +1,52 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_HWLIBS_VER_H__
+
+/***********************************************************************
+ *
+ * Set of macros to provide version information
+ *
+ ***********************************************************************/
+
+/* This is the major revision of the Altera ACDS Release    */
+#define ALTERA_ACDS_MAJOR_REV           13
+
+/* This is the minor revision of the Altera ACDS Release    */
+#define ALTERA_ACDS_MINOR_REV            0
+
+/* This is an internal HwLibs revision control code.        */
+/* End-users should NOT depend upon the value of this field */
+#define ALTERA_HWLIBS_REV                0
+
+/* This is a text string containing the current release and service pack IDs */
+#define ALTERA_ACDS_REV_STR             "13.0SP1"
+
+#endif   /* __ALT_HWLIBS_VER_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h
new file mode 100644
index 0000000..db1e6dd
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h
@@ -0,0 +1,531 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_INT_COMMON_H__
+#define __ALT_INT_COMMON_H__
+
+#include "hwlib.h"
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*!
+ * \addtogroup INT_COMMON Interrupt Controller Common Definitions
+ *
+ * This module contains the definitions common to the Interrupt Controller
+ * Low-Level API and Interrupt Controller Manager Interface.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates all the interrupt identification types.
+ */
+typedef enum ALT_INT_INTERRUPT_e
+{
+    ALT_INT_INTERRUPT_SGI0  =  0, /*!< # */
+    ALT_INT_INTERRUPT_SGI1  =  1, /*!< # */
+    ALT_INT_INTERRUPT_SGI2  =  2, /*!< # */
+    ALT_INT_INTERRUPT_SGI3  =  3, /*!< # */
+    ALT_INT_INTERRUPT_SGI4  =  4, /*!< # */
+    ALT_INT_INTERRUPT_SGI5  =  5, /*!< # */
+    ALT_INT_INTERRUPT_SGI6  =  6, /*!< # */
+    ALT_INT_INTERRUPT_SGI7  =  7, /*!< # */
+    ALT_INT_INTERRUPT_SGI8  =  8, /*!< # */
+    ALT_INT_INTERRUPT_SGI9  =  9, /*!< # */
+    ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */
+    ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */
+    ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */
+    ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */
+    ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */
+    ALT_INT_INTERRUPT_SGI15 = 15,
+    /*!<
+     * Software Generated Interrupts (SGI), 0 - 15.
+     *  * All interrupts in this group are software triggered.
+     */
+
+    ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL   = 27, /*!< # */
+    ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE  = 29, /*!< # */
+    ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */
+    /*!<
+     * Private Peripheral Interrupts (PPI) for the Global Timer, per CPU
+     * private timer, and watchdog timer.
+     *  * All interrupts in this group are edge triggered.
+     */
+
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL         = 32, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC    = 33, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB     = 34, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG   = 35, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA  = 36, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB     = 37, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG   = 39, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA  = 40, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS0           = 41, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS1           = 42, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS2           = 43, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS3           = 44, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS4           = 45, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS5           = 46, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS6           = 47,
+    /*!<
+     * Interrupts sourced from CPU0.
+     *
+     * The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the
+     * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
+     * for CPU0.
+     *
+     *  * PARITYFAIL interrupts in this group are edge triggered.
+     *  * DEFFLAGS interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL         = 48, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC    = 49, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB     = 50, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG   = 51, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA  = 52, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB     = 53, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG   = 55, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA  = 56, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS0           = 57, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS1           = 58, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS2           = 59, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS3           = 60, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS4           = 61, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS5           = 62, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS6           = 63,
+    /*!<
+     * Interrupts sourced from CPU1.
+     *
+     * The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the
+     * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
+     * for CPU1.
+     *
+     *  * PARITYFAIL interrupts in this group are edge triggered.
+     *  * DEFFLAGS interrupts in this group are level triggered.
+     */
+    
+    ALT_INT_INTERRUPT_SCU_PARITYFAIL0 =  64, /*!< # */
+    ALT_INT_INTERRUPT_SCU_PARITYFAIL1 =  65, /*!< # */
+    ALT_INT_INTERRUPT_SCU_EV_ABORT    =  66,
+    /*!<
+     * Interrupts sourced from the Snoop Control Unit (SCU).
+     *  * All interrupts in this group are edge triggered.
+     */
+    
+    ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ     = 67, /*!< # */
+    ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ   = 68, /*!< # */
+    ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */
+    ALT_INT_INTERRUPT_L2_COMBINED_IRQ        = 70,
+    /*!<
+     * Interrupts sourced from the L2 Cache Controller.
+     *
+     * The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache
+     * controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR,
+     * ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts.
+     * Consult the L2C documentation for information on these interrupts.
+     *
+     *  * ECC interrupts in this group are edge triggered.
+     *  * Other interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ =  71,
+    /*!<
+     * Interrupts sourced from the SDRAM Controller.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ0  =  72, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ1  =  73, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ2  =  74, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ3  =  75, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ4  =  76, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ5  =  77, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ6  =  78, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ7  =  79, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ8  =  80, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ9  =  81, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 =  82, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 =  83, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 =  84, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 =  85, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 =  86, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 =  87, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 =  88, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 =  89, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 =  90, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 =  91, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 =  92, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 =  93, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 =  94, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 =  95, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 =  96, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 =  97, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 =  98, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 =  99, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135,
+    /*!<
+     * Interrupt request from the FPGA logic, 0 - 63.
+     *  * Trigger type depends on the implementation in the FPGA.
+     */
+
+    ALT_INT_INTERRUPT_DMA_IRQ0                = 136, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ1                = 137, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ2                = 138, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ3                = 139, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ4                = 140, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ5                = 141, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ6                = 142, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ7                = 143, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ_ABORT           = 144, /*!< # */
+    ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ   = 145, /*!< # */
+    ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146,
+    /*!<
+     * Interrupts sourced from the DMA Controller.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_EMAC0_IRQ                    = 147, /*!< # */
+    ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ   = 148, /*!< # */
+    ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */
+    ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ   = 150, /*!< # */
+    ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151,
+    /*!<
+     * Interrupts sourced from the Ethernet MAC 0 (EMAC0).
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_EMAC1_IRQ                    = 152, /*!< # */
+    ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ   = 153, /*!< # */
+    ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */
+    ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ   = 155, /*!< # */
+    ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156,
+    /*!<
+     * Interrupts sourced from the Ethernet MAC 1 (EMAC1).
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_USB0_IRQ             = 157, /*!< # */
+    ALT_INT_INTERRUPT_USB0_ECC_CORRECTED   = 158, /*!< # */
+    ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159,
+    /*!<
+     * Interrupts sourced from the USB OTG 0.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_USB1_IRQ             = 160, /*!< # */
+    ALT_INT_INTERRUPT_USB1_ECC_CORRECTED   = 161, /*!< # */
+    ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162,
+    /*!<
+     * Interrupts sourced from the USB OTG 1.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_CAN0_STS_IRQ             = 163, /*!< # */
+    ALT_INT_INTERRUPT_CAN0_MO_IRQ              = 164, /*!< # */
+    ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ   = 165, /*!< # */
+    ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166,
+    /*!<
+     * Interrupts sourced from the CAN Controller 0.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_CAN1_STS_IRQ             = 167, /*!< # */
+    ALT_INT_INTERRUPT_CAN1_MO_IRQ              = 168, /*!< # */
+    ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ   = 169, /*!< # */
+    ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170,
+    /*!<
+     * Interrupts sourced from the CAN Controller 1.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_SDMMC_IRQ                   = 171, /*!< # */
+    ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED   = 172, /*!< # */
+    ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */
+    ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED   = 174, /*!< # */
+    ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175,
+    /*!<
+     * Interrupts sourced from the SDMMC Controller.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_NAND_IRQ                  = 176, /*!< # */
+    ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ   = 177, /*!< # */
+    ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */
+    ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ   = 179, /*!< # */
+    ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */
+    ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ   = 181, /*!< # */
+    ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182,
+    /*!<
+     * Interrupts sourced from the NAND Controller.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_QSPI_IRQ                 = 183, /*!< # */
+    ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ   = 184, /*!< # */
+    ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185,
+    /*!<
+     * Interrupts sourced from the QSPI Controller.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */
+    ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */
+    ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */
+    ALT_INT_INTERRUPT_SPI3_IRQ = 189,
+    /*!<
+     * Interrupts sourced from the SPI Controllers 0 - 3.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */
+    ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */
+    ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */
+    ALT_INT_INTERRUPT_I2C3_IRQ = 193,
+    /*!<
+     * Interrupts sourced from the I2C Controllers 0 - 3.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_UART0 = 194, /*!< # */
+    ALT_INT_INTERRUPT_UART1 = 195,
+    /*!<
+     * Interrupts sourced from the UARTs 0 - 1.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */
+    ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */
+    ALT_INT_INTERRUPT_GPIO2 = 198,
+    /*!<
+     * Interrupts sourced from the GPIO 0 - 2.
+     *  * All interrupts in this group are level triggered.
+     */
+    
+    ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */
+    ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */
+    ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */
+    ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202,
+    /*!<
+     * Interrupts sourced from the Timer controllers.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */
+    ALT_INT_INTERRUPT_WDOG1_IRQ = 204,
+    /*!<
+     * Interrupts sourced from the Watchdog Timers 0 - 1.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_CLKMGR_IRQ = 205,
+    /*!<
+     * Interrupts sourced from the Clock Manager.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206,
+    /*!<
+     * Interrupts sourced from the Clock Manager MPU Wakeup.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207,
+    /*!<
+     * Interrupts sourced from the FPGA Manager.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */
+    ALT_INT_INTERRUPT_NCTIIRQ1 = 209,
+    /*!<
+     * Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ   = 210, /*!< # */
+    ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211
+    /*!<
+     * Interrupts sourced from the On-chip RAM.
+     *  * All interrupts in this group are level triggered.
+     */
+
+} ALT_INT_INTERRUPT_t;
+
+/*!
+ * This is the CPU target type. It is used to specify a set of CPUs on the
+ * system. If only bit 0 is set then it specifies a set of CPUs containing
+ * only CPU 0. Multiple CPUs can be specified by setting the appropriate bit
+ * up to the number of CPUs on the system.
+ */
+typedef uint32_t alt_int_cpu_target_t;
+
+/*!
+ * This type definition enumerates all the interrupt trigger types.
+ */
+typedef enum ALT_INT_TRIGGER_e
+{
+    /*!
+     * Edge triggered interrupt. This applies to Private Peripheral Interrupts
+     * (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs
+     * 16 - 1019.
+     */
+    ALT_INT_TRIGGER_EDGE,
+
+    /*!
+     * Level triggered interrupt. This applies to Private Peripheral
+     * Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with
+     * interrupt IDs 16 - 1019.
+     */
+    ALT_INT_TRIGGER_LEVEL,
+
+    /*!
+     * Software triggered interrupt. This applies to Software Generated
+     * Interrupts (SGI) only, with interrupt IDs 0 - 15.
+     */
+    ALT_INT_TRIGGER_SOFTWARE,
+
+    /*!
+     * All triggering types except for those in the Shared Peripheral Interrupts
+     * (SPI) F2S FPGA family interrupts can be determined by the system
+     * automatically. In all functions which ask for the triggering type, the
+     * ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger
+     * type for all non F2S interrupt types.
+     */
+    ALT_INT_TRIGGER_AUTODETECT,
+
+    /*!
+     * The interrupt triggering information is not applicable. This is possibly
+     * due to querying an invalid interrupt identifier.
+     */
+    ALT_INT_TRIGGER_NA
+}
+ALT_INT_TRIGGER_t;
+
+/*!
+ * This type definition enumerates all the target list filter options. This is
+ * used by the trigger Software Generated Interrupt (SGI) feature to issue a
+ * SGI to the specified processor(s) in the system. Depending on the target
+ * list filter and the target list, interrupts can be routed to any
+ * combinations of CPUs.
+ */
+typedef enum ALT_INT_SGI_TARGET_e
+{
+    /*!
+     * This filter list uses the target list parameter to specify which CPUs
+     * to send the interrupt to. If target list is 0, no interrupts are sent.
+     */
+    ALT_INT_SGI_TARGET_LIST,
+
+    /*!
+     * This filter list sends the interrupt all CPUs except the current CPU.
+     * The target list parameter is ignored.
+     */
+    ALT_INT_SGI_TARGET_ALL_EXCL_SENDER,
+
+    /*!
+     * This filter list sends the interrupt to the current CPU only. The
+     * target list parameter is ignored.
+     */
+    ALT_INT_SGI_TARGET_SENDER_ONLY
+}
+ALT_INT_SGI_TARGET_t;
+
+/*!
+ * Extracts the CPUID field from the ICCIAR register.
+ */
+#define ALT_INT_ICCIAR_CPUID_GET(icciar)    ((icciar >> 10) & 0x7)
+
+/*!
+ * Extracts the ACKINTID field from the ICCIAR register.
+ */
+#define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF)
+
+/*!
+ * The callback to use when an interrupt needs to be serviced.
+ *
+ * \param       icciar          The Interrupt Controller CPU Interrupt
+ *                              Acknowledgement Register value (ICCIAR) value
+ *                              corresponding to the current interrupt.
+ *
+ * \param       context         The user provided context.
+ */
+typedef void (*alt_int_callback_t)(uint32_t icciar, void * context);
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_INT_COMMON_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_mpu_registers.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_mpu_registers.h
new file mode 100644
index 0000000..2ead15d
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_mpu_registers.h
@@ -0,0 +1,156 @@
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_MPUSCU_H__
+#define __ALT_MPUSCU_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+
+/************************************************************************************************************/
+/*                                alt_mpuscu.h                                                                 */
+/*                                                                                                            */
+/*  Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog         */
+/*  Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor.    */
+/*                                                                                                            */
+/************************************************************************************************************/
+
+#ifndef ALT_HPS_ADDR
+#define ALT_HPS_ADDR 0x00
+#endif
+
+
+/*     ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h            */
+/*    and is the address of the base of the Snoop Control Unit (SCU)                                */
+#define GLOBALTMR_BASE                      (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET)
+#define CPU_WDTGPT_TMR_BASE                 (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET)
+#define CPU_PRIVATE_TMR_BASE                (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET)
+#define CPU_INT_CTRL_BASE                   (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET)
+#define CPU_INT_DIST_BASE                   (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET)
+
+
+            /* offsets */
+        /* Global Timer offsets */
+#define GLOBALTMR_MODULE_BASE_OFFSET        0x00000200
+#define GLOBALTMR_CNTR_LO_REG_OFFSET        0x00000000
+#define GLOBALTMR_CNTR_HI_REG_OFFSET        0x00000004
+#define GLOBALTMR_CTRL_REG_OFFSET           0x00000008
+#define GLOBALTMR_INT_STAT_REG_OFFSET       0x0000000C
+#define GLOBALTMR_COMP_LO_REG_OFFSET        0x00000010
+#define GLOBALTMR_COMP_HI_REG_OFFSET        0x00000014
+#define GLOBALTMR_AUTOINC_REG_OFFSET        0x00000018
+
+/* Global Timer bitmasks */
+#define GLOBALTMR_ENABLE_BIT                0x00000001
+#define GLOBALTMR_COMP_ENABLE_BIT           0x00000002
+#define GLOBALTMR_INT_ENABLE_BIT            0x00000004
+#define GLOBALTMR_AUTOINC_ENABLE_BIT        0x00000008
+#define GLOBALTMR_PS_MASK                   0x0000FF00
+#define GLOBALTMR_PS_SHIFT                  8
+#define GLOBALTMR_INT_STATUS_BIT            0x00000001
+
+/* Global timer constants */
+#define GLOBALTMR_MAX                       0xFFFFFFFF
+#define GLOBALTMR_PS_MAX                    0x000000FF
+
+
+/* Private timer offsets */
+#define CPU_PRIV_TIMER_MODULE_BASE_OFFSET   0x00000600
+#define CPU_PRIV_TMR_LOAD_REG_OFFSET        0x00000000
+#define CPU_PRIV_TMR_CNTR_REG_OFFSET        0x00000004
+#define CPU_PRIV_TMR_CTRL_REG_OFFSET        0x00000008
+#define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET  0x0000000C
+
+/* Private timer bitmasks */
+#define CPU_PRIV_TMR_ENABLE                 0x00000001
+#define CPU_PRIV_TMR_AUTO_RELOAD            0x00000002
+#define CPU_PRIV_TMR_INT_EN                 0x00000004
+#define CPU_PRIV_TMR_PS_MASK                0x0000FF00
+#define CPU_PRIV_TMR_PS_SHIFT               8
+#define CPU_PRIV_TMR_INT_STATUS             0x00000001
+
+/* Private timer constants */
+#define CPU_PRIV_TMR_MAX                    0xFFFFFFFF
+#define CPU_PRIV_TMR_PS_MAX                 0x000000FF
+
+
+
+    /* Watchdog timer offsets */
+#define WDOG_TIMER_MODULE_BASE_OFFSET       0x00000620
+#define WDOG_LOAD_REG_OFFSET                0x00000000
+#define WDOG_CNTR_REG_OFFSET                0x00000004
+#define WDOG_CTRL_REG_OFFSET                0x00000008
+#define WDOG_INTSTAT_REG_OFFSET             0x0000000C
+#define WDOG_RSTSTAT_REG_OFFSET             0x00000010
+#define WDOG_DISABLE_REG_OFFSET             0x00000014
+
+    /* Watchdog timer bitmasks : */
+    /* Control Register bitmasks */
+#define WDOG_TMR_ENABLE                     0x00000001
+#define WDOG_AUTO_RELOAD                    0x00000002
+#define WDOG_INT_EN                         0x00000004
+#define WDOG_WDT_MODE                       0x00000008
+#define WDOG_PS_MASK                        0x0000FF00
+#define WDOG_PS_SHIFT                       8
+    /* Interrupt Status Register bitmasks */
+#define WDOG_INT_STAT_BIT                   0x00000001
+    /* Reset Status Register bitmasks */
+#define WDOG_RST_STAT_BIT                   0x00000001
+
+    /* Watchdog timer constants */
+#define WDOG_TMR_MAX                        UINT32_MAX
+#define WDOG_PS_MAX                         UINT8_MAX
+#define WDOG_DISABLE_VAL0                   0x12345678
+#define WDOG_DISABLE_VAL1                   0x87654321
+
+
+
+    /* Interrupt Manager offsets */
+/*   <Add definitions here> */
+#define INT_CONTROLLER_MODULE_BASE_OFFSET   0x00000100
+#define INT_DISTRIBUTOR_MODULE_BASE_OFFSET  0x00001000
+#define INT_DIST_TYPE_REG                   0x00000004
+
+
+/*  Upper bound of the MPUSCU address space  */
+#define MPUSCU_MAX                          0x00001FFF
+
+
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* __ALT_MPUSCU_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h
new file mode 100644
index 0000000..7b0da34
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h
@@ -0,0 +1,249 @@
+/*! \file
+ *  Altera - SoC Reset Manager
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_RESET_MGR_H__
+#define __ALT_RESET_MGR_H__
+
+#include "hwlib.h"
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*! \addtogroup RST_MGR The Reset Manager
+ *
+ * The Reset Manager API defines functions for accessing, configuring, and
+ * controlling the HPS reset behavior.
+ * @{
+ */
+
+/******************************************************************************/
+/*! \addtogroup RST_MGR_STATUS Reset Status
+ *
+ * This functional group provides information on various aspects of SoC reset
+ * status and timeout events.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the set of reset causes and timeout events as
+ * register mask values.
+ */
+typedef enum ALT_RESET_EVENT_e
+{
+    /*! Power-On Voltage Detector Cold Reset */
+    ALT_RESET_EVENT_PORVOLTRST          = 0x00000001,
+
+    /*! nPOR Pin Cold Reset                  */
+    ALT_RESET_EVENT_NPORPINRST          = 0x00000002,
+
+    /*! FPGA Core Cold Reset                 */
+    ALT_RESET_EVENT_FPGACOLDRST         = 0x00000004,
+
+    /*! CONFIG_IO Cold Reset                 */
+    ALT_RESET_EVENT_CONFIGIOCOLDRST     = 0x00000008,
+
+    /*! Software Cold Reset                  */
+    ALT_RESET_EVENT_SWCOLDRST           = 0x00000010,
+
+    /*! nRST Pin Warm Reset                  */
+    ALT_RESET_EVENT_NRSTPINRST          = 0x00000100,
+
+    /*! FPGA Core Warm Reset                 */
+    ALT_RESET_EVENT_FPGAWARMRST         = 0x00000200,
+
+    /*! Software Warm Reset                  */
+    ALT_RESET_EVENT_SWWARMRST           = 0x00000400,
+
+    /*! MPU Watchdog 0 Warm Reset            */
+    ALT_RESET_EVENT_MPUWD0RST           = 0x00001000,
+
+    /*! MPU Watchdog 1 Warm Reset            */
+    ALT_RESET_EVENT_MPUWD1RST           = 0x00002000,
+
+    /*! L4 Watchdog 0 Warm Reset             */
+    ALT_RESET_EVENT_L4WD0RST            = 0x00004000,
+
+    /*! L4 Watchdog 1 Warm Reset             */
+    ALT_RESET_EVENT_L4WD1RST            = 0x00008000,
+
+    /*! FPGA Core Debug Reset                */
+    ALT_RESET_EVENT_FPGADBGRST          = 0x00040000,
+
+    /*! DAP Debug Reset                      */
+    ALT_RESET_EVENT_CDBGREQRST          = 0x00080000,
+
+    /*! SDRAM Self-Refresh Timeout           */
+    ALT_RESET_EVENT_SDRSELFREFTIMEOUT   = 0x01000000,
+
+    /*! FPGA manager handshake Timeout       */
+    ALT_RESET_EVENT_FPGAMGRHSTIMEOUT    = 0x02000000,
+
+    /*! SCAN manager handshake Timeout       */
+    ALT_RESET_EVENT_SCANHSTIMEOUT       = 0x04000000,
+
+    /*! FPGA handshake Timeout               */
+    ALT_RESET_EVENT_FPGAHSTIMEOUT       = 0x08000000,
+
+    /*! ETR Stall Timeout                    */
+    ALT_RESET_EVENT_ETRSTALLTIMEOUT     = 0x10000000
+} ALT_RESET_EVENT_t;
+
+/******************************************************************************/
+/*!
+ * Gets the reset and timeout events that caused the last reset.
+ *
+ * The ALT_RESET_EVENT_t enumeration values should be used to selectively
+ * examine the returned reset cause(s).
+ *
+ * \returns     A mask of the reset and/or timeout events that caused the last
+ *              reset.
+ */
+uint32_t alt_reset_event_get(void);
+
+/******************************************************************************/
+/*!
+ * Clears the reset and timeout events that caused the last reset.
+ *
+ * \param       event_mask
+ *              A mask of the selected reset and timeout events to clear in the
+ *              Reset Manager \e stat register. The mask selection can be formed
+ *              using the ALT_RESET_EVENT_t enumeration values.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup RST_MGR_CTRL Reset Control
+ *
+ * This functional group provides global and selective reset control for the SoC
+ * and its constituent modules.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Initiate a cold reset of the SoC.
+ *
+ * If this function is successful, then it should never return.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_reset_cold_reset(void);
+
+/******************************************************************************/
+/*!
+ * Initiate a warm reset of the SoC.
+ *
+ * Perform a hardware sequenced warm reset of the SoC. A hardware sequenced
+ * reset handshake with certain modules can optionally be requested in an
+ * attempt to ensure an orderly reset transition.
+ *
+ * \param       warm_reset_delay
+ *              Specifies the number of cycles after the Reset Manager releases
+ *              the Clock Manager reset before releasing any other hardware
+ *              controlled resets. Value must be greater than 16 and less than
+ *              256.
+ *
+ * \param       nRST_pin_clk_assertion
+ *              Specifies that number of clock cycles (osc1_clk?) to externally
+ *              assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <=
+ *              (2**20 - 1). A value of 0 prevents any assertion of nRST.
+ *
+ * \param       sdram_refresh
+ *              Controls whether the contents of SDRAM survive a hardware
+ *              sequenced warm reset. The reset manager requests the SDRAM
+ *              controller to put SDRAM devices into self-refresh mode before
+ *              asserting warm reset signals. An argument value of \b true
+ *              enables the option, \b false disables the option.
+ *
+ * \param       fpga_mgr_handshake
+ *              Controls whether a handshake between the reset manager and FPGA
+ *              manager occurs before a warm reset. The handshake is used to
+ *              warn the FPGA manager that a warm reset is imminent so it can
+ *              prepare for it by driving its output clock to a quiescent state
+ *              to avoid glitches. An argument value of \b true enables the
+ *              option, \b false disables the option.
+ *
+ * \param       scan_mgr_handshake
+ *              Controls whether a handshake between the reset manager and scan
+ *              manager occurs before a warm reset. The handshake is used to
+ *              warn the scan manager that a warm reset is imminent so it can
+ *              prepare for it by driving its output clock to a quiescent state
+ *              to avoid glitches. An argument value of \b true enables the
+ *              option, \b false disables the option.
+ *
+ * \param       fpga_handshake
+ *              Controls whether a handshake between the reset manager and the
+ *              FPGA occurs before a warm reset. The handshake is used to warn
+ *              the FPGA that a warm reset is imminent so that the FPGA prepare
+ *              for the reset event in soft IP. An argument value of \b true
+ *              enables the option, \b false disables the option.
+ *
+ * \param       etr_stall
+ *              Controls whether the ETR is requested to idle its AXI master
+ *              interface (i.e. finish outstanding transactions and not initiate
+ *              any more) to the L3 Interconnect before a warm reset. An
+ *              argument value of \b true enables the option, \b false disables
+ *              the option.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
+                                     uint32_t nRST_pin_clk_assertion,
+                                     bool sdram_refresh,
+                                     bool fpga_mgr_handshake,
+                                     bool scan_mgr_handshake,
+                                     bool fpga_handshake,
+                                     bool etr_stall);
+
+/*! @} */
+
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_RESET_MGR_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h
new file mode 100644
index 0000000..7a3bbfd
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h
@@ -0,0 +1,190 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __HWLIB_H__
+#define __HWLIB_H__
+
+#ifdef __cplusplus
+#include <cstddef>
+#include <cstdbool>
+#include <cstdint>
+#else   /* __cplusplus */
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+#endif  /* __cplusplus */
+
+#include "alt_hwlibs_ver.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*!
+ * The type definition for status codes returned by the HWLIB.
+ */
+typedef int32_t             ALT_STATUS_CODE;
+
+/*! Definitions of status codes returned by the HWLIB. */
+
+/*! The operation was successful. */
+#define ALT_E_SUCCESS               0
+
+/*! The operation failed. */
+#define ALT_E_ERROR                 (-1)
+/*! FPGA configuration error detected.*/
+#define ALT_E_FPGA_CFG              (-2)
+/*! FPGA CRC error detected. */
+#define ALT_E_FPGA_CRC              (-3)
+/*! An error occurred on the FPGA configuration bitstream input source. */
+#define ALT_E_FPGA_CFG_STM          (-4)
+/*! The FPGA is powered off. */
+#define ALT_E_FPGA_PWR_OFF          (-5)
+/*! The SoC does not currently control the FPGA. */
+#define ALT_E_FPGA_NO_SOC_CTRL      (-6)
+/*! The FPGA is not in USER mode. */
+#define ALT_E_FPGA_NOT_USER_MODE    (-7)
+/*! An argument violates a range constraint. */
+#define ALT_E_ARG_RANGE             (-8)
+/*! A bad argument value was passed. */
+#define ALT_E_BAD_ARG               (-9)
+/*! The operation is invalid or illegal. */
+#define ALT_E_BAD_OPERATION         (-10)
+/*! An invalid option was selected. */
+#define ALT_E_INV_OPTION            (-11)
+/*! An operation or response timeout period expired. */
+#define ALT_E_TMO                   (-12)
+/*! The argument value is reserved or unavailable. */
+#define ALT_E_RESERVED              (-13)
+/*! A clock is not enabled or violates an operational constraint. */
+#define ALT_E_BAD_CLK               (-14)
+/*! The version ID is invalid. */
+#define ALT_E_BAD_VERSION           (-15)
+/*! The buffer does not contain enough free space for the operation. */
+#define ALT_E_BUF_OVF               (-20)
+
+
+/*!
+ * Indicates a FALSE condition.
+ */
+#define ALT_E_FALSE                 (0)
+/*!
+ * Indicates a TRUE condition.
+ */
+#define ALT_E_TRUE                  (1)
+
+/* Note, additional positive status codes may be defined to return
+ * a TRUE condition with additional information */
+
+
+/* Some other useful definitions */
+
+/*!
+ * Specifies the current major and minor revision of the HWLibs. The
+ * MS four decimal digits specify the Altera ACDS release number, the
+ * LS two decimal digits specify minor revisions of the HWLibs, if any.
+ *
+ * A typical use is:
+ * \code
+ * #if  ALTERA_HWLIBS_VERSION_CODE >= ALT_HWLIBS_VERSION(13, 1, 0)
+ * \endcode
+ *     for a dependency on the major or minor ACDS revision
+ *   or
+ * \code
+ * #if  ALTERA_HWLIBS_VERSION_CODE == ALT_HWLIBS_VERSION(13, 0, 12)
+ * \endcode
+ *     for a dependency on the hwlibs revision
+ *
+ */
+#define ALT_HWLIBS_VERSION(a,b,c)   (((a)*10000)+((b)*100)+(c))
+
+#define ALTERA_HWLIBS_VERSION_CODE   ALT_HWLIBS_VERSION(ALTERA_ACDS_MAJOR_REV, \
+                                    ALTERA_ACDS_MINOR_REV, ALTERA_HWLIBS_REV)
+
+/*!
+ * Allow some parts of the documentation to be hidden by setting to zero
+ */
+#define ALTERA_INTERNAL_ONLY_DOCS   1
+
+
+/*!
+ * Provide base address of MPU address space
+ */
+
+#ifndef ALT_HPS_ADDR
+#define ALT_HPS_ADDR            0
+#endif
+
+/*!
+ * These constants are sometimes useful:
+ */
+#define ALT_MILLISECS_IN_A_SEC      1000
+#define ALT_MICROSECS_IN_A_SEC      1000000
+#define ALT_NANOSECS_IN_A_SEC       1000000000
+
+#define ALT_TWO_TO_POW0             (1)
+#define ALT_TWO_TO_POW1             (1<<1)
+#define ALT_TWO_TO_POW2             (1<<2)
+#define ALT_TWO_TO_POW3             (1<<3)
+#define ALT_TWO_TO_POW4             (1<<4)
+#define ALT_TWO_TO_POW5             (1<<5)
+#define ALT_TWO_TO_POW6             (1<<6)
+#define ALT_TWO_TO_POW7             (1<<7)
+#define ALT_TWO_TO_POW8             (1<<8)
+#define ALT_TWO_TO_POW9             (1<<9)
+#define ALT_TWO_TO_POW10            (1<<10)
+#define ALT_TWO_TO_POW11            (1<<11)
+#define ALT_TWO_TO_POW12            (1<<12)
+#define ALT_TWO_TO_POW13            (1<<13)
+#define ALT_TWO_TO_POW14            (1<<14)
+#define ALT_TWO_TO_POW15            (1<<15)
+#define ALT_TWO_TO_POW16            (1<<16)
+#define ALT_TWO_TO_POW17            (1<<17)
+#define ALT_TWO_TO_POW18            (1<<18)
+#define ALT_TWO_TO_POW19            (1<<19)
+#define ALT_TWO_TO_POW20            (1<<20)
+#define ALT_TWO_TO_POW21            (1<<21)
+#define ALT_TWO_TO_POW22            (1<<22)
+#define ALT_TWO_TO_POW23            (1<<23)
+#define ALT_TWO_TO_POW24            (1<<24)
+#define ALT_TWO_TO_POW25            (1<<25)
+#define ALT_TWO_TO_POW26            (1<<26)
+#define ALT_TWO_TO_POW27            (1<<27)
+#define ALT_TWO_TO_POW28            (1<<28)
+#define ALT_TWO_TO_POW29            (1<<29)
+#define ALT_TWO_TO_POW30            (1<<30)
+#define ALT_TWO_TO_POW31            (1<<31)
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __HWLIB_H__ */
+
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_clkmgr.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_clkmgr.h
new file mode 100644
index 0000000..1875a84
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_clkmgr.h
@@ -0,0 +1,6464 @@
+/*******************************************************************************
+*                                                                              *
+* Copyright 2013 Altera Corporation. All Rights Reserved.                      *
+*                                                                              *
+* Redistribution and use in source and binary forms, with or without           *
+* modification, are permitted provided that the following conditions are met:  *
+*                                                                              *
+* 1. Redistributions of source code must retain the above copyright notice,    *
+*    this list of conditions and the following disclaimer.                     *
+*                                                                              *
+* 2. Redistributions in binary form must reproduce the above copyright notice, *
+*    this list of conditions and the following disclaimer in the documentation *
+*    and/or other materials provided with the distribution.                    *
+*                                                                              *
+* 3. The name of the author may not be used to endorse or promote products     *
+*    derived from this software without specific prior written permission.     *
+*                                                                              *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO  *
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,       *
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;  *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,     *
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR      *
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF       *
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                   *
+*                                                                              *
+*******************************************************************************/
+
+/* Altera - ALT_CLKMGR */
+
+#ifndef __ALTERA_ALT_CLKMGR_H__
+#define __ALTERA_ALT_CLKMGR_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*
+ * Component : Clock Manager Module - ALT_CLKMGR
+ * Clock Manager Module
+ * 
+ * Registers in the Clock Manager module
+ * 
+ */
+/*
+ * Register : Control Register - ctrl
+ * 
+ * Contains fields that control the entire Clock Manager.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                  
+ * :-------|:-------|:------|:------------------------------
+ *  [0]    | RW     | 0x1   | Safe Mode                    
+ *  [1]    | ???    | 0x0   | *UNDEFINED*                  
+ *  [2]    | RW     | 0x1   | Enable SafeMode on Warm Reset
+ *  [31:3] | ???    | 0x0   | *UNDEFINED*                  
+ * 
+ */
+/*
+ * Field : Safe Mode - safemode
+ * 
+ * When set the Clock Manager is in Safe Mode.
+ * 
+ * In Safe Mode Clock Manager register settings defining clock behavior are ignored
+ * and clocks are set to a Safe Mode state.In Safe Mode all clocks with the
+ * optional exception of debug clocks, are directly generated from the EOSC1 clock
+ * input, all PLLs are bypassed, all programmable dividers are set to 1 and all
+ * clocks are enabled.
+ * 
+ * This bit should only be cleared when clocks have been correctly configured
+ * 
+ * This field is set on a cold reset and optionally on a warm reset and may not be
+ * set by SW.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */
+#define ALT_CLKMGR_CTL_SAFEMOD_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */
+#define ALT_CLKMGR_CTL_SAFEMOD_MSB        0
+/* The width in bits of the ALT_CLKMGR_CTL_SAFEMOD register field. */
+#define ALT_CLKMGR_CTL_SAFEMOD_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_CTL_SAFEMOD register field value. */
+#define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_CTL_SAFEMOD register field value. */
+#define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_CTL_SAFEMOD register field. */
+#define ALT_CLKMGR_CTL_SAFEMOD_RESET      0x1
+/* Extracts the ALT_CLKMGR_CTL_SAFEMOD field value from a register. */
+#define ALT_CLKMGR_CTL_SAFEMOD_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_CTL_SAFEMOD register field value suitable for setting the register. */
+#define ALT_CLKMGR_CTL_SAFEMOD_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Enable SafeMode on Warm Reset - ensfmdwr
+ * 
+ * When set the Clock Manager will respond to a Safe Mode request from the Reset
+ * Manager on a warm reset by setting the Safe Mode bit. When clear the clock
+ * manager will not set the the Safe Mode bit on a warm reset This bit is cleared
+ * on a cold reset. Warm reset has no affect on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
+#define ALT_CLKMGR_CTL_ENSFMDWR_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
+#define ALT_CLKMGR_CTL_ENSFMDWR_MSB        2
+/* The width in bits of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
+#define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_CTL_ENSFMDWR register field value. */
+#define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CLKMGR_CTL_ENSFMDWR register field value. */
+#define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
+#define ALT_CLKMGR_CTL_ENSFMDWR_RESET      0x1
+/* Extracts the ALT_CLKMGR_CTL_ENSFMDWR field value from a register. */
+#define ALT_CLKMGR_CTL_ENSFMDWR_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CLKMGR_CTL_ENSFMDWR register field value suitable for setting the register. */
+#define ALT_CLKMGR_CTL_ENSFMDWR_SET(value) (((value) << 2) & 0x00000004)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_CTL.
+ */
+struct ALT_CLKMGR_CTL_s
+{
+    uint32_t  safemode :  1;  /* Safe Mode */
+    uint32_t           :  1;  /* *UNDEFINED* */
+    uint32_t  ensfmdwr :  1;  /* Enable SafeMode on Warm Reset */
+    uint32_t           : 29;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_CTL. */
+typedef volatile struct ALT_CLKMGR_CTL_s  ALT_CLKMGR_CTL_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_CTL register from the beginning of the component. */
+#define ALT_CLKMGR_CTL_OFST        0x0
+
+/*
+ * Register : PLL Bypass Register - bypass
+ * 
+ * Contains fields that control bypassing each PLL.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                 
+ * :-------|:-------|:------|:-----------------------------
+ *  [0]    | RW     | 0x1   | Main PLL Bypass             
+ *  [1]    | RW     | 0x1   | SDRAM PLL Bypass            
+ *  [2]    | RW     | 0x0   | SDRAM PLL Bypass Source     
+ *  [3]    | RW     | 0x1   | Peripheral PLL Bypass       
+ *  [4]    | RW     | 0x0   | Peripheral PLL Bypass Source
+ *  [31:5] | ???    | 0x0   | *UNDEFINED*                 
+ * 
+ */
+/*
+ * Field : Main PLL Bypass - mainpll
+ * 
+ * When set, causes the Main PLL VCO and counters to be bypassed so that all clocks
+ * generated by the Main PLL are directly driven from the Main PLL input clock. The
+ * bypass source for Main PLL is the external eosc1_clk.
+ * 
+ * The reset value for this bit is applied on a cold reset.   Warm reset has no
+ * affect on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
+#define ALT_CLKMGR_BYPASS_MAINPLL_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
+#define ALT_CLKMGR_BYPASS_MAINPLL_MSB        0
+/* The width in bits of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
+#define ALT_CLKMGR_BYPASS_MAINPLL_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_BYPASS_MAINPLL register field value. */
+#define ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_BYPASS_MAINPLL register field value. */
+#define ALT_CLKMGR_BYPASS_MAINPLL_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
+#define ALT_CLKMGR_BYPASS_MAINPLL_RESET      0x1
+/* Extracts the ALT_CLKMGR_BYPASS_MAINPLL field value from a register. */
+#define ALT_CLKMGR_BYPASS_MAINPLL_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_BYPASS_MAINPLL register field value suitable for setting the register. */
+#define ALT_CLKMGR_BYPASS_MAINPLL_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : SDRAM PLL Bypass - sdrpll
+ * 
+ * When set, causes the SDRAM PLL VCO and counters to be bypassed so that all
+ * clocks generated by the SDRAM PLL are directly driven from either eosc1_clk or
+ * the SDRAM PLL input clock.
+ * 
+ * The bypass clock source for SDRAM PLL is determined by the SDRAM PLL Bypass
+ * Source Register bit.
+ * 
+ * The reset value for this bit is applied on a cold reset.   Warm reset has no
+ * affect on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
+#define ALT_CLKMGR_BYPASS_SDRPLL_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
+#define ALT_CLKMGR_BYPASS_SDRPLL_MSB        1
+/* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
+#define ALT_CLKMGR_BYPASS_SDRPLL_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLL register field value. */
+#define ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLL register field value. */
+#define ALT_CLKMGR_BYPASS_SDRPLL_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
+#define ALT_CLKMGR_BYPASS_SDRPLL_RESET      0x1
+/* Extracts the ALT_CLKMGR_BYPASS_SDRPLL field value from a register. */
+#define ALT_CLKMGR_BYPASS_SDRPLL_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CLKMGR_BYPASS_SDRPLL register field value suitable for setting the register. */
+#define ALT_CLKMGR_BYPASS_SDRPLL_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : SDRAM PLL Bypass Source - sdrpllsrc
+ * 
+ * This bit defines the bypass source forSDRAM PLL.
+ * 
+ * When changing fields that affect VCO lock the PLL must be bypassed and this bit
+ * must be set to OSC1_CLK.
+ * 
+ * The reset value for this bit is applied on a cold reset.   Warm reset has no
+ * affect on this bit.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                           | Value | Description         
+ * :-----------------------------------------------|:------|:---------------------
+ *  ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1     | 0x0   | Select EOSC1        
+ *  ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX | 0x1   | Select PLL Input Mux
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC
+ * 
+ * Select EOSC1
+ */
+#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1      0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC
+ * 
+ * Select PLL Input Mux
+ */
+#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
+#define ALT_CLKMGR_BYPASS_SDRPLLSRC_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
+#define ALT_CLKMGR_BYPASS_SDRPLLSRC_MSB        2
+/* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
+#define ALT_CLKMGR_BYPASS_SDRPLLSRC_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */
+#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */
+#define ALT_CLKMGR_BYPASS_SDRPLLSRC_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
+#define ALT_CLKMGR_BYPASS_SDRPLLSRC_RESET      0x0
+/* Extracts the ALT_CLKMGR_BYPASS_SDRPLLSRC field value from a register. */
+#define ALT_CLKMGR_BYPASS_SDRPLLSRC_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CLKMGR_BYPASS_SDRPLLSRC register field value suitable for setting the register. */
+#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : Peripheral PLL Bypass - perpll
+ * 
+ * When set, causes the Peripheral PLL VCO and counters to be bypassed so that all
+ * clocks generated by the Peripheral PLL are directly driven from either eosc1_clk
+ * or the Peripheral PLL input clock.
+ * 
+ * The bypass clock source for Peripheral PLL is determined by the Peripheral PLL
+ * Bypass Source Register bit.
+ * 
+ * The reset value for this bit is applied on a cold reset.   Warm reset has no
+ * affect on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */
+#define ALT_CLKMGR_BYPASS_PERPLL_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */
+#define ALT_CLKMGR_BYPASS_PERPLL_MSB        3
+/* The width in bits of the ALT_CLKMGR_BYPASS_PERPLL register field. */
+#define ALT_CLKMGR_BYPASS_PERPLL_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_BYPASS_PERPLL register field value. */
+#define ALT_CLKMGR_BYPASS_PERPLL_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLL register field value. */
+#define ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CLKMGR_BYPASS_PERPLL register field. */
+#define ALT_CLKMGR_BYPASS_PERPLL_RESET      0x1
+/* Extracts the ALT_CLKMGR_BYPASS_PERPLL field value from a register. */
+#define ALT_CLKMGR_BYPASS_PERPLL_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CLKMGR_BYPASS_PERPLL register field value suitable for setting the register. */
+#define ALT_CLKMGR_BYPASS_PERPLL_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : Peripheral PLL Bypass Source - perpllsrc
+ * 
+ * This bit defines the bypass source forPeripheral PLL.
+ * 
+ * When changing fields that affect VCO lock the PLL must be bypassed and this bit
+ * must be set to OSC1_CLK.
+ * 
+ * The reset value for this bit is applied on a cold reset.   Warm reset has no
+ * affect on this bit.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                           | Value | Description         
+ * :-----------------------------------------------|:------|:---------------------
+ *  ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1     | 0x0   | Select EOSC1        
+ *  ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX | 0x1   | Select PLL Input Mux
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC
+ * 
+ * Select EOSC1
+ */
+#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1      0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC
+ * 
+ * Select PLL Input Mux
+ */
+#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
+#define ALT_CLKMGR_BYPASS_PERPLLSRC_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
+#define ALT_CLKMGR_BYPASS_PERPLLSRC_MSB        4
+/* The width in bits of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
+#define ALT_CLKMGR_BYPASS_PERPLLSRC_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */
+#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK    0x00000010
+/* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */
+#define ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK    0xffffffef
+/* The reset value of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
+#define ALT_CLKMGR_BYPASS_PERPLLSRC_RESET      0x0
+/* Extracts the ALT_CLKMGR_BYPASS_PERPLLSRC field value from a register. */
+#define ALT_CLKMGR_BYPASS_PERPLLSRC_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_CLKMGR_BYPASS_PERPLLSRC register field value suitable for setting the register. */
+#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET(value) (((value) << 4) & 0x00000010)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_BYPASS.
+ */
+struct ALT_CLKMGR_BYPASS_s
+{
+    uint32_t  mainpll   :  1;  /* Main PLL Bypass */
+    uint32_t  sdrpll    :  1;  /* SDRAM PLL Bypass */
+    uint32_t  sdrpllsrc :  1;  /* SDRAM PLL Bypass Source */
+    uint32_t  perpll    :  1;  /* Peripheral PLL Bypass */
+    uint32_t  perpllsrc :  1;  /* Peripheral PLL Bypass Source */
+    uint32_t            : 27;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_BYPASS. */
+typedef volatile struct ALT_CLKMGR_BYPASS_s  ALT_CLKMGR_BYPASS_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_BYPASS register from the beginning of the component. */
+#define ALT_CLKMGR_BYPASS_OFST        0x4
+
+/*
+ * Register : Interrupt Status Register - inter
+ * 
+ * Contains fields that indicate the PLL lock status.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset   | Description                       
+ * :-------|:-------|:--------|:-----------------------------------
+ *  [0]    | RW     | 0x0     | Main PLL Achieved Lock            
+ *  [1]    | RW     | 0x0     | Peripheral PLL Achieved Lock      
+ *  [2]    | RW     | 0x0     | SDRAM PLL Achieved Lock           
+ *  [3]    | RW     | 0x0     | Main PLL Lost Lock                
+ *  [4]    | RW     | 0x0     | Peripheral PLL Lost Lock          
+ *  [5]    | RW     | 0x0     | SDRAM PLL Lost Lock               
+ *  [6]    | R      | Unknown | Main PLL Current Lock Status      
+ *  [7]    | R      | Unknown | Peripheral PLL Current Lock Status
+ *  [8]    | R      | Unknown | SDRAM PLL Current Lock Status     
+ *  [31:9] | ???    | 0x0     | *UNDEFINED*                       
+ * 
+ */
+/*
+ * Field : Main PLL Achieved Lock - mainpllachieved
+ * 
+ * If 1, the Main PLL has achieved lock at least once since this bit was cleared.
+ * If 0, the Main PLL has not achieved lock since this bit was cleared.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_MSB        0
+/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTER_MAINPLLACHIEVED field value from a register. */
+#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Peripheral PLL Achieved Lock - perpllachieved
+ * 
+ * If 1, the Peripheral PLL has achieved lock at least once since this bit was
+ * cleared. If 0, the Peripheral PLL has not achieved lock since this bit was
+ * cleared.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_PERPLLACHIEVED_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_PERPLLACHIEVED_MSB        1
+/* The width in bits of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_PERPLLACHIEVED_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_PERPLLACHIEVED_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTER_PERPLLACHIEVED field value from a register. */
+#define ALT_CLKMGR_INTER_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CLKMGR_INTER_PERPLLACHIEVED register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : SDRAM PLL Achieved Lock - sdrpllachieved
+ * 
+ * If 1, the SDRAM PLL has achieved lock at least once since this bit was cleared.
+ * If 0, the SDRAM PLL has not achieved lock since this bit was cleared.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_MSB        2
+/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTER_SDRPLLACHIEVED field value from a register. */
+#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : Main PLL Lost Lock - mainplllost
+ * 
+ * If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0,
+ * the Main PLL has not lost lock since this bit was cleared.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
+#define ALT_CLKMGR_INTER_MAINPLLLOST_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
+#define ALT_CLKMGR_INTER_MAINPLLLOST_MSB        3
+/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
+#define ALT_CLKMGR_INTER_MAINPLLLOST_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */
+#define ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */
+#define ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
+#define ALT_CLKMGR_INTER_MAINPLLLOST_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTER_MAINPLLLOST field value from a register. */
+#define ALT_CLKMGR_INTER_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CLKMGR_INTER_MAINPLLLOST register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTER_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : Peripheral PLL Lost Lock - perplllost
+ * 
+ * If 1, the Peripheral PLL has lost lock at least once since this bit was cleared.
+ * If 0, the Peripheral PLL has not lost lock since this bit was cleared.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
+#define ALT_CLKMGR_INTER_PERPLLLOST_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
+#define ALT_CLKMGR_INTER_PERPLLLOST_MSB        4
+/* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
+#define ALT_CLKMGR_INTER_PERPLLLOST_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOST register field value. */
+#define ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK    0x00000010
+/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOST register field value. */
+#define ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK    0xffffffef
+/* The reset value of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
+#define ALT_CLKMGR_INTER_PERPLLLOST_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTER_PERPLLLOST field value from a register. */
+#define ALT_CLKMGR_INTER_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_CLKMGR_INTER_PERPLLLOST register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTER_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : SDRAM PLL Lost Lock - sdrplllost
+ * 
+ * If 1, the SDRAM PLL has lost lock at least once since this bit was cleared. If
+ * 0, the SDRAM PLL has not lost lock since this bit was cleared.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
+#define ALT_CLKMGR_INTER_SDRPLLLOST_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
+#define ALT_CLKMGR_INTER_SDRPLLLOST_MSB        5
+/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
+#define ALT_CLKMGR_INTER_SDRPLLLOST_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */
+#define ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK    0x00000020
+/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */
+#define ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
+#define ALT_CLKMGR_INTER_SDRPLLLOST_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTER_SDRPLLLOST field value from a register. */
+#define ALT_CLKMGR_INTER_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_CLKMGR_INTER_SDRPLLLOST register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTER_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : Main PLL Current Lock Status - mainplllocked
+ * 
+ * If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not
+ * locked.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */
+#define ALT_CLKMGR_INTER_MAINPLLLOCKED_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */
+#define ALT_CLKMGR_INTER_MAINPLLLOCKED_MSB        6
+/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */
+#define ALT_CLKMGR_INTER_MAINPLLLOCKED_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */
+#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK    0x00000040
+/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */
+#define ALT_CLKMGR_INTER_MAINPLLLOCKED_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field is UNKNOWN. */
+#define ALT_CLKMGR_INTER_MAINPLLLOCKED_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTER_MAINPLLLOCKED field value from a register. */
+#define ALT_CLKMGR_INTER_MAINPLLLOCKED_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_CLKMGR_INTER_MAINPLLLOCKED register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : Peripheral PLL Current Lock Status - perplllocked
+ * 
+ * If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is
+ * currently not locked.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */
+#define ALT_CLKMGR_INTER_PERPLLLOCKED_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */
+#define ALT_CLKMGR_INTER_PERPLLLOCKED_MSB        7
+/* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */
+#define ALT_CLKMGR_INTER_PERPLLLOCKED_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */
+#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK    0x00000080
+/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */
+#define ALT_CLKMGR_INTER_PERPLLLOCKED_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_CLKMGR_INTER_PERPLLLOCKED register field is UNKNOWN. */
+#define ALT_CLKMGR_INTER_PERPLLLOCKED_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTER_PERPLLLOCKED field value from a register. */
+#define ALT_CLKMGR_INTER_PERPLLLOCKED_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_CLKMGR_INTER_PERPLLLOCKED register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : SDRAM PLL Current Lock Status - sdrplllocked
+ * 
+ * If 1, the SDRAM PLL is currently locked. If 0, the SDRAM PLL is currently not
+ * locked.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */
+#define ALT_CLKMGR_INTER_SDRPLLLOCKED_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */
+#define ALT_CLKMGR_INTER_SDRPLLLOCKED_MSB        8
+/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */
+#define ALT_CLKMGR_INTER_SDRPLLLOCKED_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */
+#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK    0x00000100
+/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */
+#define ALT_CLKMGR_INTER_SDRPLLLOCKED_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field is UNKNOWN. */
+#define ALT_CLKMGR_INTER_SDRPLLLOCKED_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTER_SDRPLLLOCKED field value from a register. */
+#define ALT_CLKMGR_INTER_SDRPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_CLKMGR_INTER_SDRPLLLOCKED register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET(value) (((value) << 8) & 0x00000100)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_INTER.
+ */
+struct ALT_CLKMGR_INTER_s
+{
+    uint32_t        mainpllachieved :  1;  /* Main PLL Achieved Lock */
+    uint32_t        perpllachieved  :  1;  /* Peripheral PLL Achieved Lock */
+    uint32_t        sdrpllachieved  :  1;  /* SDRAM PLL Achieved Lock */
+    uint32_t        mainplllost     :  1;  /* Main PLL Lost Lock */
+    uint32_t        perplllost      :  1;  /* Peripheral PLL Lost Lock */
+    uint32_t        sdrplllost      :  1;  /* SDRAM PLL Lost Lock */
+    const uint32_t  mainplllocked   :  1;  /* Main PLL Current Lock Status */
+    const uint32_t  perplllocked    :  1;  /* Peripheral PLL Current Lock Status */
+    const uint32_t  sdrplllocked    :  1;  /* SDRAM PLL Current Lock Status */
+    uint32_t                        : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_INTER. */
+typedef volatile struct ALT_CLKMGR_INTER_s  ALT_CLKMGR_INTER_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_INTER register from the beginning of the component. */
+#define ALT_CLKMGR_INTER_OFST        0x8
+
+/*
+ * Register : Interrupt Enable Register - intren
+ * 
+ * Contain fields that enable the interrupt.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                                  
+ * :-------|:-------|:------|:----------------------------------------------
+ *  [0]    | RW     | 0x0   | Main PLL Achieved Lock Interrupt Enable      
+ *  [1]    | RW     | 0x0   | Peripheral PLL Achieved Lock Interrupt Enable
+ *  [2]    | RW     | 0x0   | SDRAM PLL Achieved Lock Interrupt Enable     
+ *  [3]    | RW     | 0x0   | Main PLL Achieved Lock Interrupt Enable      
+ *  [4]    | RW     | 0x0   | Peripheral PLL Achieved Lock Interrupt Enable
+ *  [5]    | RW     | 0x0   | SDRAM PLL Achieved Lock Interrupt Enable     
+ *  [31:6] | ???    | 0x0   | *UNDEFINED*                                  
+ * 
+ */
+/*
+ * Field : Main PLL Achieved Lock Interrupt Enable - mainpllachieved
+ * 
+ * When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager
+ * interrupt output.  When set to 0 the Main PLL achieved lock bit is not ORed into
+ * the Clock Manager interrupt output.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_MSB        0
+/* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTREN_MAINPLLACHIEVED field value from a register. */
+#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Peripheral PLL Achieved Lock Interrupt Enable - perpllachieved
+ * 
+ * When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock
+ * Manager interrupt output.  When set to 0 the Peripheral PLL achieved lock bit is
+ * not ORed into the Clock Manager interrupt output.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_MSB        1
+/* The width in bits of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTREN_PERPLLACHIEVED field value from a register. */
+#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrpllachieved
+ * 
+ * When set to 1, the SDRAM PLL achieved lock bit is ORed into the Clock Manager
+ * interrupt output.  When set to 0 the SDRAM PLL achieved lock bit is not ORed
+ * into the Clock Manager interrupt output.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_MSB        2
+/* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */
+#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
+#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTREN_SDRPLLACHIEVED field value from a register. */
+#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : Main PLL Achieved Lock Interrupt Enable - mainplllost
+ * 
+ * When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager
+ * interrupt output.  When set to 0 the Main PLL lost lock bit is not ORed into the
+ * Clock Manager interrupt output.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_MAINPLLLOST_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_MAINPLLLOST_MSB        3
+/* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_MAINPLLLOST_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */
+#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */
+#define ALT_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_MAINPLLLOST_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTREN_MAINPLLLOST field value from a register. */
+#define ALT_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CLKMGR_INTREN_MAINPLLLOST register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : Peripheral PLL Achieved Lock Interrupt Enable - perplllost
+ * 
+ * When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager
+ * interrupt output.  When set to 0 the Peripheral PLL lost lock bit is not ORed
+ * into the Clock Manager interrupt output.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_PERPLLLOST_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_PERPLLLOST_MSB        4
+/* The width in bits of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_PERPLLLOST_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */
+#define ALT_CLKMGR_INTREN_PERPLLLOST_SET_MSK    0x00000010
+/* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */
+#define ALT_CLKMGR_INTREN_PERPLLLOST_CLR_MSK    0xffffffef
+/* The reset value of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_PERPLLLOST_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTREN_PERPLLLOST field value from a register. */
+#define ALT_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_CLKMGR_INTREN_PERPLLLOST register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrplllost
+ * 
+ * When set to 1, the SDRAM PLL lost lock bit is ORed into the Clock Manager
+ * interrupt output.  When set to 0 the SDRAM PLL lost lock bit is not ORed into
+ * the Clock Manager interrupt output.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_SDRPLLLOST_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_SDRPLLLOST_MSB        5
+/* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_SDRPLLLOST_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */
+#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET_MSK    0x00000020
+/* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */
+#define ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
+#define ALT_CLKMGR_INTREN_SDRPLLLOST_RESET      0x0
+/* Extracts the ALT_CLKMGR_INTREN_SDRPLLLOST field value from a register. */
+#define ALT_CLKMGR_INTREN_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_CLKMGR_INTREN_SDRPLLLOST register field value suitable for setting the register. */
+#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_INTREN.
+ */
+struct ALT_CLKMGR_INTREN_s
+{
+    uint32_t  mainpllachieved :  1;  /* Main PLL Achieved Lock Interrupt Enable */
+    uint32_t  perpllachieved  :  1;  /* Peripheral PLL Achieved Lock Interrupt Enable */
+    uint32_t  sdrpllachieved  :  1;  /* SDRAM PLL Achieved Lock Interrupt Enable */
+    uint32_t  mainplllost     :  1;  /* Main PLL Achieved Lock Interrupt Enable */
+    uint32_t  perplllost      :  1;  /* Peripheral PLL Achieved Lock Interrupt Enable */
+    uint32_t  sdrplllost      :  1;  /* SDRAM PLL Achieved Lock Interrupt Enable */
+    uint32_t                  : 26;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_INTREN. */
+typedef volatile struct ALT_CLKMGR_INTREN_s  ALT_CLKMGR_INTREN_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_INTREN register from the beginning of the component. */
+#define ALT_CLKMGR_INTREN_OFST        0xc
+
+/*
+ * Register : Debug clock Control Register - dbctrl
+ * 
+ * Contains fields that control the debug clocks.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                   
+ * :-------|:-------|:------|:-------------------------------
+ *  [0]    | RW     | 0x1   | Debug Clocks Stay on EOSC1_CLK
+ *  [1]    | RW     | 0x1   | Debug Clocks Enable Safe Mode 
+ *  [31:2] | ???    | 0x0   | *UNDEFINED*                   
+ * 
+ */
+/*
+ * Field : Debug Clocks Stay on EOSC1_CLK - stayosc1
+ * 
+ * When this bit is set the debug root clock (Main PLL C2 output) will always be
+ * bypassed to the EOSC1_clk independent of any other clock manager settings.
+ * When clear the debug source will be a function of register settings in the clock
+ * manager.  Clocks affected by this bit are dbg_at_clk, dbg_clk, dbg_trace_clk,
+ * and dbg_timer_clk.
+ * 
+ * The reset value for this bit is applied on a cold reset.   Warm reset has no
+ * affect on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
+#define ALT_CLKMGR_DBCTL_STAYOSC1_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
+#define ALT_CLKMGR_DBCTL_STAYOSC1_MSB        0
+/* The width in bits of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
+#define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */
+#define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */
+#define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
+#define ALT_CLKMGR_DBCTL_STAYOSC1_RESET      0x1
+/* Extracts the ALT_CLKMGR_DBCTL_STAYOSC1 field value from a register. */
+#define ALT_CLKMGR_DBCTL_STAYOSC1_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_DBCTL_STAYOSC1 register field value suitable for setting the register. */
+#define ALT_CLKMGR_DBCTL_STAYOSC1_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Debug Clocks Enable Safe Mode - ensfmdwr
+ * 
+ * When this bit is set the debug clocks will be affected by the assertion of Safe
+ * Mode on a warm reset if Stay OSC1 is not set.
+ * 
+ * When this bit is clear the debug clocks will not be affected by the assertion of
+ * Safe Mode on a warm reset.
+ * 
+ * If Debug Clocks are in Safe Mode they are taken out of Safe Mode when the Safe
+ * Mode bit is cleared independent of this bit.The reset value of this bit is
+ * applied on a cold reset; warm reset has no affect on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
+#define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
+#define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB        1
+/* The width in bits of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
+#define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */
+#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */
+#define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
+#define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET      0x1
+/* Extracts the ALT_CLKMGR_DBCTL_ENSFMDWR field value from a register. */
+#define ALT_CLKMGR_DBCTL_ENSFMDWR_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CLKMGR_DBCTL_ENSFMDWR register field value suitable for setting the register. */
+#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET(value) (((value) << 1) & 0x00000002)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_DBCTL.
+ */
+struct ALT_CLKMGR_DBCTL_s
+{
+    uint32_t  stayosc1 :  1;  /* Debug Clocks Stay on EOSC1_CLK */
+    uint32_t  ensfmdwr :  1;  /* Debug Clocks Enable Safe Mode */
+    uint32_t           : 30;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_DBCTL. */
+typedef volatile struct ALT_CLKMGR_DBCTL_s  ALT_CLKMGR_DBCTL_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_DBCTL register from the beginning of the component. */
+#define ALT_CLKMGR_DBCTL_OFST        0x10
+
+/*
+ * Register : Status Register - stat
+ * 
+ * Provides status of Hardware Managed Clock transition State Machine.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description           
+ * :-------|:-------|:------|:-----------------------
+ *  [0]    | R      | 0x0   | HW Managed Clocks BUSY
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*           
+ * 
+ */
+/*
+ * Field : HW Managed Clocks BUSY - busy
+ * 
+ * This read only bit indicates that the Hardware Managed clock's state machine is
+ * active.  If the state machine is active, then the clocks are in transition.
+ * Software should poll this bit after changing the source of internal clocks when
+ * writing to the BYPASS, CTRL or DBCTRL registers.   Immediately following writes
+ * to any of these registers, SW should wait until this bit is IDLE before
+ * proceeding with any other register writes in the Clock Manager.
+ * 
+ * The reset value of this bit is applied on a cold reset; warm reset has no affect
+ * on this bit.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                        | Value | Description         
+ * :----------------------------|:------|:---------------------
+ *  ALT_CLKMGR_STAT_BUSY_E_IDLE | 0x0   | Clocks stable       
+ *  ALT_CLKMGR_STAT_BUSY_E_BUSY | 0x1   | Clocks in transition
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_STAT_BUSY
+ * 
+ * Clocks stable
+ */
+#define ALT_CLKMGR_STAT_BUSY_E_IDLE 0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_STAT_BUSY
+ * 
+ * Clocks in transition
+ */
+#define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_BUSY register field. */
+#define ALT_CLKMGR_STAT_BUSY_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_BUSY register field. */
+#define ALT_CLKMGR_STAT_BUSY_MSB        0
+/* The width in bits of the ALT_CLKMGR_STAT_BUSY register field. */
+#define ALT_CLKMGR_STAT_BUSY_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_STAT_BUSY register field value. */
+#define ALT_CLKMGR_STAT_BUSY_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_STAT_BUSY register field value. */
+#define ALT_CLKMGR_STAT_BUSY_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_STAT_BUSY register field. */
+#define ALT_CLKMGR_STAT_BUSY_RESET      0x0
+/* Extracts the ALT_CLKMGR_STAT_BUSY field value from a register. */
+#define ALT_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_STAT_BUSY register field value suitable for setting the register. */
+#define ALT_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_STAT.
+ */
+struct ALT_CLKMGR_STAT_s
+{
+    const uint32_t  busy :  1;  /* HW Managed Clocks BUSY */
+    uint32_t             : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_STAT. */
+typedef volatile struct ALT_CLKMGR_STAT_s  ALT_CLKMGR_STAT_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_STAT register from the beginning of the component. */
+#define ALT_CLKMGR_STAT_OFST        0x14
+
+/*
+ * Register Group : Main PLL Group - ALT_CLKMGR_MAINPLL
+ * Main PLL Group
+ * 
+ * Contains registers with settings for the Main PLL.
+ * 
+ */
+/*
+ * Register : Main PLL VCO Control Register - vco
+ * 
+ * Contains settings that control the Main PLL VCO. The VCO output frequency is the
+ * input frequency multiplied by the numerator (M+1) and divided by the denominator
+ * (N+1). The VCO input clock source is always eosc1_clk.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                    
+ * :--------|:-------|:------|:--------------------------------
+ *  [0]     | RW     | 0x1   | BG PWRDN                       
+ *  [1]     | RW     | 0x0   | Enable                         
+ *  [2]     | RW     | 0x1   | Power down                     
+ *  [15:3]  | RW     | 0x1   | Numerator (M)                  
+ *  [21:16] | RW     | 0x1   | Denominator (N)                
+ *  [23:22] | ???    | 0x0   | *UNDEFINED*                    
+ *  [24]    | RW     | 0x0   | All Output Counter Reset       
+ *  [30:25] | RW     | 0x0   | Output Counter Reset           
+ *  [31]    | RW     | 0x1   | External Regulator Input Select
+ * 
+ */
+/*
+ * Field : BG PWRDN - bgpwrdn
+ * 
+ * If '1', powers down bandgap. If '0', bandgap is not power down.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_MSB        0
+/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN field value from a register. */
+#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Enable - en
+ * 
+ * If '1', VCO is enabled. If '0', VCO is in reset.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_EN_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_EN_MSB        1
+/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_EN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_EN_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_EN_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_EN_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_VCO_EN field value from a register. */
+#define ALT_CLKMGR_MAINPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CLKMGR_MAINPLL_VCO_EN register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : Power down - pwrdn
+ * 
+ * If '1', power down analog circuitry. If '0', analog circuitry not powered down.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_MSB        2
+/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_VCO_PWRDN field value from a register. */
+#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : Numerator (M) - numer
+ * 
+ * Numerator in VCO output frequency equation. For incremental frequency change, if
+ * the new value lead to less than 20% of the frequency change, this value can be
+ * changed without resetting the PLL. The Numerator and Denominator can not be
+ * changed at the same time for incremental frequency changed.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_NUMER_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_NUMER_MSB        15
+/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_NUMER_WIDTH      13
+/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET_MSK    0x0000fff8
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK    0xffff0007
+/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_NUMER_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_VCO_NUMER field value from a register. */
+#define ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
+/* Produces a ALT_CLKMGR_MAINPLL_VCO_NUMER register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
+
+/*
+ * Field : Denominator (N) - denom
+ * 
+ * Denominator in VCO output frequency equation. For incremental frequency change,
+ * if the new value lead to less than 20% of the frequency change, this value can
+ * be changed without resetting the PLL. The Numerator and Denominator can not be
+ * changed at the same time for incremental frequency changed.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_DENOM_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_DENOM_MSB        21
+/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_DENOM_WIDTH      6
+/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET_MSK    0x003f0000
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK    0xffc0ffff
+/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_DENOM_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_VCO_DENOM field value from a register. */
+#define ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
+/* Produces a ALT_CLKMGR_MAINPLL_VCO_DENOM register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
+
+/*
+ * Field : All Output Counter Reset - outresetall
+ * 
+ * Before releasing Bypass, All Output Counter Reset must be set and cleared by
+ * software for correct clock operation.
+ * 
+ * If '1', Reset phase multiplexer and all output counter state. So that after the
+ * assertion all the clocks output are start from rising edge align.
+ * 
+ * If '0', phase multiplexer and output counter state not reset and no change to
+ * the phase of the clock outputs.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_LSB        24
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_MSB        24
+/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK    0x01000000
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK    0xfeffffff
+/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL field value from a register. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
+/* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
+
+/*
+ * Field : Output Counter Reset - outreset
+ * 
+ * Resets the individual PLL output counter.
+ * 
+ * For software to change the PLL output counter without producing glitches on the
+ * respective clock, SW must set the VCO register respective Output Counter Reset
+ * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
+ * the Output Counter Reset Ack Status Register. Software then writes the
+ * appropriate counter register, and then clears the respective VCO register Output
+ * Counter Reset bit.
+ * 
+ * LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
+ * 
+ * If set to '1', reset output divider, no clock output from counter.
+ * 
+ * If set to '0', counter is not reset.
+ * 
+ * The reset value of this bit is applied on a cold reset; warm reset has no affect
+ * on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB        25
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_MSB        30
+/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_WIDTH      6
+/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET_MSK    0x7e000000
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK    0x81ffffff
+/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRST field value from a register. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
+/* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
+
+/*
+ * Field : External Regulator Input Select - regextsel
+ * 
+ * If set to '1', the external regulator is selected for the PLL.
+ * 
+ * If set to '0', the internal regulator is slected.
+ * 
+ * It is strongly recommended to select the external regulator while the PLL is not
+ * enabled (in reset), and  then disable the external regulater once the PLL
+ * becomes enabled.  Software should simulateously update the 'Enable' bit and the
+ * 'External Regulator Input Select' in the same write access to the VCO register.
+ * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be
+ * set, and vice versa.
+ * 
+ * The reset value of this bit is applied on a cold reset; warm reset has no affect
+ * on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_MSB        31
+/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET_MSK    0x80000000
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */
+#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL field value from a register. */
+#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_VCO.
+ */
+struct ALT_CLKMGR_MAINPLL_VCO_s
+{
+    uint32_t  bgpwrdn     :  1;  /* BG PWRDN */
+    uint32_t  en          :  1;  /* Enable */
+    uint32_t  pwrdn       :  1;  /* Power down */
+    uint32_t  numer       : 13;  /* Numerator (M) */
+    uint32_t  denom       :  6;  /* Denominator (N) */
+    uint32_t              :  2;  /* *UNDEFINED* */
+    uint32_t  outresetall :  1;  /* All Output Counter Reset */
+    uint32_t  outreset    :  6;  /* Output Counter Reset */
+    uint32_t  regextsel   :  1;  /* External Regulator Input Select */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_VCO. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_VCO_s  ALT_CLKMGR_MAINPLL_VCO_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_VCO register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_VCO_OFST        0x0
+
+/*
+ * Register : Main PLL VCO Advanced Control Register - misc
+ * 
+ * Contains VCO control signals and other PLL control signals need to be
+ * controllable through register.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                  
+ * :--------|:-------|:------|:------------------------------
+ *  [0]     | RW     | 0x0   | Loop Bandwidth Adjust Enabled
+ *  [12:1]  | RW     | 0x1   | Loop Bandwidth Adjust        
+ *  [13]    | RW     | 0x0   | Fast Locking Enable          
+ *  [14]    | RW     | 0x1   | Saturation Enable            
+ *  [31:15] | ???    | 0x0   | *UNDEFINED*                  
+ * 
+ */
+/*
+ * Field : Loop Bandwidth Adjust Enabled - bwadjen
+ * 
+ * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth
+ * Adjust field.
+ * 
+ * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2
+ * value of the VCO Control Register.  The M divided by 2 is the upper 12 bits
+ * (12:1) of the M field in the VCO register.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_MSB        0
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJEN field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Loop Bandwidth Adjust - bwadj
+ * 
+ * Provides Loop Bandwidth Adjust value.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_MSB        12
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_WIDTH      12
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET_MSK    0x00001ffe
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_CLR_MSK    0xffffe001
+/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJ field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
+/* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
+
+/*
+ * Field : Fast Locking Enable - fasten
+ * 
+ * Enables fast locking circuit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_LSB        13
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_MSB        13
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */
+#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET_MSK    0x00002000
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */
+#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_CLR_MSK    0xffffdfff
+/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_MISC_FASTEN field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
+/* Produces a ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000)
+
+/*
+ * Field : Saturation Enable - saten
+ * 
+ * Enables saturation behavior.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_SATEN_LSB        14
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_SATEN_MSB        14
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_SATEN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */
+#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET_MSK    0x00004000
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */
+#define ALT_CLKMGR_MAINPLL_MISC_SATEN_CLR_MSK    0xffffbfff
+/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
+#define ALT_CLKMGR_MAINPLL_MISC_SATEN_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_MISC_SATEN field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14)
+/* Produces a ALT_CLKMGR_MAINPLL_MISC_SATEN register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_MISC.
+ */
+struct ALT_CLKMGR_MAINPLL_MISC_s
+{
+    uint32_t  bwadjen :  1;  /* Loop Bandwidth Adjust Enabled */
+    uint32_t  bwadj   : 12;  /* Loop Bandwidth Adjust */
+    uint32_t  fasten  :  1;  /* Fast Locking Enable */
+    uint32_t  saten   :  1;  /* Saturation Enable */
+    uint32_t          : 17;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MISC. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_MISC_s  ALT_CLKMGR_MAINPLL_MISC_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_MISC register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_MISC_OFST        0x4
+
+/*
+ * Register : Main PLL C0 Control Register for Clock mpu_clk - mpuclk
+ * 
+ * Contains settings that control clock mpu_clk generated from the C0 output of the
+ * Main PLL.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0x0   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO/2 frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_MPUCLK_CNT field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_MPUCLK.
+ */
+struct ALT_CLKMGR_MAINPLL_MPUCLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_MPUCLK_s  ALT_CLKMGR_MAINPLL_MPUCLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_MPUCLK register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_MPUCLK_OFST        0x8
+
+/*
+ * Register : Main PLL C1 Control Register for Clock main_clk - mainclk
+ * 
+ * Contains settings that control clock main_clk generated from the C1 output of
+ * the Main PLL.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0x0   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO/4 frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_MAINCLK_CNT field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINCLK.
+ */
+struct ALT_CLKMGR_MAINPLL_MAINCLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINCLK. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_MAINCLK_s  ALT_CLKMGR_MAINPLL_MAINCLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINCLK register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_MAINCLK_OFST        0xc
+
+/*
+ * Register : Main PLL C2 Control Register for Clock dbg_base_clk - dbgatclk
+ * 
+ * Contains settings that control clock dbg_base_clk generated from the C2 output
+ * of the Main PLL.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0x0   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO/4 frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT field value from a register. */
+#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK.
+ */
+struct ALT_CLKMGR_MAINPLL_DBGATCLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_DBGATCLK_s  ALT_CLKMGR_MAINPLL_DBGATCLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_DBGATCLK register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_DBGATCLK_OFST        0x10
+
+/*
+ * Register : Main PLL C3 Control Register for Clock main_qspi_clk - mainqspiclk
+ * 
+ * Contains settings that control clock main_qspi_clk generated from the C3 output
+ * of the Main PLL.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0x3   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_RESET      0x3
+/* Extracts the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK.
+ */
+struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s  ALT_CLKMGR_MAINPLL_MAINQSPICLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINQSPICLK register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST        0x14
+
+/*
+ * Register : Main PLL C4 Control Register for Clock main_nand_sdmmc_clk - mainnandsdmmcclk
+ * 
+ * Contains settings that control clock main_nand_sdmmc_clk generated from the C4
+ * output of the Main PLL.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0x3   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_RESET      0x3
+/* Extracts the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK.
+ */
+struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s  ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST        0x18
+
+/*
+ * Register : Main PLL C5 Control Register for Clock cfg_s2f_user0_clk - cfgs2fuser0clk
+ * 
+ * Contains settings that control clock cfg_s2f_user0_clk generated from the C5
+ * output of the Main PLL.
+ * 
+ * Qsys and user documenation refer to cfg_s2f_user0_clk as cfg_h2f_user0_clk.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0xf   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */
+#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
+#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_RESET      0xf
+/* Extracts the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT field value from a register. */
+#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK.
+ */
+struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s  ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST        0x1c
+
+/*
+ * Register : Enable Register - en
+ * 
+ * Contains fields that control clock enables for clocks derived from the Main PLL.
+ * 
+ * 1: The clock is enabled.
+ * 
+ * 0: The clock is disabled.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description         
+ * :--------|:-------|:------|:---------------------
+ *  [0]     | RW     | 0x1   | l4_main_clk Enable  
+ *  [1]     | RW     | 0x1   | l3_mp_clk Enable    
+ *  [2]     | RW     | 0x1   | l4_mp_clk Enable    
+ *  [3]     | RW     | 0x1   | l4_sp_clk Enable    
+ *  [4]     | RW     | 0x1   | dbg_at_clk Enable   
+ *  [5]     | RW     | 0x1   | dbg_clk Enable      
+ *  [6]     | RW     | 0x1   | dbg_trace_clk Enable
+ *  [7]     | RW     | 0x1   | dbg_timer_clk Enable
+ *  [8]     | RW     | 0x1   | cfg_clk Enable      
+ *  [9]     | RW     | 0x1   | s2f_user0_clk Enable
+ *  [31:10] | ???    | 0x0   | *UNDEFINED*         
+ * 
+ */
+/*
+ * Field : l4_main_clk Enable - l4mainclk
+ * 
+ * Enables clock l4_main_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB        0
+/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : l3_mp_clk Enable - l3mpclk
+ * 
+ * Enables clock l3_mp_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB        1
+/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_EN_L3MPCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : l4_mp_clk Enable - l4mpclk
+ * 
+ * Enables clock l4_mp_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB        2
+/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MPCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : l4_sp_clk Enable - l4spclk
+ * 
+ * Enables clock l4_sp_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB        3
+/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4SPCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : dbg_at_clk Enable - dbgatclk
+ * 
+ * Enables clock dbg_at_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB        4
+/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK    0x00000010
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK    0xffffffef
+/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGATCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : dbg_clk Enable - dbgclk
+ * 
+ * Enables clock dbg_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB        5
+/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK    0x00000020
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : dbg_trace_clk Enable - dbgtraceclk
+ * 
+ * Enables clock dbg_trace_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB        6
+/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK    0x00000040
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : dbg_timer_clk Enable - dbgtimerclk
+ * 
+ * Enables clock dbg_timer_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB        7
+/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK    0x00000080
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : cfg_clk Enable - cfgclk
+ * 
+ * Enables clock cfg_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB        8
+/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK    0x00000100
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_EN_CFGCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : s2f_user0_clk Enable - s2fuser0clk
+ * 
+ * Enables clock s2f_user0_clk output.
+ * 
+ * Qsys and user documenation refer to s2f_user0_clk as h2f_user0_clk.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB        9
+/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK    0x00000200
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */
+#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
+#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET(value) (((value) << 9) & 0x00000200)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_EN.
+ */
+struct ALT_CLKMGR_MAINPLL_EN_s
+{
+    uint32_t  l4mainclk   :  1;  /* l4_main_clk Enable */
+    uint32_t  l3mpclk     :  1;  /* l3_mp_clk Enable */
+    uint32_t  l4mpclk     :  1;  /* l4_mp_clk Enable */
+    uint32_t  l4spclk     :  1;  /* l4_sp_clk Enable */
+    uint32_t  dbgatclk    :  1;  /* dbg_at_clk Enable */
+    uint32_t  dbgclk      :  1;  /* dbg_clk Enable */
+    uint32_t  dbgtraceclk :  1;  /* dbg_trace_clk Enable */
+    uint32_t  dbgtimerclk :  1;  /* dbg_timer_clk Enable */
+    uint32_t  cfgclk      :  1;  /* cfg_clk Enable */
+    uint32_t  s2fuser0clk :  1;  /* s2f_user0_clk Enable */
+    uint32_t              : 22;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_EN. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_EN_s  ALT_CLKMGR_MAINPLL_EN_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_EN register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_EN_OFST        0x20
+
+/*
+ * Register : Main Divide Register - maindiv
+ * 
+ * Contains fields that control clock dividers for main clocks derived from the
+ * Main PLL
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description        
+ * :--------|:-------|:------|:--------------------
+ *  [1:0]   | RW     | 0x0   | L3 MP Clock Divider
+ *  [3:2]   | RW     | 0x0   | L3 SP Clock Divider
+ *  [6:4]   | RW     | 0x0   | L4 MP Clock Divider
+ *  [9:7]   | RW     | 0x0   | L4 SP Clock Divider
+ *  [31:10] | ???    | 0x0   | *UNDEFINED*        
+ * 
+ */
+/*
+ * Field : L3 MP Clock Divider - l3mpclk
+ * 
+ * The l3_mp_clk is divided down from the l3_main_clk by the value specified in
+ * this field.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                      | Value | Description
+ * :------------------------------------------|:------|:------------
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 | 0x0   | Divide by 1
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 | 0x1   | Divide by 2
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK
+ * 
+ * Divide by 1
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1   0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK
+ * 
+ * Divide by 2
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB        1
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH      2
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK    0x00000003
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK    0xfffffffc
+/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(value) (((value) & 0x00000003) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET(value) (((value) << 0) & 0x00000003)
+
+/*
+ * Field : L3 SP Clock Divider - l3spclk
+ * 
+ * The l3_sp_clk is divided down from the l3_mp_clk by the value specified in this
+ * field.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                      | Value | Description
+ * :------------------------------------------|:------|:------------
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 | 0x0   | Divide by 1
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 | 0x1   | Divide by 2
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK
+ * 
+ * Divide by 1
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1   0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK
+ * 
+ * Divide by 2
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB        3
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH      2
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK    0x0000000c
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK    0xfffffff3
+/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(value) (((value) & 0x0000000c) >> 2)
+/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET(value) (((value) << 2) & 0x0000000c)
+
+/*
+ * Field : L4 MP Clock Divider - l4mpclk
+ * 
+ * The l4_mp_clk is divided down from the periph_base_clk by the value specified in
+ * this field.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description 
+ * :--------------------------------------------|:------|:-------------
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1   | 0x0   | Divide By 1 
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2   | 0x1   | Divide By 2 
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4   | 0x2   | Divide By 4 
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8   | 0x3   | Divide By 8 
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16  | 0x4   | Divide By 16
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 | 0x5   | Reserved    
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 | 0x6   | Reserved    
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 | 0x7   | Reserved    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
+ * 
+ * Divide By 1
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1   0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
+ * 
+ * Divide By 2
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2   0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
+ * 
+ * Divide By 4
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4   0x2
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
+ * 
+ * Divide By 8
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8   0x3
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
+ * 
+ * Divide By 16
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16  0x4
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 0x5
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 0x6
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 0x7
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_MSB        6
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_WIDTH      3
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK    0x00000070
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_CLR_MSK    0xffffff8f
+/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(value) (((value) & 0x00000070) >> 4)
+/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET(value) (((value) << 4) & 0x00000070)
+
+/*
+ * Field : L4 SP Clock Divider - l4spclk
+ * 
+ * The l4_sp_clk is divided down from the periph_base_clk by the value specified in
+ * this field.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description 
+ * :--------------------------------------------|:------|:-------------
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1   | 0x0   | Divide By 1 
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2   | 0x1   | Divide By 2 
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4   | 0x2   | Divide By 4 
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8   | 0x3   | Divide By 8 
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16  | 0x4   | Divide By 16
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 | 0x5   | Reserved    
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 | 0x6   | Reserved    
+ *  ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 | 0x7   | Reserved    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
+ * 
+ * Divide By 1
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1   0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
+ * 
+ * Divide By 2
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2   0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
+ * 
+ * Divide By 4
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4   0x2
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
+ * 
+ * Divide By 8
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8   0x3
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
+ * 
+ * Divide By 16
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16  0x4
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB        9
+/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH      3
+/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK    0x00000380
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK    0xfffffc7f
+/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(value) (((value) & 0x00000380) >> 7)
+/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET(value) (((value) << 7) & 0x00000380)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINDIV.
+ */
+struct ALT_CLKMGR_MAINPLL_MAINDIV_s
+{
+    uint32_t  l3mpclk :  2;  /* L3 MP Clock Divider */
+    uint32_t  l3spclk :  2;  /* L3 SP Clock Divider */
+    uint32_t  l4mpclk :  3;  /* L4 MP Clock Divider */
+    uint32_t  l4spclk :  3;  /* L4 SP Clock Divider */
+    uint32_t          : 22;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINDIV. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_MAINDIV_s  ALT_CLKMGR_MAINPLL_MAINDIV_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINDIV register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_MAINDIV_OFST        0x24
+
+/*
+ * Register : Debug Divide Register - dbgdiv
+ * 
+ * Contains fields that control clock dividers for debug clocks derived from the
+ * Main PLL
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description           
+ * :-------|:-------|:------|:-----------------------
+ *  [1:0]  | RW     | 0x0   | Debug AT Clock Divider
+ *  [3:2]  | RW     | 0x1   | Debug Clock Divider   
+ *  [31:4] | ???    | 0x0   | *UNDEFINED*           
+ * 
+ */
+/*
+ * Field : Debug AT Clock Divider - dbgatclk
+ * 
+ * The dbg_at_clk is divided down from the C2 output of  the Main PLL by the value
+ * specified in this field.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                      | Value | Description
+ * :------------------------------------------|:------|:------------
+ *  ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 | 0x0   | Divide by 1
+ *  ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 | 0x1   | Divide by 2
+ *  ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 | 0x2   | Divide by 4
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
+ * 
+ * Divide by 1
+ */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1   0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
+ * 
+ * Divide by 2
+ */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2   0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
+ * 
+ * Divide by 4
+ */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4   0x2
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_MSB        1
+/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_WIDTH      2
+/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK    0x00000003
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_CLR_MSK    0xfffffffc
+/* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(value) (((value) & 0x00000003) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET(value) (((value) << 0) & 0x00000003)
+
+/*
+ * Field : Debug Clock Divider - dbgclk
+ * 
+ * The dbg_clk is divided down from the dbg_at_clk by the value specified in this
+ * field.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                    | Value | Description
+ * :----------------------------------------|:------|:------------
+ *  ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 | 0x1   | Divide by 2
+ *  ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 | 0x2   | Divide by 4
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK
+ * 
+ * Divide by 2
+ */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK
+ * 
+ * Divide by 4
+ */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB        3
+/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH      2
+/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK    0x0000000c
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK    0xfffffff3
+/* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(value) (((value) & 0x0000000c) >> 2)
+/* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET(value) (((value) << 2) & 0x0000000c)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGDIV.
+ */
+struct ALT_CLKMGR_MAINPLL_DBGDIV_s
+{
+    uint32_t  dbgatclk :  2;  /* Debug AT Clock Divider */
+    uint32_t  dbgclk   :  2;  /* Debug Clock Divider */
+    uint32_t           : 28;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGDIV. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_DBGDIV_s  ALT_CLKMGR_MAINPLL_DBGDIV_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_DBGDIV register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_DBGDIV_OFST        0x28
+
+/*
+ * Register : Debug Trace Divide Register - tracediv
+ * 
+ * Contains a field that controls the clock divider for the debug trace clock
+ * derived from the Main PLL
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description              
+ * :-------|:-------|:------|:--------------------------
+ *  [2:0]  | RW     | 0x0   | Debug Trace Clock Divider
+ *  [31:3] | ???    | 0x0   | *UNDEFINED*              
+ * 
+ */
+/*
+ * Field : Debug Trace Clock Divider - traceclk
+ * 
+ * The dbg_trace_clk is divided down from the C2 output of  the Main PLL by the
+ * value specified in this field.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                          | Value | Description 
+ * :----------------------------------------------|:------|:-------------
+ *  ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1   | 0x0   | Divide By 1 
+ *  ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2   | 0x1   | Divide By 2 
+ *  ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4   | 0x2   | Divide By 4 
+ *  ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8   | 0x3   | Divide By 8 
+ *  ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16  | 0x4   | Divide By 16
+ *  ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 | 0x5   | Reserved    
+ *  ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 | 0x6   | Reserved    
+ *  ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 | 0x7   | Reserved    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
+ * 
+ * Divide By 1
+ */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1     0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
+ * 
+ * Divide By 2
+ */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2     0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
+ * 
+ * Divide By 4
+ */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4     0x2
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
+ * 
+ * Divide By 8
+ */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8     0x3
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
+ * 
+ * Divide By 16
+ */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16    0x4
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1   0x5
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2   0x6
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3   0x7
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB        2
+/* The width in bits of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH      3
+/* The mask used to set the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK    0x00000007
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK    0xfffffff8
+/* The reset value of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(value) (((value) & 0x00000007) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET(value) (((value) << 0) & 0x00000007)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV.
+ */
+struct ALT_CLKMGR_MAINPLL_TRACEDIV_s
+{
+    uint32_t  traceclk :  3;  /* Debug Trace Clock Divider */
+    uint32_t           : 29;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_TRACEDIV_s  ALT_CLKMGR_MAINPLL_TRACEDIV_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_TRACEDIV register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST        0x2c
+
+/*
+ * Register : L4 MP SP APB Clock Source - l4src
+ * 
+ * Contains fields that select the clock source for L4 MP and SP APB interconnect
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description     
+ * :-------|:-------|:------|:-----------------
+ *  [0]    | RW     | 0x0   | l4_mp_clk Source
+ *  [1]    | RW     | 0x0   | l4_sp_clk Source
+ *  [31:2] | ???    | 0x0   | *UNDEFINED*     
+ * 
+ */
+/*
+ * Field : l4_mp_clk Source - l4mp
+ * 
+ * Selects the source for l4_mp_clk
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                      | Value | Description    
+ * :------------------------------------------|:------|:----------------
+ *  ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL   | 0x0   | main_clk       
+ *  ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL | 0x1   | periph_base_clk
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP
+ * 
+ * main_clk
+ */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL     0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP
+ * 
+ * periph_base_clk
+ */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB        0
+/* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4MP field value from a register. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : l4_sp_clk Source - l4sp
+ * 
+ * Selects the source for l4_sp_clk
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                      | Value | Description    
+ * :------------------------------------------|:------|:----------------
+ *  ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL   | 0x0   | main_clk       
+ *  ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL | 0x1   | periph_base_clk
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP
+ * 
+ * main_clk
+ */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL     0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP
+ * 
+ * periph_base_clk
+ */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB        1
+/* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4SP field value from a register. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET(value) (((value) << 1) & 0x00000002)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_L4SRC.
+ */
+struct ALT_CLKMGR_MAINPLL_L4SRC_s
+{
+    uint32_t  l4mp :  1;  /* l4_mp_clk Source */
+    uint32_t  l4sp :  1;  /* l4_sp_clk Source */
+    uint32_t       : 30;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_L4SRC. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_L4SRC_s  ALT_CLKMGR_MAINPLL_L4SRC_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_L4SRC register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_L4SRC_OFST        0x30
+
+/*
+ * Register : Main PLL Output Counter Reset Ack Status Register - stat
+ * 
+ * Contains Output Clock Counter Reset acknowledge status.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                     
+ * :-------|:-------|:------|:---------------------------------
+ *  [5:0]  | R      | 0x0   | Output Counter Reset Acknowledge
+ *  [31:6] | ???    | 0x0   | *UNDEFINED*                     
+ * 
+ */
+/*
+ * Field : Output Counter Reset Acknowledge - outresetack
+ * 
+ * These read only bits per PLL output indicate that the PLL has received the
+ * Output Reset Counter request and has gracefully stopped the respective PLL
+ * output clock.
+ * 
+ * For software to change the PLL output counter without producing glitches on the
+ * respective clock, SW must set the VCO register respective Output Counter Reset
+ * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
+ * the Output Counter Reset Ack Status Register. Software then writes the
+ * appropriate counter register, and then clears the respective VCO register Output
+ * Counter Reset bit.
+ * 
+ * The reset value of this bit is applied on a cold reset; warm reset has no affect
+ * on this bit.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                         
+ * :--------------------------------------------|:------|:-------------------------------------
+ *  ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE    | 0x0   | Idle                                
+ *  ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1   | Output Counter Acknowledge received.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK
+ * 
+ * Idle
+ */
+#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE    0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK
+ * 
+ * Output Counter Acknowledge received.
+ */
+#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_MSB        5
+/* The width in bits of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_WIDTH      6
+/* The mask used to set the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */
+#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET_MSK    0x0000003f
+/* The mask used to clear the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */
+#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_CLR_MSK    0xffffffc0
+/* The reset value of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_RESET      0x0
+/* Extracts the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK field value from a register. */
+#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
+/* Produces a ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value suitable for setting the register. */
+#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_MAINPLL_STAT.
+ */
+struct ALT_CLKMGR_MAINPLL_STAT_s
+{
+    const uint32_t  outresetack :  6;  /* Output Counter Reset Acknowledge */
+    uint32_t                    : 26;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_MAINPLL_STAT. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_STAT_s  ALT_CLKMGR_MAINPLL_STAT_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_MAINPLL_STAT register from the beginning of the component. */
+#define ALT_CLKMGR_MAINPLL_STAT_OFST        0x34
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_CLKMGR_MAINPLL.
+ */
+struct ALT_CLKMGR_MAINPLL_s
+{
+    volatile ALT_CLKMGR_MAINPLL_VCO_t               vco;                /* ALT_CLKMGR_MAINPLL_VCO */
+    volatile ALT_CLKMGR_MAINPLL_MISC_t              misc;               /* ALT_CLKMGR_MAINPLL_MISC */
+    volatile ALT_CLKMGR_MAINPLL_MPUCLK_t            mpuclk;             /* ALT_CLKMGR_MAINPLL_MPUCLK */
+    volatile ALT_CLKMGR_MAINPLL_MAINCLK_t           mainclk;            /* ALT_CLKMGR_MAINPLL_MAINCLK */
+    volatile ALT_CLKMGR_MAINPLL_DBGATCLK_t          dbgatclk;           /* ALT_CLKMGR_MAINPLL_DBGATCLK */
+    volatile ALT_CLKMGR_MAINPLL_MAINQSPICLK_t       mainqspiclk;        /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */
+    volatile ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t  mainnandsdmmcclk;   /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */
+    volatile ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t    cfgs2fuser0clk;     /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */
+    volatile ALT_CLKMGR_MAINPLL_EN_t                en;                 /* ALT_CLKMGR_MAINPLL_EN */
+    volatile ALT_CLKMGR_MAINPLL_MAINDIV_t           maindiv;            /* ALT_CLKMGR_MAINPLL_MAINDIV */
+    volatile ALT_CLKMGR_MAINPLL_DBGDIV_t            dbgdiv;             /* ALT_CLKMGR_MAINPLL_DBGDIV */
+    volatile ALT_CLKMGR_MAINPLL_TRACEDIV_t          tracediv;           /* ALT_CLKMGR_MAINPLL_TRACEDIV */
+    volatile ALT_CLKMGR_MAINPLL_L4SRC_t             l4src;              /* ALT_CLKMGR_MAINPLL_L4SRC */
+    volatile ALT_CLKMGR_MAINPLL_STAT_t              stat;               /* ALT_CLKMGR_MAINPLL_STAT */
+    volatile uint32_t                               _pad_0x38_0x40[2];  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register group ALT_CLKMGR_MAINPLL. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_s  ALT_CLKMGR_MAINPLL_t;
+/* The struct declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */
+struct ALT_CLKMGR_MAINPLL_raw_s
+{
+    volatile uint32_t  vco;                /* ALT_CLKMGR_MAINPLL_VCO */
+    volatile uint32_t  misc;               /* ALT_CLKMGR_MAINPLL_MISC */
+    volatile uint32_t  mpuclk;             /* ALT_CLKMGR_MAINPLL_MPUCLK */
+    volatile uint32_t  mainclk;            /* ALT_CLKMGR_MAINPLL_MAINCLK */
+    volatile uint32_t  dbgatclk;           /* ALT_CLKMGR_MAINPLL_DBGATCLK */
+    volatile uint32_t  mainqspiclk;        /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */
+    volatile uint32_t  mainnandsdmmcclk;   /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */
+    volatile uint32_t  cfgs2fuser0clk;     /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */
+    volatile uint32_t  en;                 /* ALT_CLKMGR_MAINPLL_EN */
+    volatile uint32_t  maindiv;            /* ALT_CLKMGR_MAINPLL_MAINDIV */
+    volatile uint32_t  dbgdiv;             /* ALT_CLKMGR_MAINPLL_DBGDIV */
+    volatile uint32_t  tracediv;           /* ALT_CLKMGR_MAINPLL_TRACEDIV */
+    volatile uint32_t  l4src;              /* ALT_CLKMGR_MAINPLL_L4SRC */
+    volatile uint32_t  stat;               /* ALT_CLKMGR_MAINPLL_STAT */
+    volatile uint32_t  _pad_0x38_0x40[2];  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */
+typedef volatile struct ALT_CLKMGR_MAINPLL_raw_s  ALT_CLKMGR_MAINPLL_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : Peripheral PLL Group - ALT_CLKMGR_PERPLL
+ * Peripheral PLL Group
+ * 
+ * Contains registers with settings for the Peripheral PLL.
+ * 
+ */
+/*
+ * Register : Peripheral PLL VCO Control Register - vco
+ * 
+ * Contains settings that control the Peripheral PLL VCO. The VCO output frequency
+ * is the input frequency multiplied by the numerator (M+1) and divided by the
+ * denominator (N+1).
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                    
+ * :--------|:-------|:------|:--------------------------------
+ *  [0]     | RW     | 0x1   | BG PWRDN                       
+ *  [1]     | RW     | 0x0   | Enable                         
+ *  [2]     | RW     | 0x1   | Power down                     
+ *  [15:3]  | RW     | 0x1   | Numerator (M)                  
+ *  [21:16] | RW     | 0x1   | Denominator (N)                
+ *  [23:22] | RW     | 0x0   | Clock Source                   
+ *  [24]    | RW     | 0x0   | All Output Counter Reset       
+ *  [30:25] | RW     | 0x0   | Output Counter Reset           
+ *  [31]    | RW     | 0x1   | External Regulator Input Select
+ * 
+ */
+/*
+ * Field : BG PWRDN - bgpwrdn
+ * 
+ * If '1', powers down bandgap. If '0', bandgap is not power down.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_MSB        0
+/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_VCO_BGPWRDN field value from a register. */
+#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Enable - en
+ * 
+ * If '1', VCO is enabled. If '0', VCO is in reset.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_EN_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_EN_MSB        1
+/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_EN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_EN register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_EN_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_EN register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_EN_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_EN_RESET      0x0
+/* Extracts the ALT_CLKMGR_PERPLL_VCO_EN field value from a register. */
+#define ALT_CLKMGR_PERPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CLKMGR_PERPLL_VCO_EN register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : Power down - pwrdn
+ * 
+ * If '1', power down analog circuitry. If '0', analog circuitry not powered down.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_PWRDN_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_PWRDN_MSB        2
+/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_PWRDN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_PWRDN_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_PERPLL_VCO_PWRDN_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_VCO_PWRDN field value from a register. */
+#define ALT_CLKMGR_PERPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CLKMGR_PERPLL_VCO_PWRDN register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : Numerator (M) - numer
+ * 
+ * Numerator in VCO output frequency equation. For incremental frequency change, if
+ * the new value lead to less than 20% of the frequency change, this value can be
+ * changed without resetting the PLL. The Numerator and Denominator can not be
+ * changed at the same time for incremental frequency changed.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_PERPLL_VCO_NUMER_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_PERPLL_VCO_NUMER_MSB        15
+/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_PERPLL_VCO_NUMER_WIDTH      13
+/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET_MSK    0x0000fff8
+/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK    0xffff0007
+/* The reset value of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_PERPLL_VCO_NUMER_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_VCO_NUMER field value from a register. */
+#define ALT_CLKMGR_PERPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
+/* Produces a ALT_CLKMGR_PERPLL_VCO_NUMER register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
+
+/*
+ * Field : Denominator (N) - denom
+ * 
+ * Denominator in VCO output frequency equation. For incremental frequency change,
+ * if the new value lead to less than 20% of the frequency change, this value can
+ * be changed without resetting the PLL. The Numerator and Denominator can not be
+ * changed at the same time for incremental frequency changed.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_PERPLL_VCO_DENOM_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_PERPLL_VCO_DENOM_MSB        21
+/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_PERPLL_VCO_DENOM_WIDTH      6
+/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET_MSK    0x003f0000
+/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK    0xffc0ffff
+/* The reset value of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_PERPLL_VCO_DENOM_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_VCO_DENOM field value from a register. */
+#define ALT_CLKMGR_PERPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
+/* Produces a ALT_CLKMGR_PERPLL_VCO_DENOM register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
+
+/*
+ * Field : Clock Source - psrc
+ * 
+ * Controls the VCO input clock source.
+ * 
+ * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description       
+ * :--------------------------------------------|:------|:-------------------
+ *  ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1          | 0x0   | eosc1_clk         
+ *  ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2          | 0x1   | eosc2_clk         
+ *  ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF | 0x2   | f2s_periph_ref_clk
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC
+ * 
+ * eosc1_clk
+ */
+#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1          0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC
+ * 
+ * eosc2_clk
+ */
+#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2          0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC
+ * 
+ * f2s_periph_ref_clk
+ */
+#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF 0x2
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
+#define ALT_CLKMGR_PERPLL_VCO_PSRC_LSB        22
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
+#define ALT_CLKMGR_PERPLL_VCO_PSRC_MSB        23
+/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
+#define ALT_CLKMGR_PERPLL_VCO_PSRC_WIDTH      2
+/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET_MSK    0x00c00000
+/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK    0xff3fffff
+/* The reset value of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
+#define ALT_CLKMGR_PERPLL_VCO_PSRC_RESET      0x0
+/* Extracts the ALT_CLKMGR_PERPLL_VCO_PSRC field value from a register. */
+#define ALT_CLKMGR_PERPLL_VCO_PSRC_GET(value) (((value) & 0x00c00000) >> 22)
+/* Produces a ALT_CLKMGR_PERPLL_VCO_PSRC register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET(value) (((value) << 22) & 0x00c00000)
+
+/*
+ * Field : All Output Counter Reset - outresetall
+ * 
+ * Before releasing Bypass, All Output Counter Reset must be set and cleared by
+ * software for correct clock operation.
+ * 
+ * If '1', Reset phase multiplexer and all output counter state. So that after the
+ * assertion all the clocks output are start from rising edge align.
+ * 
+ * If '0', phase multiplexer and output counter state not reset and no change to
+ * the phase of the clock outputs.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_LSB        24
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_MSB        24
+/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET_MSK    0x01000000
+/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK    0xfeffffff
+/* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_RESET      0x0
+/* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL field value from a register. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
+/* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
+
+/*
+ * Field : Output Counter Reset - outreset
+ * 
+ * Resets the individual PLL output counter.
+ * 
+ * For software to change the PLL output counter without producing glitches on the
+ * respective clock, SW must set the VCO register respective Output Counter Reset
+ * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
+ * the Output Counter Reset Ack Status Register. Software then writes the
+ * appropriate counter register, and then clears the respective VCO register Output
+ * Counter Reset bit.
+ * 
+ * LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
+ * 
+ * If set to '1', reset output divider, no clock output from counter.
+ * 
+ * If set to '0', counter is not reset.
+ * 
+ * The reset value of this bit is applied on a cold reset; warm reset has no affect
+ * on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB        25
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRST_MSB        30
+/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRST_WIDTH      6
+/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET_MSK    0x7e000000
+/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK    0x81ffffff
+/* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRST_RESET      0x0
+/* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRST field value from a register. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
+/* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRST register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
+
+/*
+ * Field : External Regulator Input Select - regextsel
+ * 
+ * If set to '1', the external regulator is selected for the PLL.
+ * 
+ * If set to '0', the internal regulator is slected.
+ * 
+ * It is strongly recommended to select the external regulator while the PLL is not
+ * enabled (in reset), and  then disable the external regulater once the PLL
+ * becomes enabled.  Software should simulateously update the 'Enable' bit and the
+ * 'External Regulator Input Select' in the same write access to the VCO register.
+ * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be
+ * set, and vice versa.
+ * 
+ * The reset value of this bit is applied on a cold reset; warm reset has no affect
+ * on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_MSB        31
+/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET_MSK    0x80000000
+/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */
+#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL field value from a register. */
+#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_VCO.
+ */
+struct ALT_CLKMGR_PERPLL_VCO_s
+{
+    uint32_t  bgpwrdn     :  1;  /* BG PWRDN */
+    uint32_t  en          :  1;  /* Enable */
+    uint32_t  pwrdn       :  1;  /* Power down */
+    uint32_t  numer       : 13;  /* Numerator (M) */
+    uint32_t  denom       :  6;  /* Denominator (N) */
+    uint32_t  psrc        :  2;  /* Clock Source */
+    uint32_t  outresetall :  1;  /* All Output Counter Reset */
+    uint32_t  outreset    :  6;  /* Output Counter Reset */
+    uint32_t  regextsel   :  1;  /* External Regulator Input Select */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_VCO. */
+typedef volatile struct ALT_CLKMGR_PERPLL_VCO_s  ALT_CLKMGR_PERPLL_VCO_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_VCO register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_VCO_OFST        0x0
+
+/*
+ * Register : Peripheral PLL VCO Advanced Control Register - misc
+ * 
+ * Contains VCO control signals and other PLL control signals need to be
+ * controllable through register.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                  
+ * :--------|:-------|:------|:------------------------------
+ *  [0]     | RW     | 0x0   | Loop Bandwidth Adjust Enabled
+ *  [12:1]  | RW     | 0x1   | Loop Bandwidth Adjust        
+ *  [13]    | RW     | 0x0   | Fast Locking Enable          
+ *  [14]    | RW     | 0x1   | Saturation Enable            
+ *  [31:15] | ???    | 0x0   | *UNDEFINED*                  
+ * 
+ */
+/*
+ * Field : Loop Bandwidth Adjust Enabled - bwadjen
+ * 
+ * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth
+ * Adjust field.
+ * 
+ * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2
+ * value of the VCO Control Register.  The M divided by 2 is the upper 12 bits
+ * (12:1) of the M field in the VCO register.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_MSB        0
+/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_RESET      0x0
+/* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJEN field value from a register. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Loop Bandwidth Adjust - bwadj
+ * 
+ * Provides Loop Bandwidth Adjust value.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJ_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJ_MSB        12
+/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJ_WIDTH      12
+/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET_MSK    0x00001ffe
+/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJ_CLR_MSK    0xffffe001
+/* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJ_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJ field value from a register. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
+/* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJ register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
+
+/*
+ * Field : Fast Locking Enable - fasten
+ * 
+ * Enables fast locking circuit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_FASTEN_LSB        13
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_FASTEN_MSB        13
+/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_FASTEN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */
+#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET_MSK    0x00002000
+/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */
+#define ALT_CLKMGR_PERPLL_MISC_FASTEN_CLR_MSK    0xffffdfff
+/* The reset value of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_FASTEN_RESET      0x0
+/* Extracts the ALT_CLKMGR_PERPLL_MISC_FASTEN field value from a register. */
+#define ALT_CLKMGR_PERPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
+/* Produces a ALT_CLKMGR_PERPLL_MISC_FASTEN register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000)
+
+/*
+ * Field : Saturation Enable - saten
+ * 
+ * Enables saturation behavior.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_SATEN_LSB        14
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_SATEN_MSB        14
+/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_SATEN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */
+#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET_MSK    0x00004000
+/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */
+#define ALT_CLKMGR_PERPLL_MISC_SATEN_CLR_MSK    0xffffbfff
+/* The reset value of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
+#define ALT_CLKMGR_PERPLL_MISC_SATEN_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_MISC_SATEN field value from a register. */
+#define ALT_CLKMGR_PERPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14)
+/* Produces a ALT_CLKMGR_PERPLL_MISC_SATEN register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_MISC.
+ */
+struct ALT_CLKMGR_PERPLL_MISC_s
+{
+    uint32_t  bwadjen :  1;  /* Loop Bandwidth Adjust Enabled */
+    uint32_t  bwadj   : 12;  /* Loop Bandwidth Adjust */
+    uint32_t  fasten  :  1;  /* Fast Locking Enable */
+    uint32_t  saten   :  1;  /* Saturation Enable */
+    uint32_t          : 17;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_MISC. */
+typedef volatile struct ALT_CLKMGR_PERPLL_MISC_s  ALT_CLKMGR_PERPLL_MISC_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_MISC register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_MISC_OFST        0x4
+
+/*
+ * Register : Peripheral PLL C0 Control Register for Clock emac0_clk - emac0clk
+ * 
+ * Contains settings that control clock emac0_clk generated from the C0 output of
+ * the Peripheral PLL.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0x1   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT field value from a register. */
+#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK.
+ */
+struct ALT_CLKMGR_PERPLL_EMAC0CLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK. */
+typedef volatile struct ALT_CLKMGR_PERPLL_EMAC0CLK_s  ALT_CLKMGR_PERPLL_EMAC0CLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_EMAC0CLK register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST        0x8
+
+/*
+ * Register : Peripheral PLL C1 Control Register for Clock emac1_clk - emac1clk
+ * 
+ * Contains settings that control clock emac1_clk generated from the C1 output of
+ * the Peripheral PLL.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0x1   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT field value from a register. */
+#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK.
+ */
+struct ALT_CLKMGR_PERPLL_EMAC1CLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK. */
+typedef volatile struct ALT_CLKMGR_PERPLL_EMAC1CLK_s  ALT_CLKMGR_PERPLL_EMAC1CLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_EMAC1CLK register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_EMAC1CLK_OFST        0xc
+
+/*
+ * Register : Peripheral PLL C2 Control Register for Clock periph_qspi_clk - perqspiclk
+ * 
+ * Contains settings that control clock periph_qspi_clk generated from the C2
+ * output of the Peripheral PLL.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0x1   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT field value from a register. */
+#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK.
+ */
+struct ALT_CLKMGR_PERPLL_PERQSPICLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK. */
+typedef volatile struct ALT_CLKMGR_PERPLL_PERQSPICLK_s  ALT_CLKMGR_PERPLL_PERQSPICLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_PERQSPICLK register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_PERQSPICLK_OFST        0x10
+
+/*
+ * Register : Peripheral PLL C3 Control Register for Clock periph_nand_sdmmc_clk - pernandsdmmcclk
+ * 
+ * Contains settings that control clock periph_nand_sdmmc_clk generated from the C3
+ * output of the Peripheral PLL.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0x1   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT field value from a register. */
+#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK.
+ */
+struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK. */
+typedef volatile struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s  ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST        0x14
+
+/*
+ * Register : Peripheral PLL C4 Control Register for Clock periph_base_clk - perbaseclk
+ * 
+ * Contains settings that control clock periph_base_clk generated from the C4
+ * output of the Peripheral PLL.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0x1   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_PERBASECLK_CNT field value from a register. */
+#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_PERBASECLK.
+ */
+struct ALT_CLKMGR_PERPLL_PERBASECLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERBASECLK. */
+typedef volatile struct ALT_CLKMGR_PERPLL_PERBASECLK_s  ALT_CLKMGR_PERPLL_PERBASECLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_PERBASECLK register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_PERBASECLK_OFST        0x18
+
+/*
+ * Register : Peripheral PLL C5 Control Register for Clock s2f_user1_clk - s2fuser1clk
+ * 
+ * Contains settings that control clock s2f_user1_clk generated from the C5 output
+ * of the Peripheral PLL.
+ * 
+ * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [8:0]  | RW     | 0x1   | Counter    
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */
+#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
+#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT field value from a register. */
+#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK.
+ */
+struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s
+{
+    uint32_t  cnt :  9;  /* Counter */
+    uint32_t      : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK. */
+typedef volatile struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s  ALT_CLKMGR_PERPLL_S2FUSER1CLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_S2FUSER1CLK register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST        0x1c
+
+/*
+ * Register : Enable Register - en
+ * 
+ * Contains fields that control clock enables for clocks derived from the
+ * Peripheral PLL
+ * 
+ * 1: The clock is enabled.
+ * 
+ * 0: The clock is disabled.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description         
+ * :--------|:-------|:------|:---------------------
+ *  [0]     | RW     | 0x1   | emac0_clk Enable    
+ *  [1]     | RW     | 0x1   | emac1_clk Enable    
+ *  [2]     | RW     | 0x1   | usb_mp_clk Enable   
+ *  [3]     | RW     | 0x1   | spi_m_clk Enable    
+ *  [4]     | RW     | 0x1   | can0_clk Enable     
+ *  [5]     | RW     | 0x1   | can1_clk Enable     
+ *  [6]     | RW     | 0x1   | gpio_clk Enable     
+ *  [7]     | RW     | 0x1   | s2f_user1_clk Enable
+ *  [8]     | RW     | 0x1   | sdmmc_clk Enable    
+ *  [9]     | RW     | 0x1   | nand_x_clk Enable   
+ *  [10]    | RW     | 0x1   | nand_clk Enable     
+ *  [11]    | RW     | 0x1   | qspi_clk Enable     
+ *  [31:12] | ???    | 0x0   | *UNDEFINED*         
+ * 
+ */
+/*
+ * Field : emac0_clk Enable - emac0clk
+ * 
+ * Enables clock emac0_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB        0
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC0CLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : emac1_clk Enable - emac1clk
+ * 
+ * Enables clock emac1_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB        1
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC1CLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : usb_mp_clk Enable - usbclk
+ * 
+ * Enables clock usb_mp_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_USBCLK_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_USBCLK_MSB        2
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_USBCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_USBCLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_USBCLK_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CLKMGR_PERPLL_EN_USBCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : spi_m_clk Enable - spimclk
+ * 
+ * Enables clock spi_m_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB        3
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_SPIMCLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : can0_clk Enable - can0clk
+ * 
+ * Enables clock can0_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB        4
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK    0x00000010
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK    0xffffffef
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_CAN0CLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : can1_clk Enable - can1clk
+ * 
+ * Enables clock can1_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB        5
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK    0x00000020
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_CAN1CLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : gpio_clk Enable - gpioclk
+ * 
+ * Enables clock gpio_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB        6
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK    0x00000040
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_GPIOCLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : s2f_user1_clk Enable - s2fuser1clk
+ * 
+ * Enables clock s2f_user1_clk output.
+ * 
+ * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB        7
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK    0x00000080
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : sdmmc_clk Enable - sdmmcclk
+ * 
+ * Enables clock sdmmc_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB        8
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK    0x00000100
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_SDMMCCLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : nand_x_clk Enable - nandxclk
+ * 
+ * Enables clock nand_x_clk output
+ * 
+ * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and
+ * the nand_x_clk Enable should always be asserted before the nand_clk Enable is
+ * asserted. A brief delay is also required between switching the enables (8 *
+ * nand_clk period).
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB        9
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK    0x00000200
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_NANDXCLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET(value) (((value) << 9) & 0x00000200)
+
+/*
+ * Field : nand_clk Enable - nandclk
+ * 
+ * Enables clock nand_clk output
+ * 
+ * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and
+ * the nand_x_clk Enable should always be asserted before the nand_clk Enable is
+ * asserted. A brief delay is also required between switching the enables (8 *
+ * nand_clk period).
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB        10
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB        10
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK    0x00000400
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK    0xfffffbff
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_NANDCLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(value) (((value) & 0x00000400) >> 10)
+/* Produces a ALT_CLKMGR_PERPLL_EN_NANDCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET(value) (((value) << 10) & 0x00000400)
+
+/*
+ * Field : qspi_clk Enable - qspiclk
+ * 
+ * Enables clock qspi_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB        11
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB        11
+/* The width in bits of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK    0x00000800
+/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */
+#define ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK    0xfffff7ff
+/* The reset value of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
+#define ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_EN_QSPICLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(value) (((value) & 0x00000800) >> 11)
+/* Produces a ALT_CLKMGR_PERPLL_EN_QSPICLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET(value) (((value) << 11) & 0x00000800)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_EN.
+ */
+struct ALT_CLKMGR_PERPLL_EN_s
+{
+    uint32_t  emac0clk    :  1;  /* emac0_clk Enable */
+    uint32_t  emac1clk    :  1;  /* emac1_clk Enable */
+    uint32_t  usbclk      :  1;  /* usb_mp_clk Enable */
+    uint32_t  spimclk     :  1;  /* spi_m_clk Enable */
+    uint32_t  can0clk     :  1;  /* can0_clk Enable */
+    uint32_t  can1clk     :  1;  /* can1_clk Enable */
+    uint32_t  gpioclk     :  1;  /* gpio_clk Enable */
+    uint32_t  s2fuser1clk :  1;  /* s2f_user1_clk Enable */
+    uint32_t  sdmmcclk    :  1;  /* sdmmc_clk Enable */
+    uint32_t  nandxclk    :  1;  /* nand_x_clk Enable */
+    uint32_t  nandclk     :  1;  /* nand_clk Enable */
+    uint32_t  qspiclk     :  1;  /* qspi_clk Enable */
+    uint32_t              : 20;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_EN. */
+typedef volatile struct ALT_CLKMGR_PERPLL_EN_s  ALT_CLKMGR_PERPLL_EN_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_EN register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_EN_OFST        0x20
+
+/*
+ * Register : Divide Register - div
+ * 
+ * Contains fields that control clock dividers for clocks derived from the
+ * Peripheral PLL
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description             
+ * :--------|:-------|:------|:-------------------------
+ *  [2:0]   | RW     | 0x0   | USB Clock Divider       
+ *  [5:3]   | RW     | 0x0   | SPI Master Clock Divider
+ *  [8:6]   | RW     | 0x0   | CAN0 Clock Divider      
+ *  [11:9]  | RW     | 0x0   | CAN1 Clock Divider      
+ *  [31:12] | ???    | 0x0   | *UNDEFINED*             
+ * 
+ */
+/*
+ * Field : USB Clock Divider - usbclk
+ * 
+ * The usb_mp_clk is divided down from the periph_base_clk by the value specified
+ * in this field.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                  | Value | Description 
+ * :--------------------------------------|:------|:-------------
+ *  ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1   | 0x0   | Divide By 1 
+ *  ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2   | 0x1   | Divide By 2 
+ *  ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4   | 0x2   | Divide By 4 
+ *  ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8   | 0x3   | Divide By 8 
+ *  ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16  | 0x4   | Divide By 16
+ *  ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 | 0x5   | Reserved    
+ *  ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 | 0x6   | Reserved    
+ *  ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 | 0x7   | Reserved    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
+ * 
+ * Divide By 1
+ */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1     0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
+ * 
+ * Divide By 2
+ */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2     0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
+ * 
+ * Divide By 4
+ */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4     0x2
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
+ * 
+ * Divide By 8
+ */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8     0x3
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
+ * 
+ * Divide By 16
+ */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16    0x4
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1   0x5
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2   0x6
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3   0x7
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_MSB        2
+/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_WIDTH      3
+/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK    0x00000007
+/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_CLR_MSK    0xfffffff8
+/* The reset value of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_RESET      0x0
+/* Extracts the ALT_CLKMGR_PERPLL_DIV_USBCLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(value) (((value) & 0x00000007) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_DIV_USBCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET(value) (((value) << 0) & 0x00000007)
+
+/*
+ * Field : SPI Master Clock Divider - spimclk
+ * 
+ * The spi_m_clk is divided down from the periph_base_clk by the value specified in
+ * this field.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                   | Value | Description 
+ * :---------------------------------------|:------|:-------------
+ *  ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1   | 0x0   | Divide By 1 
+ *  ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2   | 0x1   | Divide By 2 
+ *  ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4   | 0x2   | Divide By 4 
+ *  ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8   | 0x3   | Divide By 8 
+ *  ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16  | 0x4   | Divide By 16
+ *  ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 | 0x5   | Reserved    
+ *  ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 | 0x6   | Reserved    
+ *  ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 | 0x7   | Reserved    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
+ * 
+ * Divide By 1
+ */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1    0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
+ * 
+ * Divide By 2
+ */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2    0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
+ * 
+ * Divide By 4
+ */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4    0x2
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
+ * 
+ * Divide By 8
+ */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8    0x3
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
+ * 
+ * Divide By 16
+ */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16   0x4
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1  0x5
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2  0x6
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3  0x7
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB        5
+/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH      3
+/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK    0x00000038
+/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK    0xffffffc7
+/* The reset value of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET      0x0
+/* Extracts the ALT_CLKMGR_PERPLL_DIV_SPIMCLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(value) (((value) & 0x00000038) >> 3)
+/* Produces a ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET(value) (((value) << 3) & 0x00000038)
+
+/*
+ * Field : CAN0 Clock Divider - can0clk
+ * 
+ * The can0_clk is divided down from the periph_base_clk by the value specified in
+ * this field.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                   | Value | Description 
+ * :---------------------------------------|:------|:-------------
+ *  ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1   | 0x0   | Divide By 1 
+ *  ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2   | 0x1   | Divide By 2 
+ *  ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4   | 0x2   | Divide By 4 
+ *  ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8   | 0x3   | Divide By 8 
+ *  ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16  | 0x4   | Divide By 16
+ *  ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 | 0x5   | Reserved    
+ *  ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 | 0x6   | Reserved    
+ *  ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 | 0x7   | Reserved    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
+ * 
+ * Divide By 1
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1    0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
+ * 
+ * Divide By 2
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2    0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
+ * 
+ * Divide By 4
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4    0x2
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
+ * 
+ * Divide By 8
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8    0x3
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
+ * 
+ * Divide By 16
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16   0x4
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1  0x5
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2  0x6
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3  0x7
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB        8
+/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH      3
+/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK    0x000001c0
+/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK    0xfffffe3f
+/* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET      0x0
+/* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN0CLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(value) (((value) & 0x000001c0) >> 6)
+/* Produces a ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET(value) (((value) << 6) & 0x000001c0)
+
+/*
+ * Field : CAN1 Clock Divider - can1clk
+ * 
+ * The can1_clk is divided down from the periph_base_clk by the value specified in
+ * this field.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                   | Value | Description 
+ * :---------------------------------------|:------|:-------------
+ *  ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1   | 0x0   | Divide By 1 
+ *  ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2   | 0x1   | Divide By 2 
+ *  ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4   | 0x2   | Divide By 4 
+ *  ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8   | 0x3   | Divide By 8 
+ *  ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16  | 0x4   | Divide By 16
+ *  ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 | 0x5   | Reserved    
+ *  ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 | 0x6   | Reserved    
+ *  ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 | 0x7   | Reserved    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
+ * 
+ * Divide By 1
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1    0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
+ * 
+ * Divide By 2
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2    0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
+ * 
+ * Divide By 4
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4    0x2
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
+ * 
+ * Divide By 8
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8    0x3
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
+ * 
+ * Divide By 16
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16   0x4
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1  0x5
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2  0x6
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
+ * 
+ * Reserved
+ */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3  0x7
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB        11
+/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH      3
+/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK    0x00000e00
+/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK    0xfffff1ff
+/* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET      0x0
+/* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN1CLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(value) (((value) & 0x00000e00) >> 9)
+/* Produces a ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET(value) (((value) << 9) & 0x00000e00)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_DIV.
+ */
+struct ALT_CLKMGR_PERPLL_DIV_s
+{
+    uint32_t  usbclk  :  3;  /* USB Clock Divider */
+    uint32_t  spimclk :  3;  /* SPI Master Clock Divider */
+    uint32_t  can0clk :  3;  /* CAN0 Clock Divider */
+    uint32_t  can1clk :  3;  /* CAN1 Clock Divider */
+    uint32_t          : 20;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_DIV. */
+typedef volatile struct ALT_CLKMGR_PERPLL_DIV_s  ALT_CLKMGR_PERPLL_DIV_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_DIV register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_DIV_OFST        0x24
+
+/*
+ * Register : GPIO Divide Register - gpiodiv
+ * 
+ * Contains a field that controls the clock divider for the GPIO De-bounce clock.
+ * 
+ * Only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                 
+ * :--------|:-------|:------|:-----------------------------
+ *  [23:0]  | RW     | 0x1   | GPIO De-bounce Clock Divider
+ *  [31:24] | ???    | 0x0   | *UNDEFINED*                 
+ * 
+ */
+/*
+ * Field : GPIO De-bounce Clock Divider - gpiodbclk
+ * 
+ * The gpio_db_clk is divided down from the periph_base_clk by the value plus one
+ * specified in this field. The value 0 (divide by 1) is illegal. A value of 1
+ * indicates divide by 2, 2 divide by 3, etc.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
+#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
+#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB        23
+/* The width in bits of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
+#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH      24
+/* The mask used to set the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */
+#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK    0x00ffffff
+/* The mask used to clear the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */
+#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK    0xff000000
+/* The reset value of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
+#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK field value from a register. */
+#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x00ffffff) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x00ffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_GPIODIV.
+ */
+struct ALT_CLKMGR_PERPLL_GPIODIV_s
+{
+    uint32_t  gpiodbclk : 24;  /* GPIO De-bounce Clock Divider */
+    uint32_t            :  8;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_GPIODIV. */
+typedef volatile struct ALT_CLKMGR_PERPLL_GPIODIV_s  ALT_CLKMGR_PERPLL_GPIODIV_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_GPIODIV register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_GPIODIV_OFST        0x28
+
+/*
+ * Register : Flash Clock Source Register - src
+ * 
+ * Contains fields that select the source clocks for the flash controllers.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description       
+ * :-------|:-------|:------|:-------------------
+ *  [1:0]  | RW     | 0x1   | SDMMC Clock Source
+ *  [3:2]  | RW     | 0x1   | NAND Clock Source 
+ *  [5:4]  | RW     | 0x1   | QSPI Clock Source 
+ *  [31:6] | ???    | 0x0   | *UNDEFINED*       
+ * 
+ */
+/*
+ * Field : SDMMC Clock Source - sdmmc
+ * 
+ * Selects the source clock for the SDMMC.
+ * 
+ * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                             | Value | Description          
+ * :-------------------------------------------------|:------|:----------------------
+ *  ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK | 0x0   | f2s_periph_ref_clk   
+ *  ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK      | 0x1   | main_nand_sdmmc_clk  
+ *  ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK    | 0x2   | periph_nand_sdmmc_clk
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC
+ * 
+ * f2s_periph_ref_clk
+ */
+#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK    0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC
+ * 
+ * main_nand_sdmmc_clk
+ */
+#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK         0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC
+ * 
+ * periph_nand_sdmmc_clk
+ */
+#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK       0x2
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
+#define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
+#define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB        1
+/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
+#define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH      2
+/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */
+#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK    0x00000003
+/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */
+#define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK    0xfffffffc
+/* The reset value of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
+#define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_SRC_SDMMC field value from a register. */
+#define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(value) (((value) & 0x00000003) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_SRC_SDMMC register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(value) (((value) << 0) & 0x00000003)
+
+/*
+ * Field : NAND Clock Source - nand
+ * 
+ * Selects the source clock for the NAND.
+ * 
+ * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                            | Value | Description          
+ * :------------------------------------------------|:------|:----------------------
+ *  ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK | 0x0   | f2s_periph_ref_clk   
+ *  ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK      | 0x1   | main_nand_sdmmc_clk  
+ *  ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK    | 0x2   | periph_nand_sdmmc_clk
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND
+ * 
+ * f2s_periph_ref_clk
+ */
+#define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK 0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND
+ * 
+ * main_nand_sdmmc_clk
+ */
+#define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK      0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND
+ * 
+ * periph_nand_sdmmc_clk
+ */
+#define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK    0x2
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
+#define ALT_CLKMGR_PERPLL_SRC_NAND_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
+#define ALT_CLKMGR_PERPLL_SRC_NAND_MSB        3
+/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
+#define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH      2
+/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */
+#define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK    0x0000000c
+/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */
+#define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK    0xfffffff3
+/* The reset value of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
+#define ALT_CLKMGR_PERPLL_SRC_NAND_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_SRC_NAND field value from a register. */
+#define ALT_CLKMGR_PERPLL_SRC_NAND_GET(value) (((value) & 0x0000000c) >> 2)
+/* Produces a ALT_CLKMGR_PERPLL_SRC_NAND register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_SRC_NAND_SET(value) (((value) << 2) & 0x0000000c)
+
+/*
+ * Field : QSPI Clock Source - qspi
+ * 
+ * Selects the source clock for the QSPI.
+ * 
+ * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                            | Value | Description       
+ * :------------------------------------------------|:------|:-------------------
+ *  ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK | 0x0   | f2s_periph_ref_clk
+ *  ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK      | 0x1   | main_qspi_clk     
+ *  ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK    | 0x2   | periph_qspi_clk   
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI
+ * 
+ * f2s_periph_ref_clk
+ */
+#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK 0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI
+ * 
+ * main_qspi_clk
+ */
+#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK      0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI
+ * 
+ * periph_qspi_clk
+ */
+#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK    0x2
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
+#define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
+#define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB        5
+/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
+#define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH      2
+/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */
+#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK    0x00000030
+/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */
+#define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK    0xffffffcf
+/* The reset value of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
+#define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET      0x1
+/* Extracts the ALT_CLKMGR_PERPLL_SRC_QSPI field value from a register. */
+#define ALT_CLKMGR_PERPLL_SRC_QSPI_GET(value) (((value) & 0x00000030) >> 4)
+/* Produces a ALT_CLKMGR_PERPLL_SRC_QSPI register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET(value) (((value) << 4) & 0x00000030)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_SRC.
+ */
+struct ALT_CLKMGR_PERPLL_SRC_s
+{
+    uint32_t  sdmmc :  2;  /* SDMMC Clock Source */
+    uint32_t  nand  :  2;  /* NAND Clock Source */
+    uint32_t  qspi  :  2;  /* QSPI Clock Source */
+    uint32_t        : 26;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_SRC. */
+typedef volatile struct ALT_CLKMGR_PERPLL_SRC_s  ALT_CLKMGR_PERPLL_SRC_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_SRC register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_SRC_OFST        0x2c
+
+/*
+ * Register : Peripheral PLL Output Counter Reset Ack Status Register - stat
+ * 
+ * Contains Output Clock Counter Reset acknowledge status.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                     
+ * :-------|:-------|:------|:---------------------------------
+ *  [5:0]  | R      | 0x0   | Output Counter Reset Acknowledge
+ *  [31:6] | ???    | 0x0   | *UNDEFINED*                     
+ * 
+ */
+/*
+ * Field : Output Counter Reset Acknowledge - outresetack
+ * 
+ * These read only bits per PLL output indicate that the PLL has received the
+ * Output Reset Counter request and has gracefully stopped the respective PLL
+ * output clock.
+ * 
+ * For software to change the PLL output counter without producing glitches on the
+ * respective clock, SW must set the VCO register respective Output Counter Reset
+ * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
+ * the Output Counter Reset Ack Status Register. Software then writes the
+ * appropriate counter register, and then clears the respective VCO register Output
+ * Counter Reset bit.
+ * 
+ * The reset value of this bit is applied on a cold reset; warm reset has no affect
+ * on this bit.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                       | Value | Description                         
+ * :-------------------------------------------|:------|:-------------------------------------
+ *  ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE    | 0x0   | Idle                                
+ *  ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1   | Output Counter Acknowledge received.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK
+ * 
+ * Idle
+ */
+#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE     0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK
+ * 
+ * Output Counter Acknowledge received.
+ */
+#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_MSB        5
+/* The width in bits of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_WIDTH      6
+/* The mask used to set the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */
+#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET_MSK    0x0000003f
+/* The mask used to clear the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */
+#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_CLR_MSK    0xffffffc0
+/* The reset value of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_RESET      0x0
+/* Extracts the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK field value from a register. */
+#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
+/* Produces a ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value suitable for setting the register. */
+#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_PERPLL_STAT.
+ */
+struct ALT_CLKMGR_PERPLL_STAT_s
+{
+    const uint32_t  outresetack :  6;  /* Output Counter Reset Acknowledge */
+    uint32_t                    : 26;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_PERPLL_STAT. */
+typedef volatile struct ALT_CLKMGR_PERPLL_STAT_s  ALT_CLKMGR_PERPLL_STAT_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_PERPLL_STAT register from the beginning of the component. */
+#define ALT_CLKMGR_PERPLL_STAT_OFST        0x30
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_CLKMGR_PERPLL.
+ */
+struct ALT_CLKMGR_PERPLL_s
+{
+    volatile ALT_CLKMGR_PERPLL_VCO_t              vco;                /* ALT_CLKMGR_PERPLL_VCO */
+    volatile ALT_CLKMGR_PERPLL_MISC_t             misc;               /* ALT_CLKMGR_PERPLL_MISC */
+    volatile ALT_CLKMGR_PERPLL_EMAC0CLK_t         emac0clk;           /* ALT_CLKMGR_PERPLL_EMAC0CLK */
+    volatile ALT_CLKMGR_PERPLL_EMAC1CLK_t         emac1clk;           /* ALT_CLKMGR_PERPLL_EMAC1CLK */
+    volatile ALT_CLKMGR_PERPLL_PERQSPICLK_t       perqspiclk;         /* ALT_CLKMGR_PERPLL_PERQSPICLK */
+    volatile ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t  pernandsdmmcclk;    /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */
+    volatile ALT_CLKMGR_PERPLL_PERBASECLK_t       perbaseclk;         /* ALT_CLKMGR_PERPLL_PERBASECLK */
+    volatile ALT_CLKMGR_PERPLL_S2FUSER1CLK_t      s2fuser1clk;        /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */
+    volatile ALT_CLKMGR_PERPLL_EN_t               en;                 /* ALT_CLKMGR_PERPLL_EN */
+    volatile ALT_CLKMGR_PERPLL_DIV_t              div;                /* ALT_CLKMGR_PERPLL_DIV */
+    volatile ALT_CLKMGR_PERPLL_GPIODIV_t          gpiodiv;            /* ALT_CLKMGR_PERPLL_GPIODIV */
+    volatile ALT_CLKMGR_PERPLL_SRC_t              src;                /* ALT_CLKMGR_PERPLL_SRC */
+    volatile ALT_CLKMGR_PERPLL_STAT_t             stat;               /* ALT_CLKMGR_PERPLL_STAT */
+    volatile uint32_t                             _pad_0x34_0x40[3];  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register group ALT_CLKMGR_PERPLL. */
+typedef volatile struct ALT_CLKMGR_PERPLL_s  ALT_CLKMGR_PERPLL_t;
+/* The struct declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */
+struct ALT_CLKMGR_PERPLL_raw_s
+{
+    volatile uint32_t  vco;                /* ALT_CLKMGR_PERPLL_VCO */
+    volatile uint32_t  misc;               /* ALT_CLKMGR_PERPLL_MISC */
+    volatile uint32_t  emac0clk;           /* ALT_CLKMGR_PERPLL_EMAC0CLK */
+    volatile uint32_t  emac1clk;           /* ALT_CLKMGR_PERPLL_EMAC1CLK */
+    volatile uint32_t  perqspiclk;         /* ALT_CLKMGR_PERPLL_PERQSPICLK */
+    volatile uint32_t  pernandsdmmcclk;    /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */
+    volatile uint32_t  perbaseclk;         /* ALT_CLKMGR_PERPLL_PERBASECLK */
+    volatile uint32_t  s2fuser1clk;        /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */
+    volatile uint32_t  en;                 /* ALT_CLKMGR_PERPLL_EN */
+    volatile uint32_t  div;                /* ALT_CLKMGR_PERPLL_DIV */
+    volatile uint32_t  gpiodiv;            /* ALT_CLKMGR_PERPLL_GPIODIV */
+    volatile uint32_t  src;                /* ALT_CLKMGR_PERPLL_SRC */
+    volatile uint32_t  stat;               /* ALT_CLKMGR_PERPLL_STAT */
+    volatile uint32_t  _pad_0x34_0x40[3];  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */
+typedef volatile struct ALT_CLKMGR_PERPLL_raw_s  ALT_CLKMGR_PERPLL_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : SDRAM PLL Group - ALT_CLKMGR_SDRPLL
+ * SDRAM PLL Group
+ * 
+ * Contains registers with settings for the SDRAM PLL.
+ * 
+ */
+/*
+ * Register : SDRAM PLL VCO Control Register - vco
+ * 
+ * Contains settings that control the SDRAM PLL VCO. The VCO output frequency is
+ * the input frequency multiplied by the numerator (M+1) and divided by the
+ * denominator (N+1).
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                    
+ * :--------|:-------|:------|:--------------------------------
+ *  [0]     | RW     | 0x1   | BG PWRDN                       
+ *  [1]     | RW     | 0x0   | Enable                         
+ *  [2]     | RW     | 0x1   | Power down                     
+ *  [15:3]  | RW     | 0x1   | Numerator (M)                  
+ *  [21:16] | RW     | 0x1   | Denominator (N)                
+ *  [23:22] | RW     | 0x0   | Clock Source                   
+ *  [24]    | RW     | 0x0   | SDRAM All Output Counter Reset 
+ *  [30:25] | RW     | 0x0   | Output Counter Reset           
+ *  [31]    | RW     | 0x1   | External Regulator Input Select
+ * 
+ */
+/*
+ * Field : BG PWRDN - bgpwrdn
+ * 
+ * If '1', powers down bandgap. If '0', bandgap is not power down.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB        0
+/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN field value from a register. */
+#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Enable - en
+ * 
+ * If '1', VCO is enabled. If '0', VCO is in reset.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_EN_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_EN_MSB        1
+/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_EN_RESET      0x0
+/* Extracts the ALT_CLKMGR_SDRPLL_VCO_EN field value from a register. */
+#define ALT_CLKMGR_SDRPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CLKMGR_SDRPLL_VCO_EN register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : Power down - pwrdn
+ * 
+ * If '1', power down analog circuitry. If '0', analog circuitry not powered down.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB        2
+/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_VCO_PWRDN field value from a register. */
+#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : Numerator (M) - numer
+ * 
+ * Numerator in VCO output frequency equation. For incremental frequency change, if
+ * the new value lead to less than 20% of the frequency change, this value can be
+ * changed without resetting the PLL. The Numerator and Denominator can not be
+ * changed at the same time for incremental frequency changed.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB        15
+/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH      13
+/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK    0x0000fff8
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK    0xffff0007
+/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_VCO_NUMER field value from a register. */
+#define ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
+/* Produces a ALT_CLKMGR_SDRPLL_VCO_NUMER register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
+
+/*
+ * Field : Denominator (N) - denom
+ * 
+ * Denominator in VCO output frequency equation. For incremental frequency change,
+ * if the new value lead to less than 20% of the frequency change, this value can
+ * be changed without resetting the PLL. The Numerator and Denominator can not be
+ * changed at the same time for incremental frequency changed.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB        21
+/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH      6
+/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK    0x003f0000
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK    0xffc0ffff
+/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_VCO_DENOM field value from a register. */
+#define ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
+/* Produces a ALT_CLKMGR_SDRPLL_VCO_DENOM register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
+
+/*
+ * Field : Clock Source - ssrc
+ * 
+ * Controls the VCO input clock source. The PLL must by bypassed to eosc1_clk
+ * before changing this field.
+ * 
+ * Qsys and user documenation refer to f2s_sdram_ref_clk as f2h_sdram_ref_clk.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                       | Value | Description      
+ * :-------------------------------------------|:------|:------------------
+ *  ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1         | 0x0   | eosc1_clk        
+ *  ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2         | 0x1   | eosc2_clk        
+ *  ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF | 0x2   | f2s_sdram_ref_clk
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
+ * 
+ * eosc1_clk
+ */
+#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1          0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
+ * 
+ * eosc2_clk
+ */
+#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2          0x1
+/*
+ * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
+ * 
+ * f2s_sdram_ref_clk
+ */
+#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF  0x2
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB        22
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB        23
+/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH      2
+/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK    0x00c00000
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK    0xff3fffff
+/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET      0x0
+/* Extracts the ALT_CLKMGR_SDRPLL_VCO_SSRC field value from a register. */
+#define ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(value) (((value) & 0x00c00000) >> 22)
+/* Produces a ALT_CLKMGR_SDRPLL_VCO_SSRC register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(value) (((value) << 22) & 0x00c00000)
+
+/*
+ * Field : SDRAM All Output Counter Reset - outresetall
+ * 
+ * Before releasing Bypass, All Output Counter Reset must be set and cleared by
+ * software for correct clock operation.
+ * 
+ * If '1', Reset phase multiplexer and output counter state. So that after the
+ * assertion all the clocks output are start from rising edge align.
+ * 
+ * If '0', phase multiplexer and output counter state not reset and no change to
+ * the phase of the clock outputs.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB        24
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB        24
+/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK    0x01000000
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK    0xfeffffff
+/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET      0x0
+/* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL field value from a register. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
+/* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
+
+/*
+ * Field : Output Counter Reset - outreset
+ * 
+ * Resets the individual PLL output counter.
+ * 
+ * For software to change the PLL output counter without producing glitches on the
+ * respective clock, SW must set the VCO register respective Output Counter Reset
+ * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
+ * the Output Counter Reset Ack Status Register. Software then writes the
+ * appropriate counter register, and then clears the respective VCO register Output
+ * Counter Reset bit.
+ * 
+ * LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
+ * 
+ * If set to '1', reset output divider, no clock output from counter.
+ * 
+ * If set to '0', counter is not reset.
+ * 
+ * The reset value of this bit is applied on a cold reset; warm reset has no affect
+ * on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB        25
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB        30
+/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH      6
+/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK    0x7e000000
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK    0x81ffffff
+/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET      0x0
+/* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRST field value from a register. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
+/* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
+
+/*
+ * Field : External Regulator Input Select - regextsel
+ * 
+ * If set to '1', the external regulator is selected for the PLL.
+ * 
+ * If set to '0', the internal regulator is slected.
+ * 
+ * It is strongly recommended to select the external regulator while the PLL is not
+ * enabled (in reset), and  then disable the external regulater once the PLL
+ * becomes enabled.  Software should simulateously update the 'Enable' bit and the
+ * 'External Regulator Input Select' in the same write access to the VCO register.
+ * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be
+ * set, and vice versa.
+ * 
+ * The reset value of this bit is applied on a cold reset; warm reset has no affect
+ * on this bit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB        31
+/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK    0x80000000
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */
+#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
+#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL field value from a register. */
+#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_SDRPLL_VCO.
+ */
+struct ALT_CLKMGR_SDRPLL_VCO_s
+{
+    uint32_t  bgpwrdn     :  1;  /* BG PWRDN */
+    uint32_t  en          :  1;  /* Enable */
+    uint32_t  pwrdn       :  1;  /* Power down */
+    uint32_t  numer       : 13;  /* Numerator (M) */
+    uint32_t  denom       :  6;  /* Denominator (N) */
+    uint32_t  ssrc        :  2;  /* Clock Source */
+    uint32_t  outresetall :  1;  /* SDRAM All Output Counter Reset */
+    uint32_t  outreset    :  6;  /* Output Counter Reset */
+    uint32_t  regextsel   :  1;  /* External Regulator Input Select */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_SDRPLL_VCO. */
+typedef volatile struct ALT_CLKMGR_SDRPLL_VCO_s  ALT_CLKMGR_SDRPLL_VCO_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_SDRPLL_VCO register from the beginning of the component. */
+#define ALT_CLKMGR_SDRPLL_VCO_OFST        0x0
+
+/*
+ * Register : SDRAM PLL VCO Advanced Control Register - ctrl
+ * 
+ * Contains VCO control signals and other PLL control signals need to be
+ * controllable through register.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                  
+ * :--------|:-------|:------|:------------------------------
+ *  [0]     | RW     | 0x0   | Loop Bandwidth Adjust Enabled
+ *  [12:1]  | RW     | 0x1   | Loop Bandwidth Adjust        
+ *  [13]    | RW     | 0x0   | Fast Locking Enable          
+ *  [14]    | RW     | 0x1   | Saturation Enable            
+ *  [31:15] | ???    | 0x0   | *UNDEFINED*                  
+ * 
+ */
+/*
+ * Field : Loop Bandwidth Adjust Enabled - bwadjen
+ * 
+ * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth
+ * Adjust field.
+ * 
+ * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2
+ * value of the VCO Control Register.  The M divided by 2 is the upper 12 bits
+ * (12:1) of the M field in the VCO register.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_MSB        0
+/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_RESET      0x0
+/* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJEN field value from a register. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Loop Bandwidth Adjust - bwadj
+ * 
+ * Provides Loop Bandwidth Adjust value.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_MSB        12
+/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_WIDTH      12
+/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET_MSK    0x00001ffe
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_CLR_MSK    0xffffe001
+/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJ field value from a register. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
+/* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
+
+/*
+ * Field : Fast Locking Enable - fasten
+ * 
+ * Enables fast locking circuit.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_LSB        13
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_MSB        13
+/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */
+#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET_MSK    0x00002000
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */
+#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_CLR_MSK    0xffffdfff
+/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_RESET      0x0
+/* Extracts the ALT_CLKMGR_SDRPLL_CTL_FASTEN field value from a register. */
+#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
+/* Produces a ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET(value) (((value) << 13) & 0x00002000)
+
+/*
+ * Field : Saturation Enable - saten
+ * 
+ * Enables saturation behavior.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_SATEN_LSB        14
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_SATEN_MSB        14
+/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_SATEN_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */
+#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET_MSK    0x00004000
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */
+#define ALT_CLKMGR_SDRPLL_CTL_SATEN_CLR_MSK    0xffffbfff
+/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
+#define ALT_CLKMGR_SDRPLL_CTL_SATEN_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_CTL_SATEN field value from a register. */
+#define ALT_CLKMGR_SDRPLL_CTL_SATEN_GET(value) (((value) & 0x00004000) >> 14)
+/* Produces a ALT_CLKMGR_SDRPLL_CTL_SATEN register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET(value) (((value) << 14) & 0x00004000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_SDRPLL_CTL.
+ */
+struct ALT_CLKMGR_SDRPLL_CTL_s
+{
+    uint32_t  bwadjen :  1;  /* Loop Bandwidth Adjust Enabled */
+    uint32_t  bwadj   : 12;  /* Loop Bandwidth Adjust */
+    uint32_t  fasten  :  1;  /* Fast Locking Enable */
+    uint32_t  saten   :  1;  /* Saturation Enable */
+    uint32_t          : 17;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_SDRPLL_CTL. */
+typedef volatile struct ALT_CLKMGR_SDRPLL_CTL_s  ALT_CLKMGR_SDRPLL_CTL_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_SDRPLL_CTL register from the beginning of the component. */
+#define ALT_CLKMGR_SDRPLL_CTL_OFST        0x4
+
+/*
+ * Register : SDRAM PLL C0 Control Register for Clock ddr_dqs_clk - ddrdqsclk
+ * 
+ * Contains settings that control clock ddr_dqs_clk generated from the C0 output of
+ * the SDRAM PLL.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description
+ * :--------|:-------|:------|:------------
+ *  [8:0]   | RW     | 0x1   | Counter    
+ *  [20:9]  | RW     | 0x0   | Phase Shift
+ *  [31:21] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT field value from a register. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+/*
+ * Field : Phase Shift - phase
+ * 
+ * Increment the phase of the VCO output by the value in this field multiplied by
+ * 45 degrees. The accumulated phase shift is the total shifted amount since the
+ * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
+ * control register. In order to guarantee the phase shift to a known value, 'SDRAM
+ * clocks output phase align' bit should be asserted before programming this field.
+ * 
+ * This field is only writeable by SW when it is zero.  HW updates this field in
+ * real time as the phase adjustment is being made.   SW may poll this field
+ * waiting for zero indicating the phase adjustment has completed by HW.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_MSB        20
+/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_WIDTH      12
+/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK    0x001ffe00
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_CLR_MSK    0xffe001ff
+/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_RESET      0x0
+/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE field value from a register. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
+/* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK.
+ */
+struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s
+{
+    uint32_t  cnt   :  9;  /* Counter */
+    uint32_t  phase : 12;  /* Phase Shift */
+    uint32_t        : 11;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK. */
+typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s  ALT_CLKMGR_SDRPLL_DDRDQSCLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQSCLK register from the beginning of the component. */
+#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST        0x8
+
+/*
+ * Register : SDRAM PLL C1 Control Register for Clock ddr_2x_dqs_clk - ddr2xdqsclk
+ * 
+ * Contains settings that control clock ddr_2x_dqs_clk generated from the C1 output
+ * of the SDRAM PLL.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description
+ * :--------|:-------|:------|:------------
+ *  [8:0]   | RW     | 0x1   | Counter    
+ *  [20:9]  | RW     | 0x0   | Phase Shift
+ *  [31:21] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT field value from a register. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+/*
+ * Field : Phase Shift - phase
+ * 
+ * Increment the phase of the VCO output by the value in this field multiplied by
+ * 45 degrees. The accumulated phase shift is the total shifted amount since the
+ * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
+ * control register. In order to guarantee the phase shift to a known value, 'SDRAM
+ * clocks output phase align' bit should be asserted before programming this field.
+ * 
+ * This field is only writeable by SW when it is zero.  HW updates this field in
+ * real time as the phase adjustment is being made.   SW may poll this field
+ * waiting for zero indicating the phase adjustment has completed by HW.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_MSB        20
+/* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_WIDTH      12
+/* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK    0x001ffe00
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_CLR_MSK    0xffe001ff
+/* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_RESET      0x0
+/* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE field value from a register. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
+/* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK.
+ */
+struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s
+{
+    uint32_t  cnt   :  9;  /* Counter */
+    uint32_t  phase : 12;  /* Phase Shift */
+    uint32_t        : 11;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK. */
+typedef volatile struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s  ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK register from the beginning of the component. */
+#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST        0xc
+
+/*
+ * Register : SDRAM PLL C2 Control Register for Clock ddr_dq_clk - ddrdqclk
+ * 
+ * Contains settings that control clock ddr_dq_clk generated from the C2 output of
+ * the SDRAM PLL.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description
+ * :--------|:-------|:------|:------------
+ *  [8:0]   | RW     | 0x1   | Counter    
+ *  [20:9]  | RW     | 0x0   | Phase Shift
+ *  [31:21] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT field value from a register. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+/*
+ * Field : Phase Shift - phase
+ * 
+ * Increment the phase of the VCO output by the value in this field multiplied by
+ * 45 degrees. The accumulated phase shift is the total shifted amount since the
+ * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
+ * control register. In order to guarantee the phase shift to a known value, 'SDRAM
+ * clocks output phase align' bit should be asserted before programming this field.
+ * 
+ * This field is only writeable by SW when it is zero.  HW updates this field in
+ * real time as the phase adjustment is being made.   SW may poll this field
+ * waiting for zero indicating the phase adjustment has completed by HW.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB        20
+/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH      12
+/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK    0x001ffe00
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK    0xffe001ff
+/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET      0x0
+/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE field value from a register. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
+/* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK.
+ */
+struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s
+{
+    uint32_t  cnt   :  9;  /* Counter */
+    uint32_t  phase : 12;  /* Phase Shift */
+    uint32_t        : 11;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK. */
+typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s  ALT_CLKMGR_SDRPLL_DDRDQCLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQCLK register from the beginning of the component. */
+#define ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST        0x10
+
+/*
+ * Register : SDRAM PLL C5 Control Register for Clock s2f_user2_clk - s2fuser2clk
+ * 
+ * Contains settings that control clock s2f_user2_clk generated from the C5 output
+ * of the SDRAM PLL.
+ * 
+ * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description
+ * :--------|:-------|:------|:------------
+ *  [8:0]   | RW     | 0x1   | Counter    
+ *  [20:9]  | RW     | 0x0   | Phase Shift
+ *  [31:21] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Counter - cnt
+ * 
+ * Divides the VCO frequency by the value+1 in this field.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_MSB        8
+/* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_WIDTH      9
+/* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK    0x000001ff
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_CLR_MSK    0xfffffe00
+/* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT field value from a register. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
+/* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
+
+/*
+ * Field : Phase Shift - phase
+ * 
+ * Increment the phase of the VCO output by the value in this field multiplied by
+ * 45 degrees. The accumulated phase shift is the total shifted amount since the
+ * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
+ * control register. In order to guarantee the phase shift to a known value, 'SDRAM
+ * clocks output phase align' bit should be asserted before programming this field.
+ * 
+ * This field is only writeable by SW when it is zero.  HW updates this field in
+ * real time as the phase adjustment is being made.   SW may poll this field
+ * waiting for zero indicating the phase adjustment has completed by HW.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_MSB        20
+/* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_WIDTH      12
+/* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK    0x001ffe00
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_CLR_MSK    0xffe001ff
+/* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_RESET      0x0
+/* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE field value from a register. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
+/* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK.
+ */
+struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s
+{
+    uint32_t  cnt   :  9;  /* Counter */
+    uint32_t  phase : 12;  /* Phase Shift */
+    uint32_t        : 11;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK. */
+typedef volatile struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s  ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK register from the beginning of the component. */
+#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST        0x14
+
+/*
+ * Register : Enable Register - en
+ * 
+ * Contains fields that control the SDRAM Clock Group enables generated from the
+ * SDRAM PLL clock outputs.
+ * 
+ * 1: The clock is enabled.
+ * 
+ * 0: The clock is disabled.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description          
+ * :-------|:-------|:------|:----------------------
+ *  [0]    | RW     | 0x1   | ddr_dqs_clk Enable   
+ *  [1]    | RW     | 0x1   | ddr_2x_dqs_clk Enable
+ *  [2]    | RW     | 0x1   | ddr_dq_clk Enable    
+ *  [3]    | RW     | 0x1   | s2f_user2_clk Enable 
+ *  [31:4] | ???    | 0x0   | *UNDEFINED*          
+ * 
+ */
+/*
+ * Field : ddr_dqs_clk Enable - ddrdqsclk
+ * 
+ * Enables clock ddr_dqs_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB        0
+/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK field value from a register. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : ddr_2x_dqs_clk Enable - ddr2xdqsclk
+ * 
+ * Enables clock ddr_2x_dqs_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB        1
+/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */
+#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */
+#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK field value from a register. */
+#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : ddr_dq_clk Enable - ddrdqclk
+ * 
+ * Enables clock ddr_dq_clk output
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB        2
+/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK field value from a register. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : s2f_user2_clk Enable - s2fuser2clk
+ * 
+ * Enables clock s2f_user2_clk output.
+ * 
+ * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB        3
+/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH      1
+/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */
+#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */
+#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
+#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET      0x1
+/* Extracts the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK field value from a register. */
+#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET(value) (((value) << 3) & 0x00000008)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_SDRPLL_EN.
+ */
+struct ALT_CLKMGR_SDRPLL_EN_s
+{
+    uint32_t  ddrdqsclk   :  1;  /* ddr_dqs_clk Enable */
+    uint32_t  ddr2xdqsclk :  1;  /* ddr_2x_dqs_clk Enable */
+    uint32_t  ddrdqclk    :  1;  /* ddr_dq_clk Enable */
+    uint32_t  s2fuser2clk :  1;  /* s2f_user2_clk Enable */
+    uint32_t              : 28;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_SDRPLL_EN. */
+typedef volatile struct ALT_CLKMGR_SDRPLL_EN_s  ALT_CLKMGR_SDRPLL_EN_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_SDRPLL_EN register from the beginning of the component. */
+#define ALT_CLKMGR_SDRPLL_EN_OFST        0x18
+
+/*
+ * Register : SDRAM PLL Output Counter Reset Ack Status Register - stat
+ * 
+ * Contains Output Clock Counter Reset acknowledge status.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                     
+ * :-------|:-------|:------|:---------------------------------
+ *  [5:0]  | R      | 0x0   | Output Counter Reset Acknowledge
+ *  [31:6] | ???    | 0x0   | *UNDEFINED*                     
+ * 
+ */
+/*
+ * Field : Output Counter Reset Acknowledge - outresetack
+ * 
+ * These read only bits per PLL output indicate that the PLL has received the
+ * Output Reset Counter request and has gracefully stopped the respective PLL
+ * output clock.
+ * 
+ * For software to change the PLL output counter without producing glitches on the
+ * respective clock, SW must set the VCO register respective Output Counter Reset
+ * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
+ * the Output Counter Reset Ack Status Register. Software then writes the
+ * appropriate counter register, and then clears the respective VCO register Output
+ * Counter Reset bit.
+ * 
+ * The reset value of this bit is applied on a cold reset; warm reset has no affect
+ * on this bit.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                       | Value | Description                         
+ * :-------------------------------------------|:------|:-------------------------------------
+ *  ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE    | 0x0   | Idle                                
+ *  ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1   | Output Counter Acknowledge received.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK
+ * 
+ * Idle
+ */
+#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE     0x0
+/*
+ * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK
+ * 
+ * Output Counter Acknowledge received.
+ */
+#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_MSB        5
+/* The width in bits of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_WIDTH      6
+/* The mask used to set the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */
+#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET_MSK    0x0000003f
+/* The mask used to clear the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */
+#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_CLR_MSK    0xffffffc0
+/* The reset value of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
+#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_RESET      0x0
+/* Extracts the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK field value from a register. */
+#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
+/* Produces a ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value suitable for setting the register. */
+#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CLKMGR_SDRPLL_STAT.
+ */
+struct ALT_CLKMGR_SDRPLL_STAT_s
+{
+    const uint32_t  outresetack :  6;  /* Output Counter Reset Acknowledge */
+    uint32_t                    : 26;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CLKMGR_SDRPLL_STAT. */
+typedef volatile struct ALT_CLKMGR_SDRPLL_STAT_s  ALT_CLKMGR_SDRPLL_STAT_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CLKMGR_SDRPLL_STAT register from the beginning of the component. */
+#define ALT_CLKMGR_SDRPLL_STAT_OFST        0x1c
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_CLKMGR_SDRPLL.
+ */
+struct ALT_CLKMGR_SDRPLL_s
+{
+    volatile ALT_CLKMGR_SDRPLL_VCO_t          vco;          /* ALT_CLKMGR_SDRPLL_VCO */
+    volatile ALT_CLKMGR_SDRPLL_CTL_t          ctrl;         /* ALT_CLKMGR_SDRPLL_CTL */
+    volatile ALT_CLKMGR_SDRPLL_DDRDQSCLK_t    ddrdqsclk;    /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */
+    volatile ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t  ddr2xdqsclk;  /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */
+    volatile ALT_CLKMGR_SDRPLL_DDRDQCLK_t     ddrdqclk;     /* ALT_CLKMGR_SDRPLL_DDRDQCLK */
+    volatile ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t  s2fuser2clk;  /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */
+    volatile ALT_CLKMGR_SDRPLL_EN_t           en;           /* ALT_CLKMGR_SDRPLL_EN */
+    volatile ALT_CLKMGR_SDRPLL_STAT_t         stat;         /* ALT_CLKMGR_SDRPLL_STAT */
+};
+
+/* The typedef declaration for register group ALT_CLKMGR_SDRPLL. */
+typedef volatile struct ALT_CLKMGR_SDRPLL_s  ALT_CLKMGR_SDRPLL_t;
+/* The struct declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */
+struct ALT_CLKMGR_SDRPLL_raw_s
+{
+    volatile uint32_t  vco;          /* ALT_CLKMGR_SDRPLL_VCO */
+    volatile uint32_t  ctrl;         /* ALT_CLKMGR_SDRPLL_CTL */
+    volatile uint32_t  ddrdqsclk;    /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */
+    volatile uint32_t  ddr2xdqsclk;  /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */
+    volatile uint32_t  ddrdqclk;     /* ALT_CLKMGR_SDRPLL_DDRDQCLK */
+    volatile uint32_t  s2fuser2clk;  /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */
+    volatile uint32_t  en;           /* ALT_CLKMGR_SDRPLL_EN */
+    volatile uint32_t  stat;         /* ALT_CLKMGR_SDRPLL_STAT */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */
+typedef volatile struct ALT_CLKMGR_SDRPLL_raw_s  ALT_CLKMGR_SDRPLL_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_CLKMGR.
+ */
+struct ALT_CLKMGR_s
+{
+    volatile ALT_CLKMGR_CTL_t      ctrl;                 /* ALT_CLKMGR_CTL */
+    volatile ALT_CLKMGR_BYPASS_t   bypass;               /* ALT_CLKMGR_BYPASS */
+    volatile ALT_CLKMGR_INTER_t    inter;                /* ALT_CLKMGR_INTER */
+    volatile ALT_CLKMGR_INTREN_t   intren;               /* ALT_CLKMGR_INTREN */
+    volatile ALT_CLKMGR_DBCTL_t    dbctrl;               /* ALT_CLKMGR_DBCTL */
+    volatile ALT_CLKMGR_STAT_t     stat;                 /* ALT_CLKMGR_STAT */
+    volatile uint32_t              _pad_0x18_0x3f[10];   /* *UNDEFINED* */
+    volatile ALT_CLKMGR_MAINPLL_t  mainpllgrp;           /* ALT_CLKMGR_MAINPLL */
+    volatile ALT_CLKMGR_PERPLL_t   perpllgrp;            /* ALT_CLKMGR_PERPLL */
+    volatile ALT_CLKMGR_SDRPLL_t   sdrpllgrp;            /* ALT_CLKMGR_SDRPLL */
+    volatile uint32_t              _pad_0xe0_0x200[72];  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register group ALT_CLKMGR. */
+typedef volatile struct ALT_CLKMGR_s  ALT_CLKMGR_t;
+/* The struct declaration for the raw register contents of register group ALT_CLKMGR. */
+struct ALT_CLKMGR_raw_s
+{
+    volatile uint32_t                  ctrl;                 /* ALT_CLKMGR_CTL */
+    volatile uint32_t                  bypass;               /* ALT_CLKMGR_BYPASS */
+    volatile uint32_t                  inter;                /* ALT_CLKMGR_INTER */
+    volatile uint32_t                  intren;               /* ALT_CLKMGR_INTREN */
+    volatile uint32_t                  dbctrl;               /* ALT_CLKMGR_DBCTL */
+    volatile uint32_t                  stat;                 /* ALT_CLKMGR_STAT */
+    volatile uint32_t                  _pad_0x18_0x3f[10];   /* *UNDEFINED* */
+    volatile ALT_CLKMGR_MAINPLL_raw_t  mainpllgrp;           /* ALT_CLKMGR_MAINPLL */
+    volatile ALT_CLKMGR_PERPLL_raw_t   perpllgrp;            /* ALT_CLKMGR_PERPLL */
+    volatile ALT_CLKMGR_SDRPLL_raw_t   sdrpllgrp;            /* ALT_CLKMGR_SDRPLL */
+    volatile uint32_t                  _pad_0xe0_0x200[72];  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_CLKMGR. */
+typedef volatile struct ALT_CLKMGR_raw_s  ALT_CLKMGR_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALTERA_ALT_CLKMGR_H__ */
+
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_gpio.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_gpio.h
new file mode 100644
index 0000000..8bc4640
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_gpio.h
@@ -0,0 +1,1991 @@
+/*******************************************************************************
+*                                                                              *
+* Copyright 2013 Altera Corporation. All Rights Reserved.                      *
+*                                                                              *
+* Redistribution and use in source and binary forms, with or without           *
+* modification, are permitted provided that the following conditions are met:  *
+*                                                                              *
+* 1. Redistributions of source code must retain the above copyright notice,    *
+*    this list of conditions and the following disclaimer.                     *
+*                                                                              *
+* 2. Redistributions in binary form must reproduce the above copyright notice, *
+*    this list of conditions and the following disclaimer in the documentation *
+*    and/or other materials provided with the distribution.                    *
+*                                                                              *
+* 3. The name of the author may not be used to endorse or promote products     *
+*    derived from this software without specific prior written permission.     *
+*                                                                              *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO  *
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,       *
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;  *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,     *
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR      *
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF       *
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                   *
+*                                                                              *
+*******************************************************************************/
+
+/* Altera - ALT_GPIO */
+
+#ifndef __ALTERA_ALT_GPIO_H__
+#define __ALTERA_ALT_GPIO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*
+ * Component : GPIO Module - ALT_GPIO
+ * GPIO Module
+ * 
+ * Registers in the GPIO module
+ * 
+ */
+/*
+ * Register : Port A Data Register - gpio_swporta_dr
+ * 
+ * This GPIO Data register is used to input or output data
+ * 
+ * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description
+ * :--------|:-------|:------|:------------
+ *  [28:0]  | RW     | 0x0   | Port A Data
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Port A Data - gpio_swporta_dr
+ * 
+ * Values written to this register are output on the I/O signals of the GPIO Data
+ * Register, if the corresponding data direction bits for GPIO Data Direction Field
+ * are set to Output mode. The value read back is equal to the last value written
+ * to this register.
+ * 
+ * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
+#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
+#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_MSB        28
+/* The width in bits of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
+#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_WIDTH      29
+/* The mask used to set the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
+#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET_MSK    0x1fffffff
+/* The mask used to clear the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
+#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_CLR_MSK    0xe0000000
+/* The reset value of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
+#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_RESET      0x0
+/* Extracts the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR field value from a register. */
+#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_GET(value) (((value) & 0x1fffffff) >> 0)
+/* Produces a ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value suitable for setting the register. */
+#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET(value) (((value) << 0) & 0x1fffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_SWPORTA_DR.
+ */
+struct ALT_GPIO_SWPORTA_DR_s
+{
+    uint32_t  gpio_swporta_dr : 29;  /* Port A Data */
+    uint32_t                  :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_SWPORTA_DR. */
+typedef volatile struct ALT_GPIO_SWPORTA_DR_s  ALT_GPIO_SWPORTA_DR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_SWPORTA_DR register from the beginning of the component. */
+#define ALT_GPIO_SWPORTA_DR_OFST        0x0
+/* The address of the ALT_GPIO_SWPORTA_DR register. */
+#define ALT_GPIO_SWPORTA_DR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DR_OFST))
+
+/*
+ * Register : Port A Data Direction Register - gpio_swporta_ddr
+ * 
+ * This register establishes the direction of each corresponding GPIO Data Field
+ * Bit.
+ * 
+ * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                
+ * :--------|:-------|:------|:----------------------------
+ *  [28:0]  | RW     | 0x0   | Port A Data Direction Field
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*                
+ * 
+ */
+/*
+ * Field : Port A Data Direction Field - gpio_swporta_ddr
+ * 
+ * Values written to this register independently control the direction of the
+ * corresponding data bit in the Port A Data Register.
+ * 
+ * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description     
+ * :--------------------------------------------|:------|:-----------------
+ *  ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN  | 0x0   | Input Direction 
+ *  ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT | 0x1   | Output Direction
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
+ * 
+ * Input Direction
+ */
+#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN  0x0
+/*
+ * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
+ * 
+ * Output Direction
+ */
+#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
+#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
+#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_MSB        28
+/* The width in bits of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
+#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_WIDTH      29
+/* The mask used to set the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
+#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET_MSK    0x1fffffff
+/* The mask used to clear the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
+#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_CLR_MSK    0xe0000000
+/* The reset value of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
+#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_RESET      0x0
+/* Extracts the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR field value from a register. */
+#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_GET(value) (((value) & 0x1fffffff) >> 0)
+/* Produces a ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value suitable for setting the register. */
+#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET(value) (((value) << 0) & 0x1fffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_SWPORTA_DDR.
+ */
+struct ALT_GPIO_SWPORTA_DDR_s
+{
+    uint32_t  gpio_swporta_ddr : 29;  /* Port A Data Direction Field */
+    uint32_t                   :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_SWPORTA_DDR. */
+typedef volatile struct ALT_GPIO_SWPORTA_DDR_s  ALT_GPIO_SWPORTA_DDR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_SWPORTA_DDR register from the beginning of the component. */
+#define ALT_GPIO_SWPORTA_DDR_OFST        0x4
+/* The address of the ALT_GPIO_SWPORTA_DDR register. */
+#define ALT_GPIO_SWPORTA_DDR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DDR_OFST))
+
+/*
+ * Register : Interrupt Enable Register - gpio_inten
+ * 
+ * The Interrupt enable register allows interrupts for each bit of the Port A data
+ * register.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description           
+ * :--------|:-------|:------|:-----------------------
+ *  [28:0]  | RW     | 0x0   | Interrupt Enable Field
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*           
+ * 
+ */
+/*
+ * Field : Interrupt Enable Field - gpio_inten
+ * 
+ * Allows each bit of Port A Data Register to be configured for interrupt
+ * capability. Interrupts are disabled on the corresponding bits of Port A Data
+ * Register if the corresponding data direction register is set to Output.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                            | Value | Description                
+ * :--------------------------------|:------|:----------------------------
+ *  ALT_GPIO_INTEN_GPIO_INTEN_E_DIS | 0x0   | Disable Interrupt on Port A
+ *  ALT_GPIO_INTEN_GPIO_INTEN_E_EN  | 0x1   | Enable Interrupt on Port A 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN
+ * 
+ * Disable Interrupt on Port A
+ */
+#define ALT_GPIO_INTEN_GPIO_INTEN_E_DIS 0x0
+/*
+ * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN
+ * 
+ * Enable Interrupt on Port A
+ */
+#define ALT_GPIO_INTEN_GPIO_INTEN_E_EN  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
+#define ALT_GPIO_INTEN_GPIO_INTEN_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
+#define ALT_GPIO_INTEN_GPIO_INTEN_MSB        28
+/* The width in bits of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
+#define ALT_GPIO_INTEN_GPIO_INTEN_WIDTH      29
+/* The mask used to set the ALT_GPIO_INTEN_GPIO_INTEN register field value. */
+#define ALT_GPIO_INTEN_GPIO_INTEN_SET_MSK    0x1fffffff
+/* The mask used to clear the ALT_GPIO_INTEN_GPIO_INTEN register field value. */
+#define ALT_GPIO_INTEN_GPIO_INTEN_CLR_MSK    0xe0000000
+/* The reset value of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
+#define ALT_GPIO_INTEN_GPIO_INTEN_RESET      0x0
+/* Extracts the ALT_GPIO_INTEN_GPIO_INTEN field value from a register. */
+#define ALT_GPIO_INTEN_GPIO_INTEN_GET(value) (((value) & 0x1fffffff) >> 0)
+/* Produces a ALT_GPIO_INTEN_GPIO_INTEN register field value suitable for setting the register. */
+#define ALT_GPIO_INTEN_GPIO_INTEN_SET(value) (((value) << 0) & 0x1fffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_INTEN.
+ */
+struct ALT_GPIO_INTEN_s
+{
+    uint32_t  gpio_inten : 29;  /* Interrupt Enable Field */
+    uint32_t             :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_INTEN. */
+typedef volatile struct ALT_GPIO_INTEN_s  ALT_GPIO_INTEN_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_INTEN register from the beginning of the component. */
+#define ALT_GPIO_INTEN_OFST        0x30
+/* The address of the ALT_GPIO_INTEN register. */
+#define ALT_GPIO_INTEN_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTEN_OFST))
+
+/*
+ * Register : Interrupt Mask Register - gpio_intmask
+ * 
+ * Controls which pins cause interrupts on Port A Data Register inputs.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description         
+ * :--------|:-------|:------|:---------------------
+ *  [28:0]  | RW     | 0x0   | Interrupt Mask Field
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*         
+ * 
+ */
+/*
+ * Field : Interrupt Mask Field - gpio_intmask
+ * 
+ * Controls whether an interrupt on Port A Data Register can generate an interrupt
+ * to the interrupt controller by not masking it. The unmasked status can be read
+ * as well as the resultant status after masking.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                
+ * :----------------------------------|:------|:----------------------------
+ *  ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS | 0x0   | Interrupt bits are unmasked
+ *  ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN  | 0x1   | Mask Interrupt             
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK
+ * 
+ * Interrupt bits are unmasked
+ */
+#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS   0x0
+/*
+ * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK
+ * 
+ * Mask Interrupt
+ */
+#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
+#define ALT_GPIO_INTMSK_GPIO_INTMSK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
+#define ALT_GPIO_INTMSK_GPIO_INTMSK_MSB        28
+/* The width in bits of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
+#define ALT_GPIO_INTMSK_GPIO_INTMSK_WIDTH      29
+/* The mask used to set the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */
+#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET_MSK    0x1fffffff
+/* The mask used to clear the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */
+#define ALT_GPIO_INTMSK_GPIO_INTMSK_CLR_MSK    0xe0000000
+/* The reset value of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
+#define ALT_GPIO_INTMSK_GPIO_INTMSK_RESET      0x0
+/* Extracts the ALT_GPIO_INTMSK_GPIO_INTMSK field value from a register. */
+#define ALT_GPIO_INTMSK_GPIO_INTMSK_GET(value) (((value) & 0x1fffffff) >> 0)
+/* Produces a ALT_GPIO_INTMSK_GPIO_INTMSK register field value suitable for setting the register. */
+#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET(value) (((value) << 0) & 0x1fffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_INTMSK.
+ */
+struct ALT_GPIO_INTMSK_s
+{
+    uint32_t  gpio_intmask : 29;  /* Interrupt Mask Field */
+    uint32_t               :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_INTMSK. */
+typedef volatile struct ALT_GPIO_INTMSK_s  ALT_GPIO_INTMSK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_INTMSK register from the beginning of the component. */
+#define ALT_GPIO_INTMSK_OFST        0x34
+/* The address of the ALT_GPIO_INTMSK register. */
+#define ALT_GPIO_INTMSK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTMSK_OFST))
+
+/*
+ * Register : Interrupt Level Register - gpio_inttype_level
+ * 
+ * The interrupt level register defines the type of interrupt (edge or level).
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description          
+ * :--------|:-------|:------|:----------------------
+ *  [28:0]  | RW     | 0x0   | Interrupt Level Field
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*          
+ * 
+ */
+/*
+ * Field : Interrupt Level Field - gpio_inttype_level
+ * 
+ * This field controls the type of interrupt that can occur on the Port A Data
+ * Register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                              | Value | Description    
+ * :--------------------------------------------------|:------|:----------------
+ *  ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL | 0x0   | Level-sensitive
+ *  ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE  | 0x1   | Edge-sensitive 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
+ * 
+ * Level-sensitive
+ */
+#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL   0x0
+/*
+ * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
+ * 
+ * Edge-sensitive
+ */
+#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
+#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
+#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_MSB        28
+/* The width in bits of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
+#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_WIDTH      29
+/* The mask used to set the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
+#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET_MSK    0x1fffffff
+/* The mask used to clear the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
+#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_CLR_MSK    0xe0000000
+/* The reset value of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
+#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_RESET      0x0
+/* Extracts the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL field value from a register. */
+#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_GET(value) (((value) & 0x1fffffff) >> 0)
+/* Produces a ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value suitable for setting the register. */
+#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET(value) (((value) << 0) & 0x1fffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_INTTYPE_LEVEL.
+ */
+struct ALT_GPIO_INTTYPE_LEVEL_s
+{
+    uint32_t  gpio_inttype_level : 29;  /* Interrupt Level Field */
+    uint32_t                     :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_INTTYPE_LEVEL. */
+typedef volatile struct ALT_GPIO_INTTYPE_LEVEL_s  ALT_GPIO_INTTYPE_LEVEL_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_INTTYPE_LEVEL register from the beginning of the component. */
+#define ALT_GPIO_INTTYPE_LEVEL_OFST        0x38
+/* The address of the ALT_GPIO_INTTYPE_LEVEL register. */
+#define ALT_GPIO_INTTYPE_LEVEL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTTYPE_LEVEL_OFST))
+
+/*
+ * Register : Interrupt Polarity Register - gpio_int_polarity
+ * 
+ * Controls the Polarity of Interrupts that can occur on inputs of Port A Data
+ * Register
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description           
+ * :--------|:-------|:------|:-----------------------
+ *  [28:0]  | RW     | 0x0   | Polarity Control Field
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*           
+ * 
+ */
+/*
+ * Field : Polarity Control Field - gpio_int_polarity
+ * 
+ * Controls the polarity of edge or level sensitivity that can occur on input of
+ * Port A Data Register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                    | Value | Description
+ * :----------------------------------------|:------|:------------
+ *  ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW  | 0x0   | Active low 
+ *  ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH | 0x1   | Active high
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL
+ * 
+ * Active low
+ */
+#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW  0x0
+/*
+ * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL
+ * 
+ * Active high
+ */
+#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
+#define ALT_GPIO_INT_POL_GPIO_INT_POL_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
+#define ALT_GPIO_INT_POL_GPIO_INT_POL_MSB        28
+/* The width in bits of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
+#define ALT_GPIO_INT_POL_GPIO_INT_POL_WIDTH      29
+/* The mask used to set the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */
+#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET_MSK    0x1fffffff
+/* The mask used to clear the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */
+#define ALT_GPIO_INT_POL_GPIO_INT_POL_CLR_MSK    0xe0000000
+/* The reset value of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
+#define ALT_GPIO_INT_POL_GPIO_INT_POL_RESET      0x0
+/* Extracts the ALT_GPIO_INT_POL_GPIO_INT_POL field value from a register. */
+#define ALT_GPIO_INT_POL_GPIO_INT_POL_GET(value) (((value) & 0x1fffffff) >> 0)
+/* Produces a ALT_GPIO_INT_POL_GPIO_INT_POL register field value suitable for setting the register. */
+#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET(value) (((value) << 0) & 0x1fffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_INT_POL.
+ */
+struct ALT_GPIO_INT_POL_s
+{
+    uint32_t  gpio_int_polarity : 29;  /* Polarity Control Field */
+    uint32_t                    :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_INT_POL. */
+typedef volatile struct ALT_GPIO_INT_POL_s  ALT_GPIO_INT_POL_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_INT_POL register from the beginning of the component. */
+#define ALT_GPIO_INT_POL_OFST        0x3c
+/* The address of the ALT_GPIO_INT_POL register. */
+#define ALT_GPIO_INT_POL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INT_POL_OFST))
+
+/*
+ * Register : Interrupt Status Register - gpio_intstatus
+ * 
+ * The Interrupt status is reported for all Port A Data Register Bits.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description           
+ * :--------|:-------|:------|:-----------------------
+ *  [28:0]  | RW     | 0x0   | Interrupt Status Field
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*           
+ * 
+ */
+/*
+ * Field : Interrupt Status Field - gpio_intstatus
+ * 
+ * Interrupt status of Port A Data Register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                  | Value | Description
+ * :--------------------------------------|:------|:------------
+ *  ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT | 0x0   | Inactive   
+ *  ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT   | 0x1   | Active     
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT
+ * 
+ * Inactive
+ */
+#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT   0x0
+/*
+ * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT
+ * 
+ * Active
+ */
+#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT     0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
+#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
+#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_MSB        28
+/* The width in bits of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
+#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_WIDTH      29
+/* The mask used to set the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */
+#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET_MSK    0x1fffffff
+/* The mask used to clear the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */
+#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_CLR_MSK    0xe0000000
+/* The reset value of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
+#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_RESET      0x0
+/* Extracts the ALT_GPIO_INTSTAT_GPIO_INTSTAT field value from a register. */
+#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0)
+/* Produces a ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value suitable for setting the register. */
+#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_INTSTAT.
+ */
+struct ALT_GPIO_INTSTAT_s
+{
+    uint32_t  gpio_intstatus : 29;  /* Interrupt Status Field */
+    uint32_t                 :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_INTSTAT. */
+typedef volatile struct ALT_GPIO_INTSTAT_s  ALT_GPIO_INTSTAT_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_INTSTAT register from the beginning of the component. */
+#define ALT_GPIO_INTSTAT_OFST        0x40
+/* The address of the ALT_GPIO_INTSTAT register. */
+#define ALT_GPIO_INTSTAT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTSTAT_OFST))
+
+/*
+ * Register : Raw Interrupt Status Register - gpio_raw_intstatus
+ * 
+ * This is the Raw Interrupt Status Register for Port A Data Register. It is used
+ * with the Interrupt Mask Register to allow interrupts from the Port A Data
+ * Register.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description               
+ * :--------|:-------|:------|:---------------------------
+ *  [28:0]  | RW     | 0x0   | Raw Interrupt Status Field
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*               
+ * 
+ */
+/*
+ * Field : Raw Interrupt Status Field - gpio_raw_intstatus
+ * 
+ * Raw interrupt of status of Port A Data Register (premasking bits)
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                          | Value | Description
+ * :----------------------------------------------|:------|:------------
+ *  ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT | 0x0   | Inactive   
+ *  ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT   | 0x1   | Active     
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT
+ * 
+ * Inactive
+ */
+#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT   0x0
+/*
+ * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT
+ * 
+ * Active
+ */
+#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT     0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
+#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
+#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_MSB        28
+/* The width in bits of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
+#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_WIDTH      29
+/* The mask used to set the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */
+#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET_MSK    0x1fffffff
+/* The mask used to clear the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */
+#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_CLR_MSK    0xe0000000
+/* The reset value of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
+#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_RESET      0x0
+/* Extracts the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT field value from a register. */
+#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0)
+/* Produces a ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value suitable for setting the register. */
+#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_RAW_INTSTAT.
+ */
+struct ALT_GPIO_RAW_INTSTAT_s
+{
+    uint32_t  gpio_raw_intstatus : 29;  /* Raw Interrupt Status Field */
+    uint32_t                     :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_RAW_INTSTAT. */
+typedef volatile struct ALT_GPIO_RAW_INTSTAT_s  ALT_GPIO_RAW_INTSTAT_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_RAW_INTSTAT register from the beginning of the component. */
+#define ALT_GPIO_RAW_INTSTAT_OFST        0x44
+/* The address of the ALT_GPIO_RAW_INTSTAT register. */
+#define ALT_GPIO_RAW_INTSTAT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_RAW_INTSTAT_OFST))
+
+/*
+ * Register : Debounce Enable Register - gpio_debounce
+ * 
+ * Debounces each IO Pin
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                    
+ * :--------|:-------|:------|:--------------------------------
+ *  [28:0]  | RW     | 0x0   | ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*                    
+ * 
+ */
+/*
+ * Field : gpio_debounce
+ * 
+ * Controls whether an external signal that is the source of an interrupt needs to
+ * be debounced to remove any spurious glitches. A signal must be valid for two
+ * periods of an external clock (gpio_db_clk) before it is internally processed.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                  | Value | Description    
+ * :--------------------------------------|:------|:----------------
+ *  ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS | 0x0   | No debounce    
+ *  ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN  | 0x1   | Enable debounce
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
+ * 
+ * No debounce
+ */
+#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS   0x0
+/*
+ * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
+ * 
+ * Enable debounce
+ */
+#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
+#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
+#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_MSB        28
+/* The width in bits of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
+#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_WIDTH      29
+/* The mask used to set the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
+#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET_MSK    0x1fffffff
+/* The mask used to clear the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
+#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_CLR_MSK    0xe0000000
+/* The reset value of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
+#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_RESET      0x0
+/* Extracts the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE field value from a register. */
+#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_GET(value) (((value) & 0x1fffffff) >> 0)
+/* Produces a ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value suitable for setting the register. */
+#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET(value) (((value) << 0) & 0x1fffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_DEBOUNCE.
+ */
+struct ALT_GPIO_DEBOUNCE_s
+{
+    uint32_t  gpio_debounce : 29;  /* ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE */
+    uint32_t                :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_DEBOUNCE. */
+typedef volatile struct ALT_GPIO_DEBOUNCE_s  ALT_GPIO_DEBOUNCE_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_DEBOUNCE register from the beginning of the component. */
+#define ALT_GPIO_DEBOUNCE_OFST        0x48
+/* The address of the ALT_GPIO_DEBOUNCE register. */
+#define ALT_GPIO_DEBOUNCE_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_DEBOUNCE_OFST))
+
+/*
+ * Register : Clear Interrupt Register - gpio_porta_eoi
+ * 
+ * Port A Data Register interrupt handling.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                 
+ * :--------|:-------|:------|:-----------------------------
+ *  [28:0]  | W      | 0x0   | Clears Edge Interrupts Field
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*                 
+ * 
+ */
+/*
+ * Field : Clears Edge Interrupts Field - gpio_porta_eoi
+ * 
+ * Controls the clearing of edge type interrupts from the Port A Data Register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                      | Value | Description       
+ * :------------------------------------------|:------|:-------------------
+ *  ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR | 0x0   | No interrupt clear
+ *  ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR   | 0x1   | Clear interrupt   
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI
+ * 
+ * No interrupt clear
+ */
+#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR   0x0
+/*
+ * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI
+ * 
+ * Clear interrupt
+ */
+#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR     0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
+#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
+#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_MSB        28
+/* The width in bits of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
+#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_WIDTH      29
+/* The mask used to set the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
+#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET_MSK    0x1fffffff
+/* The mask used to clear the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
+#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_CLR_MSK    0xe0000000
+/* The reset value of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
+#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_RESET      0x0
+/* Extracts the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI field value from a register. */
+#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_GET(value) (((value) & 0x1fffffff) >> 0)
+/* Produces a ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value suitable for setting the register. */
+#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET(value) (((value) << 0) & 0x1fffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_PORTA_EOI.
+ */
+struct ALT_GPIO_PORTA_EOI_s
+{
+    uint32_t  gpio_porta_eoi : 29;  /* Clears Edge Interrupts Field */
+    uint32_t                 :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_PORTA_EOI. */
+typedef volatile struct ALT_GPIO_PORTA_EOI_s  ALT_GPIO_PORTA_EOI_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_PORTA_EOI register from the beginning of the component. */
+#define ALT_GPIO_PORTA_EOI_OFST        0x4c
+/* The address of the ALT_GPIO_PORTA_EOI register. */
+#define ALT_GPIO_PORTA_EOI_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_PORTA_EOI_OFST))
+
+/*
+ * Register : External Port A Register - gpio_ext_porta
+ * 
+ * The external port register is used to input data to the metastability flops.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description        
+ * :--------|:-------|:------|:--------------------
+ *  [28:0]  | R      | 0x0   | External Port Field
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*        
+ * 
+ */
+/*
+ * Field : External Port Field - gpio_ext_porta
+ * 
+ * When Port A Data Register is configured as Input, then reading this location
+ * reads the values on the signals. When the data direction of Port A Data Register
+ * is set as Output, reading this location reads Port A Data Register
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
+#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
+#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_MSB        28
+/* The width in bits of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
+#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_WIDTH      29
+/* The mask used to set the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
+#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET_MSK    0x1fffffff
+/* The mask used to clear the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
+#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_CLR_MSK    0xe0000000
+/* The reset value of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
+#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_RESET      0x0
+/* Extracts the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA field value from a register. */
+#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_GET(value) (((value) & 0x1fffffff) >> 0)
+/* Produces a ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value suitable for setting the register. */
+#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET(value) (((value) << 0) & 0x1fffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_EXT_PORTA.
+ */
+struct ALT_GPIO_EXT_PORTA_s
+{
+    const uint32_t  gpio_ext_porta : 29;  /* External Port Field */
+    uint32_t                       :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_EXT_PORTA. */
+typedef volatile struct ALT_GPIO_EXT_PORTA_s  ALT_GPIO_EXT_PORTA_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_EXT_PORTA register from the beginning of the component. */
+#define ALT_GPIO_EXT_PORTA_OFST        0x50
+/* The address of the ALT_GPIO_EXT_PORTA register. */
+#define ALT_GPIO_EXT_PORTA_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_EXT_PORTA_OFST))
+
+/*
+ * Register : Synchronization Level Register - gpio_ls_sync
+ * 
+ * The Synchronization level register is used to synchronize input with l4_mp_clk
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                
+ * :-------|:-------|:------|:----------------------------
+ *  [0]    | RW     | 0x0   | Synchronization Level Field
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*                
+ * 
+ */
+/*
+ * Field : Synchronization Level Field - gpio_ls_sync
+ * 
+ * The level-sensitive interrupts is synchronized to l4_mp_clk.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                   | Value | Description                    
+ * :---------------------------------------|:------|:--------------------------------
+ *  ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC | 0x0   | No synchronization to l4_mp_clk
+ *  ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC   | 0x1   | Synchronize to l4_mp_clk       
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC
+ * 
+ * No synchronization to l4_mp_clk
+ */
+#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC  0x0
+/*
+ * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC
+ * 
+ * Synchronize to l4_mp_clk
+ */
+#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
+#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
+#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB        0
+/* The width in bits of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
+#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH      1
+/* The mask used to set the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
+#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK    0x00000001
+/* The mask used to clear the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
+#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
+#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET      0x0
+/* Extracts the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */
+#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */
+#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_LS_SYNC.
+ */
+struct ALT_GPIO_LS_SYNC_s
+{
+    uint32_t  gpio_ls_sync :  1;  /* Synchronization Level Field */
+    uint32_t               : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_LS_SYNC. */
+typedef volatile struct ALT_GPIO_LS_SYNC_s  ALT_GPIO_LS_SYNC_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_LS_SYNC register from the beginning of the component. */
+#define ALT_GPIO_LS_SYNC_OFST        0x60
+/* The address of the ALT_GPIO_LS_SYNC register. */
+#define ALT_GPIO_LS_SYNC_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_LS_SYNC_OFST))
+
+/*
+ * Register : ID Code Register - gpio_id_code
+ * 
+ * GPIO ID code.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description  
+ * :-------|:-------|:------|:--------------
+ *  [31:0] | R      | 0x0   | ID Code Field
+ * 
+ */
+/*
+ * Field : ID Code Field - gpio_id_code
+ * 
+ * Chip identification
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
+#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
+#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_MSB        31
+/* The width in bits of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
+#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_WIDTH      32
+/* The mask used to set the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
+#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET_MSK    0xffffffff
+/* The mask used to clear the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
+#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_CLR_MSK    0x00000000
+/* The reset value of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
+#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_RESET      0x0
+/* Extracts the ALT_GPIO_ID_CODE_GPIO_ID_CODE field value from a register. */
+#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
+/* Produces a ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value suitable for setting the register. */
+#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_ID_CODE.
+ */
+struct ALT_GPIO_ID_CODE_s
+{
+    const uint32_t  gpio_id_code : 32;  /* ID Code Field */
+};
+
+/* The typedef declaration for register ALT_GPIO_ID_CODE. */
+typedef volatile struct ALT_GPIO_ID_CODE_s  ALT_GPIO_ID_CODE_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_ID_CODE register from the beginning of the component. */
+#define ALT_GPIO_ID_CODE_OFST        0x64
+/* The address of the ALT_GPIO_ID_CODE register. */
+#define ALT_GPIO_ID_CODE_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_ID_CODE_OFST))
+
+/*
+ * Register : GPIO Version Register - gpio_ver_id_code
+ * 
+ * GPIO Component Version
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset      | Description                  
+ * :-------|:-------|:-----------|:------------------------------
+ *  [31:0] | R      | 0x3230382a | ASCII Component Version Field
+ * 
+ */
+/*
+ * Field : ASCII Component Version Field - gpio_ver_id_code
+ * 
+ * ASCII value for each number in the version, followed by *. For example.
+ * 32_30_31_2A represents the version 2.01
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
+#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
+#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB        31
+/* The width in bits of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
+#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH      32
+/* The mask used to set the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
+#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK    0xffffffff
+/* The mask used to clear the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
+#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK    0x00000000
+/* The reset value of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
+#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET      0x3230382a
+/* Extracts the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */
+#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
+/* Produces a ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */
+#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_VER_ID_CODE.
+ */
+struct ALT_GPIO_VER_ID_CODE_s
+{
+    const uint32_t  gpio_ver_id_code : 32;  /* ASCII Component Version Field */
+};
+
+/* The typedef declaration for register ALT_GPIO_VER_ID_CODE. */
+typedef volatile struct ALT_GPIO_VER_ID_CODE_s  ALT_GPIO_VER_ID_CODE_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_VER_ID_CODE register from the beginning of the component. */
+#define ALT_GPIO_VER_ID_CODE_OFST        0x6c
+/* The address of the ALT_GPIO_VER_ID_CODE register. */
+#define ALT_GPIO_VER_ID_CODE_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_VER_ID_CODE_OFST))
+
+/*
+ * Register : Configuration Register 2 - gpio_config_reg2
+ * 
+ * Specifies the bit width of port A.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description          
+ * :--------|:-------|:------|:----------------------
+ *  [4:0]   | R      | 0x1c  | Port A Width (less 1)
+ *  [9:5]   | R      | 0x7   | Port B Width (less 1)
+ *  [14:10] | R      | 0x7   | Port C Width (less 1)
+ *  [19:15] | R      | 0x7   | Port D Width (less 1)
+ *  [31:20] | ???    | 0x0   | *UNDEFINED*          
+ * 
+ */
+/*
+ * Field : Port A Width (less 1) - encoded_id_pwidth_a
+ * 
+ * Specifies the width of GPIO Port A. The value 28 represents the 29-bit width
+ * less one.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                                   | Value | Description              
+ * :-------------------------------------------------------|:------|:--------------------------
+ *  ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS  | 0x7   | Width (less 1) of 8 bits 
+ *  ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS | 0x1c  | Width (less 1) of 29 bits
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
+ * 
+ * Width (less 1) of 8 bits
+ */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS   0x7
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
+ * 
+ * Width (less 1) of 29 bits
+ */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS  0x1c
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB        4
+/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH      5
+/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK    0x0000001f
+/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK    0xffffffe0
+/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET      0x1c
+/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0)
+/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f)
+
+/*
+ * Field : Port B Width (less 1) - encoded_id_pwidth_b
+ * 
+ * Specifies the width of GPIO Port B. Ignored because there is no Port B in the
+ * GPIO.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                                   | Value | Description              
+ * :-------------------------------------------------------|:------|:--------------------------
+ *  ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS  | 0x7   | Width (less 1) of 8 bits 
+ *  ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS | 0x1c  | Width (less 1) of 29 bits
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
+ * 
+ * Width (less 1) of 8 bits
+ */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS   0x7
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
+ * 
+ * Width (less 1) of 29 bits
+ */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS  0x1c
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB        9
+/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH      5
+/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK    0x000003e0
+/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK    0xfffffc1f
+/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET      0x7
+/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5)
+/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0)
+
+/*
+ * Field : Port C Width (less 1) - encoded_id_pwidth_c
+ * 
+ * Specifies the width of GPIO Port C. Ignored because there is no Port C in the
+ * GPIO.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                                   | Value | Description              
+ * :-------------------------------------------------------|:------|:--------------------------
+ *  ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS  | 0x7   | Width (less 1) of 8 bits 
+ *  ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS | 0x1c  | Width (less 1) of 29 bits
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
+ * 
+ * Width (less 1) of 8 bits
+ */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS   0x7
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
+ * 
+ * Width (less 1) of 29 bits
+ */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS  0x1c
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB        10
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB        14
+/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH      5
+/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK    0x00007c00
+/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK    0xffff83ff
+/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET      0x7
+/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10)
+/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00)
+
+/*
+ * Field : Port D Width (less 1) - encoded_id_pwidth_d
+ * 
+ * Specifies the width of GPIO Port D. Ignored because there is no Port D in the
+ * GPIO.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                                   | Value | Description              
+ * :-------------------------------------------------------|:------|:--------------------------
+ *  ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS  | 0x7   | Width (less 1) of 8 bits 
+ *  ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS | 0x1c  | Width (less 1) of 29 bits
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
+ * 
+ * Width (less 1) of 8 bits
+ */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS   0x7
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
+ * 
+ * Width (less 1) of 29 bits
+ */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS  0x1c
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB        15
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB        19
+/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH      5
+/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK    0x000f8000
+/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK    0xfff07fff
+/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET      0x7
+/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15)
+/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_CFG_REG2.
+ */
+struct ALT_GPIO_CFG_REG2_s
+{
+    const uint32_t  encoded_id_pwidth_a :  5;  /* Port A Width (less 1) */
+    const uint32_t  encoded_id_pwidth_b :  5;  /* Port B Width (less 1) */
+    const uint32_t  encoded_id_pwidth_c :  5;  /* Port C Width (less 1) */
+    const uint32_t  encoded_id_pwidth_d :  5;  /* Port D Width (less 1) */
+    uint32_t                            : 12;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_CFG_REG2. */
+typedef volatile struct ALT_GPIO_CFG_REG2_s  ALT_GPIO_CFG_REG2_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_CFG_REG2 register from the beginning of the component. */
+#define ALT_GPIO_CFG_REG2_OFST        0x70
+/* The address of the ALT_GPIO_CFG_REG2 register. */
+#define ALT_GPIO_CFG_REG2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG2_OFST))
+
+/*
+ * Register : Configuration Register 1 - gpio_config_reg1
+ * 
+ * Reports settings of various GPIO configuration parameters
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                      
+ * :--------|:-------|:------|:----------------------------------
+ *  [1:0]   | R      | 0x2   | APB DATA WIDTH                   
+ *  [3:2]   | R      | 0x0   | NUM PORTS                        
+ *  [4]     | R      | 0x1   | PORT A SINGLE CTL                
+ *  [5]     | R      | 0x1   | PORT B SINGLE CTL                
+ *  [6]     | R      | 0x1   | PORT C SINGLE CTL                
+ *  [7]     | R      | 0x1   | PORT D SINGLE CTL                
+ *  [8]     | R      | 0x0   | HW PORTA                         
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*                      
+ *  [12]    | R      | 0x1   | Port A Interrupt Field           
+ *  [13]    | R      | 0x1   | Debounce Field                   
+ *  [14]    | R      | 0x1   | Encoded GPIO Parameters Available
+ *  [15]    | R      | 0x1   | ID Field                         
+ *  [20:16] | R      | 0x1f  | Encoded ID Width Field           
+ *  [31:21] | ???    | 0x0   | *UNDEFINED*                      
+ * 
+ */
+/*
+ * Field : APB DATA WIDTH - apb_data_width
+ * 
+ * Fixed to support an ABP data bus width of 32-bits.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                           | Value | Description             
+ * :-----------------------------------------------|:------|:-------------------------
+ *  ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2   | APB Data Width = 32-bits
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_APB_DATA_WIDTH
+ * 
+ * APB Data Width = 32-bits
+ */
+#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS  0x2
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
+#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
+#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB        1
+/* The width in bits of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
+#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH      2
+/* The mask used to set the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
+#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK    0x00000003
+/* The mask used to clear the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
+#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK    0xfffffffc
+/* The reset value of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
+#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET      0x2
+/* Extracts the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register. */
+#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
+/* Produces a ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
+
+/*
+ * Field : NUM PORTS - num_ports
+ * 
+ * The value of this register is fixed at one port (Port A).
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                   | Value | Description             
+ * :---------------------------------------|:------|:-------------------------
+ *  ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA | 0x0   | Number of GPIO Ports = 1
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_NUM_PORTS
+ * 
+ * Number of GPIO Ports = 1
+ */
+#define ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA  0x0
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
+#define ALT_GPIO_CFG_REG1_NUM_PORTS_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
+#define ALT_GPIO_CFG_REG1_NUM_PORTS_MSB        3
+/* The width in bits of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
+#define ALT_GPIO_CFG_REG1_NUM_PORTS_WIDTH      2
+/* The mask used to set the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */
+#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET_MSK    0x0000000c
+/* The mask used to clear the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */
+#define ALT_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK    0xfffffff3
+/* The reset value of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
+#define ALT_GPIO_CFG_REG1_NUM_PORTS_RESET      0x0
+/* Extracts the ALT_GPIO_CFG_REG1_NUM_PORTS field value from a register. */
+#define ALT_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2)
+/* Produces a ALT_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c)
+
+/*
+ * Field : PORT A SINGLE CTL - porta_single_ctl
+ * 
+ * Indicates the mode of operation of Port A to be software controlled only.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                             | Value | Description                             
+ * :-------------------------------------------------|:------|:-----------------------------------------
+ *  ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY | 0x1   | Software Enabled Individual Port Control
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL
+ * 
+ * Software Enabled Individual Port Control
+ */
+#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB        4
+/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH      1
+/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
+#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK    0x00000010
+/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
+#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK    0xffffffef
+/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET      0x1
+/* Extracts the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register. */
+#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : PORT B SINGLE CTL - portb_single_ctl
+ * 
+ * Indicates the mode of operation of Port B to be software controlled only.
+ * Ignored because there is no Port B in the GPIO.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                             | Value | Description                             
+ * :-------------------------------------------------|:------|:-----------------------------------------
+ *  ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY | 0x1   | Software Enabled Individual Port Control
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL
+ * 
+ * Software Enabled Individual Port Control
+ */
+#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB        5
+/* The width in bits of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH      1
+/* The mask used to set the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
+#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK    0x00000020
+/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
+#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET      0x1
+/* Extracts the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register. */
+#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : PORT C SINGLE CTL - portc_single_ctl
+ * 
+ * Indicates the mode of operation of Port C to be software controlled only.
+ * Ignored because there is no Port C in the GPIO.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                             | Value | Description                             
+ * :-------------------------------------------------|:------|:-----------------------------------------
+ *  ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY | 0x1   | Software Enabled Individual Port Control
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL
+ * 
+ * Software Enabled Individual Port Control
+ */
+#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB        6
+/* The width in bits of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH      1
+/* The mask used to set the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
+#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK    0x00000040
+/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
+#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET      0x1
+/* Extracts the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register. */
+#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : PORT D SINGLE CTL - portd_single_ctl
+ * 
+ * Indicates the mode of operation of Port D to be software controlled only.
+ * Ignored because there is no Port D in the GPIO.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                             | Value | Description                             
+ * :-------------------------------------------------|:------|:-----------------------------------------
+ *  ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY | 0x1   | Software Enabled Individual Port Control
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL
+ * 
+ * Software Enabled Individual Port Control
+ */
+#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB        7
+/* The width in bits of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH      1
+/* The mask used to set the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
+#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK    0x00000080
+/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
+#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
+#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET      0x1
+/* Extracts the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register. */
+#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : HW PORTA - hw_porta
+ * 
+ * The value is fixed to enable Port A configuration to be controlled by software
+ * only.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                     | Value | Description                           
+ * :-----------------------------------------|:------|:---------------------------------------
+ *  ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD | 0x0   | Software Configuration Control Enabled
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_HW_PORTA
+ * 
+ * Software Configuration Control Enabled
+ */
+#define ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD    0x0
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
+#define ALT_GPIO_CFG_REG1_HW_PORTA_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
+#define ALT_GPIO_CFG_REG1_HW_PORTA_MSB        8
+/* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
+#define ALT_GPIO_CFG_REG1_HW_PORTA_WIDTH      1
+/* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */
+#define ALT_GPIO_CFG_REG1_HW_PORTA_SET_MSK    0x00000100
+/* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */
+#define ALT_GPIO_CFG_REG1_HW_PORTA_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
+#define ALT_GPIO_CFG_REG1_HW_PORTA_RESET      0x0
+/* Extracts the ALT_GPIO_CFG_REG1_HW_PORTA field value from a register. */
+#define ALT_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : Port A Interrupt Field - porta_intr
+ * 
+ * The value of this field is fixed to allow interrupts on Port A.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                       | Value | Description              
+ * :-------------------------------------------|:------|:--------------------------
+ *  ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR | 0x1   | Port A Interrupts Enabled
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_INTR
+ * 
+ * Port A Interrupts Enabled
+ */
+#define ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
+#define ALT_GPIO_CFG_REG1_PORTA_INTR_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
+#define ALT_GPIO_CFG_REG1_PORTA_INTR_MSB        12
+/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
+#define ALT_GPIO_CFG_REG1_PORTA_INTR_WIDTH      1
+/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */
+#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET_MSK    0x00001000
+/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */
+#define ALT_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK    0xffffefff
+/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
+#define ALT_GPIO_CFG_REG1_PORTA_INTR_RESET      0x1
+/* Extracts the ALT_GPIO_CFG_REG1_PORTA_INTR field value from a register. */
+#define ALT_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12)
+/* Produces a ALT_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000)
+
+/*
+ * Field : Debounce Field - debounce
+ * 
+ * The value of this field is fixed to allow debouncing of the Port A signals.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                   | Value | Description        
+ * :---------------------------------------|:------|:--------------------
+ *  ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA | 0x1   | Debounce is Enabled
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_DEBOUNCE
+ * 
+ * Debounce is Enabled
+ */
+#define ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
+#define ALT_GPIO_CFG_REG1_DEBOUNCE_LSB        13
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
+#define ALT_GPIO_CFG_REG1_DEBOUNCE_MSB        13
+/* The width in bits of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
+#define ALT_GPIO_CFG_REG1_DEBOUNCE_WIDTH      1
+/* The mask used to set the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */
+#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET_MSK    0x00002000
+/* The mask used to clear the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */
+#define ALT_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK    0xffffdfff
+/* The reset value of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
+#define ALT_GPIO_CFG_REG1_DEBOUNCE_RESET      0x1
+/* Extracts the ALT_GPIO_CFG_REG1_DEBOUNCE field value from a register. */
+#define ALT_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13)
+/* Produces a ALT_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000)
+
+/*
+ * Field : Encoded GPIO Parameters Available - add_encoded_params
+ * 
+ * Fixed to allow the indentification of the Designware IP component.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                            | Value | Description              
+ * :------------------------------------------------|:------|:--------------------------
+ *  ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1   | Enable IP indentification
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS
+ * 
+ * Enable IP indentification
+ */
+#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
+#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB        14
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
+#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB        14
+/* The width in bits of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
+#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH      1
+/* The mask used to set the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
+#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK    0x00004000
+/* The mask used to clear the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
+#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK    0xffffbfff
+/* The reset value of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
+#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET      0x1
+/* Extracts the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register. */
+#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14)
+/* Produces a ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000)
+
+/*
+ * Field : ID Field - gpio_id
+ * 
+ * Provides an ID code value
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                               | Value | Description 
+ * :-----------------------------------|:------|:-------------
+ *  ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE | 0x1   | GPIO ID Code
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_GPIO_ID
+ * 
+ * GPIO ID Code
+ */
+#define ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
+#define ALT_GPIO_CFG_REG1_GPIO_ID_LSB        15
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
+#define ALT_GPIO_CFG_REG1_GPIO_ID_MSB        15
+/* The width in bits of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
+#define ALT_GPIO_CFG_REG1_GPIO_ID_WIDTH      1
+/* The mask used to set the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */
+#define ALT_GPIO_CFG_REG1_GPIO_ID_SET_MSK    0x00008000
+/* The mask used to clear the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */
+#define ALT_GPIO_CFG_REG1_GPIO_ID_CLR_MSK    0xffff7fff
+/* The reset value of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
+#define ALT_GPIO_CFG_REG1_GPIO_ID_RESET      0x1
+/* Extracts the ALT_GPIO_CFG_REG1_GPIO_ID field value from a register. */
+#define ALT_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15)
+/* Produces a ALT_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000)
+
+/*
+ * Field : Encoded ID Width Field - encoded_id_width
+ * 
+ * This value is fixed at 32 bits.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description      
+ * :--------------------------------------------|:------|:------------------
+ *  ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH | 0x1f  | Width of ID Field
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_GPIO_CFG_REG1_ENC_ID_WIDTH
+ * 
+ * Width of ID Field
+ */
+#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f
+
+/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
+#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
+#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB        20
+/* The width in bits of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
+#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH      5
+/* The mask used to set the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
+#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK    0x001f0000
+/* The mask used to clear the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
+#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK    0xffe0ffff
+/* The reset value of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
+#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET      0x1f
+/* Extracts the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register. */
+#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16)
+/* Produces a ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register. */
+#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_GPIO_CFG_REG1.
+ */
+struct ALT_GPIO_CFG_REG1_s
+{
+    const uint32_t  apb_data_width     :  2;  /* APB DATA WIDTH */
+    const uint32_t  num_ports          :  2;  /* NUM PORTS */
+    const uint32_t  porta_single_ctl   :  1;  /* PORT A SINGLE CTL */
+    const uint32_t  portb_single_ctl   :  1;  /* PORT B SINGLE CTL */
+    const uint32_t  portc_single_ctl   :  1;  /* PORT C SINGLE CTL */
+    const uint32_t  portd_single_ctl   :  1;  /* PORT D SINGLE CTL */
+    const uint32_t  hw_porta           :  1;  /* HW PORTA */
+    uint32_t                           :  3;  /* *UNDEFINED* */
+    const uint32_t  porta_intr         :  1;  /* Port A Interrupt Field */
+    const uint32_t  debounce           :  1;  /* Debounce Field */
+    const uint32_t  add_encoded_params :  1;  /* Encoded GPIO Parameters Available */
+    const uint32_t  gpio_id            :  1;  /* ID Field */
+    const uint32_t  encoded_id_width   :  5;  /* Encoded ID Width Field */
+    uint32_t                           : 11;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_GPIO_CFG_REG1. */
+typedef volatile struct ALT_GPIO_CFG_REG1_s  ALT_GPIO_CFG_REG1_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_GPIO_CFG_REG1 register from the beginning of the component. */
+#define ALT_GPIO_CFG_REG1_OFST        0x74
+/* The address of the ALT_GPIO_CFG_REG1 register. */
+#define ALT_GPIO_CFG_REG1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG1_OFST))
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_GPIO.
+ */
+struct ALT_GPIO_s
+{
+    volatile ALT_GPIO_SWPORTA_DR_t     gpio_swporta_dr;     /* ALT_GPIO_SWPORTA_DR */
+    volatile ALT_GPIO_SWPORTA_DDR_t    gpio_swporta_ddr;    /* ALT_GPIO_SWPORTA_DDR */
+    volatile uint32_t                  _pad_0x8_0x2f[10];   /* *UNDEFINED* */
+    volatile ALT_GPIO_INTEN_t          gpio_inten;          /* ALT_GPIO_INTEN */
+    volatile ALT_GPIO_INTMSK_t         gpio_intmask;        /* ALT_GPIO_INTMSK */
+    volatile ALT_GPIO_INTTYPE_LEVEL_t  gpio_inttype_level;  /* ALT_GPIO_INTTYPE_LEVEL */
+    volatile ALT_GPIO_INT_POL_t        gpio_int_polarity;   /* ALT_GPIO_INT_POL */
+    volatile ALT_GPIO_INTSTAT_t        gpio_intstatus;      /* ALT_GPIO_INTSTAT */
+    volatile ALT_GPIO_RAW_INTSTAT_t    gpio_raw_intstatus;  /* ALT_GPIO_RAW_INTSTAT */
+    volatile ALT_GPIO_DEBOUNCE_t       gpio_debounce;       /* ALT_GPIO_DEBOUNCE */
+    volatile ALT_GPIO_PORTA_EOI_t      gpio_porta_eoi;      /* ALT_GPIO_PORTA_EOI */
+    volatile ALT_GPIO_EXT_PORTA_t      gpio_ext_porta;      /* ALT_GPIO_EXT_PORTA */
+    volatile uint32_t                  _pad_0x54_0x5f[3];   /* *UNDEFINED* */
+    volatile ALT_GPIO_LS_SYNC_t        gpio_ls_sync;        /* ALT_GPIO_LS_SYNC */
+    volatile ALT_GPIO_ID_CODE_t        gpio_id_code;        /* ALT_GPIO_ID_CODE */
+    volatile uint32_t                  _pad_0x68_0x6b;      /* *UNDEFINED* */
+    volatile ALT_GPIO_VER_ID_CODE_t    gpio_ver_id_code;    /* ALT_GPIO_VER_ID_CODE */
+    volatile ALT_GPIO_CFG_REG2_t       gpio_config_reg2;    /* ALT_GPIO_CFG_REG2 */
+    volatile ALT_GPIO_CFG_REG1_t       gpio_config_reg1;    /* ALT_GPIO_CFG_REG1 */
+    volatile uint32_t                  _pad_0x78_0x80[2];   /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register group ALT_GPIO. */
+typedef volatile struct ALT_GPIO_s  ALT_GPIO_t;
+/* The struct declaration for the raw register contents of register group ALT_GPIO. */
+struct ALT_GPIO_raw_s
+{
+    volatile uint32_t  gpio_swporta_dr;     /* ALT_GPIO_SWPORTA_DR */
+    volatile uint32_t  gpio_swporta_ddr;    /* ALT_GPIO_SWPORTA_DDR */
+    volatile uint32_t  _pad_0x8_0x2f[10];   /* *UNDEFINED* */
+    volatile uint32_t  gpio_inten;          /* ALT_GPIO_INTEN */
+    volatile uint32_t  gpio_intmask;        /* ALT_GPIO_INTMSK */
+    volatile uint32_t  gpio_inttype_level;  /* ALT_GPIO_INTTYPE_LEVEL */
+    volatile uint32_t  gpio_int_polarity;   /* ALT_GPIO_INT_POL */
+    volatile uint32_t  gpio_intstatus;      /* ALT_GPIO_INTSTAT */
+    volatile uint32_t  gpio_raw_intstatus;  /* ALT_GPIO_RAW_INTSTAT */
+    volatile uint32_t  gpio_debounce;       /* ALT_GPIO_DEBOUNCE */
+    volatile uint32_t  gpio_porta_eoi;      /* ALT_GPIO_PORTA_EOI */
+    volatile uint32_t  gpio_ext_porta;      /* ALT_GPIO_EXT_PORTA */
+    volatile uint32_t  _pad_0x54_0x5f[3];   /* *UNDEFINED* */
+    volatile uint32_t  gpio_ls_sync;        /* ALT_GPIO_LS_SYNC */
+    volatile uint32_t  gpio_id_code;        /* ALT_GPIO_ID_CODE */
+    volatile uint32_t  _pad_0x68_0x6b;      /* *UNDEFINED* */
+    volatile uint32_t  gpio_ver_id_code;    /* ALT_GPIO_VER_ID_CODE */
+    volatile uint32_t  gpio_config_reg2;    /* ALT_GPIO_CFG_REG2 */
+    volatile uint32_t  gpio_config_reg1;    /* ALT_GPIO_CFG_REG1 */
+    volatile uint32_t  _pad_0x78_0x80[2];   /* *UNDEFINED* */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_GPIO. */
+typedef volatile struct ALT_GPIO_raw_s  ALT_GPIO_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALTERA_ALT_GPIO_H__ */
+
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_l3.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_l3.h
new file mode 100644
index 0000000..12e6f21
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_l3.h
@@ -0,0 +1,6299 @@
+/*******************************************************************************
+*                                                                              *
+* Copyright 2013 Altera Corporation. All Rights Reserved.                      *
+*                                                                              *
+* Redistribution and use in source and binary forms, with or without           *
+* modification, are permitted provided that the following conditions are met:  *
+*                                                                              *
+* 1. Redistributions of source code must retain the above copyright notice,    *
+*    this list of conditions and the following disclaimer.                     *
+*                                                                              *
+* 2. Redistributions in binary form must reproduce the above copyright notice, *
+*    this list of conditions and the following disclaimer in the documentation *
+*    and/or other materials provided with the distribution.                    *
+*                                                                              *
+* 3. The name of the author may not be used to endorse or promote products     *
+*    derived from this software without specific prior written permission.     *
+*                                                                              *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO  *
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,       *
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;  *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,     *
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR      *
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF       *
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                   *
+*                                                                              *
+*******************************************************************************/
+
+/* Altera - ALT_L3 */
+
+#ifndef __ALTERA_ALT_L3_H__
+#define __ALTERA_ALT_L3_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*
+ * Component : L3 (NIC-301) GPV Registers - ALT_L3
+ * L3 (NIC-301) GPV Registers
+ * 
+ * Registers to control L3 interconnect settings
+ * 
+ */
+/*
+ * Register : Remap - remap
+ * 
+ * The L3 interconnect has separate address maps for the various L3 Masters.
+ * Generally, the addresses are the same for most masters. However, the sparse
+ * interconnect of the L3 switch causes some masters to have holes in their memory
+ * maps. The remap bits are not mutually exclusive. Each bit can be set
+ * independently and in combinations. Priority for the bits is determined by the
+ * bit offset: lower offset bits take precedence over higher offset bits.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                     
+ * :-------|:-------|:------|:---------------------------------
+ *  [0]    | W      | 0x0   | MPU at 0x0                      
+ *  [1]    | W      | 0x0   | Non-MPU at 0x0                  
+ *  [2]    | ???    | 0x0   | *UNDEFINED*                     
+ *  [3]    | W      | 0x0   | HPS2FPGA AXI Bridge Visibility  
+ *  [4]    | W      | 0x0   | LWHPS2FPGA AXI Bridge Visibility
+ *  [31:5] | ???    | 0x0   | *UNDEFINED*                     
+ * 
+ */
+/*
+ * Field : MPU at 0x0 - mpuzero
+ * 
+ * Controls whether address 0x0 for the MPU L3 master is mapped to the Boot ROM or
+ * On-chip RAM.  This field only has an effect on the MPU L3 master.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                           | Value | Description                                     
+ * :-------------------------------|:------|:-------------------------------------------------
+ *  ALT_L3_REMAP_MPUZERO_E_BOOTROM | 0x0   | Maps the Boot ROM to address 0x0 for the MPU L3 
+ * :                               |       | master. Note that the Boot ROM is also always   
+ * :                               |       | mapped to address 0xfffd_0000 for the MPU L3    
+ * :                               |       | master independent of this field's value.       
+ *  ALT_L3_REMAP_MPUZERO_E_OCRAM   | 0x1   | Maps the On-chip RAM to address 0x0 for the MPU 
+ * :                               |       | L3 master. Note that the On-chip RAM is also    
+ * :                               |       | always mapped to address 0xffff_0000 for the MPU
+ * :                               |       | L3 master independent of this field's value.    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_REMAP_MPUZERO
+ * 
+ * Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM
+ * is also always mapped to address 0xfffd_0000 for the MPU L3 master independent
+ * of this field's value.
+ */
+#define ALT_L3_REMAP_MPUZERO_E_BOOTROM  0x0
+/*
+ * Enumerated value for register field ALT_L3_REMAP_MPUZERO
+ * 
+ * Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip
+ * RAM is also always mapped to address 0xffff_0000 for the MPU L3 master
+ * independent of this field's value.
+ */
+#define ALT_L3_REMAP_MPUZERO_E_OCRAM    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_MPUZERO register field. */
+#define ALT_L3_REMAP_MPUZERO_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_MPUZERO register field. */
+#define ALT_L3_REMAP_MPUZERO_MSB        0
+/* The width in bits of the ALT_L3_REMAP_MPUZERO register field. */
+#define ALT_L3_REMAP_MPUZERO_WIDTH      1
+/* The mask used to set the ALT_L3_REMAP_MPUZERO register field value. */
+#define ALT_L3_REMAP_MPUZERO_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_REMAP_MPUZERO register field value. */
+#define ALT_L3_REMAP_MPUZERO_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_REMAP_MPUZERO register field. */
+#define ALT_L3_REMAP_MPUZERO_RESET      0x0
+/* Extracts the ALT_L3_REMAP_MPUZERO field value from a register. */
+#define ALT_L3_REMAP_MPUZERO_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_REMAP_MPUZERO register field value suitable for setting the register. */
+#define ALT_L3_REMAP_MPUZERO_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Non-MPU at 0x0 - nonmpuzero
+ * 
+ * Controls whether address 0x0 for the non-MPU L3 masters is mapped to the SDRAM
+ * or On-chip RAM.  This field only has an effect on the non-MPU L3 masters. The
+ * non-MPU L3 masters are the DMA controllers (standalone and those built-in to
+ * peripherals), the FPGA2HPS AXI Bridge, and the DAP.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                            | Value | Description                                     
+ * :--------------------------------|:------|:-------------------------------------------------
+ *  ALT_L3_REMAP_NONMPUZERO_E_SDRAM | 0x0   | Maps the SDRAM to address 0x0 for the non-MPU L3
+ * :                                |       | masters.                                        
+ *  ALT_L3_REMAP_NONMPUZERO_E_OCRAM | 0x1   | Maps the On-chip RAM to address 0x0 for the non-
+ * :                                |       | MPU L3 masters. Note that the On-chip RAM is    
+ * :                                |       | also always mapped to address 0xffff_0000 for   
+ * :                                |       | the non-MPU L3 masters independent of this      
+ * :                                |       | field's value.                                  
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO
+ * 
+ * Maps the SDRAM to address 0x0 for the non-MPU L3 masters.
+ */
+#define ALT_L3_REMAP_NONMPUZERO_E_SDRAM 0x0
+/*
+ * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO
+ * 
+ * Maps the On-chip RAM to address 0x0 for the non-MPU L3 masters. Note that the
+ * On-chip RAM is also always mapped to address 0xffff_0000 for the non-MPU L3
+ * masters independent of this field's value.
+ */
+#define ALT_L3_REMAP_NONMPUZERO_E_OCRAM 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */
+#define ALT_L3_REMAP_NONMPUZERO_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */
+#define ALT_L3_REMAP_NONMPUZERO_MSB        1
+/* The width in bits of the ALT_L3_REMAP_NONMPUZERO register field. */
+#define ALT_L3_REMAP_NONMPUZERO_WIDTH      1
+/* The mask used to set the ALT_L3_REMAP_NONMPUZERO register field value. */
+#define ALT_L3_REMAP_NONMPUZERO_SET_MSK    0x00000002
+/* The mask used to clear the ALT_L3_REMAP_NONMPUZERO register field value. */
+#define ALT_L3_REMAP_NONMPUZERO_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_L3_REMAP_NONMPUZERO register field. */
+#define ALT_L3_REMAP_NONMPUZERO_RESET      0x0
+/* Extracts the ALT_L3_REMAP_NONMPUZERO field value from a register. */
+#define ALT_L3_REMAP_NONMPUZERO_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_L3_REMAP_NONMPUZERO register field value suitable for setting the register. */
+#define ALT_L3_REMAP_NONMPUZERO_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : HPS2FPGA AXI Bridge Visibility - hps2fpga
+ * 
+ * Controls whether the HPS2FPGA AXI Bridge is visible to L3 masters or not.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                         | Value | Description                                    
+ * :-----------------------------|:------|:------------------------------------------------
+ *  ALT_L3_REMAP_H2F_E_INVISIBLE | 0x0   | The HPS2FPGA AXI Bridge is not visible to L3   
+ * :                             |       | masters. Accesses to the associated address    
+ * :                             |       | range return an AXI decode error to the master.
+ *  ALT_L3_REMAP_H2F_E_VISIBLE   | 0x1   | The HPS2FPGA AXI Bridge is visible to L3       
+ * :                             |       | masters.                                       
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_REMAP_H2F
+ * 
+ * The HPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated
+ * address range return an AXI decode error to the master.
+ */
+#define ALT_L3_REMAP_H2F_E_INVISIBLE    0x0
+/*
+ * Enumerated value for register field ALT_L3_REMAP_H2F
+ * 
+ * The HPS2FPGA AXI Bridge is visible to L3 masters.
+ */
+#define ALT_L3_REMAP_H2F_E_VISIBLE      0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_H2F register field. */
+#define ALT_L3_REMAP_H2F_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_H2F register field. */
+#define ALT_L3_REMAP_H2F_MSB        3
+/* The width in bits of the ALT_L3_REMAP_H2F register field. */
+#define ALT_L3_REMAP_H2F_WIDTH      1
+/* The mask used to set the ALT_L3_REMAP_H2F register field value. */
+#define ALT_L3_REMAP_H2F_SET_MSK    0x00000008
+/* The mask used to clear the ALT_L3_REMAP_H2F register field value. */
+#define ALT_L3_REMAP_H2F_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_L3_REMAP_H2F register field. */
+#define ALT_L3_REMAP_H2F_RESET      0x0
+/* Extracts the ALT_L3_REMAP_H2F field value from a register. */
+#define ALT_L3_REMAP_H2F_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_L3_REMAP_H2F register field value suitable for setting the register. */
+#define ALT_L3_REMAP_H2F_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : LWHPS2FPGA AXI Bridge Visibility - lwhps2fpga
+ * 
+ * Controls whether the Lightweight HPS2FPGA AXI Bridge is visible to L3 masters or
+ * not.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                           | Value | Description                                    
+ * :-------------------------------|:------|:------------------------------------------------
+ *  ALT_L3_REMAP_LWH2F_E_INVISIBLE | 0x0   | The LWHPS2FPGA AXI Bridge is not visible to L3 
+ * :                               |       | masters. Accesses to the associated address    
+ * :                               |       | range return an AXI decode error to the master.
+ *  ALT_L3_REMAP_LWH2F_E_VISIBLE   | 0x1   | The LWHPS2FPGA AXI Bridge is visible to L3     
+ * :                               |       | masters.                                       
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_REMAP_LWH2F
+ * 
+ * The LWHPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the
+ * associated address range return an AXI decode error to the master.
+ */
+#define ALT_L3_REMAP_LWH2F_E_INVISIBLE  0x0
+/*
+ * Enumerated value for register field ALT_L3_REMAP_LWH2F
+ * 
+ * The LWHPS2FPGA AXI Bridge is visible to L3 masters.
+ */
+#define ALT_L3_REMAP_LWH2F_E_VISIBLE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_LWH2F register field. */
+#define ALT_L3_REMAP_LWH2F_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_LWH2F register field. */
+#define ALT_L3_REMAP_LWH2F_MSB        4
+/* The width in bits of the ALT_L3_REMAP_LWH2F register field. */
+#define ALT_L3_REMAP_LWH2F_WIDTH      1
+/* The mask used to set the ALT_L3_REMAP_LWH2F register field value. */
+#define ALT_L3_REMAP_LWH2F_SET_MSK    0x00000010
+/* The mask used to clear the ALT_L3_REMAP_LWH2F register field value. */
+#define ALT_L3_REMAP_LWH2F_CLR_MSK    0xffffffef
+/* The reset value of the ALT_L3_REMAP_LWH2F register field. */
+#define ALT_L3_REMAP_LWH2F_RESET      0x0
+/* Extracts the ALT_L3_REMAP_LWH2F field value from a register. */
+#define ALT_L3_REMAP_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_L3_REMAP_LWH2F register field value suitable for setting the register. */
+#define ALT_L3_REMAP_LWH2F_SET(value) (((value) << 4) & 0x00000010)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_REMAP.
+ */
+struct ALT_L3_REMAP_s
+{
+    uint32_t  mpuzero    :  1;  /* MPU at 0x0 */
+    uint32_t  nonmpuzero :  1;  /* Non-MPU at 0x0 */
+    uint32_t             :  1;  /* *UNDEFINED* */
+    uint32_t  hps2fpga   :  1;  /* HPS2FPGA AXI Bridge Visibility */
+    uint32_t  lwhps2fpga :  1;  /* LWHPS2FPGA AXI Bridge Visibility */
+    uint32_t             : 27;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_REMAP. */
+typedef volatile struct ALT_L3_REMAP_s  ALT_L3_REMAP_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_REMAP register from the beginning of the component. */
+#define ALT_L3_REMAP_OFST        0x0
+
+/*
+ * Register Group : Security Register Group - ALT_L3_SECGRP
+ * Security Register Group
+ * 
+ * Registers that control slave security.
+ * 
+ */
+/*
+ * Register : L4 Main Peripherals Security - l4main
+ * 
+ * Controls security settings for L4 Main peripherals.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description            
+ * :-------|:-------|:------|:------------------------
+ *  [0]    | W      | 0x0   | SPI Slave 0 Security   
+ *  [1]    | W      | 0x0   | SPI Slave 1 Security   
+ *  [2]    | W      | 0x0   | DMA Secure Security    
+ *  [3]    | W      | 0x0   | DMA Non-secure Security
+ *  [31:4] | ???    | 0x0   | *UNDEFINED*            
+ * 
+ */
+/*
+ * Field : SPI Slave 0 Security - spis0
+ * 
+ * Controls whether secure or non-secure masters can access the SPI Slave 0 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                | Value | Description                                  
+ * :------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                    |       | master.                                      
+ *  ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                    |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE    0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
+#define ALT_L3_SEC_L4MAIN_SPIS0_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
+#define ALT_L3_SEC_L4MAIN_SPIS0_MSB        0
+/* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
+#define ALT_L3_SEC_L4MAIN_SPIS0_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */
+#define ALT_L3_SEC_L4MAIN_SPIS0_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */
+#define ALT_L3_SEC_L4MAIN_SPIS0_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
+#define ALT_L3_SEC_L4MAIN_SPIS0_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MAIN_SPIS0 field value from a register. */
+#define ALT_L3_SEC_L4MAIN_SPIS0_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_L4MAIN_SPIS0 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MAIN_SPIS0_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : SPI Slave 1 Security - spis1
+ * 
+ * Controls whether secure or non-secure masters can access the SPI Slave 1 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                | Value | Description                                  
+ * :------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                    |       | master.                                      
+ *  ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                    |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE    0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
+#define ALT_L3_SEC_L4MAIN_SPIS1_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
+#define ALT_L3_SEC_L4MAIN_SPIS1_MSB        1
+/* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
+#define ALT_L3_SEC_L4MAIN_SPIS1_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */
+#define ALT_L3_SEC_L4MAIN_SPIS1_SET_MSK    0x00000002
+/* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */
+#define ALT_L3_SEC_L4MAIN_SPIS1_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
+#define ALT_L3_SEC_L4MAIN_SPIS1_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MAIN_SPIS1 field value from a register. */
+#define ALT_L3_SEC_L4MAIN_SPIS1_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_L3_SEC_L4MAIN_SPIS1 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MAIN_SPIS1_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : DMA Secure Security - dmasecure
+ * 
+ * Controls whether secure or non-secure masters can access the DMA Secure slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                    | Value | Description                                  
+ * :----------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                        |       | master.                                      
+ *  ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                        |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE    0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
+#define ALT_L3_SEC_L4MAIN_DMASECURE_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
+#define ALT_L3_SEC_L4MAIN_DMASECURE_MSB        2
+/* The width in bits of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
+#define ALT_L3_SEC_L4MAIN_DMASECURE_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */
+#define ALT_L3_SEC_L4MAIN_DMASECURE_SET_MSK    0x00000004
+/* The mask used to clear the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */
+#define ALT_L3_SEC_L4MAIN_DMASECURE_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
+#define ALT_L3_SEC_L4MAIN_DMASECURE_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MAIN_DMASECURE field value from a register. */
+#define ALT_L3_SEC_L4MAIN_DMASECURE_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_L3_SEC_L4MAIN_DMASECURE register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MAIN_DMASECURE_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : DMA Non-secure Security - dmanonsecure
+ * 
+ * Controls whether secure or non-secure masters can access the DMA Non-secure
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                       | Value | Description                                  
+ * :-------------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                           |       | master.                                      
+ *  ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                           |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE     0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
+#define ALT_L3_SEC_L4MAIN_DMANONSECURE_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
+#define ALT_L3_SEC_L4MAIN_DMANONSECURE_MSB        3
+/* The width in bits of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
+#define ALT_L3_SEC_L4MAIN_DMANONSECURE_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */
+#define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET_MSK    0x00000008
+/* The mask used to clear the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */
+#define ALT_L3_SEC_L4MAIN_DMANONSECURE_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
+#define ALT_L3_SEC_L4MAIN_DMANONSECURE_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MAIN_DMANONSECURE field value from a register. */
+#define ALT_L3_SEC_L4MAIN_DMANONSECURE_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_L3_SEC_L4MAIN_DMANONSECURE register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET(value) (((value) << 3) & 0x00000008)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_L4MAIN.
+ */
+struct ALT_L3_SEC_L4MAIN_s
+{
+    uint32_t  spis0        :  1;  /* SPI Slave 0 Security */
+    uint32_t  spis1        :  1;  /* SPI Slave 1 Security */
+    uint32_t  dmasecure    :  1;  /* DMA Secure Security */
+    uint32_t  dmanonsecure :  1;  /* DMA Non-secure Security */
+    uint32_t               : 28;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_L4MAIN. */
+typedef volatile struct ALT_L3_SEC_L4MAIN_s  ALT_L3_SEC_L4MAIN_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_L4MAIN register from the beginning of the component. */
+#define ALT_L3_SEC_L4MAIN_OFST        0x0
+
+/*
+ * Register : L4 SP Peripherals Security - l4sp
+ * 
+ * Controls security settings for L4 SP peripherals.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description             
+ * :--------|:-------|:------|:-------------------------
+ *  [0]     | W      | 0x0   | SDRAM Registers Security
+ *  [1]     | W      | 0x0   | SP Timer 0 Security     
+ *  [2]     | W      | 0x0   | I2C0 Security           
+ *  [3]     | W      | 0x0   | I2C1 Security           
+ *  [4]     | W      | 0x0   | I2C2 (EMAC 0) Security  
+ *  [5]     | W      | 0x0   | I2C3 (EMAC 1) Security  
+ *  [6]     | W      | 0x0   | UART 0 Security         
+ *  [7]     | W      | 0x0   | UART 1 Security         
+ *  [8]     | W      | 0x0   | CAN 0 Security          
+ *  [9]     | W      | 0x0   | CAN 1 Security          
+ *  [10]    | W      | 0x0   | SP Timer 1 Security     
+ *  [31:11] | ???    | 0x0   | *UNDEFINED*             
+ * 
+ */
+/*
+ * Field : SDRAM Registers Security - sdrregs
+ * 
+ * Controls whether secure or non-secure masters can access the SDRAM Registers
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                | Value | Description                                  
+ * :------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SP_SDRREGS_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                    |       | master.                                      
+ *  ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                    |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SP_SDRREGS_E_SECURE    0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */
+#define ALT_L3_SEC_L4SP_SDRREGS_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */
+#define ALT_L3_SEC_L4SP_SDRREGS_MSB        0
+/* The width in bits of the ALT_L3_SEC_L4SP_SDRREGS register field. */
+#define ALT_L3_SEC_L4SP_SDRREGS_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SP_SDRREGS register field value. */
+#define ALT_L3_SEC_L4SP_SDRREGS_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_L4SP_SDRREGS register field value. */
+#define ALT_L3_SEC_L4SP_SDRREGS_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_L4SP_SDRREGS register field. */
+#define ALT_L3_SEC_L4SP_SDRREGS_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SP_SDRREGS field value from a register. */
+#define ALT_L3_SEC_L4SP_SDRREGS_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_L4SP_SDRREGS register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SP_SDRREGS_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : SP Timer 0 Security - sptimer0
+ * 
+ * Controls whether secure or non-secure masters can access the SP Timer 0 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                               | Value | Description                                  
+ * :-----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SP_SPTMR0_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                   |       | master.                                      
+ *  ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                   |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SP_SPTMR0_E_SECURE     0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
+#define ALT_L3_SEC_L4SP_SPTMR0_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
+#define ALT_L3_SEC_L4SP_SPTMR0_MSB        1
+/* The width in bits of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
+#define ALT_L3_SEC_L4SP_SPTMR0_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SP_SPTMR0 register field value. */
+#define ALT_L3_SEC_L4SP_SPTMR0_SET_MSK    0x00000002
+/* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR0 register field value. */
+#define ALT_L3_SEC_L4SP_SPTMR0_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
+#define ALT_L3_SEC_L4SP_SPTMR0_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SP_SPTMR0 field value from a register. */
+#define ALT_L3_SEC_L4SP_SPTMR0_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_L3_SEC_L4SP_SPTMR0 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SP_SPTMR0_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : I2C0 Security - i2c0
+ * 
+ * Controls whether secure or non-secure masters can access the I2C0 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                  
+ * :---------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SP_I2C0_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                 |       | master.                                      
+ *  ALT_L3_SEC_L4SP_I2C0_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                 |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SP_I2C0_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SP_I2C0_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */
+#define ALT_L3_SEC_L4SP_I2C0_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */
+#define ALT_L3_SEC_L4SP_I2C0_MSB        2
+/* The width in bits of the ALT_L3_SEC_L4SP_I2C0 register field. */
+#define ALT_L3_SEC_L4SP_I2C0_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SP_I2C0 register field value. */
+#define ALT_L3_SEC_L4SP_I2C0_SET_MSK    0x00000004
+/* The mask used to clear the ALT_L3_SEC_L4SP_I2C0 register field value. */
+#define ALT_L3_SEC_L4SP_I2C0_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_L3_SEC_L4SP_I2C0 register field. */
+#define ALT_L3_SEC_L4SP_I2C0_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SP_I2C0 field value from a register. */
+#define ALT_L3_SEC_L4SP_I2C0_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_L3_SEC_L4SP_I2C0 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SP_I2C0_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : I2C1 Security - i2c1
+ * 
+ * Controls whether secure or non-secure masters can access the I2C1 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                  
+ * :---------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SP_I2C1_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                 |       | master.                                      
+ *  ALT_L3_SEC_L4SP_I2C1_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                 |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SP_I2C1_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SP_I2C1_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */
+#define ALT_L3_SEC_L4SP_I2C1_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */
+#define ALT_L3_SEC_L4SP_I2C1_MSB        3
+/* The width in bits of the ALT_L3_SEC_L4SP_I2C1 register field. */
+#define ALT_L3_SEC_L4SP_I2C1_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SP_I2C1 register field value. */
+#define ALT_L3_SEC_L4SP_I2C1_SET_MSK    0x00000008
+/* The mask used to clear the ALT_L3_SEC_L4SP_I2C1 register field value. */
+#define ALT_L3_SEC_L4SP_I2C1_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_L3_SEC_L4SP_I2C1 register field. */
+#define ALT_L3_SEC_L4SP_I2C1_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SP_I2C1 field value from a register. */
+#define ALT_L3_SEC_L4SP_I2C1_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_L3_SEC_L4SP_I2C1 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SP_I2C1_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : I2C2 (EMAC 0) Security - i2c2
+ * 
+ * Controls whether secure or non-secure masters can access the I2C2 (EMAC 0)
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                  
+ * :---------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SP_I2C2_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                 |       | master.                                      
+ *  ALT_L3_SEC_L4SP_I2C2_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                 |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SP_I2C2_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SP_I2C2_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */
+#define ALT_L3_SEC_L4SP_I2C2_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */
+#define ALT_L3_SEC_L4SP_I2C2_MSB        4
+/* The width in bits of the ALT_L3_SEC_L4SP_I2C2 register field. */
+#define ALT_L3_SEC_L4SP_I2C2_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SP_I2C2 register field value. */
+#define ALT_L3_SEC_L4SP_I2C2_SET_MSK    0x00000010
+/* The mask used to clear the ALT_L3_SEC_L4SP_I2C2 register field value. */
+#define ALT_L3_SEC_L4SP_I2C2_CLR_MSK    0xffffffef
+/* The reset value of the ALT_L3_SEC_L4SP_I2C2 register field. */
+#define ALT_L3_SEC_L4SP_I2C2_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SP_I2C2 field value from a register. */
+#define ALT_L3_SEC_L4SP_I2C2_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_L3_SEC_L4SP_I2C2 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SP_I2C2_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : I2C3 (EMAC 1) Security - i2c3
+ * 
+ * Controls whether secure or non-secure masters can access the I2C3 (EMAC 1)
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                  
+ * :---------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SP_I2C3_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                 |       | master.                                      
+ *  ALT_L3_SEC_L4SP_I2C3_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                 |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SP_I2C3_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SP_I2C3_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */
+#define ALT_L3_SEC_L4SP_I2C3_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */
+#define ALT_L3_SEC_L4SP_I2C3_MSB        5
+/* The width in bits of the ALT_L3_SEC_L4SP_I2C3 register field. */
+#define ALT_L3_SEC_L4SP_I2C3_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SP_I2C3 register field value. */
+#define ALT_L3_SEC_L4SP_I2C3_SET_MSK    0x00000020
+/* The mask used to clear the ALT_L3_SEC_L4SP_I2C3 register field value. */
+#define ALT_L3_SEC_L4SP_I2C3_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_L3_SEC_L4SP_I2C3 register field. */
+#define ALT_L3_SEC_L4SP_I2C3_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SP_I2C3 field value from a register. */
+#define ALT_L3_SEC_L4SP_I2C3_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_L3_SEC_L4SP_I2C3 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SP_I2C3_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : UART 0 Security - uart0
+ * 
+ * Controls whether secure or non-secure masters can access the UART 0 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                                  
+ * :----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SP_UART0_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                  |       | master.                                      
+ *  ALT_L3_SEC_L4SP_UART0_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                  |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_UART0
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SP_UART0_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_UART0
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SP_UART0_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */
+#define ALT_L3_SEC_L4SP_UART0_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */
+#define ALT_L3_SEC_L4SP_UART0_MSB        6
+/* The width in bits of the ALT_L3_SEC_L4SP_UART0 register field. */
+#define ALT_L3_SEC_L4SP_UART0_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SP_UART0 register field value. */
+#define ALT_L3_SEC_L4SP_UART0_SET_MSK    0x00000040
+/* The mask used to clear the ALT_L3_SEC_L4SP_UART0 register field value. */
+#define ALT_L3_SEC_L4SP_UART0_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_L3_SEC_L4SP_UART0 register field. */
+#define ALT_L3_SEC_L4SP_UART0_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SP_UART0 field value from a register. */
+#define ALT_L3_SEC_L4SP_UART0_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_L3_SEC_L4SP_UART0 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SP_UART0_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : UART 1 Security - uart1
+ * 
+ * Controls whether secure or non-secure masters can access the UART 1 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                                  
+ * :----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SP_UART1_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                  |       | master.                                      
+ *  ALT_L3_SEC_L4SP_UART1_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                  |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_UART1
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SP_UART1_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_UART1
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SP_UART1_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */
+#define ALT_L3_SEC_L4SP_UART1_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */
+#define ALT_L3_SEC_L4SP_UART1_MSB        7
+/* The width in bits of the ALT_L3_SEC_L4SP_UART1 register field. */
+#define ALT_L3_SEC_L4SP_UART1_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SP_UART1 register field value. */
+#define ALT_L3_SEC_L4SP_UART1_SET_MSK    0x00000080
+/* The mask used to clear the ALT_L3_SEC_L4SP_UART1 register field value. */
+#define ALT_L3_SEC_L4SP_UART1_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_L3_SEC_L4SP_UART1 register field. */
+#define ALT_L3_SEC_L4SP_UART1_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SP_UART1 field value from a register. */
+#define ALT_L3_SEC_L4SP_UART1_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_L3_SEC_L4SP_UART1 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SP_UART1_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : CAN 0 Security - can0
+ * 
+ * Controls whether secure or non-secure masters can access the CAN 0 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                  
+ * :---------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SP_CAN0_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                 |       | master.                                      
+ *  ALT_L3_SEC_L4SP_CAN0_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                 |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SP_CAN0_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SP_CAN0_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */
+#define ALT_L3_SEC_L4SP_CAN0_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */
+#define ALT_L3_SEC_L4SP_CAN0_MSB        8
+/* The width in bits of the ALT_L3_SEC_L4SP_CAN0 register field. */
+#define ALT_L3_SEC_L4SP_CAN0_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SP_CAN0 register field value. */
+#define ALT_L3_SEC_L4SP_CAN0_SET_MSK    0x00000100
+/* The mask used to clear the ALT_L3_SEC_L4SP_CAN0 register field value. */
+#define ALT_L3_SEC_L4SP_CAN0_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_L3_SEC_L4SP_CAN0 register field. */
+#define ALT_L3_SEC_L4SP_CAN0_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SP_CAN0 field value from a register. */
+#define ALT_L3_SEC_L4SP_CAN0_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_L3_SEC_L4SP_CAN0 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SP_CAN0_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : CAN 1 Security - can1
+ * 
+ * Controls whether secure or non-secure masters can access the CAN 1 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                  
+ * :---------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SP_CAN1_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                 |       | master.                                      
+ *  ALT_L3_SEC_L4SP_CAN1_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                 |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SP_CAN1_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SP_CAN1_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */
+#define ALT_L3_SEC_L4SP_CAN1_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */
+#define ALT_L3_SEC_L4SP_CAN1_MSB        9
+/* The width in bits of the ALT_L3_SEC_L4SP_CAN1 register field. */
+#define ALT_L3_SEC_L4SP_CAN1_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SP_CAN1 register field value. */
+#define ALT_L3_SEC_L4SP_CAN1_SET_MSK    0x00000200
+/* The mask used to clear the ALT_L3_SEC_L4SP_CAN1 register field value. */
+#define ALT_L3_SEC_L4SP_CAN1_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_L3_SEC_L4SP_CAN1 register field. */
+#define ALT_L3_SEC_L4SP_CAN1_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SP_CAN1 field value from a register. */
+#define ALT_L3_SEC_L4SP_CAN1_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_L3_SEC_L4SP_CAN1 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SP_CAN1_SET(value) (((value) << 9) & 0x00000200)
+
+/*
+ * Field : SP Timer 1 Security - sptimer1
+ * 
+ * Controls whether secure or non-secure masters can access the SP Timer 1 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                               | Value | Description                                  
+ * :-----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SP_SPTMR1_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                   |       | master.                                      
+ *  ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                   |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SP_SPTMR1_E_SECURE     0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
+#define ALT_L3_SEC_L4SP_SPTMR1_LSB        10
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
+#define ALT_L3_SEC_L4SP_SPTMR1_MSB        10
+/* The width in bits of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
+#define ALT_L3_SEC_L4SP_SPTMR1_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SP_SPTMR1 register field value. */
+#define ALT_L3_SEC_L4SP_SPTMR1_SET_MSK    0x00000400
+/* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR1 register field value. */
+#define ALT_L3_SEC_L4SP_SPTMR1_CLR_MSK    0xfffffbff
+/* The reset value of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
+#define ALT_L3_SEC_L4SP_SPTMR1_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SP_SPTMR1 field value from a register. */
+#define ALT_L3_SEC_L4SP_SPTMR1_GET(value) (((value) & 0x00000400) >> 10)
+/* Produces a ALT_L3_SEC_L4SP_SPTMR1 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SP_SPTMR1_SET(value) (((value) << 10) & 0x00000400)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_L4SP.
+ */
+struct ALT_L3_SEC_L4SP_s
+{
+    uint32_t  sdrregs  :  1;  /* SDRAM Registers Security */
+    uint32_t  sptimer0 :  1;  /* SP Timer 0 Security */
+    uint32_t  i2c0     :  1;  /* I2C0 Security */
+    uint32_t  i2c1     :  1;  /* I2C1 Security */
+    uint32_t  i2c2     :  1;  /* I2C2 (EMAC 0) Security */
+    uint32_t  i2c3     :  1;  /* I2C3 (EMAC 1) Security */
+    uint32_t  uart0    :  1;  /* UART 0 Security */
+    uint32_t  uart1    :  1;  /* UART 1 Security */
+    uint32_t  can0     :  1;  /* CAN 0 Security */
+    uint32_t  can1     :  1;  /* CAN 1 Security */
+    uint32_t  sptimer1 :  1;  /* SP Timer 1 Security */
+    uint32_t           : 21;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_L4SP. */
+typedef volatile struct ALT_L3_SEC_L4SP_s  ALT_L3_SEC_L4SP_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_L4SP register from the beginning of the component. */
+#define ALT_L3_SEC_L4SP_OFST        0x4
+
+/*
+ * Register : L4 MP Peripherals Security - l4mp
+ * 
+ * Controls security settings for L4 MP peripherals.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                   
+ * :--------|:-------|:------|:-------------------------------
+ *  [0]     | W      | 0x0   | FPGA Manager Register Security
+ *  [1]     | W      | 0x0   | DAP Security                  
+ *  [2]     | W      | 0x0   | QSPI Registers Security       
+ *  [3]     | W      | 0x0   | SDMMC Security                
+ *  [4]     | W      | 0x0   | EMAC 0 Security               
+ *  [5]     | W      | 0x0   | EMAC 1 Security               
+ *  [6]     | W      | 0x0   | ACP ID Mapper Security        
+ *  [7]     | W      | 0x0   | GPIO 0 Security               
+ *  [8]     | W      | 0x0   | GPIO 1 Security               
+ *  [9]     | W      | 0x0   | GPIO 2 Security               
+ *  [31:10] | ???    | 0x0   | *UNDEFINED*                   
+ * 
+ */
+/*
+ * Field : FPGA Manager Register Security - fpgamgrregs
+ * 
+ * Controls whether secure or non-secure masters can access the FPGA Manager
+ * Register slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                | Value | Description                                  
+ * :------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                    |       | master.                                      
+ *  ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                    |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE    0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
+#define ALT_L3_SEC_L4MP_FPGAMGR_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
+#define ALT_L3_SEC_L4MP_FPGAMGR_MSB        0
+/* The width in bits of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
+#define ALT_L3_SEC_L4MP_FPGAMGR_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MP_FPGAMGR register field value. */
+#define ALT_L3_SEC_L4MP_FPGAMGR_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_L4MP_FPGAMGR register field value. */
+#define ALT_L3_SEC_L4MP_FPGAMGR_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
+#define ALT_L3_SEC_L4MP_FPGAMGR_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MP_FPGAMGR field value from a register. */
+#define ALT_L3_SEC_L4MP_FPGAMGR_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_L4MP_FPGAMGR register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MP_FPGAMGR_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : DAP Security - dap
+ * 
+ * Controls whether secure or non-secure masters can access the DAP slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                            | Value | Description                                  
+ * :--------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MP_DAP_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                |       | master.                                      
+ *  ALT_L3_SEC_L4MP_DAP_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_DAP
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MP_DAP_E_SECURE    0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_DAP
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MP_DAP_E_NONSECURE 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_DAP register field. */
+#define ALT_L3_SEC_L4MP_DAP_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_DAP register field. */
+#define ALT_L3_SEC_L4MP_DAP_MSB        1
+/* The width in bits of the ALT_L3_SEC_L4MP_DAP register field. */
+#define ALT_L3_SEC_L4MP_DAP_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MP_DAP register field value. */
+#define ALT_L3_SEC_L4MP_DAP_SET_MSK    0x00000002
+/* The mask used to clear the ALT_L3_SEC_L4MP_DAP register field value. */
+#define ALT_L3_SEC_L4MP_DAP_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_L3_SEC_L4MP_DAP register field. */
+#define ALT_L3_SEC_L4MP_DAP_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MP_DAP field value from a register. */
+#define ALT_L3_SEC_L4MP_DAP_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_L3_SEC_L4MP_DAP register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MP_DAP_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : QSPI Registers Security - qspiregs
+ * 
+ * Controls whether secure or non-secure masters can access the QSPI Registers
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                  
+ * :---------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MP_QSPI_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                 |       | master.                                      
+ *  ALT_L3_SEC_L4MP_QSPI_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                 |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MP_QSPI_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MP_QSPI_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */
+#define ALT_L3_SEC_L4MP_QSPI_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */
+#define ALT_L3_SEC_L4MP_QSPI_MSB        2
+/* The width in bits of the ALT_L3_SEC_L4MP_QSPI register field. */
+#define ALT_L3_SEC_L4MP_QSPI_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MP_QSPI register field value. */
+#define ALT_L3_SEC_L4MP_QSPI_SET_MSK    0x00000004
+/* The mask used to clear the ALT_L3_SEC_L4MP_QSPI register field value. */
+#define ALT_L3_SEC_L4MP_QSPI_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_L3_SEC_L4MP_QSPI register field. */
+#define ALT_L3_SEC_L4MP_QSPI_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MP_QSPI field value from a register. */
+#define ALT_L3_SEC_L4MP_QSPI_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_L3_SEC_L4MP_QSPI register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MP_QSPI_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : SDMMC Security - sdmmc
+ * 
+ * Controls whether secure or non-secure masters can access the SDMMC slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                                  
+ * :----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MP_SDMMC_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                  |       | master.                                      
+ *  ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                  |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MP_SDMMC_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */
+#define ALT_L3_SEC_L4MP_SDMMC_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */
+#define ALT_L3_SEC_L4MP_SDMMC_MSB        3
+/* The width in bits of the ALT_L3_SEC_L4MP_SDMMC register field. */
+#define ALT_L3_SEC_L4MP_SDMMC_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MP_SDMMC register field value. */
+#define ALT_L3_SEC_L4MP_SDMMC_SET_MSK    0x00000008
+/* The mask used to clear the ALT_L3_SEC_L4MP_SDMMC register field value. */
+#define ALT_L3_SEC_L4MP_SDMMC_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_L3_SEC_L4MP_SDMMC register field. */
+#define ALT_L3_SEC_L4MP_SDMMC_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MP_SDMMC field value from a register. */
+#define ALT_L3_SEC_L4MP_SDMMC_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_L3_SEC_L4MP_SDMMC register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MP_SDMMC_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : EMAC 0 Security - emac0
+ * 
+ * Controls whether secure or non-secure masters can access the EMAC 0 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                                  
+ * :----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MP_EMAC0_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                  |       | master.                                      
+ *  ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                  |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MP_EMAC0_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */
+#define ALT_L3_SEC_L4MP_EMAC0_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */
+#define ALT_L3_SEC_L4MP_EMAC0_MSB        4
+/* The width in bits of the ALT_L3_SEC_L4MP_EMAC0 register field. */
+#define ALT_L3_SEC_L4MP_EMAC0_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MP_EMAC0 register field value. */
+#define ALT_L3_SEC_L4MP_EMAC0_SET_MSK    0x00000010
+/* The mask used to clear the ALT_L3_SEC_L4MP_EMAC0 register field value. */
+#define ALT_L3_SEC_L4MP_EMAC0_CLR_MSK    0xffffffef
+/* The reset value of the ALT_L3_SEC_L4MP_EMAC0 register field. */
+#define ALT_L3_SEC_L4MP_EMAC0_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MP_EMAC0 field value from a register. */
+#define ALT_L3_SEC_L4MP_EMAC0_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_L3_SEC_L4MP_EMAC0 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MP_EMAC0_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : EMAC 1 Security - emac1
+ * 
+ * Controls whether secure or non-secure masters can access the EMAC 1 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                                  
+ * :----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MP_EMAC1_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                  |       | master.                                      
+ *  ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                  |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MP_EMAC1_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */
+#define ALT_L3_SEC_L4MP_EMAC1_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */
+#define ALT_L3_SEC_L4MP_EMAC1_MSB        5
+/* The width in bits of the ALT_L3_SEC_L4MP_EMAC1 register field. */
+#define ALT_L3_SEC_L4MP_EMAC1_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MP_EMAC1 register field value. */
+#define ALT_L3_SEC_L4MP_EMAC1_SET_MSK    0x00000020
+/* The mask used to clear the ALT_L3_SEC_L4MP_EMAC1 register field value. */
+#define ALT_L3_SEC_L4MP_EMAC1_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_L3_SEC_L4MP_EMAC1 register field. */
+#define ALT_L3_SEC_L4MP_EMAC1_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MP_EMAC1 field value from a register. */
+#define ALT_L3_SEC_L4MP_EMAC1_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_L3_SEC_L4MP_EMAC1 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MP_EMAC1_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : ACP ID Mapper Security - acpidmap
+ * 
+ * Controls whether secure or non-secure masters can access the ACP ID Mapper
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                 | Value | Description                                  
+ * :-------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                     |       | master.                                      
+ *  ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                     |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
+#define ALT_L3_SEC_L4MP_ACPIDMAP_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
+#define ALT_L3_SEC_L4MP_ACPIDMAP_MSB        6
+/* The width in bits of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
+#define ALT_L3_SEC_L4MP_ACPIDMAP_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */
+#define ALT_L3_SEC_L4MP_ACPIDMAP_SET_MSK    0x00000040
+/* The mask used to clear the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */
+#define ALT_L3_SEC_L4MP_ACPIDMAP_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
+#define ALT_L3_SEC_L4MP_ACPIDMAP_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MP_ACPIDMAP field value from a register. */
+#define ALT_L3_SEC_L4MP_ACPIDMAP_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_L3_SEC_L4MP_ACPIDMAP register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MP_ACPIDMAP_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : GPIO 0 Security - gpio0
+ * 
+ * Controls whether secure or non-secure masters can access the GPIO 0 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                                  
+ * :----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MP_GPIO0_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                  |       | master.                                      
+ *  ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                  |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MP_GPIO0_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */
+#define ALT_L3_SEC_L4MP_GPIO0_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */
+#define ALT_L3_SEC_L4MP_GPIO0_MSB        7
+/* The width in bits of the ALT_L3_SEC_L4MP_GPIO0 register field. */
+#define ALT_L3_SEC_L4MP_GPIO0_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MP_GPIO0 register field value. */
+#define ALT_L3_SEC_L4MP_GPIO0_SET_MSK    0x00000080
+/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO0 register field value. */
+#define ALT_L3_SEC_L4MP_GPIO0_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_L3_SEC_L4MP_GPIO0 register field. */
+#define ALT_L3_SEC_L4MP_GPIO0_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MP_GPIO0 field value from a register. */
+#define ALT_L3_SEC_L4MP_GPIO0_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_L3_SEC_L4MP_GPIO0 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MP_GPIO0_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : GPIO 1 Security - gpio1
+ * 
+ * Controls whether secure or non-secure masters can access the GPIO 1 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                                  
+ * :----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MP_GPIO1_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                  |       | master.                                      
+ *  ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                  |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MP_GPIO1_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */
+#define ALT_L3_SEC_L4MP_GPIO1_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */
+#define ALT_L3_SEC_L4MP_GPIO1_MSB        8
+/* The width in bits of the ALT_L3_SEC_L4MP_GPIO1 register field. */
+#define ALT_L3_SEC_L4MP_GPIO1_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MP_GPIO1 register field value. */
+#define ALT_L3_SEC_L4MP_GPIO1_SET_MSK    0x00000100
+/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO1 register field value. */
+#define ALT_L3_SEC_L4MP_GPIO1_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_L3_SEC_L4MP_GPIO1 register field. */
+#define ALT_L3_SEC_L4MP_GPIO1_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MP_GPIO1 field value from a register. */
+#define ALT_L3_SEC_L4MP_GPIO1_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_L3_SEC_L4MP_GPIO1 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MP_GPIO1_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : GPIO 2 Security - gpio2
+ * 
+ * Controls whether secure or non-secure masters can access the GPIO 2 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                                  
+ * :----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4MP_GPIO2_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                  |       | master.                                      
+ *  ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                  |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4MP_GPIO2_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */
+#define ALT_L3_SEC_L4MP_GPIO2_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */
+#define ALT_L3_SEC_L4MP_GPIO2_MSB        9
+/* The width in bits of the ALT_L3_SEC_L4MP_GPIO2 register field. */
+#define ALT_L3_SEC_L4MP_GPIO2_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4MP_GPIO2 register field value. */
+#define ALT_L3_SEC_L4MP_GPIO2_SET_MSK    0x00000200
+/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO2 register field value. */
+#define ALT_L3_SEC_L4MP_GPIO2_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_L3_SEC_L4MP_GPIO2 register field. */
+#define ALT_L3_SEC_L4MP_GPIO2_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4MP_GPIO2 field value from a register. */
+#define ALT_L3_SEC_L4MP_GPIO2_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_L3_SEC_L4MP_GPIO2 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4MP_GPIO2_SET(value) (((value) << 9) & 0x00000200)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_L4MP.
+ */
+struct ALT_L3_SEC_L4MP_s
+{
+    uint32_t  fpgamgrregs :  1;  /* FPGA Manager Register Security */
+    uint32_t  dap         :  1;  /* DAP Security */
+    uint32_t  qspiregs    :  1;  /* QSPI Registers Security */
+    uint32_t  sdmmc       :  1;  /* SDMMC Security */
+    uint32_t  emac0       :  1;  /* EMAC 0 Security */
+    uint32_t  emac1       :  1;  /* EMAC 1 Security */
+    uint32_t  acpidmap    :  1;  /* ACP ID Mapper Security */
+    uint32_t  gpio0       :  1;  /* GPIO 0 Security */
+    uint32_t  gpio1       :  1;  /* GPIO 1 Security */
+    uint32_t  gpio2       :  1;  /* GPIO 2 Security */
+    uint32_t              : 22;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_L4MP. */
+typedef volatile struct ALT_L3_SEC_L4MP_s  ALT_L3_SEC_L4MP_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_L4MP register from the beginning of the component. */
+#define ALT_L3_SEC_L4MP_OFST        0x8
+
+/*
+ * Register : L4 OSC1 Peripherals Security - l4osc1
+ * 
+ * Controls security settings for L4 OSC1 peripherals.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                 
+ * :-------|:-------|:------|:-----------------------------
+ *  [0]    | W      | 0x0   | L4 Watchdog Timer 0 Security
+ *  [1]    | W      | 0x0   | L4 Watchdog Timer 0 Security
+ *  [2]    | W      | 0x0   | Clock Manager Security      
+ *  [3]    | W      | 0x0   | Reset Manager Security      
+ *  [4]    | W      | 0x0   | System Manager Security     
+ *  [5]    | W      | 0x0   | OSC1 Timer 0 Security       
+ *  [6]    | W      | 0x0   | OSC1 Timer 1 Security       
+ *  [31:7] | ???    | 0x0   | *UNDEFINED*                 
+ * 
+ */
+/*
+ * Field : L4 Watchdog Timer 0 Security - l4wd0
+ * 
+ * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                | Value | Description                                  
+ * :------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                    |       | master.                                      
+ *  ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                    |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE    0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
+#define ALT_L3_SEC_L4OSC1_L4WD0_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
+#define ALT_L3_SEC_L4OSC1_L4WD0_MSB        0
+/* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
+#define ALT_L3_SEC_L4OSC1_L4WD0_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */
+#define ALT_L3_SEC_L4OSC1_L4WD0_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */
+#define ALT_L3_SEC_L4OSC1_L4WD0_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
+#define ALT_L3_SEC_L4OSC1_L4WD0_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4OSC1_L4WD0 field value from a register. */
+#define ALT_L3_SEC_L4OSC1_L4WD0_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_L4OSC1_L4WD0 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4OSC1_L4WD0_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : L4 Watchdog Timer 0 Security - l4wd1
+ * 
+ * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                | Value | Description                                  
+ * :------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                    |       | master.                                      
+ *  ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                    |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE    0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
+#define ALT_L3_SEC_L4OSC1_L4WD1_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
+#define ALT_L3_SEC_L4OSC1_L4WD1_MSB        1
+/* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
+#define ALT_L3_SEC_L4OSC1_L4WD1_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */
+#define ALT_L3_SEC_L4OSC1_L4WD1_SET_MSK    0x00000002
+/* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */
+#define ALT_L3_SEC_L4OSC1_L4WD1_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
+#define ALT_L3_SEC_L4OSC1_L4WD1_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4OSC1_L4WD1 field value from a register. */
+#define ALT_L3_SEC_L4OSC1_L4WD1_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_L3_SEC_L4OSC1_L4WD1 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4OSC1_L4WD1_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : Clock Manager Security - clkmgr
+ * 
+ * Controls whether secure or non-secure masters can access the Clock Manager
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                 | Value | Description                                  
+ * :-------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                     |       | master.                                      
+ *  ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                     |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
+#define ALT_L3_SEC_L4OSC1_CLKMGR_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
+#define ALT_L3_SEC_L4OSC1_CLKMGR_MSB        2
+/* The width in bits of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
+#define ALT_L3_SEC_L4OSC1_CLKMGR_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */
+#define ALT_L3_SEC_L4OSC1_CLKMGR_SET_MSK    0x00000004
+/* The mask used to clear the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */
+#define ALT_L3_SEC_L4OSC1_CLKMGR_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
+#define ALT_L3_SEC_L4OSC1_CLKMGR_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4OSC1_CLKMGR field value from a register. */
+#define ALT_L3_SEC_L4OSC1_CLKMGR_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_L3_SEC_L4OSC1_CLKMGR register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4OSC1_CLKMGR_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : Reset Manager Security - rstmgr
+ * 
+ * Controls whether secure or non-secure masters can access the Reset Manager
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                 | Value | Description                                  
+ * :-------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                     |       | master.                                      
+ *  ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                     |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
+#define ALT_L3_SEC_L4OSC1_RSTMGR_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
+#define ALT_L3_SEC_L4OSC1_RSTMGR_MSB        3
+/* The width in bits of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
+#define ALT_L3_SEC_L4OSC1_RSTMGR_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */
+#define ALT_L3_SEC_L4OSC1_RSTMGR_SET_MSK    0x00000008
+/* The mask used to clear the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */
+#define ALT_L3_SEC_L4OSC1_RSTMGR_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
+#define ALT_L3_SEC_L4OSC1_RSTMGR_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4OSC1_RSTMGR field value from a register. */
+#define ALT_L3_SEC_L4OSC1_RSTMGR_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_L3_SEC_L4OSC1_RSTMGR register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4OSC1_RSTMGR_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : System Manager Security - sysmgr
+ * 
+ * Controls whether secure or non-secure masters can access the System Manager
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                 | Value | Description                                  
+ * :-------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                     |       | master.                                      
+ *  ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                     |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
+#define ALT_L3_SEC_L4OSC1_SYSMGR_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
+#define ALT_L3_SEC_L4OSC1_SYSMGR_MSB        4
+/* The width in bits of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
+#define ALT_L3_SEC_L4OSC1_SYSMGR_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */
+#define ALT_L3_SEC_L4OSC1_SYSMGR_SET_MSK    0x00000010
+/* The mask used to clear the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */
+#define ALT_L3_SEC_L4OSC1_SYSMGR_CLR_MSK    0xffffffef
+/* The reset value of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
+#define ALT_L3_SEC_L4OSC1_SYSMGR_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4OSC1_SYSMGR field value from a register. */
+#define ALT_L3_SEC_L4OSC1_SYSMGR_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_L3_SEC_L4OSC1_SYSMGR register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4OSC1_SYSMGR_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : OSC1 Timer 0 Security - osc1timer0
+ * 
+ * Controls whether secure or non-secure masters can access the OSC1 Timer 0 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                   | Value | Description                                  
+ * :---------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                       |       | master.                                      
+ *  ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                       |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE     0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR0_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR0_MSB        5
+/* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR0_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET_MSK    0x00000020
+/* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR0_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR0_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR0 field value from a register. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR0_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : OSC1 Timer 1 Security - osc1timer1
+ * 
+ * Controls whether secure or non-secure masters can access the OSC1 Timer 1 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                   | Value | Description                                  
+ * :---------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                       |       | master.                                      
+ *  ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                       |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE     0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR1_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR1_MSB        6
+/* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR1_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET_MSK    0x00000040
+/* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR1_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR1_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR1 field value from a register. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR1_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET(value) (((value) << 6) & 0x00000040)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_L4OSC1.
+ */
+struct ALT_L3_SEC_L4OSC1_s
+{
+    uint32_t  l4wd0      :  1;  /* L4 Watchdog Timer 0 Security */
+    uint32_t  l4wd1      :  1;  /* L4 Watchdog Timer 0 Security */
+    uint32_t  clkmgr     :  1;  /* Clock Manager Security */
+    uint32_t  rstmgr     :  1;  /* Reset Manager Security */
+    uint32_t  sysmgr     :  1;  /* System Manager Security */
+    uint32_t  osc1timer0 :  1;  /* OSC1 Timer 0 Security */
+    uint32_t  osc1timer1 :  1;  /* OSC1 Timer 1 Security */
+    uint32_t             : 25;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_L4OSC1. */
+typedef volatile struct ALT_L3_SEC_L4OSC1_s  ALT_L3_SEC_L4OSC1_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_L4OSC1 register from the beginning of the component. */
+#define ALT_L3_SEC_L4OSC1_OFST        0xc
+
+/*
+ * Register : L4 SPIM Peripherals Security - l4spim
+ * 
+ * Controls security settings for L4 SPIM peripherals.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description          
+ * :-------|:-------|:------|:----------------------
+ *  [0]    | W      | 0x0   | SPI Master 0 Security
+ *  [1]    | W      | 0x0   | SPI Master 1 Security
+ *  [2]    | W      | 0x0   | Scan Manager Security
+ *  [31:3] | ???    | 0x0   | *UNDEFINED*          
+ * 
+ */
+/*
+ * Field : SPI Master 0 Security - spim0
+ * 
+ * Controls whether secure or non-secure masters can access the SPI Master 0 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                | Value | Description                                  
+ * :------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                    |       | master.                                      
+ *  ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                    |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE    0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
+#define ALT_L3_SEC_L4SPIM_SPIM0_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
+#define ALT_L3_SEC_L4SPIM_SPIM0_MSB        0
+/* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
+#define ALT_L3_SEC_L4SPIM_SPIM0_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */
+#define ALT_L3_SEC_L4SPIM_SPIM0_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */
+#define ALT_L3_SEC_L4SPIM_SPIM0_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
+#define ALT_L3_SEC_L4SPIM_SPIM0_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SPIM_SPIM0 field value from a register. */
+#define ALT_L3_SEC_L4SPIM_SPIM0_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_L4SPIM_SPIM0 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SPIM_SPIM0_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : SPI Master 1 Security - spim1
+ * 
+ * Controls whether secure or non-secure masters can access the SPI Master 1 slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                | Value | Description                                  
+ * :------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                    |       | master.                                      
+ *  ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                    |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE    0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
+#define ALT_L3_SEC_L4SPIM_SPIM1_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
+#define ALT_L3_SEC_L4SPIM_SPIM1_MSB        1
+/* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
+#define ALT_L3_SEC_L4SPIM_SPIM1_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */
+#define ALT_L3_SEC_L4SPIM_SPIM1_SET_MSK    0x00000002
+/* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */
+#define ALT_L3_SEC_L4SPIM_SPIM1_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
+#define ALT_L3_SEC_L4SPIM_SPIM1_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SPIM_SPIM1 field value from a register. */
+#define ALT_L3_SEC_L4SPIM_SPIM1_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_L3_SEC_L4SPIM_SPIM1 register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SPIM_SPIM1_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : Scan Manager Security - scanmgr
+ * 
+ * Controls whether secure or non-secure masters can access the Scan Manager slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                  | Value | Description                                  
+ * :--------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                      |       | master.                                      
+ *  ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                      |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
+#define ALT_L3_SEC_L4SPIM_SCANMGR_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
+#define ALT_L3_SEC_L4SPIM_SCANMGR_MSB        2
+/* The width in bits of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
+#define ALT_L3_SEC_L4SPIM_SCANMGR_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */
+#define ALT_L3_SEC_L4SPIM_SCANMGR_SET_MSK    0x00000004
+/* The mask used to clear the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */
+#define ALT_L3_SEC_L4SPIM_SCANMGR_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
+#define ALT_L3_SEC_L4SPIM_SCANMGR_RESET      0x0
+/* Extracts the ALT_L3_SEC_L4SPIM_SCANMGR field value from a register. */
+#define ALT_L3_SEC_L4SPIM_SCANMGR_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_L3_SEC_L4SPIM_SCANMGR register field value suitable for setting the register. */
+#define ALT_L3_SEC_L4SPIM_SCANMGR_SET(value) (((value) << 2) & 0x00000004)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_L4SPIM.
+ */
+struct ALT_L3_SEC_L4SPIM_s
+{
+    uint32_t  spim0   :  1;  /* SPI Master 0 Security */
+    uint32_t  spim1   :  1;  /* SPI Master 1 Security */
+    uint32_t  scanmgr :  1;  /* Scan Manager Security */
+    uint32_t          : 29;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_L4SPIM. */
+typedef volatile struct ALT_L3_SEC_L4SPIM_s  ALT_L3_SEC_L4SPIM_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_L4SPIM register from the beginning of the component. */
+#define ALT_L3_SEC_L4SPIM_OFST        0x10
+
+/*
+ * Register : STM Peripheral Security - stm
+ * 
+ * Controls security settings for STM peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description 
+ * :-------|:-------|:------|:-------------
+ *  [0]    | W      | 0x0   | STM Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED* 
+ * 
+ */
+/*
+ * Field : STM Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the STM slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                         | Value | Description                                  
+ * :-----------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_STM_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                             |       | master.                                      
+ *  ALT_L3_SEC_STM_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                             |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_STM_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_STM_S_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_STM_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_STM_S_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_STM_S register field. */
+#define ALT_L3_SEC_STM_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_STM_S register field. */
+#define ALT_L3_SEC_STM_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_STM_S register field. */
+#define ALT_L3_SEC_STM_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_STM_S register field value. */
+#define ALT_L3_SEC_STM_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_STM_S register field value. */
+#define ALT_L3_SEC_STM_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_STM_S register field. */
+#define ALT_L3_SEC_STM_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_STM_S field value from a register. */
+#define ALT_L3_SEC_STM_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_STM_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_STM_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_STM.
+ */
+struct ALT_L3_SEC_STM_s
+{
+    uint32_t  s :  1;  /* STM Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_STM. */
+typedef volatile struct ALT_L3_SEC_STM_s  ALT_L3_SEC_STM_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_STM register from the beginning of the component. */
+#define ALT_L3_SEC_STM_OFST        0x14
+
+/*
+ * Register : LWHPS2FPGA AXI Bridge Registers Peripheral Security - lwhps2fpgaregs
+ * 
+ * Controls security settings for LWHPS2FPGA AXI Bridge Registers peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                             
+ * :-------|:-------|:------|:-----------------------------------------
+ *  [0]    | W      | 0x0   | LWHPS2FPGA AXI Bridge Registers Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*                             
+ * 
+ */
+/*
+ * Field : LWHPS2FPGA AXI Bridge Registers Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the LWHPS2FPGA AXI
+ * Bridge Registers slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                           | Value | Description                                  
+ * :-------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_LWH2F_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                               |       | master.                                      
+ *  ALT_L3_SEC_LWH2F_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                               |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_LWH2F_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_LWH2F_S_E_SECURE     0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_LWH2F_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_LWH2F_S_E_NONSECURE  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_LWH2F_S register field. */
+#define ALT_L3_SEC_LWH2F_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_LWH2F_S register field. */
+#define ALT_L3_SEC_LWH2F_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_LWH2F_S register field. */
+#define ALT_L3_SEC_LWH2F_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_LWH2F_S register field value. */
+#define ALT_L3_SEC_LWH2F_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_LWH2F_S register field value. */
+#define ALT_L3_SEC_LWH2F_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_LWH2F_S register field. */
+#define ALT_L3_SEC_LWH2F_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_LWH2F_S field value from a register. */
+#define ALT_L3_SEC_LWH2F_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_LWH2F_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_LWH2F_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_LWH2F.
+ */
+struct ALT_L3_SEC_LWH2F_s
+{
+    uint32_t  s :  1;  /* LWHPS2FPGA AXI Bridge Registers Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_LWH2F. */
+typedef volatile struct ALT_L3_SEC_LWH2F_s  ALT_L3_SEC_LWH2F_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_LWH2F register from the beginning of the component. */
+#define ALT_L3_SEC_LWH2F_OFST        0x18
+
+/*
+ * Register : USB1 Registers Peripheral Security - usb1
+ * 
+ * Controls security settings for USB1 Registers peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description            
+ * :-------|:-------|:------|:------------------------
+ *  [0]    | W      | 0x0   | USB1 Registers Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*            
+ * 
+ */
+/*
+ * Field : USB1 Registers Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the USB1 Registers
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                          | Value | Description                                  
+ * :------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_USB1_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                              |       | master.                                      
+ *  ALT_L3_SEC_USB1_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                              |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_USB1_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_USB1_S_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_USB1_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_USB1_S_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB1_S register field. */
+#define ALT_L3_SEC_USB1_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB1_S register field. */
+#define ALT_L3_SEC_USB1_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_USB1_S register field. */
+#define ALT_L3_SEC_USB1_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_USB1_S register field value. */
+#define ALT_L3_SEC_USB1_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_USB1_S register field value. */
+#define ALT_L3_SEC_USB1_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_USB1_S register field. */
+#define ALT_L3_SEC_USB1_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_USB1_S field value from a register. */
+#define ALT_L3_SEC_USB1_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_USB1_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_USB1_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_USB1.
+ */
+struct ALT_L3_SEC_USB1_s
+{
+    uint32_t  s :  1;  /* USB1 Registers Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_USB1. */
+typedef volatile struct ALT_L3_SEC_USB1_s  ALT_L3_SEC_USB1_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_USB1 register from the beginning of the component. */
+#define ALT_L3_SEC_USB1_OFST        0x20
+
+/*
+ * Register : NAND Flash Controller Data Peripheral Security - nanddata
+ * 
+ * Controls security settings for NAND Flash Controller Data peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                        
+ * :-------|:-------|:------|:------------------------------------
+ *  [0]    | W      | 0x0   | NAND Flash Controller Data Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*                        
+ * 
+ */
+/*
+ * Field : NAND Flash Controller Data Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the NAND Flash
+ * Controller Data slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                                  
+ * :----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_NANDDATA_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                  |       | master.                                      
+ *  ALT_L3_SEC_NANDDATA_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                  |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_NANDDATA_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_NANDDATA_S_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_NANDDATA_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_NANDDATA_S_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NANDDATA_S register field. */
+#define ALT_L3_SEC_NANDDATA_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NANDDATA_S register field. */
+#define ALT_L3_SEC_NANDDATA_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_NANDDATA_S register field. */
+#define ALT_L3_SEC_NANDDATA_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_NANDDATA_S register field value. */
+#define ALT_L3_SEC_NANDDATA_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_NANDDATA_S register field value. */
+#define ALT_L3_SEC_NANDDATA_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_NANDDATA_S register field. */
+#define ALT_L3_SEC_NANDDATA_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_NANDDATA_S field value from a register. */
+#define ALT_L3_SEC_NANDDATA_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_NANDDATA_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_NANDDATA_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_NANDDATA.
+ */
+struct ALT_L3_SEC_NANDDATA_s
+{
+    uint32_t  s :  1;  /* NAND Flash Controller Data Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_NANDDATA. */
+typedef volatile struct ALT_L3_SEC_NANDDATA_s  ALT_L3_SEC_NANDDATA_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_NANDDATA register from the beginning of the component. */
+#define ALT_L3_SEC_NANDDATA_OFST        0x24
+
+/*
+ * Register : USB0 Registers Peripheral Security - usb0
+ * 
+ * Controls security settings for USB0 Registers peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description            
+ * :-------|:-------|:------|:------------------------
+ *  [0]    | W      | 0x0   | USB0 Registers Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*            
+ * 
+ */
+/*
+ * Field : USB0 Registers Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the USB0 Registers
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                          | Value | Description                                  
+ * :------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_USB0_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                              |       | master.                                      
+ *  ALT_L3_SEC_USB0_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                              |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_USB0_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_USB0_S_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_USB0_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_USB0_S_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB0_S register field. */
+#define ALT_L3_SEC_USB0_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB0_S register field. */
+#define ALT_L3_SEC_USB0_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_USB0_S register field. */
+#define ALT_L3_SEC_USB0_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_USB0_S register field value. */
+#define ALT_L3_SEC_USB0_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_USB0_S register field value. */
+#define ALT_L3_SEC_USB0_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_USB0_S register field. */
+#define ALT_L3_SEC_USB0_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_USB0_S field value from a register. */
+#define ALT_L3_SEC_USB0_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_USB0_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_USB0_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_USB0.
+ */
+struct ALT_L3_SEC_USB0_s
+{
+    uint32_t  s :  1;  /* USB0 Registers Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_USB0. */
+typedef volatile struct ALT_L3_SEC_USB0_s  ALT_L3_SEC_USB0_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_USB0 register from the beginning of the component. */
+#define ALT_L3_SEC_USB0_OFST        0x78
+
+/*
+ * Register : NAND Flash Controller Registers Peripheral Security - nandregs
+ * 
+ * Controls security settings for NAND Flash Controller Registers peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                             
+ * :-------|:-------|:------|:-----------------------------------------
+ *  [0]    | W      | 0x0   | NAND Flash Controller Registers Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*                             
+ * 
+ */
+/*
+ * Field : NAND Flash Controller Registers Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the NAND Flash
+ * Controller Registers slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                          | Value | Description                                  
+ * :------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_NAND_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                              |       | master.                                      
+ *  ALT_L3_SEC_NAND_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                              |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_NAND_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_NAND_S_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_NAND_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_NAND_S_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NAND_S register field. */
+#define ALT_L3_SEC_NAND_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NAND_S register field. */
+#define ALT_L3_SEC_NAND_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_NAND_S register field. */
+#define ALT_L3_SEC_NAND_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_NAND_S register field value. */
+#define ALT_L3_SEC_NAND_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_NAND_S register field value. */
+#define ALT_L3_SEC_NAND_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_NAND_S register field. */
+#define ALT_L3_SEC_NAND_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_NAND_S field value from a register. */
+#define ALT_L3_SEC_NAND_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_NAND_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_NAND_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_NAND.
+ */
+struct ALT_L3_SEC_NAND_s
+{
+    uint32_t  s :  1;  /* NAND Flash Controller Registers Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_NAND. */
+typedef volatile struct ALT_L3_SEC_NAND_s  ALT_L3_SEC_NAND_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_NAND register from the beginning of the component. */
+#define ALT_L3_SEC_NAND_OFST        0x7c
+
+/*
+ * Register : QSPI Flash Controller Data Peripheral Security - qspidata
+ * 
+ * Controls security settings for QSPI Flash Controller Data peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                        
+ * :-------|:-------|:------|:------------------------------------
+ *  [0]    | W      | 0x0   | QSPI Flash Controller Data Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*                        
+ * 
+ */
+/*
+ * Field : QSPI Flash Controller Data Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the QSPI Flash
+ * Controller Data slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                                  
+ * :----------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_QSPIDATA_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                  |       | master.                                      
+ *  ALT_L3_SEC_QSPIDATA_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                  |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_QSPIDATA_S_E_SECURE      0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_QSPIDATA_S_E_NONSECURE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */
+#define ALT_L3_SEC_QSPIDATA_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */
+#define ALT_L3_SEC_QSPIDATA_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_QSPIDATA_S register field. */
+#define ALT_L3_SEC_QSPIDATA_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_QSPIDATA_S register field value. */
+#define ALT_L3_SEC_QSPIDATA_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_QSPIDATA_S register field value. */
+#define ALT_L3_SEC_QSPIDATA_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_QSPIDATA_S register field. */
+#define ALT_L3_SEC_QSPIDATA_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_QSPIDATA_S field value from a register. */
+#define ALT_L3_SEC_QSPIDATA_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_QSPIDATA_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_QSPIDATA_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_QSPIDATA.
+ */
+struct ALT_L3_SEC_QSPIDATA_s
+{
+    uint32_t  s :  1;  /* QSPI Flash Controller Data Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_QSPIDATA. */
+typedef volatile struct ALT_L3_SEC_QSPIDATA_s  ALT_L3_SEC_QSPIDATA_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_QSPIDATA register from the beginning of the component. */
+#define ALT_L3_SEC_QSPIDATA_OFST        0x80
+
+/*
+ * Register : FPGA Manager Data Peripheral Security - fpgamgrdata
+ * 
+ * Controls security settings for FPGA Manager Data peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description               
+ * :-------|:-------|:------|:---------------------------
+ *  [0]    | W      | 0x0   | FPGA Manager Data Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*               
+ * 
+ */
+/*
+ * Field : FPGA Manager Data Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the FPGA Manager Data
+ * slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                 | Value | Description                                  
+ * :-------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                     |       | master.                                      
+ *  ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                     |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
+#define ALT_L3_SEC_FPGAMGRDATA_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
+#define ALT_L3_SEC_FPGAMGRDATA_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
+#define ALT_L3_SEC_FPGAMGRDATA_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_FPGAMGRDATA_S register field value. */
+#define ALT_L3_SEC_FPGAMGRDATA_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_FPGAMGRDATA_S register field value. */
+#define ALT_L3_SEC_FPGAMGRDATA_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
+#define ALT_L3_SEC_FPGAMGRDATA_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_FPGAMGRDATA_S field value from a register. */
+#define ALT_L3_SEC_FPGAMGRDATA_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_FPGAMGRDATA_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_FPGAMGRDATA_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_FPGAMGRDATA.
+ */
+struct ALT_L3_SEC_FPGAMGRDATA_s
+{
+    uint32_t  s :  1;  /* FPGA Manager Data Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_FPGAMGRDATA. */
+typedef volatile struct ALT_L3_SEC_FPGAMGRDATA_s  ALT_L3_SEC_FPGAMGRDATA_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_FPGAMGRDATA register from the beginning of the component. */
+#define ALT_L3_SEC_FPGAMGRDATA_OFST        0x84
+
+/*
+ * Register : HPS2FPGA AXI Bridge Registers Peripheral Security - hps2fpgaregs
+ * 
+ * Controls security settings for HPS2FPGA AXI Bridge Registers peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                           
+ * :-------|:-------|:------|:---------------------------------------
+ *  [0]    | W      | 0x0   | HPS2FPGA AXI Bridge Registers Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*                           
+ * 
+ */
+/*
+ * Field : HPS2FPGA AXI Bridge Registers Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the HPS2FPGA AXI Bridge
+ * Registers slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                         | Value | Description                                  
+ * :-----------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_H2F_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                             |       | master.                                      
+ *  ALT_L3_SEC_H2F_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                             |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_H2F_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_H2F_S_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_H2F_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_H2F_S_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_H2F_S register field. */
+#define ALT_L3_SEC_H2F_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_H2F_S register field. */
+#define ALT_L3_SEC_H2F_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_H2F_S register field. */
+#define ALT_L3_SEC_H2F_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_H2F_S register field value. */
+#define ALT_L3_SEC_H2F_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_H2F_S register field value. */
+#define ALT_L3_SEC_H2F_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_H2F_S register field. */
+#define ALT_L3_SEC_H2F_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_H2F_S field value from a register. */
+#define ALT_L3_SEC_H2F_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_H2F_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_H2F_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_H2F.
+ */
+struct ALT_L3_SEC_H2F_s
+{
+    uint32_t  s :  1;  /* HPS2FPGA AXI Bridge Registers Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_H2F. */
+typedef volatile struct ALT_L3_SEC_H2F_s  ALT_L3_SEC_H2F_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_H2F register from the beginning of the component. */
+#define ALT_L3_SEC_H2F_OFST        0x88
+
+/*
+ * Register : MPU ACP Peripheral Security - acp
+ * 
+ * Controls security settings for MPU ACP peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description     
+ * :-------|:-------|:------|:-----------------
+ *  [0]    | W      | 0x0   | MPU ACP Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*     
+ * 
+ */
+/*
+ * Field : MPU ACP Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the MPU ACP slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                         | Value | Description                                  
+ * :-----------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_ACP_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                             |       | master.                                      
+ *  ALT_L3_SEC_ACP_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                             |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_ACP_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_ACP_S_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_ACP_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_ACP_S_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ACP_S register field. */
+#define ALT_L3_SEC_ACP_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ACP_S register field. */
+#define ALT_L3_SEC_ACP_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_ACP_S register field. */
+#define ALT_L3_SEC_ACP_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_ACP_S register field value. */
+#define ALT_L3_SEC_ACP_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_ACP_S register field value. */
+#define ALT_L3_SEC_ACP_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_ACP_S register field. */
+#define ALT_L3_SEC_ACP_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_ACP_S field value from a register. */
+#define ALT_L3_SEC_ACP_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_ACP_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_ACP_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_ACP.
+ */
+struct ALT_L3_SEC_ACP_s
+{
+    uint32_t  s :  1;  /* MPU ACP Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_ACP. */
+typedef volatile struct ALT_L3_SEC_ACP_s  ALT_L3_SEC_ACP_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_ACP register from the beginning of the component. */
+#define ALT_L3_SEC_ACP_OFST        0x8c
+
+/*
+ * Register : ROM Peripheral Security - rom
+ * 
+ * Controls security settings for ROM peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description 
+ * :-------|:-------|:------|:-------------
+ *  [0]    | W      | 0x0   | ROM Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED* 
+ * 
+ */
+/*
+ * Field : ROM Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the ROM slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                         | Value | Description                                  
+ * :-----------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_ROM_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                             |       | master.                                      
+ *  ALT_L3_SEC_ROM_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                             |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_ROM_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_ROM_S_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_ROM_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_ROM_S_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ROM_S register field. */
+#define ALT_L3_SEC_ROM_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ROM_S register field. */
+#define ALT_L3_SEC_ROM_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_ROM_S register field. */
+#define ALT_L3_SEC_ROM_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_ROM_S register field value. */
+#define ALT_L3_SEC_ROM_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_ROM_S register field value. */
+#define ALT_L3_SEC_ROM_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_ROM_S register field. */
+#define ALT_L3_SEC_ROM_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_ROM_S field value from a register. */
+#define ALT_L3_SEC_ROM_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_ROM_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_ROM_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_ROM.
+ */
+struct ALT_L3_SEC_ROM_s
+{
+    uint32_t  s :  1;  /* ROM Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_ROM. */
+typedef volatile struct ALT_L3_SEC_ROM_s  ALT_L3_SEC_ROM_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_ROM register from the beginning of the component. */
+#define ALT_L3_SEC_ROM_OFST        0x90
+
+/*
+ * Register : On-chip RAM Peripheral Security - ocram
+ * 
+ * Controls security settings for On-chip RAM peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description         
+ * :-------|:-------|:------|:---------------------
+ *  [0]    | W      | 0x0   | On-chip RAM Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*         
+ * 
+ */
+/*
+ * Field : On-chip RAM Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the On-chip RAM slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                           | Value | Description                                  
+ * :-------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_OCRAM_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                               |       | master.                                      
+ *  ALT_L3_SEC_OCRAM_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                               |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_OCRAM_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_OCRAM_S_E_SECURE     0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_OCRAM_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_OCRAM_S_E_NONSECURE  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_OCRAM_S register field. */
+#define ALT_L3_SEC_OCRAM_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_OCRAM_S register field. */
+#define ALT_L3_SEC_OCRAM_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_OCRAM_S register field. */
+#define ALT_L3_SEC_OCRAM_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_OCRAM_S register field value. */
+#define ALT_L3_SEC_OCRAM_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_OCRAM_S register field value. */
+#define ALT_L3_SEC_OCRAM_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_OCRAM_S register field. */
+#define ALT_L3_SEC_OCRAM_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_OCRAM_S field value from a register. */
+#define ALT_L3_SEC_OCRAM_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_OCRAM_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_OCRAM_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_OCRAM.
+ */
+struct ALT_L3_SEC_OCRAM_s
+{
+    uint32_t  s :  1;  /* On-chip RAM Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_OCRAM. */
+typedef volatile struct ALT_L3_SEC_OCRAM_s  ALT_L3_SEC_OCRAM_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_OCRAM register from the beginning of the component. */
+#define ALT_L3_SEC_OCRAM_OFST        0x94
+
+/*
+ * Register : SDRAM Data Peripheral Security - sdrdata
+ * 
+ * Controls security settings for SDRAM Data peripheral.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description        
+ * :-------|:-------|:------|:--------------------
+ *  [0]    | W      | 0x0   | SDRAM Data Security
+ *  [31:1] | ???    | 0x0   | *UNDEFINED*        
+ * 
+ */
+/*
+ * Field : SDRAM Data Security - s
+ * 
+ * Controls whether secure or non-secure masters can access the SDRAM Data slave.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                  
+ * :---------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_SEC_SDRDATA_S_E_SECURE    | 0x0   | The slave can only be accessed by a secure   
+ * :                                 |       | master.                                      
+ *  ALT_L3_SEC_SDRDATA_S_E_NONSECURE | 0x1   | The slave can only be accessed by a secure or
+ * :                                 |       | non-secure masters.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_SEC_SDRDATA_S
+ * 
+ * The slave can only be accessed by a secure master.
+ */
+#define ALT_L3_SEC_SDRDATA_S_E_SECURE       0x0
+/*
+ * Enumerated value for register field ALT_L3_SEC_SDRDATA_S
+ * 
+ * The slave can only be accessed by a secure or non-secure masters.
+ */
+#define ALT_L3_SEC_SDRDATA_S_E_NONSECURE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_SDRDATA_S register field. */
+#define ALT_L3_SEC_SDRDATA_S_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_SDRDATA_S register field. */
+#define ALT_L3_SEC_SDRDATA_S_MSB        0
+/* The width in bits of the ALT_L3_SEC_SDRDATA_S register field. */
+#define ALT_L3_SEC_SDRDATA_S_WIDTH      1
+/* The mask used to set the ALT_L3_SEC_SDRDATA_S register field value. */
+#define ALT_L3_SEC_SDRDATA_S_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_SEC_SDRDATA_S register field value. */
+#define ALT_L3_SEC_SDRDATA_S_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_SEC_SDRDATA_S register field. */
+#define ALT_L3_SEC_SDRDATA_S_RESET      0x0
+/* Extracts the ALT_L3_SEC_SDRDATA_S field value from a register. */
+#define ALT_L3_SEC_SDRDATA_S_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_SEC_SDRDATA_S register field value suitable for setting the register. */
+#define ALT_L3_SEC_SDRDATA_S_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_SEC_SDRDATA.
+ */
+struct ALT_L3_SEC_SDRDATA_s
+{
+    uint32_t  s :  1;  /* SDRAM Data Security */
+    uint32_t    : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_SEC_SDRDATA. */
+typedef volatile struct ALT_L3_SEC_SDRDATA_s  ALT_L3_SEC_SDRDATA_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_SEC_SDRDATA register from the beginning of the component. */
+#define ALT_L3_SEC_SDRDATA_OFST        0x98
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SECGRP.
+ */
+struct ALT_L3_SECGRP_s
+{
+    volatile ALT_L3_SEC_L4MAIN_t       l4main;              /* ALT_L3_SEC_L4MAIN */
+    volatile ALT_L3_SEC_L4SP_t         l4sp;                /* ALT_L3_SEC_L4SP */
+    volatile ALT_L3_SEC_L4MP_t         l4mp;                /* ALT_L3_SEC_L4MP */
+    volatile ALT_L3_SEC_L4OSC1_t       l4osc1;              /* ALT_L3_SEC_L4OSC1 */
+    volatile ALT_L3_SEC_L4SPIM_t       l4spim;              /* ALT_L3_SEC_L4SPIM */
+    volatile ALT_L3_SEC_STM_t          stm;                 /* ALT_L3_SEC_STM */
+    volatile ALT_L3_SEC_LWH2F_t        lwhps2fpgaregs;      /* ALT_L3_SEC_LWH2F */
+    volatile uint32_t                  _pad_0x1c_0x1f;      /* *UNDEFINED* */
+    volatile ALT_L3_SEC_USB1_t         usb1;                /* ALT_L3_SEC_USB1 */
+    volatile ALT_L3_SEC_NANDDATA_t     nanddata;            /* ALT_L3_SEC_NANDDATA */
+    volatile uint32_t                  _pad_0x28_0x77[20];  /* *UNDEFINED* */
+    volatile ALT_L3_SEC_USB0_t         usb0;                /* ALT_L3_SEC_USB0 */
+    volatile ALT_L3_SEC_NAND_t         nandregs;            /* ALT_L3_SEC_NAND */
+    volatile ALT_L3_SEC_QSPIDATA_t     qspidata;            /* ALT_L3_SEC_QSPIDATA */
+    volatile ALT_L3_SEC_FPGAMGRDATA_t  fpgamgrdata;         /* ALT_L3_SEC_FPGAMGRDATA */
+    volatile ALT_L3_SEC_H2F_t          hps2fpgaregs;        /* ALT_L3_SEC_H2F */
+    volatile ALT_L3_SEC_ACP_t          acp;                 /* ALT_L3_SEC_ACP */
+    volatile ALT_L3_SEC_ROM_t          rom;                 /* ALT_L3_SEC_ROM */
+    volatile ALT_L3_SEC_OCRAM_t        ocram;               /* ALT_L3_SEC_OCRAM */
+    volatile ALT_L3_SEC_SDRDATA_t      sdrdata;             /* ALT_L3_SEC_SDRDATA */
+};
+
+/* The typedef declaration for register group ALT_L3_SECGRP. */
+typedef volatile struct ALT_L3_SECGRP_s  ALT_L3_SECGRP_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SECGRP. */
+struct ALT_L3_SECGRP_raw_s
+{
+    volatile uint32_t  l4main;              /* ALT_L3_SEC_L4MAIN */
+    volatile uint32_t  l4sp;                /* ALT_L3_SEC_L4SP */
+    volatile uint32_t  l4mp;                /* ALT_L3_SEC_L4MP */
+    volatile uint32_t  l4osc1;              /* ALT_L3_SEC_L4OSC1 */
+    volatile uint32_t  l4spim;              /* ALT_L3_SEC_L4SPIM */
+    volatile uint32_t  stm;                 /* ALT_L3_SEC_STM */
+    volatile uint32_t  lwhps2fpgaregs;      /* ALT_L3_SEC_LWH2F */
+    volatile uint32_t  _pad_0x1c_0x1f;      /* *UNDEFINED* */
+    volatile uint32_t  usb1;                /* ALT_L3_SEC_USB1 */
+    volatile uint32_t  nanddata;            /* ALT_L3_SEC_NANDDATA */
+    volatile uint32_t  _pad_0x28_0x77[20];  /* *UNDEFINED* */
+    volatile uint32_t  usb0;                /* ALT_L3_SEC_USB0 */
+    volatile uint32_t  nandregs;            /* ALT_L3_SEC_NAND */
+    volatile uint32_t  qspidata;            /* ALT_L3_SEC_QSPIDATA */
+    volatile uint32_t  fpgamgrdata;         /* ALT_L3_SEC_FPGAMGRDATA */
+    volatile uint32_t  hps2fpgaregs;        /* ALT_L3_SEC_H2F */
+    volatile uint32_t  acp;                 /* ALT_L3_SEC_ACP */
+    volatile uint32_t  rom;                 /* ALT_L3_SEC_ROM */
+    volatile uint32_t  ocram;               /* ALT_L3_SEC_OCRAM */
+    volatile uint32_t  sdrdata;             /* ALT_L3_SEC_SDRDATA */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SECGRP. */
+typedef volatile struct ALT_L3_SECGRP_raw_s  ALT_L3_SECGRP_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : ID Register Group - ALT_L3_IDGRP
+ * ID Register Group
+ * 
+ * Contains registers that identify the ARM NIC-301 IP Core.
+ * 
+ */
+/*
+ * Register : Peripheral ID4 Register - periph_id_4
+ * 
+ * JEP106 continuation code
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description   
+ * :-------|:-------|:------|:---------------
+ *  [7:0]  | R      | 0x4   | Peripheral ID4
+ *  [31:8] | ???    | 0x0   | *UNDEFINED*   
+ * 
+ */
+/*
+ * Field : Peripheral ID4 - periph_id_4
+ * 
+ * JEP106 continuation code
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
+#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
+#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_MSB        7
+/* The width in bits of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
+#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH      8
+/* The mask used to set the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */
+#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */
+#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK    0xffffff00
+/* The reset value of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
+#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_RESET      0x4
+/* Extracts the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */
+#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */
+#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_ID_PERIPH_ID_4.
+ */
+struct ALT_L3_ID_PERIPH_ID_4_s
+{
+    const uint32_t  periph_id_4 :  8;  /* Peripheral ID4 */
+    uint32_t                    : 24;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_4. */
+typedef volatile struct ALT_L3_ID_PERIPH_ID_4_s  ALT_L3_ID_PERIPH_ID_4_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_ID_PERIPH_ID_4 register from the beginning of the component. */
+#define ALT_L3_ID_PERIPH_ID_4_OFST        0xfd0
+
+/*
+ * Register : Peripheral ID0 Register - periph_id_0
+ * 
+ * Peripheral ID0
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description      
+ * :-------|:-------|:------|:------------------
+ *  [7:0]  | R      | 0x1   | Part Number [7:0]
+ *  [31:8] | ???    | 0x0   | *UNDEFINED*      
+ * 
+ */
+/*
+ * Field : Part Number [7:0] - pn7to0
+ * 
+ * Part Number [7:0]
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
+#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
+#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_MSB        7
+/* The width in bits of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
+#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_WIDTH      8
+/* The mask used to set the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */
+#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */
+#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_CLR_MSK    0xffffff00
+/* The reset value of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
+#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_RESET      0x1
+/* Extracts the ALT_L3_ID_PERIPH_ID_0_PN7TO0 field value from a register. */
+#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */
+#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_ID_PERIPH_ID_0.
+ */
+struct ALT_L3_ID_PERIPH_ID_0_s
+{
+    const uint32_t  pn7to0 :  8;  /* Part Number [7:0] */
+    uint32_t               : 24;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_0. */
+typedef volatile struct ALT_L3_ID_PERIPH_ID_0_s  ALT_L3_ID_PERIPH_ID_0_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_ID_PERIPH_ID_0 register from the beginning of the component. */
+#define ALT_L3_ID_PERIPH_ID_0_OFST        0xfe0
+
+/*
+ * Register : Peripheral ID1 Register - periph_id_1
+ * 
+ * Peripheral ID1
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                    
+ * :-------|:-------|:------|:--------------------------------
+ *  [7:0]  | R      | 0xb3  | JEP106[3:0], Part Number [11:8]
+ *  [31:8] | ???    | 0x0   | *UNDEFINED*                    
+ * 
+ */
+/*
+ * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8
+ * 
+ * JEP106[3:0], Part Number [11:8]
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
+#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
+#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB        7
+/* The width in bits of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
+#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH      8
+/* The mask used to set the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */
+#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */
+#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK    0xffffff00
+/* The reset value of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
+#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET      0xb3
+/* Extracts the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */
+#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */
+#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_ID_PERIPH_ID_1.
+ */
+struct ALT_L3_ID_PERIPH_ID_1_s
+{
+    const uint32_t  jep3to0_pn11to8 :  8;  /* JEP106[3:0], Part Number [11:8] */
+    uint32_t                        : 24;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_1. */
+typedef volatile struct ALT_L3_ID_PERIPH_ID_1_s  ALT_L3_ID_PERIPH_ID_1_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_ID_PERIPH_ID_1 register from the beginning of the component. */
+#define ALT_L3_ID_PERIPH_ID_1_OFST        0xfe4
+
+/*
+ * Register : Peripheral ID2 Register - periph_id_2
+ * 
+ * Peripheral ID2
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                            
+ * :-------|:-------|:------|:----------------------------------------
+ *  [7:0]  | R      | 0x6b  | Revision, JEP106 code flag, JEP106[6:4]
+ *  [31:8] | ???    | 0x0   | *UNDEFINED*                            
+ * 
+ */
+/*
+ * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4
+ * 
+ * Revision, JEP106 code flag, JEP106[6:4]
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
+#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
+#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB        7
+/* The width in bits of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
+#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH      8
+/* The mask used to set the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */
+#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */
+#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK    0xffffff00
+/* The reset value of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
+#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET      0x6b
+/* Extracts the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */
+#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */
+#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_ID_PERIPH_ID_2.
+ */
+struct ALT_L3_ID_PERIPH_ID_2_s
+{
+    const uint32_t  rev_jepcode_jep6to4 :  8;  /* Revision, JEP106 code flag, JEP106[6:4] */
+    uint32_t                            : 24;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_2. */
+typedef volatile struct ALT_L3_ID_PERIPH_ID_2_s  ALT_L3_ID_PERIPH_ID_2_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_ID_PERIPH_ID_2 register from the beginning of the component. */
+#define ALT_L3_ID_PERIPH_ID_2_OFST        0xfe8
+
+/*
+ * Register : Peripheral ID3 Register - periph_id_3
+ * 
+ * Peripheral ID3
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description          
+ * :-------|:-------|:------|:----------------------
+ *  [3:0]  | R      | 0x0   | Customer Model Number
+ *  [7:4]  | R      | 0x0   | Revision             
+ *  [31:8] | ???    | 0x0   | *UNDEFINED*          
+ * 
+ */
+/*
+ * Field : Customer Model Number - cust_mod_num
+ * 
+ * Customer Model Number
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
+#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
+#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB        3
+/* The width in bits of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
+#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH      4
+/* The mask used to set the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */
+#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK    0x0000000f
+/* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */
+#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK    0xfffffff0
+/* The reset value of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
+#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET      0x0
+/* Extracts the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */
+#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0)
+/* Produces a ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */
+#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f)
+
+/*
+ * Field : Revision - rev_and
+ * 
+ * Revision
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
+#define ALT_L3_ID_PERIPH_ID_3_REV_AND_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
+#define ALT_L3_ID_PERIPH_ID_3_REV_AND_MSB        7
+/* The width in bits of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
+#define ALT_L3_ID_PERIPH_ID_3_REV_AND_WIDTH      4
+/* The mask used to set the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */
+#define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET_MSK    0x000000f0
+/* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */
+#define ALT_L3_ID_PERIPH_ID_3_REV_AND_CLR_MSK    0xffffff0f
+/* The reset value of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
+#define ALT_L3_ID_PERIPH_ID_3_REV_AND_RESET      0x0
+/* Extracts the ALT_L3_ID_PERIPH_ID_3_REV_AND field value from a register. */
+#define ALT_L3_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4)
+/* Produces a ALT_L3_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */
+#define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_ID_PERIPH_ID_3.
+ */
+struct ALT_L3_ID_PERIPH_ID_3_s
+{
+    const uint32_t  cust_mod_num :  4;  /* Customer Model Number */
+    const uint32_t  rev_and      :  4;  /* Revision */
+    uint32_t                     : 24;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_3. */
+typedef volatile struct ALT_L3_ID_PERIPH_ID_3_s  ALT_L3_ID_PERIPH_ID_3_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_ID_PERIPH_ID_3 register from the beginning of the component. */
+#define ALT_L3_ID_PERIPH_ID_3_OFST        0xfec
+
+/*
+ * Register : Component ID0 Register - comp_id_0
+ * 
+ * Component ID0
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [7:0]  | R      | 0xd   | Preamble   
+ *  [31:8] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Preamble - preamble
+ * 
+ * Preamble
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_0_PREAMBLE_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_0_PREAMBLE_MSB        7
+/* The width in bits of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_0_PREAMBLE_WIDTH      8
+/* The mask used to set the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */
+#define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */
+#define ALT_L3_ID_COMP_ID_0_PREAMBLE_CLR_MSK    0xffffff00
+/* The reset value of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_0_PREAMBLE_RESET      0xd
+/* Extracts the ALT_L3_ID_COMP_ID_0_PREAMBLE field value from a register. */
+#define ALT_L3_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_L3_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */
+#define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_ID_COMP_ID_0.
+ */
+struct ALT_L3_ID_COMP_ID_0_s
+{
+    const uint32_t  preamble :  8;  /* Preamble */
+    uint32_t                 : 24;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_ID_COMP_ID_0. */
+typedef volatile struct ALT_L3_ID_COMP_ID_0_s  ALT_L3_ID_COMP_ID_0_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_ID_COMP_ID_0 register from the beginning of the component. */
+#define ALT_L3_ID_COMP_ID_0_OFST        0xff0
+
+/*
+ * Register : Component ID1 Register - comp_id_1
+ * 
+ * Component ID1
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                         
+ * :-------|:-------|:------|:-------------------------------------
+ *  [7:0]  | R      | 0xf0  | Generic IP component class, Preamble
+ *  [31:8] | ???    | 0x0   | *UNDEFINED*                         
+ * 
+ */
+/*
+ * Field : Generic IP component class, Preamble - genipcompcls_preamble
+ * 
+ * Generic IP component class, Preamble
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB        7
+/* The width in bits of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH      8
+/* The mask used to set the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */
+#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */
+#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK    0xffffff00
+/* The reset value of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET      0xf0
+/* Extracts the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */
+#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */
+#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_ID_COMP_ID_1.
+ */
+struct ALT_L3_ID_COMP_ID_1_s
+{
+    const uint32_t  genipcompcls_preamble :  8;  /* Generic IP component class, Preamble */
+    uint32_t                              : 24;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_ID_COMP_ID_1. */
+typedef volatile struct ALT_L3_ID_COMP_ID_1_s  ALT_L3_ID_COMP_ID_1_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_ID_COMP_ID_1 register from the beginning of the component. */
+#define ALT_L3_ID_COMP_ID_1_OFST        0xff4
+
+/*
+ * Register : Component ID2 Register - comp_id_2
+ * 
+ * Component ID2
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [7:0]  | R      | 0x5   | Preamble   
+ *  [31:8] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Preamble - preamble
+ * 
+ * Preamble
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_2_PREAMBLE_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_2_PREAMBLE_MSB        7
+/* The width in bits of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_2_PREAMBLE_WIDTH      8
+/* The mask used to set the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */
+#define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */
+#define ALT_L3_ID_COMP_ID_2_PREAMBLE_CLR_MSK    0xffffff00
+/* The reset value of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_2_PREAMBLE_RESET      0x5
+/* Extracts the ALT_L3_ID_COMP_ID_2_PREAMBLE field value from a register. */
+#define ALT_L3_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_L3_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */
+#define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_ID_COMP_ID_2.
+ */
+struct ALT_L3_ID_COMP_ID_2_s
+{
+    const uint32_t  preamble :  8;  /* Preamble */
+    uint32_t                 : 24;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_ID_COMP_ID_2. */
+typedef volatile struct ALT_L3_ID_COMP_ID_2_s  ALT_L3_ID_COMP_ID_2_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_ID_COMP_ID_2 register from the beginning of the component. */
+#define ALT_L3_ID_COMP_ID_2_OFST        0xff8
+
+/*
+ * Register : Component ID3 Register - comp_id_3
+ * 
+ * Component ID3
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [7:0]  | R      | 0xb1  | Preamble   
+ *  [31:8] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Preamble - preamble
+ * 
+ * Preamble
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_3_PREAMBLE_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_3_PREAMBLE_MSB        7
+/* The width in bits of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_3_PREAMBLE_WIDTH      8
+/* The mask used to set the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */
+#define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */
+#define ALT_L3_ID_COMP_ID_3_PREAMBLE_CLR_MSK    0xffffff00
+/* The reset value of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
+#define ALT_L3_ID_COMP_ID_3_PREAMBLE_RESET      0xb1
+/* Extracts the ALT_L3_ID_COMP_ID_3_PREAMBLE field value from a register. */
+#define ALT_L3_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_L3_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */
+#define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_ID_COMP_ID_3.
+ */
+struct ALT_L3_ID_COMP_ID_3_s
+{
+    const uint32_t  preamble :  8;  /* Preamble */
+    uint32_t                 : 24;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_ID_COMP_ID_3. */
+typedef volatile struct ALT_L3_ID_COMP_ID_3_s  ALT_L3_ID_COMP_ID_3_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_ID_COMP_ID_3 register from the beginning of the component. */
+#define ALT_L3_ID_COMP_ID_3_OFST        0xffc
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_IDGRP.
+ */
+struct ALT_L3_IDGRP_s
+{
+    volatile uint32_t                 _pad_0x0_0xfcf[1012];  /* *UNDEFINED* */
+    volatile ALT_L3_ID_PERIPH_ID_4_t  periph_id_4;           /* ALT_L3_ID_PERIPH_ID_4 */
+    volatile uint32_t                 _pad_0xfd4_0xfdf[3];   /* *UNDEFINED* */
+    volatile ALT_L3_ID_PERIPH_ID_0_t  periph_id_0;           /* ALT_L3_ID_PERIPH_ID_0 */
+    volatile ALT_L3_ID_PERIPH_ID_1_t  periph_id_1;           /* ALT_L3_ID_PERIPH_ID_1 */
+    volatile ALT_L3_ID_PERIPH_ID_2_t  periph_id_2;           /* ALT_L3_ID_PERIPH_ID_2 */
+    volatile ALT_L3_ID_PERIPH_ID_3_t  periph_id_3;           /* ALT_L3_ID_PERIPH_ID_3 */
+    volatile ALT_L3_ID_COMP_ID_0_t    comp_id_0;             /* ALT_L3_ID_COMP_ID_0 */
+    volatile ALT_L3_ID_COMP_ID_1_t    comp_id_1;             /* ALT_L3_ID_COMP_ID_1 */
+    volatile ALT_L3_ID_COMP_ID_2_t    comp_id_2;             /* ALT_L3_ID_COMP_ID_2 */
+    volatile ALT_L3_ID_COMP_ID_3_t    comp_id_3;             /* ALT_L3_ID_COMP_ID_3 */
+};
+
+/* The typedef declaration for register group ALT_L3_IDGRP. */
+typedef volatile struct ALT_L3_IDGRP_s  ALT_L3_IDGRP_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_IDGRP. */
+struct ALT_L3_IDGRP_raw_s
+{
+    volatile uint32_t  _pad_0x0_0xfcf[1012];  /* *UNDEFINED* */
+    volatile uint32_t  periph_id_4;           /* ALT_L3_ID_PERIPH_ID_4 */
+    volatile uint32_t  _pad_0xfd4_0xfdf[3];   /* *UNDEFINED* */
+    volatile uint32_t  periph_id_0;           /* ALT_L3_ID_PERIPH_ID_0 */
+    volatile uint32_t  periph_id_1;           /* ALT_L3_ID_PERIPH_ID_1 */
+    volatile uint32_t  periph_id_2;           /* ALT_L3_ID_PERIPH_ID_2 */
+    volatile uint32_t  periph_id_3;           /* ALT_L3_ID_PERIPH_ID_3 */
+    volatile uint32_t  comp_id_0;             /* ALT_L3_ID_COMP_ID_0 */
+    volatile uint32_t  comp_id_1;             /* ALT_L3_ID_COMP_ID_1 */
+    volatile uint32_t  comp_id_2;             /* ALT_L3_ID_COMP_ID_2 */
+    volatile uint32_t  comp_id_3;             /* ALT_L3_ID_COMP_ID_3 */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_IDGRP. */
+typedef volatile struct ALT_L3_IDGRP_raw_s  ALT_L3_IDGRP_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : Master Register Group - ALT_L3_MSTGRP
+ * Master Register Group
+ * 
+ * Registers associated with master interfaces in the L3 Interconnect. Note that a
+ * master in the L3 Interconnect connects to a slave in a module.
+ * 
+ */
+/*
+ * Register Group : L4 MAIN - ALT_L3_MST_L4MAIN
+ * L4 MAIN
+ * 
+ * Registers associated with the L4 MAIN master. This master is used to access the
+ * APB slaves on the L4 MAIN bus.
+ * 
+ */
+/*
+ * Register : Bus Matrix Issuing Functionality Modification Register - fn_mod_bm_iss
+ * 
+ * Sets the issuing capability of the preceding switch arbitration scheme to
+ * multiple or single outstanding transactions.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description            
+ * :-------|:-------|:------|:------------------------
+ *  [0]    | RW     | 0x0   | ALT_L3_FN_MOD_BM_ISS_RD
+ *  [1]    | RW     | 0x0   | ALT_L3_FN_MOD_BM_ISS_WR
+ *  [31:2] | ???    | 0x0   | *UNDEFINED*            
+ * 
+ */
+/*
+ * Field : rd
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                               
+ * :---------------------------------|:------|:-------------------------------------------
+ *  ALT_L3_FN_MOD_BM_ISS_RD_E_MULT   | 0x0   | Multiple outstanding read transactions    
+ *  ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE | 0x1   | Only a single outstanding read transaction
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD
+ * 
+ * Multiple outstanding read transactions
+ */
+#define ALT_L3_FN_MOD_BM_ISS_RD_E_MULT      0x0
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD
+ * 
+ * Only a single outstanding read transaction
+ */
+#define ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
+#define ALT_L3_FN_MOD_BM_ISS_RD_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
+#define ALT_L3_FN_MOD_BM_ISS_RD_MSB        0
+/* The width in bits of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
+#define ALT_L3_FN_MOD_BM_ISS_RD_WIDTH      1
+/* The mask used to set the ALT_L3_FN_MOD_BM_ISS_RD register field value. */
+#define ALT_L3_FN_MOD_BM_ISS_RD_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_RD register field value. */
+#define ALT_L3_FN_MOD_BM_ISS_RD_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
+#define ALT_L3_FN_MOD_BM_ISS_RD_RESET      0x0
+/* Extracts the ALT_L3_FN_MOD_BM_ISS_RD field value from a register. */
+#define ALT_L3_FN_MOD_BM_ISS_RD_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_FN_MOD_BM_ISS_RD register field value suitable for setting the register. */
+#define ALT_L3_FN_MOD_BM_ISS_RD_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : wr
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                
+ * :---------------------------------|:------|:--------------------------------------------
+ *  ALT_L3_FN_MOD_BM_ISS_WR_E_MULT   | 0x0   | Multiple outstanding write transactions    
+ *  ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE | 0x1   | Only a single outstanding write transaction
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR
+ * 
+ * Multiple outstanding write transactions
+ */
+#define ALT_L3_FN_MOD_BM_ISS_WR_E_MULT      0x0
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR
+ * 
+ * Only a single outstanding write transaction
+ */
+#define ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
+#define ALT_L3_FN_MOD_BM_ISS_WR_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
+#define ALT_L3_FN_MOD_BM_ISS_WR_MSB        1
+/* The width in bits of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
+#define ALT_L3_FN_MOD_BM_ISS_WR_WIDTH      1
+/* The mask used to set the ALT_L3_FN_MOD_BM_ISS_WR register field value. */
+#define ALT_L3_FN_MOD_BM_ISS_WR_SET_MSK    0x00000002
+/* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_WR register field value. */
+#define ALT_L3_FN_MOD_BM_ISS_WR_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
+#define ALT_L3_FN_MOD_BM_ISS_WR_RESET      0x0
+/* Extracts the ALT_L3_FN_MOD_BM_ISS_WR field value from a register. */
+#define ALT_L3_FN_MOD_BM_ISS_WR_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_L3_FN_MOD_BM_ISS_WR register field value suitable for setting the register. */
+#define ALT_L3_FN_MOD_BM_ISS_WR_SET(value) (((value) << 1) & 0x00000002)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_FN_MOD_BM_ISS.
+ */
+struct ALT_L3_FN_MOD_BM_ISS_s
+{
+    uint32_t  rd :  1;  /* ALT_L3_FN_MOD_BM_ISS_RD */
+    uint32_t  wr :  1;  /* ALT_L3_FN_MOD_BM_ISS_WR */
+    uint32_t     : 30;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_FN_MOD_BM_ISS. */
+typedef volatile struct ALT_L3_FN_MOD_BM_ISS_s  ALT_L3_FN_MOD_BM_ISS_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_FN_MOD_BM_ISS register from the beginning of the component. */
+#define ALT_L3_FN_MOD_BM_ISS_OFST        0x8
+/* The address of the ALT_L3_FN_MOD_BM_ISS register. */
+#define ALT_L3_FN_MOD_BM_ISS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_BM_ISS_OFST))
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_L4MAIN.
+ */
+struct ALT_L3_MST_L4MAIN_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;    /* ALT_L3_FN_MOD_BM_ISS */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_L4MAIN. */
+typedef volatile struct ALT_L3_MST_L4MAIN_s  ALT_L3_MST_L4MAIN_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */
+struct ALT_L3_MST_L4MAIN_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;    /* ALT_L3_FN_MOD_BM_ISS */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */
+typedef volatile struct ALT_L3_MST_L4MAIN_raw_s  ALT_L3_MST_L4MAIN_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : L4 SP - ALT_L3_MST_L4SP
+ * L4 SP
+ * 
+ * Registers associated with the L4 SP master. This master is used to access the
+ * APB slaves on the L4 SP bus.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_L4SP.
+ */
+struct ALT_L3_MST_L4SP_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;    /* ALT_L3_FN_MOD_BM_ISS */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_L4SP. */
+typedef volatile struct ALT_L3_MST_L4SP_s  ALT_L3_MST_L4SP_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SP. */
+struct ALT_L3_MST_L4SP_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;    /* ALT_L3_FN_MOD_BM_ISS */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SP. */
+typedef volatile struct ALT_L3_MST_L4SP_raw_s  ALT_L3_MST_L4SP_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : L4 MP - ALT_L3_MST_L4MP
+ * L4 MP
+ * 
+ * Registers associated with the L4 MP master. This master is used to access the
+ * APB slaves on the L4 MP bus.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_L4MP.
+ */
+struct ALT_L3_MST_L4MP_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;    /* ALT_L3_FN_MOD_BM_ISS */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_L4MP. */
+typedef volatile struct ALT_L3_MST_L4MP_s  ALT_L3_MST_L4MP_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MP. */
+struct ALT_L3_MST_L4MP_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;    /* ALT_L3_FN_MOD_BM_ISS */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MP. */
+typedef volatile struct ALT_L3_MST_L4MP_raw_s  ALT_L3_MST_L4MP_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : L4 OSC1 - ALT_L3_MST_L4OSC1
+ * L4 OSC1
+ * 
+ * Registers associated with the L4 OSC1 master. This master is used to access the
+ * APB slaves on the L4 OSC1 bus.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_L4OSC1.
+ */
+struct ALT_L3_MST_L4OSC1_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;    /* ALT_L3_FN_MOD_BM_ISS */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_L4OSC1. */
+typedef volatile struct ALT_L3_MST_L4OSC1_s  ALT_L3_MST_L4OSC1_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */
+struct ALT_L3_MST_L4OSC1_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;    /* ALT_L3_FN_MOD_BM_ISS */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */
+typedef volatile struct ALT_L3_MST_L4OSC1_raw_s  ALT_L3_MST_L4OSC1_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : L4 SPIM - ALT_L3_MST_L4SPIM
+ * L4 SPIM
+ * 
+ * Registers associated with the L4 SPIM master. This master is used to access the
+ * APB slaves on the L4 SPIM bus.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_L4SPIM.
+ */
+struct ALT_L3_MST_L4SPIM_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;    /* ALT_L3_FN_MOD_BM_ISS */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_L4SPIM. */
+typedef volatile struct ALT_L3_MST_L4SPIM_s  ALT_L3_MST_L4SPIM_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */
+struct ALT_L3_MST_L4SPIM_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;    /* ALT_L3_FN_MOD_BM_ISS */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */
+typedef volatile struct ALT_L3_MST_L4SPIM_raw_s  ALT_L3_MST_L4SPIM_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : STM - ALT_L3_MST_STM
+ * STM
+ * 
+ * Registers associated with the STM master. This master is used to access the STM
+ * AXI slave.
+ * 
+ */
+/*
+ * Register : Issuing Functionality Modification Register - fn_mod
+ * 
+ * Sets the block issuing capability to multiple or single outstanding
+ * transactions.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description     
+ * :-------|:-------|:------|:-----------------
+ *  [0]    | RW     | 0x0   | ALT_L3_FN_MOD_RD
+ *  [1]    | RW     | 0x0   | ALT_L3_FN_MOD_WR
+ *  [31:2] | ???    | 0x0   | *UNDEFINED*     
+ * 
+ */
+/*
+ * Field : rd
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                      | Value | Description                               
+ * :--------------------------|:------|:-------------------------------------------
+ *  ALT_L3_FN_MOD_RD_E_MULT   | 0x0   | Multiple outstanding read transactions    
+ *  ALT_L3_FN_MOD_RD_E_SINGLE | 0x1   | Only a single outstanding read transaction
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_RD
+ * 
+ * Multiple outstanding read transactions
+ */
+#define ALT_L3_FN_MOD_RD_E_MULT     0x0
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_RD
+ * 
+ * Only a single outstanding read transaction
+ */
+#define ALT_L3_FN_MOD_RD_E_SINGLE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_RD register field. */
+#define ALT_L3_FN_MOD_RD_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_RD register field. */
+#define ALT_L3_FN_MOD_RD_MSB        0
+/* The width in bits of the ALT_L3_FN_MOD_RD register field. */
+#define ALT_L3_FN_MOD_RD_WIDTH      1
+/* The mask used to set the ALT_L3_FN_MOD_RD register field value. */
+#define ALT_L3_FN_MOD_RD_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_FN_MOD_RD register field value. */
+#define ALT_L3_FN_MOD_RD_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_FN_MOD_RD register field. */
+#define ALT_L3_FN_MOD_RD_RESET      0x0
+/* Extracts the ALT_L3_FN_MOD_RD field value from a register. */
+#define ALT_L3_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_FN_MOD_RD register field value suitable for setting the register. */
+#define ALT_L3_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : wr
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                      | Value | Description                                
+ * :--------------------------|:------|:--------------------------------------------
+ *  ALT_L3_FN_MOD_WR_E_MULT   | 0x0   | Multiple outstanding write transactions    
+ *  ALT_L3_FN_MOD_WR_E_SINGLE | 0x1   | Only a single outstanding write transaction
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_WR
+ * 
+ * Multiple outstanding write transactions
+ */
+#define ALT_L3_FN_MOD_WR_E_MULT     0x0
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_WR
+ * 
+ * Only a single outstanding write transaction
+ */
+#define ALT_L3_FN_MOD_WR_E_SINGLE   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_WR register field. */
+#define ALT_L3_FN_MOD_WR_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_WR register field. */
+#define ALT_L3_FN_MOD_WR_MSB        1
+/* The width in bits of the ALT_L3_FN_MOD_WR register field. */
+#define ALT_L3_FN_MOD_WR_WIDTH      1
+/* The mask used to set the ALT_L3_FN_MOD_WR register field value. */
+#define ALT_L3_FN_MOD_WR_SET_MSK    0x00000002
+/* The mask used to clear the ALT_L3_FN_MOD_WR register field value. */
+#define ALT_L3_FN_MOD_WR_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_L3_FN_MOD_WR register field. */
+#define ALT_L3_FN_MOD_WR_RESET      0x0
+/* Extracts the ALT_L3_FN_MOD_WR field value from a register. */
+#define ALT_L3_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_L3_FN_MOD_WR register field value suitable for setting the register. */
+#define ALT_L3_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_FN_MOD.
+ */
+struct ALT_L3_FN_MOD_s
+{
+    uint32_t  rd :  1;  /* ALT_L3_FN_MOD_RD */
+    uint32_t  wr :  1;  /* ALT_L3_FN_MOD_WR */
+    uint32_t     : 30;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_FN_MOD. */
+typedef volatile struct ALT_L3_FN_MOD_s  ALT_L3_FN_MOD_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_FN_MOD register from the beginning of the component. */
+#define ALT_L3_FN_MOD_OFST        0x108
+/* The address of the ALT_L3_FN_MOD register. */
+#define ALT_L3_FN_MOD_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_OFST))
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_STM.
+ */
+struct ALT_L3_MST_STM_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_t         fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_STM. */
+typedef volatile struct ALT_L3_MST_STM_s  ALT_L3_MST_STM_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_STM. */
+struct ALT_L3_MST_STM_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_STM. */
+typedef volatile struct ALT_L3_MST_STM_raw_s  ALT_L3_MST_STM_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : LWHPS2FPGA - ALT_L3_MST_LWH2F
+ * LWHPS2FPGA
+ * 
+ * Registers associated with the LWHPS2FPGA AXI Bridge master. This master is used
+ * to access the LWHPS2FPGA AXI Bridge slave. This slave is used to access the
+ * registers for all 3 AXI bridges and to access slaves in the FPGA connected to
+ * the LWHPS2FPGA AXI Bridge.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_LWH2F.
+ */
+struct ALT_L3_MST_LWH2F_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_t         fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_LWH2F. */
+typedef volatile struct ALT_L3_MST_LWH2F_s  ALT_L3_MST_LWH2F_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */
+struct ALT_L3_MST_LWH2F_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */
+typedef volatile struct ALT_L3_MST_LWH2F_raw_s  ALT_L3_MST_LWH2F_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : USB1 - ALT_L3_MST_USB1
+ * USB1
+ * 
+ * Registers associated with the USB1 master. This master is used to access the
+ * registers in USB1.
+ * 
+ */
+/*
+ * Register : AHB Control Register - ahb_cntl
+ * 
+ * Sets the block issuing capability to one outstanding transaction.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description               
+ * :-------|:-------|:------|:---------------------------
+ *  [0]    | RW     | 0x0   | ALT_L3_AHB_CNTL_DECERR_EN 
+ *  [1]    | RW     | 0x0   | ALT_L3_AHB_CNTL_FORCE_INCR
+ *  [31:2] | ???    | 0x0   | *UNDEFINED*               
+ * 
+ */
+/*
+ * Field : decerr_en
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                            | Value | Description                                     
+ * :--------------------------------|:------|:-------------------------------------------------
+ *  ALT_L3_AHB_CNTL_DECERR_EN_E_DIS | 0x0   | No DECERR response.                             
+ *  ALT_L3_AHB_CNTL_DECERR_EN_E_EN  | 0x1   | If the AHB protocol conversion function receives
+ * :                                |       | an unaligned address or a write data beat       
+ * :                                |       | without all the byte strobes set, creates a     
+ * :                                |       | DECERR response.                                
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN
+ * 
+ * No DECERR response.
+ */
+#define ALT_L3_AHB_CNTL_DECERR_EN_E_DIS 0x0
+/*
+ * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN
+ * 
+ * If the AHB protocol conversion function receives an unaligned address or a write
+ * data beat without all the byte strobes set, creates a DECERR response.
+ */
+#define ALT_L3_AHB_CNTL_DECERR_EN_E_EN  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
+#define ALT_L3_AHB_CNTL_DECERR_EN_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
+#define ALT_L3_AHB_CNTL_DECERR_EN_MSB        0
+/* The width in bits of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
+#define ALT_L3_AHB_CNTL_DECERR_EN_WIDTH      1
+/* The mask used to set the ALT_L3_AHB_CNTL_DECERR_EN register field value. */
+#define ALT_L3_AHB_CNTL_DECERR_EN_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_AHB_CNTL_DECERR_EN register field value. */
+#define ALT_L3_AHB_CNTL_DECERR_EN_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
+#define ALT_L3_AHB_CNTL_DECERR_EN_RESET      0x0
+/* Extracts the ALT_L3_AHB_CNTL_DECERR_EN field value from a register. */
+#define ALT_L3_AHB_CNTL_DECERR_EN_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_AHB_CNTL_DECERR_EN register field value suitable for setting the register. */
+#define ALT_L3_AHB_CNTL_DECERR_EN_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : force_incr
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                     
+ * :---------------------------------|:------|:-------------------------------------------------
+ *  ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS | 0x0   | Multiple outstanding write transactions         
+ *  ALT_L3_AHB_CNTL_FORCE_INCR_E_EN  | 0x1   | If a beat is received that has no write data    
+ * :                                 |       | strobes set, that write data beat is replaced   
+ * :                                 |       | with an IDLE beat. Also, causes all transactions
+ * :                                 |       | that are to be output to the AHB domain to be an
+ * :                                 |       | undefined length INCR.                          
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR
+ * 
+ * Multiple outstanding write transactions
+ */
+#define ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS    0x0
+/*
+ * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR
+ * 
+ * If a beat is received that has no write data strobes set, that write data beat
+ * is replaced with an IDLE beat. Also, causes all transactions that are to be
+ * output to the AHB domain to be an undefined length INCR.
+ */
+#define ALT_L3_AHB_CNTL_FORCE_INCR_E_EN     0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
+#define ALT_L3_AHB_CNTL_FORCE_INCR_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
+#define ALT_L3_AHB_CNTL_FORCE_INCR_MSB        1
+/* The width in bits of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
+#define ALT_L3_AHB_CNTL_FORCE_INCR_WIDTH      1
+/* The mask used to set the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */
+#define ALT_L3_AHB_CNTL_FORCE_INCR_SET_MSK    0x00000002
+/* The mask used to clear the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */
+#define ALT_L3_AHB_CNTL_FORCE_INCR_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
+#define ALT_L3_AHB_CNTL_FORCE_INCR_RESET      0x0
+/* Extracts the ALT_L3_AHB_CNTL_FORCE_INCR field value from a register. */
+#define ALT_L3_AHB_CNTL_FORCE_INCR_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_L3_AHB_CNTL_FORCE_INCR register field value suitable for setting the register. */
+#define ALT_L3_AHB_CNTL_FORCE_INCR_SET(value) (((value) << 1) & 0x00000002)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_AHB_CNTL.
+ */
+struct ALT_L3_AHB_CNTL_s
+{
+    uint32_t  decerr_en  :  1;  /* ALT_L3_AHB_CNTL_DECERR_EN */
+    uint32_t  force_incr :  1;  /* ALT_L3_AHB_CNTL_FORCE_INCR */
+    uint32_t             : 30;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_AHB_CNTL. */
+typedef volatile struct ALT_L3_AHB_CNTL_s  ALT_L3_AHB_CNTL_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_AHB_CNTL register from the beginning of the component. */
+#define ALT_L3_AHB_CNTL_OFST        0x44
+/* The address of the ALT_L3_AHB_CNTL register. */
+#define ALT_L3_AHB_CNTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_AHB_CNTL_OFST))
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_USB1.
+ */
+struct ALT_L3_MST_USB1_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];    /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;      /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x43[14];  /* *UNDEFINED* */
+    volatile ALT_L3_AHB_CNTL_t       ahb_cntl;           /* ALT_L3_AHB_CNTL */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_USB1. */
+typedef volatile struct ALT_L3_MST_USB1_s  ALT_L3_MST_USB1_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_USB1. */
+struct ALT_L3_MST_USB1_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];    /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;      /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x43[14];  /* *UNDEFINED* */
+    volatile uint32_t  ahb_cntl;           /* ALT_L3_AHB_CNTL */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB1. */
+typedef volatile struct ALT_L3_MST_USB1_raw_s  ALT_L3_MST_USB1_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : NANDDATA - ALT_L3_MST_NANDDATA
+ * NANDDATA
+ * 
+ * Registers associated with the NANDDATA master. This master is used to access
+ * data in the NAND flash controller.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_NANDDATA.
+ */
+struct ALT_L3_MST_NANDDATA_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_t         fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_NANDDATA. */
+typedef volatile struct ALT_L3_MST_NANDDATA_s  ALT_L3_MST_NANDDATA_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */
+struct ALT_L3_MST_NANDDATA_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */
+typedef volatile struct ALT_L3_MST_NANDDATA_raw_s  ALT_L3_MST_NANDDATA_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : USB0 - ALT_L3_MST_USB0
+ * USB0
+ * 
+ * Registers associated with the USB0 master. This master is used to access the
+ * registers in USB0.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_USB0.
+ */
+struct ALT_L3_MST_USB0_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];    /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;      /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x43[14];  /* *UNDEFINED* */
+    volatile ALT_L3_AHB_CNTL_t       ahb_cntl;           /* ALT_L3_AHB_CNTL */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_USB0. */
+typedef volatile struct ALT_L3_MST_USB0_s  ALT_L3_MST_USB0_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_USB0. */
+struct ALT_L3_MST_USB0_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];    /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;      /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x43[14];  /* *UNDEFINED* */
+    volatile uint32_t  ahb_cntl;           /* ALT_L3_AHB_CNTL */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB0. */
+typedef volatile struct ALT_L3_MST_USB0_raw_s  ALT_L3_MST_USB0_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : NANDREGS - ALT_L3_MST_NAND
+ * NANDREGS
+ * 
+ * Registers associated with the NANDREGS master. This master is used to access the
+ * registers in the NAND flash controller.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_NAND.
+ */
+struct ALT_L3_MST_NAND_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_t         fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_NAND. */
+typedef volatile struct ALT_L3_MST_NAND_s  ALT_L3_MST_NAND_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_NAND. */
+struct ALT_L3_MST_NAND_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_NAND. */
+typedef volatile struct ALT_L3_MST_NAND_raw_s  ALT_L3_MST_NAND_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : QSPIDATA - ALT_L3_MST_QSPIDATA
+ * QSPIDATA
+ * 
+ * Registers associated with the QSPIDATA master. This master is used to access
+ * data in the QSPI flash controller.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_QSPIDATA.
+ */
+struct ALT_L3_MST_QSPIDATA_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];    /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;      /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x43[14];  /* *UNDEFINED* */
+    volatile ALT_L3_AHB_CNTL_t       ahb_cntl;           /* ALT_L3_AHB_CNTL */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_QSPIDATA. */
+typedef volatile struct ALT_L3_MST_QSPIDATA_s  ALT_L3_MST_QSPIDATA_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */
+struct ALT_L3_MST_QSPIDATA_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];    /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;      /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x43[14];  /* *UNDEFINED* */
+    volatile uint32_t  ahb_cntl;           /* ALT_L3_AHB_CNTL */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */
+typedef volatile struct ALT_L3_MST_QSPIDATA_raw_s  ALT_L3_MST_QSPIDATA_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : FPGAMGRDATA - ALT_L3_MST_FPGAMGRDATA
+ * FPGAMGRDATA
+ * 
+ * Registers associated with the FPGAMGRDATA master. This master is used to send
+ * FPGA configuration image data to the FPGA Manager.
+ * 
+ */
+/*
+ * Register : Write Tidemark - wr_tidemark
+ * 
+ * Controls the release of the transaction in the write data FIFO.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [3:0]  | RW     | 0x4   | Level      
+ *  [31:4] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Level - level
+ * 
+ * Stalls the transaction in the write data FIFO until the number of occupied slots
+ * in the write data FIFO exceeds the level. Note that the transaction is released
+ * before this level is achieved if the network receives the WLAST beat or the
+ * write FIFO becomes full.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
+#define ALT_L3_WR_TIDEMARK_LEVEL_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
+#define ALT_L3_WR_TIDEMARK_LEVEL_MSB        3
+/* The width in bits of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
+#define ALT_L3_WR_TIDEMARK_LEVEL_WIDTH      4
+/* The mask used to set the ALT_L3_WR_TIDEMARK_LEVEL register field value. */
+#define ALT_L3_WR_TIDEMARK_LEVEL_SET_MSK    0x0000000f
+/* The mask used to clear the ALT_L3_WR_TIDEMARK_LEVEL register field value. */
+#define ALT_L3_WR_TIDEMARK_LEVEL_CLR_MSK    0xfffffff0
+/* The reset value of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
+#define ALT_L3_WR_TIDEMARK_LEVEL_RESET      0x4
+/* Extracts the ALT_L3_WR_TIDEMARK_LEVEL field value from a register. */
+#define ALT_L3_WR_TIDEMARK_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
+/* Produces a ALT_L3_WR_TIDEMARK_LEVEL register field value suitable for setting the register. */
+#define ALT_L3_WR_TIDEMARK_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_WR_TIDEMARK.
+ */
+struct ALT_L3_WR_TIDEMARK_s
+{
+    uint32_t  level :  4;  /* Level */
+    uint32_t        : 28;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_WR_TIDEMARK. */
+typedef volatile struct ALT_L3_WR_TIDEMARK_s  ALT_L3_WR_TIDEMARK_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_WR_TIDEMARK register from the beginning of the component. */
+#define ALT_L3_WR_TIDEMARK_OFST        0x40
+/* The address of the ALT_L3_WR_TIDEMARK register. */
+#define ALT_L3_WR_TIDEMARK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_TIDEMARK_OFST))
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_FPGAMGRDATA.
+ */
+struct ALT_L3_MST_FPGAMGRDATA_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];      /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;        /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x3f[13];    /* *UNDEFINED* */
+    volatile ALT_L3_WR_TIDEMARK_t    wr_tidemark;          /* ALT_L3_WR_TIDEMARK */
+    volatile uint32_t                _pad_0x44_0x107[49];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_t         fn_mod;               /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_FPGAMGRDATA. */
+typedef volatile struct ALT_L3_MST_FPGAMGRDATA_s  ALT_L3_MST_FPGAMGRDATA_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */
+struct ALT_L3_MST_FPGAMGRDATA_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];      /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;        /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x3f[13];    /* *UNDEFINED* */
+    volatile uint32_t  wr_tidemark;          /* ALT_L3_WR_TIDEMARK */
+    volatile uint32_t  _pad_0x44_0x107[49];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod;               /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */
+typedef volatile struct ALT_L3_MST_FPGAMGRDATA_raw_s  ALT_L3_MST_FPGAMGRDATA_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : HPS2FPGA - ALT_L3_MST_H2F
+ * HPS2FPGA
+ * 
+ * Registers associated with the HPS2FPGA AXI Bridge master. This master is used to
+ * access the HPS2FPGA AXI Bridge slave. This slave is used to access slaves in the
+ * FPGA connected to the HPS2FPGA AXI Bridge.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_H2F.
+ */
+struct ALT_L3_MST_H2F_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];      /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;        /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x3f[13];    /* *UNDEFINED* */
+    volatile ALT_L3_WR_TIDEMARK_t    wr_tidemark;          /* ALT_L3_WR_TIDEMARK */
+    volatile uint32_t                _pad_0x44_0x107[49];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_t         fn_mod;               /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_H2F. */
+typedef volatile struct ALT_L3_MST_H2F_s  ALT_L3_MST_H2F_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_H2F. */
+struct ALT_L3_MST_H2F_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];      /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;        /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x3f[13];    /* *UNDEFINED* */
+    volatile uint32_t  wr_tidemark;          /* ALT_L3_WR_TIDEMARK */
+    volatile uint32_t  _pad_0x44_0x107[49];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod;               /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_H2F. */
+typedef volatile struct ALT_L3_MST_H2F_raw_s  ALT_L3_MST_H2F_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : ACP - ALT_L3_MST_ACP
+ * ACP
+ * 
+ * Registers associated with the ACP master. This master is used to access the MPU
+ * ACP slave via the ACP ID Mapper.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_ACP.
+ */
+struct ALT_L3_MST_ACP_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_t         fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_ACP. */
+typedef volatile struct ALT_L3_MST_ACP_s  ALT_L3_MST_ACP_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_ACP. */
+struct ALT_L3_MST_ACP_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_ACP. */
+typedef volatile struct ALT_L3_MST_ACP_raw_s  ALT_L3_MST_ACP_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : Boot ROM - ALT_L3_MST_ROM
+ * Boot ROM
+ * 
+ * Registers associated with the Boot ROM master. This master is used to access the
+ * contents of the Boot ROM.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_ROM.
+ */
+struct ALT_L3_MST_ROM_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_t         fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_ROM. */
+typedef volatile struct ALT_L3_MST_ROM_s  ALT_L3_MST_ROM_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_ROM. */
+struct ALT_L3_MST_ROM_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];     /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;       /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x107[63];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_ROM. */
+typedef volatile struct ALT_L3_MST_ROM_raw_s  ALT_L3_MST_ROM_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : On-chip RAM - ALT_L3_MST_OCRAM
+ * On-chip RAM
+ * 
+ * Registers associated with the On-chip RAM master. This master is used to access
+ * the contents of the On-chip RAM.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MST_OCRAM.
+ */
+struct ALT_L3_MST_OCRAM_s
+{
+    volatile uint32_t                _pad_0x0_0x7[2];      /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_BM_ISS_t  fn_mod_bm_iss;        /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t                _pad_0xc_0x3f[13];    /* *UNDEFINED* */
+    volatile ALT_L3_WR_TIDEMARK_t    wr_tidemark;          /* ALT_L3_WR_TIDEMARK */
+    volatile uint32_t                _pad_0x44_0x107[49];  /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_t         fn_mod;               /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_MST_OCRAM. */
+typedef volatile struct ALT_L3_MST_OCRAM_s  ALT_L3_MST_OCRAM_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */
+struct ALT_L3_MST_OCRAM_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x7[2];      /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_bm_iss;        /* ALT_L3_FN_MOD_BM_ISS */
+    volatile uint32_t  _pad_0xc_0x3f[13];    /* *UNDEFINED* */
+    volatile uint32_t  wr_tidemark;          /* ALT_L3_WR_TIDEMARK */
+    volatile uint32_t  _pad_0x44_0x107[49];  /* *UNDEFINED* */
+    volatile uint32_t  fn_mod;               /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */
+typedef volatile struct ALT_L3_MST_OCRAM_raw_s  ALT_L3_MST_OCRAM_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_MSTGRP.
+ */
+struct ALT_L3_MSTGRP_s
+{
+    volatile ALT_L3_MST_L4MAIN_t       mastergrp_l4main;            /* ALT_L3_MST_L4MAIN */
+    volatile uint32_t                  _pad_0xc_0xfff[1021];        /* *UNDEFINED* */
+    volatile ALT_L3_MST_L4SP_t         mastergrp_l4sp;              /* ALT_L3_MST_L4SP */
+    volatile uint32_t                  _pad_0x100c_0x1fff[1021];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_L4MP_t         mastergrp_l4mp;              /* ALT_L3_MST_L4MP */
+    volatile uint32_t                  _pad_0x200c_0x2fff[1021];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_L4OSC1_t       mastergrp_l4osc1;            /* ALT_L3_MST_L4OSC1 */
+    volatile uint32_t                  _pad_0x300c_0x3fff[1021];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_L4SPIM_t       mastergrp_l4spim;            /* ALT_L3_MST_L4SPIM */
+    volatile uint32_t                  _pad_0x400c_0x4fff[1021];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_STM_t          mastergrp_stm;               /* ALT_L3_MST_STM */
+    volatile uint32_t                  _pad_0x510c_0x5fff[957];     /* *UNDEFINED* */
+    volatile ALT_L3_MST_LWH2F_t        mastergrp_lwhps2fpga;        /* ALT_L3_MST_LWH2F */
+    volatile uint32_t                  _pad_0x610c_0x7fff[1981];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_USB1_t         mastergrp_usb1;              /* ALT_L3_MST_USB1 */
+    volatile uint32_t                  _pad_0x8048_0x8fff[1006];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_NANDDATA_t     mastergrp_nanddata;          /* ALT_L3_MST_NANDDATA */
+    volatile uint32_t                  _pad_0x910c_0x1dfff[21437];  /* *UNDEFINED* */
+    volatile ALT_L3_MST_USB0_t         mastergrp_usb0;              /* ALT_L3_MST_USB0 */
+    volatile uint32_t                  _pad_0x1e048_0x1efff[1006];  /* *UNDEFINED* */
+    volatile ALT_L3_MST_NAND_t         mastergrp_nandregs;          /* ALT_L3_MST_NAND */
+    volatile uint32_t                  _pad_0x1f10c_0x1ffff[957];   /* *UNDEFINED* */
+    volatile ALT_L3_MST_QSPIDATA_t     mastergrp_qspidata;          /* ALT_L3_MST_QSPIDATA */
+    volatile uint32_t                  _pad_0x20048_0x20fff[1006];  /* *UNDEFINED* */
+    volatile ALT_L3_MST_FPGAMGRDATA_t  mastergrp_fpgamgrdata;       /* ALT_L3_MST_FPGAMGRDATA */
+    volatile uint32_t                  _pad_0x2110c_0x21fff[957];   /* *UNDEFINED* */
+    volatile ALT_L3_MST_H2F_t          mastergrp_hps2fpga;          /* ALT_L3_MST_H2F */
+    volatile uint32_t                  _pad_0x2210c_0x22fff[957];   /* *UNDEFINED* */
+    volatile ALT_L3_MST_ACP_t          mastergrp_acp;               /* ALT_L3_MST_ACP */
+    volatile uint32_t                  _pad_0x2310c_0x23fff[957];   /* *UNDEFINED* */
+    volatile ALT_L3_MST_ROM_t          mastergrp_rom;               /* ALT_L3_MST_ROM */
+    volatile uint32_t                  _pad_0x2410c_0x24fff[957];   /* *UNDEFINED* */
+    volatile ALT_L3_MST_OCRAM_t        mastergrp_ocram;             /* ALT_L3_MST_OCRAM */
+};
+
+/* The typedef declaration for register group ALT_L3_MSTGRP. */
+typedef volatile struct ALT_L3_MSTGRP_s  ALT_L3_MSTGRP_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_MSTGRP. */
+struct ALT_L3_MSTGRP_raw_s
+{
+    volatile ALT_L3_MST_L4MAIN_raw_t       mastergrp_l4main;            /* ALT_L3_MST_L4MAIN */
+    volatile uint32_t                      _pad_0xc_0xfff[1021];        /* *UNDEFINED* */
+    volatile ALT_L3_MST_L4SP_raw_t         mastergrp_l4sp;              /* ALT_L3_MST_L4SP */
+    volatile uint32_t                      _pad_0x100c_0x1fff[1021];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_L4MP_raw_t         mastergrp_l4mp;              /* ALT_L3_MST_L4MP */
+    volatile uint32_t                      _pad_0x200c_0x2fff[1021];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_L4OSC1_raw_t       mastergrp_l4osc1;            /* ALT_L3_MST_L4OSC1 */
+    volatile uint32_t                      _pad_0x300c_0x3fff[1021];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_L4SPIM_raw_t       mastergrp_l4spim;            /* ALT_L3_MST_L4SPIM */
+    volatile uint32_t                      _pad_0x400c_0x4fff[1021];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_STM_raw_t          mastergrp_stm;               /* ALT_L3_MST_STM */
+    volatile uint32_t                      _pad_0x510c_0x5fff[957];     /* *UNDEFINED* */
+    volatile ALT_L3_MST_LWH2F_raw_t        mastergrp_lwhps2fpga;        /* ALT_L3_MST_LWH2F */
+    volatile uint32_t                      _pad_0x610c_0x7fff[1981];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_USB1_raw_t         mastergrp_usb1;              /* ALT_L3_MST_USB1 */
+    volatile uint32_t                      _pad_0x8048_0x8fff[1006];    /* *UNDEFINED* */
+    volatile ALT_L3_MST_NANDDATA_raw_t     mastergrp_nanddata;          /* ALT_L3_MST_NANDDATA */
+    volatile uint32_t                      _pad_0x910c_0x1dfff[21437];  /* *UNDEFINED* */
+    volatile ALT_L3_MST_USB0_raw_t         mastergrp_usb0;              /* ALT_L3_MST_USB0 */
+    volatile uint32_t                      _pad_0x1e048_0x1efff[1006];  /* *UNDEFINED* */
+    volatile ALT_L3_MST_NAND_raw_t         mastergrp_nandregs;          /* ALT_L3_MST_NAND */
+    volatile uint32_t                      _pad_0x1f10c_0x1ffff[957];   /* *UNDEFINED* */
+    volatile ALT_L3_MST_QSPIDATA_raw_t     mastergrp_qspidata;          /* ALT_L3_MST_QSPIDATA */
+    volatile uint32_t                      _pad_0x20048_0x20fff[1006];  /* *UNDEFINED* */
+    volatile ALT_L3_MST_FPGAMGRDATA_raw_t  mastergrp_fpgamgrdata;       /* ALT_L3_MST_FPGAMGRDATA */
+    volatile uint32_t                      _pad_0x2110c_0x21fff[957];   /* *UNDEFINED* */
+    volatile ALT_L3_MST_H2F_raw_t          mastergrp_hps2fpga;          /* ALT_L3_MST_H2F */
+    volatile uint32_t                      _pad_0x2210c_0x22fff[957];   /* *UNDEFINED* */
+    volatile ALT_L3_MST_ACP_raw_t          mastergrp_acp;               /* ALT_L3_MST_ACP */
+    volatile uint32_t                      _pad_0x2310c_0x23fff[957];   /* *UNDEFINED* */
+    volatile ALT_L3_MST_ROM_raw_t          mastergrp_rom;               /* ALT_L3_MST_ROM */
+    volatile uint32_t                      _pad_0x2410c_0x24fff[957];   /* *UNDEFINED* */
+    volatile ALT_L3_MST_OCRAM_raw_t        mastergrp_ocram;             /* ALT_L3_MST_OCRAM */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_MSTGRP. */
+typedef volatile struct ALT_L3_MSTGRP_raw_s  ALT_L3_MSTGRP_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : Slave Register Group - ALT_L3_SLVGRP
+ * Slave Register Group
+ * 
+ * Registers associated with slave interfaces.
+ * 
+ */
+/*
+ * Register Group : DAP - ALT_L3_SLV_DAP
+ * DAP
+ * 
+ * Registers associated with the DAP slave interface. This slave is used by the DAP
+ * to access slaves attached to the L3/L4 Interconnect.
+ * 
+ */
+/*
+ * Register : Functionality Modification 2 Register - fn_mod2
+ * 
+ * Controls bypass merge of upsizing/downsizing.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description 
+ * :-------|:-------|:------|:-------------
+ *  [0]    | RW     | 0x0   | Bypass Merge
+ *  [31:1] | ???    | 0x0   | *UNDEFINED* 
+ * 
+ */
+/*
+ * Field : Bypass Merge - bypass_merge
+ * 
+ * Controls bypass merge of upsizing/downsizing.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                  | Value | Description                                     
+ * :--------------------------------------|:------|:-------------------------------------------------
+ *  ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER   | 0x0   | The network can alter transactions.             
+ *  ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER | 0x1   | The network does not alter any transactions that
+ * :                                      |       | could pass through the upsizer legally without  
+ * :                                      |       | alteration.                                     
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE
+ * 
+ * The network can alter transactions.
+ */
+#define ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER     0x0
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE
+ * 
+ * The network does not alter any transactions that could pass through the upsizer
+ * legally without alteration.
+ */
+#define ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
+#define ALT_L3_FN_MOD2_BYPASS_MERGE_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
+#define ALT_L3_FN_MOD2_BYPASS_MERGE_MSB        0
+/* The width in bits of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
+#define ALT_L3_FN_MOD2_BYPASS_MERGE_WIDTH      1
+/* The mask used to set the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */
+#define ALT_L3_FN_MOD2_BYPASS_MERGE_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */
+#define ALT_L3_FN_MOD2_BYPASS_MERGE_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
+#define ALT_L3_FN_MOD2_BYPASS_MERGE_RESET      0x0
+/* Extracts the ALT_L3_FN_MOD2_BYPASS_MERGE field value from a register. */
+#define ALT_L3_FN_MOD2_BYPASS_MERGE_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_FN_MOD2_BYPASS_MERGE register field value suitable for setting the register. */
+#define ALT_L3_FN_MOD2_BYPASS_MERGE_SET(value) (((value) << 0) & 0x00000001)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_FN_MOD2.
+ */
+struct ALT_L3_FN_MOD2_s
+{
+    uint32_t  bypass_merge :  1;  /* Bypass Merge */
+    uint32_t               : 31;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_FN_MOD2. */
+typedef volatile struct ALT_L3_FN_MOD2_s  ALT_L3_FN_MOD2_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_FN_MOD2 register from the beginning of the component. */
+#define ALT_L3_FN_MOD2_OFST        0x24
+/* The address of the ALT_L3_FN_MOD2 register. */
+#define ALT_L3_FN_MOD2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD2_OFST))
+
+/*
+ * Register : Functionality Modification AHB Register - fn_mod_ahb
+ * 
+ * Controls how AHB-lite burst transactions are converted to AXI tranactions.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description             
+ * :-------|:-------|:------|:-------------------------
+ *  [0]    | RW     | 0x0   | Read Increment Override 
+ *  [1]    | RW     | 0x0   | Write Increment Override
+ *  [31:2] | ???    | 0x0   | *UNDEFINED*             
+ * 
+ */
+/*
+ * Field : Read Increment Override - rd_incr_override
+ * 
+ * Controls how AHB-lite read burst transactions are converted to AXI tranactions.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                  
+ * :---------------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT | 0x0   | The L3 Interconnect converts AHB-lite read   
+ * :                                             |       | bursts to AXI transactions in accordance with
+ * :                                             |       | the default behavior as specified in the ARM 
+ * :                                             |       | NIC-301 documentation.                       
+ *  ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES | 0x1   | The L3 Interconnect converts AHB-lite read   
+ * :                                             |       | bursts to AXI single transactions.           
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE
+ * 
+ * The L3 Interconnect converts AHB-lite read bursts to AXI transactions in
+ * accordance with the default behavior as specified in the ARM NIC-301
+ * documentation.
+ */
+#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT    0x0
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE
+ * 
+ * The L3 Interconnect converts AHB-lite read bursts to AXI single transactions.
+ */
+#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
+#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
+#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_MSB        0
+/* The width in bits of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
+#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_WIDTH      1
+/* The mask used to set the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */
+#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET_MSK    0x00000001
+/* The mask used to clear the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */
+#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
+#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_RESET      0x0
+/* Extracts the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE field value from a register. */
+#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value suitable for setting the register. */
+#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Write Increment Override - wr_incr_override
+ * 
+ * Controls how AHB-lite write burst transactions are converted to AXI tranactions.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                  
+ * :---------------------------------------------|:------|:----------------------------------------------
+ *  ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT | 0x0   | The L3 Interconnect converts AHB-lite write  
+ * :                                             |       | bursts to AXI transactions in accordance with
+ * :                                             |       | the default behavior as specified in the ARM 
+ * :                                             |       | NIC-301 documentation.                       
+ *  ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES | 0x1   | The L3 Interconnect converts AHB-lite write  
+ * :                                             |       | bursts to AXI single transactions.           
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE
+ * 
+ * The L3 Interconnect converts AHB-lite write bursts to AXI transactions in
+ * accordance with the default behavior as specified in the ARM NIC-301
+ * documentation.
+ */
+#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT    0x0
+/*
+ * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE
+ * 
+ * The L3 Interconnect converts AHB-lite write bursts to AXI single transactions.
+ */
+#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
+#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
+#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_MSB        1
+/* The width in bits of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
+#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_WIDTH      1
+/* The mask used to set the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */
+#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET_MSK    0x00000002
+/* The mask used to clear the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */
+#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
+#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_RESET      0x0
+/* Extracts the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE field value from a register. */
+#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value suitable for setting the register. */
+#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET(value) (((value) << 1) & 0x00000002)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_FN_MOD_AHB.
+ */
+struct ALT_L3_FN_MOD_AHB_s
+{
+    uint32_t  rd_incr_override :  1;  /* Read Increment Override */
+    uint32_t  wr_incr_override :  1;  /* Write Increment Override */
+    uint32_t                   : 30;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_FN_MOD_AHB. */
+typedef volatile struct ALT_L3_FN_MOD_AHB_s  ALT_L3_FN_MOD_AHB_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_FN_MOD_AHB register from the beginning of the component. */
+#define ALT_L3_FN_MOD_AHB_OFST        0x28
+/* The address of the ALT_L3_FN_MOD_AHB register. */
+#define ALT_L3_FN_MOD_AHB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_AHB_OFST))
+
+/*
+ * Register : Read Channel QoS Value - read_qos
+ * 
+ * QoS (Quality of Service) value for the read channel.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [3:0]  | RW     | 0x0   | Priority   
+ *  [31:4] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Priority - pri
+ * 
+ * QoS (Quality of Service) value for the read channel. A higher value has a higher
+ * priority.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_RD_QOS_PRI register field. */
+#define ALT_L3_RD_QOS_PRI_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_RD_QOS_PRI register field. */
+#define ALT_L3_RD_QOS_PRI_MSB        3
+/* The width in bits of the ALT_L3_RD_QOS_PRI register field. */
+#define ALT_L3_RD_QOS_PRI_WIDTH      4
+/* The mask used to set the ALT_L3_RD_QOS_PRI register field value. */
+#define ALT_L3_RD_QOS_PRI_SET_MSK    0x0000000f
+/* The mask used to clear the ALT_L3_RD_QOS_PRI register field value. */
+#define ALT_L3_RD_QOS_PRI_CLR_MSK    0xfffffff0
+/* The reset value of the ALT_L3_RD_QOS_PRI register field. */
+#define ALT_L3_RD_QOS_PRI_RESET      0x0
+/* Extracts the ALT_L3_RD_QOS_PRI field value from a register. */
+#define ALT_L3_RD_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0)
+/* Produces a ALT_L3_RD_QOS_PRI register field value suitable for setting the register. */
+#define ALT_L3_RD_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_RD_QOS.
+ */
+struct ALT_L3_RD_QOS_s
+{
+    uint32_t  pri :  4;  /* Priority */
+    uint32_t      : 28;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_RD_QOS. */
+typedef volatile struct ALT_L3_RD_QOS_s  ALT_L3_RD_QOS_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_RD_QOS register from the beginning of the component. */
+#define ALT_L3_RD_QOS_OFST        0x100
+/* The address of the ALT_L3_RD_QOS register. */
+#define ALT_L3_RD_QOS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_RD_QOS_OFST))
+
+/*
+ * Register : Write Channel QoS Value - write_qos
+ * 
+ * QoS (Quality of Service) value for the write channel.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [3:0]  | RW     | 0x0   | Priority   
+ *  [31:4] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : Priority - pri
+ * 
+ * QoS (Quality of Service) value for the write channel. A higher value has a
+ * higher priority.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_L3_WR_QOS_PRI register field. */
+#define ALT_L3_WR_QOS_PRI_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_L3_WR_QOS_PRI register field. */
+#define ALT_L3_WR_QOS_PRI_MSB        3
+/* The width in bits of the ALT_L3_WR_QOS_PRI register field. */
+#define ALT_L3_WR_QOS_PRI_WIDTH      4
+/* The mask used to set the ALT_L3_WR_QOS_PRI register field value. */
+#define ALT_L3_WR_QOS_PRI_SET_MSK    0x0000000f
+/* The mask used to clear the ALT_L3_WR_QOS_PRI register field value. */
+#define ALT_L3_WR_QOS_PRI_CLR_MSK    0xfffffff0
+/* The reset value of the ALT_L3_WR_QOS_PRI register field. */
+#define ALT_L3_WR_QOS_PRI_RESET      0x0
+/* Extracts the ALT_L3_WR_QOS_PRI field value from a register. */
+#define ALT_L3_WR_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0)
+/* Produces a ALT_L3_WR_QOS_PRI register field value suitable for setting the register. */
+#define ALT_L3_WR_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_L3_WR_QOS.
+ */
+struct ALT_L3_WR_QOS_s
+{
+    uint32_t  pri :  4;  /* Priority */
+    uint32_t      : 28;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_L3_WR_QOS. */
+typedef volatile struct ALT_L3_WR_QOS_s  ALT_L3_WR_QOS_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_L3_WR_QOS register from the beginning of the component. */
+#define ALT_L3_WR_QOS_OFST        0x104
+/* The address of the ALT_L3_WR_QOS register. */
+#define ALT_L3_WR_QOS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_QOS_OFST))
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLV_DAP.
+ */
+struct ALT_L3_SLV_DAP_s
+{
+    volatile uint32_t             _pad_0x0_0x23[9];    /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD2_t     fn_mod2;             /* ALT_L3_FN_MOD2 */
+    volatile ALT_L3_FN_MOD_AHB_t  fn_mod_ahb;          /* ALT_L3_FN_MOD_AHB */
+    volatile uint32_t             _pad_0x2c_0xff[53];  /* *UNDEFINED* */
+    volatile ALT_L3_RD_QOS_t      read_qos;            /* ALT_L3_RD_QOS */
+    volatile ALT_L3_WR_QOS_t      write_qos;           /* ALT_L3_WR_QOS */
+    volatile ALT_L3_FN_MOD_t      fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_SLV_DAP. */
+typedef volatile struct ALT_L3_SLV_DAP_s  ALT_L3_SLV_DAP_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLV_DAP. */
+struct ALT_L3_SLV_DAP_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x23[9];    /* *UNDEFINED* */
+    volatile uint32_t  fn_mod2;             /* ALT_L3_FN_MOD2 */
+    volatile uint32_t  fn_mod_ahb;          /* ALT_L3_FN_MOD_AHB */
+    volatile uint32_t  _pad_0x2c_0xff[53];  /* *UNDEFINED* */
+    volatile uint32_t  read_qos;            /* ALT_L3_RD_QOS */
+    volatile uint32_t  write_qos;           /* ALT_L3_WR_QOS */
+    volatile uint32_t  fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DAP. */
+typedef volatile struct ALT_L3_SLV_DAP_raw_s  ALT_L3_SLV_DAP_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : MPU - ALT_L3_SLV_MPU
+ * MPU
+ * 
+ * Registers associated with the MPU slave interface. This slave is used by the MPU
+ * to access slaves attached to the L3/L4 Interconnect.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLV_MPU.
+ */
+struct ALT_L3_SLV_MPU_s
+{
+    volatile uint32_t         _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile ALT_L3_RD_QOS_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile ALT_L3_WR_QOS_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile ALT_L3_FN_MOD_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_SLV_MPU. */
+typedef volatile struct ALT_L3_SLV_MPU_s  ALT_L3_SLV_MPU_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLV_MPU. */
+struct ALT_L3_SLV_MPU_raw_s
+{
+    volatile uint32_t  _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile uint32_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile uint32_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile uint32_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_MPU. */
+typedef volatile struct ALT_L3_SLV_MPU_raw_s  ALT_L3_SLV_MPU_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : SDMMC - ALT_L3_SLV_SDMMC
+ * SDMMC
+ * 
+ * Registers associated with the SDMMC slave interface. This slave is used by the
+ * DMA controller built into the SDMMC to access slaves attached to the L3/L4
+ * Interconnect.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLV_SDMMC.
+ */
+struct ALT_L3_SLV_SDMMC_s
+{
+    volatile uint32_t             _pad_0x0_0x27[10];   /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_AHB_t  fn_mod_ahb;          /* ALT_L3_FN_MOD_AHB */
+    volatile uint32_t             _pad_0x2c_0xff[53];  /* *UNDEFINED* */
+    volatile ALT_L3_RD_QOS_t      read_qos;            /* ALT_L3_RD_QOS */
+    volatile ALT_L3_WR_QOS_t      write_qos;           /* ALT_L3_WR_QOS */
+    volatile ALT_L3_FN_MOD_t      fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_SLV_SDMMC. */
+typedef volatile struct ALT_L3_SLV_SDMMC_s  ALT_L3_SLV_SDMMC_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */
+struct ALT_L3_SLV_SDMMC_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x27[10];   /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_ahb;          /* ALT_L3_FN_MOD_AHB */
+    volatile uint32_t  _pad_0x2c_0xff[53];  /* *UNDEFINED* */
+    volatile uint32_t  read_qos;            /* ALT_L3_RD_QOS */
+    volatile uint32_t  write_qos;           /* ALT_L3_WR_QOS */
+    volatile uint32_t  fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */
+typedef volatile struct ALT_L3_SLV_SDMMC_raw_s  ALT_L3_SLV_SDMMC_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : DMA - ALT_L3_SLV_DMA
+ * DMA
+ * 
+ * Registers associated with the DMA Controller slave interface. This slave is used
+ * by the DMA Controller to access slaves attached to the L3/L4 Interconnect.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLV_DMA.
+ */
+struct ALT_L3_SLV_DMA_s
+{
+    volatile uint32_t         _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile ALT_L3_RD_QOS_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile ALT_L3_WR_QOS_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile ALT_L3_FN_MOD_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_SLV_DMA. */
+typedef volatile struct ALT_L3_SLV_DMA_s  ALT_L3_SLV_DMA_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLV_DMA. */
+struct ALT_L3_SLV_DMA_raw_s
+{
+    volatile uint32_t  _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile uint32_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile uint32_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile uint32_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DMA. */
+typedef volatile struct ALT_L3_SLV_DMA_raw_s  ALT_L3_SLV_DMA_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : FPGA2HPS - ALT_L3_SLV_F2H
+ * FPGA2HPS
+ * 
+ * Registers associated with the FPGA2HPS AXI Bridge slave interface. This slave is
+ * used by the FPGA2HPS AXI Bridge to access slaves attached to the L3/L4
+ * Interconnect.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLV_F2H.
+ */
+struct ALT_L3_SLV_F2H_s
+{
+    volatile uint32_t              _pad_0x0_0x3f[16];   /* *UNDEFINED* */
+    volatile ALT_L3_WR_TIDEMARK_t  wr_tidemark;         /* ALT_L3_WR_TIDEMARK */
+    volatile uint32_t              _pad_0x44_0xff[47];  /* *UNDEFINED* */
+    volatile ALT_L3_RD_QOS_t       read_qos;            /* ALT_L3_RD_QOS */
+    volatile ALT_L3_WR_QOS_t       write_qos;           /* ALT_L3_WR_QOS */
+    volatile ALT_L3_FN_MOD_t       fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_SLV_F2H. */
+typedef volatile struct ALT_L3_SLV_F2H_s  ALT_L3_SLV_F2H_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLV_F2H. */
+struct ALT_L3_SLV_F2H_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x3f[16];   /* *UNDEFINED* */
+    volatile uint32_t  wr_tidemark;         /* ALT_L3_WR_TIDEMARK */
+    volatile uint32_t  _pad_0x44_0xff[47];  /* *UNDEFINED* */
+    volatile uint32_t  read_qos;            /* ALT_L3_RD_QOS */
+    volatile uint32_t  write_qos;           /* ALT_L3_WR_QOS */
+    volatile uint32_t  fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_F2H. */
+typedef volatile struct ALT_L3_SLV_F2H_raw_s  ALT_L3_SLV_F2H_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : ETR - ALT_L3_SLV_ETR
+ * ETR
+ * 
+ * Registers associated with the ETR (TMC) slave interface. This slave is used by
+ * the ETR to access slaves attached to the L3/L4 Interconnect.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLV_ETR.
+ */
+struct ALT_L3_SLV_ETR_s
+{
+    volatile uint32_t         _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile ALT_L3_RD_QOS_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile ALT_L3_WR_QOS_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile ALT_L3_FN_MOD_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_SLV_ETR. */
+typedef volatile struct ALT_L3_SLV_ETR_s  ALT_L3_SLV_ETR_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLV_ETR. */
+struct ALT_L3_SLV_ETR_raw_s
+{
+    volatile uint32_t  _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile uint32_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile uint32_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile uint32_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_ETR. */
+typedef volatile struct ALT_L3_SLV_ETR_raw_s  ALT_L3_SLV_ETR_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : EMAC0 - ALT_L3_SLV_EMAC0
+ * EMAC0
+ * 
+ * Registers associated with the EMAC0 slave interface. This slave is used by the
+ * DMA controller built into the EMAC0 to access slaves attached to the L3/L4
+ * Interconnect.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLV_EMAC0.
+ */
+struct ALT_L3_SLV_EMAC0_s
+{
+    volatile uint32_t         _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile ALT_L3_RD_QOS_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile ALT_L3_WR_QOS_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile ALT_L3_FN_MOD_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_SLV_EMAC0. */
+typedef volatile struct ALT_L3_SLV_EMAC0_s  ALT_L3_SLV_EMAC0_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */
+struct ALT_L3_SLV_EMAC0_raw_s
+{
+    volatile uint32_t  _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile uint32_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile uint32_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile uint32_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */
+typedef volatile struct ALT_L3_SLV_EMAC0_raw_s  ALT_L3_SLV_EMAC0_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : EMAC1 - ALT_L3_SLV_EMAC1
+ * EMAC1
+ * 
+ * Registers associated with the EMAC1 slave interface. This slave is used by the
+ * DMA controller built into the EMAC1 to access slaves attached to the L3/L4
+ * Interconnect.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLV_EMAC1.
+ */
+struct ALT_L3_SLV_EMAC1_s
+{
+    volatile uint32_t         _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile ALT_L3_RD_QOS_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile ALT_L3_WR_QOS_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile ALT_L3_FN_MOD_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_SLV_EMAC1. */
+typedef volatile struct ALT_L3_SLV_EMAC1_s  ALT_L3_SLV_EMAC1_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */
+struct ALT_L3_SLV_EMAC1_raw_s
+{
+    volatile uint32_t  _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile uint32_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile uint32_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile uint32_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */
+typedef volatile struct ALT_L3_SLV_EMAC1_raw_s  ALT_L3_SLV_EMAC1_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : USB0 - ALT_L3_SLV_USB0
+ * USB0
+ * 
+ * Registers associated with the USB0 slave interface. This slave is used by the
+ * DMA controller built into the USB0 to access slaves attached to the L3/L4
+ * Interconnect.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLV_USB0.
+ */
+struct ALT_L3_SLV_USB0_s
+{
+    volatile uint32_t             _pad_0x0_0x27[10];   /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_AHB_t  fn_mod_ahb;          /* ALT_L3_FN_MOD_AHB */
+    volatile uint32_t             _pad_0x2c_0xff[53];  /* *UNDEFINED* */
+    volatile ALT_L3_RD_QOS_t      read_qos;            /* ALT_L3_RD_QOS */
+    volatile ALT_L3_WR_QOS_t      write_qos;           /* ALT_L3_WR_QOS */
+    volatile ALT_L3_FN_MOD_t      fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_SLV_USB0. */
+typedef volatile struct ALT_L3_SLV_USB0_s  ALT_L3_SLV_USB0_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB0. */
+struct ALT_L3_SLV_USB0_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x27[10];   /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_ahb;          /* ALT_L3_FN_MOD_AHB */
+    volatile uint32_t  _pad_0x2c_0xff[53];  /* *UNDEFINED* */
+    volatile uint32_t  read_qos;            /* ALT_L3_RD_QOS */
+    volatile uint32_t  write_qos;           /* ALT_L3_WR_QOS */
+    volatile uint32_t  fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB0. */
+typedef volatile struct ALT_L3_SLV_USB0_raw_s  ALT_L3_SLV_USB0_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : NAND - ALT_L3_SLV_NAND
+ * NAND
+ * 
+ * Registers associated with the NAND slave interface. This slave is used by the
+ * DMA controller built into the NAND flash controller to access slaves attached to
+ * the L3/L4 Interconnect.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLV_NAND.
+ */
+struct ALT_L3_SLV_NAND_s
+{
+    volatile uint32_t         _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile ALT_L3_RD_QOS_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile ALT_L3_WR_QOS_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile ALT_L3_FN_MOD_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_SLV_NAND. */
+typedef volatile struct ALT_L3_SLV_NAND_s  ALT_L3_SLV_NAND_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLV_NAND. */
+struct ALT_L3_SLV_NAND_raw_s
+{
+    volatile uint32_t  _pad_0x0_0xff[64];  /* *UNDEFINED* */
+    volatile uint32_t  read_qos;           /* ALT_L3_RD_QOS */
+    volatile uint32_t  write_qos;          /* ALT_L3_WR_QOS */
+    volatile uint32_t  fn_mod;             /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_NAND. */
+typedef volatile struct ALT_L3_SLV_NAND_raw_s  ALT_L3_SLV_NAND_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : USB1 - ALT_L3_SLV_USB1
+ * USB1
+ * 
+ * Registers associated with the USB1 slave interface. This slave is used by the
+ * DMA controller built into the USB1 to access slaves attached to the L3/L4
+ * Interconnect.
+ * 
+ */
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLV_USB1.
+ */
+struct ALT_L3_SLV_USB1_s
+{
+    volatile uint32_t             _pad_0x0_0x27[10];   /* *UNDEFINED* */
+    volatile ALT_L3_FN_MOD_AHB_t  fn_mod_ahb;          /* ALT_L3_FN_MOD_AHB */
+    volatile uint32_t             _pad_0x2c_0xff[53];  /* *UNDEFINED* */
+    volatile ALT_L3_RD_QOS_t      read_qos;            /* ALT_L3_RD_QOS */
+    volatile ALT_L3_WR_QOS_t      write_qos;           /* ALT_L3_WR_QOS */
+    volatile ALT_L3_FN_MOD_t      fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for register group ALT_L3_SLV_USB1. */
+typedef volatile struct ALT_L3_SLV_USB1_s  ALT_L3_SLV_USB1_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB1. */
+struct ALT_L3_SLV_USB1_raw_s
+{
+    volatile uint32_t  _pad_0x0_0x27[10];   /* *UNDEFINED* */
+    volatile uint32_t  fn_mod_ahb;          /* ALT_L3_FN_MOD_AHB */
+    volatile uint32_t  _pad_0x2c_0xff[53];  /* *UNDEFINED* */
+    volatile uint32_t  read_qos;            /* ALT_L3_RD_QOS */
+    volatile uint32_t  write_qos;           /* ALT_L3_WR_QOS */
+    volatile uint32_t  fn_mod;              /* ALT_L3_FN_MOD */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB1. */
+typedef volatile struct ALT_L3_SLV_USB1_raw_s  ALT_L3_SLV_USB1_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3_SLVGRP.
+ */
+struct ALT_L3_SLVGRP_s
+{
+    volatile ALT_L3_SLV_DAP_t    slavegrp_dap;             /* ALT_L3_SLV_DAP */
+    volatile uint32_t            _pad_0x10c_0xfff[957];    /* *UNDEFINED* */
+    volatile ALT_L3_SLV_MPU_t    slavegrp_mpu;             /* ALT_L3_SLV_MPU */
+    volatile uint32_t            _pad_0x110c_0x1fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_SDMMC_t  slavegrp_sdmmc;           /* ALT_L3_SLV_SDMMC */
+    volatile uint32_t            _pad_0x210c_0x2fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_DMA_t    slavegrp_dma;             /* ALT_L3_SLV_DMA */
+    volatile uint32_t            _pad_0x310c_0x3fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_F2H_t    slavegrp_fpga2hps;        /* ALT_L3_SLV_F2H */
+    volatile uint32_t            _pad_0x410c_0x4fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_ETR_t    slavegrp_etr;             /* ALT_L3_SLV_ETR */
+    volatile uint32_t            _pad_0x510c_0x5fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_EMAC0_t  slavegrp_emac0;           /* ALT_L3_SLV_EMAC0 */
+    volatile uint32_t            _pad_0x610c_0x6fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_EMAC1_t  slavegrp_emac1;           /* ALT_L3_SLV_EMAC1 */
+    volatile uint32_t            _pad_0x710c_0x7fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_USB0_t   slavegrp_usb0;            /* ALT_L3_SLV_USB0 */
+    volatile uint32_t            _pad_0x810c_0x8fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_NAND_t   slavegrp_nand;            /* ALT_L3_SLV_NAND */
+    volatile uint32_t            _pad_0x910c_0x9fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_USB1_t   slavegrp_usb1;            /* ALT_L3_SLV_USB1 */
+};
+
+/* The typedef declaration for register group ALT_L3_SLVGRP. */
+typedef volatile struct ALT_L3_SLVGRP_s  ALT_L3_SLVGRP_t;
+/* The struct declaration for the raw register contents of register group ALT_L3_SLVGRP. */
+struct ALT_L3_SLVGRP_raw_s
+{
+    volatile ALT_L3_SLV_DAP_raw_t    slavegrp_dap;             /* ALT_L3_SLV_DAP */
+    volatile uint32_t                _pad_0x10c_0xfff[957];    /* *UNDEFINED* */
+    volatile ALT_L3_SLV_MPU_raw_t    slavegrp_mpu;             /* ALT_L3_SLV_MPU */
+    volatile uint32_t                _pad_0x110c_0x1fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_SDMMC_raw_t  slavegrp_sdmmc;           /* ALT_L3_SLV_SDMMC */
+    volatile uint32_t                _pad_0x210c_0x2fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_DMA_raw_t    slavegrp_dma;             /* ALT_L3_SLV_DMA */
+    volatile uint32_t                _pad_0x310c_0x3fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_F2H_raw_t    slavegrp_fpga2hps;        /* ALT_L3_SLV_F2H */
+    volatile uint32_t                _pad_0x410c_0x4fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_ETR_raw_t    slavegrp_etr;             /* ALT_L3_SLV_ETR */
+    volatile uint32_t                _pad_0x510c_0x5fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_EMAC0_raw_t  slavegrp_emac0;           /* ALT_L3_SLV_EMAC0 */
+    volatile uint32_t                _pad_0x610c_0x6fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_EMAC1_raw_t  slavegrp_emac1;           /* ALT_L3_SLV_EMAC1 */
+    volatile uint32_t                _pad_0x710c_0x7fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_USB0_raw_t   slavegrp_usb0;            /* ALT_L3_SLV_USB0 */
+    volatile uint32_t                _pad_0x810c_0x8fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_NAND_raw_t   slavegrp_nand;            /* ALT_L3_SLV_NAND */
+    volatile uint32_t                _pad_0x910c_0x9fff[957];  /* *UNDEFINED* */
+    volatile ALT_L3_SLV_USB1_raw_t   slavegrp_usb1;            /* ALT_L3_SLV_USB1 */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3_SLVGRP. */
+typedef volatile struct ALT_L3_SLVGRP_raw_s  ALT_L3_SLVGRP_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_L3.
+ */
+struct ALT_L3_s
+{
+    volatile ALT_L3_REMAP_t   remap;                        /* ALT_L3_REMAP */
+    volatile uint32_t         _pad_0x4_0x7;                 /* *UNDEFINED* */
+    volatile ALT_L3_SECGRP_t  secgrp;                       /* ALT_L3_SECGRP */
+    volatile uint32_t         _pad_0xa4_0xfff[983];         /* *UNDEFINED* */
+    volatile ALT_L3_IDGRP_t   idgrp;                        /* ALT_L3_IDGRP */
+    volatile ALT_L3_MSTGRP_t  mastergrp;                    /* ALT_L3_MSTGRP */
+    volatile uint32_t         _pad_0x2710c_0x41fff[27581];  /* *UNDEFINED* */
+    volatile ALT_L3_SLVGRP_t  slavegrp;                     /* ALT_L3_SLVGRP */
+    volatile uint32_t         _pad_0x4c10c_0x80000[53181];  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register group ALT_L3. */
+typedef volatile struct ALT_L3_s  ALT_L3_t;
+/* The struct declaration for the raw register contents of register group ALT_L3. */
+struct ALT_L3_raw_s
+{
+    volatile uint32_t             remap;                        /* ALT_L3_REMAP */
+    volatile uint32_t             _pad_0x4_0x7;                 /* *UNDEFINED* */
+    volatile ALT_L3_SECGRP_raw_t  secgrp;                       /* ALT_L3_SECGRP */
+    volatile uint32_t             _pad_0xa4_0xfff[983];         /* *UNDEFINED* */
+    volatile ALT_L3_IDGRP_raw_t   idgrp;                        /* ALT_L3_IDGRP */
+    volatile ALT_L3_MSTGRP_raw_t  mastergrp;                    /* ALT_L3_MSTGRP */
+    volatile uint32_t             _pad_0x2710c_0x41fff[27581];  /* *UNDEFINED* */
+    volatile ALT_L3_SLVGRP_raw_t  slavegrp;                     /* ALT_L3_SLVGRP */
+    volatile uint32_t             _pad_0x4c10c_0x80000[53181];  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_L3. */
+typedef volatile struct ALT_L3_raw_s  ALT_L3_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALTERA_ALT_L3_H__ */
+
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_rstmgr.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_rstmgr.h
new file mode 100644
index 0000000..ab4ac65
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_rstmgr.h
@@ -0,0 +1,3382 @@
+/*******************************************************************************
+*                                                                              *
+* Copyright 2013 Altera Corporation. All Rights Reserved.                      *
+*                                                                              *
+* Redistribution and use in source and binary forms, with or without           *
+* modification, are permitted provided that the following conditions are met:  *
+*                                                                              *
+* 1. Redistributions of source code must retain the above copyright notice,    *
+*    this list of conditions and the following disclaimer.                     *
+*                                                                              *
+* 2. Redistributions in binary form must reproduce the above copyright notice, *
+*    this list of conditions and the following disclaimer in the documentation *
+*    and/or other materials provided with the distribution.                    *
+*                                                                              *
+* 3. The name of the author may not be used to endorse or promote products     *
+*    derived from this software without specific prior written permission.     *
+*                                                                              *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO  *
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,       *
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;  *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,     *
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR      *
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF       *
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                   *
+*                                                                              *
+*******************************************************************************/
+
+/* Altera - ALT_RSTMGR */
+
+#ifndef __ALTERA_ALT_RSTMGR_H__
+#define __ALTERA_ALT_RSTMGR_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*
+ * Component : Reset Manager Module - ALT_RSTMGR
+ * Reset Manager Module
+ * 
+ * Registers in the Reset Manager module
+ * 
+ */
+/*
+ * Register : Status Register - stat
+ * 
+ * The STAT register contains bits that indicate the reset source or a timeout
+ * event. For reset sources, a field is 1 if its associated reset requester caused
+ * the reset. For timeout events, a field is 1 if its associated timeout occured as
+ * part of a hardware sequenced warm/debug reset.
+ * 
+ * Software clears bits by writing them with a value of 1. Writes to bits with a
+ * value of 0 are ignored.
+ * 
+ * After a cold reset is complete, all bits are reset to their reset value except
+ * for the bit(s) that indicate the source of the cold reset. If multiple cold
+ * reset requests overlap with each other, the source de-asserts the request last
+ * will be logged. The other reset request source(s)  de-assert the request in the
+ * same cycle will also be logged, the rest of the fields are reset to default
+ * value of 0.
+ * 
+ * After a warm reset is complete, the bit(s) that indicate the source of  the warm
+ * reset are set to 1. A warm reset doesn't clear any of the bits  in the STAT
+ * register; these bits must be cleared by software writing  the STAT register.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                         
+ * :--------|:-------|:------|:-------------------------------------
+ *  [0]     | RW     | 0x0   | Power-On Voltage Detector Cold Reset
+ *  [1]     | RW     | 0x0   | nPOR Pin Cold Reset                 
+ *  [2]     | RW     | 0x0   | FPGA Core Cold Reset                
+ *  [3]     | RW     | 0x0   | CONFIG_IO Cold Reset                
+ *  [4]     | RW     | 0x0   | Software Cold Reset                 
+ *  [7:5]   | ???    | 0x0   | *UNDEFINED*                         
+ *  [8]     | RW     | 0x0   | nRST Pin Warm Reset                 
+ *  [9]     | RW     | 0x0   | FPGA Core Warm Reset                
+ *  [10]    | RW     | 0x0   | Software Warm Reset                 
+ *  [11]    | ???    | 0x0   | *UNDEFINED*                         
+ *  [12]    | RW     | 0x0   | MPU Watchdog 0 Warm Reset           
+ *  [13]    | RW     | 0x0   | MPU Watchdog 1 Warm Reset           
+ *  [14]    | RW     | 0x0   | L4 Watchdog 0 Warm Reset            
+ *  [15]    | RW     | 0x0   | L4 Watchdog 1 Warm Reset            
+ *  [17:16] | ???    | 0x0   | *UNDEFINED*                         
+ *  [18]    | RW     | 0x0   | FPGA Core Debug Reset               
+ *  [19]    | RW     | 0x0   | DAP Debug Reset                     
+ *  [23:20] | ???    | 0x0   | *UNDEFINED*                         
+ *  [24]    | RW     | 0x0   | SDRAM Self-Refresh Timeout          
+ *  [25]    | RW     | 0x0   | FPGA manager handshake Timeout      
+ *  [26]    | RW     | 0x0   | SCAN manager handshake Timeout      
+ *  [27]    | RW     | 0x0   | FPGA handshake Timeout              
+ *  [28]    | RW     | 0x0   | ETR Stall Timeout                   
+ *  [31:29] | ???    | 0x0   | *UNDEFINED*                         
+ * 
+ */
+/*
+ * Field : Power-On Voltage Detector Cold Reset - porvoltrst
+ * 
+ * Built-in POR voltage detector triggered a cold reset (por_voltage_req = 1)
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
+#define ALT_RSTMGR_STAT_PORVOLTRST_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
+#define ALT_RSTMGR_STAT_PORVOLTRST_MSB        0
+/* The width in bits of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
+#define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_PORVOLTRST register field value. */
+#define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK    0x00000001
+/* The mask used to clear the ALT_RSTMGR_STAT_PORVOLTRST register field value. */
+#define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
+#define ALT_RSTMGR_STAT_PORVOLTRST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_PORVOLTRST field value from a register. */
+#define ALT_RSTMGR_STAT_PORVOLTRST_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_RSTMGR_STAT_PORVOLTRST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_PORVOLTRST_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : nPOR Pin Cold Reset - nporpinrst
+ * 
+ * nPOR pin triggered a cold reset (por_pin_req = 1)
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */
+#define ALT_RSTMGR_STAT_NPORPINRST_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */
+#define ALT_RSTMGR_STAT_NPORPINRST_MSB        1
+/* The width in bits of the ALT_RSTMGR_STAT_NPORPINRST register field. */
+#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_NPORPINRST register field value. */
+#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK    0x00000002
+/* The mask used to clear the ALT_RSTMGR_STAT_NPORPINRST register field value. */
+#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_RSTMGR_STAT_NPORPINRST register field. */
+#define ALT_RSTMGR_STAT_NPORPINRST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_NPORPINRST field value from a register. */
+#define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_RSTMGR_STAT_NPORPINRST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : FPGA Core Cold Reset - fpgacoldrst
+ * 
+ * FPGA core triggered a cold reset (f2h_cold_rst_req_n = 1)
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
+#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
+#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB        2
+/* The width in bits of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
+#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */
+#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK    0x00000004
+/* The mask used to clear the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */
+#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
+#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_FPGACOLDRST field value from a register. */
+#define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_RSTMGR_STAT_FPGACOLDRST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : CONFIG_IO Cold Reset - configiocoldrst
+ * 
+ * FPGA entered CONFIG_IO mode and a triggered a cold reset
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
+#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
+#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB        3
+/* The width in bits of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
+#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */
+#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK    0x00000008
+/* The mask used to clear the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */
+#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
+#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_CFGIOCOLDRST field value from a register. */
+#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_RSTMGR_STAT_CFGIOCOLDRST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : Software Cold Reset - swcoldrst
+ * 
+ * Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
+#define ALT_RSTMGR_STAT_SWCOLDRST_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
+#define ALT_RSTMGR_STAT_SWCOLDRST_MSB        4
+/* The width in bits of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
+#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_SWCOLDRST register field value. */
+#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK    0x00000010
+/* The mask used to clear the ALT_RSTMGR_STAT_SWCOLDRST register field value. */
+#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK    0xffffffef
+/* The reset value of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
+#define ALT_RSTMGR_STAT_SWCOLDRST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_SWCOLDRST field value from a register. */
+#define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_RSTMGR_STAT_SWCOLDRST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : nRST Pin Warm Reset - nrstpinrst
+ * 
+ * nRST pin triggered a hardware sequenced warm reset
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
+#define ALT_RSTMGR_STAT_NRSTPINRST_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
+#define ALT_RSTMGR_STAT_NRSTPINRST_MSB        8
+/* The width in bits of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
+#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_NRSTPINRST register field value. */
+#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK    0x00000100
+/* The mask used to clear the ALT_RSTMGR_STAT_NRSTPINRST register field value. */
+#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
+#define ALT_RSTMGR_STAT_NRSTPINRST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_NRSTPINRST field value from a register. */
+#define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_RSTMGR_STAT_NRSTPINRST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : FPGA Core Warm Reset - fpgawarmrst
+ * 
+ * FPGA core triggered a hardware sequenced warm reset (f2h_warm_rst_req_n = 1)
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
+#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
+#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB        9
+/* The width in bits of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
+#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */
+#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK    0x00000200
+/* The mask used to clear the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */
+#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
+#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_FPGAWARMRST field value from a register. */
+#define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_RSTMGR_STAT_FPGAWARMRST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200)
+
+/*
+ * Field : Software Warm Reset - swwarmrst
+ * 
+ * Software wrote CTRL.SWWARMRSTREQ to 1 and triggered a hardware sequenced warm
+ * reset
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */
+#define ALT_RSTMGR_STAT_SWWARMRST_LSB        10
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */
+#define ALT_RSTMGR_STAT_SWWARMRST_MSB        10
+/* The width in bits of the ALT_RSTMGR_STAT_SWWARMRST register field. */
+#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_SWWARMRST register field value. */
+#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK    0x00000400
+/* The mask used to clear the ALT_RSTMGR_STAT_SWWARMRST register field value. */
+#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK    0xfffffbff
+/* The reset value of the ALT_RSTMGR_STAT_SWWARMRST register field. */
+#define ALT_RSTMGR_STAT_SWWARMRST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_SWWARMRST field value from a register. */
+#define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10)
+/* Produces a ALT_RSTMGR_STAT_SWWARMRST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400)
+
+/*
+ * Field : MPU Watchdog 0 Warm Reset - mpuwd0rst
+ * 
+ * MPU Watchdog 0 triggered a hardware sequenced warm reset
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
+#define ALT_RSTMGR_STAT_MPUWD0RST_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
+#define ALT_RSTMGR_STAT_MPUWD0RST_MSB        12
+/* The width in bits of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
+#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_MPUWD0RST register field value. */
+#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK    0x00001000
+/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD0RST register field value. */
+#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK    0xffffefff
+/* The reset value of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
+#define ALT_RSTMGR_STAT_MPUWD0RST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_MPUWD0RST field value from a register. */
+#define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00001000) >> 12)
+/* Produces a ALT_RSTMGR_STAT_MPUWD0RST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 12) & 0x00001000)
+
+/*
+ * Field : MPU Watchdog 1 Warm Reset - mpuwd1rst
+ * 
+ * MPU Watchdog 1 triggered a hardware sequenced warm reset
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
+#define ALT_RSTMGR_STAT_MPUWD1RST_LSB        13
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
+#define ALT_RSTMGR_STAT_MPUWD1RST_MSB        13
+/* The width in bits of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
+#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_MPUWD1RST register field value. */
+#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK    0x00002000
+/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD1RST register field value. */
+#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK    0xffffdfff
+/* The reset value of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
+#define ALT_RSTMGR_STAT_MPUWD1RST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_MPUWD1RST field value from a register. */
+#define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00002000) >> 13)
+/* Produces a ALT_RSTMGR_STAT_MPUWD1RST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 13) & 0x00002000)
+
+/*
+ * Field : L4 Watchdog 0 Warm Reset - l4wd0rst
+ * 
+ * L4 Watchdog 0 triggered a hardware sequenced warm reset
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
+#define ALT_RSTMGR_STAT_L4WD0RST_LSB        14
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
+#define ALT_RSTMGR_STAT_L4WD0RST_MSB        14
+/* The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field. */
+#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value. */
+#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK    0x00004000
+/* The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value. */
+#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK    0xffffbfff
+/* The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field. */
+#define ALT_RSTMGR_STAT_L4WD0RST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register. */
+#define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00004000) >> 14)
+/* Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 14) & 0x00004000)
+
+/*
+ * Field : L4 Watchdog 1 Warm Reset - l4wd1rst
+ * 
+ * L4 Watchdog 1 triggered a hardware sequenced warm reset
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
+#define ALT_RSTMGR_STAT_L4WD1RST_LSB        15
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
+#define ALT_RSTMGR_STAT_L4WD1RST_MSB        15
+/* The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field. */
+#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value. */
+#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK    0x00008000
+/* The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value. */
+#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK    0xffff7fff
+/* The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field. */
+#define ALT_RSTMGR_STAT_L4WD1RST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register. */
+#define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00008000) >> 15)
+/* Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 15) & 0x00008000)
+
+/*
+ * Field : FPGA Core Debug Reset - fpgadbgrst
+ * 
+ * FPGA triggered debug reset (f2h_dbg_rst_req_n = 1)
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
+#define ALT_RSTMGR_STAT_FPGADBGRST_LSB        18
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
+#define ALT_RSTMGR_STAT_FPGADBGRST_MSB        18
+/* The width in bits of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
+#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_FPGADBGRST register field value. */
+#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK    0x00040000
+/* The mask used to clear the ALT_RSTMGR_STAT_FPGADBGRST register field value. */
+#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK    0xfffbffff
+/* The reset value of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
+#define ALT_RSTMGR_STAT_FPGADBGRST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_FPGADBGRST field value from a register. */
+#define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00040000) >> 18)
+/* Produces a ALT_RSTMGR_STAT_FPGADBGRST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 18) & 0x00040000)
+
+/*
+ * Field : DAP Debug Reset - cdbgreqrst
+ * 
+ * DAP triggered debug reset
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
+#define ALT_RSTMGR_STAT_CDBGREQRST_LSB        19
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
+#define ALT_RSTMGR_STAT_CDBGREQRST_MSB        19
+/* The width in bits of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
+#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_CDBGREQRST register field value. */
+#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK    0x00080000
+/* The mask used to clear the ALT_RSTMGR_STAT_CDBGREQRST register field value. */
+#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK    0xfff7ffff
+/* The reset value of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
+#define ALT_RSTMGR_STAT_CDBGREQRST_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_CDBGREQRST field value from a register. */
+#define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00080000) >> 19)
+/* Produces a ALT_RSTMGR_STAT_CDBGREQRST register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 19) & 0x00080000)
+
+/*
+ * Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout
+ * 
+ * A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to
+ * put the SDRAM devices into self-refresh mode before starting a hardware
+ * sequenced warm reset timed-out and the Reset Manager had to proceed with the
+ * warm reset anyway.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
+#define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB        24
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
+#define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB        24
+/* The width in bits of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
+#define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */
+#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK    0x01000000
+/* The mask used to clear the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */
+#define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK    0xfeffffff
+/* The reset value of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
+#define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_SDRSELFREFTMO field value from a register. */
+#define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value) (((value) & 0x01000000) >> 24)
+/* Produces a ALT_RSTMGR_STAT_SDRSELFREFTMO register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value) (((value) << 24) & 0x01000000)
+
+/*
+ * Field : FPGA manager handshake Timeout - fpgamgrhstimeout
+ * 
+ * A 1 indicates that Reset Manager's request to the FPGA manager to stop driving
+ * configuration clock to FPGA CB before starting a hardware sequenced warm reset
+ * timed-out and the Reset Manager had to proceed with the warm reset anyway.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
+#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB        25
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
+#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB        25
+/* The width in bits of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
+#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */
+#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK    0x02000000
+/* The mask used to clear the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */
+#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK    0xfdffffff
+/* The reset value of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
+#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_FPGAMGRHSTMO field value from a register. */
+#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value) (((value) & 0x02000000) >> 25)
+/* Produces a ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value) (((value) << 25) & 0x02000000)
+
+/*
+ * Field : SCAN manager handshake Timeout - scanhstimeout
+ * 
+ * A 1 indicates that Reset Manager's request to the SCAN manager to stop driving
+ * JTAG clock to FPGA CB before starting a hardware sequenced warm reset timed-out
+ * and the Reset Manager had to proceed with the warm reset anyway.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
+#define ALT_RSTMGR_STAT_SCANHSTMO_LSB        26
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
+#define ALT_RSTMGR_STAT_SCANHSTMO_MSB        26
+/* The width in bits of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
+#define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_SCANHSTMO register field value. */
+#define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK    0x04000000
+/* The mask used to clear the ALT_RSTMGR_STAT_SCANHSTMO register field value. */
+#define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK    0xfbffffff
+/* The reset value of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
+#define ALT_RSTMGR_STAT_SCANHSTMO_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_SCANHSTMO field value from a register. */
+#define ALT_RSTMGR_STAT_SCANHSTMO_GET(value) (((value) & 0x04000000) >> 26)
+/* Produces a ALT_RSTMGR_STAT_SCANHSTMO register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_SCANHSTMO_SET(value) (((value) << 26) & 0x04000000)
+
+/*
+ * Field : FPGA handshake Timeout - fpgahstimeout
+ * 
+ * A 1 indicates that Reset Manager's handshake request to FPGA before starting a
+ * hardware sequenced warm reset timed-out and the Reset Manager had to proceed
+ * with the warm reset anyway.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
+#define ALT_RSTMGR_STAT_FPGAHSTMO_LSB        27
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
+#define ALT_RSTMGR_STAT_FPGAHSTMO_MSB        27
+/* The width in bits of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
+#define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */
+#define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK    0x08000000
+/* The mask used to clear the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */
+#define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK    0xf7ffffff
+/* The reset value of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
+#define ALT_RSTMGR_STAT_FPGAHSTMO_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_FPGAHSTMO field value from a register. */
+#define ALT_RSTMGR_STAT_FPGAHSTMO_GET(value) (((value) & 0x08000000) >> 27)
+/* Produces a ALT_RSTMGR_STAT_FPGAHSTMO register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_FPGAHSTMO_SET(value) (((value) << 27) & 0x08000000)
+
+/*
+ * Field : ETR Stall Timeout - etrstalltimeout
+ * 
+ * A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to
+ * stall its AXI master port before starting a hardware sequenced warm reset timed-
+ * out and the Reset Manager had to proceed with the warm reset anyway.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
+#define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB        28
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
+#define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB        28
+/* The width in bits of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
+#define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */
+#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK    0x10000000
+/* The mask used to clear the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */
+#define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK    0xefffffff
+/* The reset value of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
+#define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET      0x0
+/* Extracts the ALT_RSTMGR_STAT_ETRSTALLTMO field value from a register. */
+#define ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value) (((value) & 0x10000000) >> 28)
+/* Produces a ALT_RSTMGR_STAT_ETRSTALLTMO register field value suitable for setting the register. */
+#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value) (((value) << 28) & 0x10000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_RSTMGR_STAT.
+ */
+struct ALT_RSTMGR_STAT_s
+{
+    uint32_t  porvoltrst        :  1;  /* Power-On Voltage Detector Cold Reset */
+    uint32_t  nporpinrst        :  1;  /* nPOR Pin Cold Reset */
+    uint32_t  fpgacoldrst       :  1;  /* FPGA Core Cold Reset */
+    uint32_t  configiocoldrst   :  1;  /* CONFIG_IO Cold Reset */
+    uint32_t  swcoldrst         :  1;  /* Software Cold Reset */
+    uint32_t                    :  3;  /* *UNDEFINED* */
+    uint32_t  nrstpinrst        :  1;  /* nRST Pin Warm Reset */
+    uint32_t  fpgawarmrst       :  1;  /* FPGA Core Warm Reset */
+    uint32_t  swwarmrst         :  1;  /* Software Warm Reset */
+    uint32_t                    :  1;  /* *UNDEFINED* */
+    uint32_t  mpuwd0rst         :  1;  /* MPU Watchdog 0 Warm Reset */
+    uint32_t  mpuwd1rst         :  1;  /* MPU Watchdog 1 Warm Reset */
+    uint32_t  l4wd0rst          :  1;  /* L4 Watchdog 0 Warm Reset */
+    uint32_t  l4wd1rst          :  1;  /* L4 Watchdog 1 Warm Reset */
+    uint32_t                    :  2;  /* *UNDEFINED* */
+    uint32_t  fpgadbgrst        :  1;  /* FPGA Core Debug Reset */
+    uint32_t  cdbgreqrst        :  1;  /* DAP Debug Reset */
+    uint32_t                    :  4;  /* *UNDEFINED* */
+    uint32_t  sdrselfreftimeout :  1;  /* SDRAM Self-Refresh Timeout */
+    uint32_t  fpgamgrhstimeout  :  1;  /* FPGA manager handshake Timeout */
+    uint32_t  scanhstimeout     :  1;  /* SCAN manager handshake Timeout */
+    uint32_t  fpgahstimeout     :  1;  /* FPGA handshake Timeout */
+    uint32_t  etrstalltimeout   :  1;  /* ETR Stall Timeout */
+    uint32_t                    :  3;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_RSTMGR_STAT. */
+typedef volatile struct ALT_RSTMGR_STAT_s  ALT_RSTMGR_STAT_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component. */
+#define ALT_RSTMGR_STAT_OFST        0x0
+
+/*
+ * Register : Control Register - ctrl
+ * 
+ * The CTRL register is used by software to control reset behavior.It includes
+ * fields for software to initiate the cold and warm reset, enable hardware
+ * handshake with other modules before warm reset, and perform software handshake.
+ * The software handshake sequence must match the hardware sequence. Software
+ * mustde-assert the handshake request after asserting warm reset and before de-
+ * assert the warm reset.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                                       
+ * :--------|:-------|:--------|:---------------------------------------------------
+ *  [0]     | RW     | 0x0     | Software Cold Reset Request                       
+ *  [1]     | RW     | 0x0     | Software Warm Reset Request                       
+ *  [3:2]   | ???    | 0x0     | *UNDEFINED*                                       
+ *  [4]     | RW     | 0x0     | SDRAM Self-Refresh Enable                         
+ *  [5]     | RW     | 0x0     | SDRAM Self-Refresh Request                        
+ *  [6]     | R      | 0x0     | SDRAM Self-Refresh Acknowledge                    
+ *  [7]     | ???    | 0x0     | *UNDEFINED*                                       
+ *  [8]     | RW     | 0x0     | FPGA Manager Handshake Enable                     
+ *  [9]     | RW     | 0x0     | FPGA Manager Handshake Request                    
+ *  [10]    | R      | Unknown | FPGA Manager Handshake Acknowledge                
+ *  [11]    | ???    | 0x0     | *UNDEFINED*                                       
+ *  [12]    | RW     | 0x0     | SCAN Manager Handshake Enable                     
+ *  [13]    | RW     | 0x0     | SCAN Manager Handshake Request                    
+ *  [14]    | R      | Unknown | SCAN Manager Handshake Acknowledge                
+ *  [15]    | ???    | 0x0     | *UNDEFINED*                                       
+ *  [16]    | RW     | 0x0     | FPGA Handshake Enable                             
+ *  [17]    | RW     | 0x0     | FPGA Handshake Request                            
+ *  [18]    | R      | Unknown | FPGA Handshake Acknowledge                        
+ *  [19]    | ???    | 0x0     | *UNDEFINED*                                       
+ *  [20]    | RW     | 0x1     | ETR (Embedded Trace Router) Stall Enable          
+ *  [21]    | RW     | 0x0     | ETR (Embedded Trace Router) Stall Request         
+ *  [22]    | R      | 0x0     | ETR (Embedded Trace Router) Stall Acknowledge     
+ *  [23]    | RW     | 0x0     | ETR (Embedded Trace Router) Stall After Warm Reset
+ *  [31:24] | ???    | 0x0     | *UNDEFINED*                                       
+ * 
+ */
+/*
+ * Field : Software Cold Reset Request - swcoldrstreq
+ * 
+ * This is a one-shot bit written by software to 1 to trigger a cold reset. It
+ * always reads the value 0.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
+#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
+#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB        0
+/* The width in bits of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
+#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */
+#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK    0x00000001
+/* The mask used to clear the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */
+#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
+#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_SWCOLDRSTREQ field value from a register. */
+#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Software Warm Reset Request - swwarmrstreq
+ * 
+ * This is a one-shot bit written by software to 1 to trigger a hardware sequenced
+ * warm reset. It always reads the value 0.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB        1
+/* The width in bits of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK    0x00000002
+/* The mask used to clear the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_SWWARMRSTREQ field value from a register. */
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_RSTMGR_CTL_SWWARMRSTREQ register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : SDRAM Self-Refresh Enable - sdrselfrefen
+ * 
+ * This field controls whether the contents of SDRAM devices survive a hardware
+ * sequenced warm reset. If set to 1, the Reset Manager makes a request to the
+ * SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode
+ * before asserting warm reset signals. However, if SDRAM is already in warm reset,
+ * Handshake with SDRAM is not performed.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB        4
+/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */
+#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK    0x00000010
+/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */
+#define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK    0xffffffef
+/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFEN field value from a register. */
+#define ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_RSTMGR_CTL_SDRSELFREFEN register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : SDRAM Self-Refresh Request - sdrselfrefreq
+ * 
+ * Software writes this field 1 to request to the SDRAM Controller Subsystem that
+ * it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM
+ * contents across a software warm reset.
+ * 
+ * Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0.
+ * Note that it is possible for the SDRAM Controller Subsystem to never assert
+ * SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB        5
+/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */
+#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK    0x00000020
+/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */
+#define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFREQ field value from a register. */
+#define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_RSTMGR_CTL_SDRSELFREFREQ register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack
+ * 
+ * This is the acknowlege for a SDRAM self-refresh mode request initiated by the
+ * SDRSELFREFREQ field.  A 1 indicates that the SDRAM Controller Subsystem has put
+ * the SDRAM devices into self-refresh mode.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB        6
+/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */
+#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK    0x00000040
+/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */
+#define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
+#define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_SDRSELFREQACK field value from a register. */
+#define ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_RSTMGR_CTL_SDRSELFREQACK register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : FPGA Manager Handshake Enable - fpgamgrhsen
+ * 
+ * Enables a handshake between the Reset Manager and FPGA Manager before a warm
+ * reset. The handshake is used to warn the FPGA Manager that a warm reset it
+ * coming so it can prepare for it. When the FPGA Manager receives a warm reset
+ * handshake, the FPGA Manager drives its output clock to a quiescent state to
+ * avoid glitches.
+ * 
+ * If set to 1, the  Manager makes a request to the FPGA Managerbefore asserting
+ * warm reset signals. However if the FPGA Manager is already in warm reset, the
+ * handshake is skipped.
+ * 
+ * If set to 0, the handshake is skipped.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB        8
+/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK    0x00000100
+/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSEN field value from a register. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSEN register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : FPGA Manager Handshake Request - fpgamgrhsreq
+ * 
+ * Software writes this field 1 to request to the FPGA Manager to idle its output
+ * clock.
+ * 
+ * Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0.
+ * Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so
+ * software should timeout in this case.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB        9
+/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK    0x00000200
+/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSREQ field value from a register. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value) (((value) << 9) & 0x00000200)
+
+/*
+ * Field : FPGA Manager Handshake Acknowledge - fpgamgrhsack
+ * 
+ * This is the acknowlege (high active) that the FPGA manager has successfully
+ * idled its output clock.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB        10
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB        10
+/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK    0x00000400
+/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK    0xfffffbff
+/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field is UNKNOWN. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSACK field value from a register. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value) (((value) & 0x00000400) >> 10)
+/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSACK register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value) (((value) << 10) & 0x00000400)
+
+/*
+ * Field : SCAN Manager Handshake Enable - scanmgrhsen
+ * 
+ * Enables a handshake between the Reset Manager and Scan Manager before a warm
+ * reset. The handshake is used to warn the Scan Manager that a warm reset it
+ * coming so it can prepare for it. When the Scan Manager receives a warm reset
+ * handshake, the Scan Manager drives its output clocks to a quiescent state to
+ * avoid glitches.
+ * 
+ * If set to 1, the Reset Manager makes a request to the Scan Managerbefore
+ * asserting warm reset signals. However if the Scan Manager is already in warm
+ * reset, the handshake is skipped.
+ * 
+ * If set to 0, the handshake is skipped.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
+#define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
+#define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB        12
+/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
+#define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */
+#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK    0x00001000
+/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */
+#define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK    0xffffefff
+/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
+#define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSEN field value from a register. */
+#define ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value) (((value) & 0x00001000) >> 12)
+/* Produces a ALT_RSTMGR_CTL_SCANMGRHSEN register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value) (((value) << 12) & 0x00001000)
+
+/*
+ * Field : SCAN Manager Handshake Request - scanmgrhsreq
+ * 
+ * Software writes this field 1 to request to the SCAN manager to idle its output
+ * clocks.
+ * 
+ * Software waits for the SCANMGRHSACK to be 1 and then writes this field to 0.
+ * Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g.
+ * its input clock is disabled) so software should timeout in this case.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
+#define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB        13
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
+#define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB        13
+/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
+#define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */
+#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK    0x00002000
+/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */
+#define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK    0xffffdfff
+/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
+#define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSREQ field value from a register. */
+#define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value) (((value) & 0x00002000) >> 13)
+/* Produces a ALT_RSTMGR_CTL_SCANMGRHSREQ register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value) (((value) << 13) & 0x00002000)
+
+/*
+ * Field : SCAN Manager Handshake Acknowledge - scanmgrhsack
+ * 
+ * This is the acknowlege (high active) that the SCAN manager has   successfully
+ * idled its output clocks.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
+#define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB        14
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
+#define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB        14
+/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
+#define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */
+#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK    0x00004000
+/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */
+#define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK    0xffffbfff
+/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSACK register field is UNKNOWN. */
+#define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSACK field value from a register. */
+#define ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value) (((value) & 0x00004000) >> 14)
+/* Produces a ALT_RSTMGR_CTL_SCANMGRHSACK register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value) (((value) << 14) & 0x00004000)
+
+/*
+ * Field : FPGA Handshake Enable - fpgahsen
+ * 
+ * This field controls whether to perform handshake with FPGA before asserting warm
+ * reset.
+ * 
+ * If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm
+ * reset signals. However if FPGA is already in warm reset state, the handshake is
+ * not performed.
+ * 
+ * If set to 0, the handshake is not performed
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
+#define ALT_RSTMGR_CTL_FPGAHSEN_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
+#define ALT_RSTMGR_CTL_FPGAHSEN_MSB        16
+/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
+#define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSEN register field value. */
+#define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK    0x00010000
+/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSEN register field value. */
+#define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK    0xfffeffff
+/* The reset value of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
+#define ALT_RSTMGR_CTL_FPGAHSEN_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_FPGAHSEN field value from a register. */
+#define ALT_RSTMGR_CTL_FPGAHSEN_GET(value) (((value) & 0x00010000) >> 16)
+/* Produces a ALT_RSTMGR_CTL_FPGAHSEN register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_FPGAHSEN_SET(value) (((value) << 16) & 0x00010000)
+
+/*
+ * Field : FPGA Handshake Request - fpgahsreq
+ * 
+ * Software writes this field 1 to initiate handshake  request to FPGA .
+ * 
+ * Software waits for the FPGAHSACK to be active and then writes this field to 0.
+ * Note that it is possible for the FPGA to never assert FPGAHSACK so software
+ * should timeout in this case.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
+#define ALT_RSTMGR_CTL_FPGAHSREQ_LSB        17
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
+#define ALT_RSTMGR_CTL_FPGAHSREQ_MSB        17
+/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
+#define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */
+#define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK    0x00020000
+/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */
+#define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK    0xfffdffff
+/* The reset value of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
+#define ALT_RSTMGR_CTL_FPGAHSREQ_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_FPGAHSREQ field value from a register. */
+#define ALT_RSTMGR_CTL_FPGAHSREQ_GET(value) (((value) & 0x00020000) >> 17)
+/* Produces a ALT_RSTMGR_CTL_FPGAHSREQ register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_FPGAHSREQ_SET(value) (((value) << 17) & 0x00020000)
+
+/*
+ * Field : FPGA Handshake Acknowledge - fpgahsack
+ * 
+ * This is the acknowlege (high active) that the FPGA handshake   acknowledge has
+ * been received by Reset Manager.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
+#define ALT_RSTMGR_CTL_FPGAHSACK_LSB        18
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
+#define ALT_RSTMGR_CTL_FPGAHSACK_MSB        18
+/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
+#define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSACK register field value. */
+#define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK    0x00040000
+/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSACK register field value. */
+#define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK    0xfffbffff
+/* The reset value of the ALT_RSTMGR_CTL_FPGAHSACK register field is UNKNOWN. */
+#define ALT_RSTMGR_CTL_FPGAHSACK_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_FPGAHSACK field value from a register. */
+#define ALT_RSTMGR_CTL_FPGAHSACK_GET(value) (((value) & 0x00040000) >> 18)
+/* Produces a ALT_RSTMGR_CTL_FPGAHSACK register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_FPGAHSACK_SET(value) (((value) << 18) & 0x00040000)
+
+/*
+ * Field : ETR (Embedded Trace Router) Stall Enable - etrstallen
+ * 
+ * This field controls whether the ETR is requested to idle its AXI master
+ * interface (i.e. finish outstanding transactions and not initiate any more) to
+ * the L3 Interconnect before a warm or debug reset. If set to 1, the Reset Manager
+ * makes a request to the ETR to stall its AXI master and waits for it to finish
+ * any outstanding AXI transactions before a warm reset of the L3 Interconnect or a
+ * debug reset of the ETR. This stalling is required because the debug logic
+ * (including the ETR) is reset on a debug reset and the ETR AXI master is
+ * connected to the L3 Interconnect which is reset on a warm reset and these resets
+ * can happen independently.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLEN_LSB        20
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLEN_MSB        20
+/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */
+#define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK    0x00100000
+/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */
+#define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK    0xffefffff
+/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLEN_RESET      0x1
+/* Extracts the ALT_RSTMGR_CTL_ETRSTALLEN field value from a register. */
+#define ALT_RSTMGR_CTL_ETRSTALLEN_GET(value) (((value) & 0x00100000) >> 20)
+/* Produces a ALT_RSTMGR_CTL_ETRSTALLEN register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_ETRSTALLEN_SET(value) (((value) << 20) & 0x00100000)
+
+/*
+ * Field : ETR (Embedded Trace Router) Stall Request - etrstallreq
+ * 
+ * Software writes this field 1 to request to the ETR that it stalls its AXI master
+ * to the L3 Interconnect.
+ * 
+ * Software waits for the ETRSTALLACK to be 1 and then writes this field to 0.
+ * Note that it is possible for the ETR to never assert ETRSTALLACK so software
+ * should timeout if ETRSTALLACK is never asserted.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB        21
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB        21
+/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */
+#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK    0x00200000
+/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */
+#define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK    0xffdfffff
+/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_ETRSTALLREQ field value from a register. */
+#define ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value) (((value) & 0x00200000) >> 21)
+/* Produces a ALT_RSTMGR_CTL_ETRSTALLREQ register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value) (((value) << 21) & 0x00200000)
+
+/*
+ * Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack
+ * 
+ * This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ
+ * field.  A 1 indicates that the ETR has stalled its AXI master
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLACK_LSB        22
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLACK_MSB        22
+/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */
+#define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK    0x00400000
+/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */
+#define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK    0xffbfffff
+/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLACK_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_ETRSTALLACK field value from a register. */
+#define ALT_RSTMGR_CTL_ETRSTALLACK_GET(value) (((value) & 0x00400000) >> 22)
+/* Produces a ALT_RSTMGR_CTL_ETRSTALLACK register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_ETRSTALLACK_SET(value) (((value) << 22) & 0x00400000)
+
+/*
+ * Field : ETR (Embedded Trace Router) Stall After Warm Reset - etrstallwarmrst
+ * 
+ * If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to
+ * indicate that the stall of the ETR AXI master is pending. Hardware leaves the
+ * ETR stalled until software clears this field by writing it with 1. Software must
+ * only clear this field when it is ready to have the ETR AXI master start making
+ * AXI requests to write trace data.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB        23
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB        23
+/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */
+#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK    0x00800000
+/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */
+#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK    0xff7fffff
+/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
+#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET      0x0
+/* Extracts the ALT_RSTMGR_CTL_ETRSTALLWARMRST field value from a register. */
+#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value) (((value) & 0x00800000) >> 23)
+/* Produces a ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value suitable for setting the register. */
+#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value) (((value) << 23) & 0x00800000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_RSTMGR_CTL.
+ */
+struct ALT_RSTMGR_CTL_s
+{
+    uint32_t        swcoldrstreq    :  1;  /* Software Cold Reset Request */
+    uint32_t        swwarmrstreq    :  1;  /* Software Warm Reset Request */
+    uint32_t                        :  2;  /* *UNDEFINED* */
+    uint32_t        sdrselfrefen    :  1;  /* SDRAM Self-Refresh Enable */
+    uint32_t        sdrselfrefreq   :  1;  /* SDRAM Self-Refresh Request */
+    const uint32_t  sdrselfreqack   :  1;  /* SDRAM Self-Refresh Acknowledge */
+    uint32_t                        :  1;  /* *UNDEFINED* */
+    uint32_t        fpgamgrhsen     :  1;  /* FPGA Manager Handshake Enable */
+    uint32_t        fpgamgrhsreq    :  1;  /* FPGA Manager Handshake Request */
+    const uint32_t  fpgamgrhsack    :  1;  /* FPGA Manager Handshake Acknowledge */
+    uint32_t                        :  1;  /* *UNDEFINED* */
+    uint32_t        scanmgrhsen     :  1;  /* SCAN Manager Handshake Enable */
+    uint32_t        scanmgrhsreq    :  1;  /* SCAN Manager Handshake Request */
+    const uint32_t  scanmgrhsack    :  1;  /* SCAN Manager Handshake Acknowledge */
+    uint32_t                        :  1;  /* *UNDEFINED* */
+    uint32_t        fpgahsen        :  1;  /* FPGA Handshake Enable */
+    uint32_t        fpgahsreq       :  1;  /* FPGA Handshake Request */
+    const uint32_t  fpgahsack       :  1;  /* FPGA Handshake Acknowledge */
+    uint32_t                        :  1;  /* *UNDEFINED* */
+    uint32_t        etrstallen      :  1;  /* ETR (Embedded Trace Router) Stall Enable */
+    uint32_t        etrstallreq     :  1;  /* ETR (Embedded Trace Router) Stall Request */
+    const uint32_t  etrstallack     :  1;  /* ETR (Embedded Trace Router) Stall Acknowledge */
+    uint32_t        etrstallwarmrst :  1;  /* ETR (Embedded Trace Router) Stall After Warm Reset */
+    uint32_t                        :  8;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_RSTMGR_CTL. */
+typedef volatile struct ALT_RSTMGR_CTL_s  ALT_RSTMGR_CTL_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_RSTMGR_CTL register from the beginning of the component. */
+#define ALT_RSTMGR_CTL_OFST        0x4
+
+/*
+ * Register : Reset Cycles Count Register - counts
+ * 
+ * The COUNTS register is used by software to control reset behavior.It includes
+ * fields for software to control the behavior of the warm reset and nRST pin.
+ * 
+ * Fields are only reset by a cold reset.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                   
+ * :--------|:-------|:------|:-------------------------------
+ *  [7:0]   | RW     | 0x80  | Warm reset release delay count
+ *  [27:8]  | RW     | 0x800 | nRST Pin Count                
+ *  [31:28] | ???    | 0x0   | *UNDEFINED*                   
+ * 
+ */
+/*
+ * Field : Warm reset release delay count - warmrstcycles
+ * 
+ * On a warm reset, the Reset Manager releases the reset to the Clock Manager, and
+ * then waits for the number of cycles specified in this register before releasing
+ * the rest of the hardware controlled resets.  Value must be greater than 16.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
+#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
+#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB        7
+/* The width in bits of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
+#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH      8
+/* The mask used to set the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */
+#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */
+#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK    0xffffff00
+/* The reset value of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
+#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET      0x80
+/* Extracts the ALT_RSTMGR_COUNTS_WARMRSTCYCLES field value from a register. */
+#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value suitable for setting the register. */
+#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff)
+
+/*
+ * Field : nRST Pin Count - nrstcnt
+ * 
+ * The Reset Manager pulls down the nRST pin on a warm reset for the number of
+ * cycles specified in this register. A value of 0x0 prevents the Reset Manager
+ * from pulling down the nRST pin.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
+#define ALT_RSTMGR_COUNTS_NRSTCNT_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
+#define ALT_RSTMGR_COUNTS_NRSTCNT_MSB        27
+/* The width in bits of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
+#define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH      20
+/* The mask used to set the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */
+#define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK    0x0fffff00
+/* The mask used to clear the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */
+#define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK    0xf00000ff
+/* The reset value of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
+#define ALT_RSTMGR_COUNTS_NRSTCNT_RESET      0x800
+/* Extracts the ALT_RSTMGR_COUNTS_NRSTCNT field value from a register. */
+#define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8)
+/* Produces a ALT_RSTMGR_COUNTS_NRSTCNT register field value suitable for setting the register. */
+#define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_RSTMGR_COUNTS.
+ */
+struct ALT_RSTMGR_COUNTS_s
+{
+    uint32_t  warmrstcycles :  8;  /* Warm reset release delay count */
+    uint32_t  nrstcnt       : 20;  /* nRST Pin Count */
+    uint32_t                :  4;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_RSTMGR_COUNTS. */
+typedef volatile struct ALT_RSTMGR_COUNTS_s  ALT_RSTMGR_COUNTS_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_RSTMGR_COUNTS register from the beginning of the component. */
+#define ALT_RSTMGR_COUNTS_OFST        0x8
+
+/*
+ * Register : MPU Module Reset Register - mpumodrst
+ * 
+ * The MPUMODRST register is used by software to trigger module resets (individual
+ * module reset signals). Software explicitly asserts and de-asserts module reset
+ * signals by writing bits in the appropriate *MODRST register. It is up to
+ * software to ensure module reset signals are asserted for the appropriate length
+ * of time and are de-asserted in the correct order. It is also up to software to
+ * not assert a module reset signal that would prevent software from de-asserting
+ * the module reset signal. For example, software should not assert the module
+ * reset to the CPU executing the software.
+ * 
+ * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
+ * assert the module reset signal.
+ * 
+ * All fields except CPU1 are only reset by a cold reset. The CPU1 field is reset
+ * by a cold reset. The CPU1 field is also reset by a warm reset if not masked by
+ * the corresponding MPUWARMMASK field.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description    
+ * :-------|:-------|:------|:----------------
+ *  [0]    | RW     | 0x0   | CPU0           
+ *  [1]    | RW     | 0x1   | CPU1           
+ *  [2]    | RW     | 0x0   | Watchdogs      
+ *  [3]    | RW     | 0x0   | SCU/Peripherals
+ *  [4]    | RW     | 0x0   | L2             
+ *  [31:5] | ???    | 0x0   | *UNDEFINED*    
+ * 
+ */
+/*
+ * Field : CPU0 - cpu0
+ * 
+ * Resets Cortex-A9 CPU0 in MPU. Whe software changes this field from 0 to 1,
+ * ittriggers the following sequence:  1. CPU0 reset is asserted. cpu0 clkoff is
+ * de-asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is asserted.
+ * 
+ * When software changes this field from 1 to 0, it triggers the following
+ * sequence: 1.CPU0 reset is de-asserted. 2. after 32 cycles, cpu0 clkoff is de-
+ * asserted.
+ * 
+ * Software needs to wait for at least 64 osc1_clk cycles between each change of
+ * this field to keep the proper reset/clkoff sequence.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
+#define ALT_RSTMGR_MPUMODRST_CPU0_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
+#define ALT_RSTMGR_MPUMODRST_CPU0_MSB        0
+/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
+#define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */
+#define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK    0x00000001
+/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */
+#define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
+#define ALT_RSTMGR_MPUMODRST_CPU0_RESET      0x0
+/* Extracts the ALT_RSTMGR_MPUMODRST_CPU0 field value from a register. */
+#define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_RSTMGR_MPUMODRST_CPU0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : CPU1 - cpu1
+ * 
+ * Resets Cortex-A9 CPU1 in MPU.
+ * 
+ * It is reset to 1 on a cold or warm reset. This holds CPU1 in reset until
+ * software is ready to release CPU1 from reset by writing 0 to this field.
+ * 
+ * On single-core devices, writes to this field are ignored.On dual-core devices,
+ * writes to this field trigger the same sequence as writes to the CPU0 field
+ * (except the sequence is performed on CPU1).
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
+#define ALT_RSTMGR_MPUMODRST_CPU1_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
+#define ALT_RSTMGR_MPUMODRST_CPU1_MSB        1
+/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
+#define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */
+#define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK    0x00000002
+/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */
+#define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
+#define ALT_RSTMGR_MPUMODRST_CPU1_RESET      0x1
+/* Extracts the ALT_RSTMGR_MPUMODRST_CPU1 field value from a register. */
+#define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_RSTMGR_MPUMODRST_CPU1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : Watchdogs - wds
+ * 
+ * Resets both per-CPU Watchdog Reset Status registers in MPU.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */
+#define ALT_RSTMGR_MPUMODRST_WDS_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */
+#define ALT_RSTMGR_MPUMODRST_WDS_MSB        2
+/* The width in bits of the ALT_RSTMGR_MPUMODRST_WDS register field. */
+#define ALT_RSTMGR_MPUMODRST_WDS_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MPUMODRST_WDS register field value. */
+#define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK    0x00000004
+/* The mask used to clear the ALT_RSTMGR_MPUMODRST_WDS register field value. */
+#define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_RSTMGR_MPUMODRST_WDS register field. */
+#define ALT_RSTMGR_MPUMODRST_WDS_RESET      0x0
+/* Extracts the ALT_RSTMGR_MPUMODRST_WDS field value from a register. */
+#define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_RSTMGR_MPUMODRST_WDS register field value suitable for setting the register. */
+#define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : SCU/Peripherals - scuper
+ * 
+ * Resets SCU and peripherals. Peripherals consist of the interrupt controller,
+ * global timer, both per-CPU private timers, and both per-CPU watchdogs (except
+ * for the Watchdog Reset Status registers).
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
+#define ALT_RSTMGR_MPUMODRST_SCUPER_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
+#define ALT_RSTMGR_MPUMODRST_SCUPER_MSB        3
+/* The width in bits of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
+#define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */
+#define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK    0x00000008
+/* The mask used to clear the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */
+#define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
+#define ALT_RSTMGR_MPUMODRST_SCUPER_RESET      0x0
+/* Extracts the ALT_RSTMGR_MPUMODRST_SCUPER field value from a register. */
+#define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_RSTMGR_MPUMODRST_SCUPER register field value suitable for setting the register. */
+#define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : L2 - l2
+ * 
+ * Resets L2 cache controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */
+#define ALT_RSTMGR_MPUMODRST_L2_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */
+#define ALT_RSTMGR_MPUMODRST_L2_MSB        4
+/* The width in bits of the ALT_RSTMGR_MPUMODRST_L2 register field. */
+#define ALT_RSTMGR_MPUMODRST_L2_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MPUMODRST_L2 register field value. */
+#define ALT_RSTMGR_MPUMODRST_L2_SET_MSK    0x00000010
+/* The mask used to clear the ALT_RSTMGR_MPUMODRST_L2 register field value. */
+#define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK    0xffffffef
+/* The reset value of the ALT_RSTMGR_MPUMODRST_L2 register field. */
+#define ALT_RSTMGR_MPUMODRST_L2_RESET      0x0
+/* Extracts the ALT_RSTMGR_MPUMODRST_L2 field value from a register. */
+#define ALT_RSTMGR_MPUMODRST_L2_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_RSTMGR_MPUMODRST_L2 register field value suitable for setting the register. */
+#define ALT_RSTMGR_MPUMODRST_L2_SET(value) (((value) << 4) & 0x00000010)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_RSTMGR_MPUMODRST.
+ */
+struct ALT_RSTMGR_MPUMODRST_s
+{
+    uint32_t  cpu0   :  1;  /* CPU0 */
+    uint32_t  cpu1   :  1;  /* CPU1 */
+    uint32_t  wds    :  1;  /* Watchdogs */
+    uint32_t  scuper :  1;  /* SCU/Peripherals */
+    uint32_t  l2     :  1;  /* L2 */
+    uint32_t         : 27;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_RSTMGR_MPUMODRST. */
+typedef volatile struct ALT_RSTMGR_MPUMODRST_s  ALT_RSTMGR_MPUMODRST_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_RSTMGR_MPUMODRST register from the beginning of the component. */
+#define ALT_RSTMGR_MPUMODRST_OFST        0x10
+
+/*
+ * Register : Peripheral Module Reset Register - permodrst
+ * 
+ * The PERMODRST register is used by software to trigger module resets (individual
+ * module reset signals). Software explicitly asserts and de-asserts module reset
+ * signals by writing bits in the appropriate *MODRST register. It is up to
+ * software to ensure module reset signals are asserted for the appropriate length
+ * of time and are de-asserted in the correct order. It is also up to software to
+ * not assert a module reset signal that would prevent software from de-asserting
+ * the module reset signal. For example, software should not assert the module
+ * reset to the CPU executing the software.
+ * 
+ * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
+ * assert the module reset signal.
+ * 
+ * All fields are reset by a cold reset.All fields are also reset by a warm reset
+ * if not masked by the corresponding PERWARMMASK field.
+ * 
+ * The reset value of all fields is 1. This holds the corresponding module in reset
+ * until software is ready to release the module from reset by writing 0 to its
+ * field.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description               
+ * :--------|:-------|:------|:---------------------------
+ *  [0]     | RW     | 0x1   | EMAC0                     
+ *  [1]     | RW     | 0x1   | EMAC1                     
+ *  [2]     | RW     | 0x1   | USB0                      
+ *  [3]     | RW     | 0x1   | USB1                      
+ *  [4]     | RW     | 0x1   | NAND Flash                
+ *  [5]     | RW     | 0x1   | QSPI Flash                
+ *  [6]     | RW     | 0x1   | L4 Watchdog 0             
+ *  [7]     | RW     | 0x1   | L4 Watchdog 1             
+ *  [8]     | RW     | 0x1   | OSC1 Timer 0              
+ *  [9]     | RW     | 0x1   | OSC1 Timer 1              
+ *  [10]    | RW     | 0x1   | SP Timer 0                
+ *  [11]    | RW     | 0x1   | SP Timer 1                
+ *  [12]    | RW     | 0x1   | I2C0                      
+ *  [13]    | RW     | 0x1   | I2C1                      
+ *  [14]    | RW     | 0x1   | I2C2                      
+ *  [15]    | RW     | 0x1   | I2C3                      
+ *  [16]    | RW     | 0x1   | UART0                     
+ *  [17]    | RW     | 0x1   | UART1                     
+ *  [18]    | RW     | 0x1   | SPIM0                     
+ *  [19]    | RW     | 0x1   | SPIM1                     
+ *  [20]    | RW     | 0x1   | SPIS0                     
+ *  [21]    | RW     | 0x1   | SPIS1                     
+ *  [22]    | RW     | 0x1   | SD/MMC                    
+ *  [23]    | RW     | 0x1   | CAN0                      
+ *  [24]    | RW     | 0x1   | CAN1                      
+ *  [25]    | RW     | 0x1   | GPIO0                     
+ *  [26]    | RW     | 0x1   | GPIO1                     
+ *  [27]    | RW     | 0x1   | GPIO2                     
+ *  [28]    | RW     | 0x1   | DMA Controller            
+ *  [29]    | RW     | 0x1   | SDRAM Controller Subsystem
+ *  [31:30] | ???    | 0x0   | *UNDEFINED*               
+ * 
+ */
+/*
+ * Field : EMAC0 - emac0
+ * 
+ * Resets EMAC0
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
+#define ALT_RSTMGR_PERMODRST_EMAC0_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
+#define ALT_RSTMGR_PERMODRST_EMAC0_MSB        0
+/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
+#define ALT_RSTMGR_PERMODRST_EMAC0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */
+#define ALT_RSTMGR_PERMODRST_EMAC0_SET_MSK    0x00000001
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */
+#define ALT_RSTMGR_PERMODRST_EMAC0_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
+#define ALT_RSTMGR_PERMODRST_EMAC0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_EMAC0 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_RSTMGR_PERMODRST_EMAC0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : EMAC1 - emac1
+ * 
+ * Resets EMAC1
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
+#define ALT_RSTMGR_PERMODRST_EMAC1_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
+#define ALT_RSTMGR_PERMODRST_EMAC1_MSB        1
+/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
+#define ALT_RSTMGR_PERMODRST_EMAC1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */
+#define ALT_RSTMGR_PERMODRST_EMAC1_SET_MSK    0x00000002
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */
+#define ALT_RSTMGR_PERMODRST_EMAC1_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
+#define ALT_RSTMGR_PERMODRST_EMAC1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_EMAC1 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_RSTMGR_PERMODRST_EMAC1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : USB0 - usb0
+ * 
+ * Resets USB0
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */
+#define ALT_RSTMGR_PERMODRST_USB0_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */
+#define ALT_RSTMGR_PERMODRST_USB0_MSB        2
+/* The width in bits of the ALT_RSTMGR_PERMODRST_USB0 register field. */
+#define ALT_RSTMGR_PERMODRST_USB0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_USB0 register field value. */
+#define ALT_RSTMGR_PERMODRST_USB0_SET_MSK    0x00000004
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB0 register field value. */
+#define ALT_RSTMGR_PERMODRST_USB0_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_RSTMGR_PERMODRST_USB0 register field. */
+#define ALT_RSTMGR_PERMODRST_USB0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_USB0 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_USB0_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_RSTMGR_PERMODRST_USB0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_USB0_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : USB1 - usb1
+ * 
+ * Resets USB1
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */
+#define ALT_RSTMGR_PERMODRST_USB1_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */
+#define ALT_RSTMGR_PERMODRST_USB1_MSB        3
+/* The width in bits of the ALT_RSTMGR_PERMODRST_USB1 register field. */
+#define ALT_RSTMGR_PERMODRST_USB1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_USB1 register field value. */
+#define ALT_RSTMGR_PERMODRST_USB1_SET_MSK    0x00000008
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB1 register field value. */
+#define ALT_RSTMGR_PERMODRST_USB1_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_RSTMGR_PERMODRST_USB1 register field. */
+#define ALT_RSTMGR_PERMODRST_USB1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_USB1 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_USB1_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_RSTMGR_PERMODRST_USB1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_USB1_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : NAND Flash - nand
+ * 
+ * Resets NAND flash controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */
+#define ALT_RSTMGR_PERMODRST_NAND_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */
+#define ALT_RSTMGR_PERMODRST_NAND_MSB        4
+/* The width in bits of the ALT_RSTMGR_PERMODRST_NAND register field. */
+#define ALT_RSTMGR_PERMODRST_NAND_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_NAND register field value. */
+#define ALT_RSTMGR_PERMODRST_NAND_SET_MSK    0x00000010
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_NAND register field value. */
+#define ALT_RSTMGR_PERMODRST_NAND_CLR_MSK    0xffffffef
+/* The reset value of the ALT_RSTMGR_PERMODRST_NAND register field. */
+#define ALT_RSTMGR_PERMODRST_NAND_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_NAND field value from a register. */
+#define ALT_RSTMGR_PERMODRST_NAND_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_RSTMGR_PERMODRST_NAND register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_NAND_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : QSPI Flash - qspi
+ * 
+ * Resets QSPI flash controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */
+#define ALT_RSTMGR_PERMODRST_QSPI_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */
+#define ALT_RSTMGR_PERMODRST_QSPI_MSB        5
+/* The width in bits of the ALT_RSTMGR_PERMODRST_QSPI register field. */
+#define ALT_RSTMGR_PERMODRST_QSPI_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_QSPI register field value. */
+#define ALT_RSTMGR_PERMODRST_QSPI_SET_MSK    0x00000020
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_QSPI register field value. */
+#define ALT_RSTMGR_PERMODRST_QSPI_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_RSTMGR_PERMODRST_QSPI register field. */
+#define ALT_RSTMGR_PERMODRST_QSPI_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_QSPI field value from a register. */
+#define ALT_RSTMGR_PERMODRST_QSPI_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_RSTMGR_PERMODRST_QSPI register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_QSPI_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : L4 Watchdog 0 - l4wd0
+ * 
+ * Resets watchdog 0 connected to L4
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
+#define ALT_RSTMGR_PERMODRST_L4WD0_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
+#define ALT_RSTMGR_PERMODRST_L4WD0_MSB        6
+/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
+#define ALT_RSTMGR_PERMODRST_L4WD0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */
+#define ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK    0x00000040
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */
+#define ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
+#define ALT_RSTMGR_PERMODRST_L4WD0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_L4WD0 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_L4WD0_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_RSTMGR_PERMODRST_L4WD0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_L4WD0_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : L4 Watchdog 1 - l4wd1
+ * 
+ * Resets watchdog 1 connected to L4
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
+#define ALT_RSTMGR_PERMODRST_L4WD1_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
+#define ALT_RSTMGR_PERMODRST_L4WD1_MSB        7
+/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
+#define ALT_RSTMGR_PERMODRST_L4WD1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */
+#define ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK    0x00000080
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */
+#define ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
+#define ALT_RSTMGR_PERMODRST_L4WD1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_L4WD1 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_L4WD1_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_RSTMGR_PERMODRST_L4WD1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_L4WD1_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : OSC1 Timer 0 - osc1timer0
+ * 
+ * Resets OSC1 timer 0 connected to L4
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR0_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR0_MSB        8
+/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK    0x00000100
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR0_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR0 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR0_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : OSC1 Timer 1 - osc1timer1
+ * 
+ * Resets OSC1 timer 1 connected to L4
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR1_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR1_MSB        9
+/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK    0x00000200
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR1_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR1 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR1_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET(value) (((value) << 9) & 0x00000200)
+
+/*
+ * Field : SP Timer 0 - sptimer0
+ * 
+ * Resets SP timer 0 connected to L4
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPTMR0_LSB        10
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPTMR0_MSB        10
+/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPTMR0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK    0x00000400
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPTMR0_CLR_MSK    0xfffffbff
+/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPTMR0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR0 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_SPTMR0_GET(value) (((value) & 0x00000400) >> 10)
+/* Produces a ALT_RSTMGR_PERMODRST_SPTMR0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_SPTMR0_SET(value) (((value) << 10) & 0x00000400)
+
+/*
+ * Field : SP Timer 1 - sptimer1
+ * 
+ * Resets SP timer 1 connected to L4
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPTMR1_LSB        11
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPTMR1_MSB        11
+/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPTMR1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK    0x00000800
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPTMR1_CLR_MSK    0xfffff7ff
+/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPTMR1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR1 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_SPTMR1_GET(value) (((value) & 0x00000800) >> 11)
+/* Produces a ALT_RSTMGR_PERMODRST_SPTMR1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_SPTMR1_SET(value) (((value) << 11) & 0x00000800)
+
+/*
+ * Field : I2C0 - i2c0
+ * 
+ * Resets I2C0 controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C0_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C0_MSB        12
+/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C0 register field value. */
+#define ALT_RSTMGR_PERMODRST_I2C0_SET_MSK    0x00001000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C0 register field value. */
+#define ALT_RSTMGR_PERMODRST_I2C0_CLR_MSK    0xffffefff
+/* The reset value of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_I2C0 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_I2C0_GET(value) (((value) & 0x00001000) >> 12)
+/* Produces a ALT_RSTMGR_PERMODRST_I2C0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_I2C0_SET(value) (((value) << 12) & 0x00001000)
+
+/*
+ * Field : I2C1 - i2c1
+ * 
+ * Resets I2C1 controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C1_LSB        13
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C1_MSB        13
+/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C1 register field value. */
+#define ALT_RSTMGR_PERMODRST_I2C1_SET_MSK    0x00002000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C1 register field value. */
+#define ALT_RSTMGR_PERMODRST_I2C1_CLR_MSK    0xffffdfff
+/* The reset value of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_I2C1 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_I2C1_GET(value) (((value) & 0x00002000) >> 13)
+/* Produces a ALT_RSTMGR_PERMODRST_I2C1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_I2C1_SET(value) (((value) << 13) & 0x00002000)
+
+/*
+ * Field : I2C2 - i2c2
+ * 
+ * Resets I2C2 controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C2_LSB        14
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C2_MSB        14
+/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C2_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C2 register field value. */
+#define ALT_RSTMGR_PERMODRST_I2C2_SET_MSK    0x00004000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C2 register field value. */
+#define ALT_RSTMGR_PERMODRST_I2C2_CLR_MSK    0xffffbfff
+/* The reset value of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C2_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_I2C2 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_I2C2_GET(value) (((value) & 0x00004000) >> 14)
+/* Produces a ALT_RSTMGR_PERMODRST_I2C2 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_I2C2_SET(value) (((value) << 14) & 0x00004000)
+
+/*
+ * Field : I2C3 - i2c3
+ * 
+ * Resets I2C3 controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C3_LSB        15
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C3_MSB        15
+/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C3_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C3 register field value. */
+#define ALT_RSTMGR_PERMODRST_I2C3_SET_MSK    0x00008000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C3 register field value. */
+#define ALT_RSTMGR_PERMODRST_I2C3_CLR_MSK    0xffff7fff
+/* The reset value of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
+#define ALT_RSTMGR_PERMODRST_I2C3_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_I2C3 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_I2C3_GET(value) (((value) & 0x00008000) >> 15)
+/* Produces a ALT_RSTMGR_PERMODRST_I2C3 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_I2C3_SET(value) (((value) << 15) & 0x00008000)
+
+/*
+ * Field : UART0 - uart0
+ * 
+ * Resets UART0
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */
+#define ALT_RSTMGR_PERMODRST_UART0_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */
+#define ALT_RSTMGR_PERMODRST_UART0_MSB        16
+/* The width in bits of the ALT_RSTMGR_PERMODRST_UART0 register field. */
+#define ALT_RSTMGR_PERMODRST_UART0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_UART0 register field value. */
+#define ALT_RSTMGR_PERMODRST_UART0_SET_MSK    0x00010000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART0 register field value. */
+#define ALT_RSTMGR_PERMODRST_UART0_CLR_MSK    0xfffeffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_UART0 register field. */
+#define ALT_RSTMGR_PERMODRST_UART0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_UART0 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
+/* Produces a ALT_RSTMGR_PERMODRST_UART0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
+
+/*
+ * Field : UART1 - uart1
+ * 
+ * Resets UART1
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */
+#define ALT_RSTMGR_PERMODRST_UART1_LSB        17
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */
+#define ALT_RSTMGR_PERMODRST_UART1_MSB        17
+/* The width in bits of the ALT_RSTMGR_PERMODRST_UART1 register field. */
+#define ALT_RSTMGR_PERMODRST_UART1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_UART1 register field value. */
+#define ALT_RSTMGR_PERMODRST_UART1_SET_MSK    0x00020000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART1 register field value. */
+#define ALT_RSTMGR_PERMODRST_UART1_CLR_MSK    0xfffdffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_UART1 register field. */
+#define ALT_RSTMGR_PERMODRST_UART1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_UART1 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
+/* Produces a ALT_RSTMGR_PERMODRST_UART1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
+
+/*
+ * Field : SPIM0 - spim0
+ * 
+ * Resets SPIM0 controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIM0_LSB        18
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIM0_MSB        18
+/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIM0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK    0x00040000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPIM0_CLR_MSK    0xfffbffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIM0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_SPIM0 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_SPIM0_GET(value) (((value) & 0x00040000) >> 18)
+/* Produces a ALT_RSTMGR_PERMODRST_SPIM0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_SPIM0_SET(value) (((value) << 18) & 0x00040000)
+
+/*
+ * Field : SPIM1 - spim1
+ * 
+ * Resets SPIM1 controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIM1_LSB        19
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIM1_MSB        19
+/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIM1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK    0x00080000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPIM1_CLR_MSK    0xfff7ffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIM1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_SPIM1 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_SPIM1_GET(value) (((value) & 0x00080000) >> 19)
+/* Produces a ALT_RSTMGR_PERMODRST_SPIM1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_SPIM1_SET(value) (((value) << 19) & 0x00080000)
+
+/*
+ * Field : SPIS0 - spis0
+ * 
+ * Resets SPIS0 controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIS0_LSB        20
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIS0_MSB        20
+/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIS0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK    0x00100000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPIS0_CLR_MSK    0xffefffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIS0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_SPIS0 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_SPIS0_GET(value) (((value) & 0x00100000) >> 20)
+/* Produces a ALT_RSTMGR_PERMODRST_SPIS0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_SPIS0_SET(value) (((value) << 20) & 0x00100000)
+
+/*
+ * Field : SPIS1 - spis1
+ * 
+ * Resets SPIS1 controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIS1_LSB        21
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIS1_MSB        21
+/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIS1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK    0x00200000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */
+#define ALT_RSTMGR_PERMODRST_SPIS1_CLR_MSK    0xffdfffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
+#define ALT_RSTMGR_PERMODRST_SPIS1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_SPIS1 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_SPIS1_GET(value) (((value) & 0x00200000) >> 21)
+/* Produces a ALT_RSTMGR_PERMODRST_SPIS1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_SPIS1_SET(value) (((value) << 21) & 0x00200000)
+
+/*
+ * Field : SD/MMC - sdmmc
+ * 
+ * Resets SD/MMC controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
+#define ALT_RSTMGR_PERMODRST_SDMMC_LSB        22
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
+#define ALT_RSTMGR_PERMODRST_SDMMC_MSB        22
+/* The width in bits of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
+#define ALT_RSTMGR_PERMODRST_SDMMC_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_SDMMC register field value. */
+#define ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK    0x00400000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDMMC register field value. */
+#define ALT_RSTMGR_PERMODRST_SDMMC_CLR_MSK    0xffbfffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
+#define ALT_RSTMGR_PERMODRST_SDMMC_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_SDMMC field value from a register. */
+#define ALT_RSTMGR_PERMODRST_SDMMC_GET(value) (((value) & 0x00400000) >> 22)
+/* Produces a ALT_RSTMGR_PERMODRST_SDMMC register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_SDMMC_SET(value) (((value) << 22) & 0x00400000)
+
+/*
+ * Field : CAN0 - can0
+ * 
+ * Resets CAN0 controller.
+ * 
+ * Writes to this field on devices not containing CAN controllers will be ignored.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
+#define ALT_RSTMGR_PERMODRST_CAN0_LSB        23
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
+#define ALT_RSTMGR_PERMODRST_CAN0_MSB        23
+/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
+#define ALT_RSTMGR_PERMODRST_CAN0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN0 register field value. */
+#define ALT_RSTMGR_PERMODRST_CAN0_SET_MSK    0x00800000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN0 register field value. */
+#define ALT_RSTMGR_PERMODRST_CAN0_CLR_MSK    0xff7fffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
+#define ALT_RSTMGR_PERMODRST_CAN0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_CAN0 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_CAN0_GET(value) (((value) & 0x00800000) >> 23)
+/* Produces a ALT_RSTMGR_PERMODRST_CAN0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_CAN0_SET(value) (((value) << 23) & 0x00800000)
+
+/*
+ * Field : CAN1 - can1
+ * 
+ * Resets CAN1 controller.
+ * 
+ * Writes to this field on devices not containing CAN controllers will be ignored.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
+#define ALT_RSTMGR_PERMODRST_CAN1_LSB        24
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
+#define ALT_RSTMGR_PERMODRST_CAN1_MSB        24
+/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
+#define ALT_RSTMGR_PERMODRST_CAN1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN1 register field value. */
+#define ALT_RSTMGR_PERMODRST_CAN1_SET_MSK    0x01000000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN1 register field value. */
+#define ALT_RSTMGR_PERMODRST_CAN1_CLR_MSK    0xfeffffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
+#define ALT_RSTMGR_PERMODRST_CAN1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_CAN1 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_CAN1_GET(value) (((value) & 0x01000000) >> 24)
+/* Produces a ALT_RSTMGR_PERMODRST_CAN1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_CAN1_SET(value) (((value) << 24) & 0x01000000)
+
+/*
+ * Field : GPIO0 - gpio0
+ * 
+ * Resets GPIO0
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO0_LSB        25
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO0_MSB        25
+/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */
+#define ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK    0x02000000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */
+#define ALT_RSTMGR_PERMODRST_GPIO0_CLR_MSK    0xfdffffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_GPIO0 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_GPIO0_GET(value) (((value) & 0x02000000) >> 25)
+/* Produces a ALT_RSTMGR_PERMODRST_GPIO0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_GPIO0_SET(value) (((value) << 25) & 0x02000000)
+
+/*
+ * Field : GPIO1 - gpio1
+ * 
+ * Resets GPIO1
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO1_LSB        26
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO1_MSB        26
+/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */
+#define ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK    0x04000000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */
+#define ALT_RSTMGR_PERMODRST_GPIO1_CLR_MSK    0xfbffffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_GPIO1 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_GPIO1_GET(value) (((value) & 0x04000000) >> 26)
+/* Produces a ALT_RSTMGR_PERMODRST_GPIO1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_GPIO1_SET(value) (((value) << 26) & 0x04000000)
+
+/*
+ * Field : GPIO2 - gpio2
+ * 
+ * Resets GPIO2
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO2_LSB        27
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO2_MSB        27
+/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO2_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */
+#define ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK    0x08000000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */
+#define ALT_RSTMGR_PERMODRST_GPIO2_CLR_MSK    0xf7ffffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
+#define ALT_RSTMGR_PERMODRST_GPIO2_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_GPIO2 field value from a register. */
+#define ALT_RSTMGR_PERMODRST_GPIO2_GET(value) (((value) & 0x08000000) >> 27)
+/* Produces a ALT_RSTMGR_PERMODRST_GPIO2 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_GPIO2_SET(value) (((value) << 27) & 0x08000000)
+
+/*
+ * Field : DMA Controller - dma
+ * 
+ * Resets DMA controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */
+#define ALT_RSTMGR_PERMODRST_DMA_LSB        28
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */
+#define ALT_RSTMGR_PERMODRST_DMA_MSB        28
+/* The width in bits of the ALT_RSTMGR_PERMODRST_DMA register field. */
+#define ALT_RSTMGR_PERMODRST_DMA_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_DMA register field value. */
+#define ALT_RSTMGR_PERMODRST_DMA_SET_MSK    0x10000000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_DMA register field value. */
+#define ALT_RSTMGR_PERMODRST_DMA_CLR_MSK    0xefffffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_DMA register field. */
+#define ALT_RSTMGR_PERMODRST_DMA_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_DMA field value from a register. */
+#define ALT_RSTMGR_PERMODRST_DMA_GET(value) (((value) & 0x10000000) >> 28)
+/* Produces a ALT_RSTMGR_PERMODRST_DMA register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_DMA_SET(value) (((value) << 28) & 0x10000000)
+
+/*
+ * Field : SDRAM Controller Subsystem - sdr
+ * 
+ * Resets SDRAM Controller Subsystem affected by a warm or cold reset.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */
+#define ALT_RSTMGR_PERMODRST_SDR_LSB        29
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */
+#define ALT_RSTMGR_PERMODRST_SDR_MSB        29
+/* The width in bits of the ALT_RSTMGR_PERMODRST_SDR register field. */
+#define ALT_RSTMGR_PERMODRST_SDR_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PERMODRST_SDR register field value. */
+#define ALT_RSTMGR_PERMODRST_SDR_SET_MSK    0x20000000
+/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDR register field value. */
+#define ALT_RSTMGR_PERMODRST_SDR_CLR_MSK    0xdfffffff
+/* The reset value of the ALT_RSTMGR_PERMODRST_SDR register field. */
+#define ALT_RSTMGR_PERMODRST_SDR_RESET      0x1
+/* Extracts the ALT_RSTMGR_PERMODRST_SDR field value from a register. */
+#define ALT_RSTMGR_PERMODRST_SDR_GET(value) (((value) & 0x20000000) >> 29)
+/* Produces a ALT_RSTMGR_PERMODRST_SDR register field value suitable for setting the register. */
+#define ALT_RSTMGR_PERMODRST_SDR_SET(value) (((value) << 29) & 0x20000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_RSTMGR_PERMODRST.
+ */
+struct ALT_RSTMGR_PERMODRST_s
+{
+    uint32_t  emac0      :  1;  /* EMAC0 */
+    uint32_t  emac1      :  1;  /* EMAC1 */
+    uint32_t  usb0       :  1;  /* USB0 */
+    uint32_t  usb1       :  1;  /* USB1 */
+    uint32_t  nand       :  1;  /* NAND Flash */
+    uint32_t  qspi       :  1;  /* QSPI Flash */
+    uint32_t  l4wd0      :  1;  /* L4 Watchdog 0 */
+    uint32_t  l4wd1      :  1;  /* L4 Watchdog 1 */
+    uint32_t  osc1timer0 :  1;  /* OSC1 Timer 0 */
+    uint32_t  osc1timer1 :  1;  /* OSC1 Timer 1 */
+    uint32_t  sptimer0   :  1;  /* SP Timer 0 */
+    uint32_t  sptimer1   :  1;  /* SP Timer 1 */
+    uint32_t  i2c0       :  1;  /* I2C0 */
+    uint32_t  i2c1       :  1;  /* I2C1 */
+    uint32_t  i2c2       :  1;  /* I2C2 */
+    uint32_t  i2c3       :  1;  /* I2C3 */
+    uint32_t  uart0      :  1;  /* UART0 */
+    uint32_t  uart1      :  1;  /* UART1 */
+    uint32_t  spim0      :  1;  /* SPIM0 */
+    uint32_t  spim1      :  1;  /* SPIM1 */
+    uint32_t  spis0      :  1;  /* SPIS0 */
+    uint32_t  spis1      :  1;  /* SPIS1 */
+    uint32_t  sdmmc      :  1;  /* SD/MMC */
+    uint32_t  can0       :  1;  /* CAN0 */
+    uint32_t  can1       :  1;  /* CAN1 */
+    uint32_t  gpio0      :  1;  /* GPIO0 */
+    uint32_t  gpio1      :  1;  /* GPIO1 */
+    uint32_t  gpio2      :  1;  /* GPIO2 */
+    uint32_t  dma        :  1;  /* DMA Controller */
+    uint32_t  sdr        :  1;  /* SDRAM Controller Subsystem */
+    uint32_t             :  2;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_RSTMGR_PERMODRST. */
+typedef volatile struct ALT_RSTMGR_PERMODRST_s  ALT_RSTMGR_PERMODRST_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_RSTMGR_PERMODRST register from the beginning of the component. */
+#define ALT_RSTMGR_PERMODRST_OFST        0x14
+
+/*
+ * Register : Peripheral 2 Module Reset Register - per2modrst
+ * 
+ * The PER2MODRST register is used by software to trigger module resets (individual
+ * module reset signals). Software explicitly asserts and de-asserts module reset
+ * signals by writing bits in the appropriate *MODRST register. It is up to
+ * software to ensure module reset signals are asserted for the appropriate length
+ * of time and are de-asserted in the correct order. It is also up to software to
+ * not assert a module reset signal that would prevent software from de-asserting
+ * the module reset signal. For example, software should not assert the module
+ * reset to the CPU executing the software.
+ * 
+ * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
+ * assert the module reset signal.
+ * 
+ * All fields are reset by a cold reset.All fields are also reset by a warm reset
+ * if not masked by the corresponding PERWARMMASK field.
+ * 
+ * The reset value of all fields is 1. This holds the corresponding module in reset
+ * until software is ready to release the module from reset by writing 0 to its
+ * field.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [0]    | RW     | 0x1   | FPGA DMA0  
+ *  [1]    | RW     | 0x1   | FPGA DMA1  
+ *  [2]    | RW     | 0x1   | FPGA DMA2  
+ *  [3]    | RW     | 0x1   | FPGA DMA3  
+ *  [4]    | RW     | 0x1   | FPGA DMA4  
+ *  [5]    | RW     | 0x1   | FPGA DMA5  
+ *  [6]    | RW     | 0x1   | FPGA DMA6  
+ *  [7]    | RW     | 0x1   | FPGA DMA7  
+ *  [31:8] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : FPGA DMA0 - dmaif0
+ * 
+ * Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA
+ * Controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF0_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF0_MSB        0
+/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF0_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET_MSK    0x00000001
+/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF0_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF0_RESET      0x1
+/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF0 field value from a register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF0_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF0 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : FPGA DMA1 - dmaif1
+ * 
+ * Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA
+ * Controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF1_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF1_MSB        1
+/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF1_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET_MSK    0x00000002
+/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF1_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF1_RESET      0x1
+/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF1 field value from a register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF1_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF1 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : FPGA DMA2 - dmaif2
+ * 
+ * Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA
+ * Controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF2_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF2_MSB        2
+/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF2_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET_MSK    0x00000004
+/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF2_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF2_RESET      0x1
+/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF2 field value from a register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF2_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF2 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : FPGA DMA3 - dmaif3
+ * 
+ * Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA
+ * Controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF3_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF3_MSB        3
+/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF3_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET_MSK    0x00000008
+/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF3_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF3_RESET      0x1
+/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF3 field value from a register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF3_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF3 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : FPGA DMA4 - dmaif4
+ * 
+ * Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA
+ * Controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF4_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF4_MSB        4
+/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF4_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET_MSK    0x00000010
+/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF4_CLR_MSK    0xffffffef
+/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF4_RESET      0x1
+/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF4 field value from a register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF4_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF4 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : FPGA DMA5 - dmaif5
+ * 
+ * Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA
+ * Controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF5_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF5_MSB        5
+/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF5_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET_MSK    0x00000020
+/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF5_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF5_RESET      0x1
+/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF5 field value from a register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF5_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF5 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : FPGA DMA6 - dmaif6
+ * 
+ * Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA
+ * Controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF6_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF6_MSB        6
+/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF6_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET_MSK    0x00000040
+/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF6_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF6_RESET      0x1
+/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF6 field value from a register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF6_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF6 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : FPGA DMA7 - dmaif7
+ * 
+ * Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA
+ * Controller
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF7_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF7_MSB        7
+/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF7_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET_MSK    0x00000080
+/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF7_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF7_RESET      0x1
+/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF7 field value from a register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF7_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF7 register field value suitable for setting the register. */
+#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET(value) (((value) << 7) & 0x00000080)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_RSTMGR_PER2MODRST.
+ */
+struct ALT_RSTMGR_PER2MODRST_s
+{
+    uint32_t  dmaif0 :  1;  /* FPGA DMA0 */
+    uint32_t  dmaif1 :  1;  /* FPGA DMA1 */
+    uint32_t  dmaif2 :  1;  /* FPGA DMA2 */
+    uint32_t  dmaif3 :  1;  /* FPGA DMA3 */
+    uint32_t  dmaif4 :  1;  /* FPGA DMA4 */
+    uint32_t  dmaif5 :  1;  /* FPGA DMA5 */
+    uint32_t  dmaif6 :  1;  /* FPGA DMA6 */
+    uint32_t  dmaif7 :  1;  /* FPGA DMA7 */
+    uint32_t         : 24;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_RSTMGR_PER2MODRST. */
+typedef volatile struct ALT_RSTMGR_PER2MODRST_s  ALT_RSTMGR_PER2MODRST_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_RSTMGR_PER2MODRST register from the beginning of the component. */
+#define ALT_RSTMGR_PER2MODRST_OFST        0x18
+
+/*
+ * Register : Bridge Module Reset Register - brgmodrst
+ * 
+ * The BRGMODRST register is used by software to trigger module resets (individual
+ * module reset signals). Software explicitly asserts and de-asserts module reset
+ * signals by writing bits in the appropriate *MODRST register. It is up to
+ * software to ensure module reset signals are asserted for the appropriate length
+ * of time and are de-asserted in the correct order. It is also up to software to
+ * not assert a module reset signal that would prevent software from de-asserting
+ * the module reset signal. For example, software should not assert the module
+ * reset to the CPU executing the software.
+ * 
+ * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
+ * assert the module reset signal.
+ * 
+ * All fields are reset by a cold reset.All fields are also reset by a warm reset
+ * if not masked by the corresponding BRGWARMMASK field.
+ * 
+ * The reset value of all fields is 1. This holds the corresponding module in reset
+ * until software is ready to release the module from reset by writing 0 to its
+ * field.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description      
+ * :-------|:-------|:------|:------------------
+ *  [0]    | RW     | 0x1   | HPS2FPGA Bridge  
+ *  [1]    | RW     | 0x1   | LWHPS2FPGA Bridge
+ *  [2]    | RW     | 0x1   | FPGA2HPS Bridge  
+ *  [31:3] | ???    | 0x0   | *UNDEFINED*      
+ * 
+ */
+/*
+ * Field : HPS2FPGA Bridge - hps2fpga
+ * 
+ * Resets HPS2FPGA Bridge
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */
+#define ALT_RSTMGR_BRGMODRST_H2F_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */
+#define ALT_RSTMGR_BRGMODRST_H2F_MSB        0
+/* The width in bits of the ALT_RSTMGR_BRGMODRST_H2F register field. */
+#define ALT_RSTMGR_BRGMODRST_H2F_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_BRGMODRST_H2F register field value. */
+#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK    0x00000001
+/* The mask used to clear the ALT_RSTMGR_BRGMODRST_H2F register field value. */
+#define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_RSTMGR_BRGMODRST_H2F register field. */
+#define ALT_RSTMGR_BRGMODRST_H2F_RESET      0x1
+/* Extracts the ALT_RSTMGR_BRGMODRST_H2F field value from a register. */
+#define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_RSTMGR_BRGMODRST_H2F register field value suitable for setting the register. */
+#define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : LWHPS2FPGA Bridge - lwhps2fpga
+ * 
+ * Resets LWHPS2FPGA Bridge
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
+#define ALT_RSTMGR_BRGMODRST_LWH2F_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
+#define ALT_RSTMGR_BRGMODRST_LWH2F_MSB        1
+/* The width in bits of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
+#define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */
+#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK    0x00000002
+/* The mask used to clear the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */
+#define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
+#define ALT_RSTMGR_BRGMODRST_LWH2F_RESET      0x1
+/* Extracts the ALT_RSTMGR_BRGMODRST_LWH2F field value from a register. */
+#define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_RSTMGR_BRGMODRST_LWH2F register field value suitable for setting the register. */
+#define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : FPGA2HPS Bridge - fpga2hps
+ * 
+ * Resets FPGA2HPS Bridge
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */
+#define ALT_RSTMGR_BRGMODRST_F2H_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */
+#define ALT_RSTMGR_BRGMODRST_F2H_MSB        2
+/* The width in bits of the ALT_RSTMGR_BRGMODRST_F2H register field. */
+#define ALT_RSTMGR_BRGMODRST_F2H_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_BRGMODRST_F2H register field value. */
+#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK    0x00000004
+/* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2H register field value. */
+#define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_RSTMGR_BRGMODRST_F2H register field. */
+#define ALT_RSTMGR_BRGMODRST_F2H_RESET      0x1
+/* Extracts the ALT_RSTMGR_BRGMODRST_F2H field value from a register. */
+#define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_RSTMGR_BRGMODRST_F2H register field value suitable for setting the register. */
+#define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_RSTMGR_BRGMODRST.
+ */
+struct ALT_RSTMGR_BRGMODRST_s
+{
+    uint32_t  hps2fpga   :  1;  /* HPS2FPGA Bridge */
+    uint32_t  lwhps2fpga :  1;  /* LWHPS2FPGA Bridge */
+    uint32_t  fpga2hps   :  1;  /* FPGA2HPS Bridge */
+    uint32_t             : 29;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_RSTMGR_BRGMODRST. */
+typedef volatile struct ALT_RSTMGR_BRGMODRST_s  ALT_RSTMGR_BRGMODRST_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_RSTMGR_BRGMODRST register from the beginning of the component. */
+#define ALT_RSTMGR_BRGMODRST_OFST        0x1c
+
+/*
+ * Register : Miscellaneous Module Reset Register - miscmodrst
+ * 
+ * The MISCMODRST register is used by software to trigger module resets (individual
+ * module reset signals). Software explicitly asserts and de-asserts module reset
+ * signals by writing bits in the appropriate *MODRST register. It is up to
+ * software to ensure module reset signals are asserted for the appropriate length
+ * of time and are de-asserted in the correct order. It is also up to software to
+ * not assert a module reset signal that would prevent software from de-asserting
+ * the module reset signal. For example, software should not assert the module
+ * reset to the CPU executing the software.
+ * 
+ * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
+ * assert the module reset signal.
+ * 
+ * All fields are only reset by a cold reset
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                          
+ * :--------|:-------|:------|:--------------------------------------
+ *  [0]     | RW     | 0x0   | Boot ROM                             
+ *  [1]     | RW     | 0x0   | On-chip RAM                          
+ *  [2]     | RW     | 0x0   | System Manager (Cold or Warm)        
+ *  [3]     | RW     | 0x0   | System Manager (Cold-only)           
+ *  [4]     | RW     | 0x0   | FPGA Manager                         
+ *  [5]     | RW     | 0x0   | ACP ID Mapper                        
+ *  [6]     | RW     | 0x0   | HPS to FPGA Core (Cold or Warm)      
+ *  [7]     | RW     | 0x0   | HPS to FPGA Core (Cold-only)         
+ *  [8]     | RW     | 0x0   | nRST Pin                             
+ *  [9]     | RW     | 0x0   | Timestamp                            
+ *  [10]    | RW     | 0x0   | Clock Manager                        
+ *  [11]    | RW     | 0x0   | Scan Manager                         
+ *  [12]    | RW     | 0x0   | Freeze Controller                    
+ *  [13]    | RW     | 0x0   | System/Debug                         
+ *  [14]    | RW     | 0x0   | Debug                                
+ *  [15]    | RW     | 0x0   | TAP Controller                       
+ *  [16]    | RW     | 0x0   | SDRAM Controller Subsystem Cold Reset
+ *  [31:17] | ???    | 0x0   | *UNDEFINED*                          
+ * 
+ */
+/*
+ * Field : Boot ROM - rom
+ * 
+ * Resets Boot ROM
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */
+#define ALT_RSTMGR_MISCMODRST_ROM_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */
+#define ALT_RSTMGR_MISCMODRST_ROM_MSB        0
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_ROM register field. */
+#define ALT_RSTMGR_MISCMODRST_ROM_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_ROM register field value. */
+#define ALT_RSTMGR_MISCMODRST_ROM_SET_MSK    0x00000001
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ROM register field value. */
+#define ALT_RSTMGR_MISCMODRST_ROM_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_RSTMGR_MISCMODRST_ROM register field. */
+#define ALT_RSTMGR_MISCMODRST_ROM_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_ROM field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_RSTMGR_MISCMODRST_ROM register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_ROM_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : On-chip RAM - ocram
+ * 
+ * Resets On-chip RAM
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
+#define ALT_RSTMGR_MISCMODRST_OCRAM_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
+#define ALT_RSTMGR_MISCMODRST_OCRAM_MSB        1
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
+#define ALT_RSTMGR_MISCMODRST_OCRAM_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */
+#define ALT_RSTMGR_MISCMODRST_OCRAM_SET_MSK    0x00000002
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */
+#define ALT_RSTMGR_MISCMODRST_OCRAM_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
+#define ALT_RSTMGR_MISCMODRST_OCRAM_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_OCRAM field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_RSTMGR_MISCMODRST_OCRAM register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : System Manager (Cold or Warm) - sysmgr
+ * 
+ * Resets logic in System Manager that doesn't differentiate between cold and warm
+ * resets
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGR_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGR_MSB        2
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGR_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET_MSK    0x00000004
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGR_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGR_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGR field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGR_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGR register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : System Manager (Cold-only) - sysmgrcold
+ * 
+ * Resets logic in System Manager that is only reset by a cold reset (ignores warm
+ * reset)
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_MSB        3
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET_MSK    0x00000008
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : FPGA Manager - fpgamgr
+ * 
+ * Resets FPGA Manager
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_FPGAMGR_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_FPGAMGR_MSB        4
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_FPGAMGR_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */
+#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET_MSK    0x00000010
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */
+#define ALT_RSTMGR_MISCMODRST_FPGAMGR_CLR_MSK    0xffffffef
+/* The reset value of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_FPGAMGR_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_FPGAMGR field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_FPGAMGR_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_RSTMGR_MISCMODRST_FPGAMGR register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : ACP ID Mapper - acpidmap
+ * 
+ * Resets ACP ID Mapper
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
+#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
+#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_MSB        5
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
+#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */
+#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET_MSK    0x00000020
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */
+#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
+#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_ACPIDMAP field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : HPS to FPGA Core (Cold or Warm) - s2f
+ * 
+ * Resets logic in FPGA core that doesn't differentiate between HPS cold and warm
+ * resets (h2f_rst_n = 1)
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */
+#define ALT_RSTMGR_MISCMODRST_S2F_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */
+#define ALT_RSTMGR_MISCMODRST_S2F_MSB        6
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2F register field. */
+#define ALT_RSTMGR_MISCMODRST_S2F_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2F register field value. */
+#define ALT_RSTMGR_MISCMODRST_S2F_SET_MSK    0x00000040
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2F register field value. */
+#define ALT_RSTMGR_MISCMODRST_S2F_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_RSTMGR_MISCMODRST_S2F register field. */
+#define ALT_RSTMGR_MISCMODRST_S2F_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_S2F field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_S2F_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_RSTMGR_MISCMODRST_S2F register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_S2F_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : HPS to FPGA Core (Cold-only) - s2fcold
+ * 
+ * Resets logic in FPGA core that is only reset by a cold reset (ignores warm
+ * reset) (h2f_cold_rst_n = 1)
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_S2FCOLD_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_S2FCOLD_MSB        7
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_S2FCOLD_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */
+#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET_MSK    0x00000080
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */
+#define ALT_RSTMGR_MISCMODRST_S2FCOLD_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_S2FCOLD_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_S2FCOLD field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_S2FCOLD_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_RSTMGR_MISCMODRST_S2FCOLD register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : nRST Pin - nrstpin
+ * 
+ * Pulls nRST pin low
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
+#define ALT_RSTMGR_MISCMODRST_NRSTPIN_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
+#define ALT_RSTMGR_MISCMODRST_NRSTPIN_MSB        8
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
+#define ALT_RSTMGR_MISCMODRST_NRSTPIN_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */
+#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET_MSK    0x00000100
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */
+#define ALT_RSTMGR_MISCMODRST_NRSTPIN_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
+#define ALT_RSTMGR_MISCMODRST_NRSTPIN_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_NRSTPIN field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_NRSTPIN_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_RSTMGR_MISCMODRST_NRSTPIN register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : Timestamp - timestampcold
+ * 
+ * Resets debug timestamp to 0 (cold reset only)
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_TSCOLD_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_TSCOLD_MSB        9
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_TSCOLD_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */
+#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET_MSK    0x00000200
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */
+#define ALT_RSTMGR_MISCMODRST_TSCOLD_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_TSCOLD_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_TSCOLD field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_TSCOLD_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_RSTMGR_MISCMODRST_TSCOLD register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET(value) (((value) << 9) & 0x00000200)
+
+/*
+ * Field : Clock Manager - clkmgrcold
+ * 
+ * Resets Clock Manager (cold reset only)
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_LSB        10
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_MSB        10
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */
+#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET_MSK    0x00000400
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */
+#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_CLR_MSK    0xfffffbff
+/* The reset value of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
+#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000400) >> 10)
+/* Produces a ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET(value) (((value) << 10) & 0x00000400)
+
+/*
+ * Field : Scan Manager - scanmgr
+ * 
+ * Resets Scan Manager
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_SCANMGR_LSB        11
+/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_SCANMGR_MSB        11
+/* The width in bits of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_SCANMGR_WIDTH      1
+/* The mask used to set the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */
+#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET_MSK    0x00000800
+/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */
+#define ALT_RSTMGR_MISCMODRST_SCANMGR_CLR_MSK    0xfffff7ff
+/* The reset value of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
+#define ALT_RSTMGR_MISCMODRST_SCANMGR_RESET      0x0
+/* Extracts the ALT_RSTMGR_MISCMODRST_SCANMGR field value from a register. */
+#define ALT_RSTMGR_MISCMODRST_SCANMGR_GET(value) (((value) & 0x00000800) >> 11)
+/* Produces a ALT_RSTMGR_MISCMODRST_SCANMGR register field value suitable for setting the register. */
+#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET(value) (((value) << 11) & 0x00000800)
+
+/*
+ * Field : Freeze Controller - frzctrlcold
+ * 
+ * Resets Freeze Controller in System Manager (cold reset only)
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMO