[rtems commit] bsp/altera-vyclone-v: Broadcast cache maintenances

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    dda78f43d532e44151afff2684ea24f0f47f35d7
Changeset: http://git.rtems.org/rtems/commit/?id=dda78f43d532e44151afff2684ea24f0f47f35d7

Author:    Ralf Kirchner <ralf.kirchner at embedded-brains.de>
Date:      Wed May 28 14:47:01 2014 +0200

bsp/altera-vyclone-v: Broadcast cache maintenances

---

 .../arm/altera-cyclone-v/startup/bspstarthooks.c   |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c
index 140156c..18c65b4 100644
--- a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c
@@ -132,16 +132,16 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
 #ifdef RTEMS_SMP
     /* Enable cache coherency support for this processor */
     uint32_t actlr = arm_cp15_get_auxiliary_control();
-    actlr |= ARM_CORTEX_A9_ACTL_SMP;
+    actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW;
     arm_cp15_set_auxiliary_control(actlr);
 #endif
 
     if (cpu_id == 0) {
       arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xF);
     }
-    
+
     setup_mmu_and_cache( cpu_id );
-    
+
 #ifdef RTEMS_SMP
     if (cpu_id != 0) {
       arm_a9mpcore_start_set_vector_base();