[rtems commit] or1ksim: work-around to make or1ksim tick timer accurate.

[Joel Sherrill]

Module:    rtems
Branch:    master
Commit:    5f56d2679a28f64b55dc34aa4907e35d531708c7
Changeset: http://git.rtems.org/rtems/commit/?id=5f56d2679a28f64b55dc34aa4907e35d531708c7

Author:    Hesham ALMatary <heshamelmatary at gmail.com>
Date:      Mon Sep 15 17:33:29 2014 -0500

or1ksim: work-around to make or1ksim tick timer accurate.

This patch avoids unexpected behavior when initializing tick timer registers.
Initializing these registers fires unexpected exceptions and interrupts even
though RTEMS has not enabled interrupts yet. So, a little long interval added
to allow RTEMS to finish the remaining initialization work before running the
application. The tick timer interval is adjusted to reflect an accurate
timing for RTEMS applications.

---

 c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c |   35 +++++++++++++++++++-----
 1 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c b/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c
index 3877fe0..7358bf5 100644
--- a/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c
+++ b/c/src/lib/libbsp/or1k/or1ksim/clock/clockdrv.c
@@ -24,7 +24,7 @@
 #include <rtems/score/or1k-utility.h>
 
 /* The number of clock cycles before generating a tick timer interrupt. */
-#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT     0xFFED9
+#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT     0x09ED9
 #define OR1KSIM_CLOCK_CYCLE_TIME_NANOSECONDS  10
 
 /* This prototype is added here to Avoid warnings */
@@ -63,18 +63,39 @@ static void or1ksim_clock_handler_install(proc_ptr new_isr, proc_ptr old_isr)
 
 static void or1ksim_clock_initialize(void)
 {
-  uint32_t sr;
+  uint32_t TTMR;
 
-  or1ksim_clock_at_tick();
+ /* For TTMR register,
+  * The least significant 28 bits are the number of clock cycles
+  * before generating a tick timer interrupt. While the most
+  * significant 4 bits are used for mode configuration, tick timer
+  * interrupt enable and pending interrupts status.
+  */
 
-   /* Enable tick timer */
-  sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
-  sr |= CPU_OR1K_SPR_SR_TEE;
-  _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
+  /* FIXME: Long interval should pass since initializing the tick timer
+   * registers fires exceptions dispite interrupts has not been enabled yet.
+   */
+  TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
+           (0xFFED9 & CPU_OR1K_SPR_TTMR_TP_MASK)
+         ) & ~(CPU_OR1K_SPR_TTMR_IP);
+
+  _OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
+  _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
 }
 
  static void or1ksim_clock_cleanup(void)
 {
+ uint32_t sr;
+
+  sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
+
+  /* Disable tick timer exceptions */
+  _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)
+  & ~CPU_OR1K_SPR_SR_TEE);
+
+  /* Invalidate tick timer config registers */
+  _OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
+  _OR1K_mtspr(CPU_OR1K_SPR_TTMR, 0);
 }
 
 /*