[rtems commit] bsp/genmcf548x: Use inline cache implementation
Sebastian Huber
sebh at rtems.org
Tue Sep 23 08:42:49 UTC 2014
Module: rtems
Branch: master
Commit: 79bbb1cb67126763d4020195d8561c1481023cab
Changeset: http://git.rtems.org/rtems/commit/?id=79bbb1cb67126763d4020195d8561c1481023cab
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Tue Sep 23 10:45:23 2014 +0200
bsp/genmcf548x: Use inline cache implementation
---
c/src/lib/libbsp/m68k/genmcf548x/Makefile.am | 9 +-
c/src/lib/libbsp/m68k/genmcf548x/include/bsp.h | 7 +
c/src/lib/libbsp/m68k/genmcf548x/include/cache_.h | 117 ++++++++++++++++++++
.../lib/libbsp/m68k/genmcf548x/startup/bspstart.c | 95 +----------------
4 files changed, 133 insertions(+), 95 deletions(-)
diff --git a/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am b/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am
index 8350d80..11dca0b 100644
--- a/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am
+++ b/c/src/lib/libbsp/m68k/genmcf548x/Makefile.am
@@ -33,6 +33,7 @@ project_lib_DATA += startup/linkcmds
noinst_LIBRARIES += libbsp.a
libbsp_a_SOURCES =
+libbsp_a_CPPFLAGS =
# startup
libbsp_a_SOURCES += ../../shared/bspclean.c ../../shared/bsplibc.c \
@@ -57,6 +58,11 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c
libbsp_a_SOURCES += irq/irq.c
libbsp_a_SOURCES += irq/intc-icr-init-values.c
+# Cache
+libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../include/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/include
+
if HAS_NETWORKING
network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
noinst_PROGRAMS += network.rel
@@ -66,8 +72,7 @@ network_rel_CPPFLAGS = $(AM_CPPFLAGS) \
network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
-libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
- ../../../libcpu/@RTEMS_CPU@/shared/misc.rel \
+libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/misc.rel \
../../../libcpu/@RTEMS_CPU@/mcf548x/mcdma.rel
if HAS_NETWORKING
diff --git a/c/src/lib/libbsp/m68k/genmcf548x/include/bsp.h b/c/src/lib/libbsp/m68k/genmcf548x/include/bsp.h
index 769ea0f..e8ea67f 100644
--- a/c/src/lib/libbsp/m68k/genmcf548x/include/bsp.h
+++ b/c/src/lib/libbsp/m68k/genmcf548x/include/bsp.h
@@ -123,6 +123,13 @@ extern int rtems_mcf548x_fec_driver_attach_detach(struct rtems_bsdnet_ifconfig *
#define DBUG_SETTINGS (*(const dbug_settings_t *)0xFC020000)
#endif /* HAS_DBUG */
+
+void bsp_cacr_set_flags(uint32_t flags);
+
+void bsp_cacr_set_self_clear_flags(uint32_t flags);
+
+void bsp_cacr_clear_flags(uint32_t flags);
+
#ifdef __cplusplus
}
#endif
diff --git a/c/src/lib/libbsp/m68k/genmcf548x/include/cache_.h b/c/src/lib/libbsp/m68k/genmcf548x/include/cache_.h
new file mode 100644
index 0000000..7d597c8
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/genmcf548x/include/cache_.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2007-2014 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Dornierstr. 4
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+
+#ifndef LIBBSP_M68K_GENMCF548X_CACHE_H
+#define LIBBSP_M68K_GENMCF548X_CACHE_H
+
+#include <bsp.h>
+
+#define CPU_DATA_CACHE_ALIGNMENT 16
+
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT 16
+
+/*
+ * There is no complete cache lock (only 2 ways of 4 can be locked)
+ */
+static inline void _CPU_cache_freeze_data(void)
+{
+ /* Do nothing */
+}
+
+static inline void _CPU_cache_unfreeze_data(void)
+{
+ /* Do nothing */
+}
+
+static inline void _CPU_cache_freeze_instruction(void)
+{
+ /* Do nothing */
+}
+
+static inline void _CPU_cache_unfreeze_instruction(void)
+{
+ /* Do nothing */
+}
+
+static inline void _CPU_cache_enable_instruction(void)
+{
+ bsp_cacr_clear_flags( MCF548X_CACR_IDCM);
+}
+
+static inline void _CPU_cache_disable_instruction(void)
+{
+ bsp_cacr_set_flags( MCF548X_CACR_IDCM);
+}
+
+static inline void _CPU_cache_invalidate_entire_instruction(void)
+{
+ bsp_cacr_set_self_clear_flags( MCF548X_CACR_ICINVA);
+}
+
+static inline void _CPU_cache_invalidate_1_instruction_line(const void *addr)
+{
+ uint32_t a = (uint32_t) addr & ~0x3;
+
+ __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x0));
+ __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x1));
+ __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x2));
+ __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x3));
+}
+
+static inline void _CPU_cache_enable_data(void)
+{
+ bsp_cacr_clear_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
+}
+
+static inline void _CPU_cache_disable_data(void)
+{
+ bsp_cacr_set_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
+}
+
+static inline void _CPU_cache_invalidate_entire_data(void)
+{
+ bsp_cacr_set_self_clear_flags( MCF548X_CACR_DCINVA);
+}
+
+static inline void _CPU_cache_invalidate_1_data_line( const void *addr)
+{
+ uint32_t a = (uint32_t) addr & ~0x3;
+
+ __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
+ __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
+ __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
+ __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
+}
+
+static inline void _CPU_cache_flush_1_data_line( const void *addr)
+{
+ uint32_t a = (uint32_t) addr & ~0x3;
+
+ __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
+ __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
+ __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
+ __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
+}
+
+static inline void _CPU_cache_flush_entire_data( void)
+{
+ uint32_t line = 0;
+
+ for (line = 0; line < 512; ++line) {
+ _CPU_cache_flush_1_data_line( (const void *) (line * 16));
+ }
+}
+
+#endif /* LIBBSP_M68K_GENMCF548X_CACHE_H */
diff --git a/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c b/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c
index df6adea..6c1da2a 100644
--- a/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c
+++ b/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c
@@ -44,6 +44,7 @@
\*===============================================================*/
#include <bsp.h>
+#include <bsp/bootcard.h>
extern uint32_t _CPU_cacr_shadow;
@@ -120,101 +121,9 @@ void bsp_cacr_clear_flags( uint32_t flags)
}
/*
- * There is no complete cache lock (only 2 ways of 4 can be locked)
- */
-void _CPU_cache_freeze_data(void)
-{
- /* Do nothing */
-}
-
-void _CPU_cache_unfreeze_data(void)
-{
- /* Do nothing */
-}
-
-void _CPU_cache_freeze_instruction(void)
-{
- /* Do nothing */
-}
-
-void _CPU_cache_unfreeze_instruction(void)
-{
- /* Do nothing */
-}
-
-void _CPU_cache_enable_instruction(void)
-{
- bsp_cacr_clear_flags( MCF548X_CACR_IDCM);
-}
-
-void _CPU_cache_disable_instruction(void)
-{
- bsp_cacr_set_flags( MCF548X_CACR_IDCM);
-}
-
-void _CPU_cache_invalidate_entire_instruction(void)
-{
- bsp_cacr_set_self_clear_flags( MCF548X_CACR_ICINVA);
-}
-
-void _CPU_cache_invalidate_1_instruction_line(const void *addr)
-{
- uint32_t a = (uint32_t) addr & ~0x3;
-
- __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x0));
- __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x1));
- __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x2));
- __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x3));
-}
-
-void _CPU_cache_enable_data(void)
-{
- bsp_cacr_clear_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
-}
-
-void _CPU_cache_disable_data(void)
-{
- bsp_cacr_set_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
-}
-
-void _CPU_cache_invalidate_entire_data(void)
-{
- bsp_cacr_set_self_clear_flags( MCF548X_CACR_DCINVA);
-}
-
-void _CPU_cache_invalidate_1_data_line( const void *addr)
-{
- uint32_t a = (uint32_t) addr & ~0x3;
-
- __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
- __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
- __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
- __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
-}
-
-void _CPU_cache_flush_1_data_line( const void *addr)
-{
- uint32_t a = (uint32_t) addr & ~0x3;
-
- __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
- __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
- __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
- __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
-}
-
-void _CPU_cache_flush_entire_data( void)
-{
- uint32_t line = 0;
-
- for (line = 0; line < 512; ++line) {
- _CPU_cache_flush_1_data_line( (const void *) (line * 16));
- }
-}
-
-/*
* Coldfire acr and mmu settings
*/
- void acr_mmu_mapping(void)
+ static void acr_mmu_mapping(void)
{
/*
More information about the vc
mailing list