[rtems commit] bsps/arm: Do not use __ARM_ARCH_7A__

Sebastian Huber sebh at rtems.org
Fri Jul 31 07:59:25 UTC 2015


Module:    rtems
Branch:    master
Commit:    d0733bb871e31d9742afb84610ab4beb708c635c
Changeset: http://git.rtems.org/rtems/commit/?id=d0733bb871e31d9742afb84610ab4beb708c635c

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Fri Jul 31 09:55:22 2015 +0200

bsps/arm: Do not use __ARM_ARCH_7A__

This would lead to link-time errors in case less specialized compiler
machine options are used, e.g. to run the GCC test suite.

---

 c/src/lib/libbsp/arm/shared/include/arm-errata.h | 44 +++++++++---------------
 1 file changed, 16 insertions(+), 28 deletions(-)

diff --git a/c/src/lib/libbsp/arm/shared/include/arm-errata.h b/c/src/lib/libbsp/arm/shared/include/arm-errata.h
index c58084a..4403eb1 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-errata.h
+++ b/c/src/lib/libbsp/arm/shared/include/arm-errata.h
@@ -30,31 +30,24 @@
 extern "C" {
 #endif /* __cplusplus */
 
-#if defined( __ARM_ARCH_7A__ )
-static arm_release_id arm_errata_get_processor_release(
-  void
-)
+static inline arm_release_id arm_errata_get_processor_release(void)
 {
   const uint32_t MIDR          = arm_cp15_get_id_code();
   const uint8_t  REVISION      = (MIDR & 0xF00000U) >> 20;
   const uint8_t  PATCH_LEVEL   = (MIDR & 0xFU);
-  
+
   return ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL(
     REVISION,
     PATCH_LEVEL
   );
 }
-#endif /* #if defined( __ARM_ARCH_7A__ ) */
 
-#if defined( __ARM_ARCH_7A__ )
-#if ( defined( RTEMS_SMP ) )
-static bool arm_errata_is_applicable_processor_errata_764369(
-  void
-)
+static bool inline arm_errata_is_applicable_processor_errata_764369(void)
 {
+#if defined(RTEMS_SMP)
   const arm_release_id RELEASE       = arm_errata_get_processor_release();
   bool                 is_applicable = false;
-  
+
   /* Errata information for Cortex-A9 processors.
    * Information taken from ARMs
    * "Cortex-A series processors
@@ -64,7 +57,7 @@ static bool arm_errata_is_applicable_processor_errata_764369(
    * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice"
    * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html
    * Please see this document for more information on these erratas */
-  
+
   switch( RELEASE ) {
     case ARM_RELEASE_ID_R4_P1:
     case ARM_RELEASE_ID_R4_P4:
@@ -82,22 +75,18 @@ static bool arm_errata_is_applicable_processor_errata_764369(
       is_applicable = false;
     break;
   }
-  
+
   return is_applicable;
-}
 #else
-  #define arm_errata_is_applicable_processor_errata_764369() false
-#endif /*  ( defined( RTEMS_SMP ) ) */
-#endif /* #if defined( __ARM_ARCH_7A__ ) */
-
-#if defined( __ARM_ARCH_7A__ )
-static bool arm_errata_is_applicable_processor_errata_775420(
-  void
-)
+  return false;
+#endif
+}
+
+static inline bool arm_errata_is_applicable_processor_errata_775420(void)
 {
   const arm_release_id RELEASE       = arm_errata_get_processor_release();
   bool                 is_applicable = false;
-  
+
   /* Errata information for Cortex-A9 processors.
   * Information taken from ARMs
   * "Cortex-A series processors
@@ -107,7 +96,7 @@ static bool arm_errata_is_applicable_processor_errata_775420(
   * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice"
   * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html
   * Please see this document for more information on these erratas */
-  
+
   switch( RELEASE ) {
     case ARM_RELEASE_ID_R2_P10:
     case ARM_RELEASE_ID_R2_P8:
@@ -120,13 +109,12 @@ static bool arm_errata_is_applicable_processor_errata_775420(
       is_applicable = false;
     break;
   }
-  
+
   return is_applicable;
 }
-#endif /* #if defined( __ARM_ARCH_7A__ ) */
 
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
 
-#endif /* ARM_ERRATA_H_ */
\ No newline at end of file
+#endif /* ARM_ERRATA_H_ */



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