[rtems commit] doc: Add SMP section to CPU Arch Supplement
Sebastian Huber
sebh at rtems.org
Thu Jul 23 07:12:05 UTC 2015
Module: rtems
Branch: master
Commit: 19078dc6e60010002498e455d2b6a39fd9160ba4
Changeset: http://git.rtems.org/rtems/commit/?id=19078dc6e60010002498e455d2b6a39fd9160ba4
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Thu Jul 23 08:36:30 2015 +0200
doc: Add SMP section to CPU Arch Supplement
---
doc/cpu_supplement/arm.t | 5 +++++
doc/cpu_supplement/avr.t | 4 ++++
doc/cpu_supplement/bfin.t | 4 ++++
doc/cpu_supplement/epiphany.t | 4 ++++
doc/cpu_supplement/general.t | 5 +++++
doc/cpu_supplement/h8300.t | 4 ++++
doc/cpu_supplement/i386.t | 4 ++++
doc/cpu_supplement/lm32.t | 4 ++++
doc/cpu_supplement/m32c.t | 4 ++++
doc/cpu_supplement/m32r.t | 4 ++++
doc/cpu_supplement/m68k.t | 4 ++++
doc/cpu_supplement/microblaze.t | 4 ++++
doc/cpu_supplement/mips.t | 4 ++++
doc/cpu_supplement/nios2.t | 4 ++++
doc/cpu_supplement/or1k.t | 4 ++++
doc/cpu_supplement/powerpc.t | 5 +++++
doc/cpu_supplement/sh.t | 4 ++++
doc/cpu_supplement/sparc.t | 5 +++++
doc/cpu_supplement/sparc64.t | 4 ++++
doc/cpu_supplement/v850.t | 4 ++++
20 files changed, 84 insertions(+)
diff --git a/doc/cpu_supplement/arm.t b/doc/cpu_supplement/arm.t
index 304e1e1..e24ca00 100644
--- a/doc/cpu_supplement/arm.t
+++ b/doc/cpu_supplement/arm.t
@@ -172,6 +172,11 @@ following actions:
@item executes an infinite loop to simulate a halt processor instruction.
@end itemize
+ at section Symmetric Multiprocessing
+
+SMP is supported on ARMv7-A. Available platforms are the Altera Cyclone V and
+the Xilinx Zynq.
+
@section Thread-Local Storage
Thread-local storage is supported.
diff --git a/doc/cpu_supplement/avr.t b/doc/cpu_supplement/avr.t
index 233e052..9ad4d2e 100644
--- a/doc/cpu_supplement/avr.t
+++ b/doc/cpu_supplement/avr.t
@@ -117,6 +117,10 @@ actions:
simulate a halt processor instruction.
@end itemize
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not supported due to a broken tool chain.
diff --git a/doc/cpu_supplement/bfin.t b/doc/cpu_supplement/bfin.t
index 320061a..3beed67 100644
--- a/doc/cpu_supplement/bfin.t
+++ b/doc/cpu_supplement/bfin.t
@@ -130,6 +130,10 @@ actions:
simulate a halt processor instruction.
@end itemize
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.
diff --git a/doc/cpu_supplement/epiphany.t b/doc/cpu_supplement/epiphany.t
index a0976cf..87f74c3 100644
--- a/doc/cpu_supplement/epiphany.t
+++ b/doc/cpu_supplement/epiphany.t
@@ -73,3 +73,7 @@ following actions:
@item places the error code in @code{r0}, and
@item executes an infinite loop to simulate a halt processor instruction.
@end itemize
+
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
diff --git a/doc/cpu_supplement/general.t b/doc/cpu_supplement/general.t
index 82b8dcb..43f91e1 100644
--- a/doc/cpu_supplement/general.t
+++ b/doc/cpu_supplement/general.t
@@ -344,6 +344,11 @@ interrupts and halts the processor.
In each of the architecture specific chapters, this describes the precise
operations of the default CPU specific fatal error handler.
+ at section Symmetric Multiprocessing
+
+This section contains information about the Symmetric Multiprocessing (SMP)
+status of a particular architecture.
+
@section Thread-Local Storage
In order to support thread-local storage (TLS) the CPU port must implement the
diff --git a/doc/cpu_supplement/h8300.t b/doc/cpu_supplement/h8300.t
index 8120a31..8c50ffb 100644
--- a/doc/cpu_supplement/h8300.t
+++ b/doc/cpu_supplement/h8300.t
@@ -2,6 +2,10 @@
@chapter Renesas H8/300 Specific Information
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.
diff --git a/doc/cpu_supplement/i386.t b/doc/cpu_supplement/i386.t
index 716cf9b..77acace 100644
--- a/doc/cpu_supplement/i386.t
+++ b/doc/cpu_supplement/i386.t
@@ -266,6 +266,10 @@ The default fatal error handler for this architecture disables processor
interrupts, places the error code in EAX, and executes a HLT instruction
to halt the processor.
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.
diff --git a/doc/cpu_supplement/lm32.t b/doc/cpu_supplement/lm32.t
index a81e0b5..6aab8e3 100644
--- a/doc/cpu_supplement/lm32.t
+++ b/doc/cpu_supplement/lm32.t
@@ -163,6 +163,10 @@ interrupts and halts the processor.
In each of the architecture specific chapters, this describes the precise
operations of the default CPU specific fatal error handler.
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.
diff --git a/doc/cpu_supplement/m32c.t b/doc/cpu_supplement/m32c.t
index ce738fe..98d86c1 100644
--- a/doc/cpu_supplement/m32c.t
+++ b/doc/cpu_supplement/m32c.t
@@ -2,6 +2,10 @@
@chapter Renesas M32C Specific Information
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.
diff --git a/doc/cpu_supplement/m32r.t b/doc/cpu_supplement/m32r.t
index f70c185..951bf94 100644
--- a/doc/cpu_supplement/m32r.t
+++ b/doc/cpu_supplement/m32r.t
@@ -2,6 +2,10 @@
@chapter Renesas M32R Specific Information
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.
diff --git a/doc/cpu_supplement/m68k.t b/doc/cpu_supplement/m68k.t
index a3ddc88..7201571 100644
--- a/doc/cpu_supplement/m68k.t
+++ b/doc/cpu_supplement/m68k.t
@@ -357,6 +357,10 @@ The default fatal error handler for this architecture disables processor
interrupts to level 7, places the error code in D0, and executes a
@code{stop} instruction to simulate a halt processor instruction.
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is supported.
diff --git a/doc/cpu_supplement/microblaze.t b/doc/cpu_supplement/microblaze.t
index b641d43..ff52d2e 100644
--- a/doc/cpu_supplement/microblaze.t
+++ b/doc/cpu_supplement/microblaze.t
@@ -2,6 +2,10 @@
@chapter Xilinx MicroBlaze Specific Information
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.
diff --git a/doc/cpu_supplement/mips.t b/doc/cpu_supplement/mips.t
index 7d6fcb3..c966bf5 100644
--- a/doc/cpu_supplement/mips.t
+++ b/doc/cpu_supplement/mips.t
@@ -122,6 +122,10 @@ The default fatal error handler for this target architecture disables
processor interrupts, places the error code in @b{XXX}, and executes a
@code{XXX} instruction to simulate a halt processor instruction.
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.
diff --git a/doc/cpu_supplement/nios2.t b/doc/cpu_supplement/nios2.t
index 9013f15..2d423c7 100644
--- a/doc/cpu_supplement/nios2.t
+++ b/doc/cpu_supplement/nios2.t
@@ -2,6 +2,10 @@
@chapter Altera Nios II Specific Information
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.
diff --git a/doc/cpu_supplement/or1k.t b/doc/cpu_supplement/or1k.t
index cce55fd..4d14f74 100644
--- a/doc/cpu_supplement/or1k.t
+++ b/doc/cpu_supplement/or1k.t
@@ -74,3 +74,7 @@ following actions:
@item places the error code in @code{r0}, and
@item executes an infinite loop to simulate a halt processor instruction.
@end itemize
+
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
diff --git a/doc/cpu_supplement/powerpc.t b/doc/cpu_supplement/powerpc.t
index abf02e0..4e7af1f 100644
--- a/doc/cpu_supplement/powerpc.t
+++ b/doc/cpu_supplement/powerpc.t
@@ -657,6 +657,11 @@ If the Program Exception returns, then the following actions are performed:
@end itemize
+ at section Symmetric Multiprocessing
+
+SMP is supported. Available platforms are the Freescale QorIQ P series (e.g.
+P1020) and T series (e.g. T2080, T4240).
+
@section Thread-Local Storage
Thread-local storage is supported.
diff --git a/doc/cpu_supplement/sh.t b/doc/cpu_supplement/sh.t
index 763c31e..fb2d3c2 100644
--- a/doc/cpu_supplement/sh.t
+++ b/doc/cpu_supplement/sh.t
@@ -139,6 +139,10 @@ The default fatal error handler for this architecture disables processor
interrupts, places the error code in @b{XXX}, and executes a @code{XXX}
instruction to simulate a halt processor instruction.
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.
diff --git a/doc/cpu_supplement/sparc.t b/doc/cpu_supplement/sparc.t
index 740643a..749c1fd 100644
--- a/doc/cpu_supplement/sparc.t
+++ b/doc/cpu_supplement/sparc.t
@@ -969,6 +969,11 @@ error source in register @code{g2}, and the error code in register
@code{g3}. It will then generate a system error which will
hand over control to the debugger, simulator, etc.
+ at section Symmetric Multiprocessing
+
+SMP is supported. Available platforms are the Cobham Gaisler GR712RC and
+GR740.
+
@section Thread-Local Storage
Thread-local storage is supported.
diff --git a/doc/cpu_supplement/sparc64.t b/doc/cpu_supplement/sparc64.t
index f930008..5c07989 100644
--- a/doc/cpu_supplement/sparc64.t
+++ b/doc/cpu_supplement/sparc64.t
@@ -773,6 +773,10 @@ default fatal error handler disables processor interrupts to
level 15, places the error code in g1, and goes into an infinite
loop to simulate a halt processor instruction.
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is supported.
diff --git a/doc/cpu_supplement/v850.t b/doc/cpu_supplement/v850.t
index e8ef05e..ab84461 100644
--- a/doc/cpu_supplement/v850.t
+++ b/doc/cpu_supplement/v850.t
@@ -103,6 +103,10 @@ following actions:
@item executes a halt processor instruction.
@end itemize
+ at section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.
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