[rtems commit] doc: Add new documentation section for Epiphany architecture

[Gedare Bloom]

Module:    rtems
Branch:    master
Commit:    10504d3ca4d827eaed7c5b2822b3dc75e7b6d11b
Changeset: http://git.rtems.org/rtems/commit/?id=10504d3ca4d827eaed7c5b2822b3dc75e7b6d11b

Author:    Hesham ALMatary <heshamelmatary at gmail.com>
Date:      Wed May 20 09:51:02 2015 +0100

doc: Add new documentation section for Epiphany architecture

---

 doc/cpu_supplement/Makefile.am         |  6 +++
 doc/cpu_supplement/cpu_supplement.texi |  2 +
 doc/cpu_supplement/epiphany.t          | 75 ++++++++++++++++++++++++++++++++++
 3 files changed, 83 insertions(+)

diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am
index 300ff78..06ebf48 100644
--- a/doc/cpu_supplement/Makefile.am
+++ b/doc/cpu_supplement/Makefile.am
@@ -15,6 +15,7 @@ GENERATED_FILES += general.texi
 GENERATED_FILES += arm.texi
 GENERATED_FILES += avr.texi
 GENERATED_FILES += bfin.texi
+GENERATED_FILES += epiphany.texi
 GENERATED_FILES += h8300.texi
 GENERATED_FILES += i386.texi
 GENERATED_FILES += lm32.texi
@@ -62,6 +63,11 @@ bfin.texi: bfin.t
 	    -u "Top" \
 	    -n "" < $< > $@
 
+epiphany.texi: epiphany.t
+	$(BMENU2) -p "" \
+	    -u "Top" \
+	    -n "" < $< > $@
+
 h8300.texi: h8300.t
 	$(BMENU2) -p "" \
 	    -u "Top" \
diff --git a/doc/cpu_supplement/cpu_supplement.texi b/doc/cpu_supplement/cpu_supplement.texi
index 5c484d0..105a54e 100644
--- a/doc/cpu_supplement/cpu_supplement.texi
+++ b/doc/cpu_supplement/cpu_supplement.texi
@@ -65,6 +65,7 @@
 * ARM Specific Information::
 * Atmel AVR Specific Information::
 * Blackfin Specific Information::
+* Epiphany Specific Information::
 * Renesas H8/300 Specific Information::
 * Intel/AMD x86 Specific Information::
 * Lattice Mico32 Specific Information::
@@ -89,6 +90,7 @@
 @include arm.texi
 @include avr.texi
 @include bfin.texi
+ at include epiphany.texi
 @include h8300.texi
 @include i386.texi
 @include lm32.texi
diff --git a/doc/cpu_supplement/epiphany.t b/doc/cpu_supplement/epiphany.t
new file mode 100644
index 0000000..a0976cf
--- /dev/null
+++ b/doc/cpu_supplement/epiphany.t
@@ -0,0 +1,75 @@
+ at c
+ at c  Copyright (c) 2015 University of York.
+ at c  Hesham ALMatary <hmka501 at york.ac.uk>
+
+ at ifinfo
+ at end ifinfo
+ at chapter Epiphany Specific Information
+
+This chapter discusses the
+ at uref{http://adapteva.com/docs/epiphany_sdk_ref.pdf, Epiphany Architecture}
+dependencies in this port of RTEMS. Epiphany is a chip that can come with 16 and
+64 cores, each of which can run RTEMS separately or they can work together to 
+run a SMP RTEMS application.
+
+ at subheading Architecture Documents
+
+For information on the Epiphany architecture refer to the
+ at uref{http://adapteva.com/docs/epiphany_arch_ref.pdf,Epiphany Architecture Reference}.
+
+ at section Calling Conventions
+
+Please refer to the
+ at uref{http://adapteva.com/docs/epiphany_sdk_ref.pdf, Epiphany SDK}
+Appendix A: Application Binary Interface
+
+ at subsection Floating Point Unit
+
+A floating point unit is currently not supported.
+
+ at section Memory Model
+
+A flat 32-bit memory model is supported, no caches. Each core has its own 32 KiB
+strictly ordered local memory along with an access to a shared 32 MiB external
+DRAM.
+
+ at section Interrupt Processing
+
+Every Epiphany core has 10 exception types:
+
+ at itemize @bullet
+
+ at item Reset
+ at item Software Exception
+ at item Data Page Fault
+ at item Timer 0
+ at item Timer 1
+ at item Message Interrupt
+ at item DMA0 Interrupt
+ at item DMA1 Interrupt
+ at item WANT Interrupt
+ at item User Interrupt
+
+ at end itemize
+
+ at subsection Interrupt Levels
+
+There are only two levels: interrupts enabled and interrupts disabled.
+
+ at subsection Interrupt Stack
+
+The Epiphany RTEMS port uses a dedicated software interrupt stack.
+The stack for interrupts is allocated during interrupt driver initialization.
+When an  interrupt is entered, the _ISR_Handler routine is responsible for
+switching from the interrupted task stack to RTEMS software interrupt stack.
+
+ at section Default Fatal Error Processing
+
+The default fatal error handler for this architecture performs the
+following actions:
+
+ at itemize @bullet
+ at item disables operating system supported interrupts (IRQ),
+ at item places the error code in @code{r0}, and
+ at item executes an infinite loop to simulate a halt processor instruction.
+ at end itemize