[rtems commit] powerpc: Add FSL cache defines

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    e96feebdd1c5815e8a607dc9ee00d1d0f5ff8524
Changeset: http://git.rtems.org/rtems/commit/?id=e96feebdd1c5815e8a607dc9ee00d1d0f5ff8524

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Tue Oct 27 10:20:02 2015 +0100

powerpc: Add FSL cache defines

---

 cpukit/score/cpu/powerpc/rtems/powerpc/registers.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
index c982e46..4ea631c 100644
--- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
+++ b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
@@ -550,7 +550,17 @@ lidate */
 #define FSL_EIS_L1CFG0 515
 #define FSL_EIS_L1CFG1 516
 #define FSL_EIS_L1CSR0 1010
+#define FSL_EIS_L1CSR0_CFI (1 << (63 - 62))
 #define FSL_EIS_L1CSR1 1011
+#define FSL_EIS_L1CSR1_ICFI (1 << (63 - 62))
+
+/* Freescale Book E Implementation Standards (EIS): L2 Cache */
+
+#define FSL_EIS_L2CFG0 519
+#define FSL_EIS_L2CSR0 1017
+#define FSL_EIS_L2CSR0_L2FI (1 << (63 - 42))
+#define FSL_EIS_L2CSR0_L2FL (1 << (63 - 52))
+#define FSL_EIS_L2CSR1 1018
 
 /* Freescale Book E Implementation Standards (EIS): Timer */