[rtems commit] ARMv7M: Improve exception handler routine and add comments on SP selection

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    f52885b6bc246e090cc66fe9ef92d26db2bca646
Changeset: http://git.rtems.org/rtems/commit/?id=f52885b6bc246e090cc66fe9ef92d26db2bca646

Author:    Martin Galvan <martin.galvan at tallertechnologies.com>
Date:      Fri Sep 18 18:53:31 2015 -0300

ARMv7M: Improve exception handler routine and add comments on SP selection

This patch adds a brief description of how context state is saved into the
SP on exception entry, and makes a few changes to _ARMV7M_Exception_default
in order to make it a bit more efficient. I also removed the unused 'v7mfsz'
input parameter.

This should apply over Sudarshan's patch.

---

 cpukit/score/cpu/arm/armv7m-exception-default.c | 32 ++++++++++++++++---------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/cpukit/score/cpu/arm/armv7m-exception-default.c b/cpukit/score/cpu/arm/armv7m-exception-default.c
index 2ddc6fc..0e4efad 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-default.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-default.c
@@ -22,20 +22,31 @@
 
 void __attribute__((naked)) _ARMV7M_Exception_default( void )
 {
+    /* On exception entry, ARMv7M saves context state onto a stack pointed to
+     * by either MSP or PSP. The value stored in LR indicates whether we were
+     * in Thread or Handler mode, whether we were using the FPU (if any),
+     * and which stack pointer we were using.
+     * In particular, bit 2 of LR will be 0 if we were using MSP.
+     *
+     * For a more detailed explanation, see the Exception Entry Behavior
+     * section of the ARMv7M Architecture Reference Manual.
+     */
+
+    /* As we're in Handler mode here, we'll always operate on MSP.
+     * However, we need to store the right SP in our CPU_Exception_frame.
+     */
   __asm__ volatile (
-    "sub sp, %[cpufsz]\n"
+    "sub sp, %[cpufsz]\n"   /* Allocate space for a CPU_Exception_frame. */
     "stm sp, {r0-r12}\n"
-    "mov r2, lr\n"
-    "mrs r1, msp\n"
-    "mrs r0, psp\n"
-    "tst lr, #4\n"
-    "itt eq\n"
-    "moveq r0, r1\n"
-    "addeq r0, %[cpufsz]\n"
+    "tst lr, #4\n"          /* Check if bit 2 of LR is zero. If so, PSR.Z = 1 */
+    "itte eq\n"             /* IF bit 2 of LR is zero... (PSR.Z == 1) */
+    "mrseq r0, msp\n"       /* THEN we were using MSP. */
+    "addeq r0, %[cpufsz]\n" /* THEN, set r0 = old MSP value. */
+    "mrsne r0, psp\n"       /* ELSE it's not zero; we were using PSP. */
     "add r2, r0, %[v7mlroff]\n"
     "add r1, sp, %[cpulroff]\n"
-    "ldm r2, {r3-r5}\n"
-    "stm r1, {r3-r5}\n"
+    "ldm r2, {r3-r5}\n"     /* Grab LR, PC and PSR from the stack.. */
+    "stm r1, {r3-r5}\n"     /* ..and store them in our CPU_Exception_frame. */
     "mrs r1, ipsr\n"
     "str r1, [sp, %[cpuvecoff]]\n"
 
@@ -74,7 +85,6 @@ void __attribute__((naked)) _ARMV7M_Exception_default( void )
     "b _ARM_Exception_default\n"
     :
     : [cpufsz] "i" (sizeof(CPU_Exception_frame)),
-      [v7mfsz] "i" (sizeof(ARMV7M_Exception_frame)),
       [cpulroff] "i" (offsetof(CPU_Exception_frame, register_lr)),
       [v7mlroff] "i" (offsetof(ARMV7M_Exception_frame, register_lr)),
       [cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector)),