[rtems commit] arm: Add VFP context validate support for ARMv5

Sebastian Huber sebh at rtems.org
Fri Aug 19 05:40:50 UTC 2016


Module:    rtems
Branch:    master
Commit:    36fad91f00360db3a45e3046ae7b62ae13fac9fd
Changeset: http://git.rtems.org/rtems/commit/?id=36fad91f00360db3a45e3046ae7b62ae13fac9fd

Author:    Kevin Kirspel <Kevin-Kirspel at idexx.com>
Date:      Fri Aug 19 07:38:07 2016 +0200

arm: Add VFP context validate support for ARMv5

---

 cpukit/score/cpu/arm/arm-context-validate.S         | 9 ++++++---
 cpukit/score/cpu/arm/arm-context-volatile-clobber.S | 7 +++++--
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/cpukit/score/cpu/arm/arm-context-validate.S b/cpukit/score/cpu/arm/arm-context-validate.S
index fdfb6c1..5bb2e25 100644
--- a/cpukit/score/cpu/arm/arm-context-validate.S
+++ b/cpukit/score/cpu/arm/arm-context-validate.S
@@ -46,7 +46,11 @@
 
 	.section	.text
 
+#ifdef __thumb__
 FUNCTION_THUMB_ENTRY(_CPU_Context_validate)
+#else
+FUNCTION_ENTRY(_CPU_Context_validate)
+#endif
 
 	/* Save */
 
@@ -99,11 +103,10 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate)
 #ifdef ARM_MULTILIB_VFP
 	/* R3 contains the FPSCR */
 	vmrs	r3, FPSCR
-	movs	r4, #0x001f
 #ifdef ARM_MULTILIB_ARCH_V7M
-	movt	r4, #0xf000
+	ldr	r4, =0xf000001f
 #else
-	movt	r4, #0xf800
+	ldr	r4, =0xf800001f
 #endif
 	bic	r3, r3, r4
 	and	r4, r4, r0
diff --git a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
index 7970b8e..b3c9d77 100644
--- a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
+++ b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
@@ -20,7 +20,11 @@
 
 	.section	.text
 
+#ifdef __thumb__
 FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber)
+#else
+FUNCTION_ENTRY(_CPU_Context_volatile_clobber)
+#endif
 
 .macro clobber_register reg
 	sub	r0, r0, #1
@@ -29,8 +33,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber)
 
 #ifdef ARM_MULTILIB_VFP
 	vmrs	r1, FPSCR
-	movs	r2, #0x001f
-	movt	r2, #0xf800
+	ldr	r2, =0xf800001f
 	bic	r1, r1, r2
 	and	r2, r2, r0
 	orr	r1, r1, r2




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