[rtems commit] Remove M32R architecture
Joel Sherril
joel at rtems.org
Mon Jan 4 17:14:56 UTC 2016
Module: rtems
Branch: master
Commit: f5201df0dc70e4510c7a6862a96d66175fbbf514
Changeset: http://git.rtems.org/rtems/commit/?id=f5201df0dc70e4510c7a6862a96d66175fbbf514
Author: Joel Sherrill <joel.sherrill at oarcorp.com>
Date: Tue Dec 15 11:25:01 2015 -0600
Remove M32R architecture
updates #2446.
---
c/src/aclocal/rtems-cpu-subdirs.m4 | 1 -
c/src/lib/libbsp/m32r/Makefile.am | 9 -
c/src/lib/libbsp/m32r/acinclude.m4 | 8 -
c/src/lib/libbsp/m32r/configure.ac | 20 -
cpukit/configure.ac | 4 +-
cpukit/libcsupport/src/newlibc_exit.c | 4 +-
.../libdl/include/arch/m32r/machine/elf_machdep.h | 39 -
cpukit/libdl/rtl-mdreloc-m32r.c | 156 ---
cpukit/libdl/rtl-shell.c | 2 +-
cpukit/librpc/src/xdr/xdr_float.c | 1 -
cpukit/score/cpu/Makefile.am | 1 -
cpukit/score/cpu/m32r/Makefile.am | 22 -
cpukit/score/cpu/m32r/context_init.c | 61 -
cpukit/score/cpu/m32r/context_switch.S | 67 --
cpukit/score/cpu/m32r/cpu.c | 125 --
cpukit/score/cpu/m32r/cpu_asm.c | 106 --
cpukit/score/cpu/m32r/m32r-exception-frame-print.c | 24 -
cpukit/score/cpu/m32r/preinstall.am | 54 -
cpukit/score/cpu/m32r/rtems/asm.h | 127 --
cpukit/score/cpu/m32r/rtems/score/cpu.h | 1272 --------------------
cpukit/score/cpu/m32r/rtems/score/cpu_asm.h | 72 --
cpukit/score/cpu/m32r/rtems/score/cpuatomic.h | 14 -
cpukit/score/cpu/m32r/rtems/score/m32r.h | 70 --
cpukit/score/cpu/m32r/rtems/score/types.h | 52 -
cpukit/score/src/threadglobalconstruction.c | 4 +-
doc/cpu_supplement/Makefile.am | 8 +-
doc/cpu_supplement/cpu_supplement.texi | 2 -
doc/cpu_supplement/m32r.t | 11 -
doc/user/preface.texi | 3 +-
testsuites/libtests/configure.ac | 3 +-
30 files changed, 7 insertions(+), 2335 deletions(-)
diff --git a/c/src/aclocal/rtems-cpu-subdirs.m4 b/c/src/aclocal/rtems-cpu-subdirs.m4
index 524edac..3cb28b1 100644
--- a/c/src/aclocal/rtems-cpu-subdirs.m4
+++ b/c/src/aclocal/rtems-cpu-subdirs.m4
@@ -18,7 +18,6 @@ _RTEMS_CPU_SUBDIR([h8300],[$1]);;
_RTEMS_CPU_SUBDIR([i386],[$1]);;
_RTEMS_CPU_SUBDIR([lm32],[$1]);;
_RTEMS_CPU_SUBDIR([m32c],[$1]);;
-_RTEMS_CPU_SUBDIR([m32r],[$1]);;
_RTEMS_CPU_SUBDIR([m68k],[$1]);;
_RTEMS_CPU_SUBDIR([mips],[$1]);;
_RTEMS_CPU_SUBDIR([moxie],[$1]);;
diff --git a/c/src/lib/libbsp/m32r/Makefile.am b/c/src/lib/libbsp/m32r/Makefile.am
deleted file mode 100644
index f504c03..0000000
--- a/c/src/lib/libbsp/m32r/Makefile.am
+++ /dev/null
@@ -1,9 +0,0 @@
-ACLOCAL_AMFLAGS = -I ../../../aclocal
-
-## Descend into the @RTEMS_BSP_FAMILY@ directory
-SUBDIRS = @RTEMS_BSP_FAMILY@
-
-EXTRA_DIST =
-
-include $(top_srcdir)/../../../automake/subdirs.am
-include $(top_srcdir)/../../../automake/local.am
diff --git a/c/src/lib/libbsp/m32r/acinclude.m4 b/c/src/lib/libbsp/m32r/acinclude.m4
deleted file mode 100644
index 296a6f7..0000000
--- a/c/src/lib/libbsp/m32r/acinclude.m4
+++ /dev/null
@@ -1,8 +0,0 @@
-# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY)
-AC_DEFUN([RTEMS_CHECK_BSPDIR],
-[
- case "$1" in
- *)
- AC_MSG_ERROR([Invalid BSP]);;
- esac
-])
diff --git a/c/src/lib/libbsp/m32r/configure.ac b/c/src/lib/libbsp/m32r/configure.ac
deleted file mode 100644
index 362e534..0000000
--- a/c/src/lib/libbsp/m32r/configure.ac
+++ /dev/null
@@ -1,20 +0,0 @@
-## Process this file with autoconf to produce a configure script.
-
-AC_PREREQ([2.69])
-AC_INIT([rtems-c-src-lib-libbsp-m32r],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
-AC_CONFIG_SRCDIR([Makefile.am])
-RTEMS_TOP(../../../../..)
-
-RTEMS_CANONICAL_TARGET_CPU
-AM_INIT_AUTOMAKE([no-define foreign 1.12.2])
-AM_MAINTAINER_MODE
-
-RTEMS_ENV_RTEMSBSP
-
-RTEMS_PROJECT_ROOT
-
-RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY])
-
-# Explicitly list all Makefiles here
-AC_CONFIG_FILES([Makefile])
-AC_OUTPUT
diff --git a/cpukit/configure.ac b/cpukit/configure.ac
index f1589a8..8436c91 100644
--- a/cpukit/configure.ac
+++ b/cpukit/configure.ac
@@ -388,8 +388,7 @@ AM_CONDITIONAL([RPCTOOLS],[test "$RPCGEN" = rpcgen \
# reloc backends
AC_MSG_CHECKING([whether CPU supports libdl])
case $RTEMS_CPU in
- arm | i386 | m32r | m68k | mips | \
- moxie | powerpc | sparc)
+ arm | i386 | m68k | mips | moxie | powerpc | sparc)
HAVE_LIBDL=yes ;;
# bfin has an issue to resolve with libdl. See ticket #2252
bfin)
@@ -463,7 +462,6 @@ score/cpu/i386/Makefile
score/cpu/lm32/Makefile
score/cpu/m68k/Makefile
score/cpu/m32c/Makefile
-score/cpu/m32r/Makefile
score/cpu/mips/Makefile
score/cpu/moxie/Makefile
score/cpu/nios2/Makefile
diff --git a/cpukit/libcsupport/src/newlibc_exit.c b/cpukit/libcsupport/src/newlibc_exit.c
index fad7f76..c093bb2 100644
--- a/cpukit/libcsupport/src/newlibc_exit.c
+++ b/cpukit/libcsupport/src/newlibc_exit.c
@@ -22,9 +22,7 @@
/* FIXME: These defines are a blatant hack */
#if defined(__USE_INIT_FINI__)
- #if defined(__m32r__)
- #define FINI_SYMBOL __fini
- #elif defined(__ARM_EABI__)
+ #if defined(__ARM_EABI__)
#define FINI_SYMBOL __libc_fini_array
#else
#define FINI_SYMBOL _fini
diff --git a/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h b/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h
deleted file mode 100644
index 3f531cf..0000000
--- a/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB
-
-#define ELF32_MACHDEP_ID_CASES \
- case EM_M32R: \
- break;
-
-#define ELF32_MACHDEP_ID EM_M32R
-
-#define ARCH_ELFSIZE 32
-
-#define R_M32R_NONE 0
-/*-----------OLD TYPE-------------*/
-#define R_M32R_16 1
-#define R_M32R_32 2
-#define R_M32R_24 3
-#define R_M32R_10_PCREL 4
-#define R_M32R_18_PCREL 5
-#define R_M32R_26_PCREL 6
-#define R_M32R_HI16_ULO 7
-#define R_M32R_HI16_SLO 8
-#define R_M32R_LO16 9
-#define R_M32R_SDA16 10
-#define R_M32R_GNU_VTINHERIT 11
-#define R_M32R_GNU_VTENTRY 12
-/*--------------------------------*/
-
-#define R_M32R_16_RELA 33
-#define R_M32R_32_RELA 34
-#define R_M32R_24_RELA 35
-#define R_M32R_18_PCREL_RELA 37
-#define R_M32R_26_PCREL_RELA 38
-#define R_M32R_HI16_ULO_RELA 39
-#define R_M32R_HI16_SLO_RELA 40
-#define R_M32R_LO16_RELA 41
-#define R_M32R_SDA16_RELA 42
-#define R_M32R_RELA_GNU_VTINHERIT 43
-#define R_M32R_RELA_GNU_VTENTRY 44
-
-#define R_TYPE(name) __CONCAT(R_M32R_,name)
diff --git a/cpukit/libdl/rtl-mdreloc-m32r.c b/cpukit/libdl/rtl-mdreloc-m32r.c
deleted file mode 100644
index 265e9cb..0000000
--- a/cpukit/libdl/rtl-mdreloc-m32r.c
+++ /dev/null
@@ -1,156 +0,0 @@
-#include <sys/cdefs.h>
-
-#include <errno.h>
-#include <stdio.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-#include <rtems/rtl/rtl.h>
-#include "rtl-elf.h"
-#include "rtl-error.h"
-#include "rtl-trace.h"
-
-static inline Elf_Addr
-load_ptr(void *where)
-{
- Elf_Addr res;
-
- memcpy(&res, where, sizeof(res));
-
- return (res);
-}
-
-static inline void
-store_ptr(void *where, Elf_Addr val)
-{
- memcpy(where, &val, sizeof(val));
-}
-
-bool
-rtems_rtl_elf_rel_resolve_sym (Elf_Word type)
-{
- return true;
-}
-
-bool
-rtems_rtl_elf_relocate_rela (const rtems_rtl_obj_t* obj,
- const Elf_Rela* rela,
- const rtems_rtl_obj_sect_t* sect,
- const char* symname,
- const Elf_Byte syminfo,
- const Elf_Word symvalue)
-{
-
- Elf_Addr *where;
- Elf_Word tmp;
-
- where = (Elf_Addr *)(sect->base + rela->r_offset);
- if (rtems_rtl_trace (RTEMS_RTL_TRACE_RELOC)) {
- printf("relocated address 0x%08lx\n", (Elf_Addr)where);
- }
-
- switch (ELF_R_TYPE(rela->r_info)) {
- case R_TYPE(NONE):
- break;
-
- case R_TYPE(16_RELA):
- /*
- * half16: S + A
- */
- *(uint16_t *)where = (symvalue + rela->r_addend) & 0xffff;
- break;
-
- case R_TYPE(24_RELA):
- /*
- * imm24: (S + A) & 0xFFFFFF
- */
- tmp = symvalue + rela->r_addend;
- if (((Elf_Sword)tmp > 0x7fffff) || ((Elf_Sword)tmp < -0x800000)) {
- printf("24_RELA Overflow\n");
- return false;
- }
- *where = (*where & 0xff000000) | (tmp & 0xffffff);
- break;
-
- case R_TYPE(32_RELA):
- /*
- * word32: S + A
- */
- *where += symvalue + rela->r_addend;
- break;
-
- case R_TYPE(26_PCREL_RELA):
- /*
- * disp24: ((S + A - P) >> 2) & 0xFFFFFF
- */
- tmp = symvalue + rela->r_addend - (Elf_Addr)where;
- tmp = (Elf_Sword)tmp >> 2;
- if (((Elf_Sword)tmp > 0x7fffff) || ((Elf_Sword)tmp < -0x800000)) {
- printf("26_PCREL_RELA Overflow\n");
- return false;
- }
-
- *where = (*where & 0xff000000) | (tmp & 0xffffff);
- break;
-
- case R_TYPE(18_PCREL_RELA):
- /*
- * disp16: ((S + A - P) >> 2) & 0xFFFFFF
- */
- tmp = symvalue + rela->r_addend - (Elf_Addr)where;
- tmp = (Elf_Sword)tmp >> 2;
- if (((Elf_Sword)tmp > 0x7fff) || ((Elf_Sword)tmp < -0x8000)) {
- printf("18_PCREL_RELA Overflow\n");
- return false;
- }
-
- *where = (*where & 0xffff0000) | (tmp & 0xffff);
- break;
-
- case R_TYPE(HI16_ULO_RELA):
- /*
- * imm16: ((S + A) >> 16)
- */
- tmp = *where;
- tmp += ((symvalue + rela->r_addend) >> 16) & 0xffff;
- *where = tmp;
- break;
-
- case R_TYPE(HI16_SLO_RELA):
- /*
- * imm16: ((S + A) >> 16) or ((S + A + 0x10000) >> 16)
- */
- tmp = symvalue + rela->r_addend;
- if (tmp & 0x8000) tmp += 0x10000;
- tmp = (tmp >> 16) & 0xffff;
- *where += tmp;
- break;
-
- case R_TYPE(LO16_RELA):
- /*
- * imm16: (S + A) & 0xFFFF
- */
- tmp = symvalue + rela->r_addend;
- *where = (*where & 0xffff0000) | (tmp & 0xffff);
- break;
-
- default:
- rtems_rtl_set_error (EINVAL, "rela type record not supported");
- printf("Unsupported rela reloc types\n");
- return false;
- }
- return true;
-}
-
-bool
-rtems_rtl_elf_relocate_rel (const rtems_rtl_obj_t* obj,
- const Elf_Rel* rel,
- const rtems_rtl_obj_sect_t* sect,
- const char* symname,
- const Elf_Byte syminfo,
- const Elf_Word symvalue)
-{
-
- rtems_rtl_set_error (EINVAL, "rel type record not supported");
- return true;
-}
diff --git a/cpukit/libdl/rtl-shell.c b/cpukit/libdl/rtl-shell.c
index 20a6aab..a10c931 100644
--- a/cpukit/libdl/rtl-shell.c
+++ b/cpukit/libdl/rtl-shell.c
@@ -25,7 +25,7 @@
* Flag the targets where off_t is 32 bits. This is not a compiler type
* so we can't rely on prerdefines.
*/
-#if defined(__m32r__) || defined(__moxie__)
+#if defined(__moxie__)
#define PRIdoff_t PRIo32
#else
#define PRIdoff_t PRIo64
diff --git a/cpukit/librpc/src/xdr/xdr_float.c b/cpukit/librpc/src/xdr/xdr_float.c
index ac8c46d..5d6b4ea 100644
--- a/cpukit/librpc/src/xdr/xdr_float.c
+++ b/cpukit/librpc/src/xdr/xdr_float.c
@@ -77,7 +77,6 @@ static char *rcsid = "$FreeBSD: src/lib/libc/xdr/xdr_float.c,v 1.7 1999/08/28 00
defined(__AVR__) || \
defined(__BFIN__) || \
defined(__m32c__) || \
- defined(__M32R__) || \
defined(__v850)
#include <rtems/endian.h>
diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am
index 7279d38..4438e3f 100644
--- a/cpukit/score/cpu/Makefile.am
+++ b/cpukit/score/cpu/Makefile.am
@@ -9,7 +9,6 @@ DIST_SUBDIRS += h8300
DIST_SUBDIRS += i386
DIST_SUBDIRS += lm32
DIST_SUBDIRS += m32c
-DIST_SUBDIRS += m32r
DIST_SUBDIRS += m68k
DIST_SUBDIRS += mips
DIST_SUBDIRS += moxie
diff --git a/cpukit/score/cpu/m32r/Makefile.am b/cpukit/score/cpu/m32r/Makefile.am
deleted file mode 100644
index dcf0871..0000000
--- a/cpukit/score/cpu/m32r/Makefile.am
+++ /dev/null
@@ -1,22 +0,0 @@
-include $(top_srcdir)/automake/compile.am
-
-include_HEADERS =
-
-include_rtemsdir = $(includedir)/rtems
-include_rtems_HEADERS = rtems/asm.h
-
-include_rtems_scoredir = $(includedir)/rtems/score
-include_rtems_score_HEADERS = rtems/score/cpu.h
-include_rtems_score_HEADERS += rtems/score/m32r.h
-include_rtems_score_HEADERS += rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += rtems/score/types.h
-include_rtems_score_HEADERS += rtems/score/cpuatomic.h
-
-noinst_LIBRARIES = libscorecpu.a
-libscorecpu_a_SOURCES = cpu.c cpu_asm.c context_switch.S context_init.c
-libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c
-libscorecpu_a_SOURCES += m32r-exception-frame-print.c
-libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
-
-include $(srcdir)/preinstall.am
-include $(top_srcdir)/automake/local.am
diff --git a/cpukit/score/cpu/m32r/context_init.c b/cpukit/score/cpu/m32r/context_init.c
deleted file mode 100644
index 90f582a..0000000
--- a/cpukit/score/cpu/m32r/context_init.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
- * @file
- *
- * @brief M32R CPU Context Initialize
- */
-
-/*
- * COPYRIGHT (c) 1989-2008.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <stdint.h>
-#include <rtems/system.h>
-
-typedef struct {
- uint32_t marker;
-} Starting_Frame;
-
-#define _get_r12( _r12 ) \
- __asm__ volatile( "mv r12, %0" : "=r" (_r12))
-
-void _CPU_Context_Initialize(
- Context_Control *the_context,
- uint32_t *stack_base,
- uint32_t size,
- uint32_t new_level,
- void *entry_point,
- bool is_fp,
- void *tls_area
-)
-{
- void *stackEnd = stack_base;
- Starting_Frame *frame;
- uint32_t r12;
-
- stackEnd += size;
-
- frame = (Starting_Frame *)stackEnd;
- frame--;
- frame->marker = 0xa5a5a5a5;
-
- _get_r12( r12 );
-
- the_context->r8 = 0x88888888;
- the_context->r9 = 0x99999999;
- the_context->r10 = 0xaaaaaaaa;
- the_context->r11 = 0xbbbbbbbb;
- the_context->r12 = r12;
- the_context->r13_fp = 0;
- the_context->r14_lr = (uintptr_t) entry_point;
- the_context->r15_sp = (uintptr_t) frame;
-
-}
diff --git a/cpukit/score/cpu/m32r/context_switch.S b/cpukit/score/cpu/m32r/context_switch.S
deleted file mode 100644
index 9f52090..0000000
--- a/cpukit/score/cpu/m32r/context_switch.S
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Context switch for the Reneas M32C
- *
- * COPYRIGHT (c) 1989-2008.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#define ARG_EXECUTING 8
-#define ARG_HEIR 12
-
-#define CONTEXT_R8 0x00
-#define CONTEXT_R9 0x04
-#define CONTEXT_R10 0x08
-#define CONTEXT_R11 0x0C
-#define CONTEXT_R12 0x10
-#define CONTEXT_R13_FP 0x14
-#define CONTEXT_R14_LR 0x18
-#define CONTEXT_R15_SP 0x1C
-#define CONTEXT_ACC_LOW 0x20
-#define CONTEXT_ACC_HIGH 0x24
-
- .file "context_switch.S"
- .text
- .global _CPU_Context_switch
- .type _CPU_Context_switch, @function
-_CPU_Context_switch:
- st r8, @(CONTEXT_R8,r0)
- st r9, @(CONTEXT_R9,r0)
- st r10, @(CONTEXT_R10,r0)
- st r11, @(CONTEXT_R11,r0)
- st r12, @(CONTEXT_R12,r0)
- st r13, @(CONTEXT_R13_FP,r0)
- st r14, @(CONTEXT_R14_LR,r0)
- st r15, @(CONTEXT_R15_SP,r0)
- mvfaclo r2
- st r2, @(CONTEXT_ACC_LOW,r0)
- mvfachi r2
- st r2, @(CONTEXT_ACC_HIGH,r0)
-
-restore:
- ld r8, @(CONTEXT_R8,r1)
- ld r9, @(CONTEXT_R9,r1)
- ld r10, @(CONTEXT_R10,r1)
- ld r11, @(CONTEXT_R11,r1)
- ld r12, @(CONTEXT_R12,r1)
- ld r13, @(CONTEXT_R13_FP,r1)
- ld r14, @(CONTEXT_R14_LR,r1)
- ld r15, @(CONTEXT_R15_SP,r1)
- ld r2, @(CONTEXT_ACC_LOW,r1)
- mvtaclo r2
- ld r2, @(CONTEXT_ACC_HIGH,r1)
- mvtachi r2
- jmp lr
-
- .global _CPU_Context_Restart_self
- .type _CPU_Context_Restart_self, @function
-_CPU_Context_Restart_self:
- mv r1, r0
- bra restore
diff --git a/cpukit/score/cpu/m32r/cpu.c b/cpukit/score/cpu/m32r/cpu.c
deleted file mode 100644
index 7bdf490..0000000
--- a/cpukit/score/cpu/m32r/cpu.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
- * @file
- *
- * @brief M32R CPU Support
- */
-
-/*
- * COPYRIGHT (c) 1989-2008.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtems/system.h>
-#include <rtems/score/isr.h>
-
-/* _CPU_Initialize
- *
- * This routine performs processor dependent initialization.
- *
- * INPUT PARAMETERS: NONE
- *
- * NO_CPU Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-
-void _CPU_Initialize(void)
-{
-}
-
-/*
- * This routine returns the current interrupt level.
- *
- * NO_CPU Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-
-uint32_t _CPU_ISR_Get_level( void )
-{
- return 0;
-}
-
-/*
- * _CPU_ISR_install_raw_handler
- *
- * NO_CPU Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-
-void _CPU_ISR_install_raw_handler(
- uint32_t vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-)
-{
- /*
- * This is where we install the interrupt handler into the "raw" interrupt
- * table used by the CPU to dispatch interrupt handlers.
- */
- /* _set_var_vect(new_handler,vector); */
-}
-
-/*
- * _CPU_ISR_install_vector
- *
- * This kernel routine installs the RTEMS handler for the
- * specified vector.
- *
- * Input parameters:
- * vector - interrupt vector number
- * old_handler - former ISR for this vector number
- * new_handler - replacement ISR for this vector number
- *
- * Output parameters: NONE
- *
- *
- * NO_CPU Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-
-void _CPU_ISR_install_vector(
- uint32_t vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-)
-{
- *old_handler = _ISR_Vector_table[ vector ];
-
- /*
- * If the interrupt vector table is a table of pointer to isr entry
- * points, then we need to install the appropriate RTEMS interrupt
- * handler for this vector number.
- */
-
- _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
-
- /*
- * We put the actual user ISR address in '_ISR_vector_table'. This will
- * be used by the _ISR_Handler so the user gets control.
- */
-
- _ISR_Vector_table[ vector ] = new_handler;
-}
-
-/*
- * _CPU_Install_interrupt_stack
- *
- * NO_CPU Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-
-void _CPU_Install_interrupt_stack( void )
-{
-}
diff --git a/cpukit/score/cpu/m32r/cpu_asm.c b/cpukit/score/cpu/m32r/cpu_asm.c
deleted file mode 100644
index f808f42..0000000
--- a/cpukit/score/cpu/m32r/cpu_asm.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * @file
- *
- * @brief M32R ISR Handler
- *
- * cpu_asm.c ===> cpu_asm.S or cpu_asm.s
- *
- * @note This is supposed to be a .S or .s file NOT a C file.
- *
- * M32R does not yet have interrupt support. When this functionality
- * is written, this file should become obsolete.
- *
- */
-
-/*
- * COPYRIGHT (c) 1989-2008.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtems/system.h>
-#include <rtems/score/cpu.h>
-
-/*
- * Prototypes
- */
-void _ISR_Handler(void);
-
-/* void __ISR_Handler()
- *
- * This routine provides the RTEMS interrupt management.
- *
- * NO_CPU Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-
-void _ISR_Handler(void)
-{
- /*
- * This discussion ignores a lot of the ugly details in a real
- * implementation such as saving enough registers/state to be
- * able to do something real. Keep in mind that the goal is
- * to invoke a user's ISR handler which is written in C and
- * uses a certain set of registers.
- *
- * Also note that the exact order is to a large extent flexible.
- * Hardware will dictate a sequence for a certain subset of
- * _ISR_Handler while requirements for setting
- */
-
- /*
- * At entry to "common" _ISR_Handler, the vector number must be
- * available. On some CPUs the hardware puts either the vector
- * number or the offset into the vector table for this ISR in a
- * known place. If the hardware does not give us this information,
- * then the assembly portion of RTEMS for this port will contain
- * a set of distinct interrupt entry points which somehow place
- * the vector number in a known place (which is safe if another
- * interrupt nests this one) and branches to _ISR_Handler.
- *
- * save some or all context on stack
- * may need to save some special interrupt information for exit
- *
- * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
- * if ( _ISR_Nest_level == 0 )
- * switch to software interrupt stack
- * #endif
- *
- * _ISR_Nest_level++;
- *
- * _Thread_Dispatch_disable_level++;
- *
- * (*_ISR_Vector_table[ vector ])( vector );
- *
- * _Thread_Dispatch_disable_level--;
- *
- * --_ISR_Nest_level;
- *
- * if ( _ISR_Nest_level )
- * goto the label "exit interrupt (simple case)"
- *
- * if ( _Thread_Dispatch_disable_level )
- * goto the label "exit interrupt (simple case)"
- *
- * if ( _Thread_Dispatch_necessary ) {
- * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
- * prepare to get out of interrupt
- * return from interrupt (maybe to _ISR_Dispatch)
- *
- * LABEL "exit interrupt (simple case):
- * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
- * if outermost interrupt
- * restore stack
- * #endif
- * prepare to get out of interrupt
- * return from interrupt
- */
-}
diff --git a/cpukit/score/cpu/m32r/m32r-exception-frame-print.c b/cpukit/score/cpu/m32r/m32r-exception-frame-print.c
deleted file mode 100644
index 71e7e1c..0000000
--- a/cpukit/score/cpu/m32r/m32r-exception-frame-print.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
- *
- * embedded brains GmbH
- * Obere Lagerstr. 30
- * 82178 Puchheim
- * Germany
- * <rtems at embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
- #include "config.h"
-#endif
-
-#include <rtems/score/cpu.h>
-
-void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
-{
- /* TODO */
-}
diff --git a/cpukit/score/cpu/m32r/preinstall.am b/cpukit/score/cpu/m32r/preinstall.am
deleted file mode 100644
index 3d76b74..0000000
--- a/cpukit/score/cpu/m32r/preinstall.am
+++ /dev/null
@@ -1,54 +0,0 @@
-## Automatically generated by ampolish3 - Do not edit
-
-if AMPOLISH3
-$(srcdir)/preinstall.am: Makefile.am
- $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
-endif
-
-PREINSTALL_DIRS =
-DISTCLEANFILES = $(PREINSTALL_DIRS)
-
-all-am: $(PREINSTALL_FILES)
-
-PREINSTALL_FILES =
-CLEANFILES = $(PREINSTALL_FILES)
-
-$(PROJECT_INCLUDE)/$(dirstamp):
- @$(MKDIR_P) $(PROJECT_INCLUDE)
- @: > $(PROJECT_INCLUDE)/$(dirstamp)
-PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
-
-$(PROJECT_INCLUDE)/rtems/$(dirstamp):
- @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
- @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
-PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
-
-$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
-
-$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
- @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
- @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
-PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
-
-$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
-
-$(PROJECT_INCLUDE)/rtems/score/m32r.h: rtems/score/m32r.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/m32r.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/m32r.h
-
-$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
-
-$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
-
-$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h
-
diff --git a/cpukit/score/cpu/m32r/rtems/asm.h b/cpukit/score/cpu/m32r/rtems/asm.h
deleted file mode 100644
index 11f5b87..0000000
--- a/cpukit/score/cpu/m32r/rtems/asm.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
- * @file
- *
- * @brief Address the Problems Caused by Incompatible Flavor of
- * Assemblers and Toolsets
- *
- * This include file attempts to address the problems
- * caused by incompatible flavors of assemblers and
- * toolsets. It primarily addresses variations in the
- * use of leading underscores on symbols and the requirement
- * that register names be preceded by a %.
- *
- * NOTE: The spacing in the use of these macros
- * is critical to them working as advertised.
- */
-
-/*
- * COPYRIGHT:
- *
- * This file is based on similar code found in newlib available
- * from ftp.cygnus.com. The file which was used had no copyright
- * notice. This file is freely distributable as long as the source
- * of the file is noted. This file is:
- *
- * COPYRIGHT (c) 1994-2006.
- * On-Line Applications Research Corporation (OAR).
- */
-
-#ifndef _RTEMS_ASM_H
-#define _RTEMS_ASM_H
-
-/*
- * Indicate we are in an assembly file and get the basic CPU definitions.
- */
-
-#ifndef ASM
-#define ASM
-#endif
-#include <rtems/score/cpuopts.h>
-#include <rtems/score/m32r.h>
-
-#ifndef __USER_LABEL_PREFIX__
-/**
- * Recent versions of GNU cpp define variables which indicate the
- * need for underscores and percents. If not using GNU cpp or
- * the version does not support this, then you will obviously
- * have to define these as appropriate.
- *
- * This symbol is prefixed to all C program symbols.
- */
-#define __USER_LABEL_PREFIX__ _
-#endif
-
-#ifndef __REGISTER_PREFIX__
-/**
- * Recent versions of GNU cpp define variables which indicate the
- * need for underscores and percents. If not using GNU cpp or
- * the version does not support this, then you will obviously
- * have to define these as appropriate.
- *
- * This symbol is prefixed to all register names.
- */
-#define __REGISTER_PREFIX__
-#endif
-
-#include <rtems/concat.h>
-
-/** Use the right prefix for global labels. */
-#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
-
-/** Use the right prefix for registers. */
-#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
-
-/*
- * define macros for all of the registers on this CPU
- *
- * EXAMPLE: #define d0 REG (d0)
- */
-
-/*
- * Define macros to handle section beginning and ends.
- */
-
-
-/** This macro is used to denote the beginning of a code declaration. */
-#define BEGIN_CODE_DCL .text
-/** This macro is used to denote the end of a code declaration. */
-#define END_CODE_DCL
-/** This macro is used to denote the beginning of a data declaration section. */
-#define BEGIN_DATA_DCL .data
-/** This macro is used to denote the end of a data declaration section. */
-#define END_DATA_DCL
-/** This macro is used to denote the beginning of a code section. */
-#define BEGIN_CODE .text
-/** This macro is used to denote the end of a code section. */
-#define END_CODE
-/** This macro is used to denote the beginning of a data section. */
-#define BEGIN_DATA
-/** This macro is used to denote the end of a data section. */
-#define END_DATA
-/**
- * This macro is used to denote the beginning of the
- * unitialized data section.
- */
-#define BEGIN_BSS
-/** This macro is used to denote the end of the unitialized data section. */
-#define END_BSS
-/** This macro is used to denote the end of the assembly file. */
-#define END
-
-/**
- * This macro is used to declare a public global symbol.
- *
- * NOTE: This must be tailored for a particular flavor of the C compiler.
- * They may need to put underscores in front of the symbols.
- */
-#define PUBLIC(sym) .globl SYM (sym)
-
-/**
- * This macro is used to prototype a public global symbol.
- *
- * NOTE: This must be tailored for a particular flavor of the C compiler.
- * They may need to put underscores in front of the symbols.
- */
-#define EXTERN(sym) .globl SYM (sym)
-
-#endif
diff --git a/cpukit/score/cpu/m32r/rtems/score/cpu.h b/cpukit/score/cpu/m32r/rtems/score/cpu.h
deleted file mode 100644
index 9ad41cd..0000000
--- a/cpukit/score/cpu/m32r/rtems/score/cpu.h
+++ /dev/null
@@ -1,1272 +0,0 @@
-/**
- * @file
- *
- * @brief Intel M32R CPU Dependent Source
- *
- * This include file contains information pertaining to the XXX
- * processor.
- *
- * NOTE: This file is part of a porting template that is intended
- * to be used as the starting point when porting RTEMS to a new
- * CPU family. The following needs to be done when using this as
- * the starting point for a new port:
- *
- * + Anywhere there is an XXX, it should be replaced
- * with information about the CPU family being ported to.
- *
- * + At the end of each comment section, there is a heading which
- * says "Port Specific Information:". When porting to RTEMS,
- * add CPU family specific information in this section
- */
-
-/*
- * COPYRIGHT (c) 1989-2008.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_CPU_H
-#define _RTEMS_SCORE_CPU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/types.h>
-#include <rtems/score/m32r.h>
-
-/* conditional compilation parameters */
-
-/**
- * Should the calls to @ref _Thread_Enable_dispatch be inlined?
- *
- * If TRUE, then they are inlined.
- * If FALSE, then a subroutine call is made.
- *
- * This conditional is an example of the classic trade-off of size
- * versus speed. Inlining the call (TRUE) typically increases the
- * size of RTEMS while speeding up the enabling of dispatching.
- *
- * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
- * only be 0 or 1 unless you are in an interrupt handler and that
- * interrupt handler invokes the executive.] When not inlined
- * something calls @ref _Thread_Enable_dispatch which in turns calls
- * @ref _Thread_Dispatch. If the enable dispatch is inlined, then
- * one subroutine call is avoided entirely.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_INLINE_ENABLE_DISPATCH FALSE
-
-/**
- * Does RTEMS manage a dedicated interrupt stack in software?
- *
- * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
- * If FALSE, nothing is done.
- *
- * If the CPU supports a dedicated interrupt stack in hardware,
- * then it is generally the responsibility of the BSP to allocate it
- * and set it up.
- *
- * If the CPU does not support a dedicated interrupt stack, then
- * the porter has two options: (1) execute interrupts on the
- * stack of the interrupted task, and (2) have RTEMS manage a dedicated
- * interrupt stack.
- *
- * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
-
-/**
- * Does the CPU follow the simple vectored interrupt model?
- *
- * If TRUE, then RTEMS allocates the vector table it internally manages.
- * If FALSE, then the BSP is assumed to allocate and manage the vector
- * table
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
-
-/**
- * Does this CPU have hardware support for a dedicated interrupt stack?
- *
- * If TRUE, then it must be installed during initialization.
- * If FALSE, then no installation is performed.
- *
- * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
-
-/**
- * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
- *
- * If TRUE, then the memory is allocated during initialization.
- * If FALSE, then the memory is allocated during initialization.
- *
- * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
-
-/**
- * Does the RTEMS invoke the user's ISR with the vector number and
- * a pointer to the saved interrupt frame (1) or just the vector
- * number (0)?
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_ISR_PASSES_FRAME_POINTER 0
-
-/**
- * @def CPU_HARDWARE_FP
- *
- * Does the CPU have hardware floating point?
- *
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
- *
- * If there is a FP coprocessor such as the i387 or mc68881, then
- * the answer is TRUE.
- *
- * The macro name "M32R_HAS_FPU" should be made CPU specific.
- * It indicates whether or not this CPU model has FP support. For
- * example, it would be possible to have an i386_nofp CPU model
- * which set this to false to indicate that you have an i386 without
- * an i387 and wish to leave floating point support out of RTEMS.
- */
-
-/**
- * @def CPU_SOFTWARE_FP
- *
- * Does the CPU have no hardware floating point and GCC provides a
- * software floating point implementation which must be context
- * switched?
- *
- * This feature conditional is used to indicate whether or not there
- * is software implemented floating point that must be context
- * switched. The determination of whether or not this applies
- * is very tool specific and the state saved/restored is also
- * compiler specific.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#if ( M32R_HAS_FPU == 1 )
-#define CPU_HARDWARE_FP TRUE
-#else
-#define CPU_HARDWARE_FP FALSE
-#endif
-#define CPU_SOFTWARE_FP FALSE
-
-/**
- * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
- *
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
- *
- * So far, the only CPUs in which this option has been used are the
- * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and
- * gcc both implicitly used the floating point registers to perform
- * integer multiplies. Similarly, the PowerPC port of gcc has been
- * seen to allocate floating point local variables and touch the FPU
- * even when the flow through a subroutine (like vfprintf()) might
- * not use floating point formats.
- *
- * If a function which you would not think utilize the FP unit DOES,
- * then one can not easily predict which tasks will use the FP hardware.
- * In this case, this option should be TRUE.
- *
- * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_ALL_TASKS_ARE_FP TRUE
-
-/**
- * Should the IDLE task have a floating point context?
- *
- * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- * and it has a floating point context which is switched in and out.
- * If FALSE, then the IDLE task does not have a floating point context.
- *
- * Setting this to TRUE negatively impacts the time required to preempt
- * the IDLE task from an interrupt because the floating point context
- * must be saved as part of the preemption.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_IDLE_TASK_IS_FP FALSE
-
-/**
- * Should the saving of the floating point registers be deferred
- * until a context switch is made to another different floating point
- * task?
- *
- * If TRUE, then the floating point context will not be stored until
- * necessary. It will remain in the floating point registers and not
- * disturned until another floating point task is switched to.
- *
- * If FALSE, then the floating point context is saved when a floating
- * point task is switched out and restored when the next floating point
- * task is restored. The state of the floating point registers between
- * those two operations is not specified.
- *
- * If the floating point context does NOT have to be saved as part of
- * interrupt dispatching, then it should be safe to set this to TRUE.
- *
- * Setting this flag to TRUE results in using a different algorithm
- * for deciding when to save and restore the floating point context.
- * The deferred FP switch algorithm minimizes the number of times
- * the FP context is saved and restored. The FP context is not saved
- * until a context switch is made to another, different FP task.
- * Thus in a system with only one FP task, the FP context will never
- * be saved or restored.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_USE_DEFERRED_FP_SWITCH TRUE
-
-/**
- * Does this port provide a CPU dependent IDLE task implementation?
- *
- * If TRUE, then the routine @ref _CPU_Thread_Idle_body
- * must be provided and is the default IDLE thread body instead of
- * @ref _CPU_Thread_Idle_body.
- *
- * If FALSE, then use the generic IDLE thread body if the BSP does
- * not provide one.
- *
- * This is intended to allow for supporting processors which have
- * a low power or idle mode. When the IDLE thread is executed, then
- * the CPU can be powered down.
- *
- * The order of precedence for selecting the IDLE thread body is:
- *
- * -# BSP provided
- * -# CPU dependent (if provided)
- * -# generic (if no BSP and no CPU dependent)
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
-
-/**
- * Does the stack grow up (toward higher addresses) or down
- * (toward lower addresses)?
- *
- * If TRUE, then the grows upward.
- * If FALSE, then the grows toward smaller addresses.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_STACK_GROWS_UP TRUE
-
-/**
- * The following is the variable attribute used to force alignment
- * of critical RTEMS structures. On some processors it may make
- * sense to have these aligned on tighter boundaries than
- * the minimum requirements of the compiler in order to have as
- * much of the critical data area as possible in a cache line.
- *
- * The placement of this macro in the declaration of the variables
- * is based on the syntactically requirements of the GNU C
- * "__attribute__" extension. For example with GNU C, use
- * the following to force a structures to a 32 byte boundary.
- *
- * __attribute__ ((aligned (32)))
- *
- * NOTE: Currently only the Priority Bit Map table uses this feature.
- * To benefit from using this, the data must be heavily
- * used so it will stay in the cache and used frequently enough
- * in the executive to justify turning this on.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_STRUCTURE_ALIGNMENT
-
-#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
-
-/**
- * @defgroup CPUEndian Processor Dependent Endianness Support
- *
- * This group assists in issues related to processor endianness.
- *
- */
-/**@{**/
-
-/**
- * Define what is required to specify how the network to host conversion
- * routines are handled.
- *
- * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
- * same values.
- *
- * @see CPU_LITTLE_ENDIAN
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_BIG_ENDIAN TRUE
-
-/**
- * Define what is required to specify how the network to host conversion
- * routines are handled.
- *
- * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
- * same values.
- *
- * @see CPU_BIG_ENDIAN
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_LITTLE_ENDIAN FALSE
-
-/** @} */
-
-/**
- * @ingroup CPUInterrupt
- * The following defines the number of bits actually used in the
- * interrupt field of the task mode. How those bits map to the
- * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_MODES_INTERRUPT_MASK 0x00000001
-
-#define CPU_PER_CPU_CONTROL_SIZE 0
-
-/*
- * Processor defined structures required for cpukit/score.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-
-/* may need to put some structures here. */
-
-typedef struct {
- /* There is no CPU specific per-CPU state */
-} CPU_Per_CPU_control;
-
-/**
- * @defgroup CPUContext Processor Dependent Context Management
- *
- * From the highest level viewpoint, there are 2 types of context to save.
- *
- * -# Interrupt registers to save
- * -# Task level registers to save
- *
- * Since RTEMS handles integer and floating point contexts separately, this
- * means we have the following 3 context items:
- *
- * -# task level context stuff:: Context_Control
- * -# floating point task stuff:: Context_Control_fp
- * -# special interrupt level context :: CPU_Interrupt_frame
- *
- * On some processors, it is cost-effective to save only the callee
- * preserved registers during a task context switch. This means
- * that the ISR code needs to save those registers which do not
- * persist across function calls. It is not mandatory to make this
- * distinctions between the caller/callee saves registers for the
- * purpose of minimizing context saved during task switch and on interrupts.
- * If the cost of saving extra registers is minimal, simplicity is the
- * choice. Save the same context on interrupt entry as for tasks in
- * this case.
- *
- * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- * care should be used in designing the context area.
- *
- * On some CPUs with hardware floating point support, the Context_Control_fp
- * structure will not be used or it simply consist of an array of a
- * fixed number of bytes. This is done when the floating point context
- * is dumped by a "FP save context" type instruction and the format
- * is not really defined by the CPU. In this case, there is no need
- * to figure out the exact format -- only the size. Of course, although
- * this is enough information for RTEMS, it is probably not enough for
- * a debugger such as gdb. But that is another problem.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-/**@{**/
-
-/**
- * This defines the minimal set of integer and processor state registers
- * that must be saved during a voluntary context switch from one thread
- * to another.
- */
-typedef struct {
- /** r8 -- temporary register */
- uint32_t r8;
- /** r9 -- temporary register */
- uint32_t r9;
- /** r10 -- temporary register */
- uint32_t r10;
- /** r11 -- temporary register */
- uint32_t r11;
- /** r12 -- may be global pointer */
- uint32_t r12;
- /** r13 -- frame pointer */
- uint32_t r13_fp;
- /** r14 -- link register (aka return pointer */
- uint32_t r14_lr;
- /** r15 -- stack pointer */
- uint32_t r15_sp;
- /** dsp accumulator low order 32-bits */
- uint32_t acc_low;
- /** dsp accumulator high order 32-bits */
- uint32_t acc_high;
-} Context_Control;
-
-/**
- * This macro returns the stack pointer associated with @a _context.
- *
- * @param[in] _context is the thread context area to access
- *
- * @return This method returns the stack pointer.
- */
-#define _CPU_Context_Get_SP( _context ) \
- (_context)->r15_sp
-
-/**
- * This defines the complete set of floating point registers that must
- * be saved during any context switch from one thread to another.
- */
-typedef struct {
- /** FPU registers are listed here */
- double some_float_register;
-} Context_Control_fp;
-
-/**
- * This defines the set of integer and processor state registers that must
- * be saved during an interrupt. This set does not include any which are
- * in @ref Context_Control.
- */
-typedef struct {
- /** This field is a hint that a port will have a number of integer
- * registers that need to be saved when an interrupt occurs or
- * when a context switch occurs at the end of an ISR.
- */
- uint32_t special_interrupt_register;
-} CPU_Interrupt_frame;
-
-/**
- * This variable is optional. It is used on CPUs on which it is difficult
- * to generate an "uninitialized" FP context. It is filled in by
- * @ref _CPU_Initialize and copied into the task's FP context area during
- * @ref _CPU_Context_Initialize.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
-
-/** @} */
-
-/**
- * @defgroup CPUInterrupt Processor Dependent Interrupt Management
- *
- * On some CPUs, RTEMS supports a software managed interrupt stack.
- * This stack is allocated by the Interrupt Manager and the switch
- * is performed in @ref _ISR_Handler. These variables contain pointers
- * to the lowest and highest addresses in the chunk of memory allocated
- * for the interrupt stack. Since it is unknown whether the stack
- * grows up or down (in general), this give the CPU dependent
- * code the option of picking the version it wants to use.
- *
- * NOTE: These two variables are required if the macro
- * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-/**@{**/
-
-/*
- * Nothing prevents the porter from declaring more CPU specific variables.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-
-/* XXX: if needed, put more variables here */
-
-/**
- * @ingroup CPUContext
- * The size of the floating point context area. On some CPUs this
- * will not be a "sizeof" because the format of the floating point
- * area is not defined -- only the size is. This is usually on
- * CPUs with a "floating point save context" instruction.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
-
-/**
- * Amount of extra stack (above minimum stack size) required by
- * MPCI receive server thread. Remember that in a multiprocessor
- * system this thread must exist and be able to process all directives.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
-
-/**
- * This defines the number of entries in the @ref _ISR_Vector_table managed
- * by RTEMS.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
-
-/**
- * This defines the highest interrupt vector number for this port.
- */
-#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
-
-/**
- * This is defined if the port has a special way to report the ISR nesting
- * level. Most ports maintain the variable @a _ISR_Nest_level.
- */
-#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
-
-/** @} */
-
-/**
- * @ingroup CPUContext
- * Should be large enough to run all RTEMS tests. This ensures
- * that a "reasonable" small application should not have any problems.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_STACK_MINIMUM_SIZE (1024)
-
-#define CPU_SIZEOF_POINTER 4
-
-/**
- * CPU's worst alignment requirement for data types on a byte boundary. This
- * alignment does not take into account the requirements for the stack.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_ALIGNMENT 8
-
-/**
- * This number corresponds to the byte alignment requirement for the
- * heap handler. This alignment requirement may be stricter than that
- * for the data types alignment specified by @ref CPU_ALIGNMENT. It is
- * common for the heap to follow the same alignment requirement as
- * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for
- * the heap, then this should be set to @ref CPU_ALIGNMENT.
- *
- * NOTE: This does not have to be a power of 2 although it should be
- * a multiple of 2 greater than or equal to 2. The requirement
- * to be a multiple of 2 is because the heap uses the least
- * significant field of the front and back flags to indicate
- * that a block is in use or free. So you do not want any odd
- * length blocks really putting length data in that bit.
- *
- * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
- * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
- * elements allocated from the heap meet all restrictions.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
-
-/**
- * This number corresponds to the byte alignment requirement for memory
- * buffers allocated by the partition manager. This alignment requirement
- * may be stricter than that for the data types alignment specified by
- * @ref CPU_ALIGNMENT. It is common for the partition to follow the same
- * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is
- * strict enough for the partition, then this should be set to
- * @ref CPU_ALIGNMENT.
- *
- * NOTE: This does not have to be a power of 2. It does have to
- * be greater or equal to than @ref CPU_ALIGNMENT.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
-
-/**
- * This number corresponds to the byte alignment requirement for the
- * stack. This alignment requirement may be stricter than that for the
- * data types alignment specified by @ref CPU_ALIGNMENT. If the
- * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
- * set to 0.
- *
- * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_STACK_ALIGNMENT 0
-
-/*
- * ISR handler macros
- */
-
-/**
- * @addtogroup CPUInterrupt
- */
-/**@{**/
-
-/**
- * Support routine to initialize the RTEMS vector table after it is allocated.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_Initialize_vectors()
-
-/**
- * Disable all interrupts for an RTEMS critical section. The previous
- * level is returned in @a _isr_cookie.
- *
- * @param[out] _isr_cookie will contain the previous level cookie
- *
- * Port Specific Information:
- *
- * TODO: As of 8 October 2014, this method is not implemented.
- */
-#define _CPU_ISR_Disable( _isr_cookie ) \
- do { \
- (_isr_cookie) = 0; \
- } while (0)
-
-/**
- * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- * This indicates the end of an RTEMS critical section. The parameter
- * @a _isr_cookie is not modified.
- *
- * @param[in] _isr_cookie contain the previous level cookie
- *
- * Port Specific Information:
- *
- * TODO: As of 8 October 2014, this method is not implemented.
- */
-#define _CPU_ISR_Enable( _isr_cookie ) \
- do { \
- (_isr_cookie) = (_isr_cookie); \
- } while (0)
-
-/**
- * This temporarily restores the interrupt to @a _isr_cookie before immediately
- * disabling them again. This is used to divide long RTEMS critical
- * sections into two or more parts. The parameter @a _isr_cookie is not
- * modified.
- *
- * @param[in] _isr_cookie contain the previous level cookie
- *
- * Port Specific Information:
- *
- * TODO: As of 8 October 2014, this method is not implemented.
- */
-#define _CPU_ISR_Flash( _isr_cookie ) \
- do { \
- _CPU_ISR_Enable( _isr_cookie ); \
- _CPU_ISR_Disable( _isr_cookie ); \
- } while (0)
-
-/**
- * This routine and @ref _CPU_ISR_Get_level
- * Map the interrupt level in task mode onto the hardware that the CPU
- * actually provides. Currently, interrupt levels which do not
- * map onto the CPU in a generic fashion are undefined. Someday,
- * it would be nice if these were "mapped" by the application
- * via a callout. For example, m68k has 8 levels 0 - 7, levels
- * 8 - 255 would be available for bsp/application specific meaning.
- * This could be used to manage a programmable interrupt controller
- * via the rtems_task_mode directive.
- *
- * Port Specific Information:
- *
- * TODO: As of 8 October 2014, this method is not implemented.
- */
-static inline void _CPU_ISR_Set_level( unsigned int new_level )
-{
-}
-
-/**
- * Return the current interrupt disable level for this task in
- * the format used by the interrupt level portion of the task mode.
- *
- * NOTE: This routine usually must be implemented as a subroutine.
- *
- * Port Specific Information:
- *
- * TODO: As of 8 October 2014, this method is not implemented.
- */
-uint32_t _CPU_ISR_Get_level( void );
-
-/* end of ISR handler macros */
-
-/** @} */
-
-/* Context handler macros */
-
-/**
- * @brief Initialize CPU context.
- *
- * @ingroup CPUContext
- * Initialize the context to a state suitable for starting a
- * task after a context restore operation. Generally, this
- * involves:
- *
- * - setting a starting address
- * - preparing the stack
- * - preparing the stack and frame pointers
- * - setting the proper interrupt level in the context
- * - initializing the floating point context
- *
- * This routine generally does not set any unnecessary register
- * in the context. The state of the "general data" registers is
- * undefined at task start time.
- *
- * @param[in] _the_context is the context structure to be initialized
- * @param[in] _stack_base is the lowest physical address of this task's stack
- * @param[in] _size is the size of this task's stack
- * @param[in] _isr is the interrupt disable level
- * @param[in] _entry_point is the thread's entry point. This is
- * always @a _Thread_Handler
- * @param[in] _is_fp is TRUE if the thread is to be a floating
- * point thread. This is typically only used on CPUs where the
- * FPU may be easily disabled by software such as on the SPARC
- * where the PSR contains an enable FPU bit.
- * @param[in] tls_area is the thread-local storage (TLS) area
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Context_Initialize(
- Context_Control *the_context,
- uint32_t *stack_base,
- size_t size,
- uint32_t new_level,
- void *entry_point,
- bool is_fp,
- void *tls_area
-);
-
-/**
- * This routine is responsible for somehow restarting the currently
- * executing task. If you are lucky, then all that is necessary
- * is restoring the context. Otherwise, there will need to be
- * a special assembly routine which does something special in this
- * case. For many ports, simply adding a label to the restore path
- * of @ref _CPU_Context_switch will work. On other ports, it may be
- * possibly to load a few arguments and jump to the restore path. It will
- * not work if restarting self conflicts with the stack frame
- * assumptions of restoring a context.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Context_Restart_self(
- Context_Control *the_context
-) RTEMS_NO_RETURN;
-
-/**
- * @ingroup CPUContext
- * The purpose of this macro is to allow the initial pointer into
- * a floating point context area (used to save the floating point
- * context) to be at an arbitrary place in the floating point
- * context area.
- *
- * This is necessary because some FP units are designed to have
- * their context saved as a stack which grows into lower addresses.
- * Other FP units can be saved by simply moving registers into offsets
- * from the base of the context area. Finally some FP units provide
- * a "dump context" instruction which could fill in from high to low
- * or low to high based on the whim of the CPU designers.
- *
- * @param[in] _base is the lowest physical address of the floating point
- * context area
- * @param[in] _offset is the offset into the floating point area
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_Context_Fp_start( _base, _offset ) \
- ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
-
-/**
- * This routine initializes the FP context area passed to it to.
- * There are a few standard ways in which to initialize the
- * floating point context. The code included for this macro assumes
- * that this is a CPU in which a "initial" FP context was saved into
- * @a _CPU_Null_fp_context and it simply copies it to the destination
- * context passed to it.
- *
- * Other floating point context save/restore models include:
- * -# not doing anything, and
- * -# putting a "null FP status word" in the correct place in the FP context.
- *
- * @param[in] _destination is the floating point context area
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_Context_Initialize_fp( _destination ) \
- { \
- *(*(_destination)) = _CPU_Null_fp_context; \
- }
-
-/* end of Context handler macros */
-
-/* Fatal Error manager macros */
-
-/**
- * This routine copies _error into a known place -- typically a stack
- * location or a register, optionally disables interrupts, and
- * halts/stops the CPU.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_Fatal_halt( _source, _error ) \
- { \
- }
-
-/* end of Fatal Error manager macros */
-
-/* Bitfield handler macros */
-
-/**
- * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
- *
- * This set of routines are used to implement fast searches for
- * the most important ready task.
- */
-/**@{**/
-
-/**
- * This definition is set to TRUE if the port uses the generic bitfield
- * manipulation implementation.
- */
-#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
-
-/**
- * This definition is set to TRUE if the port uses the data tables provided
- * by the generic bitfield manipulation implementation.
- * This can occur when actually using the generic bitfield manipulation
- * implementation or when implementing the same algorithm in assembly
- * language for improved performance. It is unlikely that a port will use
- * the data if it has a bitfield scan instruction.
- */
-#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
-
-/**
- * This routine sets @a _output to the bit number of the first bit
- * set in @a _value. @a _value is of CPU dependent type
- * @a Priority_bit_map_Word. This type may be either 16 or 32 bits
- * wide although only the 16 least significant bits will be used.
- *
- * There are a number of variables in using a "find first bit" type
- * instruction.
- *
- * -# What happens when run on a value of zero?
- * -# Bits may be numbered from MSB to LSB or vice-versa.
- * -# The numbering may be zero or one based.
- * -# The "find first bit" instruction may search from MSB or LSB.
- *
- * RTEMS guarantees that (1) will never happen so it is not a concern.
- * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
- * @ref _CPU_Priority_bits_index. These three form a set of routines
- * which must logically operate together. Bits in the _value are
- * set and cleared based on masks built by @ref _CPU_Priority_Mask.
- * The basic major and minor values calculated by @ref _Priority_Major
- * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
- * to properly range between the values returned by the "find first bit"
- * instruction. This makes it possible for @ref _Priority_Get_highest to
- * calculate the major and directly index into the minor table.
- * This mapping is necessary to ensure that 0 (a high priority major/minor)
- * is the first bit found.
- *
- * This entire "find first bit" and mapping process depends heavily
- * on the manner in which a priority is broken into a major and minor
- * components with the major being the 4 MSB of a priority and minor
- * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
- * to the lowest priority.
- *
- * If your CPU does not have a "find first bit" instruction, then
- * there are ways to make do without it. Here are a handful of ways
- * to implement this in software:
- *
- at verbatim
- - a series of 16 bit test instructions
- - a "binary search using if's"
- - _number = 0
- if _value > 0x00ff
- _value >>=8
- _number = 8;
-
- if _value > 0x0000f
- _value >=8
- _number += 4
-
- _number += bit_set_table[ _value ]
- at endverbatim
-
- * where bit_set_table[ 16 ] has values which indicate the first
- * bit set
- *
- * @param[in] _value is the value to be scanned
- * @param[in] _output is the first bit set
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- { \
- (_output) = 0; /* do something to prevent warnings */ \
- }
-#endif
-
-/* end of Bitfield handler macros */
-
-/**
- * This routine builds the mask which corresponds to the bit fields
- * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion
- * for that routine.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-
-#define _CPU_Priority_Mask( _bit_number ) \
- ( 1 << (_bit_number) )
-
-#endif
-
-/**
- * This routine translates the bit numbers returned by
- * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
- * a major or minor component of a priority. See the discussion
- * for that routine.
- *
- * @param[in] _priority is the major or minor number to translate
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-
-#define _CPU_Priority_bits_index( _priority ) \
- (_priority)
-
-#endif
-
-/* end of Priority handler macros */
-
-/** @} */
-
-/* functions */
-
-/**
- * @brief CPU initialization.
- *
- * This routine performs CPU dependent initialization.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Initialize(void);
-
-/**
- * @ingroup CPUInterrupt
- * This routine installs a "raw" interrupt handler directly into the
- * processor's vector table.
- *
- * @param[in] vector is the vector number
- * @param[in] new_handler is the raw ISR handler to install
- * @param[in] old_handler is the previously installed ISR Handler
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_ISR_install_raw_handler(
- uint32_t vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-/**
- * @ingroup CPUInterrupt
- * This routine installs an interrupt vector.
- *
- * @param[in] vector is the vector number
- * @param[in] new_handler is the RTEMS ISR handler to install
- * @param[in] old_handler is the previously installed ISR Handler
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_ISR_install_vector(
- uint32_t vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-/**
- * @ingroup CPUInterrupt
- * This routine installs the hardware interrupt stack pointer.
- *
- * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
- * is TRUE.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Install_interrupt_stack( void );
-
-/**
- * @ingroup CPUContext
- * This routine switches from the run context to the heir context.
- *
- * @param[in] run points to the context of the currently executing task
- * @param[in] heir points to the context of the heir task
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Context_switch(
- Context_Control *run,
- Context_Control *heir
-);
-
-/**
- * @addtogroup CPUContext
- */
-/**@{**/
-
-/**
- * This routine is generally used only to restart self in an
- * efficient manner. It may simply be a label in @ref _CPU_Context_switch.
- *
- * @param[in] new_context points to the context to be restored.
- *
- * NOTE: May be unnecessary to reload some registers.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Context_restore(
- Context_Control *new_context
-) RTEMS_NO_RETURN;
-
-/**
- * This routine saves the floating point context passed to it.
- *
- * @param[in] fp_context_ptr is a pointer to a pointer to a floating
- * point context area
- *
- * @return on output @a *fp_context_ptr will contain the address that
- * should be used with @ref _CPU_Context_restore_fp to restore this context.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Context_save_fp(
- Context_Control_fp **fp_context_ptr
-);
-
-/**
- * This routine restores the floating point context passed to it.
- *
- * @param[in] fp_context_ptr is a pointer to a pointer to a floating
- * point context area to restore
- *
- * @return on output @a *fp_context_ptr will contain the address that
- * should be used with @ref _CPU_Context_save_fp to save this context.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Context_restore_fp(
- Context_Control_fp **fp_context_ptr
-);
-
-static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
-{
- /* TODO */
-}
-
-static inline void _CPU_Context_validate( uintptr_t pattern )
-{
- while (1) {
- /* TODO */
- }
-}
-
-/** @} */
-
-/* FIXME */
-typedef CPU_Interrupt_frame CPU_Exception_frame;
-
-void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
-
-/**
- * @ingroup CPUEndian
- * The following routine swaps the endian format of an unsigned int.
- * It must be static because it is referenced indirectly.
- *
- * This version will work on any processor, but if there is a better
- * way for your CPU PLEASE use it. The most common way to do this is to:
- *
- * swap least significant two bytes with 16-bit rotate
- * swap upper and lower 16-bits
- * swap most significant two bytes with 16-bit rotate
- *
- * Some CPUs have special instructions which swap a 32-bit quantity in
- * a single instruction (e.g. i486). It is probably best to avoid
- * an "endian swapping control bit" in the CPU. One good reason is
- * that interrupts would probably have to be disabled to ensure that
- * an interrupt does not try to access the same "chunk" with the wrong
- * endian. Another good reason is that on some CPUs, the endian bit
- * endianness for ALL fetches -- both code and data -- so the code
- * will be fetched incorrectly.
- *
- * @param[in] value is the value to be swapped
- * @return the value after being endian swapped
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-static inline uint32_t CPU_swap_u32(
- uint32_t value
-)
-{
- uint32_t byte1, byte2, byte3, byte4, swapped;
-
- byte4 = (value >> 24) & 0xff;
- byte3 = (value >> 16) & 0xff;
- byte2 = (value >> 8) & 0xff;
- byte1 = value & 0xff;
-
- swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
- return swapped;
-}
-
-/**
- * @ingroup CPUEndian
- * This routine swaps a 16 bir quantity.
- *
- * @param[in] value is the value to be swapped
- * @return the value after being endian swapped
- */
-#define CPU_swap_u16( value ) \
- (((value&0xff) << 8) | ((value >> 8)&0xff))
-
-typedef uint32_t CPU_Counter_ticks;
-
-CPU_Counter_ticks _CPU_Counter_read( void );
-
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h b/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h
deleted file mode 100644
index ac6aac4..0000000
--- a/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/**
- * @file
- *
- * @brief Intel M32R Assembly File
- *
- * Very loose template for an include file for the cpu_asm.? file
- * if it is implemented as a ".S" file (preprocessed by cpp) instead
- * of a ".s" file (preprocessed by gm4 or gasp).
- */
-
-/*
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef _RTEMS_SCORE_CPU_ASM_H
-#define _RTEMS_SCORE_CPU_ASM_H
-
-/* pull in the generated offsets */
-
-#include <rtems/score/offsets.h>
-
-/*
- * Hardware General Registers
- */
-
-/* put something here */
-
-/*
- * Hardware Floating Point Registers
- */
-
-/* put something here */
-
-/*
- * Hardware Control Registers
- */
-
-/* put something here */
-
-/*
- * Calling Convention
- */
-
-/* put something here */
-
-/*
- * Temporary registers
- */
-
-/* put something here */
-
-/*
- * Floating Point Registers - SW Conventions
- */
-
-/* put something here */
-
-/*
- * Temporary floating point registers
- */
-
-/* put something here */
-
-#endif
-
-/* end of file */
diff --git a/cpukit/score/cpu/m32r/rtems/score/cpuatomic.h b/cpukit/score/cpu/m32r/rtems/score/cpuatomic.h
deleted file mode 100644
index 598ee76..0000000
--- a/cpukit/score/cpu/m32r/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/m32r/rtems/score/m32r.h b/cpukit/score/cpu/m32r/rtems/score/m32r.h
deleted file mode 100644
index cd91134..0000000
--- a/cpukit/score/cpu/m32r/rtems/score/m32r.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/**
- * @file
- *
- * @brief Set up Basic CPU Dependency Settings Based on Compiler Settings
- *
- * This file sets up basic CPU dependency settings based on
- * compiler settings. For example, it can determine if
- * floating point is available. This particular implementation
- * is specified to the NO CPU port.
- */
-
-/*
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_NO_CPU_H
-#define _RTEMS_SCORE_NO_CPU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * This file contains the information required to build
- * RTEMS for a particular member of the NO CPU family.
- * It does this by setting variables to indicate which
- * implementation dependent features are present in a particular
- * member of the family.
- *
- * This is a good place to list all the known CPU models
- * that this port supports and which RTEMS CPU model they correspond
- * to.
- */
-
-#if defined(rtems_multilib)
-/*
- * Figure out all CPU Model Feature Flags based upon compiler
- * predefines.
- */
-
-#define CPU_MODEL_NAME "rtems_multilib"
-#define NOCPU_HAS_FPU 1
-
-#elif defined(__m32r__)
-
-#define CPU_MODEL_NAME "m32r"
-#define NOCPU_HAS_FPU 1
-
-#else
-
-#error "Unsupported CPU Model"
-
-#endif
-
-/*
- * Define the name of the CPU family.
- */
-
-#define CPU_NAME "NO CPU"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _RTEMS_SCORE_NO_CPU_H */
diff --git a/cpukit/score/cpu/m32r/rtems/score/types.h b/cpukit/score/cpu/m32r/rtems/score/types.h
deleted file mode 100644
index 3ee57f2..0000000
--- a/cpukit/score/cpu/m32r/rtems/score/types.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/**
- * @file
- *
- * @brief Intel M32R CPU Type Definitions
- *
- * This include file contains type definitions pertaining to the Intel
- * m32r processor family.
- */
-
-/*
- * COPYRIGHT (c) 1989-2006.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_TYPES_H
-#define _RTEMS_SCORE_TYPES_H
-
-#include <rtems/score/basedefs.h>
-
-#ifndef ASM
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * This section defines the basic types for this processor.
- */
-
-/** Type that can store a 32-bit integer or a pointer. */
-typedef uintptr_t CPU_Uint32ptr;
-
-/** This defines the type for a priority bit map entry. */
-typedef uint16_t Priority_bit_map_Word;
-
-/** This defines the return type for an ISR entry point. */
-typedef void m32r_isr;
-
-/** This defines the prototype for an ISR entry point. */
-typedef m32r_isr ( *m32r_isr_entry )( void );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !ASM */
-
-#endif
diff --git a/cpukit/score/src/threadglobalconstruction.c b/cpukit/score/src/threadglobalconstruction.c
index 05a8613..c7c10d9 100644
--- a/cpukit/score/src/threadglobalconstruction.c
+++ b/cpukit/score/src/threadglobalconstruction.c
@@ -28,9 +28,7 @@
* initialization this target and compiler version uses.
*/
#if defined(__USE_INIT_FINI__)
- #if defined(__M32R__)
- #define INIT_NAME __init
- #elif defined(__ARM_EABI__)
+ #if defined(__ARM_EABI__)
#define INIT_NAME __libc_init_array
#else
#define INIT_NAME _init
diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am
index 06ebf48..f27cc6a 100644
--- a/doc/cpu_supplement/Makefile.am
+++ b/doc/cpu_supplement/Makefile.am
@@ -1,5 +1,5 @@
#
-# COPYRIGHT (c) 1988-2012.
+# COPYRIGHT (c) 1988-2015.
# On-Line Applications Research Corporation (OAR).
# All rights reserved.
@@ -20,7 +20,6 @@ GENERATED_FILES += h8300.texi
GENERATED_FILES += i386.texi
GENERATED_FILES += lm32.texi
GENERATED_FILES += m32c.texi
-GENERATED_FILES += m32r.texi
GENERATED_FILES += m68k.texi
GENERATED_FILES += microblaze.texi
GENERATED_FILES += mips.texi
@@ -83,11 +82,6 @@ m32c.texi: m32c.t
-u "Top" \
-n "" < $< > $@
-m32r.texi: m32r.t
- $(BMENU2) -p "" \
- -u "Top" \
- -n "" < $< > $@
-
lm32.texi: lm32.t
$(BMENU2) -p "" \
-u "Top" \
diff --git a/doc/cpu_supplement/cpu_supplement.texi b/doc/cpu_supplement/cpu_supplement.texi
index 105a54e..2fcdfa0 100644
--- a/doc/cpu_supplement/cpu_supplement.texi
+++ b/doc/cpu_supplement/cpu_supplement.texi
@@ -70,7 +70,6 @@
* Intel/AMD x86 Specific Information::
* Lattice Mico32 Specific Information::
* Renesas M32C Specific Information::
-* Renesas M32R Specific Information::
* M68xxx and Coldfire Specific Information::
* Xilinx MicroBlaze Specific Information::
* MIPS Specific Information::
@@ -95,7 +94,6 @@
@include i386.texi
@include lm32.texi
@include m32c.texi
- at include m32r.texi
@include m68k.texi
@include microblaze.texi
@include mips.texi
diff --git a/doc/cpu_supplement/m32r.t b/doc/cpu_supplement/m32r.t
deleted file mode 100644
index 951bf94..0000000
--- a/doc/cpu_supplement/m32r.t
+++ /dev/null
@@ -1,11 +0,0 @@
- at c Copyright (c) 2014 embedded brains GmbH. All rights reserved.
-
- at chapter Renesas M32R Specific Information
-
- at section Symmetric Multiprocessing
-
-SMP is not supported.
-
- at section Thread-Local Storage
-
-Thread-local storage is not implemented.
diff --git a/doc/user/preface.texi b/doc/user/preface.texi
index e47f18e..f8c0728 100644
--- a/doc/user/preface.texi
+++ b/doc/user/preface.texi
@@ -1,5 +1,5 @@
@c
- at c COPYRIGHT (c) 1989-2011.
+ at c COPYRIGHT (c) 1989-2015.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@@ -161,7 +161,6 @@ It has been ported to the following processor families:
@item Renesas (formerly Hitachi) SuperH
@item Renesas (formerly Hitachi) H8/300
@item Renesas M32C
- at item Renesas M32R
@item SPARC v7, v8, and V9
@end itemize
diff --git a/testsuites/libtests/configure.ac b/testsuites/libtests/configure.ac
index a34bbb2..4941c51 100644
--- a/testsuites/libtests/configure.ac
+++ b/testsuites/libtests/configure.ac
@@ -48,8 +48,7 @@ AM_CONDITIONAL(HAS_POSIX,test x"${rtems_cv_RTEMS_POSIX_API}" = x"yes")
# Must match the list in cpukit.
AC_MSG_CHECKING([whether CPU supports libdl])
case $RTEMS_CPU in
- arm | i386 | m32r | m68k | mips | \
- moxie | powerpc | sparc)
+ arm | i386 | m68k | mips | moxie | powerpc | sparc)
TEST_LIBDL=yes ;;
# bfin has an issue to resolve with libdl. See ticket #2252
bfin)
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