[rtems commit] or1k: Add functions for entire cache operations

Sebastian Huber sebh at rtems.org
Mon Nov 28 06:31:46 UTC 2016


Module:    rtems
Branch:    master
Commit:    e639c026b9bbe2d2faab37d61d52f63bebcfce38
Changeset: http://git.rtems.org/rtems/commit/?id=e639c026b9bbe2d2faab37d61d52f63bebcfce38

Author:    Martin Erik Werner <martinerikwerner.aac at gmail.com>
Date:      Fri Nov 25 19:21:40 2016 +0100

or1k: Add functions for entire cache operations

Add functions for flushing and invalidating whole cache.

Since we don't have system calls that can operate on anything more than
a single cache line, these simply retrieves the cache size and iterates
over the full size, invalidating each line.

The current implementation assumes that there's only one level of cache.

These changes were contributed by Antmicro under contract by Ã…AC
Microtec AB.

Close #2602

---

 c/src/lib/libcpu/or1k/shared/cache/cache.c | 45 ++++++++++++++++++++++++++++--
 1 file changed, 42 insertions(+), 3 deletions(-)

diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/c/src/lib/libcpu/or1k/shared/cache/cache.c
index 54728e1..88cda1a 100644
--- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
+++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
@@ -1,4 +1,8 @@
 /*
+ * COPYRIGHT (c) 2014 Ã…AC Microtec AB <www.aacmicrotec.com>
+ * Contributor(s):
+ *  Karol Gugala <kgugala at antmicro.com>
+ *
  * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary at gmail.com>
  *
  * COPYRIGHT (c) 1989-2006
@@ -14,6 +18,7 @@
 #include <rtems/score/or1k-utility.h>
 #include <rtems/score/percpu.h>
 #include <libcpu/cache.h>
+#include <cache_.h>
 
 static inline void _CPU_OR1K_Cache_enable_data(void)
 {
@@ -206,17 +211,51 @@ void _CPU_cache_unfreeze_instruction(void)
 
 void _CPU_cache_flush_entire_data(void)
 {
-
+  int addr;
+
+  /* We have only 0 level cache so we do not need to invalidate others */
+  for (
+      addr = _CPU_cache_get_data_cache_size(0);
+      addr > 0;
+      addr -= CPU_DATA_CACHE_ALIGNMENT
+  ) {
+    _CPU_OR1K_Cache_data_block_flush((uintptr_t) addr);
+  }
 }
 
 void _CPU_cache_invalidate_entire_data(void)
 {
-
+  int addr;
+
+  /* We have only 0 level cache so we do not need to invalidate others */
+  for (
+      addr = _CPU_cache_get_data_cache_size(0);
+      addr > 0;
+      addr -= CPU_DATA_CACHE_ALIGNMENT
+  ) {
+    _CPU_cache_invalidate_1_data_line((uintptr_t) addr);
+  }
 }
 
 void _CPU_cache_invalidate_entire_instruction(void)
 {
-
+  int addr;
+
+  /* We have only 0 level cache so we do not need to invalidate others */
+  for (
+      addr = _CPU_cache_get_instruction_cache_size(0);
+      addr > 0;
+      addr -= CPU_INSTRUCTION_CACHE_ALIGNMENT
+  ) {
+    _CPU_cache_invalidate_1_instruction_line((uintptr_t) addr);
+  }
+
+  /* Flush instructions out of instruction buffer */
+  __asm__ volatile("l.nop");
+  __asm__ volatile("l.nop");
+  __asm__ volatile("l.nop");
+  __asm__ volatile("l.nop");
+  __asm__ volatile("l.nop");
 }
 
 void _CPU_cache_enable_data(void)



More information about the vc mailing list