[rtems commit] powerpc, sparc, sparc64: Correct tables
Joel Sherrill
joel at rtems.org
Fri Oct 28 18:10:32 UTC 2016
Module: rtems
Branch: master
Commit: 0c978901d082c88a74f269ddf184438300c58213
Changeset: http://git.rtems.org/rtems/commit/?id=0c978901d082c88a74f269ddf184438300c58213
Author: Joel Sherrill <joel at rtems.org>
Date: Fri Oct 28 13:07:04 2016 -0500
powerpc, sparc, sparc64: Correct tables
---
cpu_supplement/powerpc.rst | 16 ++++++-------
cpu_supplement/sparc.rst | 55 +++++++++++++++++++-----------------------
cpu_supplement/sparc64.rst | 59 ++++++++++++++++++++--------------------------
3 files changed, 57 insertions(+), 73 deletions(-)
diff --git a/cpu_supplement/powerpc.rst b/cpu_supplement/powerpc.rst
index 5204ebc..3c5eb5c 100644
--- a/cpu_supplement/powerpc.rst
+++ b/cpu_supplement/powerpc.rst
@@ -373,14 +373,14 @@ architecture does not require the processor to generate alignment exceptions.
The following table lists the alignment requirements for a variety of data
accesses:
-+--------------+-----------------------+
-| Data Type | Alignment Requirement |
-+--------------+-----------------------+
-| byte | 1 |
-| half-word | 2 |
-| word | 4 |
-| doubleword | 8 |
-+--------------+-----------------------+
+============== ======================
+Data Type Alignment Requirement
+============== ======================
+byte 1
+half-word 2
+word 4
+doubleword 8
+============== ======================
Doubleword load and store operations are only available in PowerPC CPU models
which are sixty-four bit implementations.
diff --git a/cpu_supplement/sparc.rst b/cpu_supplement/sparc.rst
index 6b16bb6..f993cd8 100644
--- a/cpu_supplement/sparc.rst
+++ b/cpu_supplement/sparc.rst
@@ -236,34 +236,27 @@ architecturally defined role in the programming model which provides an
alternate name. The following table describes the mapping between the 32
registers and the register sets:
-+-----------------+----------------+------------------+
-| Register Number | Register Names | Description |
-+-----------------+----------------+------------------+
-| 0 - 7 | g0 - g7 | Global Registers |
-+-----------------+----------------+------------------+
-| 8 - 15 | o0 - o7 | Output Registers |
-+-----------------+----------------+------------------+
-| 16 - 23 | l0 - l7 | Local Registers |
-+-----------------+----------------+------------------+
-| 24 - 31 | i0 - i7 | Input Registers |
-+-----------------+----------------+------------------+
+================ ================ ===================
+Register Number Register Names Description
+================ ================ ===================
+0 - 7 g0 - g7 Global Registers
+8 - 15 o0 - o7 Output Registers
+16 - 23 l0 - l7 Local Registers
+24 - 31 i0 - i7 Input Registers
+================ ================ ===================
As mentioned above, some of the registers serve defined roles in the
programming model. The following table describes the role of each of these
registers:
-+---------------+----------------+----------------------+
-| Register Name | Alternate Name | Description |
-+---------------+----------------+----------------------+
-| g0 | na | reads return 0 |
-| | | writes are ignored |
-+---------------+----------------+----------------------+
-| o6 | sp | stack pointer |
-+---------------+----------------+----------------------+
-| i6 | fp | frame pointer |
-+---------------+----------------+----------------------+
-| i7 | na | return address |
-+---------------+----------------+----------------------+
+============== ================ ==================================
+Register Name Alternate Name Description
+============== ================ ==================================
+g0 na reads return 0, writes are ignored
+o6 sp stack pointer
+i6 fp frame pointer
+i7 na return address
+============== ================ ==================================
The registers g2 through g4 are reserved for applications. GCC uses them as
volatile registers by default. So they are treated like volatile registers in
@@ -483,14 +476,14 @@ endian fashion by the SPARC. Memory accesses which are not properly aligned
generate a "memory address not aligned" trap (type number 7). The following
table lists the alignment requirements for a variety of data accesses:
- +--------------+-----------------------+
- | Data Type | Alignment Requirement |
- +--------------+-----------------------+
- | byte | 1 |
- | half-word | 2 |
- | word | 4 |
- | doubleword | 8 |
- +--------------+-----------------------+
+============== ======================
+Data Type Alignment Requirement
+============== ======================
+byte 1
+half-word 2
+word 4
+doubleword 8
+============== ======================
Doubleword load and store operations must use a pair of registers as their
source or destination. This pair of registers must be an adjacent pair of
diff --git a/cpu_supplement/sparc64.rst b/cpu_supplement/sparc64.rst
index 4bc5427..f2785ff 100644
--- a/cpu_supplement/sparc64.rst
+++ b/cpu_supplement/sparc64.rst
@@ -143,34 +143,27 @@ architecturally defined role in the programming model which provides an
alternate name. The following table describes the mapping between the 32
registers and the register sets:
- +-----------------+----------------+------------------+
- | Register Number | Register Names | Description |
- +-----------------+----------------+------------------+
- | 0 - 7 | g0 - g7 | Global Registers |
- +-----------------+----------------+------------------+
- | 8 - 15 | o0 - o7 | Output Registers |
- +-----------------+----------------+------------------+
- | 16 - 23 | l0 - l7 | Local Registers |
- +-----------------+----------------+------------------+
- | 24 - 31 | i0 - i7 | Input Registers |
- +-----------------+----------------+------------------+
+================ ================ ===================
+Register Number Register Names Description
+================ ================ ===================
+0 - 7 g0 - g7 Global Registers
+8 - 15 o0 - o7 Output Registers
+16 - 23 l0 - l7 Local Registers
+24 - 31 i0 - i7 Input Registers
+================ ================ ===================
As mentioned above, some of the registers serve defined roles in the
programming model. The following table describes the role of each of these
registers:
- +---------------+----------------+----------------------+
- | Register Name | Alternate Name | Description |
- +---------------+----------------+----------------------+
- | g0 | na | reads return 0 |
- | | | writes are ignored |
- +---------------+----------------+----------------------+
- | o6 | sp | stack pointer |
- +---------------+----------------+----------------------+
- | i6 | fp | frame pointer |
- +---------------+----------------+----------------------+
- | i7 | na | return address |
- +---------------+----------------+----------------------+
+============== ================ ==================================
+Register Name Alternate Name Description
+============== ================ ==================================
+g0 na reads return 0, writes are ignored
+o6 sp stack pointer
+i6 fp frame pointer
+i7 na return address
+============== ================ ==================================
Floating Point Registers
~~~~~~~~~~~~~~~~~~~~~~~~
@@ -384,17 +377,15 @@ fashion by the SPARC. Memory accesses which are not properly aligned generate a
"memory address not aligned" trap (type number 0x34). The following table lists
the alignment requirements for a variety of data accesses:
-.. table::
-
- +--------------+-----------------------+
- | Data Type | Alignment Requirement |
- +--------------+-----------------------+
- | byte | 1 |
- | half-word | 2 |
- | word | 4 |
- | doubleword | 8 |
- | quadword | 16 |
- +--------------+-----------------------+
+============== ======================
+Data Type Alignment Requirement
+============== ======================
+byte 1
+half-word 2
+word 4
+doubleword 8
+quadword 16
+============== ======================
RTEMS currently does not support any SPARC Memory Management Units, therefore,
virtual memory or segmentation systems involving the SPARC are not supported.
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