[rtems commit] score: Enhance _SMP_barrier_Wait()

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    271690eb8838f2af30593584a87cb7595bdbdc6b
Changeset: http://git.rtems.org/rtems/commit/?id=271690eb8838f2af30593584a87cb7595bdbdc6b

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Tue Oct 11 14:42:55 2016 +0200

score: Enhance _SMP_barrier_Wait()

Indicate which processor released the barrier.  Similar to
pthread_barrier_wait().

---

 cpukit/score/include/rtems/score/smpbarrier.h | 5 ++++-
 cpukit/score/src/smpbarrierwait.c             | 8 +++++++-
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/cpukit/score/include/rtems/score/smpbarrier.h b/cpukit/score/include/rtems/score/smpbarrier.h
index 8225450..fddf7bb 100644
--- a/cpukit/score/include/rtems/score/smpbarrier.h
+++ b/cpukit/score/include/rtems/score/smpbarrier.h
@@ -106,8 +106,11 @@ static inline void _SMP_barrier_State_initialize(
  * @param[in, out] control The SMP barrier control.
  * @param[in, out] state The SMP barrier per-thread state.
  * @param[in] count The thread count bound to rendezvous.
+ *
+ * @retval true This processor performed the barrier release.
+ * @retval false Otherwise.
  */
-void _SMP_barrier_Wait(
+bool _SMP_barrier_Wait(
   SMP_barrier_Control *control,
   SMP_barrier_State *state,
   unsigned int count
diff --git a/cpukit/score/src/smpbarrierwait.c b/cpukit/score/src/smpbarrierwait.c
index 5a0de90..d06d819 100644
--- a/cpukit/score/src/smpbarrierwait.c
+++ b/cpukit/score/src/smpbarrierwait.c
@@ -18,7 +18,7 @@
 
 #include <rtems/score/smpbarrier.h>
 
-void _SMP_barrier_Wait(
+bool _SMP_barrier_Wait(
   SMP_barrier_Control *control,
   SMP_barrier_State *state,
   unsigned int count
@@ -26,6 +26,7 @@ void _SMP_barrier_Wait(
 {
   unsigned int sense = ~state->sense;
   unsigned int previous_value;
+  bool performed_release;
 
   state->sense = sense;
 
@@ -38,11 +39,16 @@ void _SMP_barrier_Wait(
   if ( previous_value + 1U == count ) {
     _Atomic_Store_uint( &control->value, 0U, ATOMIC_ORDER_RELAXED );
     _Atomic_Store_uint( &control->sense, sense, ATOMIC_ORDER_RELEASE );
+    performed_release = true;
   } else {
     while (
       _Atomic_Load_uint( &control->sense, ATOMIC_ORDER_ACQUIRE ) != sense
     ) {
       /* Wait */
     }
+
+    performed_release = false;
   }
+
+  return performed_release;
 }