[rtems commit] arm: Fix CPU context validation for Cortex-R4

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    b437a36064c9260ffb08e55a91a4812e59efa1c4
Changeset: http://git.rtems.org/rtems/commit/?id=b437a36064c9260ffb08e55a91a4812e59efa1c4

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Thu Mar  9 14:32:04 2017 +0100

arm: Fix CPU context validation for Cortex-R4

Do not touch the FPSCR[QC] bit since this is DNM/RAZ on Cortex-R4.

---

 cpukit/score/cpu/arm/arm-context-validate.S         | 6 +-----
 cpukit/score/cpu/arm/arm-context-volatile-clobber.S | 4 ++--
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/cpukit/score/cpu/arm/arm-context-validate.S b/cpukit/score/cpu/arm/arm-context-validate.S
index 5bb2e25..d735bc6 100644
--- a/cpukit/score/cpu/arm/arm-context-validate.S
+++ b/cpukit/score/cpu/arm/arm-context-validate.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013, 2017 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
  *  Dornierstr. 4
@@ -103,11 +103,7 @@ FUNCTION_ENTRY(_CPU_Context_validate)
 #ifdef ARM_MULTILIB_VFP
 	/* R3 contains the FPSCR */
 	vmrs	r3, FPSCR
-#ifdef ARM_MULTILIB_ARCH_V7M
 	ldr	r4, =0xf000001f
-#else
-	ldr	r4, =0xf800001f
-#endif
 	bic	r3, r3, r4
 	and	r4, r4, r0
 	orr	r3, r3, r4
diff --git a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
index b3c9d77..0b7e0f3 100644
--- a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
+++ b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013, 2017 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
  *  Dornierstr. 4
@@ -33,7 +33,7 @@ FUNCTION_ENTRY(_CPU_Context_volatile_clobber)
 
 #ifdef ARM_MULTILIB_VFP
 	vmrs	r1, FPSCR
-	ldr	r2, =0xf800001f
+	ldr	r2, =0xf000001f
 	bic	r1, r1, r2
 	and	r2, r2, r0
 	orr	r1, r1, r2