[rtems commit] bsp/t32mppc: Use fixed exception handlers
Sebastian Huber
sebh at rtems.org
Wed Nov 8 12:14:51 UTC 2017
Module: rtems
Branch: master
Commit: 7078a00b13ab90fb39d6504a3bbeacd48b894752
Changeset: http://git.rtems.org/rtems/commit/?id=7078a00b13ab90fb39d6504a3bbeacd48b894752
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Wed Nov 8 13:13:32 2017 +0100
bsp/t32mppc: Use fixed exception handlers
---
c/src/lib/libbsp/powerpc/t32mppc/Makefile.am | 3 +-
.../libbsp/powerpc/t32mppc/clock/clock-config.c | 64 ++++++++
c/src/lib/libbsp/powerpc/t32mppc/configure.ac | 8 +
c/src/lib/libbsp/powerpc/t32mppc/include/bsp.h | 6 +-
c/src/lib/libbsp/powerpc/t32mppc/include/irq.h | 23 ++-
c/src/lib/libbsp/powerpc/t32mppc/irq/irq.c | 15 +-
c/src/lib/libbsp/powerpc/t32mppc/start/start.S | 180 ++++++++++++---------
.../lib/libbsp/powerpc/t32mppc/startup/bspstart.c | 57 +++++--
8 files changed, 260 insertions(+), 96 deletions(-)
diff --git a/c/src/lib/libbsp/powerpc/t32mppc/Makefile.am b/c/src/lib/libbsp/powerpc/t32mppc/Makefile.am
index ebc6972..e37b740 100644
--- a/c/src/lib/libbsp/powerpc/t32mppc/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/t32mppc/Makefile.am
@@ -49,13 +49,14 @@ libbsp_a_SOURCES += \
../../shared/gnatinstallhandler.c \
../../shared/bspclean.c \
../../shared/bspgetworkarea.c \
+ ../shared/src/ppc-exc-handler-table.c \
../shared/src/tictac.c \
../shared/src/bsp-start-zero.S \
startup/bspstart.c \
startup/bspreset.c
# Clock
-libbsp_a_SOURCES += ../shared/clock/clock.c
+libbsp_a_SOURCES += clock/clock-config.c
# Timer
libbsp_a_SOURCES += ../../shared/timerstub.c
diff --git a/c/src/lib/libbsp/powerpc/t32mppc/clock/clock-config.c b/c/src/lib/libbsp/powerpc/t32mppc/clock/clock-config.c
new file mode 100644
index 0000000..7cdc37b
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/t32mppc/clock/clock-config.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2011, 2017 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Dornierstr. 4
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/timecounter.h>
+
+#include <libcpu/powerpc-utility.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+
+/* This is defined in clockdrv_shell.h */
+static rtems_isr Clock_isr(void *arg);
+
+static struct timecounter t32mppc_clock_tc;
+
+#define CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR
+
+void t32mppc_decrementer_dispatch(void)
+{
+ PPC_SET_SPECIAL_PURPOSE_REGISTER(BOOKE_TSR, BOOKE_TSR_DIS);
+ Clock_isr(NULL);
+}
+
+static uint32_t t32mppc_clock_get_timecount(struct timecounter *tc)
+{
+ return ppc_time_base();
+}
+
+static void t32mppc_clock_initialize(void)
+{
+ uint64_t frequency = bsp_time_base_frequency / 10;
+ uint32_t us_per_tick = rtems_configuration_get_microseconds_per_tick();
+ uint32_t interval = (uint32_t) ((frequency * us_per_tick) / 1000000);
+
+ PPC_SET_SPECIAL_PURPOSE_REGISTER(BOOKE_DECAR, interval - 1);
+ PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(
+ BOOKE_TCR,
+ BOOKE_TCR_DIE | BOOKE_TCR_ARE
+ );
+ ppc_set_decrementer_register(interval - 1);
+
+ t32mppc_clock_tc.tc_get_timecount = t32mppc_clock_get_timecount;
+ t32mppc_clock_tc.tc_counter_mask = 0xffffffff;
+ t32mppc_clock_tc.tc_frequency = bsp_time_base_frequency;
+ t32mppc_clock_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
+ rtems_timecounter_install(&t32mppc_clock_tc);
+}
+
+#define Clock_driver_support_initialize_hardware() \
+ t32mppc_clock_initialize()
+
+/* Include shared source clock driver code */
+#include "../../../shared/clockdrv_shell.h"
diff --git a/c/src/lib/libbsp/powerpc/t32mppc/configure.ac b/c/src/lib/libbsp/powerpc/t32mppc/configure.ac
index fce295e..ff50fe1 100644
--- a/c/src/lib/libbsp/powerpc/t32mppc/configure.ac
+++ b/c/src/lib/libbsp/powerpc/t32mppc/configure.ac
@@ -17,6 +17,14 @@ RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
+RTEMS_BSPOPTS_SET([PPC_EXC_CONFIG_USE_FIXED_HANDLER],[*],[1])
+RTEMS_BSPOPTS_HELP([PPC_EXC_CONFIG_USE_FIXED_HANDLER],
+[use fixed high-level exception handler])
+
+RTEMS_BSPOPTS_SET([PPC_EXC_CONFIG_BOOKE_ONLY],[*],[1])
+RTEMS_BSPOPTS_HELP([PPC_EXC_CONFIG_BOOKE_ONLY],
+[only support Book E exception types])
+
RTEMS_CHECK_SMP
AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
diff --git a/c/src/lib/libbsp/powerpc/t32mppc/include/bsp.h b/c/src/lib/libbsp/powerpc/t32mppc/include/bsp.h
index 53d92d2..c27f235 100644
--- a/c/src/lib/libbsp/powerpc/t32mppc/include/bsp.h
+++ b/c/src/lib/libbsp/powerpc/t32mppc/include/bsp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2014 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -29,6 +29,10 @@ extern "C" {
#define BSP_FEATURE_IRQ_EXTENSION
+extern uint32_t bsp_time_base_frequency;
+
+void t32mppc_decrementer_dispatch(void);
+
#endif /* ASM */
#ifdef __cplusplus
diff --git a/c/src/lib/libbsp/powerpc/t32mppc/include/irq.h b/c/src/lib/libbsp/powerpc/t32mppc/include/irq.h
index 4a01bf4..0053aa5 100644
--- a/c/src/lib/libbsp/powerpc/t32mppc/include/irq.h
+++ b/c/src/lib/libbsp/powerpc/t32mppc/include/irq.h
@@ -1,8 +1,8 @@
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
- * Obere Lagerstr. 30
+ * Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems at embedded-brains.de>
@@ -18,6 +18,7 @@
#include <rtems.h>
#include <rtems/irq.h>
#include <rtems/irq-extension.h>
+#include <rtems/score/processormask.h>
#ifdef __cplusplus
extern "C" {
@@ -26,6 +27,24 @@ extern "C" {
#define BSP_INTERRUPT_VECTOR_MIN 0
#define BSP_INTERRUPT_VECTOR_MAX 0
+RTEMS_INLINE_ROUTINE void bsp_interrupt_set_affinity(
+ rtems_vector_number vector,
+ const Processor_mask *affinity
+)
+{
+ (void) vector;
+ (void) affinity;
+}
+
+RTEMS_INLINE_ROUTINE void bsp_interrupt_get_affinity(
+ rtems_vector_number vector,
+ Processor_mask *affinity
+)
+{
+ (void) vector;
+ _Processor_mask_From_index( affinity, 0 );
+}
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/c/src/lib/libbsp/powerpc/t32mppc/irq/irq.c b/c/src/lib/libbsp/powerpc/t32mppc/irq/irq.c
index 0c98c3a..5b2c34d 100644
--- a/c/src/lib/libbsp/powerpc/t32mppc/irq/irq.c
+++ b/c/src/lib/libbsp/powerpc/t32mppc/irq/irq.c
@@ -1,8 +1,8 @@
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
- * Obere Lagerstr. 30
+ * Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems at embedded-brains.de>
@@ -12,13 +12,24 @@
* http://www.rtems.org/license/LICENSE.
*/
+#include <bsp.h>
#include <bsp/irq-generic.h>
+#include <bsp/vectors.h>
void bsp_interrupt_vector_enable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
}
+void bsp_interrupt_dispatch(uintptr_t exception_number)
+{
+ if (exception_number == 10) {
+ t32mppc_decrementer_dispatch();
+ } else {
+ bsp_interrupt_handler_default(0);
+ }
+}
+
void bsp_interrupt_vector_disable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
diff --git a/c/src/lib/libbsp/powerpc/t32mppc/start/start.S b/c/src/lib/libbsp/powerpc/t32mppc/start/start.S
index f491437..6e4df3c 100644
--- a/c/src/lib/libbsp/powerpc/t32mppc/start/start.S
+++ b/c/src/lib/libbsp/powerpc/t32mppc/start/start.S
@@ -95,86 +95,106 @@ copy:
.section ".bsp_start_text", "ax"
.align 4
bsp_exc_vector_base:
- stw r1, ppc_exc_lock_crit at sdarel(r13)
- stw r4, ppc_exc_vector_register_crit at sdarel(r13)
- li r4, -32767
- b ppc_exc_wrap_bookE_crit
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 2
- b ppc_exc_wrap_nopush_e500_mchk
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 3
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 4
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, -32763
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 6
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 7
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 8
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 12
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 24
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, -32752
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, -32749
- b ppc_exc_wrap_nopush_std
- stw r1, ppc_exc_lock_crit at sdarel(r13)
- stw r4, ppc_exc_vector_register_crit at sdarel(r13)
- li r4, -32748
- b ppc_exc_wrap_bookE_crit
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 18
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 17
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 13
- b ppc_exc_wrap_nopush_bookE_crit
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 10
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 25
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 26
- b ppc_exc_wrap_nopush_std
- stwu r1, -EXC_GENERIC_SIZE(r1)
- stw r4, GPR4_OFFSET(r1)
- li r4, 15
- b ppc_exc_wrap_nopush_std
+ /* Critical input */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 0
+ b ppc_exc_fatal_critical
+ /* Machine check */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 1
+ b ppc_exc_fatal_machine_check
+ /* Data storage */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 2
+ b ppc_exc_fatal_normal
+ /* Instruction storage */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 3
+ b ppc_exc_fatal_normal
+ /* External input */
+ PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 4
+ b ppc_exc_interrupt
+ /* Alignment */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 5
+ b ppc_exc_fatal_normal
+ /* Program */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 6
+ b ppc_exc_fatal_normal
+ /* Floating-point unavailable */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 7
+ b ppc_exc_fatal_normal
+ /* System call */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 8
+ b ppc_exc_fatal_normal
+ /* APU unavailable */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 9
+ b ppc_exc_fatal_normal
+ /* Decrementer */
+ PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 10
+ b ppc_exc_interrupt
+ /* Fixed-interval timer interrupt */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 11
+ b ppc_exc_fatal_normal
+ /* Watchdog timer interrupt */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 12
+ b ppc_exc_fatal_critical
+ /* Data TLB error */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 13
+ b ppc_exc_fatal_normal
+ /* Instruction TLB error */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 14
+ b ppc_exc_fatal_normal
+ /* Debug */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 15
+ b ppc_exc_fatal_debug
+ /* SPE APU unavailable or AltiVec unavailable */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 32
+ b ppc_exc_fatal_normal
+ /* SPE floating-point data exception or AltiVec assist */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 33
+ b ppc_exc_fatal_normal
+ /* SPE floating-point round exception */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 34
+ b ppc_exc_fatal_normal
+ /* Performance monitor */
+ PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
+ PPC_REG_STORE r3, GPR3_OFFSET(r1)
+ li r3, 35
+ b ppc_exc_fatal_normal
/* Start stack area */
.section ".bsp_rwextra", "aw", @nobits
diff --git a/c/src/lib/libbsp/powerpc/t32mppc/startup/bspstart.c b/c/src/lib/libbsp/powerpc/t32mppc/startup/bspstart.c
index 73d1d8c..f729ae6 100644
--- a/c/src/lib/libbsp/powerpc/t32mppc/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/t32mppc/startup/bspstart.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2014 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -31,7 +31,7 @@ LINKER_SYMBOL(bsp_exc_vector_base);
* equal. For now we simulate processor that issues 10000000 instructions per
* second.
*/
-uint32_t bsp_time_base_frequency = 10000000 / 10;
+uint32_t bsp_time_base_frequency = 10000000;
void BSP_panic(char *s)
{
@@ -61,6 +61,50 @@ void _BSP_Fatal_error(unsigned n)
}
}
+#define MTIVPR(base) \
+ __asm__ volatile ("mtivpr %0" : : "r" (base))
+
+#define VECTOR_TABLE_ENTRY_SIZE 16
+
+#define MTIVOR(vec, offset) \
+ do { \
+ __asm__ volatile ("mtspr " RTEMS_XSTRING(vec) ", %0" : : "r" (offset)); \
+ offset += VECTOR_TABLE_ENTRY_SIZE; \
+ } while (0)
+
+static void t32mppc_initialize_exceptions(void *interrupt_stack_begin)
+{
+ uintptr_t addr;
+
+ ppc_exc_initialize_interrupt_stack(
+ (uintptr_t) interrupt_stack_begin,
+ rtems_configuration_get_interrupt_stack_size()
+ );
+
+ addr = (uintptr_t) bsp_exc_vector_base;
+ MTIVPR(addr);
+ MTIVOR(BOOKE_IVOR0, addr);
+ MTIVOR(BOOKE_IVOR1, addr);
+ MTIVOR(BOOKE_IVOR2, addr);
+ MTIVOR(BOOKE_IVOR3, addr);
+ MTIVOR(BOOKE_IVOR4, addr);
+ MTIVOR(BOOKE_IVOR5, addr);
+ MTIVOR(BOOKE_IVOR6, addr);
+ MTIVOR(BOOKE_IVOR7, addr);
+ MTIVOR(BOOKE_IVOR8, addr);
+ MTIVOR(BOOKE_IVOR9, addr);
+ MTIVOR(BOOKE_IVOR10, addr);
+ MTIVOR(BOOKE_IVOR11, addr);
+ MTIVOR(BOOKE_IVOR12, addr);
+ MTIVOR(BOOKE_IVOR13, addr);
+ MTIVOR(BOOKE_IVOR14, addr);
+ MTIVOR(BOOKE_IVOR15, addr);
+ MTIVOR(BOOKE_IVOR32, addr);
+ MTIVOR(BOOKE_IVOR33, addr);
+ MTIVOR(BOOKE_IVOR34, addr);
+ MTIVOR(BOOKE_IVOR35, addr);
+}
+
void bsp_start(void)
{
get_ppc_cpu_type();
@@ -68,13 +112,6 @@ void bsp_start(void)
rtems_counter_initialize_converter(bsp_time_base_frequency);
- /* Initialize exception handler */
- ppc_exc_initialize_with_vector_base(
- (uintptr_t) bsp_section_work_begin,
- rtems_configuration_get_interrupt_stack_size(),
- bsp_exc_vector_base
- );
-
- /* Initalize interrupt support */
+ t32mppc_initialize_exceptions(bsp_section_work_begin);
bsp_interrupt_initialize();
}
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