[rtems commit] bsp/riscv: Initialize FPU depending on ISA

[Hesham Almatary]

On Wed, Aug 1, 2018 at 10:18 AM, Sebastian Huber <sebh at rtems.org> wrote:
> Module:    rtems
> Branch:    master
> Commit:    529154bad207a42a6d0f03343c7e215eab97ced5
> Changeset: http://git.rtems.org/rtems/commit/?id=529154bad207a42a6d0f03343c7e215eab97ced5
>
> Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
> Date:      Tue Jul 31 09:15:00 2018 +0200
>
> bsp/riscv: Initialize FPU depending on ISA
>
> Initialize fcsr to zero for a defined rounding mode.
>
> Update #3433.
>
> ---
>
>  bsps/riscv/riscv/start/start.S | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S
> index 290c95a..feb07fe 100644
> --- a/bsps/riscv/riscv/start/start.S
> +++ b/bsps/riscv/riscv/start/start.S
> @@ -48,9 +48,12 @@ SYM(_start):
>         LADDR   gp, __global_pointer$
>         .option pop
>
> -       /* Init FPU unit if it's there */
> +       /* Init FPU */
> +#ifdef __riscv_flen
>         li      t0, MSTATUS_FS
>         csrs    mstatus, t0
> +       csrw    fcsr, zero
> +#endif
Do you think it makes sense to check the MISA register for checking
the existence of an FPU unit or not?


>
>         /* Set exception handler */
>         LADDR   t0, _RISCV_Exception_handler
>
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-- 
Hesham