[rtems commit] ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    ba856559a4120a7f454aad30445508f0acc2a040
Changeset: http://git.rtems.org/rtems/commit/?id=ba856559a4120a7f454aad30445508f0acc2a040

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Fri Dec 21 10:16:02 2018 +0100

ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS

Remove this superfluous define.

Update #3667.

---

 bsps/arm/shared/cache/cache-cp15.c    | 3 +--
 bsps/arm/shared/cache/cache-cp15.h    | 1 -
 bsps/arm/shared/cache/cache-l2c-310.c | 3 +--
 3 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/bsps/arm/shared/cache/cache-cp15.c b/bsps/arm/shared/cache/cache-cp15.c
index 17de99e..4fb38c7 100644
--- a/bsps/arm/shared/cache/cache-cp15.c
+++ b/bsps/arm/shared/cache/cache-cp15.c
@@ -30,8 +30,7 @@
 #define CPU_MAXIMAL_CACHE_ALIGNMENT 64
 #endif
 
-#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
-          ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
+#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 
 
 static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
diff --git a/bsps/arm/shared/cache/cache-cp15.h b/bsps/arm/shared/cache/cache-cp15.h
index ff01384..1470c52 100644
--- a/bsps/arm/shared/cache/cache-cp15.h
+++ b/bsps/arm/shared/cache/cache-cp15.h
@@ -33,7 +33,6 @@ extern "C" {
 /* These two defines also ensure that the rtems_cache_* functions have bodies */
 #define ARM_CACHE_L1_CPU_DATA_ALIGNMENT 32
 #define ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT 32
-#define ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 
 #define ARM_CACHE_L1_CSS_ID_DATA \
           (ARM_CP15_CACHE_CSS_ID_DATA | ARM_CP15_CACHE_CSS_LEVEL(0))
diff --git a/bsps/arm/shared/cache/cache-l2c-310.c b/bsps/arm/shared/cache/cache-l2c-310.c
index 6869d20..e447aa0 100644
--- a/bsps/arm/shared/cache/cache-l2c-310.c
+++ b/bsps/arm/shared/cache/cache-l2c-310.c
@@ -68,8 +68,7 @@
 /* Some/many ARM Cortex-A cores have L1 data line length 64 bytes */
 #define CPU_MAXIMAL_CACHE_ALIGNMENT 64
 #endif
-#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
-  ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
+#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
 
 #define L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 )