[rtems commit] bsp/riscv: Fix vector table for lp64

Hesham Almatary heshamelmatary at gmail.com
Fri Jul 6 14:35:10 UTC 2018


On Fri, Jun 29, 2018 at 10:57 AM, Sebastian Huber <sebh at rtems.org> wrote:
> Module:    rtems
> Branch:    master
> Commit:    c558cc4b00f00b6746eec3a249a7a79995cea7cf
> Changeset: http://git.rtems.org/rtems/commit/?id=c558cc4b00f00b6746eec3a249a7a79995cea7cf
>
> Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
> Date:      Thu Jun 28 13:04:58 2018 +0200
>
> bsp/riscv: Fix vector table for lp64
>
> Update #3433.
>
> ---
>
>  bsps/riscv/riscv/start/start.S | 38 ++++++++++++++++++++++----------------
>  1 file changed, 22 insertions(+), 16 deletions(-)
>
> diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S
> index b59e55f..390459a 100644
> --- a/bsps/riscv/riscv/start/start.S
> +++ b/bsps/riscv/riscv/start/start.S
> @@ -104,22 +104,28 @@ SYM(_start):
>         .word   0xdeadbeef
>  #endif
>
> +#if __riscv_xlen == 32
> +#define ADDR .word
> +#elif __riscv_xlen == 64
> +#define ADDR .quad
Out of curirosity, why is it .quad and not .dword?
> +#endif
> +
>         .align  4
>  bsp_start_vector_table_begin:
> -       .word   _RISCV_Exception_default /* User int */
> -       .word   _RISCV_Exception_default /* Supervisor int */
> -       .word   _RISCV_Exception_default /* Reserved */
> -       .word   _RISCV_Exception_default /* Machine int */
> -       .word   _RISCV_Exception_default /* User timer int */
> -       .word   _RISCV_Exception_default /* Supervisor Timer int */
> -       .word   _RISCV_Exception_default /* Reserved */
> -       .word   _RISCV_Exception_default /* Machine Timer int */
> -       .word   _RISCV_Exception_default /* User external int */
> -       .word   _RISCV_Exception_default /* Supervisor external int */
> -       .word   _RISCV_Exception_default /* Reserved */
> -       .word   _RISCV_Exception_default /* Machine external int */
> -       .word   _RISCV_Exception_default
> -       .word   _RISCV_Exception_default
> -       .word   _RISCV_Exception_default
> -       .word   _RISCV_Exception_default
> +       ADDR    _RISCV_Exception_default /* User int */
> +       ADDR    _RISCV_Exception_default /* Supervisor int */
> +       ADDR    _RISCV_Exception_default /* Reserved */
> +       ADDR    _RISCV_Exception_default /* Machine int */
> +       ADDR    _RISCV_Exception_default /* User timer int */
> +       ADDR    _RISCV_Exception_default /* Supervisor Timer int */
> +       ADDR    _RISCV_Exception_default /* Reserved */
> +       ADDR    _RISCV_Exception_default /* Machine Timer int */
> +       ADDR    _RISCV_Exception_default /* User external int */
> +       ADDR    _RISCV_Exception_default /* Supervisor external int */
> +       ADDR    _RISCV_Exception_default /* Reserved */
> +       ADDR    _RISCV_Exception_default /* Machine external int */
> +       ADDR    _RISCV_Exception_default
> +       ADDR    _RISCV_Exception_default
> +       ADDR    _RISCV_Exception_default
> +       ADDR    _RISCV_Exception_default
>  bsp_start_vector_table_end:
>
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-- 
Hesham


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