[rtems commit] bsps/riscv_generic: Rename and add variants

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    92388f6941b75a43ae9f3db27402fc270536625c
Changeset: http://git.rtems.org/rtems/commit/?id=92388f6941b75a43ae9f3db27402fc270536625c

Author:    Hesham Almatary <Hesham.Almatary at cl.cam.ac.uk>
Date:      Mon May 28 12:14:12 2018 +0100

bsps/riscv_generic: Rename and add variants

Add BSP variants to match supported RISC-V ISA variants (multilibs).

---

 bsps/riscv/riscv_generic/config/{riscv_generic.cfg => rv32i.cfg}   | 2 +-
 bsps/riscv/riscv_generic/config/rv32iac.cfg                        | 7 +++++++
 bsps/riscv/riscv_generic/config/rv32im.cfg                         | 7 +++++++
 bsps/riscv/riscv_generic/config/rv32imac.cfg                       | 7 +++++++
 bsps/riscv/riscv_generic/config/rv32imafc.cfg                      | 7 +++++++
 .../riscv_generic/config/{riscv64_generic.cfg => rv64imac.cfg}     | 2 +-
 bsps/riscv/riscv_generic/config/rv64imafdc.cfg                     | 7 +++++++
 7 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/bsps/riscv/riscv_generic/config/riscv_generic.cfg b/bsps/riscv/riscv_generic/config/rv32i.cfg
similarity index 70%
rename from bsps/riscv/riscv_generic/config/riscv_generic.cfg
rename to bsps/riscv/riscv_generic/config/rv32i.cfg
index 785ac42..44a7416 100644
--- a/bsps/riscv/riscv_generic/config/riscv_generic.cfg
+++ b/bsps/riscv/riscv_generic/config/rv32i.cfg
@@ -2,6 +2,6 @@ include $(RTEMS_ROOT)/make/custom/default.cfg
 
 RTEMS_CPU = riscv
 
-CPU_CFLAGS =
+CPU_CFLAGS = -march=rv32i -mabi=ilp32
 
 CFLAGS_OPTIMIZE_V ?= -Os
diff --git a/bsps/riscv/riscv_generic/config/rv32iac.cfg b/bsps/riscv/riscv_generic/config/rv32iac.cfg
new file mode 100644
index 0000000..c321aef
--- /dev/null
+++ b/bsps/riscv/riscv_generic/config/rv32iac.cfg
@@ -0,0 +1,7 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = riscv
+
+CPU_CFLAGS = -march=rv32iac -mabi=ilp32
+
+CFLAGS_OPTIMIZE_V ?= -Os
diff --git a/bsps/riscv/riscv_generic/config/rv32im.cfg b/bsps/riscv/riscv_generic/config/rv32im.cfg
new file mode 100644
index 0000000..c4171ba
--- /dev/null
+++ b/bsps/riscv/riscv_generic/config/rv32im.cfg
@@ -0,0 +1,7 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = riscv
+
+CPU_CFLAGS = -march=rv32im -mabi=ilp32
+
+CFLAGS_OPTIMIZE_V ?= -Os
diff --git a/bsps/riscv/riscv_generic/config/rv32imac.cfg b/bsps/riscv/riscv_generic/config/rv32imac.cfg
new file mode 100644
index 0000000..644cadb
--- /dev/null
+++ b/bsps/riscv/riscv_generic/config/rv32imac.cfg
@@ -0,0 +1,7 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = riscv
+
+CPU_CFLAGS = -march=rv32imac -mabi=ilp32
+
+CFLAGS_OPTIMIZE_V ?= -Os
diff --git a/bsps/riscv/riscv_generic/config/rv32imafc.cfg b/bsps/riscv/riscv_generic/config/rv32imafc.cfg
new file mode 100644
index 0000000..2e24a2c
--- /dev/null
+++ b/bsps/riscv/riscv_generic/config/rv32imafc.cfg
@@ -0,0 +1,7 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = riscv
+
+CPU_CFLAGS = -march=rv32imafc -mabi=ilp32f
+
+CFLAGS_OPTIMIZE_V ?= -Os
diff --git a/bsps/riscv/riscv_generic/config/riscv64_generic.cfg b/bsps/riscv/riscv_generic/config/rv64imac.cfg
similarity index 70%
rename from bsps/riscv/riscv_generic/config/riscv64_generic.cfg
rename to bsps/riscv/riscv_generic/config/rv64imac.cfg
index 04897e5..e79bf27 100644
--- a/bsps/riscv/riscv_generic/config/riscv64_generic.cfg
+++ b/bsps/riscv/riscv_generic/config/rv64imac.cfg
@@ -2,6 +2,6 @@ include $(RTEMS_ROOT)/make/custom/default.cfg
 
 RTEMS_CPU = riscv
 
-CPU_CFLAGS = -mcmodel=medany
+CPU_CFLAGS = -march=rv64imac -mabi=lp64
 
 CFLAGS_OPTIMIZE_V ?= -O0 -g
diff --git a/bsps/riscv/riscv_generic/config/rv64imafdc.cfg b/bsps/riscv/riscv_generic/config/rv64imafdc.cfg
new file mode 100644
index 0000000..b167667
--- /dev/null
+++ b/bsps/riscv/riscv_generic/config/rv64imafdc.cfg
@@ -0,0 +1,7 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = riscv
+
+CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d
+
+CFLAGS_OPTIMIZE_V ?= -O0 -g