[rtems commit] riscv: Add TLS support

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    694e79a0b778e20b70c04e024ec43e76e563cc61
Changeset: http://git.rtems.org/rtems/commit/?id=694e79a0b778e20b70c04e024ec43e76e563cc61

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Thu Jun 28 08:20:47 2018 +0200

riscv: Add TLS support

Update #3433.

---

 cpukit/score/cpu/riscv/riscv-context-initialize.c | 8 ++++++++
 cpukit/score/cpu/riscv/riscv-context-switch.S     | 1 +
 2 files changed, 9 insertions(+)

diff --git a/cpukit/score/cpu/riscv/riscv-context-initialize.c b/cpukit/score/cpu/riscv/riscv-context-initialize.c
index d293e24..9f51d05 100644
--- a/cpukit/score/cpu/riscv/riscv-context-initialize.c
+++ b/cpukit/score/cpu/riscv/riscv-context-initialize.c
@@ -35,6 +35,7 @@
 
 #include <rtems/score/cpu.h>
 #include <rtems/score/address.h>
+#include <rtems/score/tls.h>
 
 void _CPU_Context_Initialize(
   Context_Control *context,
@@ -54,4 +55,11 @@ void _CPU_Context_Initialize(
   context->ra = (uintptr_t) entry_point;
   context->sp = (uintptr_t) stack;
   context->isr_dispatch_disable = 0;
+
+  if ( tls_area != NULL ) {
+    void *tls_block;
+
+    tls_block = _TLS_TCB_before_TLS_block_initialize( tls_area );
+    context->tp = (uintptr_t) tls_block;
+  }
 }
diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S
index 1b82e2a..3626155 100644
--- a/cpukit/score/cpu/riscv/riscv-context-switch.S
+++ b/cpukit/score/cpu/riscv/riscv-context-switch.S
@@ -67,6 +67,7 @@ SYM(_CPU_Context_switch):
 
 	LREG	ra, RISCV_CONTEXT_RA(a1)
 	LREG	sp, RISCV_CONTEXT_SP(a1)
+	LREG	tp, RISCV_CONTEXT_TP(a1)
 	LREG	s0, RISCV_CONTEXT_S0(a1)
 	LREG	s1, RISCV_CONTEXT_S1(a1)
 	LREG	s2, RISCV_CONTEXT_S2(a1)