[rtems commit] riscv: Remove mstatus from thread context

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    b706b4a3c09184b2f8ebf5290dc2b1d4a4db6684
Changeset: http://git.rtems.org/rtems/commit/?id=b706b4a3c09184b2f8ebf5290dc2b1d4a4db6684

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Wed Jun 27 08:54:13 2018 +0200

riscv: Remove mstatus from thread context

The mstatus register contains no thread-specific state which must be
saved/restored during a context switch.  Machine interrupts (MIE) must
be enabled during a context switch.

Create separate CPU_Interrupt_frame structure.

Update #3433.

---

 cpukit/score/cpu/riscv/include/rtems/score/cpu.h     | 10 +++-------
 cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 15 +++++++++++----
 cpukit/score/cpu/riscv/riscv-context-initialize.c    |  4 ----
 cpukit/score/cpu/riscv/riscv-context-switch.S        | 12 ------------
 4 files changed, 14 insertions(+), 27 deletions(-)

diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index 9a628c04..8821c0e 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -47,7 +47,9 @@ extern "C" {
 
 #define CPU_INLINE_ENABLE_DISPATCH       FALSE
 #define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
-#define CPU_ISR_PASSES_FRAME_POINTER 1
+
+#define CPU_ISR_PASSES_FRAME_POINTER FALSE
+
 #define CPU_HARDWARE_FP                  FALSE
 #define CPU_SOFTWARE_FP                  FALSE
 #define CPU_ALL_TASKS_ARE_FP             FALSE
@@ -72,10 +74,6 @@ typedef struct {
   /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/
   unsigned long x[32];
 
-  /* Special purpose registers */
-  unsigned long mstatus;
-  unsigned long mcause;
-  unsigned long mepc;
   uint32_t isr_dispatch_disable;
 #ifdef RTEMS_SMP
   volatile bool is_executing;
@@ -90,8 +88,6 @@ typedef struct {
   double  some_float_register;
 } Context_Control_fp;
 
-typedef Context_Control CPU_Interrupt_frame;
-
 #define CPU_CONTEXT_FP_SIZE  0
 Context_Control_fp  _CPU_Null_fp_context;
 
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
index 6279c7c..4952e29 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
@@ -38,15 +38,15 @@
 
 #if __riscv_xlen == 32
 
-#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 140
+#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 128
 
-#define CPU_INTERRUPT_FRAME_SIZE 144
+#define CPU_INTERRUPT_FRAME_SIZE 140
 
 #elif __riscv_xlen == 64
 
-#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 280
+#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 256
 
-#define CPU_INTERRUPT_FRAME_SIZE 288
+#define CPU_INTERRUPT_FRAME_SIZE 280
 
 #endif /* __riscv_xlen */
 
@@ -56,6 +56,13 @@
 extern "C" {
 #endif
 
+typedef struct {
+  unsigned long x[32];
+  unsigned long mstatus;
+  unsigned long mcause;
+  unsigned long mepc;
+} CPU_Interrupt_frame;
+
 #ifdef RTEMS_SMP
 
 static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void )
diff --git a/cpukit/score/cpu/riscv/riscv-context-initialize.c b/cpukit/score/cpu/riscv/riscv-context-initialize.c
index 7baf066..0dce495 100644
--- a/cpukit/score/cpu/riscv/riscv-context-initialize.c
+++ b/cpukit/score/cpu/riscv/riscv-context-initialize.c
@@ -35,7 +35,6 @@
 
 #include <rtems/score/cpu.h>
 #include <rtems/score/address.h>
-#include <rtems/score/riscv-utility.h>
 
 void _CPU_Context_Initialize(
   Context_Control *context,
@@ -59,7 +58,4 @@ void _CPU_Context_Initialize(
   context->x[1] = (uintptr_t) entry_point;
 
   context->isr_dispatch_disable = 0;
-
-  /* Enable interrupts and FP */
-  context->mstatus = MSTATUS_FS | MSTATUS_MIE;
 }
diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S
index 54adc6d..b6de9e6 100644
--- a/cpukit/score/cpu/riscv/riscv-context-switch.S
+++ b/cpukit/score/cpu/riscv/riscv-context-switch.S
@@ -45,12 +45,6 @@ SYM(_CPU_Context_switch):
 	GET_SELF_CPU_CONTROL	a2
 	lw	a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
 
-	/* Disable interrupts and store all registers */
-	csrr	t0, mstatus
-	SREG	t0, (32 * CPU_SIZEOF_POINTER)(a0)
-
-	csrci	mstatus, RISCV_MSTATUS_MIE
-
 	SREG	x1, (1 * CPU_SIZEOF_POINTER)(a0)
 	SREG	x2, (2 * CPU_SIZEOF_POINTER)(a0)
 	SREG	x4, (4 * CPU_SIZEOF_POINTER)(a0)
@@ -119,12 +113,6 @@ SYM(_CPU_Context_switch):
 	LREG	x29, (29 * CPU_SIZEOF_POINTER)(a1)
 	LREG	x30, (30 * CPU_SIZEOF_POINTER)(a1)
 
-	/* Load mstatus */
-	LREG	x31, (32 * CPU_SIZEOF_POINTER)(a1)
-	csrw	mstatus, x31
-
-	LREG	x30, (30 * CPU_SIZEOF_POINTER)(a1)
-
 	LREG	x11, (11 * CPU_SIZEOF_POINTER)(a1)
 
 	ret