[rtems commit] bsps/arm: Support GIC group 0/1

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    e33be09cfbf549228fea16f4421b277bfb9ae7dc
Changeset: http://git.rtems.org/rtems/commit/?id=e33be09cfbf549228fea16f4421b277bfb9ae7dc

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Wed Feb 27 15:10:53 2019 +0100

bsps/arm: Support GIC group 0/1

---

 bsps/arm/include/bsp/arm-gic-irq.h  | 12 +++++++++++-
 bsps/arm/include/bsp/arm-gic-regs.h |  9 +++++++--
 bsps/arm/include/bsp/arm-gic.h      | 37 +++++++++++++++++++++++++++++++++++-
 bsps/arm/shared/irq/irq-gic.c       | 38 ++++++++++++++++++++++++++++++++++++-
 4 files changed, 91 insertions(+), 5 deletions(-)

diff --git a/bsps/arm/include/bsp/arm-gic-irq.h b/bsps/arm/include/bsp/arm-gic-irq.h
index 09d3fe5..fa0d63d 100644
--- a/bsps/arm/include/bsp/arm-gic-irq.h
+++ b/bsps/arm/include/bsp/arm-gic-irq.h
@@ -7,7 +7,7 @@
  */
 
 /*
- * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013, 2019 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
  *  Dornierstr. 4
@@ -59,6 +59,16 @@ rtems_status_code arm_gic_irq_get_priority(
   uint8_t *priority
 );
 
+rtems_status_code arm_gic_irq_set_group(
+  rtems_vector_number vector,
+  gic_group group
+);
+
+rtems_status_code arm_gic_irq_get_group(
+  rtems_vector_number vector,
+  gic_group *group
+);
+
 void bsp_interrupt_set_affinity(
   rtems_vector_number vector,
   const Processor_mask *affinity
diff --git a/bsps/arm/include/bsp/arm-gic-regs.h b/bsps/arm/include/bsp/arm-gic-regs.h
index 2375b5c..5eeb98c 100644
--- a/bsps/arm/include/bsp/arm-gic-regs.h
+++ b/bsps/arm/include/bsp/arm-gic-regs.h
@@ -7,7 +7,7 @@
  */
 
 /*
- * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013, 2019 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
  *  Dornierstr. 4
@@ -27,6 +27,10 @@
 
 typedef struct {
   uint32_t iccicr;
+#define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4)
+#define GIC_CPUIF_ICCICR_FIQ_EN BSP_BIT32(3)
+#define GIC_CPUIF_ICCICR_ACK_CTL BSP_BIT32(2)
+#define GIC_CPUIF_ICCICR_ENABLE_GRP_1 BSP_BIT32(1)
 #define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0)
   uint32_t iccpmr;
 #define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7)
@@ -83,6 +87,7 @@ typedef struct {
 
 typedef struct {
   uint32_t icddcr;
+#define GIC_DIST_ICDDCR_ENABLE_GRP_1 BSP_BIT32(1)
 #define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0)
   uint32_t icdictr;
 #define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15)
@@ -109,7 +114,7 @@ typedef struct {
 #define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
 #define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
   uint32_t reserved_0c[29];
-  uint32_t icdisr[32];
+  uint32_t icdigr[32];
   uint32_t icdiser[32];
   uint32_t icdicer[32];
   uint32_t icdispr[32];
diff --git a/bsps/arm/include/bsp/arm-gic.h b/bsps/arm/include/bsp/arm-gic.h
index ab58409..2abbea5 100644
--- a/bsps/arm/include/bsp/arm-gic.h
+++ b/bsps/arm/include/bsp/arm-gic.h
@@ -7,7 +7,7 @@
  */
 
 /*
- * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013, 2019 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
  *  Dornierstr. 4
@@ -101,6 +101,41 @@ static inline bool gic_id_is_active(volatile gic_dist *dist, uint32_t id)
   return (dist->icdabr[i] & bit) != 0;
 }
 
+typedef enum {
+  GIC_GROUP_0,
+  GIC_GROUP_1
+} gic_group;
+
+static inline gic_group gic_id_get_group(
+  volatile gic_dist *dist,
+  uint32_t id
+)
+{
+  uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id);
+  uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id);
+
+  return (dist->icdigr[i] & bit) != 0 ?  GIC_GROUP_1 : GIC_GROUP_0;
+}
+
+static inline void gic_id_set_group(
+  volatile gic_dist *dist,
+  uint32_t id,
+  gic_group group
+)
+{
+  uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id);
+  uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id);
+  uint32_t icdigr = dist->icdigr[i];
+
+  icdigr &= ~bit;
+
+  if (group == GIC_GROUP_1) {
+    icdigr |= bit;
+  }
+
+  dist->icdigr[i] = icdigr;
+}
+
 static inline void gic_id_set_priority(
   volatile gic_dist *dist,
   uint32_t id,
diff --git a/bsps/arm/shared/irq/irq-gic.c b/bsps/arm/shared/irq/irq-gic.c
index ea4b6ef..6f525b7 100644
--- a/bsps/arm/shared/irq/irq-gic.c
+++ b/bsps/arm/shared/irq/irq-gic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013, 2019 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
  *  Dornierstr. 4
@@ -157,6 +157,42 @@ rtems_status_code arm_gic_irq_get_priority(
   return sc;
 }
 
+rtems_status_code arm_gic_irq_set_group(
+  rtems_vector_number vector,
+  gic_group group
+)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  if (bsp_interrupt_is_valid_vector(vector)) {
+    volatile gic_dist *dist = ARM_GIC_DIST;
+
+    gic_id_set_group(dist, vector, group);
+  } else {
+    sc = RTEMS_INVALID_ID;
+  }
+
+  return sc;
+}
+
+rtems_status_code arm_gic_irq_get_group(
+  rtems_vector_number vector,
+  gic_group *group
+)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  if (bsp_interrupt_is_valid_vector(vector)) {
+    volatile gic_dist *dist = ARM_GIC_DIST;
+
+    *group = gic_id_get_group(dist, vector);
+  } else {
+    sc = RTEMS_INVALID_ID;
+  }
+
+  return sc;
+}
+
 void bsp_interrupt_set_affinity(
   rtems_vector_number vector,
   const Processor_mask *affinity