[rtems commit] riscv: Fix misaligned access in context validate

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    9399473cb83985fd222e299e4581a232f5d35028
Changeset: http://git.rtems.org/rtems/commit/?id=9399473cb83985fd222e299e4581a232f5d35028

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Sat Feb  2 11:03:13 2019 +0100

riscv: Fix misaligned access in context validate

---

 cpukit/score/cpu/riscv/riscv-context-validate.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cpukit/score/cpu/riscv/riscv-context-validate.S b/cpukit/score/cpu/riscv/riscv-context-validate.S
index bd2a7f0..6bdb06a 100644
--- a/cpukit/score/cpu/riscv/riscv-context-validate.S
+++ b/cpukit/score/cpu/riscv/riscv-context-validate.S
@@ -66,7 +66,7 @@
 #if __riscv_flen == 32
 #define FOFFSET(i) (OFFSET(29) + (i) * 4)
 #elif __riscv_flen == 64
-#define FOFFSET(i) (OFFSET(29) + (i) * 8)
+#define FOFFSET(i) (OFFSET(30) + (i) * 8)
 #else
 #define FOFFSET(i) OFFSET(29)
 #endif /* __riscv_flen */