[rtems commit] bsps/arm: Fix typo in disable cache for ARMv7-AR

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    0abe47f142691910cae4e8a8b0544e63c14a5516
Changeset: http://git.rtems.org/rtems/commit/?id=0abe47f142691910cae4e8a8b0544e63c14a5516

Author:    Thomas Dörfler <thomas.doerfler at embedded-brains.de>
Date:      Thu Jan 10 07:29:54 2019 +0100

bsps/arm: Fix typo in disable cache for ARMv7-AR

Update #3667.

---

 bsps/arm/shared/cache/cache-v7ar-disable-data.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bsps/arm/shared/cache/cache-v7ar-disable-data.S b/bsps/arm/shared/cache/cache-v7ar-disable-data.S
index b275c1d..4b20fb2 100644
--- a/bsps/arm/shared/cache/cache-v7ar-disable-data.S
+++ b/bsps/arm/shared/cache/cache-v7ar-disable-data.S
@@ -73,7 +73,7 @@ FUNCTION_ENTRY(rtems_cache_disable_data)
 
 	/* Read CCSIDR */
 	lsl	r4, r3, #1
-	mcr	p15, 2, r5, c0, c0, 0
+	mcr	p15, 2, r4, c0, c0, 0
 	isb
 	mrc	p15, 1, r5, c0, c0, 0