[rtems commit] arm: Select the TLB invalidate based on the core' s Id variant.
Chris Johns
chrisj at rtems.org
Tue Jul 30 22:37:56 UTC 2019
Module: rtems
Branch: master
Commit: 98d67923768d21bbf4b4699428492147e166cd24
Changeset: http://git.rtems.org/rtems/commit/?id=98d67923768d21bbf4b4699428492147e166cd24
Author: Chris Johns <chrisj at rtems.org>
Date: Tue Jun 25 20:48:51 2019 +1000
arm: Select the TLB invalidate based on the core's Id variant.
Closes #3760
---
bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
index c2be0f5..cf2d555 100644
--- a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
+++ b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
@@ -65,12 +65,16 @@ static uint32_t set_translation_table_entries(
for ( i = istart; i != iend; i = (i + 1U) & index_mask ) {
void *mva = (void *) (i << ARM_MMU_SECT_BASE_SHIFT);
- #if defined(__ARM_ARCH_7A__)
- arm_cp15_tlb_invalidate_entry_all_asids(mva);
- #else
- arm_cp15_tlb_instruction_invalidate_entry(mva);
- arm_cp15_tlb_data_invalidate_entry(mva);
- #endif
+#if defined(__ARM_ARCH_7A__)
+ if ((arm_cp15_get_multiprocessor_affinity() & (1 << 30)) == 0) {
+ arm_cp15_tlb_invalidate_entry_all_asids(mva);
+ }
+ else
+#endif
+ {
+ arm_cp15_tlb_instruction_invalidate_entry(mva);
+ arm_cp15_tlb_data_invalidate_entry(mva);
+ }
}
_ARM_Data_synchronization_barrier();
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