[rtems-central commit] Revert "spec: Workaround for broken document generator"

Sebastian Huber sebh at rtems.org
Sat Dec 4 12:29:48 UTC 2021


Module:    rtems-central
Branch:    master
Commit:    c73cdc716033405108ce752292f2f7628df2a627
Changeset: http://git.rtems.org/rtems-central/commit/?id=c73cdc716033405108ce752292f2f7628df2a627

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Sat Dec  4 13:34:53 2021 +0100

Revert "spec: Workaround for broken document generator"

This reverts commit 45494f7663d4d84655a1bde7fd8097329117c75d.

---

 spec/score/cpu/val/fatal-halt-sparc.yml | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/spec/score/cpu/val/fatal-halt-sparc.yml b/spec/score/cpu/val/fatal-halt-sparc.yml
index ace31b3..0055347 100644
--- a/spec/score/cpu/val/fatal-halt-sparc.yml
+++ b/spec/score/cpu/val/fatal-halt-sparc.yml
@@ -15,8 +15,8 @@ references:
   type: file
 text: |
   Inspection of the referenced ${/glossary/sourcecode:/term} files showed that
-  the function is implemented as specified.  In addition, the instruction
-  sequence of the directive was executed in assembler single step mode under
-  control of a debugger on the SPARC/RISCV instruction simulator version 2.29
-  to validate that its function is as specified.
+  the ${../if/fatal-halt:/name} directive is implemented as specified.  In
+  addition, the instruction sequence of the directive was executed in assembler
+  single step mode under control of a debugger on the SPARC/RISCV instruction
+  simulator version 2.29 to validate that its function is as specified.
 type: validation



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