[rtems commit] bsp/stm32h7: Split start configuration
Sebastian Huber
sebh at rtems.org
Mon Jan 4 18:23:43 UTC 2021
Module: rtems
Branch: master
Commit: affc8de85f951768b2fa6fb46f154f738f5a0150
Changeset: http://git.rtems.org/rtems/commit/?id=affc8de85f951768b2fa6fb46f154f738f5a0150
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Mon Jan 4 18:58:24 2021 +0100
bsp/stm32h7: Split start configuration
This allows applications to individually provide configuration
structures.
Update #4209.
---
bsps/arm/stm32h7/start/stm32h7-config-clk.c | 45 +++++++++++++++++++
bsps/arm/stm32h7/start/stm32h7-config-fls.c | 34 ++++++++++++++
bsps/arm/stm32h7/start/stm32h7-config-osc.c | 52 ++++++++++++++++++++++
.../{stm32h7-config.c => stm32h7-config-per.c} | 38 ----------------
bsps/arm/stm32h7/start/stm32h7-config-pwr.c | 35 +++++++++++++++
spec/build/bsps/arm/stm32h7/bspstm32h7.yml | 6 ++-
6 files changed, 171 insertions(+), 39 deletions(-)
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-clk.c b/bsps/arm/stm32h7/start/stm32h7-config-clk.c
new file mode 100644
index 0000000..3e7c930
--- /dev/null
+++ b/bsps/arm/stm32h7/start/stm32h7-config-clk.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+const RCC_ClkInitTypeDef stm32h7_config_clocks = {
+ .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+ | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1,
+ .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK,
+ .SYSCLKDivider = RCC_SYSCLK_DIV1,
+ .AHBCLKDivider = RCC_HCLK_DIV2,
+ .APB3CLKDivider = RCC_APB3_DIV2,
+ .APB1CLKDivider = RCC_APB1_DIV2,
+ .APB2CLKDivider = RCC_APB2_DIV2,
+ .APB4CLKDivider = RCC_APB4_DIV2
+};
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-fls.c b/bsps/arm/stm32h7/start/stm32h7-config-fls.c
new file mode 100644
index 0000000..f2d10d2
--- /dev/null
+++ b/bsps/arm/stm32h7/start/stm32h7-config-fls.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4;
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-osc.c b/bsps/arm/stm32h7/start/stm32h7-config-osc.c
new file mode 100644
index 0000000..b639c7c
--- /dev/null
+++ b/bsps/arm/stm32h7/start/stm32h7-config-osc.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+const RCC_OscInitTypeDef stm32h7_config_oscillator = {
+ .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
+ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48,
+ .HSEState = RCC_HSE_ON,
+ .LSEState = RCC_LSE_ON,
+ .HSIState = RCC_HSI_DIV1,
+ .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT,
+ .HSI48State = RCC_HSI48_ON,
+ .PLL.PLLState = RCC_PLL_ON,
+ .PLL.PLLSource = RCC_PLLSOURCE_HSE,
+ .PLL.PLLM = 5,
+ .PLL.PLLN = 192,
+ .PLL.PLLP = 2,
+ .PLL.PLLQ = 12,
+ .PLL.PLLR = 2,
+ .PLL.PLLRGE = RCC_PLL1VCIRANGE_2,
+ .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE,
+ .PLL.PLLFRACN = 0
+};
diff --git a/bsps/arm/stm32h7/start/stm32h7-config.c b/bsps/arm/stm32h7/start/stm32h7-config-per.c
similarity index 67%
rename from bsps/arm/stm32h7/start/stm32h7-config.c
rename to bsps/arm/stm32h7/start/stm32h7-config-per.c
index 874ad04..79aa149 100644
--- a/bsps/arm/stm32h7/start/stm32h7-config.c
+++ b/bsps/arm/stm32h7/start/stm32h7-config-per.c
@@ -31,44 +31,6 @@
#include <stm32h7/hal.h>
-const uint32_t stm32h7_config_pwr_regulator_voltagescaling =
- PWR_REGULATOR_VOLTAGE_SCALE0;
-
-const RCC_OscInitTypeDef stm32h7_config_oscillator = {
- .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
- | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48,
- .HSEState = RCC_HSE_ON,
- .LSEState = RCC_LSE_ON,
- .HSIState = RCC_HSI_DIV1,
- .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT,
- .HSI48State = RCC_HSI48_ON,
- .PLL.PLLState = RCC_PLL_ON,
- .PLL.PLLSource = RCC_PLLSOURCE_HSE,
- .PLL.PLLM = 5,
- .PLL.PLLN = 192,
- .PLL.PLLP = 2,
- .PLL.PLLQ = 12,
- .PLL.PLLR = 2,
- .PLL.PLLRGE = RCC_PLL1VCIRANGE_2,
- .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE,
- .PLL.PLLFRACN = 0
-};
-
-const RCC_ClkInitTypeDef stm32h7_config_clocks = {
- .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
- | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
- | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1,
- .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK,
- .SYSCLKDivider = RCC_SYSCLK_DIV1,
- .AHBCLKDivider = RCC_HCLK_DIV2,
- .APB3CLKDivider = RCC_APB3_DIV2,
- .APB1CLKDivider = RCC_APB1_DIV2,
- .APB2CLKDivider = RCC_APB2_DIV2,
- .APB4CLKDivider = RCC_APB4_DIV2
-};
-
-const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4;
-
const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3
| RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-pwr.c b/bsps/arm/stm32h7/start/stm32h7-config-pwr.c
new file mode 100644
index 0000000..3fcdeba
--- /dev/null
+++ b/bsps/arm/stm32h7/start/stm32h7-config-pwr.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+const uint32_t stm32h7_config_pwr_regulator_voltagescaling =
+ PWR_REGULATOR_VOLTAGE_SCALE0;
diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml
index 8352473..6424de3 100644
--- a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml
+++ b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml
@@ -398,7 +398,11 @@ source:
- bsps/arm/stm32h7/start/ext-mem-ctl.c
- bsps/arm/stm32h7/start/getentropy-rng.c
- bsps/arm/stm32h7/start/mpu-config.c
-- bsps/arm/stm32h7/start/stm32h7-config.c
+- bsps/arm/stm32h7/start/stm32h7-config-clk.c
+- bsps/arm/stm32h7/start/stm32h7-config-fls.c
+- bsps/arm/stm32h7/start/stm32h7-config-osc.c
+- bsps/arm/stm32h7/start/stm32h7-config-per.c
+- bsps/arm/stm32h7/start/stm32h7-config-pwr.c
- bsps/arm/stm32h7/start/stm32h7-hal.c
- bsps/arm/stm32h7/start/stm32h7-hal-eth.c
- bsps/arm/stm32h7/start/stm32h7-hal-uart.c
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