[rtems-central commit] spec: Add grlib register blocks
Sebastian Huber
sebh at rtems.org
Wed Jul 21 17:20:21 UTC 2021
Module: rtems-central
Branch: master
Commit: bdbc189e4fc814a88fb8f99385b8ab727007aae7
Changeset: http://git.rtems.org/rtems-central/commit/?id=bdbc189e4fc814a88fb8f99385b8ab727007aae7
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Tue May 4 14:46:51 2021 +0200
spec: Add grlib register blocks
---
spec/dev/grlib/if/ahbstat-header.yml | 16 +
spec/dev/grlib/if/ahbstat.yml | 111 +++
spec/dev/grlib/if/ahbtrace-header.yml | 16 +
spec/dev/grlib/if/ahbtrace.yml | 215 +++++
spec/dev/grlib/if/apbuart-header.yml | 16 +
spec/dev/grlib/if/apbuart.yml | 282 ++++++
spec/dev/grlib/if/dsu4-header.yml | 16 +
spec/dev/grlib/if/dsu4.yml | 653 ++++++++++++++
spec/dev/grlib/if/ftmctrl-header.yml | 16 +
spec/dev/grlib/if/ftmctrl.yml | 203 +++++
spec/dev/grlib/if/gptimer-header.yml | 16 +
spec/dev/grlib/if/gptimer-timer.yml | 149 ++++
spec/dev/grlib/if/gptimer.yml | 151 ++++
spec/dev/grlib/if/gr1553b-header.yml | 16 +
spec/dev/grlib/if/gr1553b.yml | 1173 +++++++++++++++++++++++++
spec/dev/grlib/if/gr740thsens-header.yml | 16 +
spec/dev/grlib/if/gr740thsens.yml | 148 ++++
spec/dev/grlib/if/grcan-header.yml | 16 +
spec/dev/grlib/if/grcan.yml | 518 +++++++++++
spec/dev/grlib/if/grclkgate-header.yml | 16 +
spec/dev/grlib/if/grclkgate.yml | 107 +++
spec/dev/grlib/if/grethgbit-header.yml | 16 +
spec/dev/grlib/if/grethgbit.yml | 406 +++++++++
spec/dev/grlib/if/grgpio-header.yml | 16 +
spec/dev/grlib/if/grgpio.yml | 401 +++++++++
spec/dev/grlib/if/grgprbank-header.yml | 16 +
spec/dev/grlib/if/grgprbank.yml | 358 ++++++++
spec/dev/grlib/if/grgpreg-header.yml | 16 +
spec/dev/grlib/if/grgpreg.yml | 104 +++
spec/dev/grlib/if/griommu-header.yml | 16 +
spec/dev/grlib/if/griommu.yml | 721 ++++++++++++++++
spec/dev/grlib/if/group.yml | 19 +
spec/dev/grlib/if/grpci2-header.yml | 16 +
spec/dev/grlib/if/grpci2.yml | 862 +++++++++++++++++++
spec/dev/grlib/if/grspw2-header.yml | 16 +
spec/dev/grlib/if/grspw2.yml | 564 ++++++++++++
spec/dev/grlib/if/grspwrouter-header.yml | 16 +
spec/dev/grlib/if/grspwrouter.yml | 771 +++++++++++++++++
spec/dev/grlib/if/irqamp-header.yml | 16 +
spec/dev/grlib/if/irqamp-timestamp.yml | 125 +++
spec/dev/grlib/if/irqamp.yml | 432 ++++++++++
spec/dev/grlib/if/l2cache-header.yml | 16 +
spec/dev/grlib/if/l2cache.yml | 669 +++++++++++++++
spec/dev/grlib/if/l4stat-header.yml | 16 +
spec/dev/grlib/if/l4stat.yml | 194 +++++
spec/dev/grlib/if/memscrub-header.yml | 16 +
spec/dev/grlib/if/memscrub.yml | 403 +++++++++
spec/dev/grlib/if/mmctrl-header.yml | 16 +
spec/dev/grlib/if/mmctrl.yml | 302 +++++++
spec/dev/grlib/if/spictrl-header.yml | 16 +
spec/dev/grlib/if/spictrl.yml | 430 ++++++++++
spec/dev/grlib/if/spwpnp-header.yml | 16 +
spec/dev/grlib/if/spwpnp.yml | 314 +++++++
spec/dev/grlib/if/spwrmap-header.yml | 16 +
spec/dev/grlib/if/spwrmap.yml | 1370 ++++++++++++++++++++++++++++++
spec/dev/grlib/if/spwtdp-header.yml | 16 +
spec/dev/grlib/if/spwtdp.yml | 950 +++++++++++++++++++++
57 files changed, 13537 insertions(+)
diff --git a/spec/dev/grlib/if/ahbstat-header.yml b/spec/dev/grlib/if/ahbstat-header.yml
new file mode 100644
index 0000000..79104b8
--- /dev/null
+++ b/spec/dev/grlib/if/ahbstat-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the AHBSTAT register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: ahbstat
+path: grlib/ahbstat-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/ahbstat.yml b/spec/dev/grlib/if/ahbstat.yml
new file mode 100644
index 0000000..3e870e8
--- /dev/null
+++ b/spec/dev/grlib/if/ahbstat.yml
@@ -0,0 +1,111 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBAHBSTAT
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: ahbstat-header
+definition:
+- default:
+ count: 1
+ name: AHBS
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: AHBFAR
+ offset: 0x4
+ variants: []
+register-prefix: null
+register-block-group: AHBSTAT
+register-block-size: 8
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ME'
+ start: 13
+ width: 1
+ - access: [w]
+ brief: null
+ description: null
+ name: 'FW'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CF'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AF'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CE'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'NE'
+ start: 8
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'HWRITE'
+ start: 7
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'HMASTER'
+ start: 3
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'HSIZE'
+ start: 0
+ width: 3
+ variants: []
+ brief: |
+ AHB Status register
+ description: null
+ name: AHBS
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'HADDR'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ AHB Failing address register
+ description: null
+ name: AHBFAR
+ width: 32
+name: ahbstat
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/ahbtrace-header.yml b/spec/dev/grlib/if/ahbtrace-header.yml
new file mode 100644
index 0000000..1b6ed05
--- /dev/null
+++ b/spec/dev/grlib/if/ahbtrace-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the AHBTRACE register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: ahbtrace
+path: grlib/ahbtrace-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/ahbtrace.yml b/spec/dev/grlib/if/ahbtrace.yml
new file mode 100644
index 0000000..57e03e2
--- /dev/null
+++ b/spec/dev/grlib/if/ahbtrace.yml
@@ -0,0 +1,215 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBAHBTRACE
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: ahbtrace-header
+definition:
+- default:
+ count: 1
+ name: CTRL
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: INDEX
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: TIMETAG
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: MSFILT
+ offset: 0xc
+ variants: []
+- default:
+ count: 1
+ name: TBBA
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: TBBM
+ offset: 0x14
+ variants: []
+- default:
+ count: 1
+ name: TBBA
+ offset: 0x18
+ variants: []
+- default:
+ count: 1
+ name: TBBM
+ offset: 0x1c
+ variants: []
+register-prefix: null
+register-block-group: AHBTRACE
+register-block-size: 32
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DCNT'
+ start: 16
+ width: 7
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PF'
+ start: 8
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BW'
+ start: 6
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RF'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AF'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FR'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FW'
+ start: 2
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DM'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Trace buffer control register
+ description: null
+ name: CTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'INDEX'
+ start: 4
+ width: 7
+ variants: []
+ brief: |
+ Trace buffer index register
+ description: null
+ name: INDEX
+ width: 32
+- bits:
+ - default:
+ - access: []
+ brief: null
+ description: null
+ name: 'TIMETAG'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Trace buffer time tag register
+ description: null
+ name: TIMETAG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SMASK_15_0'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MMASK_15_0'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Trace buffer master/slave filter register
+ description: null
+ name: MSFILT
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BADDR_31_2'
+ start: 2
+ width: 30
+ variants: []
+ brief: |
+ Trace buffer break address registers
+ description: null
+ name: TBBA
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BMASK_31_2'
+ start: 2
+ width: 30
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LD'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ST'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Trace buffer break mask registers
+ description: null
+ name: TBBM
+ width: 32
+name: ahbtrace
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/apbuart-header.yml b/spec/dev/grlib/if/apbuart-header.yml
new file mode 100644
index 0000000..82f5ea0
--- /dev/null
+++ b/spec/dev/grlib/if/apbuart-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the APBUART register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: apbuart
+path: grlib/apbuart-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/apbuart.yml b/spec/dev/grlib/if/apbuart.yml
new file mode 100644
index 0000000..968101c
--- /dev/null
+++ b/spec/dev/grlib/if/apbuart.yml
@@ -0,0 +1,282 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBAPBUART
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: apbuart-header
+definition:
+- default:
+ count: 1
+ name: DATA
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: STATUS
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: CTRL
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: SCALER
+ offset: 0xc
+ variants: []
+- default:
+ count: 1
+ name: FIFO
+ offset: 0x10
+ variants: []
+register-prefix: null
+register-block-group: APBUART
+register-block-size: 20
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ UART data register
+ description: null
+ name: DATA
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RCNT'
+ start: 26
+ width: 6
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TCNT'
+ start: 20
+ width: 6
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RF'
+ start: 10
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TF'
+ start: 9
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RH'
+ start: 8
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TH'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FE'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'OV'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BR'
+ start: 3
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 2
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TS'
+ start: 1
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DR'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ UART status register
+ description: null
+ name: STATUS
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'FA'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SI'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DI'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BI'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DB'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RF'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TF'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EC'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LB'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FL'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PS'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TI'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RI'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ UART control register
+ description: null
+ name: CTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SCALER_RELOAD_VALUE'
+ start: 0
+ width: 20
+ variants: []
+ brief: |
+ UART scaler reload register
+ description: null
+ name: SCALER
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ UART FIFO debug register
+ description: null
+ name: FIFO
+ width: 32
+name: apbuart
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/dsu4-header.yml b/spec/dev/grlib/if/dsu4-header.yml
new file mode 100644
index 0000000..54993c8
--- /dev/null
+++ b/spec/dev/grlib/if/dsu4-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the DSU4 register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: dsu4
+path: grlib/dsu4-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/dsu4.yml b/spec/dev/grlib/if/dsu4.yml
new file mode 100644
index 0000000..b10391e
--- /dev/null
+++ b/spec/dev/grlib/if/dsu4.yml
@@ -0,0 +1,653 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBDSU4
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: dsu4-header
+definition:
+- default:
+ count: 1
+ name: CTRL
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: DTTC
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: BRSS
+ offset: 0x20
+ variants: []
+- default:
+ count: 1
+ name: DBGM
+ offset: 0x24
+ variants: []
+- default:
+ count: 1
+ name: ATBC
+ offset: 0x40
+ variants: []
+- default:
+ count: 1
+ name: ATBI
+ offset: 0x44
+ variants: []
+- default:
+ count: 1
+ name: ATBFC
+ offset: 0x48
+ variants: []
+- default:
+ count: 1
+ name: ATBFM
+ offset: 0x4c
+ variants: []
+- default:
+ count: 1
+ name: ATBBA
+ offset: 0x50
+ variants: []
+- default:
+ count: 1
+ name: ATBBM
+ offset: 0x54
+ variants: []
+- default:
+ count: 1
+ name: ATBBA
+ offset: 0x58
+ variants: []
+- default:
+ count: 1
+ name: ATBBM
+ offset: 0x5c
+ variants: []
+- default:
+ count: 1
+ name: ICNT
+ offset: 0x70
+ variants: []
+- default:
+ count: 1
+ name: AHBWPC
+ offset: 0x80
+ variants: []
+- default:
+ count: 1
+ name: AHBWPD
+ offset: 0x90
+ variants: []
+- default:
+ count: 1
+ name: AHBWPD
+ offset: 0x9c
+ variants: []
+- default:
+ count: 1
+ name: AHBWPM
+ offset: 0xa0
+ variants: []
+- default:
+ count: 1
+ name: AHBWPM
+ offset: 0xac
+ variants: []
+- default:
+ count: 1
+ name: AHBWPD
+ offset: 0xb0
+ variants: []
+- default:
+ count: 1
+ name: AHBWPD
+ offset: 0xbc
+ variants: []
+- default:
+ count: 1
+ name: AHBWPM
+ offset: 0xc0
+ variants: []
+- default:
+ count: 1
+ name: AHBWPM
+ offset: 0xcc
+ variants: []
+- default:
+ count: 1
+ name: ITBC0
+ offset: 0x110000
+ variants: []
+- default:
+ count: 1
+ name: ITBC1
+ offset: 0x110004
+ variants: []
+- default:
+ count: 1
+ name: DTR
+ offset: 0x400020
+ variants: []
+- default:
+ count: 1
+ name: DASI
+ offset: 0x400024
+ variants: []
+register-prefix: null
+register-block-group: DSU4
+register-block-size: 4194344
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PW'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'HL'
+ start: 10
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 9
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'EB'
+ start: 8
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'EE'
+ start: 7
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DM'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BZ'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BX'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BS'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BW'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ DSU control register
+ description: null
+ name: CTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TIMETAG'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ DSU time tag counter register
+ description: null
+ name: DTTC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SS_3_0'
+ start: 16
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BN_3_0'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ DSU break and single step register
+ description: null
+ name: BRSS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DM_3_0'
+ start: 16
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ED_3_0'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ DSU debug mode mask register
+ description: null
+ name: DBGM
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'EM'
+ start: 12
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TRAPTYPE'
+ start: 4
+ width: 8
+ variants: []
+ brief: |
+ DSU trap register
+ description: null
+ name: DTR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ASI'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ DSU ASI diagnostic access register
+ description: null
+ name: DASI
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DCNT'
+ start: 16
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DF'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SF'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TF'
+ start: 5
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BW'
+ start: 3
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BR'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DM'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ AHB trace buffer control register
+ description: null
+ name: ATBC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'INDEX'
+ start: 4
+ width: 8
+ variants: []
+ brief: |
+ AHB trace buffer index register
+ description: null
+ name: ATBI
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WPF'
+ start: 12
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BPF'
+ start: 8
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PF'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AF'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FR'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FW'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ AHB trace buffer filter control register
+ description: null
+ name: ATBFC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SMASK_15_0'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MMASK_15_0'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ AHB trace buffer filter mask register
+ description: null
+ name: ATBFM
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BADDR_31_2'
+ start: 2
+ width: 30
+ variants: []
+ brief: |
+ AHB trace buffer break address registers
+ description: null
+ name: ATBBA
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BMASK_31_2'
+ start: 2
+ width: 30
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LD'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ST'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ AHB trace buffer break mask registers
+ description: null
+ name: ATBBM
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CE'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IC'
+ start: 30
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 29
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ICOUNT_28_0'
+ start: 0
+ width: 29
+ variants: []
+ brief: |
+ Instruction trace count register
+ description: null
+ name: ICNT
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IN'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CP'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IN'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CP'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ AHB watchpoint control register
+ description: null
+ name: AHBWPC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ AHB watchpoint data registers
+ description: null
+ name: AHBWPD
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ AHB watchpoint mask registers
+ description: null
+ name: AHBWPM
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TFILT'
+ start: 28
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ITPOINTER'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Instruction trace buffer control register 0
+ description: null
+ name: ITBC0
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WO'
+ start: 27
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TLIM'
+ start: 24
+ width: 3
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TOV'
+ start: 23
+ width: 1
+ variants: []
+ brief: |
+ Instruction trace buffer control register 1
+ description: null
+ name: ITBC1
+ width: 32
+name: dsu4
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/ftmctrl-header.yml b/spec/dev/grlib/if/ftmctrl-header.yml
new file mode 100644
index 0000000..698b0d0
--- /dev/null
+++ b/spec/dev/grlib/if/ftmctrl-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the FTMCTRL register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: ftmctrl
+path: grlib/ftmctrl-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/ftmctrl.yml b/spec/dev/grlib/if/ftmctrl.yml
new file mode 100644
index 0000000..ebeaf6f
--- /dev/null
+++ b/spec/dev/grlib/if/ftmctrl.yml
@@ -0,0 +1,203 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBFTMCTRL
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: ftmctrl-header
+definition:
+- default:
+ count: 1
+ name: MCFG1
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: MCFG3
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: MCFG5
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: MCFG7
+ offset: 0x18
+ variants: []
+register-prefix: null
+register-block-group: FTMCTRL
+register-block-size: 28
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PBRDY'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ABRDY'
+ start: 30
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IOBUSW'
+ start: 29
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IBRDY'
+ start: 27
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BEXCN'
+ start: 26
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IO_WAITSTATES'
+ start: 24
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IOEN'
+ start: 20
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ROMBANKSZ'
+ start: 19
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PWEN'
+ start: 14
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PROM_WIDTH'
+ start: 12
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PROM_WRITE_WS'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PROM_READ_WS'
+ start: 8
+ width: 2
+ variants: []
+ brief: |
+ Memory configuration register 1
+ description: null
+ name: MCFG1
+ width: 32
+- bits:
+ - default:
+ - access: []
+ brief: null
+ description: null
+ name: 'ME'
+ start: 27
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WB'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RB'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TCB'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ Memory configuration register 3
+ description: null
+ name: MCFG3
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IOHWS'
+ start: 23
+ width: 7
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ROMHWS'
+ start: 7
+ width: 7
+ variants: []
+ brief: |
+ Memory configuration register 5
+ description: null
+ name: MCFG5
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BRDYNCNT'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BRDYNRLD'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Memory configuration register 7
+ description: null
+ name: MCFG7
+ width: 32
+name: ftmctrl
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/gptimer-header.yml b/spec/dev/grlib/if/gptimer-header.yml
new file mode 100644
index 0000000..742126a
--- /dev/null
+++ b/spec/dev/grlib/if/gptimer-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GPTIMER register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: gptimer
+path: grlib/gptimer-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/gptimer-timer.yml b/spec/dev/grlib/if/gptimer-timer.yml
new file mode 100644
index 0000000..d79ce1f
--- /dev/null
+++ b/spec/dev/grlib/if/gptimer-timer.yml
@@ -0,0 +1,149 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBGPTIMERTimer
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: gptimer
+- role: interface-placement
+ uid: gptimer-header
+definition:
+- default:
+ count: 1
+ name: TCNTVAL
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: TRLDVAL
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: TCTRL
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: TLATCH
+ offset: 0xc
+ variants: []
+register-prefix: gptimer
+register-block-group: GPTIMER TIMER
+register-block-size: 16
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TCVAL'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Timer n counter value register
+ description: null
+ name: TCNTVAL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TRLDVAL'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Timer n counter reload value register
+ description: null
+ name: TRLDVAL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WS'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WN'
+ start: 7
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DH'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CH'
+ start: 5
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'IP'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IE'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LD'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RS'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Timer n control register
+ description: null
+ name: TCTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'LTCV'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Timer n latch register
+ description: null
+ name: TLATCH
+ width: 32
+name: gptimer_timer
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/gptimer.yml b/spec/dev/grlib/if/gptimer.yml
new file mode 100644
index 0000000..e029ab7
--- /dev/null
+++ b/spec/dev/grlib/if/gptimer.yml
@@ -0,0 +1,151 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBGPTIMER
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: gptimer-header
+- name: TIMER
+ role: register-block-include
+ uid: gptimer-timer
+definition:
+- default:
+ count: 1
+ name: SCALER
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: SRELOAD
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: CONFIG
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: LATCHCFG
+ offset: 0xc
+ variants: []
+- default:
+ count: 15
+ name: TIMER
+ offset: 0x10
+ variants: []
+register-prefix: null
+register-block-group: GPTIMER
+register-block-size: 256
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SCALER'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Scaler value register
+ description: null
+ name: SCALER
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SRELOAD'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Scaler reload value register
+ description: null
+ name: SRELOAD
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EV'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ES'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EL'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EE'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DF'
+ start: 9
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SI'
+ start: 8
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IRQ'
+ start: 3
+ width: 5
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TIMERS'
+ start: 0
+ width: 3
+ variants: []
+ brief: |
+ Configuration register
+ description: null
+ name: CONFIG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LATCHSEL'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Timer latch configuration register
+ description: null
+ name: LATCHCFG
+ width: 32
+name: gptimer
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/gr1553b-header.yml b/spec/dev/grlib/if/gr1553b-header.yml
new file mode 100644
index 0000000..6be3cb5
--- /dev/null
+++ b/spec/dev/grlib/if/gr1553b-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GR1553B register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: gr1553b
+path: grlib/gr1553b-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/gr1553b.yml b/spec/dev/grlib/if/gr1553b.yml
new file mode 100644
index 0000000..8de3cf1
--- /dev/null
+++ b/spec/dev/grlib/if/gr1553b.yml
@@ -0,0 +1,1173 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGR1553B
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: gr1553b-header
+definition:
+- default:
+ count: 1
+ name: IRQ
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: IRQE
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: HC
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: BCSC
+ offset: 0x40
+ variants: []
+- default:
+ count: 1
+ name: BCA
+ offset: 0x44
+ variants: []
+- default:
+ count: 1
+ name: BCTNP
+ offset: 0x48
+ variants: []
+- default:
+ count: 1
+ name: BCANP
+ offset: 0x4c
+ variants: []
+- default:
+ count: 1
+ name: BCT
+ offset: 0x50
+ variants: []
+- default:
+ count: 1
+ name: BCRP
+ offset: 0x58
+ variants: []
+- default:
+ count: 1
+ name: BCBS
+ offset: 0x5c
+ variants: []
+- default:
+ count: 1
+ name: BCTCP
+ offset: 0x68
+ variants: []
+- default:
+ count: 1
+ name: BCACP
+ offset: 0x6c
+ variants: []
+- default:
+ count: 1
+ name: RTS
+ offset: 0x80
+ variants: []
+- default:
+ count: 1
+ name: RTC
+ offset: 0x84
+ variants: []
+- default:
+ count: 1
+ name: RTBS
+ offset: 0x88
+ variants: []
+- default:
+ count: 1
+ name: RTSW
+ offset: 0x8c
+ variants: []
+- default:
+ count: 1
+ name: RTSY
+ offset: 0x90
+ variants: []
+- default:
+ count: 1
+ name: RTSTBA
+ offset: 0x94
+ variants: []
+- default:
+ count: 1
+ name: RTMCC
+ offset: 0x98
+ variants: []
+- default:
+ count: 1
+ name: RTTTC
+ offset: 0xa4
+ variants: []
+- default:
+ count: 1
+ name: RTELM
+ offset: 0xac
+ variants: []
+- default:
+ count: 1
+ name: RTELP
+ offset: 0xb0
+ variants: []
+- default:
+ count: 1
+ name: RTELIP
+ offset: 0xb4
+ variants: []
+- default:
+ count: 1
+ name: BMS
+ offset: 0xc0
+ variants: []
+- default:
+ count: 1
+ name: BMC
+ offset: 0xc4
+ variants: []
+- default:
+ count: 1
+ name: BMRTAF
+ offset: 0xc8
+ variants: []
+- default:
+ count: 1
+ name: BMRTSF
+ offset: 0xcc
+ variants: []
+- default:
+ count: 1
+ name: BMRTMC
+ offset: 0xd0
+ variants: []
+- default:
+ count: 1
+ name: BMLBS
+ offset: 0xd4
+ variants: []
+- default:
+ count: 1
+ name: BMLBE
+ offset: 0xd8
+ variants: []
+- default:
+ count: 1
+ name: BMLBP
+ offset: 0xdc
+ variants: []
+- default:
+ count: 1
+ name: BMTTC
+ offset: 0xe0
+ variants: []
+register-prefix: null
+register-block-group: GR1553B
+register-block-size: 228
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'BMTOF'
+ start: 17
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'BMD'
+ start: 16
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RTTE'
+ start: 10
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RTD'
+ start: 9
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RTEV'
+ start: 8
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'BCWK'
+ start: 2
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'BCD'
+ start: 1
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'BCEV'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ GR1553B IRQ Register
+ description: null
+ name: IRQ
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BMTOE'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BMDE'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RTTEE'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RTDE'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RTEVE'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BCWKE'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BCDE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BCEVE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ GR1553B IRQ Enable Register
+ description: null
+ name: IRQE
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MOD'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CVER'
+ start: 12
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'XKEYS'
+ start: 11
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ENDIAN'
+ start: 9
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SCLK'
+ start: 8
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CCFREQ'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ GR1553B Hardware Configuration Register
+ description: null
+ name: HC
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BCSUP'
+ start: 31
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BCFEAT'
+ start: 28
+ width: 3
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BCCHK'
+ start: 16
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ASADL'
+ start: 11
+ width: 5
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ASST'
+ start: 8
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SCADL'
+ start: 3
+ width: 5
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SCST'
+ start: 0
+ width: 3
+ variants: []
+ brief: |
+ GR1553B BC Status and Config Register
+ description: null
+ name: BCSC
+ width: 32
+- bits:
+ - default:
+ - access: [w]
+ brief: null
+ description: null
+ name: 'BCKEY'
+ start: 16
+ width: 16
+ - access: [w]
+ brief: null
+ description: null
+ name: 'ASSTP'
+ start: 9
+ width: 1
+ - access: [w]
+ brief: null
+ description: null
+ name: 'ASSRT'
+ start: 8
+ width: 1
+ - access: [w]
+ brief: null
+ description: null
+ name: 'CLRT'
+ start: 4
+ width: 1
+ - access: [w]
+ brief: null
+ description: null
+ name: 'SETT'
+ start: 3
+ width: 1
+ - access: [w]
+ brief: null
+ description: null
+ name: 'SCSTP'
+ start: 2
+ width: 1
+ - access: [w]
+ brief: null
+ description: null
+ name: 'SCSUS'
+ start: 1
+ width: 1
+ - access: [w]
+ brief: null
+ description: null
+ name: 'SCSRT'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ GR1553B BC Action Register
+ description: null
+ name: BCA
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'POINTER'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B BC Transfer list next pointer register
+ description: null
+ name: BCTNP
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'POINTER'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B BC Asynchronous list next pointer register
+ description: null
+ name: BCANP
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SCTM'
+ start: 0
+ width: 24
+ variants: []
+ brief: |
+ GR1553B BC Timer register
+ description: null
+ name: BCT
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'POSITION'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B BC Transfer-triggered IRQ ring position register
+ description: null
+ name: BCRP
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SWAP'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B BC per-RT Bus swap register
+ description: null
+ name: BCBS
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'POINTER'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B BC Transfer list current slot pointer
+ description: null
+ name: BCTCP
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'POINTER'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B BC Asynchronous list current slot pointer
+ description: null
+ name: BCACP
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RTSUP'
+ start: 31
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ACT'
+ start: 3
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SHDA'
+ start: 2
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SHDB'
+ start: 1
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RUN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ GR1553B RT Status register
+ description: null
+ name: RTS
+ width: 32
+- bits:
+ - default:
+ - access: [w]
+ brief: null
+ description: null
+ name: 'RTKEY'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SYS'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SYDS'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BRS'
+ start: 13
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RTEIS'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RTADDR'
+ start: 1
+ width: 5
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RTEN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ GR1553B RT Config register
+ description: null
+ name: RTC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TFDE'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SREQ'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BUSY'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SSF'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DBCA'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TFLG'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ GR1553B RT Bus status register
+ description: null
+ name: RTBS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BITW'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'VECW'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ GR1553B RT Status words register
+ description: null
+ name: RTSW
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SYTM'
+ start: 16
+ width: 16
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SYD'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ GR1553B RT Sync register
+ description: null
+ name: RTSY
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SATB'
+ start: 9
+ width: 23
+ variants: []
+ brief: |
+ GR1553B RT Subaddress table base address register
+ description: null
+ name: RTSTBA
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RRTB'
+ start: 28
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RRT'
+ start: 26
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ITFB'
+ start: 24
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ITF'
+ start: 22
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ISTB'
+ start: 20
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IST'
+ start: 18
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DBC'
+ start: 16
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TBW'
+ start: 14
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TVW'
+ start: 12
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TSB'
+ start: 10
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TS'
+ start: 8
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SDB'
+ start: 6
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SD'
+ start: 4
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SB'
+ start: 2
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S'
+ start: 0
+ width: 2
+ variants: []
+ brief: |
+ GR1553B RT Mode code control register
+ description: null
+ name: RTMCC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TRES'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TVAL'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ GR1553B RT Time tag control register
+ description: null
+ name: RTTTC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B RT Event log size mask register
+ description: null
+ name: RTELM
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'POINTER'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B RT Event log position register
+ description: null
+ name: RTELP
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'POINTER'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B RT Event Log interrupt position register
+ description: null
+ name: RTELIP
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BMSUP'
+ start: 31
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'KEYEN'
+ start: 30
+ width: 1
+ variants: []
+ brief: |
+ GR1553B BM Status register
+ description: null
+ name: BMS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BMKEY'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WRSTP'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EXST'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IMCL'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'UDWL'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MANL'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BMEN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ GR1553B BM Control register
+ description: null
+ name: BMC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B BM RT Address filter register
+ description: null
+ name: BMRTAF
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B BM RT Subaddress filter register
+ description: null
+ name: BMRTSF
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'STSB'
+ start: 18
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'STS'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TLC'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TSW'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RRTB'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RRT'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ITFB'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ITF'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ISTB'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IST'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DBC'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TBW'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TVW'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TSB'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TS'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SDB'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SD'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SB'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ GR1553B BM RT Mode code filter register
+ description: null
+ name: BMRTMC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'START'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B BM Log buffer start
+ description: null
+ name: BMLBS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'END'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B BM Log buffer end
+ description: null
+ name: BMLBE
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'POSITION'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ GR1553B BM Log buffer position
+ description: null
+ name: BMLBP
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TRES'
+ start: 24
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TVAL'
+ start: 0
+ width: 24
+ variants: []
+ brief: |
+ GR1553B BM Time tag control register
+ description: null
+ name: BMTTC
+ width: 32
+name: gr1553b
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/gr740thsens-header.yml b/spec/dev/grlib/if/gr740thsens-header.yml
new file mode 100644
index 0000000..addfceb
--- /dev/null
+++ b/spec/dev/grlib/if/gr740thsens-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GR740THSENS register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: gr740thsens
+path: grlib/gr740thsens-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/gr740thsens.yml b/spec/dev/grlib/if/gr740thsens.yml
new file mode 100644
index 0000000..073d6ee
--- /dev/null
+++ b/spec/dev/grlib/if/gr740thsens.yml
@@ -0,0 +1,148 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGR740THSENS
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: gr740thsens-header
+definition:
+- default:
+ count: 1
+ name: CTRL
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: STATUS
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: THRES
+ offset: 0x8
+ variants: []
+register-prefix: null
+register-block-group: GR740THSENS
+register-block-size: 12
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DIV'
+ start: 16
+ width: 10
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ALEN'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PDN'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DCORRECT'
+ start: 2
+ width: 5
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SRSTN'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CLKEN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Control register
+ description: null
+ name: CTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MAX'
+ start: 24
+ width: 7
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MIN'
+ start: 16
+ width: 7
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SCLK'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WE'
+ start: 10
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'UPD'
+ start: 9
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'ALACT'
+ start: 8
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 0
+ width: 7
+ variants: []
+ brief: |
+ Status register
+ description: null
+ name: STATUS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'THRES'
+ start: 0
+ width: 7
+ variants: []
+ brief: |
+ Threshold register
+ description: null
+ name: THRES
+ width: 32
+name: gr740thsens
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/grcan-header.yml b/spec/dev/grlib/if/grcan-header.yml
new file mode 100644
index 0000000..d0b4736
--- /dev/null
+++ b/spec/dev/grlib/if/grcan-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GRCAN register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: grcan
+path: grlib/grcan-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/grcan.yml b/spec/dev/grlib/if/grcan.yml
new file mode 100644
index 0000000..54ba977
--- /dev/null
+++ b/spec/dev/grlib/if/grcan.yml
@@ -0,0 +1,518 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRCAN
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: grcan-header
+definition:
+- default:
+ count: 1
+ name: CanCONF
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: CanSTAT
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: CanCTRL
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: CanMASK
+ offset: 0x18
+ variants: []
+- default:
+ count: 1
+ name: CanCODE
+ offset: 0x1c
+ variants: []
+- default:
+ count: 1
+ name: CanTxCTRL
+ offset: 0x200
+ variants: []
+- default:
+ count: 1
+ name: CanTxADDR
+ offset: 0x204
+ variants: []
+- default:
+ count: 1
+ name: CanTxSIZE
+ offset: 0x208
+ variants: []
+- default:
+ count: 1
+ name: CanTxWR
+ offset: 0x20c
+ variants: []
+- default:
+ count: 1
+ name: CanTxRD
+ offset: 0x210
+ variants: []
+- default:
+ count: 1
+ name: CanTxRD
+ offset: 0x214
+ variants: []
+- default:
+ count: 1
+ name: CanRxCTRL
+ offset: 0x300
+ variants: []
+- default:
+ count: 1
+ name: CanRxADDR
+ offset: 0x304
+ variants: []
+- default:
+ count: 1
+ name: CanRxSIZE
+ offset: 0x308
+ variants: []
+- default:
+ count: 1
+ name: CanRxWR
+ offset: 0x30c
+ variants: []
+- default:
+ count: 1
+ name: CanRxRD
+ offset: 0x310
+ variants: []
+- default:
+ count: 1
+ name: CanRxIRQ
+ offset: 0x314
+ variants: []
+- default:
+ count: 1
+ name: CanRxMASK
+ offset: 0x318
+ variants: []
+- default:
+ count: 1
+ name: CanRxCODE
+ offset: 0x31c
+ variants: []
+register-prefix: null
+register-block-group: GRCAN
+register-block-size: 800
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SCALER'
+ start: 24
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PS1'
+ start: 20
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PS2'
+ start: 16
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RSJ'
+ start: 12
+ width: 3
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BPR'
+ start: 8
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SAM'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SILNT'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SELECT'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ENABLE1'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ENABLE0'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ABORT'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Configuration Register
+ description: null
+ name: CanCONF
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TXCHANNELS'
+ start: 28
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RXCHANNELS'
+ start: 24
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TXERRCNT'
+ start: 16
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RXERRCNT'
+ start: 8
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ACTIVE'
+ start: 4
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AHBERR'
+ start: 3
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'OR'
+ start: 2
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'OFF'
+ start: 1
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PASS'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Status Register
+ description: null
+ name: CanSTAT
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RESET'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ENABLE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Control Register
+ description: null
+ name: CanCTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 0
+ width: 29
+ variants: []
+ brief: |
+ SYNC Mask Filter Register
+ description: null
+ name: CanMASK
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SYNC'
+ start: 0
+ width: 29
+ variants: []
+ brief: |
+ SYNC Code Filter Register
+ description: null
+ name: CanCODE
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SINGLE'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ONGOING'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ENABLE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Transmit Channel Control Register
+ description: null
+ name: CanTxCTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ADDR'
+ start: 10
+ width: 22
+ variants: []
+ brief: |
+ Transmit Channel Address Register
+ description: null
+ name: CanTxADDR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SIZE'
+ start: 6
+ width: 15
+ variants: []
+ brief: |
+ Transmit Channel Size Register
+ description: null
+ name: CanTxSIZE
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WRITE'
+ start: 4
+ width: 16
+ variants: []
+ brief: |
+ Transmit Channel Write Register
+ description: null
+ name: CanTxWR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'READ'
+ start: 4
+ width: 16
+ variants: []
+ brief: |
+ Transmit Channel Read Register
+ description: null
+ name: CanTxRD
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQ'
+ start: 4
+ width: 16
+ variants: []
+ brief: |
+ Transmit Channel Read Register
+ description: null
+ name: CanTxRD
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ONGOING'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ENABLE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Receive Channel Control Register
+ description: null
+ name: CanRxCTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ADDR'
+ start: 10
+ width: 22
+ variants: []
+ brief: |
+ Receive Channel Address Register
+ description: null
+ name: CanRxADDR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SIZE'
+ start: 6
+ width: 15
+ variants: []
+ brief: |
+ Receive Channel Size Register
+ description: null
+ name: CanRxSIZE
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WRITE'
+ start: 4
+ width: 16
+ variants: []
+ brief: |
+ Receive Channel Write Register
+ description: null
+ name: CanRxWR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'READ'
+ start: 4
+ width: 16
+ variants: []
+ brief: |
+ Receive Channel Read Register
+ description: null
+ name: CanRxRD
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQ'
+ start: 4
+ width: 16
+ variants: []
+ brief: |
+ Receive Channel Interrupt Register
+ description: null
+ name: CanRxIRQ
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AM'
+ start: 0
+ width: 29
+ variants: []
+ brief: |
+ Receive Channel Mask Register
+ description: null
+ name: CanRxMASK
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AC'
+ start: 0
+ width: 29
+ variants: []
+ brief: |
+ Receive Channel Code Register
+ description: null
+ name: CanRxCODE
+ width: 32
+name: grcan
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/grclkgate-header.yml b/spec/dev/grlib/if/grclkgate-header.yml
new file mode 100644
index 0000000..aa88d33
--- /dev/null
+++ b/spec/dev/grlib/if/grclkgate-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GRCLKGATE register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: grclkgate
+path: grlib/grclkgate-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/grclkgate.yml b/spec/dev/grlib/if/grclkgate.yml
new file mode 100644
index 0000000..6671903
--- /dev/null
+++ b/spec/dev/grlib/if/grclkgate.yml
@@ -0,0 +1,107 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRCLKGATE
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: grclkgate-header
+definition:
+- default:
+ count: 1
+ name: UNLOCK
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: CLKEN
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: RESET
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: OVERRIDE
+ offset: 0xc
+ variants: []
+register-prefix: null
+register-block-group: GRCLKGATE
+register-block-size: 16
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'UNLOCK'
+ start: 0
+ width: 11
+ variants: []
+ brief: |
+ Unlock register
+ description: null
+ name: UNLOCK
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ENABLE'
+ start: 0
+ width: 11
+ variants: []
+ brief: |
+ Clock enable register
+ description: null
+ name: CLKEN
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RESET'
+ start: 0
+ width: 11
+ variants: []
+ brief: |
+ Reset register
+ description: null
+ name: RESET
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FOVERRIDE'
+ start: 16
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'OVERRIDE'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ CPU/FPU override register
+ description: null
+ name: OVERRIDE
+ width: 32
+name: grclkgate
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/grethgbit-header.yml b/spec/dev/grlib/if/grethgbit-header.yml
new file mode 100644
index 0000000..8bfd7d7
--- /dev/null
+++ b/spec/dev/grlib/if/grethgbit-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GRETH_GBIT register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: grethgbit
+path: grlib/grethgbit-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/grethgbit.yml b/spec/dev/grlib/if/grethgbit.yml
new file mode 100644
index 0000000..dce8678
--- /dev/null
+++ b/spec/dev/grlib/if/grethgbit.yml
@@ -0,0 +1,406 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRETHGBIT
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: grethgbit-header
+definition:
+- default:
+ count: 1
+ name: CR
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: SR
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: MACMSB
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: MACLSB
+ offset: 0xc
+ variants: []
+- default:
+ count: 1
+ name: MDIO
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: TDTBA
+ offset: 0x14
+ variants: []
+- default:
+ count: 1
+ name: RDTBA
+ offset: 0x18
+ variants: []
+- default:
+ count: 1
+ name: EDCLMACMSB
+ offset: 0x28
+ variants: []
+- default:
+ count: 1
+ name: EDCLMACLSB
+ offset: 0x2c
+ variants: []
+register-prefix: null
+register-block-group: GRETH_GBIT
+register-block-size: 48
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'EA'
+ start: 31
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BS'
+ start: 28
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'GA'
+ start: 27
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MA'
+ start: 26
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MC'
+ start: 25
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ED'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RD'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DD'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ME'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PI'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BM'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'GB'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SP'
+ start: 7
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RS'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PM'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FD'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RI'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TI'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ control register
+ description: null
+ name: CR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PS'
+ start: 8
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'IA'
+ start: 7
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TS'
+ start: 6
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TA'
+ start: 5
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RA'
+ start: 4
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TI'
+ start: 3
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RI'
+ start: 2
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 1
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ status register.
+ description: null
+ name: SR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MSB'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ MAC address MSB.
+ description: null
+ name: MACMSB
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LSB'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ MAC address LSB.
+ description: null
+ name: MACLSB
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PHYADDR'
+ start: 11
+ width: 5
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'REGADDR'
+ start: 6
+ width: 5
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BU'
+ start: 3
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'LF'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RD'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WR'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ MDIO control/status register.
+ description: null
+ name: MDIO
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BASEADDR'
+ start: 10
+ width: 22
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DESCPNT'
+ start: 3
+ width: 7
+ variants: []
+ brief: |
+ transmitter descriptor table base address register.
+ description: null
+ name: TDTBA
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BASEADDR'
+ start: 10
+ width: 22
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DESCPNT'
+ start: 3
+ width: 7
+ variants: []
+ brief: |
+ receiver descriptor table base address register.
+ description: null
+ name: RDTBA
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MSB'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ EDCL MAC address MSB.
+ description: null
+ name: EDCLMACMSB
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LSB'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ EDCL MAC address LSB.
+ description: null
+ name: EDCLMACLSB
+ width: 32
+name: grethgbit
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/grgpio-header.yml b/spec/dev/grlib/if/grgpio-header.yml
new file mode 100644
index 0000000..c020494
--- /dev/null
+++ b/spec/dev/grlib/if/grgpio-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GRGPIO register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: grgpio
+path: grlib/grgpio-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/grgpio.yml b/spec/dev/grlib/if/grgpio.yml
new file mode 100644
index 0000000..9d88c21
--- /dev/null
+++ b/spec/dev/grlib/if/grgpio.yml
@@ -0,0 +1,401 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRGPIO
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: grgpio-header
+definition:
+- default:
+ count: 1
+ name: DATA
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: OUTPUT
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: DIRECTION
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: IMASK
+ offset: 0xc
+ variants: []
+- default:
+ count: 1
+ name: IPOL
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: IEDGE
+ offset: 0x14
+ variants: []
+- default:
+ count: 1
+ name: BYPASS
+ offset: 0x18
+ variants: []
+- default:
+ count: 1
+ name: CAP
+ offset: 0x1c
+ variants: []
+- default:
+ count: 8
+ name: IRQMAPR
+ offset: 0x20
+ variants: []
+- default:
+ count: 1
+ name: IAVAIL
+ offset: 0x40
+ variants: []
+- default:
+ count: 1
+ name: IFLAG
+ offset: 0x44
+ variants: []
+- default:
+ count: 1
+ name: IPEN
+ offset: 0x48
+ variants: []
+- default:
+ count: 1
+ name: PULSE
+ offset: 0x4c
+ variants: []
+- default:
+ count: 1
+ name: LOR:LOR_OUTPUT
+ offset: 0x54
+ variants: []
+- default:
+ count: 1
+ name: LOR:LOR_DIRECTION
+ offset: 0x58
+ variants: []
+- default:
+ count: 1
+ name: LOR:LOR_IMASK
+ offset: 0x5c
+ variants: []
+- default:
+ count: 1
+ name: LAND:LAND_OUTPUT
+ offset: 0x64
+ variants: []
+- default:
+ count: 1
+ name: LAND:LAND_DIRECTION
+ offset: 0x68
+ variants: []
+- default:
+ count: 1
+ name: LAND:LAND_IMASK
+ offset: 0x6c
+ variants: []
+- default:
+ count: 1
+ name: LXOR:LXOR_OUTPUT
+ offset: 0x74
+ variants: []
+- default:
+ count: 1
+ name: LXOR:LXOR_DIRECTION
+ offset: 0x78
+ variants: []
+- default:
+ count: 1
+ name: LXOR:LXOR_IMASK
+ offset: 0x7c
+ variants: []
+register-prefix: null
+register-block-group: GRGPIO
+register-block-size: 128
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ I/O port data register
+ description: null
+ name: DATA
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ I/O port output register
+ description: null
+ name: OUTPUT
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DIR'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ I/O port direction register
+ description: null
+ name: DIRECTION
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Interrupt mask register
+ description: null
+ name: IMASK
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'POL'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Interrupt polarity register
+ description: null
+ name: IPOL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EDGE'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Interrupt edge register
+ description: null
+ name: IEDGE
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BYPASS'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Bypass register
+ description: null
+ name: BYPASS
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PU'
+ start: 18
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IER'
+ start: 17
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IFL'
+ start: 16
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IRQGEN'
+ start: 8
+ width: 5
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NLINES'
+ start: 0
+ width: 5
+ variants: []
+ brief: |
+ Capability register
+ description: null
+ name: CAP
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQMAP_I'
+ start: 24
+ width: 7
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQMAP_I_1'
+ start: 16
+ width: 5
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQMAP_I_2'
+ start: 8
+ width: 5
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQMAP_I_3'
+ start: 4
+ width: 1
+ variants: []
+ brief: |
+ Interrupt map register n, where n = 0 .. 3
+ description: null
+ name: IRQMAPR
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IMASK'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Interrupt available register
+ description: null
+ name: IAVAIL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'IFLAG'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Interrupt flag register
+ description: null
+ name: IFLAG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IPEN'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Interrupt enable register
+ description: null
+ name: IPEN
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PULSE'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Pulse register
+ description: null
+ name: PULSE
+ width: 32
+- bits:
+ - default:
+ - access: [w]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Logical-OR registers
+ description: null
+ name: LOR
+ width: 32
+- bits:
+ - default:
+ - access: [w]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Logical-AND registers
+ description: null
+ name: LAND
+ width: 32
+- bits:
+ - default:
+ - access: [w]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Logical-XOR registers
+ description: null
+ name: LXOR
+ width: 32
+name: grgpio
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/grgprbank-header.yml b/spec/dev/grlib/if/grgprbank-header.yml
new file mode 100644
index 0000000..38604cf
--- /dev/null
+++ b/spec/dev/grlib/if/grgprbank-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GRGPRBANK register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: grgprbank
+path: grlib/grgprbank-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/grgprbank.yml b/spec/dev/grlib/if/grgprbank.yml
new file mode 100644
index 0000000..aaedec5
--- /dev/null
+++ b/spec/dev/grlib/if/grgprbank.yml
@@ -0,0 +1,358 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRGPRBANK
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: grgprbank-header
+definition:
+- default:
+ count: 1
+ name: FTMFUNC
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: ALTFUNC
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: LVDSMCLK
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: PLLNEWCFG
+ offset: 0xc
+ variants: []
+- default:
+ count: 1
+ name: PLLRECFG
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: PLLCURCFG
+ offset: 0x14
+ variants: []
+- default:
+ count: 1
+ name: DRVSTR1
+ offset: 0x18
+ variants: []
+- default:
+ count: 1
+ name: DRVSTR2
+ offset: 0x1c
+ variants: []
+- default:
+ count: 1
+ name: LOCKDOWN
+ offset: 0x20
+ variants: []
+register-prefix: null
+register-block-group: GPRBANK
+register-block-size: 36
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FTMEN'
+ start: 0
+ width: 22
+ variants: []
+ brief: |
+ FTMCTRL function enable register
+ description: null
+ name: FTMFUNC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ALTEN'
+ start: 0
+ width: 22
+ variants: []
+ brief: |
+ Alternative function enable register
+ description: null
+ name: ALTFUNC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SMEM'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DMEM'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SPWOE'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ LVDS and memory clock pad enable register
+ description: null
+ name: LVDSMCLK
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SWTAG'
+ start: 27
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SPWPLLCFG'
+ start: 18
+ width: 9
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MEMPLLCFG'
+ start: 9
+ width: 9
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SYSPLLCFG'
+ start: 0
+ width: 9
+ variants: []
+ brief: |
+ PLL new configuration register
+ description: null
+ name: PLLNEWCFG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RECONF'
+ start: 0
+ width: 3
+ variants: []
+ brief: |
+ PLL reconfigure command register
+ description: null
+ name: PLLRECFG
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SWTAG'
+ start: 27
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SPWPLLCFG'
+ start: 18
+ width: 9
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MEMPLLCFG'
+ start: 9
+ width: 9
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SYSPLLCFG'
+ start: 0
+ width: 9
+ variants: []
+ brief: |
+ PLL current configuration register
+ description: null
+ name: PLLCURCFG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S9'
+ start: 18
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S8'
+ start: 16
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S7'
+ start: 14
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S6'
+ start: 12
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S5'
+ start: 10
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S4'
+ start: 8
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S3'
+ start: 6
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S2'
+ start: 4
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S1'
+ start: 2
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S0'
+ start: 0
+ width: 2
+ variants: []
+ brief: |
+ Drive strength configuration register 1
+ description: null
+ name: DRVSTR1
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S19'
+ start: 18
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S18'
+ start: 16
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S17'
+ start: 14
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S16'
+ start: 12
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S15'
+ start: 10
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S14'
+ start: 8
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S13'
+ start: 6
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S12'
+ start: 4
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S11'
+ start: 2
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'S10'
+ start: 0
+ width: 2
+ variants: []
+ brief: |
+ Drive strength configuration register 2
+ description: null
+ name: DRVSTR2
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PERMANENT'
+ start: 16
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'REVOCABLE'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ Configuration lockdown register
+ description: null
+ name: LOCKDOWN
+ width: 32
+name: grgprbank
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/grgpreg-header.yml b/spec/dev/grlib/if/grgpreg-header.yml
new file mode 100644
index 0000000..039d449
--- /dev/null
+++ b/spec/dev/grlib/if/grgpreg-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GRGPREG register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: grgpreg
+path: grlib/grgpreg-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/grgpreg.yml b/spec/dev/grlib/if/grgpreg.yml
new file mode 100644
index 0000000..5ec8f6f
--- /dev/null
+++ b/spec/dev/grlib/if/grgpreg.yml
@@ -0,0 +1,104 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRGPREG
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: grgpreg-header
+definition:
+- default:
+ count: 1
+ name: BOOTSTRAP
+ offset: 0x0
+ variants: []
+register-prefix: null
+register-block-group: GRGPREG
+register-block-size: 4
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'B10'
+ start: 25
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'B9'
+ start: 24
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'B8'
+ start: 23
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'B7'
+ start: 22
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'B6'
+ start: 21
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'B5'
+ start: 20
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'B4'
+ start: 19
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'B3'
+ start: 18
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'B2'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'B1'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'GPIO'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Bootstrap register
+ description: null
+ name: BOOTSTRAP
+ width: 32
+name: grgpreg
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/griommu-header.yml b/spec/dev/grlib/if/griommu-header.yml
new file mode 100644
index 0000000..df84a37
--- /dev/null
+++ b/spec/dev/grlib/if/griommu-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GRIOMMU register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: griommu
+path: grlib/griommu-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/griommu.yml b/spec/dev/grlib/if/griommu.yml
new file mode 100644
index 0000000..567d4fb
--- /dev/null
+++ b/spec/dev/grlib/if/griommu.yml
@@ -0,0 +1,721 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRIOMMU
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: griommu-header
+definition:
+- default:
+ count: 1
+ name: CAP0
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: CAP1
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: CAP2
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: CTRL
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: FLUSH
+ offset: 0x14
+ variants: []
+- default:
+ count: 1
+ name: STATUS
+ offset: 0x18
+ variants: []
+- default:
+ count: 1
+ name: IMASK
+ offset: 0x1c
+ variants: []
+- default:
+ count: 1
+ name: AHBFAS
+ offset: 0x20
+ variants: []
+- default:
+ count: 1
+ name: MSTCFG
+ offset: 0x40
+ variants: []
+- default:
+ count: 1
+ name: MSTCFG
+ offset: 0x64
+ variants: []
+- default:
+ count: 1
+ name: GRPCTRL
+ offset: 0x80
+ variants: []
+- default:
+ count: 1
+ name: GRPCTRL
+ offset: 0x9c
+ variants: []
+- default:
+ count: 1
+ name: DIAGCTRL
+ offset: 0xc0
+ variants: []
+- default:
+ count: 1
+ name: DIAGD
+ offset: 0xc4
+ variants: []
+- default:
+ count: 1
+ name: DIAGD
+ offset: 0xe0
+ variants: []
+- default:
+ count: 1
+ name: DIAGT
+ offset: 0xe4
+ variants: []
+- default:
+ count: 1
+ name: DERRI
+ offset: 0xe8
+ variants: []
+- default:
+ count: 1
+ name: TERRI
+ offset: 0xec
+ variants: []
+- default:
+ count: 1
+ name: ASMPCTRL
+ offset: 0x100
+ variants: []
+- default:
+ count: 1
+ name: ASMPCTRL
+ offset: 0x10c
+ variants: []
+register-prefix: null
+register-block-group: GRIOMMU
+register-block-size: 272
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'A'
+ start: 31
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AC'
+ start: 30
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CA'
+ start: 29
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CP'
+ start: 28
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NARB'
+ start: 20
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CS'
+ start: 19
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'FT'
+ start: 17
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ST'
+ start: 16
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'I'
+ start: 15
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IT'
+ start: 14
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IA'
+ start: 13
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IP'
+ start: 12
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MB'
+ start: 8
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'GRPS'
+ start: 4
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MSTS'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ Capability register 0
+ description: null
+ name: CAP0
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CADDR'
+ start: 20
+ width: 12
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CMASK'
+ start: 16
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CTAGBITS'
+ start: 8
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CISIZE'
+ start: 5
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CLINES'
+ start: 0
+ width: 5
+ variants: []
+ brief: |
+ Capability register 1
+ description: null
+ name: CAP1
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TMASK'
+ start: 24
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MTYPE'
+ start: 18
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TTYPE'
+ start: 16
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TTAGBITS'
+ start: 8
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ISIZE'
+ start: 5
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TLBENT'
+ start: 0
+ width: 5
+ variants: []
+ brief: |
+ Capability register 2
+ description: null
+ name: CAP2
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PGSZ'
+ start: 18
+ width: 3
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LB'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SP'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ITR'
+ start: 12
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DP'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SIV'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'HPROT'
+ start: 8
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AU'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WP'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DM'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'GS'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CE'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PM'
+ start: 1
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Control register
+ description: null
+ name: CTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FGRP'
+ start: 4
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'GF'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'F'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ TLB/cache flush register
+ description: null
+ name: FLUSH
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 5
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'DE'
+ start: 4
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'FC'
+ start: 3
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'FL'
+ start: 2
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'AD'
+ start: 1
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Status register
+ description: null
+ name: STATUS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PEI'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FCI'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FLI'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ADI'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TEI'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Interrupt mask register
+ description: null
+ name: IMASK
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'FADDR_31_5'
+ start: 5
+ width: 27
+ - access: [r]
+ brief: null
+ description: null
+ name: 'FW'
+ start: 4
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'FMASTER'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ AHB failing access register
+ description: null
+ name: AHBFAS
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'VENDOR'
+ start: 24
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DEVICE'
+ start: 12
+ width: 12
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BS'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'GROUP'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ Master configuration register 0 - 9
+ description: null
+ name: MSTCFG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BASE_31_4'
+ start: 4
+ width: 28
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'P'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AG'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Group control register 0 - 7
+ description: null
+ name: GRPCTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DA'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RW'
+ start: 30
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DP'
+ start: 21
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TP'
+ start: 20
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SETADDR'
+ start: 0
+ width: 19
+ variants: []
+ brief: |
+ Diagnostic cache access register
+ description: null
+ name: DIAGCTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CDATAN'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Diagnostic cache access data register 0 - 7
+ description: null
+ name: DIAGD
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TAG'
+ start: 1
+ width: 31
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'V'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Diagnostic cache access tag register
+ description: null
+ name: DIAGT
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DPERRINJ'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Data RAM error injection register
+ description: null
+ name: DERRI
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TPERRINJ'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Tag RAM error injection register
+ description: null
+ name: TERRI
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FC'
+ start: 18
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SC'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MC'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'GRPACCSZCTRL'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ ASMP access control registers 0 - 3
+ description: null
+ name: ASMPCTRL
+ width: 32
+name: griommu
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/group.yml b/spec/dev/grlib/if/group.yml
new file mode 100644
index 0000000..8f7465e
--- /dev/null
+++ b/spec/dev/grlib/if/group.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This group contains the GRLIB API.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIB
+index-entries: []
+interface-type: group
+links:
+- role: interface-placement
+ uid: gptimer-header
+- role: interface-ingroup
+ uid: /if/group
+name: GRLIB
+text: |
+ The RTEMS API shall provide an interface to the GRLIB register blocks.
+type: interface
diff --git a/spec/dev/grlib/if/grpci2-header.yml b/spec/dev/grlib/if/grpci2-header.yml
new file mode 100644
index 0000000..cabb453
--- /dev/null
+++ b/spec/dev/grlib/if/grpci2-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GRPCI2 register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: grpci2
+path: grlib/grpci2-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/grpci2.yml b/spec/dev/grlib/if/grpci2.yml
new file mode 100644
index 0000000..b08f5ac
--- /dev/null
+++ b/spec/dev/grlib/if/grpci2.yml
@@ -0,0 +1,862 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRPCI2
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: grpci2-header
+definition:
+- default:
+ count: 1
+ name: CTRL
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: STATCAP
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: BCIM
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: AHB2PCI
+ offset: 0xc
+ variants: []
+- default:
+ count: 1
+ name: DMACTRL
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: DMABASE
+ offset: 0x14
+ variants: []
+- default:
+ count: 1
+ name: DMACHAN
+ offset: 0x18
+ variants: []
+- default:
+ count: 1
+ name: PCI2AHB
+ offset: 0x20
+ variants: []
+- default:
+ count: 1
+ name: PCI2AHB
+ offset: 0x34
+ variants: []
+- default:
+ count: 1
+ name: AHBM2PCI
+ offset: 0x40
+ variants: []
+- default:
+ count: 1
+ name: AHBM2PCI
+ offset: 0x7c
+ variants: []
+- default:
+ count: 1
+ name: TCTRC
+ offset: 0x80
+ variants: []
+- default:
+ count: 1
+ name: TMODE
+ offset: 0x84
+ variants: []
+- default:
+ count: 1
+ name: TADP
+ offset: 0x88
+ variants: []
+- default:
+ count: 1
+ name: TADM
+ offset: 0x8c
+ variants: []
+- default:
+ count: 1
+ name: TCP
+ offset: 0x90
+ variants: []
+- default:
+ count: 1
+ name: TCM
+ offset: 0x94
+ variants: []
+- default:
+ count: 1
+ name: TADS
+ offset: 0x98
+ variants: []
+- default:
+ count: 1
+ name: TCS
+ offset: 0x9c
+ variants: []
+register-prefix: null
+register-block-group: GRPCI2
+register-block-size: 160
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MR'
+ start: 30
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TR'
+ start: 29
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SI'
+ start: 27
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 26
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ER'
+ start: 25
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EI'
+ start: 24
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BUS_NUMBER'
+ start: 16
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DFA'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IB'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CB'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DIF'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DEVICE_INT_MASK'
+ start: 4
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'HOST_INT_MASK'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ Control register
+ description: null
+ name: CTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'HOST'
+ start: 31
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MST'
+ start: 30
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TAR'
+ start: 29
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DMA'
+ start: 28
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DI'
+ start: 27
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'HI'
+ start: 26
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IRQ_MODE'
+ start: 24
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TRACE'
+ start: 23
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'CFGDO'
+ start: 20
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'CFGER'
+ start: 19
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'CORE_INT_STATUS'
+ start: 12
+ width: 7
+ - access: [r]
+ brief: null
+ description: null
+ name: 'HOST_INT_STATUS'
+ start: 8
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'FDEPTH'
+ start: 2
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'FNUM'
+ start: 0
+ width: 2
+ variants: []
+ brief: |
+ Status and Capability register
+ description: null
+ name: STATCAP
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AHB_MASTER_UNMASK'
+ start: 16
+ width: 16
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BURST_LENGTH'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ PCI master prefetch burst limit
+ description: null
+ name: BCIM
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AHB_TO_PCI_IO'
+ start: 16
+ width: 16
+ variants: []
+ brief: |
+ AHB to PCI mapping for PCI IO
+ description: null
+ name: AHB2PCI
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SAFE'
+ start: 31
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'CHIRQ'
+ start: 12
+ width: 8
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'MA'
+ start: 11
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TA'
+ start: 10
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 9
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'AE'
+ start: 8
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'DE'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'NUMCH'
+ start: 4
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ACTIVE'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DIS'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ DMA control and status register
+ description: null
+ name: DMACTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BASE'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ DMA descriptor base address register
+ description: null
+ name: DMABASE
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CHAN'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ DMA channel active register
+ description: null
+ name: DMACHAN
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ADDR'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ PCI BAR to AHB address mapping register
+ description: null
+ name: PCI2AHB
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ADDR'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ AHB master to PCI memory address mapping register
+ description: null
+ name: AHBM2PCI
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TRIG_INDEX'
+ start: 16
+ width: 16
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AR'
+ start: 15
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 14
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DEPTH'
+ start: 4
+ width: 8
+ - access: [w]
+ brief: null
+ description: null
+ name: 'SO'
+ start: 1
+ width: 1
+ - access: [w]
+ brief: null
+ description: null
+ name: 'SA'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ PCI trace Control and Status register
+ description: null
+ name: TCTRC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TRACING_MODE'
+ start: 24
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TRIG_COUNT'
+ start: 16
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DELAYED_STOP'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ PCI trace counter and mode register
+ description: null
+ name: TMODE
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PATTERN'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ PCI trace AD pattern register
+ description: null
+ name: TADP
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ PCI trace AD mask register
+ description: null
+ name: TADM
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CBE_3_0'
+ start: 16
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FRAME'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRDY'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TRDY'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'STOP'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DEVSEL'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PAR'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PERR'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SERR'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IDSEL'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'REQ'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'GNT'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LOCK'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RST'
+ start: 3
+ width: 1
+ variants: []
+ brief: |
+ PCI trace Ctrl signal pattern register
+ description: null
+ name: TCP
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CBE_3_0'
+ start: 16
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FRAME'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRDY'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TRDY'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'STOP'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DEVSEL'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PAR'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PERR'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SERR'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IDSEL'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'REQ'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'GNT'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LOCK'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RST'
+ start: 3
+ width: 1
+ variants: []
+ brief: |
+ PCI trace Ctrl signal mask register
+ description: null
+ name: TCM
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SIGNAL'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ PCI trace PCI AD state register
+ description: null
+ name: TADS
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CBE_3_0'
+ start: 16
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'FRAME'
+ start: 15
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IRDY'
+ start: 14
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TRDY'
+ start: 13
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'STOP'
+ start: 12
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DEVSEL'
+ start: 11
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PAR'
+ start: 10
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PERR'
+ start: 9
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SERR'
+ start: 8
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IDSEL'
+ start: 7
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'REQ'
+ start: 6
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'GNT'
+ start: 5
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'LOCK'
+ start: 4
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RST'
+ start: 3
+ width: 1
+ variants: []
+ brief: |
+ PCI trace PCI Ctrl signal state register
+ description: null
+ name: TCS
+ width: 32
+name: grpci2
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/grspw2-header.yml b/spec/dev/grlib/if/grspw2-header.yml
new file mode 100644
index 0000000..1959aae
--- /dev/null
+++ b/spec/dev/grlib/if/grspw2-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GRSPW2 register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: grspw2
+path: grlib/grspw2-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/grspw2.yml b/spec/dev/grlib/if/grspw2.yml
new file mode 100644
index 0000000..f3723f6
--- /dev/null
+++ b/spec/dev/grlib/if/grspw2.yml
@@ -0,0 +1,564 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRSPW2
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: grspw2-header
+definition:
+- default:
+ count: 1
+ name: CTRL
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: STS
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: DEFADDR
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: CLKDIV
+ offset: 0xc
+ variants: []
+- default:
+ count: 1
+ name: DKEY
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: TC
+ offset: 0x14
+ variants: []
+- default:
+ count: 1
+ name: DMACTRL
+ offset: 0x20
+ variants: []
+- default:
+ count: 1
+ name: DMAMAXLEN
+ offset: 0x24
+ variants: []
+- default:
+ count: 1
+ name: DMATXDESC
+ offset: 0x28
+ variants: []
+- default:
+ count: 1
+ name: DMARXDESC
+ offset: 0x2c
+ variants: []
+- default:
+ count: 1
+ name: DMAADDR
+ offset: 0x30
+ variants: []
+register-prefix: null
+register-block-group: GRSPW2
+register-block-size: 52
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RA'
+ start: 31
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RX'
+ start: 30
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RC'
+ start: 29
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NCH'
+ start: 27
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PO'
+ start: 26
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RD'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TL'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TF'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TR'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TT'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LI'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TQ'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RS'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PM'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TI'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IE'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AS'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LS'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LD'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Control
+ description: null
+ name: CTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NRXD'
+ start: 26
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NTXD'
+ start: 24
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'LS'
+ start: 21
+ width: 3
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'EE'
+ start: 8
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'IA'
+ start: 7
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 4
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'DE'
+ start: 3
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'ER'
+ start: 2
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'CE'
+ start: 1
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TO'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Status
+ description: null
+ name: STS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DEFMASK'
+ start: 8
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DEFADDR'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ Default address
+ description: null
+ name: DEFADDR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CLKDIVSTART'
+ start: 8
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CLKDIVRUN'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ Clock divisor
+ description: null
+ name: CLKDIV
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DESTKEY'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ Destination key
+ description: null
+ name: DKEY
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TCTRL'
+ start: 6
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TIMECNT'
+ start: 0
+ width: 6
+ variants: []
+ brief: |
+ Time-code
+ description: null
+ name: TC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'EP'
+ start: 23
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TR'
+ start: 22
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RP'
+ start: 19
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TP'
+ start: 18
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TL'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LE'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SP'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SA'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'NS'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RD'
+ start: 11
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RX'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AT'
+ start: 9
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RA'
+ start: 8
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TA'
+ start: 7
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PR'
+ start: 6
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PS'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AI'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RI'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TI'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ DMA control/status, channel 1
+ description: null
+ name: DMACTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RXMAXLEN'
+ start: 2
+ width: 23
+ variants: []
+ brief: |
+ DMA RX maximum length, channel 1
+ description: null
+ name: DMAMAXLEN
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DESCBASEADDR'
+ start: 10
+ width: 22
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DESCSEL'
+ start: 4
+ width: 6
+ variants: []
+ brief: |
+ DMA transmitter descriptor table address, channel 1
+ description: null
+ name: DMATXDESC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DESCBASEADDR'
+ start: 10
+ width: 22
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DESCSEL'
+ start: 3
+ width: 7
+ variants: []
+ brief: |
+ DMA receiver descriptor table address, channel 1
+ description: null
+ name: DMARXDESC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 8
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ADDR'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ DMA address, channel 1
+ description: null
+ name: DMAADDR
+ width: 32
+name: grspw2
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/grspwrouter-header.yml b/spec/dev/grlib/if/grspwrouter-header.yml
new file mode 100644
index 0000000..9dfd072
--- /dev/null
+++ b/spec/dev/grlib/if/grspwrouter-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the GRSPWROUTER register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: grspwrouter
+path: grlib/grspwrouter-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/grspwrouter.yml b/spec/dev/grlib/if/grspwrouter.yml
new file mode 100644
index 0000000..cd7f9d3
--- /dev/null
+++ b/spec/dev/grlib/if/grspwrouter.yml
@@ -0,0 +1,771 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRSPWROUTER
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: grspwrouter-header
+definition:
+- default:
+ count: 1
+ name: AMBACTRL
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: AMBASTS
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: AMBADEFADDR
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: AMBADKEY
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: AMBATC
+ offset: 0x14
+ variants: []
+- default:
+ count: 1
+ name: AMBADMACTRL
+ offset: 0x20
+ variants: []
+- default:
+ count: 1
+ name: AMBADMAMAXLEN
+ offset: 0x24
+ variants: []
+- default:
+ count: 1
+ name: AMBADMATXDESC
+ offset: 0x28
+ variants: []
+- default:
+ count: 1
+ name: AMBADMARXDESC
+ offset: 0x2c
+ variants: []
+- default:
+ count: 1
+ name: AMBADMAADDR
+ offset: 0x30
+ variants: []
+- default:
+ count: 1
+ name: AMBADMACTRL
+ offset: 0x40
+ variants: []
+- default:
+ count: 1
+ name: AMBADMAMAXLEN
+ offset: 0x44
+ variants: []
+- default:
+ count: 1
+ name: AMBADMATXDESC
+ offset: 0x48
+ variants: []
+- default:
+ count: 1
+ name: AMBADMARXDESC
+ offset: 0x4c
+ variants: []
+- default:
+ count: 1
+ name: AMBADMAADDR
+ offset: 0x50
+ variants: []
+- default:
+ count: 1
+ name: AMBADMACTRL
+ offset: 0x60
+ variants: []
+- default:
+ count: 1
+ name: AMBADMAMAXLEN
+ offset: 0x64
+ variants: []
+- default:
+ count: 1
+ name: AMBADMATXDESC
+ offset: 0x68
+ variants: []
+- default:
+ count: 1
+ name: AMBADMARXDESC
+ offset: 0x6c
+ variants: []
+- default:
+ count: 1
+ name: AMBADMAADDR
+ offset: 0x70
+ variants: []
+- default:
+ count: 1
+ name: AMBADMACTRL
+ offset: 0x80
+ variants: []
+- default:
+ count: 1
+ name: AMBADMAMAXLEN
+ offset: 0x84
+ variants: []
+- default:
+ count: 1
+ name: AMBADMATXDESC
+ offset: 0x88
+ variants: []
+- default:
+ count: 1
+ name: AMBADMARXDESC
+ offset: 0x8c
+ variants: []
+- default:
+ count: 1
+ name: AMBADMAADDR
+ offset: 0x90
+ variants: []
+- default:
+ count: 1
+ name: AMBAINTCTRL
+ offset: 0xa0
+ variants: []
+- default:
+ count: 1
+ name: AMBAINTRX
+ offset: 0xa4
+ variants: []
+- default:
+ count: 1
+ name: AMBAACKRX
+ offset: 0xa8
+ variants: []
+- default:
+ count: 1
+ name: AMBAINTTO0
+ offset: 0xac
+ variants: []
+- default:
+ count: 1
+ name: AMBAINTTO1
+ offset: 0xb0
+ variants: []
+- default:
+ count: 1
+ name: AMBAINTMSK0
+ offset: 0xb4
+ variants: []
+- default:
+ count: 1
+ name: AMBAINTMSK1
+ offset: 0xb8
+ variants: []
+register-prefix: null
+register-block-group: GRSPWROUTER
+register-block-size: 188
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RA'
+ start: 31
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RX'
+ start: 30
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RC'
+ start: 29
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NCH'
+ start: 27
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DI'
+ start: 24
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ME'
+ start: 23
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RD'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TQ'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RS'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PM'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TI'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IE'
+ start: 3
+ width: 1
+ variants: []
+ brief: |
+ AMBA port Control
+ description: null
+ name: AMBACTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NIRQ'
+ start: 28
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NRXD'
+ start: 26
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NTXD'
+ start: 24
+ width: 2
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'ME'
+ start: 12
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'EE'
+ start: 8
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'IA'
+ start: 7
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TO'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ AMBA port Status
+ description: null
+ name: AMBASTS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DEFMASK'
+ start: 8
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DEFADDR'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ AMBA port Default address
+ description: null
+ name: AMBADEFADDR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DESTKEY'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ AMBA port Destination key
+ description: null
+ name: AMBADKEY
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TCMSK'
+ start: 24
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TCVAL'
+ start: 16
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TCTRL'
+ start: 6
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TIMECNT'
+ start: 0
+ width: 6
+ variants: []
+ brief: |
+ AMBA port Time-code
+ description: null
+ name: AMBATC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'INTNUM'
+ start: 26
+ width: 6
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'EP'
+ start: 23
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TR'
+ start: 22
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IE'
+ start: 21
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IT'
+ start: 20
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RP'
+ start: 19
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TP'
+ start: 18
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SP'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SA'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'NS'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RD'
+ start: 11
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RX'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AT'
+ start: 9
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RA'
+ start: 8
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TA'
+ start: 7
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PR'
+ start: 6
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PS'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AI'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RI'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TI'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ AMBA port DMA control/status
+ description: null
+ name: AMBADMACTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RXMAXLEN'
+ start: 2
+ width: 23
+ variants: []
+ brief: |
+ AMBA port DMA RX maximum length
+ description: null
+ name: AMBADMAMAXLEN
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DESCBASEADDR'
+ start: 10
+ width: 22
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DESCSEL'
+ start: 4
+ width: 6
+ variants: []
+ brief: |
+ AMBA port DMA transmit descriptor table address
+ description: null
+ name: AMBADMATXDESC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DESCBASEADDR'
+ start: 10
+ width: 22
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DESCSEL'
+ start: 3
+ width: 7
+ variants: []
+ brief: |
+ AMBA port DMA receive descriptor table address
+ description: null
+ name: AMBADMARXDESC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 8
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ADDR'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ AMBA port DMA address
+ description: null
+ name: AMBADMAADDR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'INTNUM'
+ start: 26
+ width: 6
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EE'
+ start: 24
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IA'
+ start: 23
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TQ'
+ start: 20
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AQ'
+ start: 19
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IQ'
+ start: 18
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AA'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AT'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IT'
+ start: 13
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'ID'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'II'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TXINT'
+ start: 0
+ width: 6
+ variants: []
+ brief: |
+ AMBA port Distributed interrupt control
+ description: null
+ name: AMBAINTCTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RXIRQ'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ AMBA port Interrupt receive
+ description: null
+ name: AMBAINTRX
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RXACK'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ AMBA port Interrupt acknowledgement / extended interrupt receive
+ description: null
+ name: AMBAACKRX
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'INTTO'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ AMBA port Interrupt timeout, interrupt 0-31
+ description: null
+ name: AMBAINTTO0
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'INTTO'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ AMBA port Interrupt timeout, interrupt 32-63
+ description: null
+ name: AMBAINTTO1
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ AMBA port Interrupt mask, interrupt 0-31
+ description: null
+ name: AMBAINTMSK0
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ AMBA port Interrupt mask, interrupt 32-63
+ description: null
+ name: AMBAINTMSK1
+ width: 32
+name: grspwrouter
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/irqamp-header.yml b/spec/dev/grlib/if/irqamp-header.yml
new file mode 100644
index 0000000..9d79a2c
--- /dev/null
+++ b/spec/dev/grlib/if/irqamp-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the IRQAMP register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: irqamp
+path: grlib/irqamp-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/irqamp-timestamp.yml b/spec/dev/grlib/if/irqamp-timestamp.yml
new file mode 100644
index 0000000..54b4835
--- /dev/null
+++ b/spec/dev/grlib/if/irqamp-timestamp.yml
@@ -0,0 +1,125 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBIRQAMPTimestamp
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: irqamp
+- role: interface-placement
+ uid: irqamp-header
+definition:
+- default:
+ count: 1
+ name: ITCNT
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: ITSTMPC
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: ITSTMPAS
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: ITSTMPAC
+ offset: 0xc
+ variants: []
+register-prefix: IRQAMP
+register-block-group: IRQ(A)MP Timestamp
+register-block-size: 16
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TCNT'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Interrupt timestamp counter n register
+ description: null
+ name: ITCNT
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TSTAMP'
+ start: 27
+ width: 5
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'S1'
+ start: 26
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'S2'
+ start: 25
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'KS'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TSISEL'
+ start: 0
+ width: 5
+ variants: []
+ brief: |
+ Interrupt timestamp n control register
+ description: null
+ name: ITSTMPC
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TASSERTION'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Interrupt Assertion Timestamp n register
+ description: null
+ name: ITSTMPAS
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TACKNOWLEDGE'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Interrupt Acknowledge Timestamp n register
+ description: null
+ name: ITSTMPAC
+ width: 32
+name: irqamp_timestamp
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/irqamp.yml b/spec/dev/grlib/if/irqamp.yml
new file mode 100644
index 0000000..5639316
--- /dev/null
+++ b/spec/dev/grlib/if/irqamp.yml
@@ -0,0 +1,432 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBIRQAMP
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: irqamp-header
+- name: ITSTMP
+ role: register-block-include
+ uid: irqamp-timestamp
+definition:
+- default:
+ count: 1
+ name: ILEVEL
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: IPEND
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: IFORCE0
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: ICLEAR
+ offset: 0xc
+ variants: []
+- default:
+ count: 1
+ name: MPSTAT
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: BRDCST
+ offset: 0x14
+ variants: []
+- default:
+ count: 1
+ name: ERRSTAT
+ offset: 0x18
+ variants: []
+- default:
+ count: 1
+ name: WDOGCTRL
+ offset: 0x1c
+ variants: []
+- default:
+ count: 1
+ name: ASMPCTRL
+ offset: 0x20
+ variants: []
+- default:
+ count: 2
+ name: ICSELR
+ offset: 0x24
+ variants: []
+- default:
+ count: 16
+ name: PIMASK
+ offset: 0x40
+ variants: []
+- default:
+ count: 16
+ name: PIFORCE
+ offset: 0x80
+ variants: []
+- default:
+ count: 16
+ name: PEXTACK
+ offset: 0xc0
+ variants: []
+- default:
+ count: 16
+ name: ITSTMP
+ offset: 0x100
+ variants: []
+- default:
+ count: 16
+ name: BADDR
+ offset: 0x200
+ variants: []
+- default:
+ count: 16
+ name: IRQMAP
+ offset: 0x300
+ variants: []
+register-prefix: null
+register-block-group: IRQ(A)MP
+register-block-size: 1024
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IL_15_1'
+ start: 1
+ width: 15
+ variants: []
+ brief: |
+ Interrupt level register
+ description: null
+ name: ILEVEL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EIP_31_16'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IP_15_1'
+ start: 1
+ width: 15
+ variants: []
+ brief: |
+ Interrupt pending register
+ description: null
+ name: IPEND
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IF_15_1'
+ start: 1
+ width: 15
+ variants: []
+ brief: |
+ Interrupt force register for processor 0
+ description: null
+ name: IFORCE0
+ width: 32
+- bits:
+ - default:
+ - access: [w]
+ brief: null
+ description: null
+ name: 'EIC_31_16'
+ start: 16
+ width: 16
+ - access: [w]
+ brief: null
+ description: null
+ name: 'IC_15_1'
+ start: 1
+ width: 15
+ variants: []
+ brief: |
+ Interrupt clear register
+ description: null
+ name: ICLEAR
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NCPU'
+ start: 28
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BA'
+ start: 27
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ER'
+ start: 26
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'EIRQ'
+ start: 16
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'STATUS'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ Multiprocessor status register
+ description: null
+ name: MPSTAT
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BM15_1'
+ start: 1
+ width: 15
+ variants: []
+ brief: |
+ Broadcast register
+ description: null
+ name: BRDCST
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ERRMODE_3_0'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ Error Mode Status Register
+ description: null
+ name: ERRSTAT
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NWDOG'
+ start: 27
+ width: 5
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WDOGIRQ'
+ start: 16
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WDOGMSK'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ Watchdog control register
+ description: null
+ name: WDOGCTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NCTRL'
+ start: 28
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ICF'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'L'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Asymmetric multiprocessing control register
+ description: null
+ name: ASMPCTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ICSEL0'
+ start: 28
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ICSEL1'
+ start: 24
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ICSEL2'
+ start: 20
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ICSEL3'
+ start: 16
+ width: 4
+ variants: []
+ brief: |
+ Interrupt controller select register
+ description: null
+ name: ICSELR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EIM_31_16'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IM15_1'
+ start: 1
+ width: 15
+ variants: []
+ brief: |
+ Processor n interrupt mask register
+ description: null
+ name: PIMASK
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'FC_15_1'
+ start: 17
+ width: 15
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IF15_1'
+ start: 1
+ width: 15
+ variants: []
+ brief: |
+ Processor n interrupt force register
+ description: null
+ name: PIFORCE
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'EID_4_0'
+ start: 0
+ width: 5
+ variants: []
+ brief: |
+ Processor n extended interrupt acknowledge register
+ description: null
+ name: PEXTACK
+ width: 32
+- bits:
+ - default:
+ - access: [w]
+ brief: null
+ description: null
+ name: 'BOOTADDR_31_3'
+ start: 3
+ width: 29
+ - access: [w]
+ brief: null
+ description: null
+ name: 'AS'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Processor n Boot Address register
+ description: null
+ name: BADDR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQMAP_4_N_0'
+ start: 24
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQMAP_4_N_1'
+ start: 16
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQMAP_4_N_2'
+ start: 8
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQMAP_4_N_3'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ Interrupt map register n
+ description: null
+ name: IRQMAP
+ width: 32
+name: irqamp
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/l2cache-header.yml b/spec/dev/grlib/if/l2cache-header.yml
new file mode 100644
index 0000000..4bdc950
--- /dev/null
+++ b/spec/dev/grlib/if/l2cache-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the L2CACHE register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: l2cache
+path: grlib/l2cache-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/l2cache.yml b/spec/dev/grlib/if/l2cache.yml
new file mode 100644
index 0000000..2f4d4cd
--- /dev/null
+++ b/spec/dev/grlib/if/l2cache.yml
@@ -0,0 +1,669 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBL2CACHE
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: l2cache-header
+definition:
+- default:
+ count: 1
+ name: L2CC
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: L2CS
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: L2CFMA
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: L2CFSI
+ offset: 0xc
+ variants: []
+- default:
+ count: 1
+ name: L2CERR
+ offset: 0x20
+ variants: []
+- default:
+ count: 1
+ name: L2CERRA
+ offset: 0x24
+ variants: []
+- default:
+ count: 1
+ name: L2CTCB
+ offset: 0x28
+ variants: []
+- default:
+ count: 1
+ name: L2CCB
+ offset: 0x2c
+ variants: []
+- default:
+ count: 1
+ name: L2CSCRUB
+ offset: 0x30
+ variants: []
+- default:
+ count: 1
+ name: L2CSDEL
+ offset: 0x34
+ variants: []
+- default:
+ count: 1
+ name: L2CEINJ
+ offset: 0x38
+ variants: []
+- default:
+ count: 1
+ name: L2CACCC
+ offset: 0x3c
+ variants: []
+- default:
+ count: 1
+ name: L2CEINJCFG
+ offset: 0x4c
+ variants: []
+- default:
+ count: 1
+ name: L2CMTRR
+ offset: 0x80
+ variants: []
+register-prefix: null
+register-block-group: L2CACHE
+register-block-size: 132
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EDAC'
+ start: 30
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'REPL'
+ start: 28
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BBS'
+ start: 16
+ width: 3
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'INDEX_WAY'
+ start: 12
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LOCK'
+ start: 8
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'HPRHB'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'HPB'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'UC'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'HC'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WP'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'HP'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ L2C Control register
+ description: null
+ name: L2CC
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'LS'
+ start: 24
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AT'
+ start: 23
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MP'
+ start: 22
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MTRR'
+ start: 16
+ width: 6
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BBUS_W'
+ start: 13
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'WAY_SIZE'
+ start: 2
+ width: 11
+ - access: [r]
+ brief: null
+ description: null
+ name: 'WAY'
+ start: 0
+ width: 2
+ variants: []
+ brief: |
+ L2C Status register
+ description: null
+ name: L2CS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ADDR'
+ start: 5
+ width: 27
+ - access: [w]
+ brief: null
+ description: null
+ name: 'DI'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FMODE'
+ start: 0
+ width: 3
+ variants: []
+ brief: |
+ L2C Flush (Memory address) register
+ description: null
+ name: L2CFMA
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'INDEX'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TAG'
+ start: 10
+ width: 22
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FL'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'VB'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DB'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WAY'
+ start: 4
+ width: 2
+ - access: [w]
+ brief: null
+ description: null
+ name: 'DI'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WF'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FMODE'
+ start: 0
+ width: 2
+ variants: []
+ brief: |
+ L2C Flush (Set, Index) register
+ description: null
+ name: L2CFSI
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AHB_MASTER_INDEX'
+ start: 28
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SCRUB'
+ start: 27
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TYPE'
+ start: 24
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TAG_DATA'
+ start: 23
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'COR_UCOR'
+ start: 22
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MULTI'
+ start: 21
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'VALID'
+ start: 20
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DISERESP'
+ start: 19
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CORRECTABLE_ERROR_COUNTER'
+ start: 16
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IRQ_PENDING'
+ start: 12
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQ_MASK'
+ start: 8
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SELECT_CB'
+ start: 6
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SELECT_TCB'
+ start: 4
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'XCB'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RCB'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'COMP'
+ start: 1
+ width: 1
+ - access: [w]
+ brief: null
+ description: null
+ name: 'RST'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ L2CError status/control register
+ description: null
+ name: L2CERR
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'EADDR'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ L2C Error address register
+ description: null
+ name: L2CERRA
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TCB'
+ start: 0
+ width: 7
+ variants: []
+ brief: |
+ L2C TAG-Check-Bits register
+ description: null
+ name: L2CTCB
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CB'
+ start: 0
+ width: 28
+ variants: []
+ brief: |
+ L2C Data-Check-Bits register
+ description: null
+ name: L2CCB
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'INDEX'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WAY'
+ start: 2
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PEN'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ L2C Scrub control/status register
+ description: null
+ name: L2CSCRUB
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DEL'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ L2C Scrub delay register
+ description: null
+ name: L2CSDEL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ADDR'
+ start: 2
+ width: 30
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'INJ'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ L2C Error injection register
+ description: null
+ name: L2CEINJ
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DSC'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SH'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SPLITQ'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'NHM'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BERR'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'OAPM'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FLINE'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DBPF'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: '128WF'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DBPWS'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SPLIT'
+ start: 1
+ width: 1
+ variants: []
+ brief: |
+ L2C Access control register
+ description: null
+ name: L2CACCC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EDI'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TER'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IMD'
+ start: 8
+ width: 1
+ variants: []
+ brief: |
+ L2C injection configuration register
+ description: null
+ name: L2CEINJCFG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ADDR'
+ start: 18
+ width: 14
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ACC'
+ start: 16
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MASK'
+ start: 2
+ width: 14
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WP'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AC'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ L2C Memory type range register
+ description: null
+ name: L2CMTRR
+ width: 32
+name: l2cache
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/l4stat-header.yml b/spec/dev/grlib/if/l4stat-header.yml
new file mode 100644
index 0000000..ffd0aa1
--- /dev/null
+++ b/spec/dev/grlib/if/l4stat-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the L4STAT register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: l4stat
+path: grlib/l4stat-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/l4stat.yml b/spec/dev/grlib/if/l4stat.yml
new file mode 100644
index 0000000..800cb15
--- /dev/null
+++ b/spec/dev/grlib/if/l4stat.yml
@@ -0,0 +1,194 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBL4STAT
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: l4stat-header
+definition:
+- default:
+ count: 1
+ name: CVAL
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: CVAL
+ offset: 0x3c
+ variants: []
+- default:
+ count: 1
+ name: CCTRL
+ offset: 0x80
+ variants: []
+- default:
+ count: 1
+ name: CCTRL
+ offset: 0xcc
+ variants: []
+- default:
+ count: 1
+ name: CSVAL
+ offset: 0x100
+ variants: []
+- default:
+ count: 1
+ name: CSVAL
+ offset: 0x13c
+ variants: []
+- default:
+ count: 1
+ name: TSTAMP
+ offset: 0x180
+ variants: []
+register-prefix: null
+register-block-group: L4STAT
+register-block-size: 388
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CVAL'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Counter 0-15 value register
+ description: null
+ name: CVAL
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NCPU'
+ start: 28
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NCNT'
+ start: 23
+ width: 5
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MC'
+ start: 22
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IA'
+ start: 21
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DS'
+ start: 20
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'EE'
+ start: 19
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AE'
+ start: 18
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EL'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CD'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SU'
+ start: 14
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CL'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EVENT_ID'
+ start: 4
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CPU_AHBM'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ Counter 0-15 control register
+ description: null
+ name: CCTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CSVAL'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Counter 0-15 max/latch register
+ description: null
+ name: CSVAL
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TSTAMP'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Timestamp register
+ description: null
+ name: TSTAMP
+ width: 32
+name: l4stat
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/memscrub-header.yml b/spec/dev/grlib/if/memscrub-header.yml
new file mode 100644
index 0000000..cadc27d
--- /dev/null
+++ b/spec/dev/grlib/if/memscrub-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the MEMSCRUB register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: memscrub
+path: grlib/memscrub-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/memscrub.yml b/spec/dev/grlib/if/memscrub.yml
new file mode 100644
index 0000000..ac58a34
--- /dev/null
+++ b/spec/dev/grlib/if/memscrub.yml
@@ -0,0 +1,403 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBMEMSCRUB
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: memscrub-header
+definition:
+- default:
+ count: 1
+ name: AHBS
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: AHBFAR
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: AHBERC
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: STAT
+ offset: 0x10
+ variants: []
+- default:
+ count: 1
+ name: CONFIG
+ offset: 0x14
+ variants: []
+- default:
+ count: 1
+ name: RANGEL
+ offset: 0x18
+ variants: []
+- default:
+ count: 1
+ name: RANGEH
+ offset: 0x1c
+ variants: []
+- default:
+ count: 1
+ name: POS
+ offset: 0x20
+ variants: []
+- default:
+ count: 1
+ name: ETHRES
+ offset: 0x24
+ variants: []
+- default:
+ count: 1
+ name: INIT
+ offset: 0x28
+ variants: []
+- default:
+ count: 1
+ name: RANGEL2
+ offset: 0x2c
+ variants: []
+- default:
+ count: 1
+ name: RANGEH2
+ offset: 0x30
+ variants: []
+register-prefix: null
+register-block-group: MEMSCRUB
+register-block-size: 52
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CECNT'
+ start: 22
+ width: 10
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'UECNT'
+ start: 14
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DONE'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SEC'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SBC'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CE'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'NE'
+ start: 8
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'HWRITE'
+ start: 7
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'HMASTER'
+ start: 3
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'HSIZE'
+ start: 0
+ width: 3
+ variants: []
+ brief: |
+ AHB Status register
+ description: null
+ name: AHBS
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AHB_FAILING_ADDRESS'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ AHB Failing Address Register
+ description: null
+ name: AHBFAR
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CECNTT'
+ start: 22
+ width: 10
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'UECNTT'
+ start: 14
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CECTE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'UECTE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ AHB Error configuration register
+ description: null
+ name: AHBERC
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RUNCOUNT'
+ start: 22
+ width: 10
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BLKCOUNT'
+ start: 14
+ width: 8
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'DONE'
+ start: 13
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BURSTLEN'
+ start: 1
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ACTIVE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Status register
+ description: null
+ name: STAT
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DELAY'
+ start: 8
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IRQD'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SERA'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LOOP'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MODE'
+ start: 2
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ES'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SCEN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Configuration register
+ description: null
+ name: CONFIG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RLADDR'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Range low address register
+ description: null
+ name: RANGEL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RHADDR'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Range high address register
+ description: null
+ name: RANGEH
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'POSITION'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Position register
+ description: null
+ name: POS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RECT'
+ start: 22
+ width: 10
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BECT'
+ start: 14
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RECTE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BECTE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Error threshold register
+ description: null
+ name: ETHRES
+ width: 32
+- bits:
+ - default:
+ - access: [w]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Initialisation data register
+ description: null
+ name: INIT
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RLADDR'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Second range low address register
+ description: null
+ name: RANGEL2
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RHADDR'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Second range high address register
+ description: null
+ name: RANGEH2
+ width: 32
+name: memscrub
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/mmctrl-header.yml b/spec/dev/grlib/if/mmctrl-header.yml
new file mode 100644
index 0000000..a359b8f
--- /dev/null
+++ b/spec/dev/grlib/if/mmctrl-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the MMCTRL register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: mmctrl
+path: grlib/mmctrl-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/mmctrl.yml b/spec/dev/grlib/if/mmctrl.yml
new file mode 100644
index 0000000..96159fc
--- /dev/null
+++ b/spec/dev/grlib/if/mmctrl.yml
@@ -0,0 +1,302 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBMMCTRL
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: mmctrl-header
+definition:
+- default:
+ count: 1
+ name: SDCFG1
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: SDCFG2
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: MUXCFG
+ offset: 0x20
+ variants: []
+- default:
+ count: 1
+ name: FTDA
+ offset: 0x24
+ variants: []
+- default:
+ count: 1
+ name: FTDC
+ offset: 0x28
+ variants: []
+- default:
+ count: 1
+ name: FTDD
+ offset: 0x2c
+ variants: []
+- default:
+ count: 1
+ name: FTBND
+ offset: 0x30
+ variants: []
+register-prefix: null
+register-block-group: MMCTRL
+register-block-size: 52
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RF'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TRP'
+ start: 30
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TRFC'
+ start: 27
+ width: 3
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TC'
+ start: 26
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BANKSZ'
+ start: 23
+ width: 3
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'COLSZ'
+ start: 21
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'COMMAND'
+ start: 18
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MS'
+ start: 16
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: '64'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RFLOAD'
+ start: 0
+ width: 15
+ variants: []
+ brief: |
+ SDRAM configuration register 1
+ description: null
+ name: SDCFG1
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CE'
+ start: 30
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN2T'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DCS'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BPARK'
+ start: 13
+ width: 1
+ variants: []
+ brief: |
+ SDRAM configuration register 2
+ description: null
+ name: SDCFG2
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ERRLOC'
+ start: 20
+ width: 12
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DDERR'
+ start: 19
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DWIDTH'
+ start: 16
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'BEID'
+ start: 12
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DATAMUX'
+ start: 5
+ width: 3
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CEN'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BAUPD'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'BAEN'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CODE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EDEN'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Mux configuration register
+ description: null
+ name: MUXCFG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FTDA'
+ start: 2
+ width: 30
+ variants: []
+ brief: |
+ FT diagnostic address register
+ description: null
+ name: FTDA
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CBD'
+ start: 24
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CBC'
+ start: 16
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CBB'
+ start: 8
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CBA'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ FT diagnostic checkbits register
+ description: null
+ name: FTDC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DATA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ FT diagnostic data register
+ description: null
+ name: FTDD
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FTBND_31_3'
+ start: 3
+ width: 29
+ variants: []
+ brief: |
+ FT boundary address register
+ description: null
+ name: FTBND
+ width: 32
+name: mmctrl
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/spictrl-header.yml b/spec/dev/grlib/if/spictrl-header.yml
new file mode 100644
index 0000000..7bdde19
--- /dev/null
+++ b/spec/dev/grlib/if/spictrl-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the SPICTRL register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: spictrl
+path: grlib/spictrl-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/spictrl.yml b/spec/dev/grlib/if/spictrl.yml
new file mode 100644
index 0000000..89d204a
--- /dev/null
+++ b/spec/dev/grlib/if/spictrl.yml
@@ -0,0 +1,430 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBSPICTRL
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: spictrl-header
+definition:
+- default:
+ count: 1
+ name: CAP
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: MODE
+ offset: 0x20
+ variants: []
+- default:
+ count: 1
+ name: EVENT
+ offset: 0x24
+ variants: []
+- default:
+ count: 1
+ name: MASK
+ offset: 0x28
+ variants: []
+- default:
+ count: 1
+ name: CMD
+ offset: 0x2c
+ variants: []
+- default:
+ count: 1
+ name: TX
+ offset: 0x30
+ variants: []
+- default:
+ count: 1
+ name: RX
+ offset: 0x34
+ variants: []
+- default:
+ count: 1
+ name: SLVSEL
+ offset: 0x38
+ variants: []
+- default:
+ count: 1
+ name: ASLVSEL
+ offset: 0x3c
+ variants: []
+register-prefix: null
+register-block-group: SPICTRL
+register-block-size: 64
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SSSZ'
+ start: 24
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MAXWLEN'
+ start: 20
+ width: 4
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TWEN'
+ start: 19
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AMODE'
+ start: 18
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ASELA'
+ start: 17
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SSEN'
+ start: 16
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'FDEPTH'
+ start: 8
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SR'
+ start: 7
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'FT'
+ start: 5
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'REV'
+ start: 0
+ width: 5
+ variants: []
+ brief: |
+ Capability register
+ description: null
+ name: CAP
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LOOP'
+ start: 30
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CPOL'
+ start: 29
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CPHA'
+ start: 28
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DIV_16'
+ start: 27
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'REV'
+ start: 26
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MX'
+ start: 25
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 24
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LEN'
+ start: 20
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PM'
+ start: 16
+ width: 4
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TWEN'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ASEL'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'FACT'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'OD'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CG'
+ start: 7
+ width: 5
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ASELDEL'
+ start: 5
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TAC'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TTO'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IGSEL'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CITE'
+ start: 1
+ width: 1
+ variants: []
+ brief: |
+ Mode register
+ description: null
+ name: MODE
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TIP'
+ start: 31
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'LT'
+ start: 14
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'OV'
+ start: 12
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'UN'
+ start: 11
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'MME'
+ start: 10
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NE'
+ start: 9
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'NF'
+ start: 8
+ width: 1
+ variants: []
+ brief: |
+ Event register
+ description: null
+ name: EVENT
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TIPE'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LTE'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'OVE'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'UNE'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MMEE'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'NEEE'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'NFE'
+ start: 8
+ width: 1
+ variants: []
+ brief: |
+ Mask register
+ description: null
+ name: MASK
+ width: 32
+- bits:
+ - default:
+ - access: [w]
+ brief: null
+ description: null
+ name: 'LST'
+ start: 22
+ width: 1
+ variants: []
+ brief: |
+ Command register
+ description: null
+ name: CMD
+ width: 32
+- bits:
+ - default:
+ - access: [w]
+ brief: null
+ description: null
+ name: 'TDATA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Transmit register
+ description: null
+ name: TX
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RDATA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Receive register
+ description: null
+ name: RX
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SLVSEL'
+ start: 0
+ width: 2
+ variants: []
+ brief: |
+ Slave select register
+ description: null
+ name: SLVSEL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ASLVSEL'
+ start: 0
+ width: 2
+ variants: []
+ brief: |
+ Automatic slave select register
+ description: null
+ name: ASLVSEL
+ width: 32
+name: spictrl
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/spwpnp-header.yml b/spec/dev/grlib/if/spwpnp-header.yml
new file mode 100644
index 0000000..8240e11
--- /dev/null
+++ b/spec/dev/grlib/if/spwpnp-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the SPWPNP register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: spwpnp
+path: grlib/spwpnp-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/spwpnp.yml b/spec/dev/grlib/if/spwpnp.yml
new file mode 100644
index 0000000..9cdbea1
--- /dev/null
+++ b/spec/dev/grlib/if/spwpnp.yml
@@ -0,0 +1,314 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This set of defines the ${.:/register-block-group} address map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBSPWPNP
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: spwpnp-header
+definition:
+- default:
+ count: 1
+ name: PNPVEND
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: PNPVER
+ offset: 0x1
+ variants: []
+- default:
+ count: 1
+ name: PNPDEVSTS
+ offset: 0x2
+ variants: []
+- default:
+ count: 1
+ name: PNPACTLNK
+ offset: 0x3
+ variants: []
+- default:
+ count: 1
+ name: PNPOA0
+ offset: 0x5
+ variants: []
+- default:
+ count: 1
+ name: PNPOA1
+ offset: 0x6
+ variants: []
+- default:
+ count: 1
+ name: PNPOA2
+ offset: 0x7
+ variants: []
+- default:
+ count: 1
+ name: PNPDEVID
+ offset: 0x8
+ variants: []
+- default:
+ count: 1
+ name: PNPUVEND
+ offset: 0x9
+ variants: []
+- default:
+ count: 1
+ name: PNPUSN
+ offset: 0xa
+ variants: []
+- default:
+ count: 1
+ name: PNPVSTRL
+ offset: 0x4000
+ variants: []
+- default:
+ count: 1
+ name: PNPPSTRL
+ offset: 0x6000
+ variants: []
+- default:
+ count: 1
+ name: PNPPCNT
+ offset: 0x8000
+ variants: []
+- default:
+ count: 1
+ name: PNPACNT
+ offset: 0xc000
+ variants: []
+register-prefix: null
+register-block-group: SpaceWire Plug-and-Play
+register-block-size: 49156
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'VEND'
+ start: 16
+ width: 16
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PROD'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Device Vendor and Product ID
+ description: null
+ name: PNPVEND
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MAJOR'
+ start: 24
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MINOR'
+ start: 16
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PATCH'
+ start: 8
+ width: 8
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Version
+ description: null
+ name: PNPVER
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'STATUS'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Device Status
+ description: null
+ name: PNPDEVSTS
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ACTIVE'
+ start: 1
+ width: 12
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Active Links
+ description: null
+ name: PNPACTLNK
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Owner Address 0
+ description: null
+ name: PNPOA0
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Owner Address 1
+ description: null
+ name: PNPOA1
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RA'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Owner Address 2
+ description: null
+ name: PNPOA2
+ width: 32
+- bits:
+ - default:
+ - access: [r, w, cas]
+ brief: null
+ description: null
+ name: 'DID'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Device ID
+ description: null
+ name: PNPDEVID
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'VEND'
+ start: 16
+ width: 16
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PROD'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Unit Vendor and Product ID
+ description: null
+ name: PNPUVEND
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'USN'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Unit Serial Number
+ description: null
+ name: PNPUSN
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'LEN'
+ start: 0
+ width: 15
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Vendor String Length
+ description: null
+ name: PNPVSTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'LEN'
+ start: 0
+ width: 15
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Product String Length
+ description: null
+ name: PNPPSTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PC'
+ start: 0
+ width: 5
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Protocol Count
+ description: null
+ name: PNPPCNT
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AC'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Application Count
+ description: null
+ name: PNPACNT
+ width: 32
+name: spwpnp
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/spwrmap-header.yml b/spec/dev/grlib/if/spwrmap-header.yml
new file mode 100644
index 0000000..09fcf51
--- /dev/null
+++ b/spec/dev/grlib/if/spwrmap-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the SPWRMAP register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: spwrmap
+path: grlib/spwrmap-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/spwrmap.yml b/spec/dev/grlib/if/spwrmap.yml
new file mode 100644
index 0000000..adef54d
--- /dev/null
+++ b/spec/dev/grlib/if/spwrmap.yml
@@ -0,0 +1,1370 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This set of defines the ${.:/register-block-group} address map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBSPWMAP
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: spwrmap-header
+definition:
+- default:
+ count: 1
+ name: RTPMAP
+ offset: 0x4
+ variants: []
+- default:
+ count: 1
+ name: RTACTRL
+ offset: 0x404
+ variants: []
+- default:
+ count: 1
+ name: PCTRLCFG
+ offset: 0x800
+ variants: []
+- default:
+ count: 1
+ name: PCTRL
+ offset: 0x804
+ variants: []
+- default:
+ count: 1
+ name: PSTSCFG
+ offset: 0x880
+ variants: []
+- default:
+ count: 1
+ name: PSTS
+ offset: 0x884
+ variants: []
+- default:
+ count: 1
+ name: PTIMER
+ offset: 0x900
+ variants: []
+- default:
+ count: 1
+ name: PCTRL2CFG
+ offset: 0x980
+ variants: []
+- default:
+ count: 1
+ name: PCTRL2
+ offset: 0x984
+ variants: []
+- default:
+ count: 1
+ name: RTRCFG
+ offset: 0xa00
+ variants: []
+- default:
+ count: 1
+ name: TC
+ offset: 0xa04
+ variants: []
+- default:
+ count: 1
+ name: VER
+ offset: 0xa08
+ variants: []
+- default:
+ count: 1
+ name: IDIV
+ offset: 0xa0c
+ variants: []
+- default:
+ count: 1
+ name: CFGWE
+ offset: 0xa10
+ variants: []
+- default:
+ count: 1
+ name: PRESCALER
+ offset: 0xa14
+ variants: []
+- default:
+ count: 1
+ name: IMASK
+ offset: 0xa18
+ variants: []
+- default:
+ count: 1
+ name: IPMASK
+ offset: 0xa1c
+ variants: []
+- default:
+ count: 1
+ name: PIP
+ offset: 0xa20
+ variants: []
+- default:
+ count: 1
+ name: ICODEGEN
+ offset: 0xa24
+ variants: []
+- default:
+ count: 1
+ name: ISR0
+ offset: 0xa28
+ variants: []
+- default:
+ count: 1
+ name: ISR1
+ offset: 0xa2c
+ variants: []
+- default:
+ count: 1
+ name: ISRTIMER
+ offset: 0xa30
+ variants: []
+- default:
+ count: 1
+ name: AITIMER
+ offset: 0xa34
+ variants: []
+- default:
+ count: 1
+ name: ISRCTIMER
+ offset: 0xa38
+ variants: []
+- default:
+ count: 1
+ name: LRUNSTAT
+ offset: 0xa40
+ variants: []
+- default:
+ count: 1
+ name: CAP
+ offset: 0xa44
+ variants: []
+- default:
+ count: 1
+ name: PNPVEND
+ offset: 0xa50
+ variants: []
+- default:
+ count: 1
+ name: PNPUVEND
+ offset: 0xa54
+ variants: []
+- default:
+ count: 1
+ name: PNPUSN
+ offset: 0xa58
+ variants: []
+- default:
+ count: 1
+ name: MAXPLEN
+ offset: 0xe00
+ variants: []
+- default:
+ count: 1
+ name: CREDCNT
+ offset: 0xe84
+ variants: []
+- default:
+ count: 1
+ name: RTCOMB
+ offset: 0x1004
+ variants: []
+register-prefix: null
+register-block-group: SpaceWire Remote Memory Access Protocol (RMAP)
+register-block-size: 4104
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 1
+ width: 12
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PD'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Routing table port mapping, addresses 1-12 and 32-255
+ description: null
+ name: RTPMAP
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SR'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PR'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'HD'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Routing table address control, addresses 1-12 and 32-255
+ description: null
+ name: RTACTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PL'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TS'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TR'
+ start: 9
+ width: 1
+ variants: []
+ brief: |
+ Port control, port 0 (configuration port)
+ description: null
+ name: PCTRLCFG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RD'
+ start: 24
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ST'
+ start: 21
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SR'
+ start: 20
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AD'
+ start: 19
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LR'
+ start: 18
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PL'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TS'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IC'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ET'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DI'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TR'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PR'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TF'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RS'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CE'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AS'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LS'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LD'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Port control, ports 1-12 (SpaceWire ports and AMBA ports)
+ description: null
+ name: PCTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'EO'
+ start: 31
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'EE'
+ start: 30
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PL'
+ start: 29
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TT'
+ start: 28
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PT'
+ start: 27
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'HC'
+ start: 26
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PI'
+ start: 25
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CE'
+ start: 24
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'EC'
+ start: 20
+ width: 4
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TS'
+ start: 18
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'ME'
+ start: 17
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IP'
+ start: 7
+ width: 5
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CP'
+ start: 4
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PC'
+ start: 0
+ width: 4
+ variants: []
+ brief: |
+ Port status, port 0 (configuration port)
+ description: null
+ name: PSTSCFG
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PT'
+ start: 30
+ width: 2
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PL'
+ start: 29
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TT'
+ start: 28
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'RS'
+ start: 27
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'SR'
+ start: 26
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'LR'
+ start: 22
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SP'
+ start: 21
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AC'
+ start: 20
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'TS'
+ start: 18
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'ME'
+ start: 17
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TF'
+ start: 16
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 15
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'LS'
+ start: 12
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IP'
+ start: 7
+ width: 5
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PR'
+ start: 6
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PB'
+ start: 5
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'IA'
+ start: 4
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'CE'
+ start: 3
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'ER'
+ start: 2
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'DE'
+ start: 1
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Port status, ports 1-12 (SpaceWire ports and AMBA ports)
+ description: null
+ name: PSTS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RL'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Port timer reload, ports 0-12
+ description: null
+ name: PTIMER
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SM'
+ start: 24
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SV'
+ start: 16
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'OR'
+ start: 15
+ width: 1
+ variants: []
+ brief: |
+ Port control 2, port 0 (configuration port)
+ description: null
+ name: PCTRL2CFG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SM'
+ start: 24
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SV'
+ start: 16
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'OR'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'UR'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AT'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AR'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IT'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IR'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SD'
+ start: 1
+ width: 5
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SC'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Port control 2, ports 1-12 (SpaceWire ports and AMBA ports)
+ description: null
+ name: PCTRL2
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SP'
+ start: 27
+ width: 5
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AP'
+ start: 22
+ width: 5
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SR'
+ start: 15
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 14
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IC'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IS'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IP'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AI'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AT'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IE'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EE'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SA'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TF'
+ start: 3
+ width: 1
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'ME'
+ start: 2
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TA'
+ start: 1
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PP'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Router configuration / status
+ description: null
+ name: RTRCFG
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 8
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CF'
+ start: 6
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TC'
+ start: 0
+ width: 6
+ variants: []
+ brief: |
+ Time-code
+ description: null
+ name: TC
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MA'
+ start: 24
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'MI'
+ start: 16
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PA'
+ start: 8
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ID'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ Version / instance ID
+ description: null
+ name: VER
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ID'
+ start: 0
+ width: 8
+ variants: []
+ brief: |
+ Initialization divisor
+ description: null
+ name: IDIV
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'WE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Configuration port write enable
+ description: null
+ name: CFGWE
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RL'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Timer prescaler reload
+ description: null
+ name: PRESCALER
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SR'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RS'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TT'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PL'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TS'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AC'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IA'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ME'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Interrupt mask
+ description: null
+ name: IMASK
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IE'
+ start: 0
+ width: 20
+ variants: []
+ brief: |
+ Interrupt port mask
+ description: null
+ name: IPMASK
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'IP'
+ start: 0
+ width: 20
+ variants: []
+ brief: |
+ Port interrupt pending
+ description: null
+ name: PIP
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'HI'
+ start: 21
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'UA'
+ start: 20
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AH'
+ start: 19
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IT'
+ start: 18
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IN'
+ start: 0
+ width: 6
+ variants: []
+ brief: |
+ Interrupt code generation
+ description: null
+ name: ICODEGEN
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'IB'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Interrupt code distribution ISR register, interrupt 0-31
+ description: null
+ name: ISR0
+ width: 32
+- bits:
+ - default:
+ - access: [r, w1c]
+ brief: null
+ description: null
+ name: 'IB'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Interrupt code distribution ISR register, interrupt 32-63
+ description: null
+ name: ISR1
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RL'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Interrupt code distribution ISR timer reload
+ description: null
+ name: ISRTIMER
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RL'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Interrupt code distribution ACK-to-INT timer reload
+ description: null
+ name: AITIMER
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RL'
+ start: 0
+ width: 5
+ variants: []
+ brief: |
+ Interrupt code distribution ISR change timer reload
+ description: null
+ name: ISRCTIMER
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'LR'
+ start: 1
+ width: 18
+ variants: []
+ brief: |
+ Link running status
+ description: null
+ name: LRUNSTAT
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AF'
+ start: 24
+ width: 2
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PF'
+ start: 20
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'RM'
+ start: 16
+ width: 3
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AS'
+ start: 14
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'AX'
+ start: 13
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DP'
+ start: 12
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ID'
+ start: 11
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'SD'
+ start: 10
+ width: 1
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PC'
+ start: 5
+ width: 5
+ - access: [r]
+ brief: null
+ description: null
+ name: 'CC'
+ start: 0
+ width: 5
+ variants: []
+ brief: |
+ Capability
+ description: null
+ name: CAP
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'VI'
+ start: 16
+ width: 16
+ - access: [r]
+ brief: null
+ description: null
+ name: 'PI'
+ start: 0
+ width: 26
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Device Vendor and Product ID
+ description: null
+ name: PNPVEND
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'VI'
+ start: 16
+ width: 16
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PI'
+ start: 0
+ width: 26
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Unit Vendor and Product ID
+ description: null
+ name: PNPUVEND
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SN'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ SpaceWire Plug-and-Play - Unit Serial Number
+ description: null
+ name: PNPUSN
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ML'
+ start: 0
+ width: 25
+ variants: []
+ brief: |
+ Maximum packet length, ports 0-12
+ description: null
+ name: MAXPLEN
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'OC'
+ start: 6
+ width: 6
+ - access: [r]
+ brief: null
+ description: null
+ name: 'IC'
+ start: 0
+ width: 6
+ variants: []
+ brief: |
+ Credit counter, ports 1-8
+ description: null
+ name: CREDCNT
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SR'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 30
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PR'
+ start: 29
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'HD'
+ start: 28
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PE'
+ start: 1
+ width: 19
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'PD'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Routing table, combined port mapping and address control, addresses 1-255
+ description: null
+ name: RTCOMB
+ width: 32
+name: spwrmap
+notes: null
+type: interface
diff --git a/spec/dev/grlib/if/spwtdp-header.yml b/spec/dev/grlib/if/spwtdp-header.yml
new file mode 100644
index 0000000..5fa3f6f
--- /dev/null
+++ b/spec/dev/grlib/if/spwtdp-header.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This header file defines the SPWTDP register block interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+enabled-by: true
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+ uid: /if/domain
+- role: interface-ingroup
+ uid: spwtdp
+path: grlib/spwtdp-regs.h
+prefix: bsps/include
+type: interface
diff --git a/spec/dev/grlib/if/spwtdp.yml b/spec/dev/grlib/if/spwtdp.yml
new file mode 100644
index 0000000..7d82f70
--- /dev/null
+++ b/spec/dev/grlib/if/spwtdp.yml
@@ -0,0 +1,950 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+ This structure defines the ${.:/register-block-group} register block memory
+ map.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBSPWTDP
+index-entries: []
+interface-type: register-block
+links:
+- role: interface-ingroup
+ uid: group
+- role: interface-placement
+ uid: spwtdp-header
+definition:
+- default:
+ count: 1
+ name: CONF0
+ offset: 0x0
+ variants: []
+- default:
+ count: 1
+ name: CONF3
+ offset: 0xc
+ variants: []
+- default:
+ count: 1
+ name: CTRL
+ offset: 0x20
+ variants: []
+- default:
+ count: 1
+ name: CET0
+ offset: 0x24
+ variants: []
+- default:
+ count: 1
+ name: CET1
+ offset: 0x28
+ variants: []
+- default:
+ count: 1
+ name: CET2
+ offset: 0x2c
+ variants: []
+- default:
+ count: 1
+ name: CET0
+ offset: 0x30
+ variants: []
+- default:
+ count: 1
+ name: CET4
+ offset: 0x34
+ variants: []
+- default:
+ count: 1
+ name: DPF
+ offset: 0x40
+ variants: []
+- default:
+ count: 1
+ name: DET0
+ offset: 0x44
+ variants: []
+- default:
+ count: 1
+ name: DET1
+ offset: 0x48
+ variants: []
+- default:
+ count: 1
+ name: DET2
+ offset: 0x4c
+ variants: []
+- default:
+ count: 1
+ name: DET3
+ offset: 0x50
+ variants: []
+- default:
+ count: 1
+ name: DET4
+ offset: 0x54
+ variants: []
+- default:
+ count: 1
+ name: TRPFRX
+ offset: 0x60
+ variants: []
+- default:
+ count: 1
+ name: TR0
+ offset: 0x64
+ variants: []
+- default:
+ count: 1
+ name: TR1
+ offset: 0x68
+ variants: []
+- default:
+ count: 1
+ name: TR2
+ offset: 0x6c
+ variants: []
+- default:
+ count: 1
+ name: TR3
+ offset: 0x70
+ variants: []
+- default:
+ count: 1
+ name: TR4
+ offset: 0x74
+ variants: []
+- default:
+ count: 1
+ name: TTPFTX
+ offset: 0x80
+ variants: []
+- default:
+ count: 1
+ name: TT0
+ offset: 0x84
+ variants: []
+- default:
+ count: 1
+ name: TT1
+ offset: 0x88
+ variants: []
+- default:
+ count: 1
+ name: TT2
+ offset: 0x8c
+ variants: []
+- default:
+ count: 1
+ name: TT3
+ offset: 0x90
+ variants: []
+- default:
+ count: 1
+ name: TT4
+ offset: 0x94
+ variants: []
+- default:
+ count: 1
+ name: LPF
+ offset: 0xa0
+ variants: []
+- default:
+ count: 1
+ name: IE
+ offset: 0xc0
+ variants: []
+- default:
+ count: 1
+ name: DC
+ offset: 0xc8
+ variants: []
+- default:
+ count: 1
+ name: DS
+ offset: 0xcc
+ variants: []
+- default:
+ count: 1
+ name: EDM0
+ offset: 0x100
+ variants: []
+- default:
+ count: 1
+ name: EDPF0
+ offset: 0x110
+ variants: []
+- default:
+ count: 1
+ name: ED0ET0
+ offset: 0x114
+ variants: []
+- default:
+ count: 1
+ name: ED0ET1
+ offset: 0x118
+ variants: []
+- default:
+ count: 1
+ name: ED0ET2
+ offset: 0x11c
+ variants: []
+- default:
+ count: 1
+ name: ED0ET3
+ offset: 0x120
+ variants: []
+- default:
+ count: 1
+ name: ED0ET4
+ offset: 0x124
+ variants: []
+register-prefix: null
+register-block-group: SPWTDP
+register-block-size: 296
+register-block-type: memory
+registers:
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'JE'
+ start: 24
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ST'
+ start: 21
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EP'
+ start: 20
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ET'
+ start: 19
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SP'
+ start: 18
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SE'
+ start: 17
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'LE'
+ start: 16
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'AE'
+ start: 15
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MAPPING'
+ start: 8
+ width: 5
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TD'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'MU'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SEL'
+ start: 4
+ width: 2
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'ME'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RE'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'RS'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Configuration 0
+ description: null
+ name: CONF0
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'STM'
+ start: 16
+ width: 6
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DI64R'
+ start: 13
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DI64T'
+ start: 12
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DI64'
+ start: 11
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DI'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'INRX'
+ start: 5
+ width: 5
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'INTX'
+ start: 0
+ width: 5
+ variants: []
+ brief: |
+ Configuration 3
+ description: null
+ name: CONF3
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'NC'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'IS'
+ start: 30
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SPWTC'
+ start: 16
+ width: 8
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CPF'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Control
+ description: null
+ name: CTRL
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CET0'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Command Elapsed Time 0
+ description: null
+ name: CET0
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CET1'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Command Elapsed Time 1
+ description: null
+ name: CET1
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CET2'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Command Elapsed Time 2
+ description: null
+ name: CET2
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CET3'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Command Elapsed Time 3
+ description: null
+ name: CET0
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CET4'
+ start: 24
+ width: 8
+ variants: []
+ brief: |
+ Command Elapsed Time 4
+ description: null
+ name: CET4
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DPF'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Datation Preamble Field
+ description: null
+ name: DPF
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DET0'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Datation Elapsed Time 0
+ description: null
+ name: DET0
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DET1'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Datation Elapsed Time 1
+ description: null
+ name: DET1
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DET2'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Datation Elapsed Time 2
+ description: null
+ name: DET2
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DET3'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Datation Elapsed Time 3
+ description: null
+ name: DET3
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'DET4'
+ start: 24
+ width: 8
+ variants: []
+ brief: |
+ Datation Elapsed Time 4
+ description: null
+ name: DET4
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TRPF'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Time-Stamp Preamble Field Rx
+ description: null
+ name: TRPFRX
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TR0'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Time Stamp Elapsed Time 0 Rx
+ description: null
+ name: TR0
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TR1'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Time Stamp Elapsed Time 1 Rx
+ description: null
+ name: TR1
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TR2'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Time Stamp Elapsed Time 2 Rx
+ description: null
+ name: TR2
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TR3'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Time Stamp Elapsed Time 3 Rx
+ description: null
+ name: TR3
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TR4'
+ start: 24
+ width: 8
+ variants: []
+ brief: |
+ Time Stamp Elapsed Time 4 Rx
+ description: null
+ name: TR4
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TSTC'
+ start: 24
+ width: 8
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TTPF'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Time-Stamp SpaceWire Time-Code and Preamble Field Tx
+ description: null
+ name: TTPFTX
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TT0'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Time Stamp Elapsed Time 0 Tx
+ description: null
+ name: TT0
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TT1'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Time Stamp Elapsed Time 1 Tx
+ description: null
+ name: TT1
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TT2'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Time Stamp Elapsed Time 2 Tx
+ description: null
+ name: TT2
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TT3'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ Time Stamp Elapsed Time 3 Tx
+ description: null
+ name: TT3
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'TT4'
+ start: 24
+ width: 8
+ variants: []
+ brief: |
+ Time Stamp Elapsed Time 4 Tx
+ description: null
+ name: TT4
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'LPF'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ Latency Preamble Field
+ description: null
+ name: LPF
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'NCTCE'
+ start: 19
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SETE'
+ start: 10
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EDIE3'
+ start: 9
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EDIE2'
+ start: 8
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EDIE1'
+ start: 7
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EDIE0'
+ start: 6
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DITE'
+ start: 5
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DIRE'
+ start: 4
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TTE'
+ start: 3
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TME'
+ start: 2
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'TRE'
+ start: 1
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'SE'
+ start: 0
+ width: 1
+ variants: []
+ brief: |
+ Interrupt Enable
+ description: null
+ name: IE
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'DC'
+ start: 0
+ width: 15
+ variants: []
+ brief: |
+ Delay Count
+ description: null
+ name: DC
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EN'
+ start: 31
+ width: 1
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'CD'
+ start: 0
+ width: 24
+ variants: []
+ brief: |
+ Disable Sync
+ description: null
+ name: DS
+ width: 32
+- bits:
+ - default:
+ - access: [r, w]
+ brief: null
+ description: null
+ name: 'EDM0'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ External Datation 0 Mask
+ description: null
+ name: EDM0
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'EDPF0'
+ start: 0
+ width: 16
+ variants: []
+ brief: |
+ External Datation 0 Preamble Field
+ description: null
+ name: EDPF0
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ED0ET0'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ External Datation 0 Elapsed Time 0
+ description: null
+ name: ED0ET0
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ED0ET1'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ External Datation 0 Elapsed Time 1
+ description: null
+ name: ED0ET1
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ED0ET2'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ External Datation 0 Elapsed Time 2
+ description: null
+ name: ED0ET2
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ED0ET3'
+ start: 0
+ width: 32
+ variants: []
+ brief: |
+ External Datation 0 Elapsed Time 3
+ description: null
+ name: ED0ET3
+ width: 32
+- bits:
+ - default:
+ - access: [r]
+ brief: null
+ description: null
+ name: 'ED0ET4'
+ start: 24
+ width: 8
+ variants: []
+ brief: |
+ External Datation 0 Elapsed Time 4
+ description: null
+ name: ED0ET4
+ width: 32
+name: spwtdp
+notes: null
+type: interface
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