[rtems commit] aarch64: Fix context switch
Sebastian Huber
sebh at rtems.org
Fri Mar 5 14:06:32 UTC 2021
Module: rtems
Branch: master
Commit: 61d688bfcf191347af9b6a23f16176e6667d0bf5
Changeset: http://git.rtems.org/rtems/commit/?id=61d688bfcf191347af9b6a23f16176e6667d0bf5
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Thu Mar 4 08:12:47 2021 +0100
aarch64: Fix context switch
The Per_CPU_Control::isr_dispatch_disable is a 32-bit integer.
Close #4206.
---
cpukit/score/cpu/aarch64/cpu_asm.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpukit/score/cpu/aarch64/cpu_asm.S b/cpukit/score/cpu/aarch64/cpu_asm.S
index 6c4da04..9e609e0 100644
--- a/cpukit/score/cpu/aarch64/cpu_asm.S
+++ b/cpukit/score/cpu/aarch64/cpu_asm.S
@@ -64,7 +64,7 @@
DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
/* Start saving context */
GET_SELF_CPU_CONTROL reg_2
- ldr x3, [x2, #PER_CPU_ISR_DISPATCH_DISABLE]
+ ldr w3, [x2, #PER_CPU_ISR_DISPATCH_DISABLE]
stp x19, x20, [x0]
stp x21, x22, [x0, #0x10]
@@ -109,7 +109,7 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
msr TPIDR_EL0, x3
- str x4, [x2, #PER_CPU_ISR_DISPATCH_DISABLE]
+ str w4, [x2, #PER_CPU_ISR_DISPATCH_DISABLE]
ldp x19, x20, [x1]
ldp x21, x22, [x1, #0x10]
More information about the vc
mailing list