[rtems commit] bsps/gicv2: Allow BSPs to define IRQ attributes
Joel Sherrill
joel at rtems.org
Tue Sep 21 14:03:23 UTC 2021
Module: rtems
Branch: master
Commit: 670a5089e2ff80beb508784f0141a9d28a091dff
Changeset: http://git.rtems.org/rtems/commit/?id=670a5089e2ff80beb508784f0141a9d28a091dff
Author: Kinsey Moore <kinsey.moore at oarcorp.com>
Date: Sat Sep 18 20:23:53 2021 -0500
bsps/gicv2: Allow BSPs to define IRQ attributes
ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
---
bsps/shared/dev/irq/arm-gicv2-get-attributes.c | 77 ++++++++++++++++++++++
bsps/shared/dev/irq/arm-gicv2-zynqmp.c | 76 +++++++++++++++++++++
bsps/shared/dev/irq/arm-gicv2.c | 61 ++++++++---------
spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml | 1 +
.../arm/altera-cyclone-v/bspalteracyclonev.yml | 1 +
spec/build/bsps/arm/imx/bspimx.yml | 1 +
.../bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml | 1 +
spec/build/bsps/arm/xen/bspxen.yml | 1 +
spec/build/bsps/arm/xilinx-zynq/obj.yml | 1 +
.../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 1 +
10 files changed, 187 insertions(+), 34 deletions(-)
diff --git a/bsps/shared/dev/irq/arm-gicv2-get-attributes.c b/bsps/shared/dev/irq/arm-gicv2-get-attributes.c
new file mode 100644
index 0000000..62aa504
--- /dev/null
+++ b/bsps/shared/dev/irq/arm-gicv2-get-attributes.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief This source file contains the interrupt get attribute implementation.
+ */
+
+/*
+ * Copyright (c) 2013, 2021 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Dornierstr. 4
+ * 82178 Puchheim
+ * Germany
+ * <info at embedded-brains.de>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dev/irq/arm-gic.h>
+#include <bsp/irq-generic.h>
+
+rtems_status_code bsp_interrupt_get_attributes(
+ rtems_vector_number vector,
+ rtems_interrupt_attributes *attributes
+)
+{
+ attributes->is_maskable = true;
+ attributes->maybe_enable = true;
+ attributes->maybe_disable = true;
+ attributes->can_raise = true;
+
+ if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
+ /*
+ * It is implementation-defined whether implemented SGIs are permanently
+ * enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and
+ * GICD_ICENABLER0.
+ */
+ attributes->can_raise_on = true;
+ attributes->cleared_by_acknowledge = true;
+ attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL;
+ } else {
+ attributes->can_disable = true;
+ attributes->can_clear = true;
+ attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL;
+
+ if ( vector > ARM_GIC_IRQ_PPI_LAST ) {
+ /* SPI */
+ attributes->can_get_affinity = true;
+ attributes->can_set_affinity = true;
+ }
+ }
+
+ return RTEMS_SUCCESSFUL;
+}
diff --git a/bsps/shared/dev/irq/arm-gicv2-zynqmp.c b/bsps/shared/dev/irq/arm-gicv2-zynqmp.c
new file mode 100644
index 0000000..ee44791
--- /dev/null
+++ b/bsps/shared/dev/irq/arm-gicv2-zynqmp.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief This source file contains the interrupt get attribute implementation.
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore <kinsey.moore at oarcorp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dev/irq/arm-gic.h>
+#include <bsp/irq-generic.h>
+
+rtems_status_code bsp_interrupt_get_attributes(
+ rtems_vector_number vector,
+ rtems_interrupt_attributes *attributes
+)
+{
+ attributes->is_maskable = true;
+ attributes->maybe_enable = true;
+ attributes->maybe_disable = true;
+ attributes->can_raise = true;
+
+ if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
+ /*
+ * It is implementation-defined whether implemented SGIs are permanently
+ * enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and
+ * GICD_ICENABLER0.
+ */
+ attributes->can_raise_on = true;
+ attributes->cleared_by_acknowledge = true;
+ attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL;
+ } else {
+ attributes->can_disable = true;
+ attributes->can_clear = true;
+ attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL;
+
+ /*
+ * Interrupt 67 affinity value presents as unimplemented in the
+ * configuration of the GICv2 instance used in ZynqMP CPUs.
+ */
+ if ( vector > ARM_GIC_IRQ_PPI_LAST && vector != 67 ) {
+ /* SPI */
+ attributes->can_get_affinity = true;
+ attributes->can_set_affinity = true;
+ }
+ }
+
+ return RTEMS_SUCCESSFUL;
+}
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index 9c47a4d..b7898e2e 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -64,40 +64,6 @@ void bsp_interrupt_dispatch(void)
}
}
-rtems_status_code bsp_interrupt_get_attributes(
- rtems_vector_number vector,
- rtems_interrupt_attributes *attributes
-)
-{
- attributes->is_maskable = true;
- attributes->maybe_enable = true;
- attributes->maybe_disable = true;
- attributes->can_raise = true;
-
- if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
- /*
- * It is implementation-defined whether implemented SGIs are permanently
- * enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and
- * GICD_ICENABLER0.
- */
- attributes->can_raise_on = true;
- attributes->cleared_by_acknowledge = true;
- attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL;
- } else {
- attributes->can_disable = true;
- attributes->can_clear = true;
- attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL;
-
- if ( vector > ARM_GIC_IRQ_PPI_LAST ) {
- /* SPI */
- attributes->can_get_affinity = true;
- attributes->can_set_affinity = true;
- }
- }
-
- return RTEMS_SUCCESSFUL;
-}
-
rtems_status_code bsp_interrupt_is_pending(
rtems_vector_number vector,
bool *pending
@@ -348,11 +314,24 @@ rtems_status_code bsp_interrupt_set_affinity(
{
volatile gic_dist *dist = ARM_GIC_DIST;
uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0);
+ rtems_interrupt_attributes attr;
+ rtems_status_code sc;
+
+ memset( &attr, 0, sizeof( attr ) );
+ sc = bsp_interrupt_get_attributes( vector, &attr );
+
+ if ( sc ) {
+ return sc;
+ }
if ( vector <= ARM_GIC_IRQ_PPI_LAST ) {
return RTEMS_UNSATISFIED;
}
+ if ( attr.can_set_affinity == 0 ) {
+ return RTEMS_UNSATISFIED;
+ }
+
gic_id_set_targets(dist, vector, targets);
return RTEMS_SUCCESSFUL;
}
@@ -364,12 +343,26 @@ rtems_status_code bsp_interrupt_get_affinity(
{
volatile gic_dist *dist = ARM_GIC_DIST;
uint8_t targets;
+ rtems_interrupt_attributes attr;
+ rtems_status_code sc;
+
+ memset( &attr, 0, sizeof( attr ) );
+ sc = bsp_interrupt_get_attributes( vector, &attr );
+
+ if ( sc ) {
+ return sc;
+ }
if ( vector <= ARM_GIC_IRQ_PPI_LAST ) {
return RTEMS_UNSATISFIED;
}
targets = gic_id_get_targets(dist, vector);
+
+ if ( attr.can_get_affinity == 0 ) {
+ return RTEMS_UNSATISFIED;
+ }
+
_Processor_mask_From_uint32_t(affinity, targets, 0);
return RTEMS_SUCCESSFUL;
}
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml b/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml
index d8286be..4f6b9c4 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml
@@ -28,6 +28,7 @@ source:
- bsps/shared/dev/clock/arm-generic-timer.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c
- bsps/shared/dev/irq/arm-gicv2.c
+- bsps/shared/dev/irq/arm-gicv2-zynqmp.c
- bsps/shared/dev/serial/console-termios-init.c
- bsps/shared/dev/serial/console-termios.c
- bsps/shared/irq/irq-default-handler.c
diff --git a/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml
index a9f3f7d..9911757 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml
@@ -132,6 +132,7 @@ source:
- bsps/shared/dev/btimer/btimer-stub.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c
- bsps/shared/dev/irq/arm-gicv2.c
+- bsps/shared/dev/irq/arm-gicv2-get-attributes.c
- bsps/shared/dev/rtc/rtc-support.c
- bsps/shared/dev/serial/console-termios-init.c
- bsps/shared/dev/serial/console-termios.c
diff --git a/spec/build/bsps/arm/imx/bspimx.yml b/spec/build/bsps/arm/imx/bspimx.yml
index 1471974..79d09a3 100644
--- a/spec/build/bsps/arm/imx/bspimx.yml
+++ b/spec/build/bsps/arm/imx/bspimx.yml
@@ -100,6 +100,7 @@ source:
- bsps/shared/dev/clock/arm-generic-timer.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c
- bsps/shared/dev/irq/arm-gicv2.c
+- bsps/shared/dev/irq/arm-gicv2-get-attributes.c
- bsps/shared/dev/serial/console-termios.c
- bsps/shared/irq/irq-default-handler.c
- bsps/shared/start/bsp-fdt.c
diff --git a/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml b/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml
index 2824081..df86f80 100644
--- a/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml
+++ b/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml
@@ -72,6 +72,7 @@ source:
- bsps/shared/dev/btimer/btimer-stub.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c
- bsps/shared/dev/irq/arm-gicv2.c
+- bsps/shared/dev/irq/arm-gicv2-get-attributes.c
- bsps/shared/dev/serial/console-termios-init.c
- bsps/shared/dev/serial/console-termios.c
- bsps/shared/dev/serial/getserialmouseps2.c
diff --git a/spec/build/bsps/arm/xen/bspxen.yml b/spec/build/bsps/arm/xen/bspxen.yml
index 5b9c2e8..0de27ab 100644
--- a/spec/build/bsps/arm/xen/bspxen.yml
+++ b/spec/build/bsps/arm/xen/bspxen.yml
@@ -71,6 +71,7 @@ source:
- bsps/shared/dev/clock/arm-generic-timer.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c
- bsps/shared/dev/irq/arm-gicv2.c
+- bsps/shared/dev/irq/arm-gicv2-get-attributes.c
- bsps/shared/dev/serial/console-termios-init.c
- bsps/shared/dev/serial/console-termios.c
- bsps/shared/irq/irq-default-handler.c
diff --git a/spec/build/bsps/arm/xilinx-zynq/obj.yml b/spec/build/bsps/arm/xilinx-zynq/obj.yml
index 8a11a45..f896b5a 100644
--- a/spec/build/bsps/arm/xilinx-zynq/obj.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/obj.yml
@@ -36,6 +36,7 @@ source:
- bsps/shared/dev/btimer/btimer-stub.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c
- bsps/shared/dev/irq/arm-gicv2.c
+- bsps/shared/dev/irq/arm-gicv2-get-attributes.c
- bsps/shared/dev/serial/console-termios.c
- bsps/shared/irq/irq-default-handler.c
- bsps/shared/start/bspfatal-default.c
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
index 21a21f3..0d336cc 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
@@ -94,6 +94,7 @@ source:
- bsps/shared/dev/clock/arm-generic-timer.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c
- bsps/shared/dev/irq/arm-gicv2.c
+- bsps/shared/dev/irq/arm-gicv2-zynqmp.c
- bsps/shared/dev/serial/console-termios.c
- bsps/shared/irq/irq-default-handler.c
- bsps/shared/start/bspfatal-default.c
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