[rtems commit] bsp/stm32h7: configure peripheral clocks for STM32H7B3xxQ (e.g. STM32H7B3I-DK BSP)

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    2c4331a14d66083361019e0d4c34f427e678a70a
Changeset: http://git.rtems.org/rtems/commit/?id=2c4331a14d66083361019e0d4c34f427e678a70a

Author:    Karel Gardas <karel at functional.vision>
Date:      Fri Apr  1 18:14:19 2022 +0200

bsp/stm32h7: configure peripheral clocks for STM32H7B3xxQ (e.g. STM32H7B3I-DK BSP)

---

 bsps/arm/stm32h7/start/stm32h7-config-per.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/bsps/arm/stm32h7/start/stm32h7-config-per.c b/bsps/arm/stm32h7/start/stm32h7-config-per.c
index 79aa1494dd..ce6370d3d0 100644
--- a/bsps/arm/stm32h7/start/stm32h7-config-per.c
+++ b/bsps/arm/stm32h7/start/stm32h7-config-per.c
@@ -32,6 +32,22 @@
 #include <stm32h7/hal.h>
 
 const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
+#ifdef STM32H7B3xxQ
+  /* for stm32h7b3i-dk BSP we provide only minimalistic peripheral
+     configuration just to make available U(S)ARTs working */
+  .PeriphClockSelection = RCC_PERIPHCLK_USART3
+    | RCC_PERIPHCLK_USART1,
+  .PLL2.PLL2M = 24,
+  .PLL2.PLL2N = 200,
+  .PLL2.PLL2P = 0,
+  .PLL2.PLL2Q = 2,
+  .PLL2.PLL2R = 0,
+  .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2,
+  .PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM,
+  .PLL2.PLL2FRACN = 0,
+  .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1,
+  .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2,
+#else
   .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3
     | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1
     | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG,
@@ -59,4 +75,5 @@ const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
   .UsbClockSelection = RCC_USBCLKSOURCE_PLL3,
   .RTCClockSelection = RCC_RTCCLKSOURCE_LSE,
   .RngClockSelection = RCC_RNGCLKSOURCE_HSI48
+#endif
 };