[rtems-central commit] spec: Improve some Interrupt Manager tests

[Sebastian Huber]

Module:    rtems-central
Branch:    master
Commit:    b66e5a24c44e8c6be1b91d231ae6c49e013dfe18
Changeset: http://git.rtems.org/rtems-central/commit/?id=b66e5a24c44e8c6be1b91d231ae6c49e013dfe18

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Tue Jan 11 10:33:55 2022 +0100

spec: Improve some Interrupt Manager tests

Some interrupt controllers will signal a pending interrupt if it is
disabled (for example ARM GIC), others will not signal a pending
interrupt if it is disabled (for example Freescale/NXP MPIC).

---

 spec/rtems/intr/req/is-pending.yml | 36 ++++++++++++++++++++++--------------
 spec/rtems/intr/req/raise-on.yml   | 24 ++++++++++++------------
 spec/rtems/intr/req/raise.yml      | 24 ++++++++++++------------
 3 files changed, 46 insertions(+), 38 deletions(-)

diff --git a/spec/rtems/intr/req/is-pending.yml b/spec/rtems/intr/req/is-pending.yml
index 01ffcb5..2cfdc74 100644
--- a/spec/rtems/intr/req/is-pending.yml
+++ b/spec/rtems/intr/req/is-pending.yml
@@ -285,8 +285,14 @@ test-support: |
     } else if ( !attr->is_maskable ) {
       /* We can only safely test maskable interrupts */
       T_false( IsPending( ctx ) );
+    } else if ( IsPending( ctx ) ) {
+      /*
+       * If there is already an interrupt pending, then it is probably raised
+       * by a peripheral which we cannot control.
+       */
     } else if (
-      attr->can_disable && ( attr->can_clear || attr->cleared_by_acknowledge )
+      attr->can_raise && attr->can_disable &&
+      ( attr->can_clear || attr->cleared_by_acknowledge )
     ) {
       rtems_interrupt_entry entry;
       rtems_interrupt_level level;
@@ -302,19 +308,21 @@ test-support: |
       T_rsc_success( sc );
 
       if ( !IsPending( ctx) && ( attr->can_enable || IsEnabled( ctx ) ) ) {
-        if ( attr->can_disable ) {
-          Disable( ctx );
-          Raise( ctx );
-          T_true( IsPending( ctx ) );
-
-          sc = rtems_interrupt_vector_enable( ctx->vector );
-          T_rsc_success( sc );
-
-          while ( ctx->interrupt_count < 1 ) {
-            /* Wait */
-          }
-        } else {
-          ++ctx->interrupt_count;
+        Disable( ctx );
+        Raise( ctx );
+
+        /*
+         * Some interrupt controllers will signal a pending interrupt if it is
+         * disabled (for example ARM GIC), others will not signal a pending
+         * interrupt if it is disabled (for example Freescale/NXP MPIC).
+         */
+        (void) IsPending( ctx );
+
+        sc = rtems_interrupt_vector_enable( ctx->vector );
+        T_rsc_success( sc );
+
+        while ( ctx->interrupt_count < 1 ) {
+          /* Wait */
         }
 
         rtems_interrupt_local_disable( level );
diff --git a/spec/rtems/intr/req/raise-on.yml b/spec/rtems/intr/req/raise-on.yml
index 795d5e0..6ce9946 100644
--- a/spec/rtems/intr/req/raise-on.yml
+++ b/spec/rtems/intr/req/raise-on.yml
@@ -343,21 +343,21 @@ test-support: |
       T_rsc_success( sc );
 
       if ( !IsPending( ctx) && ( attr->can_enable || IsEnabled( ctx ) ) ) {
-        T_false( IsPending( ctx ) );
+        Disable( ctx );
+        RaiseOn( ctx );
 
-        if ( attr->can_disable ) {
-          Disable( ctx );
-          RaiseOn( ctx );
-          T_true( IsPending( ctx ) );
+        /*
+         * Some interrupt controllers will signal a pending interrupt if it is
+         * disabled (for example ARM GIC), others will not signal a pending
+         * interrupt if it is disabled (for example Freescale/NXP MPIC).
+         */
+        (void) IsPending( ctx );
 
-          sc = rtems_interrupt_vector_enable( ctx->vector );
-          T_rsc_success( sc );
+        sc = rtems_interrupt_vector_enable( ctx->vector );
+        T_rsc_success( sc );
 
-          while ( ctx->interrupt_count < 1 ) {
-            /* Wait */
-          }
-        } else {
-          ++ctx->interrupt_count;
+        while ( ctx->interrupt_count < 1 ) {
+          /* Wait */
         }
 
         T_false( IsPending( ctx ) );
diff --git a/spec/rtems/intr/req/raise.yml b/spec/rtems/intr/req/raise.yml
index 871a414..3515b40 100644
--- a/spec/rtems/intr/req/raise.yml
+++ b/spec/rtems/intr/req/raise.yml
@@ -282,21 +282,21 @@ test-support: |
       T_rsc_success( sc );
 
       if ( !IsPending( ctx) && ( attr->can_enable || IsEnabled( ctx ) ) ) {
-        T_false( IsPending( ctx ) );
+        Disable( ctx );
+        Raise( ctx );
 
-        if ( attr->can_disable ) {
-          Disable( ctx );
-          Raise( ctx );
-          T_true( IsPending( ctx ) );
+        /*
+         * Some interrupt controllers will signal a pending interrupt if it is
+         * disabled (for example ARM GIC), others will not signal a pending
+         * interrupt if it is disabled (for example Freescale/NXP MPIC).
+         */
+        (void) IsPending( ctx );
 
-          sc = rtems_interrupt_vector_enable( ctx->vector );
-          T_rsc_success( sc );
+        sc = rtems_interrupt_vector_enable( ctx->vector );
+        T_rsc_success( sc );
 
-          while ( ctx->interrupt_count < 1 ) {
-            /* Wait */
-          }
-        } else {
-          ++ctx->interrupt_count;
+        while ( ctx->interrupt_count < 1 ) {
+          /* Wait */
         }
 
         T_false( IsPending( ctx ) );