[rtems commit] riscv: Simplify _CPU_ISR_Set_level()
Sebastian Huber
sebh at rtems.org
Wed Nov 9 15:55:46 UTC 2022
Module: rtems
Branch: master
Commit: 4a46161b3f893599802486f44fcd0f3fecabcd76
Changeset: http://git.rtems.org/rtems/commit/?id=4a46161b3f893599802486f44fcd0f3fecabcd76
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Tue Nov 8 14:23:07 2022 +0100
riscv: Simplify _CPU_ISR_Set_level()
Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported interrupt
level allowed to set is 0 (interrupts enabled). This constraint is enforced by
the API level functions which return an error status for other interrupt
levels.
---
cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 28 +++++++++++-------------
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index 88f7e7960c..f74ce99684 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -193,21 +193,19 @@ static inline bool _CPU_ISR_Is_enabled( unsigned long level )
static inline void _CPU_ISR_Set_level( uint32_t level )
{
- if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) {
- __asm__ volatile (
- ".option push\n"
- ".option arch, +zicsr\n"
- "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
- ".option pop"
- );
- } else {
- __asm__ volatile (
- ".option push\n"
- ".option arch, +zicsr\n"
- "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
- ".option pop"
- );
- }
+ /*
+ * Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported
+ * interrupt level allowed to set is 0 (interrupts enabled). This constraint
+ * is enforced by the API level functions which return an error status for
+ * other interrupt levels.
+ */
+ (void) level;
+ __asm__ volatile (
+ ".option push\n"
+ ".option arch, +zicsr\n"
+ "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
+ ".option pop"
+ );
}
uint32_t _CPU_ISR_Get_level( void );
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